From 30907d7772613abd5c01b8bc04bc15d3f06111a5 Mon Sep 17 00:00:00 2001 From: Bogdan Marinescu Date: Mon, 23 Sep 2013 10:09:33 +0100 Subject: [PATCH] Refactor LPC1114 and LPC11C24 code Since most of the code for LPC1114 and LPC11C24 is similar, refactor the code structure to avoid duplication of the common code. --- .../cmsis/TARGET_NXP/TARGET_LPC11XX/LPC11xx.h | 602 ------------------ .../TOOLCHAIN_ARM_MICRO/LPC1114.sct | 16 - .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 - .../TOOLCHAIN_ARM_STD/LPC1114.sct | 14 - .../TARGET_LPC11XX/TOOLCHAIN_ARM_STD/sys.cpp | 31 - .../TOOLCHAIN_GCC_ARM/startup_LPC11xx.s | 213 ------- .../TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp | 161 ----- .../TOOLCHAIN_GCC_CS/startup_LPC11xx.s | 112 ---- .../TARGET_LPC11XX/TOOLCHAIN_GCC_CS/sys.cpp | 79 --- .../cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis.h | 13 - .../TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.c | 57 -- .../TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.h | 26 - .../TARGET_LPC11XX/system_LPC11xx.h | 64 -- .../LPC11xx.h | 0 .../TARGET_LPC11CXX/system_LPC11xx.c | 0 .../TARGET_LPC11XX/system_LPC11xx.c | 0 .../TARGET_LPC11CXX}/startup_LPC11xx.s | 0 .../TARGET_LPC11XX}/LPC1114.sct | 0 .../TARGET_LPC11XX}/startup_LPC11xx.s | 0 .../TOOLCHAIN_ARM_MICRO/sys.cpp | 0 .../TARGET_LPC11CXX}/startup_LPC11xx.s | 0 .../TARGET_LPC11XX}/LPC1114.sct | 0 .../TARGET_LPC11XX}/startup_LPC11xx.s | 0 .../TOOLCHAIN_ARM_STD/sys.cpp | 0 .../TARGET_LPC11CXX/LPC11C24.ld} | 0 .../TARGET_LPC11XX}/LPC1114.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_LPC11xx.s | 0 .../TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp | 0 .../TOOLCHAIN_GCC_CS/startup_LPC11xx.s | 0 .../TOOLCHAIN_GCC_CS/sys.cpp | 0 .../cmsis.h | 0 .../cmsis_nvic.c | 0 .../cmsis_nvic.h | 0 .../system_LPC11xx.h | 0 .../hal/TARGET_NXP/TARGET_LPC11CXX/gpio_api.c | 62 -- .../TARGET_NXP/TARGET_LPC11CXX/gpio_irq_api.c | 166 ----- .../hal/TARGET_NXP/TARGET_LPC11CXX/i2c_api.c | 387 ----------- .../hal/TARGET_NXP/TARGET_LPC11CXX/spi_api.c | 214 ------- .../hal/TARGET_NXP/TARGET_LPC11XX/PortNames.h | 33 - .../TARGET_NXP/TARGET_LPC11XX/analogin_api.c | 123 ---- .../TARGET_NXP/TARGET_LPC11XX/gpio_object.h | 46 -- .../hal/TARGET_NXP/TARGET_LPC11XX/pinmap.c | 47 -- .../hal/TARGET_NXP/TARGET_LPC11XX/port_api.c | 78 --- .../TARGET_NXP/TARGET_LPC11XX/serial_api.c | 278 -------- .../hal/TARGET_NXP/TARGET_LPC11XX/sleep.c | 75 --- .../hal/TARGET_NXP/TARGET_LPC11XX/us_ticker.c | 62 -- .../PortNames.h | 0 .../TARGET_LPC11CXX/PeripheralNames.h | 0 .../TARGET_LPC11CXX/PinNames.h | 0 .../TARGET_LPC11CXX/README.md | 0 .../TARGET_LPC11CXX/adc_pinmap.h | 20 + .../TARGET_LPC11CXX/device.h | 0 .../TARGET_LPC11CXX/objects.h | 0 .../TARGET_LPC11CXX/pwmout_api.c | 0 .../TARGET_LPC11CXX/reserved_pins.h | 8 + .../TARGET_LPC11CXX/spi_pinmap.h | 34 + .../TARGET_LPC11XX/PeripheralNames.h | 0 .../TARGET_LPC11XX/PinNames.h | 0 .../TARGET_LPC11XX/README.md | 0 .../TARGET_LPC11XX/adc_pinmap.h | 20 + .../TARGET_LPC11XX/device.h | 0 .../TARGET_LPC11XX/objects.h | 0 .../TARGET_LPC11XX/pwmout_api.c | 0 .../TARGET_LPC11XX/reserved_pins.h | 8 + .../TARGET_LPC11XX/spi_pinmap.h | 33 + .../analogin_api.c | 15 +- .../gpio_api.c | 19 +- .../gpio_irq_api.c | 0 .../gpio_object.h | 0 .../i2c_api.c | 0 .../pinmap.c | 0 .../port_api.c | 0 .../serial_api.c | 0 .../sleep.c | 0 .../spi_api.c | 25 +- .../us_ticker.c | 0 workspace_tools/targets.py | 4 +- 77 files changed, 141 insertions(+), 3035 deletions(-) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/LPC11xx.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/LPC1114.sct delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/sys.cpp delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/LPC1114.sct delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/sys.cpp delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CS/sys.cpp delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/system_LPC11xx.h rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/LPC11xx.h (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11CXX/system_LPC11xx.c (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11XX/system_LPC11xx.c (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO => TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX}/startup_LPC11xx.s (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO => TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX}/LPC1114.sct (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO => TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX}/startup_LPC11xx.s (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/TOOLCHAIN_ARM_MICRO/sys.cpp (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX/TOOLCHAIN_ARM_STD => TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX}/startup_LPC11xx.s (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX/TOOLCHAIN_ARM_STD => TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX}/LPC1114.sct (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11XX/TOOLCHAIN_ARM_STD => TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX}/startup_LPC11xx.s (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/TOOLCHAIN_ARM_STD/sys.cpp (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX/TOOLCHAIN_GCC_ARM/LPC1114.ld => TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld} (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11XX/TOOLCHAIN_GCC_ARM => TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX}/LPC1114.ld (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/TOOLCHAIN_GCC_CS/startup_LPC11xx.s (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/TOOLCHAIN_GCC_CS/sys.cpp (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/cmsis.h (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/cmsis_nvic.c (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/cmsis_nvic.h (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/system_LPC11xx.h (100%) delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_irq_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/i2c_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/spi_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/PortNames.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/analogin_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_object.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/pinmap.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/port_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/serial_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/sleep.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/us_ticker.c rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11CXX/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11CXX/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11CXX/README.md (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/adc_pinmap.h rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11CXX/device.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11CXX/objects.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11CXX/pwmout_api.c (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/reserved_pins.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/spi_pinmap.h rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11XX/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11XX/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11XX/README.md (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/adc_pinmap.h rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11XX/device.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11XX/objects.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC11XX_11CXX}/TARGET_LPC11XX/pwmout_api.c (100%) create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/reserved_pins.h create mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/spi_pinmap.h rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/analogin_api.c (92%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11XX => TARGET_LPC11XX_11CXX}/gpio_api.c (86%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11XX => TARGET_LPC11XX_11CXX}/gpio_irq_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/gpio_object.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11XX => TARGET_LPC11XX_11CXX}/i2c_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/pinmap.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/port_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/serial_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/sleep.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11XX => TARGET_LPC11XX_11CXX}/spi_api.c (91%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC11CXX => TARGET_LPC11XX_11CXX}/us_ticker.c (100%) diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/LPC11xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/LPC11xx.h deleted file mode 100644 index 3465e38f6eb..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/LPC11xx.h +++ /dev/null @@ -1,602 +0,0 @@ -/**************************************************************************** - * $Id:: LPC11xx.h 9198 2012-05-29 usb00175 $ - * Project: NXP LPC11xx software example - * - * Description: - * CMSIS Cortex-M0 Core Peripheral Access Layer Header File for - * NXP LPC11xx Device Series - - **************************************************************************** - * Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. - -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. - -****************************************************************************/ -#ifndef __LPC11xx_H__ -#define __LPC11xx_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup LPC11xx_Definitions LPC11xx Definitions - This file defines all structures and symbols for LPC11xx: - - Registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions - @{ -*/ - - -/******************************************************************************/ -/* Processor and Core Peripherals */ -/******************************************************************************/ -/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions - Configuration of the Cortex-M0 Processor and Core Peripherals - @{ -*/ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/ - WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ - WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */ - WAKEUP2_IRQn = 2, - WAKEUP3_IRQn = 3, - WAKEUP4_IRQn = 4, - WAKEUP5_IRQn = 5, - WAKEUP6_IRQn = 6, - WAKEUP7_IRQn = 7, - WAKEUP8_IRQn = 8, - WAKEUP9_IRQn = 9, - WAKEUP10_IRQn = 10, - WAKEUP11_IRQn = 11, - WAKEUP12_IRQn = 12, - CAN_IRQn = 13, /*!< CAN Interrupt */ - SSP1_IRQn = 14, /*!< SSP1 Interrupt */ - I2C_IRQn = 15, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ - SSP0_IRQn = 20, /*!< SSP0 Interrupt */ - UART_IRQn = 21, /*!< UART Interrupt */ - Reserved0_IRQn = 22, /*!< Reserved Interrupt */ - Reserved1_IRQn = 23, - ADC_IRQn = 24, /*!< A/D Converter Interrupt */ - WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ - FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ - EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */ - EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */ - EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */ - EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */ -} IRQn_Type; - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M0 Processor and Core Peripherals */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*@}*/ /* end of group LPC11xx_CMSIS */ - - -#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ -#include "system_LPC11xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SYSCON) --------------------------------------*/ -/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block - @{ -*/ -typedef struct -{ - __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ - __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ - __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ - __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */ - uint32_t RESERVED0[4]; - - __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ - __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ - __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */ - uint32_t RESERVED1[1]; - __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ - __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ - uint32_t RESERVED3[10]; - - __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ - __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ - __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ - uint32_t RESERVED4[1]; - - __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ - uint32_t RESERVED5[4]; - __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */ - __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */ - __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */ - uint32_t RESERVED6[12]; - - __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */ - __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */ - __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */ - uint32_t RESERVED8[1]; - __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ - __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ - __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ - uint32_t RESERVED9[5]; - - __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ - __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */ - uint32_t RESERVED10[18]; - __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ - __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */ - - uint32_t RESERVED13[7]; - __IO uint32_t NMISRC; /*!< Offset: 0x174 NMI source selection register (R/W) */ - uint32_t RESERVED14[34]; - - __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */ - __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ - __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */ - __I uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/) */ - __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */ - __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */ - __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */ - __IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */ - uint32_t RESERVED17[4]; - - __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ - __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ - __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ - uint32_t RESERVED15[110]; - __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ -} LPC_SYSCON_TypeDef; -/*@}*/ /* end of group LPC11xx_SYSCON */ - - -/*------------- Pin Connect Block (IOCON) --------------------------------*/ -/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block - @{ -*/ -typedef struct -{ - __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */ - uint32_t RESERVED0[1]; - __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */ - __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */ - __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */ - __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */ - __IO uint32_t SSEL1_LOC; /*!< Offset: 0x018 IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) */ - __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */ - - __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */ - __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */ - __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */ - __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */ - __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */ - __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */ - __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */ - __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */ - - __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */ - __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */ - __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */ - __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */ - __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */ - __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */ - __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */ - __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */ - - __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */ - __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */ - __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */ - __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */ - __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */ - __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */ - __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */ - __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */ - - __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */ - __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */ - __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */ - __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */ - __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */ - __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */ - __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */ - __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */ - - __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */ - __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */ - __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */ - __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */ - __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */ - __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */ - __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */ - __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */ - - __IO uint32_t CT16B0_CAP0_LOC; /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */ - __IO uint32_t SCK1_LOC; /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */ - __IO uint32_t MISO1_LOC; /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */ - __IO uint32_t MOSI1_LOC; /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */ - __IO uint32_t CT32B0_CAP0_LOC; /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */ - __IO uint32_t RXD_LOC; /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */ -} LPC_IOCON_TypeDef; -/*@}*/ /* end of group LPC11xx_IOCON */ - - -/*------------- Power Management Unit (PMU) --------------------------*/ -/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit - @{ -*/ -typedef struct -{ - __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ - __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ - __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ - __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ - __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ - __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */ -} LPC_PMU_TypeDef; -/*@}*/ /* end of group LPC11xx_PMU */ - - - -// ------------------------------------------------------------------------------------------------ -// ----- FLASHCTRL ----- -// ------------------------------------------------------------------------------------------------ - -typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */ - __I uint32_t RESERVED2[1]; - __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */ - __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */ - __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */ - __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */ - __I uint32_t RESERVED3[1001]; - __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */ - __I uint32_t RESERVED4[1]; - __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */ -} LPC_FLASHCTRL_Type; - - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output - @{ -*/ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */ - struct { - uint32_t RESERVED0[4095]; - __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */ - }; - }; - uint32_t RESERVED1[4096]; - __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */ - __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */ - __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */ - __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */ - __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */ - __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */ - __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */ - __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (/W) */ -} LPC_GPIO_TypeDef; -/*@}*/ /* end of group LPC11xx_GPIO */ - -/*------------- Timer (TMR) --------------------------------------------------*/ -/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer - @{ -*/ -typedef struct -{ - __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ - __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ - __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ - __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ - union { - __IO uint32_t MR[4]; /*!< Offset: Match Register base */ - struct{ - __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ - __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ - __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ - __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ - }; - }; - __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ - __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ - __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ - uint32_t RESERVED1[2]; - __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ - uint32_t RESERVED2[12]; - __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ - __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */ -} LPC_TMR_TypeDef; -/*@}*/ /* end of group LPC11xx_TMR */ - - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter - @{ -*/ -typedef struct -{ - union { - __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ - __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ - __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ - }; - union { - __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ - __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ - }; - union { - __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ - __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ - }; - __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ - __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ - __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ - __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ - __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ - __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ - uint32_t RESERVED1; - __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ - uint32_t RESERVED2[6]; - __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ - __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ - __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ - __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R) */ -} LPC_UART_TypeDef; -/*@}*/ /* end of group LPC11xx_UART */ - - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port - @{ -*/ -typedef struct -{ - __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ - __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ - __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ - __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ - __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ - __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ - __I uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/) */ - __I uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/) */ - __O uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (/W) */ -} LPC_SSP_TypeDef; -/*@}*/ /* end of group LPC11xx_SSP */ - - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface - @{ -*/ -typedef struct -{ - __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ - __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ - __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ - __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ - __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ - __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ - __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ - __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ - __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ - __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ - __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ - __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ - __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ - __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ - __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ -} LPC_I2C_TypeDef; -/*@}*/ /* end of group LPC11xx_I2C */ - - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer - @{ -*/ -typedef struct -{ - __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ - __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */ - __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */ - uint32_t RESERVED0; - __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ - __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ -} LPC_WDT_TypeDef; -/*@}*/ /* end of group LPC11xx_WDT */ - - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter - @{ -*/ -typedef struct -{ - __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ - __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ - uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ - __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ - __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ -} LPC_ADC_TypeDef; -/*@}*/ /* end of group LPC11xx_ADC */ - - -/*------------- CAN Controller (CAN) ----------------------------*/ -/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN) - @{ -*/ -typedef struct -{ - __IO uint32_t CNTL; /* 0x000 */ - __IO uint32_t STAT; - __IO uint32_t EC; - __IO uint32_t BT; - __IO uint32_t INT; - __IO uint32_t TEST; - __IO uint32_t BRPE; - uint32_t RESERVED0; - __IO uint32_t IF1_CMDREQ; /* 0x020 */ - __IO uint32_t IF1_CMDMSK; - __IO uint32_t IF1_MSK1; - __IO uint32_t IF1_MSK2; - __IO uint32_t IF1_ARB1; - __IO uint32_t IF1_ARB2; - __IO uint32_t IF1_MCTRL; - __IO uint32_t IF1_DA1; - __IO uint32_t IF1_DA2; - __IO uint32_t IF1_DB1; - __IO uint32_t IF1_DB2; - uint32_t RESERVED1[13]; - __IO uint32_t IF2_CMDREQ; /* 0x080 */ - __IO uint32_t IF2_CMDMSK; - __IO uint32_t IF2_MSK1; - __IO uint32_t IF2_MSK2; - __IO uint32_t IF2_ARB1; - __IO uint32_t IF2_ARB2; - __IO uint32_t IF2_MCTRL; - __IO uint32_t IF2_DA1; - __IO uint32_t IF2_DA2; - __IO uint32_t IF2_DB1; - __IO uint32_t IF2_DB2; - uint32_t RESERVED2[21]; - __I uint32_t TXREQ1; /* 0x100 */ - __I uint32_t TXREQ2; - uint32_t RESERVED3[6]; - __I uint32_t ND1; /* 0x120 */ - __I uint32_t ND2; - uint32_t RESERVED4[6]; - __I uint32_t IR1; /* 0x140 */ - __I uint32_t IR2; - uint32_t RESERVED5[6]; - __I uint32_t MSGV1; /* 0x160 */ - __I uint32_t MSGV2; - uint32_t RESERVED6[6]; - __IO uint32_t CLKDIV; /* 0x180 */ -} LPC_CAN_TypeDef; -/*@}*/ /* end of group LPC11xx_CAN */ - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000) - -/* AHB peripherals */ -#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) -#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) -#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) -#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) -#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC11xx_H__ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/LPC1114.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/LPC1114.sct deleted file mode 100644 index 44850e6a947..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/LPC1114.sct +++ /dev/null @@ -1,16 +0,0 @@ - -LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k) - - ER_IROM1 0x00000000 0x8000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; 48 vectors * 4 bytes = 0xC0 for remap - RW_IRAM1 (0x10000000+0xC0) (0x1000-0xC0) { - .ANY (+RW +ZI) - } - -} - diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/sys.cpp deleted file mode 100644 index 2f1024ace8b..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/sys.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/LPC1114.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/LPC1114.sct deleted file mode 100644 index 0a7772d0c31..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/LPC1114.sct +++ /dev/null @@ -1,14 +0,0 @@ - -LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k) - ER_IROM1 0x00000000 0x8000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0xF40 - RW_IRAM1 0x100000C0 0xF40 { - .ANY (+RW +ZI) - } -} - diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/sys.cpp deleted file mode 100644 index 2f1024ace8b..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/sys.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s deleted file mode 100644 index 3ffdd07e58a..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s +++ /dev/null @@ -1,213 +0,0 @@ -/* File: startup_ARMCM0.S - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv6-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x80 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x80 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - -/* LPC11xx interrupts */ - .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */ - .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */ - .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */ - .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */ - .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */ - .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */ - .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */ - .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */ - .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */ - .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */ - .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */ - .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */ - .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */ - .long Default_Handler /* 29 13 */ - .long SSP1_IRQHandler /* 30 14 SSP1 */ - .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */ - .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */ - .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */ - .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */ - .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */ - .long SSP0_IRQHandler /* 36 20 SSP */ - .long UART_IRQHandler /* 37 21 UART */ - .long Default_Handler /* 38 22 */ - .long Default_Handler /* 39 23 */ - .long ADC_IRQHandler /* 40 24 ADC end of conversion */ - .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */ - .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */ - .long Default_Handler /* 43 27 */ - .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */ - .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */ - .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */ - .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */ - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .flash_to_ram_loop_end - - movs r4, 0 -.flash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .flash_to_ram_loop -.flash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - def_default_handler WAKEUP_IRQHandler - def_default_handler SSP1_IRQHandler - def_default_handler I2C_IRQHandler - def_default_handler TIMER16_0_IRQHandler - def_default_handler TIMER16_1_IRQHandler - def_default_handler TIMER32_0_IRQHandler - def_default_handler TIMER32_1_IRQHandler - def_default_handler SSP0_IRQHandler - def_default_handler UART_IRQHandler - def_default_handler ADC_IRQHandler - def_default_handler WDT_IRQHandler - def_default_handler BOD_IRQHandler - def_default_handler PIOINT3_IRQHandler - def_default_handler PIOINT2_IRQHandler - def_default_handler PIOINT1_IRQHandler - def_default_handler PIOINT0_IRQHandler - - .weak DEF_IRQHandler - .set DEF_IRQHandler, Default_Handler - - .end - diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp deleted file mode 100644 index ffcb738df4f..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp +++ /dev/null @@ -1,161 +0,0 @@ -extern "C" { - -#include "LPC11Uxx.h" - -#define WEAK __attribute__ ((weak)) -#define ALIAS(f) __attribute__ ((weak, alias (#f))) -#define AFTER_VECTORS __attribute__ ((section(".after_vectors"))) - - void ResetISR (void); -WEAK void NMI_Handler (void); -WEAK void HardFault_Handler (void); -WEAK void SVCall_Handler (void); -WEAK void PendSV_Handler (void); -WEAK void SysTick_Handler (void); -WEAK void IntDefaultHandler (void); - void FLEX_INT0_IRQHandler(void) ALIAS(IntDefaultHandler); - void FLEX_INT1_IRQHandler(void) ALIAS(IntDefaultHandler); - void FLEX_INT2_IRQHandler(void) ALIAS(IntDefaultHandler); - void FLEX_INT3_IRQHandler(void) ALIAS(IntDefaultHandler); - void FLEX_INT4_IRQHandler(void) ALIAS(IntDefaultHandler); - void FLEX_INT5_IRQHandler(void) ALIAS(IntDefaultHandler); - void FLEX_INT6_IRQHandler(void) ALIAS(IntDefaultHandler); - void FLEX_INT7_IRQHandler(void) ALIAS(IntDefaultHandler); - void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler); - void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler); - void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler); - void I2C_IRQHandler (void) ALIAS(IntDefaultHandler); - void TIMER16_0_IRQHandler(void) ALIAS(IntDefaultHandler); - void TIMER16_1_IRQHandler(void) ALIAS(IntDefaultHandler); - void TIMER32_0_IRQHandler(void) ALIAS(IntDefaultHandler); - void TIMER32_1_IRQHandler(void) ALIAS(IntDefaultHandler); - void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler); - void UART_IRQHandler (void) ALIAS(IntDefaultHandler); - void USB_IRQHandler (void) ALIAS(IntDefaultHandler); - void USB_FIQHandler (void) ALIAS(IntDefaultHandler); - void ADC_IRQHandler (void) ALIAS(IntDefaultHandler); - void WDT_IRQHandler (void) ALIAS(IntDefaultHandler); - void BOD_IRQHandler (void) ALIAS(IntDefaultHandler); - void FMC_IRQHandler (void) ALIAS(IntDefaultHandler); - void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler); - -extern void __libc_init_array(void); -extern int main(void); -extern void _vStackTop(void); - -extern void (* const g_pfnVectors[])(void); -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = { - &_vStackTop, - ResetISR, - NMI_Handler, - HardFault_Handler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - SVCall_Handler, - 0, - 0, - PendSV_Handler, - SysTick_Handler, - FLEX_INT0_IRQHandler, - FLEX_INT1_IRQHandler, - FLEX_INT2_IRQHandler, - FLEX_INT3_IRQHandler, - FLEX_INT4_IRQHandler, - FLEX_INT5_IRQHandler, - FLEX_INT6_IRQHandler, - FLEX_INT7_IRQHandler, - GINT0_IRQHandler, - GINT1_IRQHandler, - 0, - 0, - 0, - 0, - SSP1_IRQHandler, - I2C_IRQHandler, - TIMER16_0_IRQHandler, - TIMER16_1_IRQHandler, - TIMER32_0_IRQHandler, - TIMER32_1_IRQHandler, - SSP0_IRQHandler, - UART_IRQHandler, - USB_IRQHandler, - USB_FIQHandler, - ADC_IRQHandler, - WDT_IRQHandler, - BOD_IRQHandler, - FMC_IRQHandler, - 0, - 0, - USBWakeup_IRQHandler, - 0, -}; - -AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int *pulSrc = (unsigned int*) romstart; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++; -} - -AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0; -} - -extern unsigned int __data_section_table; -extern unsigned int __data_section_table_end; -extern unsigned int __bss_section_table_end; - -AFTER_VECTORS void ResetISR(void) { - unsigned int LoadAddr, ExeAddr, SectionLen; - unsigned int *SectionTableAddr; - - // Data Init - SectionTableAddr = &__data_section_table; - while (SectionTableAddr < &__data_section_table_end) { - LoadAddr = *SectionTableAddr++; - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - data_init(LoadAddr, ExeAddr, SectionLen); - } - - // BSS Init - while (SectionTableAddr < &__bss_section_table_end) { - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - bss_init(ExeAddr, SectionLen); - } - - SystemInit(); - __libc_init_array(); - main(); - while (1) {;} -} - -AFTER_VECTORS void NMI_Handler (void) {while(1){}} -AFTER_VECTORS void HardFault_Handler(void) {while(1){}} -AFTER_VECTORS void SVCall_Handler (void) {while(1){}} -AFTER_VECTORS void PendSV_Handler (void) {while(1){}} -AFTER_VECTORS void SysTick_Handler (void) {while(1){}} -AFTER_VECTORS void IntDefaultHandler(void) {while(1){}} - -#include - -void *operator new (size_t size) {return malloc(size);} -void *operator new[](size_t size) {return malloc(size);} - -void operator delete (void *p) {free(p);} -void operator delete[](void *p) {free(p);} - -int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) { - return 0; -} - -} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s deleted file mode 100644 index cc8ab7bc242..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s +++ /dev/null @@ -1,112 +0,0 @@ - .equ Stack_Size, 0x80 - .section ".stack", "w" - .align 3 - .globl __cs3_stack_mem - .globl __cs3_stack_size -__cs3_stack_mem: - .if Stack_Size - .space Stack_Size - .endif - .size __cs3_stack_mem, . - __cs3_stack_mem - .set __cs3_stack_size, . - __cs3_stack_mem - - .equ Heap_Size, 0x80 - .section ".heap", "w" - .align 3 - .globl __cs3_heap_start - .globl __cs3_heap_end -__cs3_heap_start: - .if Heap_Size - .space Heap_Size - .endif -__cs3_heap_end: - - .section ".cs3.interrupt_vector" - .globl __cs3_interrupt_vector_cortex_m - .type __cs3_interrupt_vector_cortex_m, %object - -__cs3_interrupt_vector_cortex_m: - .long __cs3_stack - .long __cs3_reset - .long NMI_Handler - .long HardFault_Handler - .long 0 - .long 0 - .long 0 - .long 0 - .long 0 - .long 0 - .long 0 - .long SVC_Handler - .long 0 - .long 0 - .long PendSV_Handler - .long SysTick_Handler - - .long DEF_IRQHandler - - .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m - - .thumb - - .section .cs3.reset,"x",%progbits - .thumb_func - .globl __cs3_reset_cortex_m - .type __cs3_reset_cortex_m, %function -__cs3_reset_cortex_m: - .fnstart - LDR R0, =SystemInit - BLX R0 - LDR R0,=__cs3_start_c - BX R0 - .pool - .cantunwind - .fnend - .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m - - .section ".text" - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ DEF_IRQHandler - - .end diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CS/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CS/sys.cpp deleted file mode 100644 index 6fc5736daf9..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_CS/sys.cpp +++ /dev/null @@ -1,79 +0,0 @@ -#include "cmsis.h" -#include -#include - -extern "C" { - -struct SCS3Regions { - unsigned long Dummy; - unsigned long* InitRam; - unsigned long* StartRam; - unsigned long InitSizeRam; - unsigned long ZeroSizeRam; -}; - -extern unsigned long __cs3_regions; -extern unsigned long __cs3_heap_start; - -int main(void); -void __libc_init_array(void); -void exit(int ErrorCode); - -static void *heap_pointer = NULL; - -void __cs3_start_c(void) { - static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions; - unsigned long* pulDest; - unsigned long* pulSrc; - unsigned long ByteCount; - unsigned long i; - - pulSrc = pCS3Regions->InitRam; - pulDest = pCS3Regions->StartRam; - ByteCount = pCS3Regions->InitSizeRam; - if (pulSrc != pulDest) { - for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) { - *(pulDest++) = *(pulSrc++); - } - } else { - pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount); - } - - ByteCount = pCS3Regions->ZeroSizeRam; - for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) { - *(pulDest++) = 0; - } - - heap_pointer = &__cs3_heap_start; - __libc_init_array(); - exit(main()); -} - -int _kill(int pid, int sig) { - errno = EINVAL; - return -1; -} - -void _exit(int status) { - exit(status); -} - -int _getpid(void) { - return 1; -} - -void *_sbrk(unsigned int incr) { - void *mem; - - unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7); - if (next > __get_MSP()) { - mem = NULL; - } else { - mem = (void *)heap_pointer; - } - heap_pointer = (void *)next; - - return mem; -} - -} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis.h deleted file mode 100644 index 6e00f1e26bb..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC11xx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.c deleted file mode 100644 index f1028cbe576..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.c +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for LPC11U24 - * Copyright (c) 2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#include "cmsis_nvic.h" - -/* In the M0, there is no VTOR. In the LPC range such as the LPC11U, - * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0), - * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF - * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0 - * - * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH - * above the vector table before 0x200 will actually go to RAM. So we need to provide - * a solution where the compiler gets the right results based on the memory map - * - * Option 1 - We allocate and copy 0x200 of RAM rather than just the table - * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM - * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0 - * - * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there - * - No flash accesses will go to ram, as there will be nothing there - * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal - * - RAM overhead: 0, FLASH overhead: 320 bytes - * - * Option 2 is the one to go for, as RAM is the most valuable resource - */ - -#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - int i; - // Space for dynamic vectors, initialised to allocate in R/W - static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - - // Copy and switch to dynamic vectors if first time called - if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) { - uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0 - for(i = 0; i < NVIC_NUM_VECTORS; i++) { - vectors[i] = old_vectors[i]; - } - LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block - } - - // Set the vector - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - // We can always read vectors at 0x0, as the addresses are remapped - uint32_t *vectors = (uint32_t*)0; - - // Return the vector - return vectors[IRQn + 16]; -} - diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.h deleted file mode 100644 index 4e0ddede091..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.h +++ /dev/null @@ -1,26 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/system_LPC11xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/system_LPC11xx.h deleted file mode 100644 index fa57304d488..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/system_LPC11xx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_LPC11xx.h - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File - * for the NXP LPC11xx/LPC11Cxx Device Series - * @version V1.10 - * @date 24. November 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC11xx_H -#define __SYSTEM_LPC11xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC11xx_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/LPC11xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/LPC11xx.h rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/system_LPC11xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/system_LPC11xx.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/system_LPC11xx.c rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/system_LPC11xx.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/system_LPC11xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/system_LPC11xx.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/system_LPC11xx.c rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/system_LPC11xx.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/startup_LPC11xx.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/startup_LPC11xx.s diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO/LPC1114.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/LPC1114.sct similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO/LPC1114.sct rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/LPC1114.sct diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/startup_LPC11xx.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/startup_LPC11xx.s diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/sys.cpp similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_MICRO/sys.cpp rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_STD/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/startup_LPC11xx.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_STD/startup_LPC11xx.s rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/startup_LPC11xx.s diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_STD/LPC1114.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/LPC1114.sct similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_STD/LPC1114.sct rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/LPC1114.sct diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/startup_LPC11xx.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_STD/startup_LPC11xx.s rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/startup_LPC11xx.s diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/sys.cpp similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_ARM_STD/sys.cpp rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_ARM/LPC1114.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_ARM/LPC1114.ld rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_ARM/LPC1114.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_ARM/LPC1114.ld rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_CS/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/sys.cpp similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/TOOLCHAIN_GCC_CS/sys.cpp rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/system_LPC11xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/system_LPC11xx.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/system_LPC11xx.h rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/system_LPC11xx.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_api.c deleted file mode 100644 index 8566e7ae83f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_api.c +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" - -uint32_t gpio_set(PinName pin) { - // PIO default value of following ports are not same as others - int f = ((pin == P0_0 ) || // RESET - (pin == P0_10) || // SWCLK - (pin == P0_11) || // R - (pin == P1_0 ) || // R - (pin == P1_1 ) || // R - (pin == P1_2 ) || // R - (pin == P1_3 )) ? // - (1) : (0); - - pin_function(pin, f); - return ((pin & 0x0F00) >> PIN_SHIFT); -} - -void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) { - if(pin == NC) return; - - obj->pin = pin; - LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((pin & 0xF000) >> PORT_SHIFT) * 0x10000))); - - obj->reg_mask_read = &port_reg->MASKED_ACCESS[1 << gpio_set(pin)]; - obj->reg_dir = &port_reg->DIR; - obj->reg_write = &port_reg->DATA; - - gpio_dir(obj, direction); - - switch (direction) { - case PIN_OUTPUT: pin_mode(pin, PullNone); break; - case PIN_INPUT : pin_mode(pin, PullDown); break; - } -} - -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - int pin_number = ((obj->pin & 0x0F00) >> 8); - switch (direction) { - case PIN_INPUT : *obj->reg_dir &= ~(1 << pin_number); break; - case PIN_OUTPUT: *obj->reg_dir |= (1 << pin_number); break; - } -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_irq_api.c deleted file mode 100644 index 7049894c03a..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_irq_api.c +++ /dev/null @@ -1,166 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "error.h" -#include "gpio_api.h" - -// The chip is capable of 4 external interrupts. -#define CHANNEL_NUM 4 - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; -static PinName pin_names[CHANNEL_NUM] = {}; -static uint8_t trigger_events[CHANNEL_NUM] = {}; - -static inline void handle_interrupt_in(uint32_t channel) { - // Find out whether the interrupt has been triggered by a high or low value... - // As the LPC1114 doesn't have a specific register for this, we'll just have to read - // the level of the pin as if it were just a normal input... - - // Get the number of the pin being used and the port typedef - LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((pin_names[channel] & 0xF000) >> PORT_SHIFT) * 0x10000))); - uint8_t pin_num = (pin_names[channel] & (0x0f << PIN_SHIFT)) >> PIN_SHIFT; - uint8_t trigger_event = trigger_events[channel]; - - if (trigger_event == 1) - irq_handler(channel_ids[channel], IRQ_RISE); - else if (trigger_event == 2) - irq_handler(channel_ids[channel], IRQ_FALL); - else { - // In order to get an idea of which kind of event it is, - // We need to read the logic level of the pin... - - uint8_t logic = (port_reg->DATA & (1 << pin_num)) >> pin_num; - - if (logic == 1) - irq_handler(channel_ids[channel], IRQ_RISE); - else - irq_handler(channel_ids[channel], IRQ_FALL); - } - - // Clear the interrupt... - port_reg->IC |= 1 << pin_num; -} - -void gpio_irq0(void) {handle_interrupt_in(0);} -void gpio_irq1(void) {handle_interrupt_in(1);} -void gpio_irq2(void) {handle_interrupt_in(2);} -void gpio_irq3(void) {handle_interrupt_in(3);} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) return -1; - - // Firstly, we'll put some data in *obj so we can keep track of stuff. - obj->pin = pin; - - // Set the handler to be the pointer at the top... - irq_handler = handler; - - // Which port are we using? - int channel; - uint32_t port_reg = (LPC_GPIO0_BASE + (((pin & 0xF000) >> PORT_SHIFT) * 0x10000)); - - switch (port_reg) { - case LPC_GPIO0_BASE: - NVIC_SetVector(EINT0_IRQn, (uint32_t)gpio_irq0); - NVIC_EnableIRQ(EINT0_IRQn); - channel = 0; - break; - case LPC_GPIO1_BASE: - NVIC_SetVector(EINT1_IRQn, (uint32_t)gpio_irq1); - NVIC_EnableIRQ(EINT1_IRQn); - channel = 1; - break; - case LPC_GPIO2_BASE: - NVIC_SetVector(EINT2_IRQn, (uint32_t)gpio_irq2); - NVIC_EnableIRQ(EINT2_IRQn); - channel = 2; - break; - case LPC_GPIO3_BASE: - NVIC_SetVector(EINT3_IRQn, (uint32_t)gpio_irq3); - NVIC_EnableIRQ(EINT3_IRQn); - channel = 3; - break; - default: - channel = -1; - error("Invalid interrupt choice."); - break; - } - - channel_ids[channel] = id; - pin_names[channel] = pin; - obj->ch = channel; - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - // Firstly, check if there is an existing event stored... - - LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((obj->pin & 0xF000) >> PORT_SHIFT) * 0x10000))); - - // Need to get the pin number of the pin, not the value of the enum - uint8_t pin_num = (obj->pin & (0x0f << PIN_SHIFT)) >> PIN_SHIFT; - - - if (trigger_events[obj->ch] != 0) { - // We have an event. - // Enable both edge interrupts. - - if (enable) { - trigger_events[obj->ch] = 3; - port_reg->IBE |= 1 << pin_num; - port_reg->IE |= 1 << pin_num; - } - else { - // These all need to be opposite, to reenable the other one. - trigger_events[obj->ch] = event == IRQ_RISE ? 2 : 1; - - port_reg->IBE &= ~(1 << pin_num); - - if (event == IRQ_RISE) - port_reg->IEV &= ~(1 << pin_num); - else - port_reg->IEV |= 1 << pin_num; - - port_reg->IE |= 1 << pin_num; - } - } - else { - if (enable) { - trigger_events[obj->ch] = event == IRQ_RISE ? 1 : 2; - port_reg->IE |= 1 << pin_num; - } - // One edge - port_reg->IBE &= ~(1 << pin_num); - // Rising/falling? - if (event == IRQ_RISE) - port_reg->IEV |= 1 << pin_num; - else - port_reg->IEV &= ~(1 << pin_num); - } - - // Clear - port_reg->IC |= 1 << pin_num; - - // Make it edge sensitive. - port_reg->IS &= ~(1 << pin_num); -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/i2c_api.c deleted file mode 100644 index 6fb7b238501..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/i2c_api.c +++ /dev/null @@ -1,387 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "error.h" - -static const PinMap PinMap_I2C_SDA[] = { - {P0_5, I2C_0, 1}, - {NC , NC , 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {P0_4, I2C_0, 1}, - {NC , NC, 0} -}; - -#define I2C_CONSET(x) (x->i2c->CONSET) -#define I2C_CONCLR(x) (x->i2c->CONCLR) -#define I2C_STAT(x) (x->i2c->STAT) -#define I2C_DAT(x) (x->i2c->DAT) -#define I2C_SCLL(x, val) (x->i2c->SCLL = val) -#define I2C_SCLH(x, val) (x->i2c->SCLH = val) - -static const uint32_t I2C_addr_offset[2][4] = { - {0x0C, 0x20, 0x24, 0x28}, - {0x30, 0x34, 0x38, 0x3C} -}; - -static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { - I2C_CONCLR(obj) = (start << 5) - | (stop << 4) - | (interrupt << 3) - | (acknowledge << 2); -} - -static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { - I2C_CONSET(obj) = (start << 5) - | (stop << 4) - | (interrupt << 3) - | (acknowledge << 2); -} - -// Clear the Serial Interrupt (SI) -static inline void i2c_clear_SI(i2c_t *obj) { - i2c_conclr(obj, 0, 0, 1, 0); -} - -static inline int i2c_status(i2c_t *obj) { - return I2C_STAT(obj); -} - -// Wait until the Serial Interrupt (SI) is set -static int i2c_wait_SI(i2c_t *obj) { - int timeout = 0; - while (!(I2C_CONSET(obj) & (1 << 3))) { - timeout++; - if (timeout > 100000) return -1; - } - return 0; -} - -static inline void i2c_interface_enable(i2c_t *obj) { - I2C_CONSET(obj) = 0x40; -} - -static inline void i2c_power_enable(i2c_t *obj) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5); - LPC_SYSCON->PRESETCTRL |= 1 << 1; -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - // determine the SPI to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); - - if ((int)obj->i2c == NC) { - error("I2C pin mapping failed"); - } - - // enable power - i2c_power_enable(obj); - - // set default frequency at 100k - i2c_frequency(obj, 100000); - i2c_conclr(obj, 1, 1, 1, 1); - i2c_interface_enable(obj); - - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); -} - -inline int i2c_start(i2c_t *obj) { - int status = 0; - // 8.1 Before master mode can be entered, I2CON must be initialised to: - // - I2EN STA STO SI AA - - - // - 1 0 0 0 x - - - // if AA = 0, it can't enter slave mode - i2c_conclr(obj, 1, 1, 1, 1); - - // The master mode may now be entered by setting the STA bit - // this will generate a start condition when the bus becomes free - i2c_conset(obj, 1, 0, 0, 1); - - i2c_wait_SI(obj); - status = i2c_status(obj); - - // Clear start bit now transmitted, and interrupt bit - i2c_conclr(obj, 1, 0, 0, 0); - return status; -} - -inline int i2c_stop(i2c_t *obj) { - int timeout = 0; - - // write the stop bit - i2c_conset(obj, 0, 1, 0, 0); - i2c_clear_SI(obj); - - // wait for STO bit to reset - while(I2C_CONSET(obj) & (1 << 4)) { - timeout ++; - if (timeout > 100000) return 1; - } - - return 0; -} - - -static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { - // write the data - I2C_DAT(obj) = value; - - // clear SI to init a send - i2c_clear_SI(obj); - - // wait and return status - i2c_wait_SI(obj); - return i2c_status(obj); -} - -static inline int i2c_do_read(i2c_t *obj, int last) { - // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack) - if (last) { - i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK - } else { - i2c_conset(obj, 0, 0, 0, 1); // send a ACK - } - - // accept byte - i2c_clear_SI(obj); - - // wait for it to arrive - i2c_wait_SI(obj); - - // return the data - return (I2C_DAT(obj) & 0xFF); -} - -void i2c_frequency(i2c_t *obj, int hz) { - // No peripheral clock divider on the M0 - uint32_t PCLK = SystemCoreClock; - - uint32_t pulse = PCLK / (hz * 2); - - // I2C Rate - I2C_SCLL(obj, pulse); - I2C_SCLH(obj, pulse); -} - -// The I2C does a read or a write as a whole operation -// There are two types of error conditions it can encounter -// 1) it can not obtain the bus -// 2) it gets error responses at part of the transmission -// -// We tackle them as follows: -// 1) we retry until we get the bus. we could have a "timeout" if we can not get it -// which basically turns it in to a 2) -// 2) on error, we use the standard error mechanisms to report/debug -// -// Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically -// check for that - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count, status; - - status = i2c_start(obj); - - if ((status != 0x10) && (status != 0x08)) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - - status = i2c_do_write(obj, (address | 0x01), 1); - if (status != 0x40) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - // Read in all except last byte - for (count = 0; count < (length - 1); count++) { - int value = i2c_do_read(obj, 0); - status = i2c_status(obj); - if (status != 0x50) { - i2c_stop(obj); - return count; - } - data[count] = (char) value; - } - - // read in last byte - int value = i2c_do_read(obj, 1); - status = i2c_status(obj); - if (status != 0x58) { - i2c_stop(obj); - return length - 1; - } - - data[count] = (char) value; - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int i, status; - - status = i2c_start(obj); - - if ((status != 0x10) && (status != 0x08)) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - - status = i2c_do_write(obj, (address & 0xFE), 1); - if (status != 0x18) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - for (i=0; i= 0) && (idx <= 3)) { - addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx]; - *((uint32_t *) addr) = address & 0xFF; - } -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/spi_api.c deleted file mode 100644 index a35895682c1..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/spi_api.c +++ /dev/null @@ -1,214 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "error.h" - -static const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P0_10, SPI_0, 0x02}, - {P2_11, SPI_0, 0x01}, - {P2_1 , SPI_1, 0x02}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P2_3 , SPI_1, 0x02}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P2_2 , SPI_1, 0x02}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P2_0 , SPI_1, 0x02}, - {NC , NC , 0} -}; - -static inline int ssp_disable(spi_t *obj); -static inline int ssp_enable(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); - - if ((int)obj->spi == NC) { - error("SPI pinout mapping failed"); - } - - // enable power and clocking - switch ((int)obj->spi) { - case SPI_0: - LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11; - LPC_SYSCON->SSP0CLKDIV = 0x01; - LPC_SYSCON->PRESETCTRL |= 1 << 0; - break; - case SPI_1: - LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18; - LPC_SYSCON->SSP1CLKDIV = 0x01; - LPC_SYSCON->PRESETCTRL |= 1 << 2; - break; - } - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) {} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - ssp_disable(obj); - - if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { - error("SPI format error"); - } - - int polarity = (mode & 0x2) ? 1 : 0; - int phase = (mode & 0x1) ? 1 : 0; - - // set it up - int DSS = bits - 1; // DSS (data select size) - int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity - int SPH = (phase) ? 1 : 0; // SPH - clock out phase - - int FRF = 0; // FRF (frame format) = SPI - uint32_t tmp = obj->spi->CR0; - tmp &= ~(0xFFFF); - tmp |= DSS << 0 - | FRF << 4 - | SPO << 6 - | SPH << 7; - obj->spi->CR0 = tmp; - - tmp = obj->spi->CR1; - tmp &= ~(0xD); - tmp |= 0 << 0 // LBM - loop back mode - off - | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave - | 0 << 3; // SOD - slave output disable - na - obj->spi->CR1 = tmp; - - ssp_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - ssp_disable(obj); - - uint32_t PCLK = SystemCoreClock; - - int prescaler; - - for (prescaler = 2; prescaler <= 254; prescaler += 2) { - int prescale_hz = PCLK / prescaler; - - // calculate the divider - int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); - - // check we can support the divider - if (divider < 256) { - // prescaler - obj->spi->CPSR = prescaler; - - // divider - obj->spi->CR0 &= ~(0xFFFF << 8); - obj->spi->CR0 |= (divider - 1) << 8; - ssp_enable(obj); - return; - } - } - error("Couldn't setup requested SPI frequency"); -} - -static inline int ssp_disable(spi_t *obj) { - return obj->spi->CR1 &= ~(1 << 1); -} - -static inline int ssp_enable(spi_t *obj) { - return obj->spi->CR1 |= (1 << 1); -} - -static inline int ssp_readable(spi_t *obj) { - return obj->spi->SR & (1 << 2); -} - -static inline int ssp_writeable(spi_t *obj) { - return obj->spi->SR & (1 << 1); -} - -static inline void ssp_write(spi_t *obj, int value) { - while (!ssp_writeable(obj)); - obj->spi->DR = value; -} - -static inline int ssp_read(spi_t *obj) { - while (!ssp_readable(obj)); - return obj->spi->DR; -} - -static inline int ssp_busy(spi_t *obj) { - return (obj->spi->SR & (1 << 4)) ? (1) : (0); -} - -int spi_master_write(spi_t *obj, int value) { - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) { - return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); -}; - -int spi_slave_read(spi_t *obj) { - return obj->spi->DR; -} - -void spi_slave_write(spi_t *obj, int value) { - while (ssp_writeable(obj) == 0) ; - obj->spi->DR = value; -} - -int spi_busy(spi_t *obj) { - return ssp_busy(obj); -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/PortNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/PortNames.h deleted file mode 100644 index 4887fecb332..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/PortNames.h +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, - Port1 = 1, - Port2 = 2, - Port3 = 3 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/analogin_api.c deleted file mode 100644 index 7fd16253d3d..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/analogin_api.c +++ /dev/null @@ -1,123 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "analogin_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "error.h" - -#define ANALOGIN_MEDIAN_FILTER 1 - -#define ADC_10BIT_RANGE 0x3FF -#define ADC_12BIT_RANGE 0xFFF - -static inline int div_round_up(int x, int y) { - return (x + (y - 1)) / y; -} - -static const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 2}, - {P1_0 , ADC0_1, 2}, - {P1_1 , ADC0_2, 2}, - {P1_2 , ADC0_3, 2}, - // ADC0_4 (P1_3) should be mapped to SWDIO only - {P1_4 , ADC0_5, 1}, - {P1_10, ADC0_6, 1}, - {P1_11, ADC0_7, 1}, - {NC , NC , 0} -}; - -#define ADC_RANGE ADC_10BIT_RANGE - -void analogin_init(analogin_t *obj, PinName pin) { - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - if (obj->adc == (uint32_t)NC) { - error("ADC pin mapping failed"); - return; - } - - // Power up ADC - LPC_SYSCON->PDRUNCFG &= ~(1 << 4); - LPC_SYSCON->SYSAHBCLKCTRL |= ((uint32_t)1 << 13); - - __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0xff)); - - // set pin to ADC mode - *reg &= ~(1 << 7); // set ADMODE = 0 (analog mode) - - uint32_t PCLK = SystemCoreClock; - uint32_t MAX_ADC_CLK = 4500000; - uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1; - - LPC_ADC->CR = (0 << 0) // no channels selected - | (clkdiv << 8) // max of 4.5MHz - | (0 << 16) // BURST = 0, software controlled - | ( 0 << 17 ); // CLKS = 0, not applicable - - pinmap_pinout(pin, PinMap_ADC); -} - -static inline uint32_t adc_read(analogin_t *obj) { - // Select the appropriate channel and start conversion - LPC_ADC->CR &= ~0xFF; - LPC_ADC->CR |= 1 << (int)obj->adc; - LPC_ADC->CR |= 1 << 24; - - // Repeatedly get the sample data until DONE bit - unsigned int data; - do { - data = LPC_ADC->GDR; - } while ((data & ((unsigned int)1 << 31)) == 0); - - // Stop conversion - LPC_ADC->CR &= ~(1 << 24); - - return (data >> 6) & ADC_RANGE; // 10 bit -} - -static inline void order(uint32_t *a, uint32_t *b) { - if (*a > *b) { - uint32_t t = *a; - *a = *b; - *b = t; - } -} - -static inline uint32_t adc_read_u32(analogin_t *obj) { - uint32_t value; -#if ANALOGIN_MEDIAN_FILTER - uint32_t v1 = adc_read(obj); - uint32_t v2 = adc_read(obj); - uint32_t v3 = adc_read(obj); - order(&v1, &v2); - order(&v2, &v3); - order(&v1, &v2); - value = v2; -#else - value = adc_read(obj); -#endif - return value; -} - -uint16_t analogin_read_u16(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - - return (value << 6) | ((value >> 4) & 0x003F); // 10 bit -} - -float analogin_read(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - return (float)value * (1.0f / (float)ADC_RANGE); -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_object.h deleted file mode 100644 index 2ece747074f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_object.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - __I uint32_t *reg_mask_read; - __IO uint32_t *reg_dir; - __IO uint32_t *reg_write; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - uint32_t pin_number = ((obj->pin & 0x0F00) >> 8); - if (value) - *obj->reg_write |= (1 << pin_number); - else - *obj->reg_write &= ~(1 << pin_number); -} - -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_mask_read) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/pinmap.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/pinmap.c deleted file mode 100644 index 8006ca18f1f..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/pinmap.c +++ /dev/null @@ -1,47 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pinmap.h" -#include "error.h" - -void pin_function(PinName pin, int function) { - if (pin == (uint32_t)NC) return; - - uint32_t offset = (uint32_t)pin & 0xff; - __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + offset); - - // pin function bits: [2:0] -> 111 = (0x7) - *reg = (*reg & ~0x7) | (function & 0x7); -} - -void pin_mode(PinName pin, PinMode mode) { - if (pin == (uint32_t)NC) { return; } - - uint32_t offset = (uint32_t)pin & 0xff; - uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2; - - __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + offset); - uint32_t tmp = *reg; - - // pin mode bits: [4:3] -> 11000 = (0x3 << 3) - tmp &= ~(0x3 << 3); - tmp |= (mode & 0x3) << 3; - - // drain - tmp &= ~(0x1 << 10); - tmp |= drain << 10; - - *reg = tmp; -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/port_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/port_api.c deleted file mode 100644 index 3dd911eed59..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/port_api.c +++ /dev/null @@ -1,78 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" - -// LPC114 IOCON offset table [port][pin] - -static uint8_t iocon_offset[4][12] = { - {0x0c,0x10,0x1c,0x2c,0x30,0x34,0x4c,0x50,0x60,0x64,0x68,0x74}, // PORT 0 - {0x78,0x7c,0x80,0x90,0x94,0xa0,0xa4,0xa8,0x14,0x38,0x6c,0x98}, // PORT 1 - {0x08,0x28,0x5c,0x8c,0x40,0x44,0x00,0x20,0x24,0x54,0x58,0x70}, // PORT 2 - {0x84,0x88,0x9c,0xac,0x3c,0x48} // PORT 3 -}; - -PinName port_pin(PortName port, int pin) { - return (PinName)((port << PORT_SHIFT) | (pin << PIN_SHIFT) | (uint32_t)iocon_offset[port][pin]); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { - obj->port = port; - obj->mask = mask; - - LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (port * 0x10000))); - - obj->reg_data = &port_reg->DATA; - obj->reg_dir = &port_reg->DIR; - - uint32_t i; - // The function is set per pin: reuse gpio logic - for (i=0; i<12; i++) { - if (obj->mask & (1<port, i)); - } - } - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) { - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i=0; i<12; i++) { - if (obj->mask & (1<port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) { - switch (dir) { - case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; - } -} - -void port_write(port_t *obj, int value) { - *obj->reg_data = (value & obj->mask); -} - -int port_read(port_t *obj) { - return (*obj->reg_data & obj->mask); -} - diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/serial_api.c deleted file mode 100644 index 18b1bd9a7e1..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/serial_api.c +++ /dev/null @@ -1,278 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include -#include - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "error.h" - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define UART_NUM 1 - -static const PinMap PinMap_UART_TX[] = { - {P2_8 , UART_0, 0x02}, - {P3_5 , UART_0, 0x02}, - {P3_0 , UART_0, 0x03}, - {P1_7 , UART_0, 0x01}, - {NC , NC , 0x00} -}; - -static const PinMap PinMap_UART_RX[] = { - {P2_7 , UART_0, 0x02}, - {P3_4 , UART_0, 0x02}, - {P3_1 , UART_0, 0x03}, - {P1_6 , UART_0, 0x01}, - {NC , NC , 0x00} -}; - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - int is_stdio_uart = 0; - - // determine the UART to use - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - if ((int)uart == NC) { - error("Serial pinout mapping failed"); - } - - obj->uart = (LPC_UART_TypeDef *)uart; - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); - - // enable fifos and default rx trigger level - obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled - | 0 << 1 // Rx Fifo Reset - | 0 << 2 // Tx Fifo Reset - | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars - - // disable irqs - obj->uart->IER = 0 << 0 // Rx Data available irq enable - | 0 << 1 // Tx Fifo empty irq enable - | 0 << 2; // Rx Line Status irq enable - - // set default baud rate and format - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - // pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - // set rx/tx pins in PullUp mode - pin_mode(tx, PullUp); - pin_mode(rx, PullUp); - - switch (uart) { - case UART_0: obj->index = 0; break; - } - - is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; -} - -// serial_baud -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) { - LPC_SYSCON->UARTCLKDIV = 0x1; - uint32_t PCLK = SystemCoreClock; - // First we check to see if the basic divide with no DivAddVal/MulVal - // ratio gives us an integer result. If it does, we set DivAddVal = 0, - // MulVal = 1. Otherwise, we search the valid ratio value range to find - // the closest match. This could be more elegant, using search methods - // and/or lookup tables, but the brute force method is not that much - // slower, and is more maintainable. - uint16_t DL = PCLK / (16 * baudrate); - - uint8_t DivAddVal = 0; - uint8_t MulVal = 1; - int hit = 0; - uint16_t dlv; - uint8_t mv, dav; - if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder - float err_best = (float) baudrate; - uint16_t dlmax = DL; - for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) { - for ( mv = 1; mv <= 15; mv++) { - for ( dav = 1; dav < mv; dav++) { - float ratio = 1.0f + ((float) dav / (float) mv); - float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio); - float err = fabs(((float) baudrate - calcbaud) / (float) baudrate); - if (err < err_best) { - DL = dlv; - DivAddVal = dav; - MulVal = mv; - err_best = err; - if (err < 0.001f) { - hit = 1; - } - } - } - } - } - } - - // set LCR[DLAB] to enable writing to divider registers - obj->uart->LCR |= (1 << 7); - - // set divider values - obj->uart->DLM = (DL >> 8) & 0xFF; - obj->uart->DLL = (DL >> 0) & 0xFF; - obj->uart->FDR = (uint32_t) DivAddVal << 0 - | (uint32_t) MulVal << 4; - - // clear LCR[DLAB] - obj->uart->LCR &= ~(1 << 7); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - // 0: 1 stop bits, 1: 2 stop bits - if (stop_bits != 1 && stop_bits != 2) { - error("Invalid stop bits specified"); - } - stop_bits -= 1; - - // 0: 5 data bits ... 3: 8 data bits - if (data_bits < 5 || data_bits > 8) { - error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits); - } - data_bits -= 5; - - int parity_enable, parity_select; - switch (parity) { - case ParityNone: parity_enable = 0; parity_select = 0; break; - case ParityOdd : parity_enable = 1; parity_select = 0; break; - case ParityEven: parity_enable = 1; parity_select = 1; break; - case ParityForced1: parity_enable = 1; parity_select = 2; break; - case ParityForced0: parity_enable = 1; parity_select = 3; break; - default: - error("Invalid serial parity setting"); - return; - } - - obj->uart->LCR = data_bits << 0 - | stop_bits << 2 - | parity_enable << 3 - | parity_select << 4; -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t iir, uint32_t index) { - // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling - SerialIrq irq_type; - switch (iir) { - case 1: irq_type = TxIrq; break; - case 2: irq_type = RxIrq; break; - default: return; - } - - if (serial_irq_ids[index] != 0) - irq_handler(serial_irq_ids[index], irq_type); -} - -void uart0_irq() {uart_irq((LPC_UART->IIR >> 1) & 0x7, 0);} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case UART_0: - irq_n=UART_IRQn; - vector = (uint32_t)&uart0_irq; - break; - default: - return; - } - - if (enable) { - obj->uart->IER |= 1 << irq; - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - - obj->uart->IER &= ~(1 << irq); - all_disabled = (obj->uart->IER & (1 << other_irq)) == 0; - - if (all_disabled) - NVIC_DisableIRQ(irq_n); - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) { - while (!serial_readable(obj)); - return obj->uart->RBR; -} - -void serial_putc(serial_t *obj, int c) { - while (!serial_writable(obj)); - obj->uart->THR = c; -} - -int serial_readable(serial_t *obj) { - return obj->uart->LSR & 0x01; -} - -int serial_writable(serial_t *obj) { - return obj->uart->LSR & 0x20; -} - -void serial_clear(serial_t *obj) { - obj->uart->FCR = 1 << 1 // rx FIFO reset - | 1 << 2 // tx FIFO reset - | 0 << 6; // interrupt depth -} - -void serial_pinout_tx(PinName tx) { - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_clear(serial_t *obj) { - obj->uart->LCR &= ~(1 << 6); -} - -void serial_break_set(serial_t *obj) { - obj->uart->LCR |= 1 << 6; -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/sleep.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/sleep.c deleted file mode 100644 index 051db5217bc..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/sleep.c +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "mbed_interface.h" - -void sleep(void) { - // ensure debug is disconnected - mbed_interface_disconnect(); - - // PCON[DPDEN] set to sleep - LPC_PMU->PCON = 0x0; - - // SRC[SLEEPDEEP] set to 0 = sleep - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - - // wait for interrupt - __WFI(); -} - -/* -* The mbed lpc1768 does not support the deepsleep mode -* as a debugger is connected to it (the mbed interface). -* -* As mentionned in an application note from NXP: -* -* http://www.po-star.com/public/uploads/20120319123122_141.pdf -* -* {{{ -* The user should be aware of certain limitations during debugging. -* The most important is that, due to limitations of the Cortex-M3 -* integration, the LPC17xx cannot wake up in the usual manner from -* Deep Sleep and Power-down modes. It is recommended not to use these -* modes during debug. Once an application is downloaded via JTAG/SWD -* interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example) -* should be removed from the target board, and thereafter, power cycle -* the LPC17xx to allow wake-up from deep sleep and power-down modes -* }}} -* -* As the interface firmware does not reset the target when a -* mbed_interface_disconnect() semihosting call is made, the -* core cannot wake-up from deepsleep. -* -* We treat a deepsleep() as a normal sleep(). -*/ - -void deepsleep(void) { - // ensure debug is disconnected - mbed_interface_disconnect(); - - // PCON[DPDEN] set to deepsleep - LPC_PMU->PCON = 0x2; - - // SRC[SLEEPDEEP] set to 1 = deep sleep - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - // Power up everything after powerdown - LPC_SYSCON->PDAWAKECFG &= 0xFFFFF800; - - // wait for interrupt - __WFI(); -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/us_ticker.c deleted file mode 100644 index 32b7f0d66f5..00000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/us_ticker.c +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -#define US_TICKER_TIMER ((LPC_TMR_TypeDef *)LPC_CT32B1_BASE) -#define US_TICKER_TIMER_IRQn TIMER_32_1_IRQn - -int us_ticker_inited = 0; - -void us_ticker_init(void) { - if (us_ticker_inited) return; - us_ticker_inited = 1; - - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock TIMER_1 - uint32_t PCLK = SystemCoreClock; - - US_TICKER_TIMER->TCR = 0x2; // reset - - uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks) - US_TICKER_TIMER->PR = prescale - 1; - US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0 - - NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -uint32_t us_ticker_read() { - if (!us_ticker_inited) - us_ticker_init(); - - return US_TICKER_TIMER->TC; -} - -void us_ticker_set_interrupt(unsigned int timestamp) { - // set match value - US_TICKER_TIMER->MR0 = timestamp; - // enable match interrupt - US_TICKER_TIMER->MCR |= 1; -} - -void us_ticker_disable_interrupt(void) { - US_TICKER_TIMER->MCR &= ~1; -} - -void us_ticker_clear_interrupt(void) { - US_TICKER_TIMER->IR = 1; -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/PortNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/PortNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/PinNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/README.md b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/README.md similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/README.md rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/README.md diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/adc_pinmap.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/adc_pinmap.h new file mode 100644 index 00000000000..2fc49f4adde --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/adc_pinmap.h @@ -0,0 +1,20 @@ +// ADC pin mappings for LPC11CXX +// This should be included ONLY from analogin_api.c + +#ifndef ADC_PINMAP_H +#define ADC_PINMAP_H + +static const PinMap PinMap_ADC[] = { + {P0_11, ADC0_0, 2}, + {P1_0 , ADC0_1, 2}, + {P1_1 , ADC0_2, 2}, + {P1_2 , ADC0_3, 2}, + {P1_3 , ADC0_4, 2}, + {P1_4 , ADC0_5, 1}, + {P1_10, ADC0_6, 1}, + {P1_11, ADC0_7, 1}, + {NC , NC , 0} +}; + +#endif + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/device.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/objects.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/objects.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/reserved_pins.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/reserved_pins.h new file mode 100644 index 00000000000..7c8a7ba3c4b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/reserved_pins.h @@ -0,0 +1,8 @@ +// List of reserved pins for LPC11C24 + +#ifndef RESERVED_PINS_H +#define RESERVED_PINS_H + +#define TARGET_RESERVED_PINS {P0_0, P0_10, P0_11, P1_0, P1_1, P1_2, P1_3} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/spi_pinmap.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/spi_pinmap.h new file mode 100644 index 00000000000..03dbb35095a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/spi_pinmap.h @@ -0,0 +1,34 @@ +// SPI pin mappings for LPC11CXX +// This should be included ONLY from spi_api.c + +#ifndef SPI_PINMAP_H +#define SPI_PINMAP_H + +static const PinMap PinMap_SPI_SCLK[] = { + {P0_6 , SPI_0, 0x02}, + {P0_10, SPI_0, 0x02}, + {P2_11, SPI_0, 0x01}, + {P2_1 , SPI_1, 0x02}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {P0_9 , SPI_0, 0x01}, + {P2_3 , SPI_1, 0x02}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {P0_8 , SPI_0, 0x01}, + {P2_2 , SPI_1, 0x02}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {P0_2 , SPI_0, 0x01}, + {P2_0 , SPI_1, 0x02}, + {NC , NC , 0} +}; + +#endif + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/PinNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/README.md b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/README.md similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/README.md rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/README.md diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/adc_pinmap.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/adc_pinmap.h new file mode 100644 index 00000000000..d2a80e989e1 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/adc_pinmap.h @@ -0,0 +1,20 @@ +// ADC pin mappings for LPC11XX +// This should be included ONLY from analogin_api.c + +#ifndef ADC_PINMAP_H +#define ADC_PINMAP_H + +static const PinMap PinMap_ADC[] = { + {P0_11, ADC0_0, 2}, + {P1_0 , ADC0_1, 2}, + {P1_1 , ADC0_2, 2}, + {P1_2 , ADC0_3, 2}, + // ADC0_4 (P1_3) should be mapped to SWDIO only + {P1_4 , ADC0_5, 1}, + {P1_10, ADC0_6, 1}, + {P1_11, ADC0_7, 1}, + {NC , NC , 0} +}; + +#endif + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/device.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/objects.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/objects.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/reserved_pins.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/reserved_pins.h new file mode 100644 index 00000000000..f33637f5573 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/reserved_pins.h @@ -0,0 +1,8 @@ +// List of reserved pins for LPC1114 + +#ifndef RESERVED_PINS_H +#define RESERVED_PINS_H + +#define TARGET_RESERVED_PINS {P0_0, P0_11, P1_0, P1_1, P1_2} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/spi_pinmap.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/spi_pinmap.h new file mode 100644 index 00000000000..da5ca3d48b6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/spi_pinmap.h @@ -0,0 +1,33 @@ +// SPI pin mappings for LPC11XX +// This should be included ONLY from spi_api.c + +#ifndef SPI_PINMAP_H +#define SPI_PINMAP_H + +static const PinMap PinMap_SPI_SCLK[] = { + {P0_6 , SPI_0, 0x02}, + {P2_11, SPI_0, 0x01}, + {P2_1 , SPI_1, 0x02}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {P0_9 , SPI_0, 0x01}, + {P2_3 , SPI_1, 0x02}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {P0_8 , SPI_0, 0x01}, + {P2_2 , SPI_1, 0x02}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {P0_2 , SPI_0, 0x01}, + {P2_0 , SPI_1, 0x02}, + {NC , NC , 0} +}; + +#endif + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c similarity index 92% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c index 2309224f68e..a5587eb5d0c 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c @@ -18,6 +18,8 @@ #include "pinmap.h" #include "error.h" +#include "adc_pinmap.h" + #define ANALOGIN_MEDIAN_FILTER 1 #define ADC_10BIT_RANGE 0x3FF @@ -27,24 +29,13 @@ static inline int div_round_up(int x, int y) { return (x + (y - 1)) / y; } -static const PinMap PinMap_ADC[] = { - {P0_11, ADC0_0, 2}, - {P1_0 , ADC0_1, 2}, - {P1_1 , ADC0_2, 2}, - {P1_2 , ADC0_3, 2}, - {P1_3 , ADC0_4, 2}, - {P1_4 , ADC0_5, 1}, - {P1_10, ADC0_6, 1}, - {P1_11, ADC0_7, 1}, - {NC , NC , 0} -}; - #define ADC_RANGE ADC_10BIT_RANGE void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); if (obj->adc == (uint32_t)NC) { error("ADC pin mapping failed"); + return; } // Power up ADC diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_api.c similarity index 86% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_api.c index b6f097a67c0..7ed3ed91a38 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_api.c @@ -15,16 +15,21 @@ */ #include "gpio_api.h" #include "pinmap.h" +#include "reserved_pins.h" + +static const PinName reserved_pins[] = TARGET_RESERVED_PINS; uint32_t gpio_set(PinName pin) { // PIO default value of following ports are not same as others - int f = ((pin == P0_0 ) || // RESET - (pin == P0_11) || // R - (pin == P1_0 ) || // R - (pin == P1_1 ) || // R - (pin == P1_2 )) ? // R - (1) : (0); - + unsigned i; + int f = 0; + + for (i = 0; i < sizeof(reserved_pins) / sizeof(int); i ++) + if (pin == reserved_pins[i]) { + f = 1; + break; + } + pin_function(pin, f); return ((pin & 0x0F00) >> 8); } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/pinmap.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pinmap.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/pinmap.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pinmap.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/port_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/port_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/port_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/port_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/serial_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/sleep.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/sleep.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/sleep.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/sleep.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c similarity index 91% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/spi_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c index f41f008f846..ed9ed023817 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c @@ -19,30 +19,7 @@ #include "pinmap.h" #include "error.h" -static const PinMap PinMap_SPI_SCLK[] = { - {P0_6 , SPI_0, 0x02}, - {P2_11, SPI_0, 0x01}, - {P2_1 , SPI_1, 0x02}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {P0_9 , SPI_0, 0x01}, - {P2_3 , SPI_1, 0x02}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {P0_8 , SPI_0, 0x01}, - {P2_2 , SPI_1, 0x02}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {P0_2 , SPI_0, 0x01}, - {P2_0 , SPI_1, 0x02}, - {NC , NC , 0} -}; +#include "spi_pinmap.h" static inline int ssp_disable(spi_t *obj); static inline int ssp_enable(spi_t *obj); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/us_ticker.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/us_ticker.c diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 888f40b9c00..fccaa67b3b4 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -266,7 +266,7 @@ def __init__(self): self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11XX'] + self.extra_labels = ['NXP', 'LPC11XX_11CXX', 'LPC11XX'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] @@ -277,7 +277,7 @@ def __init__(self): self.core = "Cortex-M0" - self.extra_labels = ['NXP', 'LPC11CXX'] + self.extra_labels = ['NXP', 'LPC11XX_11CXX', 'LPC11CXX'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]