From 5ae13f9c7b807547e46cfc8c96f166381b74a1d0 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 16 Jan 2019 15:01:09 +0100 Subject: [PATCH 1/2] STM32F756 / STM32F746 alignment --- .../device/TOOLCHAIN_ARM_STD/stm32f746xg.sct | 4 +-- .../device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld | 4 +-- .../TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S | 14 ++++----- .../TARGET_STM32F746xG/device/cmsis_nvic.h | 2 +- .../TARGET_NUCLEO_F756ZG/system_clock.c | 9 +++--- .../device/TOOLCHAIN_ARM_STD/stm32f756xg.sct | 30 +++++++++++++++---- .../device/TOOLCHAIN_GCC_ARM/STM32F756xG.ld | 24 ++++++++++++++- .../device/TOOLCHAIN_IAR/stm32f756xg.icf | 20 +++++++++---- .../TARGET_STM32F756xG/objects.h | 10 +++++++ 9 files changed, 90 insertions(+), 27 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct index 8e9ba7becc1..c909fdc2609 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct @@ -51,7 +51,7 @@ #define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) #define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE) -; STM32F746NG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) +; STM32F746xG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address @@ -59,7 +59,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - + RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld index 75dfa94f7a8..416d4a286ca 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld @@ -93,7 +93,7 @@ SECTIONS __etext = .; _sidata = .; - + .crash_data_ram : { . = ALIGN(8); @@ -104,7 +104,7 @@ SECTIONS . += M_CRASH_DATA_RAM_SIZE; . = ALIGN(8); __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ - } > RAM + } > RAM .data : AT (__etext) { diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S index 8a950e13b30..a457c54c818 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S @@ -235,12 +235,12 @@ g_pfnVectors: .word UART7_IRQHandler /* UART7 */ .word UART8_IRQHandler /* UART8 */ .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ .word SAI2_IRQHandler /* SAI2 */ .word QUADSPI_IRQHandler /* QUADSPI */ .word LPTIM1_IRQHandler /* LPTIM1 */ @@ -577,5 +577,5 @@ g_pfnVectors: .weak SPDIF_RX_IRQHandler .thumb_set SPDIF_RX_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/cmsis_nvic.h index 878cea72be4..de4c30ea1fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/cmsis_nvic.h @@ -34,7 +34,7 @@ // CORE: 16 vectors = 64 bytes from 0x00 to 0x3F // MCU Peripherals: 98 vectors = 392 bytes from 0x40 to 0x1C7 // Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM -#define NVIC_NUM_VECTORS 114 +#define NVIC_NUM_VECTORS 114 #define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c index c9ccf489ddc..d0afc10a243 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c @@ -30,6 +30,7 @@ **/ #include "stm32f7xx.h" +#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -92,7 +93,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ #endif } @@ -208,14 +209,14 @@ uint8_t SetSysClock_PLL_HSI(void) __PWR_CLK_ENABLE(); // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSEState = RCC_HSE_OFF; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (16 MHz / 16) - RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (1 MHz * 432) + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (2 MHz * 216) RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) RCC_OscInitStruct.PLL.PLLQ = 9; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_ARM_STD/stm32f756xg.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_ARM_STD/stm32f756xg.sct index 3c26927bf86..c909fdc2609 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_ARM_STD/stm32f756xg.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_ARM_STD/stm32f756xg.sct @@ -28,27 +28,47 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif #define Stack_Size MBED_BOOT_STACK_SIZE -; STM32F756ZG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) -LR_IROM1 0x08000000 0x100000 { ; load region size_region +#define MBED_RAM_START 0x20000000 +#define MBED_RAM_SIZE 0x50000 +#define MBED_VECTTABLE_RAM_START (MBED_RAM_START) +#define MBED_VECTTABLE_RAM_SIZE 0x1C8 +#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) +#define MBED_CRASH_REPORT_RAM_SIZE 0x100 +#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE) - ER_IROM1 0x08000000 0x100000 { ; load address = execution address +; STM32F746xG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } + RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data + } + ; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM - RW_IRAM1 (0x20000000+0x1C8) (0x50000-0x1C8-Stack_Size) { ; RW data + RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data .ANY (+RW +ZI) } - ARM_LIB_STACK (0x20000000+0x50000) EMPTY -Stack_Size { ; stack + ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack } } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_GCC_ARM/STM32F756xG.ld b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_GCC_ARM/STM32F756xG.ld index c9f4e3064e5..416d4a286ca 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_GCC_ARM/STM32F756xG.ld +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_GCC_ARM/STM32F756xG.ld @@ -6,9 +6,19 @@ STACK_SIZE = MBED_BOOT_STACK_SIZE; +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 1024K +#endif + +M_CRASH_DATA_RAM_SIZE = 0x100; + MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE RAM (rwx) : ORIGIN = 0x200001C8, LENGTH = 320K - 0x1C8 } @@ -84,6 +94,18 @@ SECTIONS __etext = .; _sidata = .; + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > RAM + .data : AT (__etext) { __data_start__ = .; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_IAR/stm32f756xg.icf b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_IAR/stm32f756xg.icf index f94fa2e1b18..0eafd914168 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_IAR/stm32f756xg.icf +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_IAR/stm32f756xg.icf @@ -1,12 +1,17 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } + /* [ROM = 1024kb = 0x100000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x080FFFFF; +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM = 320kb = 0x50000] Vector table dynamic copy: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; define symbol __NVIC_end__ = 0x200001C7; /* Aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200001C8; +define symbol __region_CRASH_DATA_RAM_start__ = 0x200001C8; +define symbol __region_CRASH_DATA_RAM_end__ = 0x200002C7; +define symbol __region_RAM_start__ = 0x200002C8; define symbol __region_RAM_end__ = 0x2004FFFF; define symbol __region_ITCMRAM_start__ = 0x00000000; @@ -16,14 +21,19 @@ define symbol __region_ITCMRAM_end__ = 0x00003FFF; define memory mem with size = 4G; define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__]; define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__]; +/* Define Crash Data Symbols */ +define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__; +define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__; + /* Stack and Heap */ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __size_heap__ = 0x10000; +define symbol __size_heap__ = 0x13000; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; define block STACKHEAP with fixed order { block HEAP, block CSTACK }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h index 28946911189..2e538dcf5bc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h @@ -58,6 +58,16 @@ struct trng_s { RNG_HandleTypeDef handle; }; +struct qspi_s { + QSPI_HandleTypeDef handle; + PinName io0; + PinName io1; + PinName io2; + PinName io3; + PinName sclk; + PinName ssel; +}; + #include "common_objects.h" #ifdef __cplusplus From 7876a653c61383995a4f3a961e937d855627503a Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 16 Jan 2019 15:11:15 +0100 Subject: [PATCH 2/2] STM32L476 / STM32L486 alignment --- .../device/TOOLCHAIN_ARM_STD/stm32l476xx.sct | 4 ++-- .../device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld | 8 ++++---- .../TARGET_NUCLEO_L486RG/system_clock.c | 2 +- .../device/TOOLCHAIN_ARM_STD/stm32l486xx.sct | 16 ++++++++++++++-- .../device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld | 16 +++++++++++++++- .../device/TOOLCHAIN_IAR/stm32l486xx.icf | 11 +++++++++-- .../TARGET_STM32L4/TARGET_STM32L486xG/objects.h | 10 ++++++++++ 7 files changed, 55 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct index 19355d7e946..fb5dafd14af 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct @@ -60,11 +60,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data } - + RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE-Stack_Size { ; RW data 96k L4-SRAM1 .ANY (+RW +ZI) } - + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby .ANY (+RW +ZI) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld index 14f1c4574a1..71f28a5c25a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld @@ -16,7 +16,7 @@ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Linker script to configure memory regions. */ MEMORY -{ +{ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188 SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k @@ -26,7 +26,7 @@ MEMORY * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler - * + * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end @@ -93,7 +93,7 @@ SECTIONS __etext = .; _sidata = .; - + .crash_data_ram : { . = ALIGN(8); @@ -104,7 +104,7 @@ SECTIONS . += M_CRASH_DATA_RAM_SIZE; . = ALIGN(8); __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ - } > SRAM1 + } > SRAM1 .data : AT (__etext) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c index fbc19d89206..d71a36fb671 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c @@ -97,7 +97,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ #endif } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/stm32l486xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/stm32l486xx.sct index e658a649009..fb5dafd14af 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/stm32l486xx.sct +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/stm32l486xx.sct @@ -36,6 +36,13 @@ #define MBED_APP_SIZE 0x100000 #endif +#define MBED_RAM_START 0x20000000 +#define MBED_RAM_SIZE 0x00018000 +#define MBED_CRASH_REPORT_RAM_START (MBED_RAM_START) +#define MBED_CRASH_REPORT_RAM_SIZE 0x100 +#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE) + #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -51,15 +58,20 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region .ANY (+RO) } - RW_IRAM1 0x20000000 0x00018000-Stack_Size { ; RW data 96k L4-SRAM1 + RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data + } + + RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE-Stack_Size { ; RW data 96k L4-SRAM1 .ANY (+RW +ZI) } + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby .ANY (+RW +ZI) } - ARM_LIB_STACK (0x20000000+0x00018000) EMPTY -Stack_Size { ; stack + ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack } + } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld index d593270e7a5..71f28a5c25a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld @@ -6,6 +6,8 @@ #define MBED_APP_SIZE 1024k #endif +M_CRASH_DATA_RAM_SIZE = 0x100; + #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif @@ -15,7 +17,7 @@ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188 SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k } @@ -92,6 +94,18 @@ SECTIONS __etext = .; _sidata = .; + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > SRAM1 + .data : AT (__etext) { __data_start__ = .; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf index 26cd40fd8c2..864e944e7ba 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf @@ -1,5 +1,5 @@ if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x80000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } /* [ROM = 1024kb = 0x100000] */ define symbol __intvec_start__ = MBED_APP_START; @@ -12,15 +12,22 @@ define symbol __NVIC_start__ = 0x10000000; define symbol __NVIC_end__ = 0x10000187; define symbol __region_SRAM2_start__ = 0x10000188; define symbol __region_SRAM2_end__ = 0x10007FFF; -define symbol __region_SRAM1_start__ = 0x20000000; +define symbol __region_CRASH_DATA_RAM_start__ = 0x20000000; +define symbol __region_CRASH_DATA_RAM_end__ = 0x200000FF; +define symbol __region_SRAM1_start__ = 0x20000100; define symbol __region_SRAM1_end__ = 0x20017FFF; /* Memory regions */ define memory mem with size = 4G; define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__]; +define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__]; define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__]; +/* Define Crash Data Symbols */ +define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__; +define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__; + if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h index ece5f1679fa..cd0f1a783c1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h @@ -58,6 +58,16 @@ struct trng_s { RNG_HandleTypeDef handle; }; +struct qspi_s { + QSPI_HandleTypeDef handle; + PinName io0; + PinName io1; + PinName io2; + PinName io3; + PinName sclk; + PinName ssel; +}; + #include "common_objects.h" #ifdef __cplusplus