Join GitHub today
GitHub is home to over 40 million developers working together to host and review code, manage projects, and build software together.Sign up
Description of defect
Cypress: PWM FPGA test wrong assert
In file mbed_hal_fpga_ci_test_shield/pwm/main.c line 146 expected value is 10 ms actual (measured) is 10 ms. But log file shows: "1077477377 - peripheral tested on port: peripheral=(1077477377) PWM_OUT=(D7) ...:146::FAIL: Expected 0.100000 Was 10.000000"
I run test case "Case("PWM - period: 10 ms, fill: 10%, api: period/write", one_peripheral<PWMPort, DefaultFormFactor, pwm_period_fill_test<10, 10, PERIOD_WRITE> >),"
Target(s) affected by this defect ?
Tested on CY8CKIT_062_WIFI_BT
Toolchain(s) (name and version) displaying this defect ?
Tested on GCC_ARM
What version of Mbed-os are you using (tag or sha) ?
What version(s) of tools are you using. List all that apply (E.g. mbed-cli)
How is this defect reproduced ?
According to the requirements:
In the test we are setting output duty-cycle to
Looks like everything is ok, but the
[HTST][INF] host test detected: default_auto
Implementation of pwmout_read() is not consistent with the requirements. This function should return the current float-point output duty-cycle in range <0.0f, 1.0f>. Currently it returns decimal percentage value.