Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add SCLK and SIN stats to SPIMasterTester #10660

Merged
merged 1 commit into from Jun 3, 2019

Conversation

@mprse
Copy link
Member

commented May 24, 2019

Description

It has been found that there is a problem with the new K66F SPI driver when clock polarity is high.
After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high.
SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails.

The idea is to add support to the FPGA test shield to catch such errors and verify this in the test.

Pull request type

[X] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change

Reviewers

@c1728p9

@ciarmcom ciarmcom requested review from c1728p9 and ARMmbed/mbed-os-maintainers May 24, 2019
@ciarmcom

This comment has been minimized.

Copy link
Member

commented May 24, 2019

@mprse, thank you for your changes.
@c1728p9 @ARMmbed/mbed-os-maintainers please review.

It has been found that there is a problem with the new K66F SPI driver when clock polarity is high.
After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high.
SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails.

The idea is to add support to the FPGA test shield to catch such errors and verify this in the test.
@mprse mprse force-pushed the mprse:fpga_ts_add_sckl_stats branch from 042c47c to 87902a8 May 27, 2019
@0xc0170

This comment has been minimized.

Copy link
Member

commented May 31, 2019

CI started

@mbed-ci

This comment has been minimized.

Copy link

commented Jun 1, 2019

Test run: SUCCESS

Summary: 11 of 11 test jobs passed
Build number : 1
Build artifacts

@0xc0170

This comment has been minimized.

Copy link
Member

commented Jun 3, 2019

@mprse labeled as 5.14 as it adds new functionality to a component.

@0xc0170 0xc0170 merged commit 62698b9 into ARMmbed:master Jun 3, 2019
26 checks passed
26 checks passed
continuous-integration/jenkins/pr-head This commit looks good
Details
continuous-integration/travis-ci/pr The Travis CI build passed
Details
jenkins-ci/build-ARM Success
Details
jenkins-ci/build-GCC_ARM Success
Details
jenkins-ci/build-IAR Success
Details
jenkins-ci/cloud-client-test Success
Details
jenkins-ci/dynamic-memory-usage Internal error, will be fixed
Details
jenkins-ci/exporter Success
Details
jenkins-ci/greentea-test Success
Details
jenkins-ci/mbed2-build-ARM Success
Details
jenkins-ci/mbed2-build-GCC_ARM Success
Details
jenkins-ci/mbed2-build-IAR Success
Details
jenkins-ci/unittests Success
Details
travis-ci/astyle Success!
Details
travis-ci/docs Success!
Details
travis-ci/doxy-spellcheck Success!
Details
travis-ci/events Success! Runtime is 8482 cycles.
Details
travis-ci/gitattributestest Success!
Details
travis-ci/include_check Success!
Details
travis-ci/licence_check Success!
Details
travis-ci/littlefs Success! Code size is 8448B.
Details
travis-ci/psa-autogen Success!
Details
travis-ci/tools-py2.7 Success!
Details
travis-ci/tools-py3.5 Success!
Details
travis-ci/tools-py3.6 Success!
Details
travis-ci/tools-py3.7 Success!
Details
@0xc0170 0xc0170 removed the ready for merge label Jun 3, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
5 participants
You can’t perform that action at this time.