From ed9995e06cb6e99d32f3b7788bc22a03f07deafd Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Wed, 10 Jul 2019 21:43:55 +0300 Subject: [PATCH 01/16] PSOC6_SB: Initial commit to add CY8CPROTO_064_SB to mbed-os sources. --- features/storage/nvstore/mbed_lib.json | 6 + .../GeneratedSource/cycfg.c | 34 + .../GeneratedSource/cycfg.h | 47 + .../GeneratedSource/cycfg_clocks.c | 41 + .../GeneratedSource/cycfg_clocks.h | 52 + .../GeneratedSource/cycfg_notices.h | 30 + .../GeneratedSource/cycfg_peripherals.c | 77 + .../GeneratedSource/cycfg_peripherals.h | 75 + .../GeneratedSource/cycfg_pins.c | 426 ++ .../GeneratedSource/cycfg_pins.h | 326 ++ .../GeneratedSource/cycfg_qspi_memslot.c | 265 ++ .../GeneratedSource/cycfg_qspi_memslot.h | 50 + .../GeneratedSource/cycfg_routing.c | 29 + .../GeneratedSource/cycfg_routing.h | 56 + .../GeneratedSource/cycfg_system.c | 475 +++ .../GeneratedSource/cycfg_system.h | 82 + .../TARGET_CY8CPROTO_064_SB/PeripheralNames.h | 117 + .../TARGET_CY8CPROTO_064_SB/PeripheralPins.c | 465 +++ .../TARGET_CY8CPROTO_064_SB/PinNames.h | 135 + .../cybsp_cy8cproto_064_sb.c | 54 + .../cybsp_cy8cproto_064_sb.h | 74 + .../TARGET_CY8CPROTO_064_SB/cybsp_types.h | 157 + .../cycfg_qspi_memslot.cyqspi | 63 + .../TARGET_CY8CPROTO_064_SB/design.modus | 468 +++ .../TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct | 314 ++ .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 643 +++ .../TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld | 464 ++ .../TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S | 631 +++ .../TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf | 271 ++ .../TOOLCHAIN_IAR/startup_psoc6_01_cm4.S | 1141 +++++ .../TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c | 552 +++ .../device/system_psoc6.h | 675 +++ .../psoc6_static_srm.h | 85 + .../secure_image_parameters.json | 17 + .../devices/include/cyb06447bzi_d54.h | 2 +- .../TARGET_PSOC6/sb-tools/.gitignore | 1 + .../TARGET_PSOC6/sb-tools/README.md | 145 + .../sb-tools/encrypted_image_runner.py | 215 + .../sb-tools/entrance_exam_runner.py | 45 + .../sb-tools/execute/entrance_exam.py | 68 + .../TARGET_PSOC6/sb-tools/execute/enums.py | 30 + .../sb-tools/execute/gen_data_from_json.py | 38 + .../TARGET_PSOC6/sb-tools/execute/helper.py | 59 + .../sb-tools/execute/p6_memory_map.py | 17 + .../TARGET_PSOC6/sb-tools/execute/p6_reg.py | 95 + .../sb-tools/execute/programmer/__init__.py | 18 + .../sb-tools/execute/programmer/base.py | 179 + .../sb-tools/execute/programmer/exceptions.py | 23 + .../sb-tools/execute/programmer/programmer.py | 29 + .../execute/programmer/pyocd_wrapper.py | 272 ++ .../sb-tools/execute/provision_device.py | 105 + .../TARGET_PSOC6/sb-tools/execute/sys_call.py | 198 + .../sb-tools/imgtool/aes_cipher.py | 106 + .../sb-tools/imgtool/create_aesHeader.py | 46 + .../TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py | 68 + .../TARGET_PSOC6/sb-tools/imgtool/imgtool.py | 198 + .../sb-tools/imgtool/imgtool/__init__.py | 13 + .../sb-tools/imgtool/imgtool/image.py | 269 ++ .../sb-tools/imgtool/imgtool/keys/__init__.py | 76 + .../sb-tools/imgtool/imgtool/keys/ecdsa.py | 102 + .../imgtool/imgtool/keys/ecdsa_test.py | 99 + .../sb-tools/imgtool/imgtool/keys/general.py | 35 + .../sb-tools/imgtool/imgtool/keys/rsa.py | 95 + .../sb-tools/imgtool/imgtool/keys/rsa_test.py | 102 + .../sb-tools/imgtool/imgtool/version.py | 53 + .../TARGET_PSOC6/sb-tools/keys/keygen.py | 73 + .../CypressBootloader_CM0p.hex | 2375 +++++++++++ .../CypressBootloader_CM0p.jwt | 1 + .../CypressBootloader_CM0p.hex | 3714 +++++++++++++++++ .../CypressBootloader_CM0p.jwt | 1 + .../TARGET_PSOC6/sb-tools/prebuild/LICENSE | 51 + .../sb-tools/prebuild/cy_auth.jwt | 1 + .../sb-tools/prebuild/hsm_state.json | 18 + .../sb-tools/prebuild/oem_state.json | 18 + .../Apache/LICENSE-2.0.txt | 202 + .../third_party_licenses/Apache/README.txt | 5 + .../MIT/cjason-license.txt | 23 + .../Other/bsd_base64_license.txt | 63 + .../prepare/policy_single_stage_CM4.json | 113 + .../prepare/policy_single_stage_CM4_smif.json | 115 + .../prepare/provisioning_lib/cyprov_crypto.py | 116 + .../provisioning_lib/cyprov_customer.py | 50 + .../prepare/provisioning_lib/cyprov_entity.py | 46 + .../prepare/provisioning_lib/cyprov_hsm.py | 443 ++ .../prepare/provisioning_lib/cyprov_oem.py | 143 + .../prepare/provisioning_lib/cyprov_pem.py | 79 + .../prepare/provisioning_lib/cyprov_types.py | 29 + .../sb-tools/prepare/provisioning_packet.py | 133 + .../sb-tools/provision_device_runner.py | 80 + .../TARGET_PSOC6/sb-tools/requirements.txt | 7 + .../sb-tools/test/test_data/blinky_large.hex | 1410 +++++++ .../sb-tools/test/test_data/blinky_small.hex | 30 + .../sb-tools/test/test_pyocd_wrapper.py | 301 ++ .../sb-tools/test/test_utility.py | 39 + targets/targets.json | 15 + tools/targets/PSOC6.py | 346 +- tools/targets/__init__.py | 11 + 97 files changed, 21243 insertions(+), 6 deletions(-) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_notices.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralNames.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PinNames.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cycfg_qspi_memslot.cyqspi create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/design.modus create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/psoc6_static_srm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/encrypted_image_runner.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/entrance_exam_runner.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/entrance_exam.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/enums.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/gen_data_from_json.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/helper.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_memory_map.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_reg.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/__init__.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/base.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/exceptions.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/programmer.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/pyocd_wrapper.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/provision_device.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/sys_call.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/__init__.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/image.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/__init__.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/version.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/keygen.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.hex create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/LICENSE create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/cy_auth.jwt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/hsm_state.json create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/oem_state.json create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/LICENSE-2.0.txt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/README.txt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/MIT/cjason-license.txt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4.json create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4_smif.json create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_crypto.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_customer.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_entity.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_hsm.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_oem.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_pem.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_types.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_packet.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/provision_device_runner.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/requirements.txt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_large.hex create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_small.hex create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_pyocd_wrapper.py create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_utility.py diff --git a/features/storage/nvstore/mbed_lib.json b/features/storage/nvstore/mbed_lib.json index ea7c1641e99..a1cc58a7325 100644 --- a/features/storage/nvstore/mbed_lib.json +++ b/features/storage/nvstore/mbed_lib.json @@ -49,6 +49,12 @@ "area_1_size": 16384, "area_2_address": "0x100FC000", "area_2_size": 16384 + }, + "CY8CPROTO_064_SB": { + "area_1_address": "0x10048000", + "area_1_size": 16384, + "area_2_address": "0x1004C000", + "area_2_size": 16384 } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.c new file mode 100644 index 00000000000..cb430a41643 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_system(); + init_cycfg_clocks(); + init_cycfg_routing(); + init_cycfg_peripherals(); + init_cycfg_pins(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.h new file mode 100644 index 00000000000..9abc7f0f4ab --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_system.h" +#include "cycfg_clocks.h" +#include "cycfg_routing.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.c new file mode 100644 index 00000000000..54dbf991f99 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,41 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 35U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.h new file mode 100644 index 00000000000..aef4c18422f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define peri_0_div_16_0_ENABLED 1U +#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT +#define peri_0_div_16_0_NUM 0U +#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U +#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U +#define CYBSP_I2C_CLK_DIV_ENABLED 1U +#define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_I2C_CLK_DIV_NUM 1U + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_notices.h new file mode 100644 index 00000000000..90f1013f8a7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 00000000000..3fce96da0b7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,77 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR8_BITS, + .enableWakeFromSleep = false, +}; +const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 12, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +const cy_stc_smif_config_t CYBSP_QSPI_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, + .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, +}; + + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 00000000000..871b62dc66e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,75 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_scb_ezi2c.h" +#include "cy_sysclk.h" +#include "cy_scb_uart.h" +#include "cy_smif.h" +#include "cycfg_qspi_memslot.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_I2C_ENABLED 1U +#define CYBSP_I2C_HW SCB3 +#define CYBSP_I2C_IRQ scb_3_interrupt_IRQn +#define CYBSP_DEBUG_UART_ENABLED 1U +#define CYBSP_DEBUG_UART_HW SCB5 +#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn +#define CYBSP_QSPI_ENABLED 1U +#define CYBSP_QSPI_HW SMIF0 +#define CYBSP_QSPI_IRQ smif_interrupt_IRQn +#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) +#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) +#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) +#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) +#define CYBSP_QSPI_DATALINES0_1 (1UL) +#define CYBSP_QSPI_DATALINES2_3 (1UL) +#define CYBSP_QSPI_DATALINES4_5 (0UL) +#define CYBSP_QSPI_DATALINES6_7 (0UL) +#define CYBSP_QSPI_SS0 (1UL) +#define CYBSP_QSPI_SS1 (0UL) +#define CYBSP_QSPI_SS2 (0UL) +#define CYBSP_QSPI_SS3 (0UL) +#define CYBSP_QSPI_DESELECT_DELAY 7 + +extern const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config; +extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config; +extern const cy_stc_smif_config_t CYBSP_QSPI_config; + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.c new file mode 100644 index 00000000000..18d8b8518ec --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.c @@ -0,0 +1,426 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SW2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SW2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_QSPI_SS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_QSPI_SCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_ECO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_ECO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_USB_DP_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_USB_DM_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_LED4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = ioss_0_port_5_pin_0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = ioss_0_port_5_pin_1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_I2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_I2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = CYBSP_SWCLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_FULL, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); + + Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); + + Cy_GPIO_Pin_Init(CYBSP_SW2_PORT, CYBSP_SW2_PIN, &CYBSP_SW2_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); + + Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); + + Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config); + + Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config); + + Cy_GPIO_Pin_Init(CYBSP_LED3_PORT, CYBSP_LED3_PIN, &CYBSP_LED3_config); + + Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); + + Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); + + Cy_GPIO_Pin_Init(CYBSP_LED4_PORT, CYBSP_LED4_PIN, &CYBSP_LED4_config); + + Cy_GPIO_Pin_Init(ioss_0_port_5_pin_0_PORT, ioss_0_port_5_pin_0_PIN, &ioss_0_port_5_pin_0_config); + + Cy_GPIO_Pin_Init(ioss_0_port_5_pin_1_PORT, ioss_0_port_5_pin_1_PIN, &ioss_0_port_5_pin_1_config); + + Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_PORT, CYBSP_I2C_SCL_PIN, &CYBSP_I2C_SCL_config); + + Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_PORT, CYBSP_I2C_SDA_PIN, &CYBSP_I2C_SDA_config); + + Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); + + Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); + + Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.h new file mode 100644 index 00000000000..d6937cc557f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.h @@ -0,0 +1,326 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#include "cycfg_routing.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_WCO_IN_ENABLED 1U +#define CYBSP_WCO_IN_PORT GPIO_PRT0 +#define CYBSP_WCO_IN_PORT_NUM 0U +#define CYBSP_WCO_IN_PIN 0U +#define CYBSP_WCO_IN_NUM 0U +#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#define CYBSP_WCO_OUT_ENABLED 1U +#define CYBSP_WCO_OUT_PORT GPIO_PRT0 +#define CYBSP_WCO_OUT_PORT_NUM 0U +#define CYBSP_WCO_OUT_PIN 1U +#define CYBSP_WCO_OUT_NUM 1U +#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#define CYBSP_SW2_ENABLED 1U +#define CYBSP_SW2_PORT GPIO_PRT0 +#define CYBSP_SW2_PORT_NUM 0U +#define CYBSP_SW2_PIN 4U +#define CYBSP_SW2_NUM 4U +#define CYBSP_SW2_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SW2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SW2_HSIOM ioss_0_port_0_pin_4_HSIOM +#define CYBSP_SW2_IRQ ioss_interrupts_gpio_0_IRQn +#define CYBSP_QSPI_SS_ENABLED 1U +#define CYBSP_QSPI_SS_PORT GPIO_PRT11 +#define CYBSP_QSPI_SS_PORT_NUM 11U +#define CYBSP_QSPI_SS_PIN 2U +#define CYBSP_QSPI_SS_NUM 2U +#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_2_HSIOM + #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM +#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_D3_ENABLED 1U +#define CYBSP_QSPI_D3_PORT GPIO_PRT11 +#define CYBSP_QSPI_D3_PORT_NUM 11U +#define CYBSP_QSPI_D3_PIN 3U +#define CYBSP_QSPI_D3_NUM 3U +#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_3_HSIOM + #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM +#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_D2_ENABLED 1U +#define CYBSP_QSPI_D2_PORT GPIO_PRT11 +#define CYBSP_QSPI_D2_PORT_NUM 11U +#define CYBSP_QSPI_D2_PIN 4U +#define CYBSP_QSPI_D2_NUM 4U +#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM +#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_D1_ENABLED 1U +#define CYBSP_QSPI_D1_PORT GPIO_PRT11 +#define CYBSP_QSPI_D1_PORT_NUM 11U +#define CYBSP_QSPI_D1_PIN 5U +#define CYBSP_QSPI_D1_NUM 5U +#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_5_HSIOM + #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM +#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_D0_ENABLED 1U +#define CYBSP_QSPI_D0_PORT GPIO_PRT11 +#define CYBSP_QSPI_D0_PORT_NUM 11U +#define CYBSP_QSPI_D0_PIN 6U +#define CYBSP_QSPI_D0_NUM 6U +#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM +#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_QSPI_SCK_ENABLED 1U +#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 +#define CYBSP_QSPI_SCK_PORT_NUM 11U +#define CYBSP_QSPI_SCK_PIN 7U +#define CYBSP_QSPI_SCK_NUM 7U +#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_7_HSIOM + #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM +#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn +#define CYBSP_ECO_IN_ENABLED 1U +#define CYBSP_ECO_IN_PORT GPIO_PRT12 +#define CYBSP_ECO_IN_PORT_NUM 12U +#define CYBSP_ECO_IN_PIN 6U +#define CYBSP_ECO_IN_NUM 6U +#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_ECO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_6_HSIOM + #define ioss_0_port_12_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM +#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn +#define CYBSP_ECO_OUT_ENABLED 1U +#define CYBSP_ECO_OUT_PORT GPIO_PRT12 +#define CYBSP_ECO_OUT_PORT_NUM 12U +#define CYBSP_ECO_OUT_PIN 7U +#define CYBSP_ECO_OUT_NUM 7U +#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_12_pin_7_HSIOM + #define ioss_0_port_12_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM +#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn +#define CYBSP_LED3_ENABLED 1U +#define CYBSP_LED3_PORT GPIO_PRT13 +#define CYBSP_LED3_PORT_NUM 13U +#define CYBSP_LED3_PIN 7U +#define CYBSP_LED3_NUM 7U +#define CYBSP_LED3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_13_pin_7_HSIOM + #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED3_HSIOM ioss_0_port_13_pin_7_HSIOM +#define CYBSP_LED3_IRQ ioss_interrupts_gpio_13_IRQn +#define CYBSP_USB_DP_ENABLED 1U +#define CYBSP_USB_DP_PORT GPIO_PRT14 +#define CYBSP_USB_DP_PORT_NUM 14U +#define CYBSP_USB_DP_PIN 0U +#define CYBSP_USB_DP_NUM 0U +#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DP_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_0_HSIOM + #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM +#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn +#define CYBSP_USB_DM_ENABLED 1U +#define CYBSP_USB_DM_PORT GPIO_PRT14 +#define CYBSP_USB_DM_PORT_NUM 14U +#define CYBSP_USB_DM_PIN 1U +#define CYBSP_USB_DM_NUM 1U +#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DM_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_1_HSIOM + #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM +#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn +#define CYBSP_LED4_ENABLED 1U +#define CYBSP_LED4_PORT GPIO_PRT1 +#define CYBSP_LED4_PORT_NUM 1U +#define CYBSP_LED4_PIN 5U +#define CYBSP_LED4_NUM 5U +#define CYBSP_LED4_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_5_HSIOM + #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED4_HSIOM ioss_0_port_1_pin_5_HSIOM +#define CYBSP_LED4_IRQ ioss_interrupts_gpio_1_IRQn +#define ioss_0_port_5_pin_0_ENABLED 1U +#define ioss_0_port_5_pin_0_PORT GPIO_PRT5 +#define ioss_0_port_5_pin_0_PORT_NUM 5U +#define ioss_0_port_5_pin_0_PIN 0U +#define ioss_0_port_5_pin_0_NUM 0U +#define ioss_0_port_5_pin_0_DRIVEMODE CY_GPIO_DM_HIGHZ +#define ioss_0_port_5_pin_0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_0_HSIOM + #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_5_pin_0_IRQ ioss_interrupts_gpio_5_IRQn +#define ioss_0_port_5_pin_1_ENABLED 1U +#define ioss_0_port_5_pin_1_PORT GPIO_PRT5 +#define ioss_0_port_5_pin_1_PORT_NUM 5U +#define ioss_0_port_5_pin_1_PIN 1U +#define ioss_0_port_5_pin_1_NUM 1U +#define ioss_0_port_5_pin_1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define ioss_0_port_5_pin_1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_1_HSIOM + #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define ioss_0_port_5_pin_1_IRQ ioss_interrupts_gpio_5_IRQn +#define CYBSP_I2C_SCL_ENABLED 1U +#define CYBSP_I2C_SCL_PORT GPIO_PRT6 +#define CYBSP_I2C_SCL_PORT_NUM 6U +#define CYBSP_I2C_SCL_PIN 0U +#define CYBSP_I2C_SCL_NUM 0U +#define CYBSP_I2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_I2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_0_HSIOM + #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM +#define CYBSP_I2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_I2C_SDA_ENABLED 1U +#define CYBSP_I2C_SDA_PORT GPIO_PRT6 +#define CYBSP_I2C_SDA_PORT_NUM 6U +#define CYBSP_I2C_SDA_PIN 1U +#define CYBSP_I2C_SDA_NUM 1U +#define CYBSP_I2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_I2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_1_HSIOM + #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM +#define CYBSP_I2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_SWO_ENABLED 1U +#define CYBSP_SWO_PORT GPIO_PRT6 +#define CYBSP_SWO_PIN 4U +#define CYBSP_SWO_NUM 4U +#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_SWDIO_ENABLED 1U +#define CYBSP_SWDIO_PORT GPIO_PRT6 +#define CYBSP_SWDIO_PIN 6U +#define CYBSP_SWDIO_NUM 6U +#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#define CYBSP_SWCLK_ENABLED 1U +#define CYBSP_SWCLK_PORT GPIO_PRT6 +#define CYBSP_SWCLK_PIN 7U +#define CYBSP_SWCLK_NUM 7U +#define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define CYBSP_SWCLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn + +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SW2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config; +extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config; +extern const cy_stc_gpio_pin_config_t CYBSP_LED3_config; +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; +extern const cy_stc_gpio_pin_config_t CYBSP_LED4_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_0_config; +extern const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config; +extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config; + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.c new file mode 100644 index 00000000000..d430d4908fd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.c @@ -0,0 +1,265 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.c +* +* Description: +* Provides definitions of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_qspi_memslot.h" + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xEBU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_QUAD, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0x01U, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 4U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x06U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x04U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x20U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x60U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x38U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x35U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x05U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x01U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0 = +{ + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x03U, + /* The size of the memory. */ + .memSize = 0x1000000U, + /* Specifies the Read command. */ + .readCmd = &S25FL128S_SlaveSlot_0_readCmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = &S25FL128S_SlaveSlot_0_writeEnCmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = &S25FL128S_SlaveSlot_0_writeDisCmd, + /* Specifies the Erase command. */ + .eraseCmd = &S25FL128S_SlaveSlot_0_eraseCmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x0001000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = &S25FL128S_SlaveSlot_0_chipEraseCmd, + /* Specifies the Program command. */ + .programCmd = &S25FL128S_SlaveSlot_0_programCmd, + /* Specifies the page size for programming. */ + .programSize = 0x0000200U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = &S25FL128S_SlaveSlot_0_readStsRegQeCmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = &S25FL128S_SlaveSlot_0_readStsRegWipCmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = &S25FL128S_SlaveSlot_0_writeStsRegQeCmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x01U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x02U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 140U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 40000U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 250U +}; + +cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 = +{ + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_0, + /* Flags. */ + .flags = CY_SMIF_FLAG_WR_EN, + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave is mapped to in the PSoC memory map. + Valid when the memory-mapped mode is enabled. */ + .baseAddress = 0x18000000U, + /* The size allocated in the PSoC memory map, for the memory slave device. + The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ + .memMappedSize = 0x10000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + Valid when the memory mapped mode is enabled. */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = &deviceCfg_S25FL128S_SlaveSlot_0 +}; + +cy_stc_smif_mem_config_t* smifMemConfigs[] = { + &S25FL128S_SlaveSlot_0 +}; + +cy_stc_smif_block_config_t smifBlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR +}; + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.h new file mode 100644 index 00000000000..116f1e52042 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.h @@ -0,0 +1,50 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.h +* +* Description: +* Provides declarations of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#ifndef CYCFG_QSPI_MEMSLOT_H +#define CYCFG_QSPI_MEMSLOT_H +#include "cy_smif_memslot.h" + +#define CY_SMIF_DEVICE_NUM 1 + +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd; +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd; +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd; +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd; +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd; +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd; +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd; +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd; +extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd; + +extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0; + +extern cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0; +extern cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM]; + +extern cy_stc_smif_block_config_t smifBlockConfig; + + +#endif /*CY_SMIF_MEMCONFIG_H*/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.c new file mode 100644 index 00000000000..095e0b0b975 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.c @@ -0,0 +1,29 @@ +/******************************************************************************* +* File Name: cycfg_routing.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_routing.h" + +void init_cycfg_routing(void) +{ +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.h new file mode 100644 index 00000000000..eff29bf6931 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.h @@ -0,0 +1,56 @@ +/******************************************************************************* +* File Name: cycfg_routing.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() +#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN +#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT +#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 +#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 +#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 +#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 +#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 +#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK +#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX +#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX +#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL +#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.c new file mode 100644 index 00000000000..42eb4f6cba9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.c @@ -0,0 +1,475 @@ +/******************************************************************************* +* File Name: cycfg_system.c +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_system.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_INIT 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP +#define CY_CFG_PWR_USING_ULP 0 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init() +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init() +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init() +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init() +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(1U); +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} +__STATIC_INLINE void init_cycfg_power(void) +{ + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #else /* Dedicated Supply */ + Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + /* Configure core regulator */ + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); + Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); + #endif /* CY_CFG_PWR_USING_LDO */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */ +} + + +void init_cycfg_system(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #ifdef CY_CFG_SYSCLK_MFO_ENABLED + Cy_SysClk_MfoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED + Cy_SysClk_ClkMfInit(); + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.h new file mode 100644 index 00000000000..cc47de73c76 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.h @@ -0,0 +1,82 @@ +/******************************************************************************* +* File Name: cycfg_system.h +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dap_0_ENABLED 1U +#define srss_0_clock_0_ENABLED 1U +#define srss_0_clock_0_bakclk_0_ENABLED 1U +#define srss_0_clock_0_fastclk_0_ENABLED 1U +#define srss_0_clock_0_fll_0_ENABLED 1U +#define srss_0_clock_0_hfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF0 0UL +#define srss_0_clock_0_hfclk_2_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF2 2UL +#define srss_0_clock_0_ilo_0_ENABLED 1U +#define srss_0_clock_0_imo_0_ENABLED 1U +#define srss_0_clock_0_lfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define srss_0_clock_0_pathmux_0_ENABLED 1U +#define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_pathmux_2_ENABLED 1U +#define srss_0_clock_0_pathmux_3_ENABLED 1U +#define srss_0_clock_0_pathmux_4_ENABLED 1U +#define srss_0_clock_0_periclk_0_ENABLED 1U +#define srss_0_clock_0_slowclk_0_ENABLED 1U +#define srss_0_clock_0_wco_0_ENABLED 1U +#define srss_0_power_0_ENABLED 1U +#define CY_CFG_PWR_MODE_LP 0x01UL +#define CY_CFG_PWR_MODE_ULP 0x02UL +#define CY_CFG_PWR_MODE_ACTIVE 0x04UL +#define CY_CFG_PWR_MODE_SLEEP 0x08UL +#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL +#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP +#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP +#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +void init_cycfg_system(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralNames.h new file mode 100644 index 00000000000..d2b32d667e8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralNames.h @@ -0,0 +1,117 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)SCB0_BASE, + UART_1 = (int)SCB1_BASE, + UART_2 = (int)SCB2_BASE, + UART_3 = (int)SCB3_BASE, + UART_4 = (int)SCB4_BASE, + UART_5 = (int)SCB5_BASE, + UART_6 = (int)SCB6_BASE, + UART_7 = (int)SCB7_BASE, +} UARTName; + + +typedef enum { + SPI_0 = (int)SCB0_BASE, + SPI_1 = (int)SCB1_BASE, + SPI_2 = (int)SCB2_BASE, + SPI_3 = (int)SCB3_BASE, + SPI_4 = (int)SCB4_BASE, + SPI_5 = (int)SCB5_BASE, + SPI_6 = (int)SCB6_BASE, + SPI_7 = (int)SCB7_BASE, + SPI_8 = (int)SCB8_BASE, +} SPIName; + +typedef enum { + I2C_0 = (int)SCB0_BASE, + I2C_1 = (int)SCB1_BASE, + I2C_2 = (int)SCB2_BASE, + I2C_3 = (int)SCB3_BASE, + I2C_4 = (int)SCB4_BASE, + I2C_5 = (int)SCB5_BASE, + I2C_6 = (int)SCB6_BASE, + I2C_7 = (int)SCB7_BASE, + I2C_8 = (int)SCB8_BASE, +} I2CName; + +typedef enum { + PWM_32b_0 = TCPWM0_BASE, + PWM_32b_1, + PWM_32b_2, + PWM_32b_3, + PWM_32b_4, + PWM_32b_5, + PWM_32b_6, + PWM_32b_7, + PWM_16b_0 = TCPWM1_BASE, + PWM_16b_1, + PWM_16b_2, + PWM_16b_3, + PWM_16b_4, + PWM_16b_5, + PWM_16b_6, + PWM_16b_7, + PWM_16b_8, + PWM_16b_9, + PWM_16b_10, + PWM_16b_11, + PWM_16b_12, + PWM_16b_13, + PWM_16b_14, + PWM_16b_15, + PWM_16b_16, + PWM_16b_17, + PWM_16b_18, + PWM_16b_19, + PWM_16b_20, + PWM_16b_21, + PWM_16b_22, + PWM_16b_23, +} PWMName; + +typedef enum { + ADC_0 = (int)SAR_BASE, +} ADCName; + +typedef enum { + DAC_0 = (int)CTDAC0_BASE, +} DACName; + +typedef enum { + SMIF_0 = (int)SMIF0_BASE, +} SMIFName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c new file mode 100644 index 00000000000..cfd1be0c795 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c @@ -0,0 +1,465 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +#if DEVICE_SERIAL +//*** SERIAL *** +const PinMap PinMap_UART_RX[] = { + {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION( P0_2_SCB0_UART_RX)}, + {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION( P1_0_SCB7_UART_RX)}, + {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION( P2_0_SCB1_UART_RX)}, + {P3_0, UART_2, CYHAL_PIN_IN_FUNCTION( P3_0_SCB2_UART_RX)}, + {P4_0, UART_7, CYHAL_PIN_IN_FUNCTION( P4_0_SCB7_UART_RX)}, + {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION( P5_0_SCB5_UART_RX)}, + {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION( P6_0_SCB3_UART_RX)}, + {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION( P6_4_SCB6_UART_RX)}, + {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION( P7_0_SCB4_UART_RX)}, + {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION( P8_0_SCB4_UART_RX)}, + {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION( P9_0_SCB2_UART_RX)}, + {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION( P10_0_SCB1_UART_RX)}, + {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION( P11_0_SCB5_UART_RX)}, + {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION( P12_0_SCB6_UART_RX)}, + {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION( P13_0_SCB6_UART_RX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_TX[] = { + {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION( P0_3_SCB0_UART_TX)}, + {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION( P1_1_SCB7_UART_TX)}, + {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION( P2_1_SCB1_UART_TX)}, + {P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION( P3_1_SCB2_UART_TX)}, + {P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION( P4_1_SCB7_UART_TX)}, + {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION( P5_1_SCB5_UART_TX)}, + {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION( P6_1_SCB3_UART_TX)}, + {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION( P6_5_SCB6_UART_TX)}, + {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION( P7_1_SCB4_UART_TX)}, + {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION( P8_1_SCB4_UART_TX)}, + {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION( P9_1_SCB2_UART_TX)}, + {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION( P10_1_SCB1_UART_TX)}, + {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION( P11_1_SCB5_UART_TX)}, + {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION( P12_1_SCB6_UART_TX)}, + {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION( P13_1_SCB6_UART_TX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_RTS[] = { + {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION( P0_4_SCB0_UART_RTS)}, + {P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION( P1_2_SCB7_UART_RTS)}, + {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION( P2_2_SCB1_UART_RTS)}, + {P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION( P3_2_SCB2_UART_RTS)}, + {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION( P5_2_SCB5_UART_RTS)}, + {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION( P6_2_SCB3_UART_RTS)}, + {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION( P6_6_SCB6_UART_RTS)}, + {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION( P7_2_SCB4_UART_RTS)}, + {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION( P8_2_SCB4_UART_RTS)}, + {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION( P9_2_SCB2_UART_RTS)}, + {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION( P10_2_SCB1_UART_RTS)}, + {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION( P11_2_SCB5_UART_RTS)}, + {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION( P12_2_SCB6_UART_RTS)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_CTS[] = { + {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION( P0_5_SCB0_UART_CTS)}, + {P1_3, UART_7, CYHAL_PIN_IN_FUNCTION( P1_3_SCB7_UART_CTS)}, + {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION( P2_3_SCB1_UART_CTS)}, + {P3_3, UART_2, CYHAL_PIN_IN_FUNCTION( P3_3_SCB2_UART_CTS)}, + {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION( P5_3_SCB5_UART_CTS)}, + {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION( P6_3_SCB3_UART_CTS)}, + {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION( P6_7_SCB6_UART_CTS)}, + {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION( P7_3_SCB4_UART_CTS)}, + {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION( P8_3_SCB4_UART_CTS)}, + {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION( P9_3_SCB2_UART_CTS)}, + {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION( P10_3_SCB1_UART_CTS)}, + {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION( P11_3_SCB5_UART_CTS)}, + {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION( P12_3_SCB6_UART_CTS)}, + {NC, NC, 0} +}; +#endif // DEVICE_SERIAL + + +#if DEVICE_I2C +//*** I2C *** +const PinMap PinMap_I2C_SCL[] = { + {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION( P0_2_SCB0_I2C_SCL)}, + {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION( P1_0_SCB7_I2C_SCL)}, + {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION( P2_0_SCB1_I2C_SCL)}, + {P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION( P3_0_SCB2_I2C_SCL)}, + {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION( P4_0_SCB7_I2C_SCL)}, + {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION( P5_0_SCB5_I2C_SCL)}, + {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION( P6_0_SCB3_I2C_SCL)}, + {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION( P6_4_SCB6_I2C_SCL)}, + {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION( P7_0_SCB4_I2C_SCL)}, + {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION( P8_0_SCB4_I2C_SCL)}, + {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION( P9_0_SCB2_I2C_SCL)}, + {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION( P10_0_SCB1_I2C_SCL)}, + {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION( P11_0_SCB5_I2C_SCL)}, + {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION( P12_0_SCB6_I2C_SCL)}, + {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION( P13_0_SCB6_I2C_SCL)}, + {NC, NC, 0} +}; +const PinMap PinMap_I2C_SDA[] = { + {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION( P0_3_SCB0_I2C_SDA)}, + {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION( P1_1_SCB7_I2C_SDA)}, + {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION( P2_1_SCB1_I2C_SDA)}, + {P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION( P3_1_SCB2_I2C_SDA)}, + {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION( P4_1_SCB7_I2C_SDA)}, + {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION( P5_1_SCB5_I2C_SDA)}, + {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION( P6_1_SCB3_I2C_SDA)}, + {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION( P6_5_SCB6_I2C_SDA)}, + {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION( P7_1_SCB4_I2C_SDA)}, + {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION( P8_1_SCB4_I2C_SDA)}, + {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION( P9_1_SCB2_I2C_SDA)}, + {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION( P10_1_SCB1_I2C_SDA)}, + {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION( P11_1_SCB5_I2C_SDA)}, + {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION( P12_1_SCB6_I2C_SDA)}, + {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION( P13_1_SCB6_I2C_SDA)}, + {NC, NC, 0} +}; +#endif // DEVICE_I2C + +#if DEVICE_SPI +//*** SPI *** +const PinMap PinMap_SPI_MOSI[] = { + {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_2_SCB0_SPI_MOSI)}, + {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_0_SCB7_SPI_MOSI)}, + {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_0_SCB1_SPI_MOSI)}, + {P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_0_SCB2_SPI_MOSI)}, + {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION( P4_0_SCB7_SPI_MOSI)}, + {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_0_SCB5_SPI_MOSI)}, + {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_0_SCB3_SPI_MOSI)}, + {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_4_SCB6_SPI_MOSI)}, + {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_0_SCB4_SPI_MOSI)}, + {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_0_SCB4_SPI_MOSI)}, + {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_0_SCB2_SPI_MOSI)}, + {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_0_SCB1_SPI_MOSI)}, + {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_0_SCB5_SPI_MOSI)}, + {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_0_SCB6_SPI_MOSI)}, + {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION( P13_0_SCB6_SPI_MOSI)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_MISO[] = { + {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION( P0_3_SCB0_SPI_MISO)}, + {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION( P1_1_SCB7_SPI_MISO)}, + {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION( P2_1_SCB1_SPI_MISO)}, + {P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION( P3_1_SCB2_SPI_MISO)}, + {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION( P4_1_SCB7_SPI_MISO)}, + {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION( P5_1_SCB5_SPI_MISO)}, + {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION( P6_1_SCB3_SPI_MISO)}, + {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION( P6_5_SCB6_SPI_MISO)}, + {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION( P7_1_SCB4_SPI_MISO)}, + {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION( P8_1_SCB4_SPI_MISO)}, + {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION( P9_1_SCB2_SPI_MISO)}, + {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION( P10_1_SCB1_SPI_MISO)}, + {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION( P11_1_SCB5_SPI_MISO)}, + {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION( P12_1_SCB6_SPI_MISO)}, + {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION( P13_1_SCB6_SPI_MISO)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SCLK[] = { + {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_4_SCB0_SPI_CLK)}, + {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_2_SCB7_SPI_CLK)}, + {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_2_SCB1_SPI_CLK)}, + {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_2_SCB2_SPI_CLK)}, + {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_2_SCB5_SPI_CLK)}, + {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_2_SCB3_SPI_CLK)}, + {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_6_SCB6_SPI_CLK)}, + {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_2_SCB4_SPI_CLK)}, + {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_2_SCB4_SPI_CLK)}, + {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_2_SCB2_SPI_CLK)}, + {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_2_SCB1_SPI_CLK)}, + {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_2_SCB5_SPI_CLK)}, + {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_2_SCB6_SPI_CLK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SSEL[] = { + {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_5_SCB0_SPI_SELECT0)}, + {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_3_SCB7_SPI_SELECT0)}, + {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_3_SCB1_SPI_SELECT0)}, + {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_3_SCB2_SPI_SELECT0)}, + {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_3_SCB5_SPI_SELECT0)}, + {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_3_SCB3_SPI_SELECT0)}, + {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_7_SCB6_SPI_SELECT0)}, + {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_3_SCB4_SPI_SELECT0)}, + {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_3_SCB4_SPI_SELECT0)}, + {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_3_SCB2_SPI_SELECT0)}, + {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_3_SCB1_SPI_SELECT0)}, + {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_3_SCB5_SPI_SELECT0)}, + {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_3_SCB6_SPI_SELECT0)}, + {NC, NC, 0} +}; +#endif // DEVICE_SPI + +#if DEVICE_PWMOUT +//*** PWM *** +const PinMap PinMap_PWM_OUT[] = { + // 16-bit PWM outputs + {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, + {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)}, + {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, + {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)}, + {P1_2, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)}, + {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)}, + {P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)}, + {P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)}, + {P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)}, + {P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)}, + {P3_0, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM1_LINE19)}, + {P3_2, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM1_LINE20)}, + {P3_4, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM1_LINE21)}, + {P4_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM1_LINE22)}, + {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, + {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, + {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, + {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, + {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)}, + {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, + {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, + {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, + {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)}, + {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, + {P7_4, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)}, + {P7_6, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)}, + {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)}, + {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)}, + {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)}, + {P8_6, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)}, + {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, + {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, + {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, + {P9_6, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)}, + {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, + {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, + {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, + {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, + {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)}, + {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)}, + {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)}, + {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)}, + {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)}, + {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)}, + {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, + {P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)}, + {P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)}, + {P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)}, + {P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)}, + // 16-bit PWM inverted outputs + {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, + {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)}, + {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, + {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)}, + {P1_3, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)}, + {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)}, + {P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)}, + {P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)}, + {P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)}, + {P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)}, + {P3_1, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM1_LINE_COMPL19)}, + {P3_3, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM1_LINE_COMPL20)}, + {P3_5, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM1_LINE_COMPL21)}, + {P4_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM1_LINE_COMPL22)}, + {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, + {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, + {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, + {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)}, + {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)}, + {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, + {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, + {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, + {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, + {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)}, + {P7_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)}, + {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, + {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)}, + {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)}, + {P8_5, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)}, + {P8_7, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)}, + {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, + {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, + {P9_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)}, + {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)}, + {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, + {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, + {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, + {P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)}, + {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)}, + {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)}, + {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)}, + {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)}, + {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)}, + {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)}, + {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, + {P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)}, + {P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)}, + {P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)}, + {P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)}, + // 32-bit PWM outputs + {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, + {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)}, + {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, + {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)}, + {P1_2, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)}, + {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)}, + {P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)}, + {P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)}, + {P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)}, + {P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)}, + {P3_0, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM0_LINE2)}, + {P3_2, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM0_LINE3)}, + {P3_4, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM0_LINE4)}, + {P4_0, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM0_LINE5)}, + {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, + {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, + {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, + {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, + {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)}, + {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, + {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, + {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, + {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)}, + {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, + {P7_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)}, + {P7_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)}, + {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)}, + {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)}, + {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)}, + {P8_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)}, + {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, + {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, + {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, + {P9_6, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)}, + {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, + {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, + {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, + {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, + {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)}, + {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)}, + {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)}, + {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)}, + {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)}, + {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)}, + {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, + {P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)}, + {P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)}, + {P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)}, + {P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)}, + // 32-bit PWM inverted outputs + {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, + {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)}, + {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, + {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)}, + {P1_3, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)}, + {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)}, + {P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)}, + {P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)}, + {P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)}, + {P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)}, + {P3_1, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM0_LINE_COMPL2)}, + {P3_3, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM0_LINE_COMPL3)}, + {P3_5, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM0_LINE_COMPL4)}, + {P4_1, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM0_LINE_COMPL5)}, + {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, + {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, + {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, + {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)}, + {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)}, + {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, + {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, + {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, + {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, + {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)}, + {P7_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)}, + {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, + {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)}, + {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)}, + {P8_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)}, + {P8_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)}, + {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, + {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, + {P9_5, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)}, + {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)}, + {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, + {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, + {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, + {P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)}, + {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)}, + {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)}, + {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)}, + {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)}, + {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)}, + {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)}, + {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, + {P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)}, + {P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)}, + {P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)}, + {P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)}, + {NC, NC, 0} +}; +#endif // DEVICE_PWMOUT + +#if DEVICE_ANALOGIN +const PinMap PinMap_ADC[] = { + {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_ANALOGOUT +const PinMap PinMap_DAC[] = { + {P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_CTDAC)}, + {P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)}, // CTDAC connects to the P10_5 pin through the AMUXA bus + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_QSPI +const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2 + {P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)}, + {NC, NC, 0} +}; + +// Ensure that the spi_data pins are defined in the order 0 to 7 +const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2 + {P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0 + {P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1 + {P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2 + {P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3 + {P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4 + {P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5 + {P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6 + {P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7 + {NC, NC, 0} +}; + +// Ensure that the spi_select pins are defined in the order 0 to 3 +const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2 + {P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0 + {P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1 + {P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2 + {P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3 + {NC, NC, 0} +}; +#endif // DEVICE_QSPI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PinNames.h new file mode 100644 index 00000000000..faacf57baf1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PinNames.h @@ -0,0 +1,135 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" +#include "PortNames.h" +#include "cyhal_pin_package.h" +#include "cyhal_utils.h" + +typedef cyhal_gpio_t PinName; + +// Arduino connector namings +#define A0 P10_0 +#define A1 P10_1 +#define A2 P10_2 +#define A3 P10_3 +#define A4 P10_4 +#define A5 P10_5 + +#define D0 P5_0 +#define D1 P5_1 +#define D2 P5_2 +#define D3 P5_3 +#define D4 P5_4 +#define D5 P5_5 +#define D6 P5_6 +#define D7 P0_2 +#define D8 P13_0 +#define D9 P13_1 +#define D10 P12_3 +#define D11 P12_0 +#define D12 P12_1 +#define D13 P12_2 +#define D14 P6_1 +#define D15 P6_0 + + // Generic signal names + +#define I2C_SCL P6_0 +#define I2C_SDA P6_1 + +#define SPI_MOSI P12_0 +#define SPI_MISO P12_1 +#define SPI_CLK P12_2 +#define SPI_CS P12_4 + +#define UART_RX P5_0 +#define UART_TX P5_1 +#define UART_RTS P5_2 +#define UART_CTS P5_3 + + // Reset pin unavailable + + +#define SWITCH2 P0_4 +#define LED1 P13_7 +#define LED2 P1_5 + +#define LED_RED LED1 +#define LED_GREEN LED2 + +#define USER_BUTTON SWITCH2 +#define BUTTON1 USER_BUTTON + +#define QSPI_CLK P11_7 +#define QSPI_IO_0 P11_6 +#define QSPI_IO_1 P11_5 +#define QSPI_IO_2 P11_4 +#define QSPI_IO_3 P11_3 +#define QSPI_SEL P11_2 + + // Standardized interfaces names +#define STDIO_UART_TX UART_TX +#define STDIO_UART_RX UART_RX +#define STDIO_UART_CTS UART_CTS +#define STDIO_UART_RTS UART_RTS + +#define CY_STDIO_UART_RX STDIO_UART_RX +#define CY_STDIO_UART_TX STDIO_UART_TX +#define CY_STDIO_UART_CTS STDIO_UART_CTS +#define CY_STDIO_UART_RTS STDIO_UART_RTS + +#define CY_BT_UART_RX BT_UART_RX +#define CY_BT_UART_TX BT_UART_TX +#define CY_BT_UART_CTS BT_UART_CTS +#define CY_BT_UART_RTS BT_UART_RTS + +#define CY_BT_PIN_POWER BT_PIN_POWER +#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE +#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE + + +#define USBTX UART_TX +#define USBRX UART_RX + +#define AOUT P9_6 + +// PinName[15-0] = Port[15-8] + Pin[4-0] +static inline unsigned CY_PIN(PinName pin) +{ + return pin & 0x07; +} + +static inline unsigned CY_PORT(PinName pin) +{ + return (pin >> 8) & 0xFF; +} + +// Because MBED pin mapping API does not allow to map multiple instances of the PWM +// to be mapped to the same pin, we create special pin names to force 32-bit PWM unit +// usage instead of standard 16-bit PWM. + +#define PWM32(pin) CY_PIN_FORCE_PWM_32(pin) + + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.c new file mode 100644 index 00000000000..179bcc28cad --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.c @@ -0,0 +1,54 @@ +/***************************************************************************//** +* \file cybsp_cy8cproto_064_sb.c +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CPROTO-064-SB pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +//#include "cybsp_retarget.h" +#include "cybsp_cy8cproto_064_sb.h" +#include "cycfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +cy_rslt_t cybsp_init(void) +{ + init_cycfg_system(); + cy_rslt_t result = cybsp_led_init(CYBSP_USER_LED1); + result |= cybsp_led_init(CYBSP_USER_LED2); + result |= cybsp_btn_init(CYBSP_USER_BTN1); + +#if defined(CYBSP_RETARGET_ENABLED) + /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_retarget_init(); + } +#endif + + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.h new file mode 100644 index 00000000000..626a5fb73f9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.h @@ -0,0 +1,74 @@ +/***************************************************************************//** +* \file cybsp_cy8cproto_064_sb.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CPROTO-064-SB pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8cproto_064_sb CY8CPROTO-064-SB +* \ingroup group_bsp +* \{ +* CY8CPROTO-064-SB PSoC 64 SecureBoot Prototyping Kit is a low-cost Prototyping +* Kit based on PSoC 64 SecureBoot MCU to enable customers to prototype and +* design with the PSoC 64 SecureBoot device. +* +*
Kit Features:
+* +* +*
Kit Contents:
+* +* +* \defgroup group_bsp_cy8cproto_064_sb_macros Macros +* \defgroup group_bsp_cy8cproto_064_sb_functions Functions +* \defgroup group_bsp_cy8cproto_064_sb_enums Enumerated Types +*/ + +#pragma once + +#include +#include +#include "cybsp_api_core.h" +#include "cybsp_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \cond INTERNAL */ + +// TODO: add BSP pin mappings + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8cproto_064_sb */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h new file mode 100644 index 00000000000..553088655f8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h @@ -0,0 +1,157 @@ +/***************************************************************************//** +* \file CY8CPROTO-064-SB/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CPROTO-064-SB kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_bsp_cy8cproto_064_sb CY8CPROTO-064-SB +* \ingroup group_bsp +* \{ +* \defgroup group_bsp_cy8cproto_064_sb_macros Macros +* \defgroup group_bsp_cy8cproto_064_sb_enums Enumerated Types +*/ + +#pragma once + +#include "cyhal.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_cy8cproto_064_sb_macros +* \{ +*/ + +/* Board components mapping */ +/** Pin: LED3 in the CY8CPROTO-064-SB board */ +#define CYBSP_LED3 P13_7 +/** Pin: LED4 in the CY8CPROTO-064-SB board */ +#define CYBSP_LED4 P1_5 +/** Pin: SW2 in the CY8CPROTO-064-SB board */ +#define CYBSP_SW2 P0_4 + +/* Board peripheral count */ +/** Macro: Number of LEDs on CY8CPROTO-064-SB board */ +#define CYBSP_LED_COUNT 2 +/** Macro: Number of buttons on CY8CPROTO-064-SB board */ +#define CYBSP_BTN_COUNT 1 + +/* Generic signal names */ +/** Pin: WCO input */ +#define CYBSP_WCO_IN P0_0 +/** Pin: WCO output */ +#define CYBSP_WCO_OUT P0_1 + +/** Pin: ECO input */ +#define CYBSP_ECO_IN P12_6 +/** Pin: ECO output */ +#define CYBSP_ECO_OUT P12_7 + +/** Pin: UART RX */ +#define CYBSP_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_UART_TX P5_1 + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX P5_1 + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL P6_0 +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA P6_1 + +/** Pin: SWDIO */ +#define CYBSP_SWDIO P6_6 +/** Pin: SWDCK */ +#define CYBSP_SWDCK P6_7 +/** Pin: SWO */ +#define CYBSP_SWO P6_4 + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS P11_2 +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 P11_3 +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 P11_4 +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 P11_5 +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 P11_6 +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK P11_7 + +/** Pin: USB Device D+ */ +#define CYBSP_USB_DP P14_0 +/** Pin: USB Device D- */ +#define CYBSP_USB_DM P14_1 + +/** \} group_bsp_cy8cproto_064_sb_macros */ + +/** +* \addtogroup group_bsp_cy8cproto_064_sb_enums +* \{ +*/ + +/** Enum defining the different states for the LED. */ +typedef enum +{ + CYBSP_LED_STATE_ON = 0, + CYBSP_LED_STATE_OFF = 1, +} cybsp_led_state_t; + +/** Enum defining the different states for a button. */ +typedef enum +{ + CYBSP_BTN_PRESSED = 0, + CYBSP_BTN_OFF = 1, +} cybsp_btn_state_t; + +/** Enum defining the different LED pins on the board. */ +typedef enum +{ + CYBSP_LED_RED = CYBSP_LED3, + CYBSP_LED_GREEN = CYBSP_LED4, + + CYBSP_USER_LED = CYBSP_LED_RED, + CYBSP_USER_LED1 = CYBSP_LED_RED, + CYBSP_USER_LED2 = CYBSP_LED_GREEN, +} cybsp_led_t; + +/** Enum defining the different button pins on the board. */ +typedef enum +{ + CYBSP_USER_BTN = CYBSP_SW2, + CYBSP_USER_BTN1 = CYBSP_SW2, +} cybsp_btn_t; + +/** \} group_bsp_cy8cproto_064_sb_enums */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_bsp_cy8cproto_064_sb */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cycfg_qspi_memslot.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cycfg_qspi_memslot.cyqspi new file mode 100644 index 00000000000..3b668965d30 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cycfg_qspi_memslot.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL128S + false + None + 0x18000000 + 0x10000 + 0x1800FFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL128S + false + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/design.modus new file mode 100644 index 00000000000..8efc4fa4c1e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/design.modus @@ -0,0 +1,468 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct new file mode 100644 index 00000000000..6d3b172fedd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -0,0 +1,314 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cyb06xx7_cm4_dual.sct +;* \version 2.50 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000400 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_START +;* is equal to MBED_ROM_START +;* +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x000CFC00 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. Without bootloader the MBED_APP_SIZE +;* is equal to MBED_ROM_SIZE +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001E000 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Size and start address of the Cortex-M0+ application image +#define FLASH_CM0P_SIZE 0x40000 +#define FLASH_CM0P_START (FLASH_START + FLASH_SIZE - FLASH_CM0P_SIZE) + +; Size and start address of the Cortex-M4 application image +#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE) +#define FLASH_CM4_START FLASH_START + + +; Cortex-M0+ application image +LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application image +LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..023ea2184dc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,643 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$Base| +__Vectors DCD |Image$$ARM_LIB_STACK$$Base| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld new file mode 100644 index 00000000000..913663190b0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -0,0 +1,464 @@ +/***************************************************************************//** +* \file cyb06xx7_cm4_dual.ld +* \version 2.50 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000400 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_START +* is equal to MBED_ROM_START +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x000CFC00 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. Without bootloader the MBED_APP_SIZE +* is equal to MBED_ROM_SIZE +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x0001E000 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Size and start address of the Cortex-M0+ application image */ +FLASH_CM0P_SIZE = 0x40000; +FLASH_CM0P_START = ORIGIN(flash) + LENGTH(flash) - FLASH_CM0P_SIZE; +/* Size and start address of the Cortex-M4 application image */ +FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE; +FLASH_CM4_START = ORIGIN(flash); + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application image */ + .cy_m0p_image FLASH_CM0P_START : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Cortex-M4 application image */ + .text FLASH_CM4_START : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..3c2f44d1e07 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,631 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf new file mode 100644 index 00000000000..3c0902869da --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf @@ -0,0 +1,271 @@ +/***************************************************************************//** +* \file cyb06xx7_cm4_dual.icf +* \version 2.50 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000400; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x000CFC00; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x0001E000; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash */ +place at start of IROM1_region { block RO }; +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..75747c4face --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -0,0 +1,1141 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c new file mode 100644 index 00000000000..a5408385ee6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c @@ -0,0 +1,552 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.50 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if ((rootPath == 1UL) || (rootPath == 2UL)) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h new file mode 100644 index 00000000000..53bc71262c6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h @@ -0,0 +1,675 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.50 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/psoc6_static_srm.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/psoc6_static_srm.h new file mode 100644 index 00000000000..f265e20da70 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/psoc6_static_srm.h @@ -0,0 +1,85 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + + */ + +/* + * This file defines hardware resources reserved by device-generated code. These + * resources are accessed directly by the Peripheral Driver library (PDL). + * + * There are four classes of resources that must be declared here: + * 1 CYCFG_ASSIGNED_PORTS macro defines which ports and pins are reserved. + * You define these as a colon separated list of ports and pins reserved + * using macro SRM_PORT(port_num, pins), once for each reserved port. + * SRM_PORT macro arguments are port number (in the range 0 ... 14) and + * pins, which is a hex value with a bit set for each reserved pin on a port. + * + * 2 CYCFG_ASSIGNED_DIVIDERS macro defines which clock dividers are reserved. + * You define these as a colon separated list of dividers reserved + * using macro SRM_DIVIDER(type, reservations), once for each required + * divider type. + * SRM_DIVIDER arguments are divider type (one of cy_en_divider_types_t + * values) and reservations, which is a hex mask value with a bit set for + * each reserved divider of a given type. + * + * 3 CYCFG_ASSIGNED_SCBS macro defines which SCB blocks are reserved. + * You define these as a colon separated list of SCBs reserved using + * macro SRM_SCB(n), which argument is SCB number in a range 0 ... 7. + * + * 4 CYCFG_ASSIGNED_TCPWM macro defines which TCPWM blocks are reserved. + * You define these as a colon separated list of TCPWMs reserved using + * macro SRM_TCPWM(n), which argument is TCPWM number in a range 0 ... 31. + * + * Examples: + * #define CYCFG_ASSIGNED_PORTS SRM_PORT(0, 0x30), SRM_PORT(5, 0x03) + * + * #define CYCFG_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01) + * + * #define CYCFG_ASSIGNED_SCBS SRM_SCB(2) + * + * #define CYCFG_ASSIGNED_TCPWMS + * + */ + +/* P0_0 and P0_1 reserved for WCO, +* P1_0 reserved for CSD TX, +* P2_0 ... P2_5 reserved for SDHC +* P6-4, P6-6 and P6_7 reserved for SWD, +* P7_1, P7_2 and P7_7 reserved for CSD Capacitors +* P8_1 ... P8_7 reserved for CSD Buttons +* P11_2 ... P11_7 reserved for QSPI +* P14_0 ... P14_1 reserved for USB +*/ +#define CYCFG_ASSIGNED_PORTS SRM_PORT(0, 0x03), SRM_PORT(1, 0x01),\ + SRM_PORT(2, 0x3f), SRM_PORT(6, 0xd0),\ + SRM_PORT(7, 0x86), SRM_PORT(8, 0xfe),\ + SRM_PORT(11, 0xfc), SRM_PORT(14, 0x03) + +/* +* 8-bit divider 0 reserved for UDB +* 8-bit divider 4 reserved for CSD +* 16-bit divider 0 reserved for USB +*/ +#define CYCFG_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x11), \ + SRM_DIVIDER(CY_SYSCLK_DIV_16_BIT, 0x01) + +#define CYCFG_ASSIGNED_SCBS + +#define CYCFG_ASSIGNED_TCPWMS + +/* End of File */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json new file mode 100644 index 00000000000..7e2c874a4b6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json @@ -0,0 +1,17 @@ +{ + "boot0" : { + "VERSION" : "0.1", + "ROLLBACK_COUNTER" : "0" + }, + + "boot1" : { + "VERSION" : "0.1", + "ROLLBACK_COUNTER" : "0" + }, + + "sdk_path" : "targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/", + "priv_key_file": "keys/USERAPP_CM4_KEY_PRIV.pem", + "aes_key_file": "keys/image-aes-128.key", + "dev_pub_key_file": "keys/dev_pub_key.pem", + "policy_file": "prepare/policy_single_stage_CM4.json" +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h index 3bbae0d9003..92d90a89b9c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h @@ -458,7 +458,7 @@ typedef enum { #define CY_SRAM_BASE 0x08000000UL #define CY_SRAM_SIZE 0x00048000UL #define CY_FLASH_BASE 0x10000000UL -#define CY_FLASH_SIZE 0x00100000UL +#define CY_FLASH_SIZE 0x000D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL #define CY_XIP_BASE 0x18000000UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore new file mode 100644 index 00000000000..601bb601e2c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore @@ -0,0 +1 @@ +packet \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md new file mode 100644 index 00000000000..c28419aba83 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md @@ -0,0 +1,145 @@ +This directory contains tools and scripts for generating keys, preparing provisioning packets and execution of provisioning. +These files are relevant to CY8CPROTO_064_SB or CY8CPROTO_064_SB_M0_PSA, CY8CPROTO_064_SB_PSA targets. +Version of Python required is 3.7+ + +# DEVICE PROVISIONING + +## 1. Generate new keys by executing the following commands from ./keys: + + *Create keys for image signing:* + + python keygen.py -k 8 --jwk USERAPP_CM4_KEY.json --pem-priv USERAPP_CM4_KEY_PRIV.pem + + *Create key for image encryption:* + + python keygen.py --aes aes.key + + +**_NOTE_:** DO NOT COMMIT any new keys to repository. --- + +## 2. Create provisioning packets: +Use *provisioning_packet.py* from ./prepare folder. + +Options: + + --oem OEM key file. + --hsm HSM key file. + --cyboot Cypress Bootloader image certificate. + --cyauth Provisioning authorization certificate. + --policy Policy file. + --out Output directory. + --ckey Customer key that will be used for image signing. Use the option multiple times to specify multiple keys. + --devcert Chain of trust certificate. Use the option multiple times to specify multiple certificates. + +* To create packet for CY8CPROTO_064_SB target using single-stage policy (CM4 only): + + python provisioning_packet.py --policy policy_single_stage_CM4.json --out ../packet --cyboot ../prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt --ckey ../keys/USERAPP_CM4_KEY.json + +* To use external memory (via SMIF) as staging(upgrade) area (slot_1) of NSPE (CM4) image use policy file with corresponding name: + + python provisioning_packet.py --policy policy_single_stage_CM4_smif.json --out ../packet --cyboot ../prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt --ckey ../keys/USERAPP_CM4_KEY.json + +Prebuild folder contains CyBootloader_WithLogs and CyBootloader_Release with corresponding *.hex and *.jwt files. + * WithLogs prints execution results to terminal. + * Release does not print to terminal and boots up silently. + +**_NOTE:_** CypressBootloader_CM0p.jwt and CypressBootloader_CM0p.hex must be used in pair from the same directory in provisioning packet generation (.packets/prov_cmd.jwt) and provisioning procedure itself. + +## 3. Run entrance exam + + python entrance_exam_runner.py + +## 4. Perform provisioning: +**_ATTENTION:_** Proceed to **UPGRADE IMAGES** section first if UPGRADE image is needed. + +Execute *provision_device_runner.py*. +The script will run with the default arguments if no arguments specified. + +Default arguments can be overridden with a custom: + + --prov-jwt Path to provisioning JWT file (packet which contains all data necessary for provisioning, including policy, authorization packets and keys) + --hex Path to Cypress Bootloader HEX binary file + --pubkey-json File where to save public key in JSON format + --pubkey-pem File where to save public key in PEM format + +*Example:* + + python provision_device_runner.py --prov-jwt packet/prov_cmd.jwt --hex prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex --pubkey-json keys/dev_pub_key.json --pubkey-pem keys/dev_pub_key.pem + +**_NOTE:_** PSoC6 supply voltage of 2.5V is required to perform provisioning. + +## UPGRADE IMAGES + +Secure Boot enabled targets support image upgrades, if specified by policy. There are two types of upgrade images supported: +- signed, non encrypted +- signed, encrypted + +The upgrade images types are determined by the following policy setting (firmware sections): + +- **_"smif_id":_** 0, - should be set to 2 if AUGUST_CYW43012 target is used, 1 - if CY8CPROTO_064_SB, 0 - SMIF disabled +- **_"upgrade":_** true/false, - should be set to *true* if UPGRADE supported, *false* - if disabled +- **_"encrypt":_** true/false, - should be set to *true* if encrypted UPGRADE supported, *false* - if disabled +- **_"encrypt_key_id":_** 1, - should remain unchanged, means that Device Key will be used in ECDH/HKDF protocol + +Requirements: +- Policy with **_smif.json** from prepare/ folder should be used. +For encrypted image: +- aes.key generated, as described in **DEVICE_PROVISIONING - 1** +- dev_pub_key.pem must be placed in keys/ folder (this key is generated in provisioning procedure) +- secure_image_parameters.json file in the target directory must contain valid keys' paths + +Non encrypted UPGRADE image +**_Example policy for CY8CPROTO_064_SB:_** + + "smif_id": 1, + "upgrade": true, + "encrypt": false, + "encrypt_key_id": 1, + +Encrypted UPGRADE image: + +**_Example policy for CY8CPROTO_064_SB:_** + + "smif_id": 1, + "upgrade": true, + "encrypt": true, + "encrypt_key_id": 1, + +Modified policy file should be used for provisioning the device, as described in paragraph 4. + +Now mbed-os application or test can be built as described in section **TESTS**. Images for UPGRADE are generated at build time, according to policy. + +- Non enrypted UPGRADE image file name ends with **_upgrade.hex_** +- Enrypted UPGRADE image file name ends with **_enc_upgrade.hex_** + +Upgrade image can be programmed to target board using Daplink. Upgrade procedure is performed after first reset. + +**_Encrypt generic image:_** +The generic HEX file (for example one that is produced by mbed-os build system) can be converted into encrypted image by using encrypted_image_runner.py script located in sb-tools. Usage example: + + python encrypted_image_runner.py --sdk-path . --hex-file someApplication.hex --key-priv keys/MCUBOOT_CM0P_KEY_PRIV.pem --key-pub keys/dev_pub_key.pem --key-aes keys/aes.key --ver 0.1 --img-id 3 --rlb-count 0 --slot-size 0x50000 --pad 1 --img-offset 402653184 + +- **_--sdk-path_** - Path to Secure Boot tools folder +- **_--key-priv_** - ECC Private key used for image signing and for generating shared secret as per ECDH/HKDF. +- **_--key-pub_** - ECC Public key used for image signing and for generating shared secret as per ECDH/HKDF. Only device Key can be used in current implementation. It is generated by provisioning procedure. +- **_--key-aes_** - AES128 key and IV file raw image will be encrypted with. +- **_--img-id_** - Image ID of encrypted image. Must match one mentioned in policy for UPGRADE image. +- **_--slot-size_** - Slot_1 (UPGRADE) size. Must match one mentioned in policy for UPGRADE image. +- **_--ver_** - Version of image. Make sure it matches one defined in secure_image_parameters.json for a given HEX. +- **_--rlb-count_** - Rollback counter. Make sure it matches one defined in secure_image_parameters.json for a given HEX. +- **_--img-offset_** - Starting address offset for UPGRADE image - passed as integer, as represented in policy + +# TESTS + +1. Build and run tests for CY8CPROTO_064_SB target with command: + + Run commands: + mbed test --compile -m CY8CPROTO_064_SB -t GCC_ARM -n tests-mbed* -v + +# TROUBLESHOOTING: + +1. In case of messages like "unable to find device" execute "mbedls -m 1907:CY8CPROTO_064_SB", then check with "mbedls" if device is detected as CY8CPROTO_064_SB with code 1907. +2. Keys, from ./keys folder is used for signing images by default, these keys should be used for provisioning. +3. Consider using CyBootloader from CyBootloader_WithLogs folder. It produces logs, which are useful to understand whether CyBootloader works correctly. +4. When running application with SMIF and _smif.json policy the field "smif_id" should be set to 1 for CY8CPROTO_064_SB. +5. Low frequency quartz (32768 Hz) oscillator have to be soldered on CY8CPROTO_064_SB (not present in stock version of board). diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/encrypted_image_runner.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/encrypted_image_runner.py new file mode 100644 index 00000000000..2d50c8e4787 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/encrypted_image_runner.py @@ -0,0 +1,215 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +import sys +import click +import subprocess +import binascii +from pathlib import Path, PurePath + +from intelhex import IntelHex, hex2bin, bin2hex +from intelhex.compat import asbytes + +HEADER_SIZE = 0x400 +AES_HEADER="aes_header.txt" # near the script file + +def check_file_exist(file): + if not Path(file).exists(): + print("ERROR: File %s not found. Check script arguments."% file) + return False + else: + return True + +def get_final_hex_name(file): + """ + Determine if script is called from mbed-os build system + for Secure Boot target processing or directly + """ + for part in PurePath(file).parts: + if "_unsigned.hex" in part: + # suppose file came from mbed-os build execution + return file[:-13] + "_enc_upgrade.hex" + # suppose stand alone script execution + return file[:-4] + "_enc_upgrade.hex" + +def manage_output(process, input_f, output_f): + """ + Function takes care of subprocess + """ + stderr = process.communicate()[1] + rc = process.wait() + + if rc != 0: + print("ERROR: Encryption script ended with error!") + print("ERROR: " + stderr.decode("utf-8")) + raise Exception("imgtool finished execution with errors!") + + if check_file_exist(output_f): + os.remove(input_f) + +@click.command() +@click.option('--sdk-path', 'sdk_path', + default=Path("."), + type=click.STRING, + help='Path to Secure Boot tools in case running script from outside') +@click.option('--hex-file', 'hex_file', + default=None, + type=click.STRING, + help='Hex file to process') +@click.option('--key-priv', 'key_priv', + default=None, + type=click.STRING, + help='Private key file to use for signing BOOT or UPGRADE image') +@click.option('--key-pub', 'key_pub', + default=None, + type=click.STRING, + help='Path to device public key - obtained from device on provisioning stage') +@click.option('--key-aes', 'key_aes', + default=None, + type=click.STRING, + help='Path to encryption key') +@click.option('--ver', 'version', + default=None, + type=click.STRING, + help='Version') +@click.option('--img-id', 'img_id', + default=None, + type=click.STRING, + help='Image ID - should correspond to values, used in policy file') +@click.option('--rlb-count', 'rlb_count', + default=None, + type=click.STRING, + help='Rollback counter value') +@click.option('--slot-size', 'slot_size', + default=None, + type=click.STRING, + help='Size of slot available for BOOT or UPGRADE image') +@click.option('--pad', 'pad', + default=False, + is_flag=True, + help='Add padding to image - required for UPGRADE image') +@click.option('--img-offset', 'img_offset', + default=None, + type=click.STRING, + help='Offset of hex file for UPGRADE image') + +def main(sdk_path, + hex_file, + key_priv, + key_pub, + key_aes, + version, + img_id, + rlb_count, + slot_size, + pad, + img_offset): + """ + Function consequentially performs operations with provided hex file + and produces an encrypted and signed hex file for UPGRADE + """ + + check_file_exist(key_priv) + check_file_exist(key_pub) + check_file_exist(key_aes) + check_file_exist(hex_file) + + in_f = hex_file[:-4] + "_i.bin" + out_f = hex_file[:-4] + "_o.bin" + + hex_file_final = get_final_hex_name(hex_file) + print("Image UPGRADE:" + hex_file_final) + + # ih = IntelHex(hex_file) + # img_start_addr = ih.start_addr['EIP'] + + hex2bin(hex_file, in_f) #bin_file) + + # $PYTHON $IMGTOOL sign --key $KEY --header-size $HEADER_SIZE --pad-header --align 8 --version $VERSION --image-id $ID --rollback_counter $ROLLBACK_COUNTER --slot-size $SLOT_SIZE --overwrite-only $binFileName $signedFileName is_file_created $signedFileName + + # call imgtool for signature + process = subprocess.Popen([sys.executable, sdk_path + "/imgtool/imgtool.py", "sign", + "--key", key_priv, + "--header-size", str(hex(HEADER_SIZE)), + "--pad-header", + "--align", "8", + "--version", version, + "--image-id", img_id, + "--rollback_counter", rlb_count, + "--slot-size", slot_size, + "--overwrite-only", + in_f, + out_f], + stdout=subprocess.PIPE, stderr=subprocess.PIPE) + manage_output(process, in_f, out_f) + + # AES + # $PYTHON $(dirname "${IMGTOOL}")"/create_aesHeader.py" -k $KEY -p $KEY_DEV --key_to_encrypt "$KEY_AES" $AES_HEADER + # call aesHeader for crypto header generation + process = subprocess.Popen([sys.executable, sdk_path + "/imgtool/create_aesHeader.py", + "-k", key_priv, + "-p", key_pub, + "--key_to_encrypt", key_aes, + AES_HEADER], + stdout=subprocess.PIPE, stderr=subprocess.PIPE) + + # catch stderr outputs + stderr = process.communicate() + rc = process.wait() + check_file_exist(AES_HEADER) + + # aes_cipher.py script file should be in the same folder as imgtool.py + # $PYTHON $(dirname "${IMGTOOL}")"/aes_cipher.py" -k $KEY_AES $signedFileName $aes_encryptedFileName + # is_file_created $aes_encryptedFileName + # encrypt signed image + process = subprocess.Popen([sys.executable, sdk_path + "/imgtool/aes_cipher.py", + "-k", key_aes, + out_f, + in_f], + stdout=subprocess.PIPE, stderr=subprocess.PIPE) + manage_output(process, out_f, in_f) + + # second part - obtain signed image from encrypted file - with padding - for staging area + # $PYTHON $IMGTOOL sign --key $KEY --header-size $HEADER_SIZE --pad-header --align 8 --version $VERSION --image-id $ID --rollback_counter $ROLLBACK_COUNTER --slot-size $SLOT_SIZE --overwrite-only $PAD -a $AES_HEADER $aes_encryptedFileName $signedEncFileName + # is_file_created $signedEncFileName + + # call imgtool for signature + process = subprocess.Popen([sys.executable, sdk_path + "/imgtool/imgtool.py", "sign", + "--key", key_priv, + "--header-size", str(hex(HEADER_SIZE)), + "--pad-header", + "--align", "8", + "--version", version, + "--image-id", img_id, + "--rollback_counter", rlb_count, + "--slot-size", slot_size, + "--overwrite-only", + "--pad", + "-a", AES_HEADER, + in_f, + out_f], + #bin_sig_enc, + #bin_sig_enc_sig], + stdout=subprocess.PIPE, stderr=subprocess.PIPE) + manage_output(process, in_f, out_f) + + bin2hex(out_f, hex_file_final, int(img_offset)) + os.remove(out_f) + + os.remove(AES_HEADER) + +if __name__ == "__main__": + main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/entrance_exam_runner.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/entrance_exam_runner.py new file mode 100644 index 00000000000..ead6127934b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/entrance_exam_runner.py @@ -0,0 +1,45 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import sys +from execute.enums import DebugCore +from execute.helper import get_target_name +from execute.programmer.programmer import ProgrammingTool +from execute.entrance_exam import entrance_exam + +TOOL_NAME = 'pyocd' # Programming/debugging tool used for communication with device +ACCESS_PORT = DebugCore.debug_sys_ap # Access port used for entrance exam + + +def main(): + """ + Provides high level support for entrance exam procedure. + """ + target = get_target_name(TOOL_NAME, ACCESS_PORT) + if not target: + print('Invalid access port.') + sys.exit(1) + + status = False + tool = ProgrammingTool.create(TOOL_NAME) + if tool.connect(target): + status = entrance_exam(tool) + + if not status: + sys.exit(1) + + +if __name__ == "__main__": + main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/entrance_exam.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/entrance_exam.py new file mode 100644 index 00000000000..8757f02db33 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/entrance_exam.py @@ -0,0 +1,68 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +from time import sleep +from execute.helper import check_mode +from execute.enums import ProtectionState +from execute.gen_data_from_json import ENTRANCE_EXAM_FW_STATUS_REG, ENTRANCE_EXAM_FW_STATUS_MASK, \ + ENTRANCE_EXAM_FW_STATUS_VAL, ENTRANCE_EXAM_REGION_HASH_ADDR, ENTRANCE_EXAM_REGION_HASH_SIZE, \ + ENTRANCE_EXAM_REGION_HASH_MODE, ENTRANCE_EXAM_REGION_HASH_EXPECTED_VAL +from execute.sys_call import region_hash + + +def entrance_exam(tool): + """ + Checks device life-cycle, Flashboot firmware and Flash state. + :param tool: Programming/debugging tool used for communication with device. + :return: True if entrance exam passed, otherwise False. + """ + # Check the device life-cycle stage + print('Check device protection state:') + if not check_mode(tool, ProtectionState.secure): + return False + + # Check if any firmware is launched by FlashBoot and running on the device + print(os.linesep + 'Read Flashboot firmware status:') + fb_firmware_status = tool.read32(ENTRANCE_EXAM_FW_STATUS_REG) + print(f'FB Firmware status = {hex(fb_firmware_status)}') + print(f'Received FB_FW_STATUS = {hex(fb_firmware_status & ENTRANCE_EXAM_FW_STATUS_MASK)}') + print(f'Expected FB_FW_STATUS = {hex(ENTRANCE_EXAM_FW_STATUS_VAL)}') + is_exam_pass = (fb_firmware_status & ENTRANCE_EXAM_FW_STATUS_MASK) == ENTRANCE_EXAM_FW_STATUS_VAL + if is_exam_pass: + print('PASS: FB Firmware status is as expected') + else: + print('FAIL: FB Firmware status is not as expected') + if fb_firmware_status == 0xA1000100: + print('Test firmware exists and running on CM4 core. Device is in SECURE UNCLAIMED mode') + elif fb_firmware_status == 0xA1000101: + print('Secure firmware exists and running on CM0p core. Device is in SECURE CLAIMED mode') + return False + + # Check flash for malicious firmware + print(os.linesep + 'Check if Main Flash of the device is empty:') + if region_hash(tool, ENTRANCE_EXAM_REGION_HASH_ADDR, ENTRANCE_EXAM_REGION_HASH_SIZE, + ENTRANCE_EXAM_REGION_HASH_MODE, ENTRANCE_EXAM_REGION_HASH_EXPECTED_VAL): + print('PASS: Flash value is as expected') + print() + print('*****************************************') + print(' ENTRANCE EXAM TEST PASSED ') + print('*****************************************') + tool.reset() + sleep(0.2) + else: + print('FAIL: Flash value is not as expected') + return False + return True diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/enums.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/enums.py new file mode 100644 index 00000000000..7624fc3f129 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/enums.py @@ -0,0 +1,30 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from enum import IntEnum, Enum + + +class DebugCore(Enum): + """ + Provides set of access ports for programming/debugging. + """ + debug_cm0_ap, debug_cm4_ap, debug_sys_ap = range(3) + + +class ProtectionState(IntEnum): + """ + Provides set of device life-cycle stages. + """ + unknown, virgin, normal, secure, dead = range(5) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/gen_data_from_json.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/gen_data_from_json.py new file mode 100644 index 00000000000..b2b815e8798 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/gen_data_from_json.py @@ -0,0 +1,38 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +################################################################################# +# ENTRANCE EXAM REGISTER AND VARIABLE CONSTANTS +################################################################################# +ENTRANCE_EXAM_EFUSE_ASSET_HASH_BASE_REG = 0x402C0840 +ENTRANCE_EXAM_ASSET_HASH_LEN = 16 +ENTRANCE_EXAM_ASSET_HASH_ZEROS = 72 +ENTRANCE_EXAM_ASSET_HASH_EXPECTED_STR = "0xD9 0x1B 0x11 0xAA 0x5D 0x75 0x68 0x6A " \ + "0x12 0x10 0xE0 0x88 0x38 0xE1 0x2B 0x79" + +ENTRANCE_EXAM_LIFECYCLE_STAGE_REG = 0x402C082b +ENTRANCE_EXAM_LIFECYCLE_STAGE_EXPECTED_VAL = 0x01 + +ENTRANCE_EXAM_FW_STATUS_REG = 0x08044800 +ENTRANCE_EXAM_FW_STATUS_VAL = 0xF0000000 +ENTRANCE_EXAM_FW_STATUS_MASK = 0xF0800000 + +ENTRANCE_EXAM_SRAM_ADDR = 0x0802c000 +ENTRANCE_EXAM_SRAM_SIZE = 0x00004000 + +ENTRANCE_EXAM_REGION_HASH_ADDR = 0x10000000 +ENTRANCE_EXAM_REGION_HASH_SIZE = 0x000e0000 +ENTRANCE_EXAM_REGION_HASH_MODE = 255 +ENTRANCE_EXAM_REGION_HASH_EXPECTED_VAL = 0x00 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/helper.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/helper.py new file mode 100644 index 00000000000..6264202c9e3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/helper.py @@ -0,0 +1,59 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from execute.enums import DebugCore, ProtectionState +from execute.p6_reg import CYREG_CPUSS_PROTECTION, CYREG_IPC2_STRUCT_DATA, CYREG_EFUSE_SECURE_HASH + + +def check_mode(tool, expected_mode: ProtectionState): + """ + Checks device protection state and compares with the expected. + :return: The device protection state. + """ + mode_name = expected_mode.name.upper() + if tool.read32(CYREG_CPUSS_PROTECTION) != int(expected_mode): + print(f'FAIL: Device is not in {mode_name} mode, error code: {hex(tool.read32(CYREG_IPC2_STRUCT_DATA))}') + print('Read Secure Hash from eFUSEs:') # 00 expected on virgin device + got_factory_hash = '' + i = 0 + while i < 24: + hash_byte_val = hex(tool.read8(CYREG_EFUSE_SECURE_HASH + i)) + got_factory_hash += hash_byte_val + ' ' + i += 1 + print(f"Received SECURE_HASH: '{got_factory_hash}'") + return False + print(f'PASS: Device is in {mode_name} mode') + return True + + +def get_target_name(tool_name, access_port): + """ + Gets name of the target based on programming tool and access port. + :param tool_name: The name of programming/debugging tool. + :param access_port: The access port used for communication. + :return: The target name. + """ + if tool_name == 'pyocd': + if access_port == DebugCore.debug_cm0_ap: + target = 'cy8c64xx_cm0' + elif access_port == DebugCore.debug_cm4_ap: + target = 'cy8c64xx_cm4' + elif access_port == DebugCore.debug_sys_ap: + target = 'cy8c64xx_cm4_full' + else: + raise ValueError(f"Unhandled access port value: '{access_port}'") + else: + raise ValueError(f"Unhandled programming tool: '{tool_name}'") + return target diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_memory_map.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_memory_map.py new file mode 100644 index 00000000000..98700bf20cb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_memory_map.py @@ -0,0 +1,17 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +FLASH_ADDRESS = 0x10000000 +FLASH_SIZE = 0x000e0000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_reg.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_reg.py new file mode 100644 index 00000000000..2e8e630aed9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_reg.py @@ -0,0 +1,95 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +################################################################################# +# PSOC6 BLE REGISTER ADDRESSES +################################################################################# +CYREG_IPC2_STRUCT_ACQUIRE = 0x40230040 # 0x40220040 2M +CYREG_IPC2_STRUCT_NOTIFY = 0x40230048 +CYREG_IPC2_STRUCT_DATA = 0x4023004C +CYREG_IPC2_STRUCT_DATA1 = 0x40230050 # for 2M only +CYREG_IPC2_STRUCT_LOCK_STATUS = 0x40230050 # 0x4023005C +CYREG_CPUSS_PROTECTION = 0x40210500 # 0x4023005C 2M + +CYREG_EFUSE_FACTORY_HASH = 0x402c082c +CYREG_EFUSE_LIFECYCLE_STAGE = 0x402c082b +CYREG_EFUSE_SECURE_HASH = 0x402c0814 +CYREG_EFUSE_LAST_BYTE = 0x402c0879 + +NVSTORE_AREA_1_ADDRESS = 0x100FB600 +NVSTORE_OEM_ADDRESS = 0x100FFA00 +NVSTORE_DEV_KEY_ADDRESS = 0x100FFC00 +NVSTORE_UDS_ADDRESS = 0x100FFE00 + +################################################################################# +# PSOC6 BLE SFLASH ADDRESSES +################################################################################# +SFLASH_TOC1_ADDR = 0x16007800 +SFLASH_TOC1_LEN = 0x1C +SFLASH_TOC2_ADDR = 0x16007c00 +SFLASH_TOC2_LEN = 0x30 +TOC1_ROW_IDX = 60 +TOC1_DUPL_ROW_IDX = 61 +TOC2_ROW_IDX = 62 +TOC2_DUPL_ROW_IDX = 63 +TOC1_BYTE_SIZE = 0x1C # Stored as 1st word of TOC1 +MAGIC_NUMBER1 = 0x01211219 # Stored as 2nd word of TOC1 +NUM_OBJECTS_TOC1 = 0x4 # Stored as 3rd word of TOC1 +SFLASH_TRIM_START_ADDR = 0x16000200 # Stored as 4th word of TOC1 +SFLASH_HV_PARAM_TABLE_ADDR = 0x16000400 +SRAM_HV_PARAM_TABLE_ADDR = 0x08001000 # Only for *C PSoC6ABLE2 silicon +SFLASH_UNIQUEID_START_ADDR = 0x16000600 # Stored as 5th word of TOC1 +FLASHBOOT_START_ADDR = 0x16002000 # Stored as 6th word of TOC1 +SFLASH_SYSCALL_TABLE_PTR_ADDR = 0x16000004 # Stored as 7th word of TOC1 +SFLASH_SYSCALL_TABLE_PTR = 0x16004100 +SFLASH_SKIP_HASH = 0x16000008 +SFLASH_FLL_CONTROL = 0x16000008 +SFLASH_NORMAL_ACCESS_CTL = 0x16000008 +MAGIC_NUMBER2 = 0x01211220 +SFLASH_FLL_EN_IDX = 0x2 + +################################################################################# +# CONSTANTS AND DEFINITIONS +################################################################################# +# any random SRAM address. Fixing it to 0x2000 for all sram_scratch purposes. +# SRAM_SCRATCH = 0x08046000 +# SRAM_SCRATCH_SIZE = 0x00000800 +FLASH_START_ADDR = 0x10000000 +FLASH_SHA256_STR_ADDR = 0x10000100 +FLASH_SHA256_STR_LEN = 12 +FLASH_SHA256_DIG_ADDR = 0x10000110 +FLASH_SIZE = 0x200000 # 2 MB for PSoC 6A-2M +SFLASH_START_ADDR = 0x16000000 +SFLASH_SIZE = 0x8000 + +GENERAL_TRIM_TABLE_HASH_ADDR = 0x16000200 +TRIM_START_ADDR = 0x16000203 +TRIM_TABLE_LEN_ADDR = 0x16000200 +WFLASH_START_ADDR = 0x14000000 +WFLASH_SIZE = 0x8000 +SRAM_START_ADDR = 0x08000000 +SRAM_SIZE = 0x48000 +# SRAM_PUB_ADDR = 0x08046800 # 2M: 0x080ff400 +ADDR_FMPARAMSTRUCT = 0x08000800 +FLASH_ROW_SIZE = 512 +# Number of trials +TRIAL_MAX = 300 +SYSTEM_RESET = 0x0 +ONLY_CM4_RESET = 0x1 +INVALIDRESETTYPE = 0x3 +R_ACCESS = 0x01 +W_ACCESS = 0x02 +X_ACCESS = 0x04 +NIL_ACCESS = 0x00 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/__init__.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/__init__.py new file mode 100644 index 00000000000..acba3a75512 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/__init__.py @@ -0,0 +1,18 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from . import base +from . import programmer +from . import pyocd_wrapper diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/base.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/base.py new file mode 100644 index 00000000000..0bd3d25f101 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/base.py @@ -0,0 +1,179 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from enum import Enum +from abc import ABCMeta, abstractmethod + + +class ResetType(Enum): + SW = 1, + HW = 2 + + +class Interface(Enum): + SWD = 1 + JTAG = 2 + + +class ProgrammerBase(metaclass=ABCMeta): + def __init__(self): + pass + + @abstractmethod + def connect(self, target_name=None, interface=None): + """ + Connects to target. + :param target_name: The target name. + :param interface: Debug interface. + :return: True if connected successfully, otherwise False. + """ + raise NotImplementedError() + + @abstractmethod + def disconnect(self): + """ + Disconnects from target. + """ + raise NotImplementedError() + + @abstractmethod + def set_frequency(self, value_khz): + """ + Sets probe frequency. + :param value_khz: Frequency in kHz. + """ + raise NotImplementedError() + + @abstractmethod + def halt(self): + """ + Halts the target. + """ + raise NotImplementedError() + + @abstractmethod + def resume(self): + """ + Resumes the execution + """ + raise NotImplementedError() + + @abstractmethod + def reset(self, reset_type=ResetType.SW): + """ + Resets the target. + :param reset_type: The reset type. + """ + raise NotImplementedError() + + @abstractmethod + def reset_and_halt(self, reset_type=ResetType.SW): + """ + Resets the target and halts the CPU immediately after reset. + :param reset_type: The reset type. + """ + raise NotImplementedError() + + @abstractmethod + def read8(self, address): + """ + Reads 8-bit value from specified memory location. + :param address: The memory address to read. + :return: The read value. + """ + raise NotImplementedError() + + @abstractmethod + def read16(self, address): + """ + Reads 16-bit value from specified memory location. + :param address: The memory address to read. + :return: The read value. + """ + raise NotImplementedError() + + @abstractmethod + def read32(self, address): + """ + Reads 32-bit value from specified memory location. + :param address: The memory address to read. + :return: The read value. + """ + raise NotImplementedError() + + @abstractmethod + def write8(self, address, value): + """ + Writes 8-bit value by specified memory location. + :param address: The memory address to write. + :param value: The 8-bit value to write. + """ + raise NotImplementedError() + + @abstractmethod + def write16(self, address, value): + """ + Writes 16-bit value by specified memory location. + :param address: The memory address to write. + :param value: The 16-bit value to write. + """ + raise NotImplementedError() + + @abstractmethod + def write32(self, address, value): + """ + Writes 32-bit value by specified memory location. + :param address: The memory address to write. + :param value: The 32-bit value to write. + """ + raise NotImplementedError() + + @abstractmethod + def read_reg(self, reg_name): + """ + Gets value of a core register. + :param reg_name: Core register name. + :return: The register value. + """ + raise NotImplementedError() + + @abstractmethod + def write_reg(self, reg_name, value): + """ + Sets value of a core register. + :param reg_name: Core register name. + :param value: The value to set. + """ + raise NotImplementedError() + + @abstractmethod + def erase(self, address, size): + """ + Erases entire device flash or specified sectors. + :param address: The memory location. + :param size: The memory size. + """ + raise NotImplementedError() + + @abstractmethod + def program(self, filename, file_format=None, address=None): + """ + Programs a file into flash. + :param filename: Path to a file. + :param file_format: File format. Default is to use the file's extension. + :param address: Base address used for the address where to flash a binary. + :return: True if programmed successfully, otherwise False. + """ + raise NotImplementedError() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/exceptions.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/exceptions.py new file mode 100644 index 00000000000..0183ced9e30 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/exceptions.py @@ -0,0 +1,23 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from pyocd.core.exceptions import TransferFaultError + + +class ExtendedTransferFaultError(TransferFaultError): + def __str__(self): + desc = super().__str__() + desc += ' If address points to a register it should be aligned with the register size.' + return desc diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/programmer.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/programmer.py new file mode 100644 index 00000000000..2beda8b8c70 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/programmer.py @@ -0,0 +1,29 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from execute.programmer.pyocd_wrapper import Pyocd + + +tools = { + 'pyocd': Pyocd +} + + +class ProgrammingTool: + @staticmethod + def create(name): + tool_type = tools[name] + tool = tool_type() + return tool diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/pyocd_wrapper.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/pyocd_wrapper.py new file mode 100644 index 00000000000..076250a4fbc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/pyocd_wrapper.py @@ -0,0 +1,272 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from execute.programmer.base import ProgrammerBase, Interface, ResetType +from pyocd.core.helpers import ConnectHelper +from pyocd.core import exceptions +from pyocd.flash import loader +from pyocd.flash.loader import FlashEraser +from pyocd import coresight +from execute.programmer.exceptions import ExtendedTransferFaultError + + +class Pyocd(ProgrammerBase): + def __init__(self): + super(Pyocd, self).__init__() + self.session = None + self.board = None + self.target = None + self.probe = None + + def connect(self, target_name=None, interface=None, probe_id=None): + """ + Connects to target using default debug interface. + :param target_name: The target name. + :param interface: Debug interface. + :param probe_id: Probe serial number. + :return: True if connected successfully, otherwise False. + """ + if interface: + raise NotImplementedError + else: + if target_name: + options = { + 'target_override': target_name + } + else: + options = {} + self.session = ConnectHelper.session_with_chosen_probe(blocking=True, options=options, board_id=probe_id, unique_id=probe_id) + if self.session is None: + return False + self.board = self.session.board + try: + self.session.open() + except exceptions.TransferFaultError as e: + if not self.board.target.is_locked(): + print(f"Transfer fault while initializing board: {e}") + return False + except Exception as e: + print(f"Exception while initializing board: {e}") + return False + + self.target = self.board.target + self.probe = self.session.probe + + # Write infinite loop into RAM and start core execution + self.halt() + # B662 - CPSIE I - Enable IRQ by clearing PRIMASK + # E7FE - B - Jump to address (argument is an offset) + self.write32(0x08000000, 0xE7FEB662) + self.write_reg('pc', 0x08000000) + self.write_reg('sp', 0x08001000) + self.write_reg('xpsr', 0x01000000) + self.resume() + + return True + + def disconnect(self): + """ + Closes active connection. + """ + if self.session is None: + raise ValueError('Debug session is not initialized.') + self.session.close() + + def set_frequency(self, value_khz): + """ + Sets probe frequency. + :param value_khz: Frequency in kHz. + """ + if self.probe is None: + raise ValueError('Debug probe is not initialized.') + self.probe.set_clock(value_khz * 1000) + + def halt(self): + """ + Halts the target. + """ + if self.session is None: + raise ValueError('Debug session is not initialized.') + self.target.halt() + + def resume(self): + """ + Resumes the execution + """ + if self.target is None: + raise ValueError('Target is not initialized.') + self.target.resume() + + def reset(self, reset_type=ResetType.SW): + """ + Resets the target. + :param reset_type: The reset type. + """ + if self.target is None: + raise ValueError('Target is not initialized.') + self.target.reset(reset_type=reset_type) + + def reset_and_halt(self, reset_type=ResetType.SW): + """ + Resets the target and halts the CPU immediately after reset. + :param reset_type: The reset type. + """ + if self.target is None: + raise ValueError('Target is not initialized.') + self.target.reset_and_halt(reset_type=reset_type) + + def read8(self, address): + """ + Reads 8-bit value from specified memory location. + :param address: The memory address to read. + :return: The read value. + """ + if self.target is None: + raise ValueError('Target is not initialized.') + try: + data = self.target.read_memory(address, transfer_size=8) + except exceptions.TransferFaultError as e: + raise ExtendedTransferFaultError(e.fault_address, e.fault_length) + return data + + def read16(self, address): + """ + Reads 16-bit value from specified memory location. + :param address: The memory address to read. + :return: The read value. + """ + if self.target is None: + raise ValueError('Target is not initialized.') + if (address & 0x01) == 0: + try: + data = self.target.read_memory(address, transfer_size=16) + except exceptions.TransferFaultError as e: + raise ExtendedTransferFaultError(e.fault_address, e.fault_length) + return data + else: + raise ValueError('Address not aligned.') + + def read32(self, address): + """ + Reads 32-bit value from specified memory location. + :param address: The memory address to read. + :return: The read value. + """ + if self.target is None: + raise ValueError('Target is not initialized.') + if (address & 0x03) == 0: + try: + data = self.target.read_memory(address, transfer_size=32) + except exceptions.TransferFaultError as e: + raise ExtendedTransferFaultError(e.fault_address, e.fault_length) + return data + else: + raise ValueError('Address not aligned.') + + def write8(self, address, value): + """ + Writes 8-bit value by specified memory location. + :param address: The memory address to write. + :param value: The 8-bit value to write. + """ + if self.target is None: + raise ValueError('Target is not initialized.') + try: + data = self.target.write_memory(address, value, transfer_size=8) + except exceptions.TransferFaultError as e: + raise ExtendedTransferFaultError(e.fault_address, e.fault_length) + return data + + def write16(self, address, value): + """ + Writes 16-bit value by specified memory location. + :param address: The memory address to write. + :param value: The 16-bit value to write. + """ + if self.target is None: + raise ValueError('Target is not initialized.') + try: + data = self.target.write_memory(address, value, transfer_size=16) + except exceptions.TransferFaultError as e: + raise ExtendedTransferFaultError(e.fault_address, e.fault_length) + return data + + def write32(self, address, value): + """ + Writes 32-bit value by specified memory location. + :param address: The memory address to write. + :param value: The 32-bit value to write. + """ + if self.target is None: + raise ValueError('Target is not initialized.') + try: + data = self.target.write_memory(address, value, transfer_size=32) + except exceptions.TransferFaultError as e: + raise ExtendedTransferFaultError(e.fault_address, e.fault_length) + return data + + def read_reg(self, reg_name): + """ + Gets value of a core register. + :param reg_name: Core register name. + :return: The register value. + """ + reg = reg_name.lower() + if reg in coresight.cortex_m.CORE_REGISTER: + value = self.target.read_core_register(reg) + return value + else: + raise ValueError(f'Unknown core register {reg}.') + + def write_reg(self, reg_name, value): + """ + Sets value of a core register. + :param reg_name: Core register name. + :param value: The value to set. + :return: The register value. + """ + reg = reg_name.lower() + if reg in coresight.cortex_m.CORE_REGISTER: + self.target.write_core_register(reg, value) + else: + raise ValueError(f'Unknown core register {reg}.') + + def erase(self, address, size): + """ + Erases entire device flash or specified sectors. + :param address: The memory location. + :param size: The memory size. + """ + region = self.session.target.memory_map.get_region_for_address(address) + if not region: + raise ValueError('Address 0x%08x is not within a memory region.' % address) + if not region.is_flash: + raise ValueError('Address 0x%08x is not in flash.' % address) + eraser = FlashEraser(self.session, FlashEraser.Mode.SECTOR) + address_range = f"{hex(address)}-{hex(address + size)}" + eraser.erase([address_range]) + + def program(self, filename, file_format=None, address=None): + """ + Programs a file into flash. + :param filename: Path to a file. + :param file_format: File format. Default is to use the file's extension. + :param address: Base address used for the address where to flash a binary. + :return: True if programmed successfully, otherwise False. + """ + if self.session is None: + raise ValueError('Debug session is not initialized.') + programmer = loader.FileProgrammer(self.session, chip_erase='sector') + programmer.program(filename, base_address=address, file_format=file_format) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/provision_device.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/provision_device.py new file mode 100644 index 00000000000..cb135b2b543 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/provision_device.py @@ -0,0 +1,105 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +from time import sleep +from execute.helper import check_mode +from execute.enums import ProtectionState +from execute.sys_call import get_prov_details, provision_keys_and_policies +from execute.p6_memory_map import FLASH_ADDRESS, FLASH_SIZE +from execute.gen_data_from_json import ENTRANCE_EXAM_FW_STATUS_REG, ENTRANCE_EXAM_FW_STATUS_MASK, \ + ENTRANCE_EXAM_FW_STATUS_VAL +from execute.p6_reg import CYREG_CPUSS_PROTECTION, NVSTORE_AREA_1_ADDRESS + + +def provision_execution(tool, pub_key_json, prov_cmd_jwt, cy_bootloader_hex): + """ + Programs Cypress Bootloader and calls system calls for device provisioning. + :param tool: Programming/debugging tool used for communication with device. + :param pub_key_json: File where to save public key in JSON format. + :param prov_cmd_jwt: Path to provisioning JWT file (packet which contains + all data necessary for provisioning, including policy, authorization + packets and keys). + :param cy_bootloader_hex: Path to Cypress Bootloader program file. + :return: True if provisioning passed, otherwise False. + """ + tool.set_frequency(200) + + print("CPUSS.PROTECTION state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD.") + print(hex(CYREG_CPUSS_PROTECTION), hex(tool.read32(CYREG_CPUSS_PROTECTION))) + + reset_device(tool) + result, key = get_prov_details(tool, 1) + print('Device public key has been read successfully.' if result else 'FAIL: Cannot read device public key.') + print(key) + + with open(os.path.join(pub_key_json), 'w') as json_file: + json_file.write(key) + + # Check the device life-cycle stage + print('Check device protection state') + if not check_mode(tool, ProtectionState.secure): + return False + + print(os.linesep + 'Erase main flash and TOC3:') + print('erasing...') + tool.erase(FLASH_ADDRESS, FLASH_SIZE) + reset_device(tool) + + print(os.linesep + 'Read FB Firmware status:') + fb_firmware_status = tool.read32(ENTRANCE_EXAM_FW_STATUS_REG) + print(f'FB Firmware status = {hex(fb_firmware_status)}') + # Print Expected and received LIFECYCLE_STAGE values + print(f'Received FB_FW_STATUS = {hex(fb_firmware_status & ENTRANCE_EXAM_FW_STATUS_MASK)}') + print(f'Expected FB_FW_STATUS = {hex(ENTRANCE_EXAM_FW_STATUS_VAL)}') + # Verify if received value is the same as expected + is_exam_pass = (fb_firmware_status & ENTRANCE_EXAM_FW_STATUS_MASK) == ENTRANCE_EXAM_FW_STATUS_VAL + print('PASS: FB Firmware status is as expected' if is_exam_pass else 'FAIL: FB Firmware status is not as expected') + + if is_exam_pass: + print(os.linesep + 'PROGRAMMING APP HEX:') + tool.program(cy_bootloader_hex) + reset_device(tool) + + if is_exam_pass: + print(os.linesep + 'Run provisioning syscall') + blow_secure_fuse = 1 # indicates whether to convert device to SECURE CLAIMED mode + is_exam_pass = provision_keys_and_policies(tool, blow_secure_fuse, os.path.join(prov_cmd_jwt)) + print(hex(NVSTORE_AREA_1_ADDRESS) + ': ', sep=' ', end='', flush=True) + if is_exam_pass: + i = 0 + while i < 8 * 4: # output 8 words + print(hex(tool.read32(NVSTORE_AREA_1_ADDRESS + i)) + ' ', sep=' ', end='', flush=True) + i += 4 + print(os.linesep) + else: + print('FAIL: Unexpected ProvisionKeysAndPolicies syscall response') + + if is_exam_pass: + print('*****************************************') + print(" PROVISIONING PASSED ") + print("*****************************************") + + reset_device(tool) + return is_exam_pass + + +def reset_device(tool): + """ + Resets device and waits for device initialization. + :param tool: Programming/debugging tool used for communication with device. + """ + tool.reset() + sleep(0.2) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/sys_call.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/sys_call.py new file mode 100644 index 00000000000..a74bc4fce42 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/sys_call.py @@ -0,0 +1,198 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +from execute.gen_data_from_json import ENTRANCE_EXAM_SRAM_ADDR, ENTRANCE_EXAM_SRAM_SIZE +from execute.p6_reg import CYREG_IPC2_STRUCT_ACQUIRE, CYREG_IPC2_STRUCT_DATA, CYREG_IPC2_STRUCT_NOTIFY, \ + CYREG_IPC2_STRUCT_LOCK_STATUS + +PROVISION_KEYS_AND_POLICIES_OPCODE = 0x33 # ProvisionKeysAndPolicies API opcode +GET_PROV_DETAILS_OPCODE = 0x37 # GetProvDetails() API opcode +REGION_HASH_OPCODE = 0x31 # RegionHash() API opcode + + +def region_hash(tool, address, length, mode, exp_value): + """ + Procedure calls RegionHash syscall over IPC and read response. + :param tool: Programming/debugging tool used for communication with device. + :param address: Region hash address. + :param length: Region hash size. + :param mode: Region hash mode. + :param exp_value: Region hash expected value. + :return: True if syscall executed successfully, otherwise False. + """ + # Acquire IPC structure + tool.write32(CYREG_IPC2_STRUCT_ACQUIRE, 0x80000000) + ipc_acquire = 0 + while (ipc_acquire & 0x80000000) == 0: + ipc_acquire = tool.read32(CYREG_IPC2_STRUCT_ACQUIRE) + + # Set RAM address and Opcode + op_code = (REGION_HASH_OPCODE << 24) + (exp_value << 16) + (mode << 8) + 0 + tool.write32(CYREG_IPC2_STRUCT_DATA, ENTRANCE_EXAM_SRAM_ADDR) + tool.write32(ENTRANCE_EXAM_SRAM_ADDR, op_code) + + scratch_addr = ENTRANCE_EXAM_SRAM_ADDR + 0x08 + tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x04, scratch_addr) + tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x08, length) + tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x0C, address) + + # IPC_STRUCT[ipc_id].IPC_NOTIFY - + tool.write32(CYREG_IPC2_STRUCT_NOTIFY, 0x00000001) + + # Wait on response + response = 0x80000000 + while (response & 0x80000000) != 0: + response = tool.read32(CYREG_IPC2_STRUCT_LOCK_STATUS) + response = tool.read32(ENTRANCE_EXAM_SRAM_ADDR) + + if (response & 0xFF000000) == 0xa0000000: + print('Region compare complete') + return True + else: + print('Region compare error response:') + print(hex(CYREG_IPC2_STRUCT_DATA), hex(tool.read32(CYREG_IPC2_STRUCT_DATA))) + print(hex(ENTRANCE_EXAM_SRAM_ADDR), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR))) + print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x04), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x04))) + print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x08), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x08))) + print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x0C), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x0C))) + return False + + +def get_prov_details(tool, key_id): + """ + Calls GetProvDetails syscall over IPC. + :param tool: Programming/debugging tool used for communication with device. + :param key_id: Public key ID. + :return: True if get provision details successfully, otherwise False. + """ + # Acquire IPC structure + tool.write32(CYREG_IPC2_STRUCT_ACQUIRE, 0x80000000) + print(hex(CYREG_IPC2_STRUCT_ACQUIRE), hex(tool.read32(CYREG_IPC2_STRUCT_ACQUIRE))) + ipc_acquire = 0 + while (ipc_acquire & 0x80000000) == 0: + ipc_acquire = tool.read32(CYREG_IPC2_STRUCT_ACQUIRE) + + # Set RAM address and Opcode + op_code = GET_PROV_DETAILS_OPCODE << 24 + tool.write32(CYREG_IPC2_STRUCT_DATA, ENTRANCE_EXAM_SRAM_ADDR) # IPC_STRUCT.DATA + tool.write32(ENTRANCE_EXAM_SRAM_ADDR, op_code) # SRAM_SCRATCH + + scratch_addr = ENTRANCE_EXAM_SRAM_ADDR + 0x08 + tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x04, scratch_addr) + tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x08, key_id) + tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x0C, 0x0) + + # IPC_STRUCT[ipc_id].IPC_NOTIFY - + tool.write32(CYREG_IPC2_STRUCT_NOTIFY, 0x00000001) + + # Wait on response + response = 0x80000000 + while (response & 0x80000000) != 0: + response = tool.read32(CYREG_IPC2_STRUCT_LOCK_STATUS) + response = tool.read32(ENTRANCE_EXAM_SRAM_ADDR) + + print(hex(CYREG_IPC2_STRUCT_DATA), hex(tool.read32(CYREG_IPC2_STRUCT_DATA))) + print(hex(ENTRANCE_EXAM_SRAM_ADDR), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR))) # Expected MSB=0xA0 + print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x04), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x04))) + print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x08), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x08))) + + is_exam_pass = (response & 0xFF000000) == 0xa0000000 + if is_exam_pass: + scratch_addr = tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x04) + read_hash_size = tool.read32(scratch_addr + 0x00) + read_hash_addr = tool.read32(scratch_addr + 0x04) + + i = 0 + response = '' + while i < read_hash_size: + # Save data in string format + hash_byte_chr = chr(tool.read8(read_hash_addr + i)) + response += hash_byte_chr + i += 1 + response = response.strip() + else: + print(hex(CYREG_IPC2_STRUCT_DATA), tool.read32(CYREG_IPC2_STRUCT_DATA)) + print(hex(ENTRANCE_EXAM_SRAM_ADDR), tool.read32(ENTRANCE_EXAM_SRAM_ADDR)) + response = None + + return is_exam_pass, response + + +def provision_keys_and_policies(tool, blow_secure_efuse, filename): + """ + Calls ProvisionKeysAndPolicies syscall over IPC. + :param tool: Programming/debugging tool used for communication with device. + :param blow_secure_efuse: Indicates whether to convert device to SECURE CLAIMED mode. + :param filename: Path to provisioning JWT file (packet which contains + all data necessary for provisioning, including policy, authorization + packets and keys). + :return: True if sending provision keys and policies passed, otherwise False + """ + file_size = os.path.getsize(filename) + if file_size > ENTRANCE_EXAM_SRAM_SIZE: + print('JWT packet too long') + return False + + print('UDS eFuses will be blown' if blow_secure_efuse == 1 else 'UDS eFuses will NOT be blown') + print(f'JWT packet size: {file_size}') + with open(filename, 'r+') as jwt_file: + jwt_file.seek(0) + content = jwt_file.read() + jwt_chars = list(content) + + # Acquires IPC structure. + tool.write32(CYREG_IPC2_STRUCT_ACQUIRE, 0x80000000) + print(hex(CYREG_IPC2_STRUCT_ACQUIRE), hex(tool.read32(CYREG_IPC2_STRUCT_ACQUIRE))) + + ipc_acquire = 0 + while (ipc_acquire & 0x80000000) == 0: + ipc_acquire = tool.read32(CYREG_IPC2_STRUCT_ACQUIRE) + + # Set RAM address and Opcode + tool.write32(CYREG_IPC2_STRUCT_DATA, ENTRANCE_EXAM_SRAM_ADDR) + tool.write32(ENTRANCE_EXAM_SRAM_ADDR, (PROVISION_KEYS_AND_POLICIES_OPCODE << 24) + (blow_secure_efuse << 16)) + + scratch_addr = ENTRANCE_EXAM_SRAM_ADDR + 0x08 + tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x04, scratch_addr) + tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x08, file_size + 0x04) + scratch_addr = ENTRANCE_EXAM_SRAM_ADDR + 0x0C + + for char in jwt_chars: + tool.write8(scratch_addr, ord(char)) + scratch_addr += 1 + + # IPC_STRUCT[ipc_id].IPC_NOTIFY - + tool.write32(CYREG_IPC2_STRUCT_NOTIFY, 0x00000001) + print(hex(CYREG_IPC2_STRUCT_NOTIFY), hex(tool.read32(CYREG_IPC2_STRUCT_NOTIFY))) + # Wait on response + response = 0x80000000 + while (response & 0x80000000) != 0: + response = tool.read32(CYREG_IPC2_STRUCT_LOCK_STATUS) + + # Read response for test + print(hex(CYREG_IPC2_STRUCT_DATA), hex(tool.read32(CYREG_IPC2_STRUCT_DATA))) + print(hex(ENTRANCE_EXAM_SRAM_ADDR) + ': ', sep=' ', end='', flush=True) + i = 0 + while i < 4 * 4: # output 4 words + print(hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR)) + ' ', sep=' ', end='', flush=True) + i += 4 + print(os.linesep) + + response = tool.read32(ENTRANCE_EXAM_SRAM_ADDR) + result = (response & 0xFF000000) == 0xa0000000 + + print('ProvisionKeysAndPolicies', 'complete' if result else f'error response: {hex(response)}') + return result diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py new file mode 100644 index 00000000000..4165163263a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py @@ -0,0 +1,106 @@ + +import click + +from cryptography.hazmat.primitives.ciphers import Cipher, algorithms, modes +from cryptography.hazmat.primitives.ciphers.aead import AESGCM +from cryptography.hazmat.backends import default_backend +from cryptography.hazmat.primitives import padding + + +class AESCipher(object): + + def __init__(self, key, IV): + + self.backend = default_backend() + self.key = AESCipher.get_bytes(key) + self.iv = AESCipher.get_bytes(IV) + self.block_size = 128 + + @staticmethod + def get_bytes(inputdata): + if type(inputdata) is str: + return str.encode(inputdata,'utf-8') + elif type(inputdata) is bytes: + return inputdata + else: + raise Exception("Unknown input data type...") + + +class AESCipherCBC(AESCipher): + + def __init__(self, key, IV): + super().__init__(key, IV) + self.cipher = Cipher(algorithms.AES(self.key), modes.CBC(self.iv), backend=self.backend) + + def encrypt(self, raw): + encryptor = self.cipher.encryptor() + padder = padding.PKCS7(self.block_size).padder() + return encryptor.update(padder.update(raw) + padder.finalize()) + encryptor.finalize() + + def decrypt(self, enc): + decryptor = self.cipher.decryptor() + unpadder = padding.PKCS7(self.block_size).unpadder() + return unpadder.update(decryptor.update(enc) + decryptor.finalize()) + unpadder.finalize() + + +class AESCipherGCM(AESCipher): + + def __init__(self, key, IV, auth_data): + super().__init__(key, IV) + self.cipher = AESGCM(self.key) + self.auth_data = str.encode(auth_data,'utf-8') + + def encrypt(self, raw): + return self.cipher.encrypt(self.iv, raw, self.auth_data) + + def decrypt(self, enc): + return self.cipher.decrypt(self.iv, enc, self.auth_data) + +def read_key_from_file(keyfile): + + with open(keyfile) as f: + content = f.read().splitlines() + if len(content) < 2: + raise Exception("Not anough AES input data: in the file should be two lines: key, iv ...") + key = bytes.fromhex(content[0]) + iv = bytes.fromhex(content[1]) + + if 8*len(key) not in set([128, 192, 256]): + raise Exception("Invalid AES Key length: should be 128, 192 or 256 bits") + check_iv_length(iv) + + return key, iv + +def check_iv_length(iv): + if 8*len(iv) != 128: + raise Exception("Invalid AES IV length: should be 128 bits") + return True + +@click.command() +@click.option('-k', '--keyfile') +@click.option('-a', '--auth_data', default='default data') +@click.option('-m', '--mode', default='CBC') +@click.argument('inputfile') +@click.argument('outputfile') +def main(keyfile, auth_data, mode, inputfile, outputfile): + + key, iv = read_key_from_file(keyfile) + + if mode == 'CBC': + check_iv_length(iv) + aes = AESCipherCBC(key, iv) + elif mode == 'GCM': + aes = AESCipherGCM(key, iv, auth_data) + else: + raise Exception("Selected mode is not supported...") + + inFile = open(inputfile,"rb") + outFile = open(outputfile,"wb") + + outFile.write(aes.encrypt(inFile.read())) + + inFile.close() + outFile.close() + +if __name__ == "__main__": + main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py new file mode 100644 index 00000000000..b21307ed455 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py @@ -0,0 +1,46 @@ +import codecs +import click + +from aes_cipher import * +from ecc_kdf import ECDH_KDF + +def get_header_info(kdf_object, key_to_encrypt_file): + + aes = AESCipherCBC(kdf_object.aes_key, kdf_object.iv) + #print (kdf_object.aes_key.hex()) + + key_to_enc, iv_to_enc = read_key_from_file(key_to_encrypt_file) + key_encrypted = aes.encrypt(key_to_enc + iv_to_enc) + + if kdf_object.salt is None or kdf_object.info is None: + raise Exception('salt and info should be presented...') + if len(kdf_object.salt) != 16 or len(kdf_object.info) != 16: + raise Exception('salt and info fields length should be 16 bytes...') + + return key_encrypted + kdf_object.salt + kdf_object.info + + +@click.command() +@click.option('-a', '--algorithm', default='ECC') #assymetric algorithm for KDF +@click.option('-k', '--private_key') #host side key pair file +@click.option('-p', '--public_key') #device side public key +@click.option('-l', '--key_length', default=16) #derived key (AES) length +@click.option('-s', '--salt', default=None) #salt for KDF +@click.option('-i', '--info', default=b'_handshake_data_') #info data for KDF +@click.option('--key_to_encrypt') #AES key file name (key and iv are used for image encryption), should be AES encrypted, using derived key +@click.argument('outputfile') #AES_header info file name + +def main(algorithm, private_key, public_key, key_length, salt, info, key_to_encrypt, outputfile): + kdf_object = None + if(algorithm == 'ECC'): + kdf_object = ECDH_KDF(private_key, public_key, key_length, salt, info) + else: + raise Exception('Algorithm not supported...') + + aes_header = get_header_info(kdf_object, key_to_encrypt) + + with open(outputfile, 'wb') as header_out: + header_out.write(aes_header) + +if __name__ == "__main__": + main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py new file mode 100644 index 00000000000..90d2a034299 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py @@ -0,0 +1,68 @@ + +from cryptography.hazmat.backends import default_backend +from cryptography.hazmat.primitives import hashes +from cryptography.hazmat.primitives.asymmetric import ec +from cryptography.hazmat.primitives.kdf.hkdf import HKDF + +from cryptography.hazmat.primitives import serialization + +import codecs +import os + +class ECDH_KDF(object): + + def __init__(self, private_key, public_key, key_length, salt, info): + + salt_length = 16 + + self.backend = default_backend() + self.host_key_pair = serialization.load_pem_private_key(self.read_key_bytes(private_key), password=None, backend=self.backend) + + #Deserialize public key: extract from private or directly from pem file + try: + self.device_public_key = serialization.load_pem_private_key(self.read_key_bytes(public_key), password=None, backend=self.backend).public_key() + except: + self.device_public_key = serialization.load_pem_public_key(self.read_key_bytes(public_key), backend=self.backend) + + self.key_length = key_length + self.iv_length = 16 + + if salt is not None: + self.salt = ECDH_KDF.get_bytes(salt) + else: + self.salt = os.urandom(salt_length) + self.info = ECDH_KDF.get_bytes(info) + + self.derived_key = self.derive_key() + self.aes_key = self.derived_key[:self.key_length] + self.iv = self.derived_key[self.key_length:] + + @staticmethod + def get_bytes(inputdata): + if type(inputdata) is str: + return str.encode(inputdata,'utf-8') + elif type(inputdata) is bytes: + return inputdata + else: + raise Exception("Unknown input data type...") + + def read_key_bytes(self, key_file): + with open(key_file, "rb") as key_file: + return key_file.read() + + def derive_key(self): + + shared_key = self.host_key_pair.exchange(ec.ECDH(), self.device_public_key) + derived_key = HKDF(algorithm=hashes.SHA256(), # Perform key derivation. + length=self.key_length + self.iv_length, + salt=self.salt, + info=self.info, + backend=self.backend).derive(shared_key) + + return derived_key + +def main(): + pass + +if __name__ == "__main__": + main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool.py new file mode 100644 index 00000000000..ee92438bdd2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool.py @@ -0,0 +1,198 @@ +#! /usr/bin/env python3 +# +# Copyright 2017 Linaro Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import click +import getpass +from imgtool import keys +from imgtool import image +from imgtool.version import decode_version + + +def gen_rsa2048(keyfile, passwd): + keys.RSA2048.generate().export_private(path=keyfile, passwd=passwd) + + +def gen_ecdsa_p256(keyfile, passwd): + keys.ECDSA256P1.generate().export_private(keyfile, passwd=passwd) + + +def gen_ecdsa_p224(keyfile, passwd): + print("TODO: p-224 not yet implemented") + + +valid_langs = ['c', 'rust'] +keygens = { + 'rsa-2048': gen_rsa2048, + 'ecdsa-p256': gen_ecdsa_p256, + 'ecdsa-p224': gen_ecdsa_p224, +} + + +def load_key(keyfile): + # TODO: better handling of invalid pass-phrase + key = keys.load(keyfile) + if key is not None: + return key + passwd = getpass.getpass("Enter key passphrase: ").encode('utf-8') + return keys.load(keyfile, passwd) + + +def get_password(): + while True: + passwd = getpass.getpass("Enter key passphrase: ") + passwd2 = getpass.getpass("Reenter passphrase: ") + if passwd == passwd2: + break + print("Passwords do not match, try again") + + # Password must be bytes, always use UTF-8 for consistent + # encoding. + return passwd.encode('utf-8') + + +@click.option('-p', '--password', is_flag=True, + help='Prompt for password to protect key') +@click.option('-t', '--type', metavar='type', required=True, + type=click.Choice(keygens.keys())) +@click.option('-k', '--key', metavar='filename', required=True) +@click.command(help='Generate pub/private keypair') +def keygen(type, key, password): + password = get_password() if password else None + keygens[type](key, password) + + +@click.option('-l', '--lang', metavar='lang', default=valid_langs[0], + type=click.Choice(valid_langs)) +@click.option('-k', '--key', metavar='filename', required=True) +@click.command(help='Get public key from keypair') +def getpub(key, lang): + key = load_key(key) + if key is None: + print("Invalid passphrase") + elif lang == 'c': + key.emit_c() + elif lang == 'rust': + key.emit_rust() + else: + raise ValueError("BUG: should never get here!") + + +def validate_version(ctx, param, value): + try: + decode_version(value) + return value + except ValueError as e: + raise click.BadParameter("{}".format(e)) + + +class BasedIntParamType(click.ParamType): + name = 'integer' + + def convert(self, value, param, ctx): + try: + if value[:2].lower() == '0x': + return int(value[2:], 16) + elif value[:1] == '0': + return int(value, 8) + return int(value, 10) + except ValueError: + self.fail('%s is not a valid integer' % value, param, ctx) + + +def load_data_from_file(filename): + FileObj = open(filename, 'rb') + data = FileObj.read() + FileObj.close() + return data + + +@click.argument('outfile') +@click.argument('infile') +@click.option('--overwrite-only', default=False, is_flag=True, + help='Use overwrite-only instead of swap upgrades') +@click.option('-M', '--max-sectors', type=int, + help='When padding allow for this amount of sectors (defaults to 128)') +@click.option('--pad', default=False, is_flag=True, + help='Pad image to --slot-size bytes, adding trailer magic') +@click.option('-S', '--slot-size', type=BasedIntParamType(), required=True, + help='Size of the slot where the image will be written') +@click.option('--pad-header', default=False, is_flag=True, + help='Add --header-size zeroed bytes at the beginning of the image') +@click.option('-H', '--header-size', type=BasedIntParamType(), required=True) +@click.option('-v', '--version', callback=validate_version, required=True) +@click.option('--align', type=click.Choice(['1', '2', '4', '8']), + required=True) +@click.option('-k', '--key', metavar='filename') +@click.option('-a', '--aes-header-file', default=None, metavar='filename') +@click.option('--image-id', required=True, type=int, help='Image ID') +@click.option('--rollback_counter', default=None, type=int, help='Rollback monotonic counter value') +@click.command(help='Create a signed or unsigned image') +def sign(key, align, version, header_size, pad_header, slot_size, pad, + max_sectors, overwrite_only, aes_header_file, image_id, rollback_counter, infile, outfile): + + if aes_header_file is not None : + aes_header = load_data_from_file(aes_header_file) + else: + aes_header = None + + img = image.Image.load(infile, version=decode_version(version), + header_size=header_size, pad_header=pad_header, + pad=pad, align=int(align), slot_size=slot_size, + max_sectors=max_sectors, + overwrite_only=overwrite_only, aes_header_data=aes_header, + image_id=image_id, rollback_counter=rollback_counter) + key = load_key(key) if key else None + img.sign(key) + + if pad: + img.pad_to(slot_size) + + img.save(outfile) + + +class AliasesGroup(click.Group): + + _aliases = { + "create": "sign", + } + + def list_commands(self, ctx): + cmds = [k for k in self.commands] + aliases = [k for k in self._aliases] + return sorted(cmds + aliases) + + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + if cmd_name in self._aliases: + return click.Group.get_command(self, ctx, self._aliases[cmd_name]) + return None + + +@click.command(cls=AliasesGroup, + context_settings=dict(help_option_names=['-h', '--help'])) +def imgtool(): + pass + + +imgtool.add_command(keygen) +imgtool.add_command(getpub) +imgtool.add_command(sign) + + +if __name__ == '__main__': + imgtool() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/__init__.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/__init__.py new file mode 100644 index 00000000000..107921f94e9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/__init__.py @@ -0,0 +1,13 @@ +# Copyright 2017 Linaro Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/image.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/image.py new file mode 100644 index 00000000000..34cf0c02a58 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/image.py @@ -0,0 +1,269 @@ +# Copyright 2018 Nordic Semiconductor ASA +# Copyright 2017 Linaro Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Image signing and management. +""" + +from . import version as versmod +from intelhex import IntelHex +import hashlib +import struct +import os.path +import os + +IMAGE_MAGIC = 0x96f3b83d +IMAGE_HEADER_SIZE = 32 +BIN_EXT = "bin" +INTEL_HEX_EXT = "hex" +DEFAULT_MAX_SECTORS = 128 + +# Image header flags. +IMAGE_F = { + 'PIC': 0x0000001, + 'NON_BOOTABLE': 0x0000010, } + +TLV_VALUES = { + 'KEYHASH': 0x01, + 'SHA256': 0x10, + 'RSA2048': 0x20, + 'ECDSA224': 0x21, + 'ECDSA256': 0x22, } + +TLV_INFO_SIZE = 4 +TLV_INFO_MAGIC = 0x6907 + +boot_magic = bytes([ + 0x77, 0xc2, 0x95, 0xf3, + 0x60, 0xd2, 0xef, 0x7f, + 0x35, 0x52, 0x50, 0x0f, + 0x2c, 0xb6, 0x79, 0x80, ]) + +class TLV(): + def __init__(self): + self.buf = bytearray() + + def add(self, kind, payload): + """Add a TLV record. Kind should be a string found in TLV_VALUES above.""" + buf = struct.pack(' 0: + if obj.base_addr: + # Adjust base_addr for new header + obj.base_addr -= obj.header_size + obj.payload = (b'\000' * obj.header_size) + obj.payload + + obj.check() + return obj + + def __init__(self, version=None, header_size=IMAGE_HEADER_SIZE, pad=0, + align=1, slot_size=0, max_sectors=DEFAULT_MAX_SECTORS, + overwrite_only=False, aes_header_data=None, image_id=1, rollback_counter=0): + self.version = version or versmod.decode_version("0") + self.header_size = header_size or IMAGE_HEADER_SIZE + self.pad = pad + self.align = align + self.slot_size = slot_size + self.max_sectors = max_sectors + self.overwrite_only = overwrite_only + self.aes_header_data = aes_header_data + self.image_id = image_id + self.rollback_counter = rollback_counter + + def __repr__(self): + return "".format( + self.version, + self.header_size, + self.base_addr if self.base_addr is not None else "N/A", + self.align, + self.slot_size, + self.max_sectors, + self.overwrite_only, + self.__class__.__name__, + len(self.payload)) + + def check(self): + """Perform some sanity checking of the image.""" + # If there is a header requested, make sure that the image + # starts with all zeros. + if self.header_size > 0: + if any(v != 0 for v in self.payload[0:self.header_size]): + raise Exception("Padding requested, but image does not start with zeros") + if self.slot_size > 0: + tsize = self._trailer_size(self.align, self.max_sectors, + self.overwrite_only) + padding = self.slot_size - (len(self.payload) + tsize) + if padding < 0: + msg = "Image size (0x{:x}) + trailer (0x{:x}) exceeds requested size 0x{:x}".format( + len(self.payload), tsize, self.slot_size) + raise Exception(msg) + + def sign(self, key, add_padding = True): + + DECRYPT_BLOCK_SIZE = 256 #future AES decription buffer size, is used for align FW image and trailer size + + if add_padding: + pl_size = len(self.payload) + pad_len = (DECRYPT_BLOCK_SIZE - pl_size % DECRYPT_BLOCK_SIZE) % DECRYPT_BLOCK_SIZE + #self.payload += bytearray(os.urandom(pad_len)) + self.payload += bytearray(pad_len) + + self.add_header(key) + if (self.aes_header_data is not None): + self.add_AES_header() + + tlv = TLV() + + # Note that ecdsa wants to do the hashing itself, which means + # we get to hash it twice. + sha = hashlib.sha256() + sha.update(self.payload) + digest = sha.digest() + + tlv.add('SHA256', digest) + + if key is not None: + pub = key.get_public_bytes() + sha = hashlib.sha256() + sha.update(pub) + pubbytes = sha.digest() + tlv.add('KEYHASH', pubbytes) + + sig = key.sign(bytes(self.payload)) + tlv.add(key.sig_tlv(), sig) + + trailer = tlv.get() + self.payload += trailer + + if add_padding: + trailer_size = len(trailer) + tr_rem_len = (DECRYPT_BLOCK_SIZE - trailer_size % DECRYPT_BLOCK_SIZE ) % DECRYPT_BLOCK_SIZE + #self.payload += bytearray(os.urandom(tr_rem_len)) + self.payload += bytearray(tr_rem_len) + + def add_header(self, key): + """Install the image header. + + The key is needed to know the type of signature, and + approximate the size of the signature.""" + + flags = 0 + + fmt = ('<' + + # type ImageHdr struct { + 'I' + # Magic uint32 + 'I' + # LoadAddr uint32 + 'H' + # HdrSz uint16 + 'B' + # Image ID uint8 + 'B' + # Rollback monotonic counter value uint8 + 'I' + # ImgSz uint32 + 'I' + # Flags uint32 + 'BBHI' + # Vers ImageVersion + 'I' # Pad2 uint32 + ) # } + assert struct.calcsize(fmt) == IMAGE_HEADER_SIZE + header = struct.pack(fmt, + IMAGE_MAGIC, + 0, # LoadAddr + self.header_size, + self.image_id, + self.rollback_counter, + len(self.payload) - self.header_size, # ImageSz + flags, # Flags + self.version.major, + self.version.minor or 0, + self.version.revision or 0, + self.version.build or 0, + 0) # Pad2 + self.payload = bytearray(self.payload) + self.payload[:len(header)] = header + + def add_AES_header(self): + """Install AES header just after main image header + + The header contains: + AES Key, IV (encrypted with AES CBC) + salt - random sequence for ECDH KDF + info - information for ECDH KDF + """ + + aes_header_bytes = self.aes_header_data #str.encode(self.aes_header_data,'utf-8') + headerAES = struct.pack( "@%ds" % (len(aes_header_bytes)), aes_header_bytes ) + self.payload[IMAGE_HEADER_SIZE:IMAGE_HEADER_SIZE + len(headerAES)] = headerAES + + + def _trailer_size(self, write_size, max_sectors, overwrite_only): + # NOTE: should already be checked by the argument parser + if overwrite_only: + return 8 * 2 + 16 + else: + if write_size not in set([1, 2, 4, 8]): + raise Exception("Invalid alignment: {}".format(write_size)) + m = DEFAULT_MAX_SECTORS if max_sectors is None else max_sectors + return m * 3 * write_size + 8 * 2 + 16 + + def pad_to(self, size): + """Pad the image to the given size, with the given flash alignment.""" + tsize = self._trailer_size(self.align, self.max_sectors, + self.overwrite_only) + padding = size - (len(self.payload) + tsize) + pbytes = b'\xff' * padding + pbytes += b'\xff' * (tsize - len(boot_magic)) + pbytes += boot_magic + self.payload += pbytes + + +class HexImage(Image): + + def load(self, path): + ih = IntelHex(path) + return ih.tobinarray(), ih.minaddr() + + def save(self, path): + h = IntelHex() + h.frombytes(bytes = self.payload, offset = self.base_addr) + h.tofile(path, 'hex') + +class BinImage(Image): + + def load(self, path): + with open(path, 'rb') as f: + return f.read(), None + + def save(self, path): + with open(path, 'wb') as f: + f.write(self.payload) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/__init__.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/__init__.py new file mode 100644 index 00000000000..da5b083193b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/__init__.py @@ -0,0 +1,76 @@ +# Copyright 2017 Linaro Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Cryptographic key management for imgtool. +""" + +from cryptography.hazmat.backends import default_backend +from cryptography.hazmat.primitives import serialization +from cryptography.hazmat.primitives.asymmetric.rsa import RSAPrivateKey, RSAPublicKey +from cryptography.hazmat.primitives.asymmetric.ec import EllipticCurvePrivateKey, EllipticCurvePublicKey + +from .rsa import RSA2048, RSA2048Public, RSAUsageError +from .ecdsa import ECDSA256P1, ECDSA256P1Public, ECDSAUsageError + +class PasswordRequired(Exception): + """Raised to indicate that the key is password protected, but a + password was not specified.""" + pass + +def load(path, passwd=None): + """Try loading a key from the given path. Returns None if the password wasn't specified.""" + with open(path, 'rb') as f: + raw_pem = f.read() + try: + pk = serialization.load_pem_private_key( + raw_pem, + password=passwd, + backend=default_backend()) + # Unfortunately, the crypto library raises unhelpful exceptions, + # so we have to look at the text. + except TypeError as e: + msg = str(e) + if "private key is encrypted" in msg: + return None + raise e + except ValueError: + # This seems to happen if the key is a public key, let's try + # loading it as a public key. + pk = serialization.load_pem_public_key( + raw_pem, + backend=default_backend()) + + if isinstance(pk, RSAPrivateKey): + if pk.key_size != 2048: + raise Exception("Unsupported RSA key size: " + pk.key_size) + return RSA2048(pk) + elif isinstance(pk, RSAPublicKey): + if pk.key_size != 2048: + raise Exception("Unsupported RSA key size: " + pk.key_size) + return RSA2048Public(pk) + elif isinstance(pk, EllipticCurvePrivateKey): + if pk.curve.name != 'secp256r1': + raise Exception("Unsupported EC curve: " + pk.curve.name) + if pk.key_size != 256: + raise Exception("Unsupported EC size: " + pk.key_size) + return ECDSA256P1(pk) + elif isinstance(pk, EllipticCurvePublicKey): + if pk.curve.name != 'secp256r1': + raise Exception("Unsupported EC curve: " + pk.curve.name) + if pk.key_size != 256: + raise Exception("Unsupported EC size: " + pk.key_size) + return ECDSA256P1Public(pk) + else: + raise Exception("Unknown key type: " + str(type(pk))) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py new file mode 100644 index 00000000000..f541d16d1a4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py @@ -0,0 +1,102 @@ +""" +ECDSA key management +""" + +from cryptography.hazmat.backends import default_backend +from cryptography.hazmat.primitives import serialization +from cryptography.hazmat.primitives.asymmetric import ec +from cryptography.hazmat.primitives.hashes import SHA256 + +from .general import KeyClass + +class ECDSAUsageError(Exception): + pass + +class ECDSA256P1Public(KeyClass): + def __init__(self, key): + self.key = key + + def shortname(self): + return "ecdsa" + + def _unsupported(self, name): + raise ECDSAUsageError("Operation {} requires private key".format(name)) + + def _get_public(self): + return self.key + + def get_public_bytes(self): + # The key is embedded into MBUboot in "SubjectPublicKeyInfo" format + return self._get_public().public_bytes( + encoding=serialization.Encoding.DER, + format=serialization.PublicFormat.SubjectPublicKeyInfo) + + def export_private(self, path, passwd=None): + self._unsupported('export_private') + + def export_public(self, path): + """Write the public key to the given file.""" + pem = self._get_public().public_bytes( + encoding=serialization.Encoding.PEM, + format=serialization.PublicFormat.SubjectPublicKeyInfo) + with open(path, 'wb') as f: + f.write(pem) + + def sig_type(self): + return "ECDSA256_SHA256" + + def sig_tlv(self): + return "ECDSA256" + + def sig_len(self): + # The DER encoding depends on the high bit, and can be + # anywhere from 70 to 72 bytes. Because we have to fill in + # the length field before computing the signature, however, + # we'll give the largest, and the sig checking code will allow + # for it to be up to two bytes larger than the actual + # signature. + return 72 + +class ECDSA256P1(ECDSA256P1Public): + """ + Wrapper around an ECDSA private key. + """ + + def __init__(self, key): + """key should be an instance of EllipticCurvePrivateKey""" + self.key = key + + @staticmethod + def generate(): + pk = ec.generate_private_key( + ec.SECP256R1(), + backend=default_backend()) + return ECDSA256P1(pk) + + def _get_public(self): + return self.key.public_key() + + def export_private(self, path, passwd=None): + """Write the private key to the given file, protecting it with the optional password.""" + if passwd is None: + enc = serialization.NoEncryption() + else: + enc = serialization.BestAvailableEncryption(passwd) + pem = self.key.private_bytes( + encoding=serialization.Encoding.PEM, + format=serialization.PrivateFormat.PKCS8, + encryption_algorithm=enc) + with open(path, 'wb') as f: + f.write(pem) + + def raw_sign(self, payload): + """Return the actual signature""" + return self.key.sign( + data=payload, + signature_algorithm=ec.ECDSA(SHA256())) + + def sign(self, payload): + # To make fixed length, pad with one or two zeros. + sig = self.raw_sign(payload) + sig += b'\000' * (self.sig_len() - len(sig)) + return sig diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py new file mode 100644 index 00000000000..8cb3220f802 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py @@ -0,0 +1,99 @@ +""" +Tests for ECDSA keys +""" + +import io +import os.path +import sys +import tempfile +import unittest + +from cryptography.exceptions import InvalidSignature +from cryptography.hazmat.primitives.asymmetric import ec +from cryptography.hazmat.primitives.hashes import SHA256 + +sys.path.insert(0, os.path.abspath(os.path.join(os.path.dirname(__file__), '../..'))) + +from imgtool.keys import load, ECDSA256P1, ECDSAUsageError + +class EcKeyGeneration(unittest.TestCase): + + def setUp(self): + self.test_dir = tempfile.TemporaryDirectory() + + def tname(self, base): + return os.path.join(self.test_dir.name, base) + + def tearDown(self): + self.test_dir.cleanup() + + def test_keygen(self): + name1 = self.tname("keygen.pem") + k = ECDSA256P1.generate() + k.export_private(name1, b'secret') + + self.assertIsNone(load(name1)) + + k2 = load(name1, b'secret') + + pubname = self.tname('keygen-pub.pem') + k2.export_public(pubname) + pk2 = load(pubname) + + # We should be able to export the public key from the loaded + # public key, but not the private key. + pk2.export_public(self.tname('keygen-pub2.pem')) + self.assertRaises(ECDSAUsageError, + pk2.export_private, self.tname('keygen-priv2.pem')) + + def test_emit(self): + """Basic sanity check on the code emitters.""" + k = ECDSA256P1.generate() + + ccode = io.StringIO() + k.emit_c(ccode) + self.assertIn("ecdsa_pub_key", ccode.getvalue()) + self.assertIn("ecdsa_pub_key_len", ccode.getvalue()) + + rustcode = io.StringIO() + k.emit_rust(rustcode) + self.assertIn("ECDSA_PUB_KEY", rustcode.getvalue()) + + def test_emit_pub(self): + """Basic sanity check on the code emitters.""" + pubname = self.tname("public.pem") + k = ECDSA256P1.generate() + k.export_public(pubname) + + k2 = load(pubname) + + ccode = io.StringIO() + k2.emit_c(ccode) + self.assertIn("ecdsa_pub_key", ccode.getvalue()) + self.assertIn("ecdsa_pub_key_len", ccode.getvalue()) + + rustcode = io.StringIO() + k2.emit_rust(rustcode) + self.assertIn("ECDSA_PUB_KEY", rustcode.getvalue()) + + def test_sig(self): + k = ECDSA256P1.generate() + buf = b'This is the message' + sig = k.raw_sign(buf) + + # The code doesn't have any verification, so verify this + # manually. + k.key.public_key().verify( + signature=sig, + data=buf, + signature_algorithm=ec.ECDSA(SHA256())) + + # Modify the message to make sure the signature fails. + self.assertRaises(InvalidSignature, + k.key.public_key().verify, + signature=sig, + data=b'This is thE message', + signature_algorithm=ec.ECDSA(SHA256())) + +if __name__ == '__main__': + unittest.main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py new file mode 100644 index 00000000000..3ba34cb186e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py @@ -0,0 +1,35 @@ +"""General key class.""" + +import sys + +AUTOGEN_MESSAGE = "/* Autogenerated by imgtool.py, do not edit. */" + +class KeyClass(object): + def _public_emit(self, header, trailer, indent, file=sys.stdout, len_format=None): + print(AUTOGEN_MESSAGE, file=file) + print(header, end='', file=file) + encoded = self.get_public_bytes() + for count, b in enumerate(encoded): + if count % 8 == 0: + print("\n" + indent, end='', file=file) + else: + print(" ", end='', file=file) + print("0x{:02x},".format(b), end='', file=file) + print("\n" + trailer, file=file) + if len_format is not None: + print(len_format.format(len(encoded)), file=file) + + def emit_c(self, file=sys.stdout): + self._public_emit( + header="const unsigned char {}_pub_key[] = {{".format(self.shortname()), + trailer="};", + indent=" ", + len_format="const unsigned int {}_pub_key_len = {{}};".format(self.shortname()), + file=file) + + def emit_rust(self, file=sys.stdout): + self._public_emit( + header="static {}_PUB_KEY: &'static [u8] = &[".format(self.shortname().upper()), + trailer="];", + indent=" ", + file=file) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py new file mode 100644 index 00000000000..4ddbfc646ea --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py @@ -0,0 +1,95 @@ +""" +RSA Key management +""" + +from cryptography.hazmat.backends import default_backend +from cryptography.hazmat.primitives import serialization +from cryptography.hazmat.primitives.asymmetric import rsa +from cryptography.hazmat.primitives.asymmetric.padding import PSS, MGF1 +from cryptography.hazmat.primitives.hashes import SHA256 + +from .general import KeyClass + +class RSAUsageError(Exception): + pass + +class RSA2048Public(KeyClass): + """The public key can only do a few operations""" + def __init__(self, key): + self.key = key + + def shortname(self): + return "rsa" + + def _unsupported(self, name): + raise RSAUsageError("Operation {} requires private key".format(name)) + + def _get_public(self): + return self.key + + def get_public_bytes(self): + # The key embedded into MCUboot is in PKCS1 format. + return self._get_public().public_bytes( + encoding=serialization.Encoding.DER, + format=serialization.PublicFormat.PKCS1) + + def export_private(self, path, passwd=None): + self._unsupported('export_private') + + def export_public(self, path): + """Write the public key to the given file.""" + pem = self._get_public().public_bytes( + encoding=serialization.Encoding.PEM, + format=serialization.PublicFormat.SubjectPublicKeyInfo) + with open(path, 'wb') as f: + f.write(pem) + + def sig_type(self): + return "PKCS1_PSS_RSA2048_SHA256" + + def sig_tlv(self): + return "RSA2048" + + def sig_len(self): + return 256 + +class RSA2048(RSA2048Public): + """ + Wrapper around an 2048-bit RSA key, with imgtool support. + """ + + def __init__(self, key): + """The key should be a private key from cryptography""" + self.key = key + + @staticmethod + def generate(): + pk = rsa.generate_private_key( + public_exponent=65537, + key_size=2048, + backend=default_backend()) + return RSA2048(pk) + + def _get_public(self): + return self.key.public_key() + + def export_private(self, path, passwd=None): + """Write the private key to the given file, protecting it with the optional password.""" + if passwd is None: + enc = serialization.NoEncryption() + else: + enc = serialization.BestAvailableEncryption(passwd) + pem = self.key.private_bytes( + encoding=serialization.Encoding.PEM, + format=serialization.PrivateFormat.PKCS8, + encryption_algorithm=enc) + with open(path, 'wb') as f: + f.write(pem) + + def sign(self, payload): + # The verification code only allows the salt length to be the + # same as the hash length, 32. + return self.key.sign( + data=payload, + padding=PSS(mgf=MGF1(SHA256()), salt_length=32), + algorithm=SHA256()) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py new file mode 100644 index 00000000000..81518780a61 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py @@ -0,0 +1,102 @@ +""" +Tests for RSA keys +""" + +import io +import os +import sys +import tempfile +import unittest + +from cryptography.exceptions import InvalidSignature +from cryptography.hazmat.primitives.asymmetric.padding import PSS, MGF1 +from cryptography.hazmat.primitives.hashes import SHA256 + +# Setup sys path so 'imgtool' is in it. +sys.path.insert(0, os.path.abspath(os.path.join(os.path.dirname(__file__), '../..'))) + +from imgtool.keys import load, RSA2048, RSAUsageError + +class KeyGeneration(unittest.TestCase): + + def setUp(self): + self.test_dir = tempfile.TemporaryDirectory() + + def tname(self, base): + return os.path.join(self.test_dir.name, base) + + def tearDown(self): + self.test_dir.cleanup() + + def test_keygen(self): + name1 = self.tname("keygen.pem") + k = RSA2048.generate() + k.export_private(name1, b'secret') + + # Try loading the key without a password. + self.assertIsNone(load(name1)) + + k2 = load(name1, b'secret') + + pubname = self.tname('keygen-pub.pem') + k2.export_public(pubname) + pk2 = load(pubname) + + # We should be able to export the public key from the loaded + # public key, but not the private key. + pk2.export_public(self.tname('keygen-pub2.pem')) + self.assertRaises(RSAUsageError, pk2.export_private, self.tname('keygen-priv2.pem')) + + def test_emit(self): + """Basic sanity check on the code emitters.""" + k = RSA2048.generate() + + ccode = io.StringIO() + k.emit_c(ccode) + self.assertIn("rsa_pub_key", ccode.getvalue()) + self.assertIn("rsa_pub_key_len", ccode.getvalue()) + + rustcode = io.StringIO() + k.emit_rust(rustcode) + self.assertIn("RSA_PUB_KEY", rustcode.getvalue()) + + def test_emit_pub(self): + """Basic sanity check on the code emitters, from public key.""" + pubname = self.tname("public.pem") + k = RSA2048.generate() + k.export_public(pubname) + + k2 = load(pubname) + + ccode = io.StringIO() + k2.emit_c(ccode) + self.assertIn("rsa_pub_key", ccode.getvalue()) + self.assertIn("rsa_pub_key_len", ccode.getvalue()) + + rustcode = io.StringIO() + k2.emit_rust(rustcode) + self.assertIn("RSA_PUB_KEY", rustcode.getvalue()) + + def test_sig(self): + k = RSA2048.generate() + buf = b'This is the message' + sig = k.sign(buf) + + # The code doesn't have any verification, so verify this + # manually. + k.key.public_key().verify( + signature=sig, + data=buf, + padding=PSS(mgf=MGF1(SHA256()), salt_length=32), + algorithm=SHA256()) + + # Modify the message to make sure the signature fails. + self.assertRaises(InvalidSignature, + k.key.public_key().verify, + signature=sig, + data=b'This is thE message', + padding=PSS(mgf=MGF1(SHA256()), salt_length=32), + algorithm=SHA256()) + +if __name__ == '__main__': + unittest.main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/version.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/version.py new file mode 100644 index 00000000000..8910e0b1a43 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/version.py @@ -0,0 +1,53 @@ +# Copyright 2017 Linaro Limited +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Semi Semantic Versioning + +Implements a subset of semantic versioning that is supportable by the image +header. +""" + +from collections import namedtuple +import re + +SemiSemVersion = namedtuple('SemiSemVersion', ['major', 'minor', 'revision', + 'build']) + +version_re = re.compile( + r"""^([1-9]\d*|0)(\.([1-9]\d*|0)(\.([1-9]\d*|0)(\+([1-9]\d*|0))?)?)?$""") + + +def decode_version(text): + """Decode the version string, which should be of the form maj.min.rev+build + """ + m = version_re.match(text) + if m: + result = SemiSemVersion( + int(m.group(1)) if m.group(1) else 0, + int(m.group(3)) if m.group(3) else 0, + int(m.group(5)) if m.group(5) else 0, + int(m.group(7)) if m.group(7) else 0) + return result + else: + msg = "Invalid version number, should be maj.min.rev+build with later " + msg += "parts optional" + raise ValueError(msg) + + +if __name__ == '__main__': + print(decode_version("1.2")) + print(decode_version("1.0")) + print(decode_version("0.0.2+75")) + print(decode_version("0.0.0+00")) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/keygen.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/keygen.py new file mode 100644 index 00000000000..f23e74a91f6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/keygen.py @@ -0,0 +1,73 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +import click +import json +from jwcrypto import jwk + +CUSTOMER_KEY_ID_MIN = 6 +CUSTOMER_KEY_ID_MAX = 10 + +kid_help = 'Key ID to define key slot number in the key storage. Key ID must be in range {}.' + +@click.command() +@click.option('-k', '--kid', 'kId', + type=click.IntRange(CUSTOMER_KEY_ID_MIN, CUSTOMER_KEY_ID_MAX), + default=CUSTOMER_KEY_ID_MIN, + help=kid_help.format(str(list(range(CUSTOMER_KEY_ID_MIN, CUSTOMER_KEY_ID_MAX+1))))) +@click.option('--jwk', 'jwKey', + type=click.File('w'), + default='key.json', + help='Name of the key in JWK format to create.') +@click.option('--pem-priv', 'pemPriv', + type=click.File('wb'), + default=None, + help='Name of the private key in PEM format to create. If it is not given PEM file will not be created.') +@click.option('--pem-pub', 'pemPub', + type=click.File('wb'), + default=None, + help='Name of the public key in PEM format to create. If it is not given PEM file will not be created.') +@click.option('--aes', 'aes', + type=click.File('w'), + default=None, + help='Name of the AES-128 key to create. If it is given only AES key wiil be created and JWK will not.') +def main(kId, jwKey, pemPriv, pemPub, aes): + if aes == None: + key = jwk.JWK.generate(kty='EC', crv='P-256', use='sig') + + keyJson = json.loads(key.export(private_key=True)) + keyJson['kid'] = str(kId) + + keyStr = json.dumps(keyJson, indent=4) + jwKey.write(keyStr) + + if pemPriv != None: + pemPriv.write(key.export_to_pem(private_key=True, password=None)) + + if pemPub != None: + pemPub.write(key.export_to_pem(private_key=False, password=None)) + + print(keyStr) + else: + key = os.urandom(16) + iv = os.urandom(16) + file = key.hex() + '\n' + iv.hex() + aes.write(file) + print('AES-128 KEY: ', key.hex(), sep='\t') + print('AES-128 IV:', iv.hex(), sep='\t') + +if __name__ == "__main__": + main() \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex 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b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/LICENSE @@ -0,0 +1,51 @@ +Copyright (c) 2018-2019 Cypress Semiconductor Corporation + +Permissive Binary License + +Version 1.0, September 2015 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named "DEPENDENCIES" and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/cy_auth.jwt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/cy_auth.jwt new file mode 100644 index 00000000000..ce5af311fca --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/cy_auth.jwt @@ -0,0 +1 @@ +eyJhbGciOiJFUzI1NiJ9.eyJhdXRoIjp7fSwiY3lfcHViX2tleSI6eyJjcnYiOiJQLTI1NiIsImtpZCI6IjMiLCJrdHkiOiJFQyIsInVzZSI6InNpZyIsIngiOiJTYjhsVHB5X3BkM05yVVRraEl6ZzJqek0zN3VOcU5pdXQ4V0MtUXYzWE1RIiwieSI6IkN0d0NpNGFyWHNqRUQ1VFZtcl92UGxQMmtlMTMzS0s3bFA3U3pfSVppREUifSwiZXhwIjoxNTc3NzQzMjAwLCJoc21fcHViX2tleSI6eyJjcnYiOiJQLTI1NiIsImtpZCI6IjQiLCJrdHkiOiJFQyIsInVzZSI6InNpZyIsIngiOiJzSk1zTi0ySm8yN2tjNTF3Vks3eEoyZlA5QkRrekFjMmZaRVpNbG9oSFhBIiwieSI6Ik1XbHV6bVhnWE92ZFFRRFlYM3l5MVRrOVFvSEwtOURaaHN3WnBZMFhlNVUifSwiaWF0IjoxNTUzNjg1NTczLCJ0eXBlIjoiQ1lfQVVUSF9IU00ifQ.oXeFYugOceM2XvnoWTEju8ByztA4OvFKrQxndIOts_nlgmRti2ddoHRGR86GMNCDfcHr54mXH33GkQ8D96DoGw \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/hsm_state.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/hsm_state.json new file mode 100644 index 00000000000..e2481709d9f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/hsm_state.json @@ -0,0 +1,18 @@ +{ + "hsm_priv_key": { + "crv": "P-256", + "d": "d-r9nPjLka7g5BHiT7OexYV7na-ofuNfjPPN4XvP_yQ", + "kty": "EC", + "use": "sig", + "x": "sJMsN-2Jo27kc51wVK7xJ2fP9BDkzAc2fZEZMlohHXA", + "y": "MWluzmXgXOvdQQDYX3yy1Tk9QoHL-9DZhswZpY0Xe5U" + }, + "hsm_pub_key": { + "crv": "P-256", + "kty": "EC", + "use": "sig", + "kid": "4", + "x": "sJMsN-2Jo27kc51wVK7xJ2fP9BDkzAc2fZEZMlohHXA", + "y": "MWluzmXgXOvdQQDYX3yy1Tk9QoHL-9DZhswZpY0Xe5U" + } +} \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/oem_state.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/oem_state.json new file mode 100644 index 00000000000..978cfbd2358 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/oem_state.json @@ -0,0 +1,18 @@ +{ + "oem_priv_key": { + "crv": "P-256", + "d": "JVozA1oRvg-zSotMUbrGebV3oBhBaF1mqUyEn_Fdcqc", + "kty": "EC", + "use": "sig", + "x": "vfb7_jewTxpFVINcXdrZQJBArC5igrN0BLc783FigrM", + "y": "9rBBUKXzpj1A5K7fxPtEaJdsfo7Jj_wsF7LTZLc-sPM" + }, + "oem_pub_key": { + "crv": "P-256", + "kty": "EC", + "use": "sig", + "kid": "5", + "x": "vfb7_jewTxpFVINcXdrZQJBArC5igrN0BLc783FigrM", + "y": "9rBBUKXzpj1A5K7fxPtEaJdsfo7Jj_wsF7LTZLc-sPM" + } +} \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/LICENSE-2.0.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/LICENSE-2.0.txt new file mode 100644 index 00000000000..7a4a3ea2424 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/LICENSE-2.0.txt @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. 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If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. 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Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. 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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/README.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/README.txt new file mode 100644 index 00000000000..3c082fb3baa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/README.txt @@ -0,0 +1,5 @@ +The following are licensed under the Apache 2.0 license: + +mcuboot +Mbed Crypto + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/MIT/cjason-license.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/MIT/cjason-license.txt new file mode 100644 index 00000000000..9b4fcd8266b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/MIT/cjason-license.txt @@ -0,0 +1,23 @@ +Copyright (c) 2009 Dave Gamble + +Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + +The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. +*/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt new file mode 100644 index 00000000000..d95796bd1b5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt @@ -0,0 +1,63 @@ +Oracle Binary Code License Agreement for the Java SE Platform Products and JavaFX + +ORACLE AMERICA, INC. ("ORACLE"), FOR AND ON BEHALF OF ITSELF AND ITS SUBSIDIARIES AND AFFILIATES UNDER COMMON CONTROL, IS WILLING TO LICENSE THE SOFTWARE TO YOU ONLY UPON THE CONDITION THAT YOU ACCEPT ALL OF THE TERMS CONTAINED IN THIS BINARY CODE LICENSE AGREEMENT AND SUPPLEMENTAL LICENSE TERMS (COLLECTIVELY "AGREEMENT"). PLEASE READ THE AGREEMENT CAREFULLY. BY SELECTING THE "ACCEPT LICENSE AGREEMENT" (OR THE EQUIVALENT) BUTTON AND/OR BY USING THE SOFTWARE YOU ACKNOWLEDGE THAT YOU HAVE READ THE TERMS AND AGREE TO THEM. IF YOU ARE AGREEING TO THESE TERMS ON BEHALF OF A COMPANY OR OTHER LEGAL ENTITY, YOU REPRESENT THAT YOU HAVE THE LEGAL AUTHORITY TO BIND THE LEGAL ENTITY TO THESE TERMS. IF YOU DO NOT HAVE SUCH AUTHORITY, OR IF YOU DO NOT WISH TO BE BOUND BY THE TERMS, THEN SELECT THE "DECLINE LICENSE AGREEMENT" (OR THE EQUIVALENT) BUTTON AND YOU MUST NOT USE THE SOFTWARE ON THIS SITE OR ANY OTHER MEDIA ON WHICH THE SOFTWARE IS CONTAINED. + +1. DEFINITIONS. "Software" means the software identified above in binary form that you selected for download, install or use (in the version You selected for download, install or use) from Oracle or its authorized licensees and/or those portions of such software produced by jlink as output using a Program’s code, when such output is in unmodified form in combination, and for sole use with, that Program, as well as any other machine readable materials (including, but not limited to, libraries, source files, header files, and data files), any updates or error corrections provided by Oracle, and any user manuals, programming guides and other documentation provided to you by Oracle under this Agreement. The Java Linker (jlink) is available with Java 9 and later versions. "General Purpose Desktop Computers and Servers" means computers, including desktop and laptop computers, or servers, used for general computing functions under end user control (such as but not specifically limited to email, general purpose Internet browsing, and office suite productivity tools). The use of Software in systems and solutions that provide dedicated functionality (other than as mentioned above) or designed for use in embedded or function-specific software applications, for example but not limited to: Software embedded in or bundled with industrial control systems, wireless mobile telephones, wireless handheld devices, kiosks, TV/STB, Blu-ray Disc devices, telematics and network control switching equipment, printers and storage management systems, and other related systems are excluded from this definition and not licensed under this Agreement. "Programs" means (a) Java technology applets and applications intended to run on the Java Platform, Standard Edition platform on Java-enabled General Purpose Desktop Computers and Servers; and (b) JavaFX technology applications intended to run on the JavaFX Runtime on JavaFX-enabled General Purpose Desktop Computers and Servers. “Java SE LIUM” means the Licensing Information User Manual – Oracle Java SE and Oracle Java Embedded Products Document accessible at http://www.oracle.com/technetwork/java/javase/documentation/index.html. “Commercial Features” means those features that are identified as such in the Java SE LIUM under the “Description of Product Editions and Permitted Features” section. + +2. LICENSE TO USE. Subject to the terms and conditions of this Agreement including, but not limited to, the Java Technology Restrictions of the Supplemental License Terms, Oracle grants you a non-exclusive, non-transferable, limited license without license fees to reproduce and use internally the Software complete and unmodified for the sole purpose of running Programs. THE LICENSE SET FORTH IN THIS SECTION 2 DOES NOT EXTEND TO THE COMMERCIAL FEATURES. YOUR RIGHTS AND OBLIGATIONS RELATED TO THE COMMERCIAL FEATURES ARE AS SET FORTH IN THE SUPPLEMENTAL TERMS ALONG WITH ADDITIONAL LICENSES FOR DEVELOPERS AND PUBLISHERS. + +3. RESTRICTIONS. Software is copyrighted. Title to Software and all associated intellectual property rights is retained by Oracle and/or its licensors. Unless enforcement is prohibited by applicable law, you may not modify, decompile, or reverse engineer Software. You acknowledge that the Software is developed for general use in a variety of information management applications; it is not developed or intended for use in any inherently dangerous applications, including applications that may create a risk of personal injury. If you use the Software in dangerous applications, then you shall be responsible to take all appropriate fail-safe, backup, redundancy, and other measures to ensure its safe use. Oracle disclaims any express or implied warranty of fitness for such uses. No right, title or interest in or to any trademark, service mark, logo or trade name of Oracle or its licensors is granted under this Agreement. Additional restrictions for developers and/or publishers licenses are set forth in the Supplemental License Terms. + +4. DISCLAIMER OF WARRANTY. THE SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND. ORACLE FURTHER DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. + +5. LIMITATION OF LIABILITY. IN NO EVENT SHALL ORACLE BE LIABLE FOR ANY INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE OR CONSEQUENTIAL DAMAGES, OR DAMAGES FOR LOSS OF PROFITS, REVENUE, DATA OR DATA USE, INCURRED BY YOU OR ANY THIRD PARTY, WHETHER IN AN ACTION IN CONTRACT OR TORT, EVEN IF ORACLE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ORACLE'S ENTIRE LIABILITY FOR DAMAGES HEREUNDER SHALL IN NO EVENT EXCEED ONE THOUSAND DOLLARS (U.S. $1,000). + +6. TERMINATION. This Agreement is effective until terminated. You may terminate this Agreement at any time by destroying all copies of Software. This Agreement will terminate immediately without notice from Oracle if you fail to comply with any provision of this Agreement. Either party may terminate this Agreement immediately should any Software become, or in either party's opinion be likely to become, the subject of a claim of infringement of any intellectual property right. Upon termination, you must destroy all copies of Software. + +7. EXPORT REGULATIONS. You agree that U.S. export control laws and other applicable export and import laws govern your use of the Software, including technical data; additional information can be found on Oracle's Global Trade Compliance web site (http://www.oracle.com/us/products/export). You agree that neither the Software nor any direct product thereof will be exported, directly, or indirectly, in violation of these laws, or will be used for any purpose prohibited by these laws including, without limitation, nuclear, chemical, or biological weapons proliferation. + +8. TRADEMARKS AND LOGOS. You acknowledge and agree as between you and Oracle that Oracle owns the ORACLE and JAVA trademarks and all ORACLE- and JAVA-related trademarks, service marks, logos and other brand designations ("Oracle Marks"), and you agree to comply with the Third Party Usage Guidelines for Oracle Trademarks currently located at http://www.oracle.com/us/legal/third-party-trademarks/index.html. Any use you make of the Oracle Marks inures to Oracle's benefit. + +9. U.S. GOVERNMENT LICENSE RIGHTS. If Software is being acquired by or on behalf of the U.S. Government or by a U.S. Government prime contractor or subcontractor (at any tier), then the Government's rights in Software and accompanying documentation shall be only those set forth in this Agreement. + +10. GOVERNING LAW. This agreement is governed by the substantive and procedural laws of California. You and Oracle agree to submit to the exclusive jurisdiction of, and venue in, the courts of San Francisco, or Santa Clara counties in California in any dispute arising out of or relating to this agreement. + +11. SEVERABILITY. If any provision of this Agreement is held to be unenforceable, this Agreement will remain in effect with the provision omitted, unless omission would frustrate the intent of the parties, in which case this Agreement will immediately terminate. + +12. INTEGRATION. This Agreement is the entire agreement between you and Oracle relating to its subject matter. It supersedes all prior or contemporaneous oral or written communications, proposals, representations and warranties and prevails over any conflicting or additional terms of any quote, order, acknowledgment, or other communication between the parties relating to its subject matter during the term of this Agreement. No modification of this Agreement will be binding, unless in writing and signed by an authorized representative of each party. + +SUPPLEMENTAL LICENSE TERMS + +These Supplemental License Terms add to or modify the terms of the Binary Code License Agreement. Capitalized terms not defined in these Supplemental Terms shall have the same meanings ascribed to them in the Binary Code License Agreement. These Supplemental Terms shall supersede any inconsistent or conflicting terms in the Binary Code License Agreement, or in any license contained within the Software. + +A. COMMERCIAL FEATURES. You may not use the Commercial Features for running Programs, Java applets or applications in your internal business operations or for any commercial or production purpose, or for any purpose other than as set forth in Sections B, C, D and E of these Supplemental Terms. If You want to use the Commercial Features for any purpose other than as permitted in this Agreement, You must obtain a separate license from Oracle. + +B. SOFTWARE INTERNAL USE FOR DEVELOPMENT LICENSE GRANT. Subject to the terms and conditions of this Agreement and restrictions and exceptions set forth in the Java SE LIUM incorporated herein by reference, including, but not limited to the Java Technology Restrictions of these Supplemental Terms, Oracle grants you a non-exclusive, non-transferable, limited license without fees to reproduce internally and use internally the Software complete and unmodified for the purpose of designing, developing, and testing your Programs. + +C. LICENSE TO DISTRIBUTE SOFTWARE. Subject to the terms and conditions of this Agreement and restrictions and exceptions set forth in the Java SE LIUM, including, but not limited to the Java Technology Restrictions and Limitations on Redistribution of these Supplemental Terms, Oracle grants you a non-exclusive, non-transferable, limited license without fees to reproduce and distribute the Software, provided that (i) you distribute the Software complete and unmodified and only bundled as part of, and for the sole purpose of running, your Programs, (ii) the Programs add significant and primary functionality to the Software, (iii) you do not distribute additional software intended to replace any component(s) of the Software, (iv) you do not remove or alter any proprietary legends or notices contained in the Software, (v) you only distribute the Software subject to a license agreement that: (a) is a complete, unmodified reproduction of this Agreement; or (b) protects Oracle's interests consistent with the terms contained in this Agreement and that includes the notice set forth in Section H, and (vi) you agree to defend and indemnify Oracle and its licensors from and against any damages, costs, liabilities, settlement amounts and/or expenses (including attorneys' fees) incurred in connection with any claim, lawsuit or action by any third party that arises or results from the use or distribution of any and all Programs and/or Software. The license set forth in this Section C does not extend to the Software identified in Section G. + +D. LICENSE TO DISTRIBUTE REDISTRIBUTABLES. Subject to the terms and conditions of this Agreement and restrictions and exceptions set forth in the Java SE LIUM, including but not limited to the Java Technology Restrictions and Limitations on Redistribution of these Supplemental Terms, Oracle grants you a non-exclusive, non-transferable, limited license without fees to reproduce and distribute those files specifically identified as redistributable in the Java SE LIUM ("Redistributables") provided that: (i) you distribute the Redistributables complete and unmodified, and only bundled as part of Programs, (ii) the Programs add significant and primary functionality to the Redistributables, (iii) you do not distribute additional software intended to supersede any component(s) of the Redistributables (unless otherwise specified in the applicable Java SE LIUM), (iv) you do not remove or alter any proprietary legends or notices contained in or on the Redistributables, (v) you only distribute the Redistributables pursuant to a license agreement that: (a) is a complete, unmodified reproduction of this Agreement; or (b) protects Oracle's interests consistent with the terms contained in the Agreement and includes the notice set forth in Section H, (vi) you agree to defend and indemnify Oracle and its licensors from and against any damages, costs, liabilities, settlement amounts and/or expenses (including attorneys' fees) incurred in connection with any claim, lawsuit or action by any third party that arises or results from the use or distribution of any and all Programs and/or Software. The license set forth in this Section D does not extend to the Software identified in Section G. + +E. DISTRIBUTION BY PUBLISHERS. This section pertains to your distribution of the JavaTM SE Development Kit Software (“JDK”) with your printed book or magazine (as those terms are commonly used in the industry) relating to Java technology ("Publication"). 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Additional copyright notices and license terms applicable to portions of the Software are set forth in the Java SE LIUM accessible at http://www.oracle.com/technetwork/java/javase/documentation/index.html. In addition to any terms and conditions of any third party opensource/freeware license identified in the Java SE LIUM, the disclaimer of warranty and limitation of liability provisions in paragraphs 4 and 5 of the Binary Code License Agreement shall apply to all Software in this distribution. + +K. TERMINATION FOR INFRINGEMENT. Either party may terminate this Agreement immediately should any Software become, or in either party's opinion be likely to become, the subject of a claim of infringement of any intellectual property right. + +L. INSTALLATION AND AUTO-UPDATE. The Software's installation and auto-update processes transmit a limited amount of data to Oracle (or its service provider) about those specific processes to help Oracle understand and optimize them. Oracle does not associate the data with personally identifiable information. You can find more information about the data Oracle collects as a result of your Software download at http://www.oracle.com/technetwork/java/javase/documentation/index.html. + +For inquiries please contact: Oracle America, Inc., 500 Oracle Parkway, + +Redwood Shores, California 94065, USA. + +Last updated 21 September 2017 \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4.json new file mode 100644 index 00000000000..3655085fe4c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4.json @@ -0,0 +1,113 @@ +{ + "debug" : + { + "m0p" : { + "permission" : "disabled", + "control" : "firmware", + "key" : 5 + }, + "m4" : { + "permission" : "allowed", + "control" : "firmware", + "key" : 5 + }, + "system" : { + "permission" : "enabled", + "control" : "firmware", + "key" : 5, + "syscall": true, + "mmio": true, + "flash": true, + "workflash": true, + "sflash": true, + "sram": true + }, + "rma" : { + "permission" : "allowed", + "destroy_fuses" : [ + { + "start" : 888, + "size" : 136 + }, + { + "start" : 648, + "size" : 104 + } + ], + "destroy_flash" : [ + { + "start" : 268435456, + "size" : 851968 + }, + { + "start" : 269483520, + "size" : 16 + } + ], + "key" : 5 + } + }, + "wounding" : + { + }, + "boot_upgrade" : + { + "title": "upgrade_policy", + "firmware": [ + { + "boot_auth": [ + 3 + ], + "id": 0, + "launch": 4, + "smif_id": 0, + "upgrade": false, + "upgrade_auth": [ + 3 + ], + "resources": [ + { + "type": "FLASH_PC1_SPM", + "address": 269287424, + "size": 65536 + }, + { + "type": "SRAM_SPM_PRIV", + "address": 134348800, + "size": 65536 + }, + { + "type": "SRAM_DAP", + "address": 134397952, + "size": 16384 + } + ] + }, + { + "boot_auth": [ + 8 + ], + "id": 4, + "monotonic": 0, + "smif_id": 0, + "upgrade": true, + "upgrade_auth": [ + 8 + ], + + "resources": [ + { + "type": "BOOT", + "address": 268435456, + "size": 327680 + }, + { + "type": "UPGRADE", + "address": 268763136, + "size": 327680 + } + ] + } + ] + } +} \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4_smif.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4_smif.json new file mode 100644 index 00000000000..9bb1f75d0e0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4_smif.json @@ -0,0 +1,115 @@ +{ + "debug" : + { + "m0p" : { + "permission" : "disabled", + "control" : "firmware", + "key" : 5 + }, + "m4" : { + "permission" : "allowed", + "control" : "firmware", + "key" : 5 + }, + "system" : { + "permission" : "enabled", + "control" : "firmware", + "key" : 5, + "syscall": true, + "mmio": true, + "flash": true, + "workflash": true, + "sflash": true, + "sram": true + }, + "rma" : { + "permission" : "allowed", + "destroy_fuses" : [ + { + "start" : 888, + "size" : 136 + }, + { + "start" : 648, + "size" : 104 + } + ], + "destroy_flash" : [ + { + "start" : 268435456, + "size" : 851968 + }, + { + "start" : 269483520, + "size" : 16 + } + ], + "key" : 5 + } + }, + "wounding" : + { + }, + "boot_upgrade" : + { + "title": "upgrade_policy", + "firmware": [ + { + "boot_auth": [ + 3 + ], + "id": 0, + "launch": 4, + "smif_id": 0, + "upgrade": false, + "upgrade_auth": [ + 3 + ], + "resources": [ + { + "type": "FLASH_PC1_SPM", + "address": 269287424, + "size": 65536 + }, + { + "type": "SRAM_SPM_PRIV", + "address": 134348800, + "size": 65536 + }, + { + "type": "SRAM_DAP", + "address": 134397952, + "size": 16384 + } + ] + }, + { + "boot_auth": [ + 8 + ], + "id": 4, + "monotonic": 0, + "smif_id": 1, + "upgrade": true, + "encrypt": false, + "encrypt_key_id": 1, + "upgrade_auth": [ + 8 + ], + + "resources": [ + { + "type": "BOOT", + "address": 268435456, + "size": 327680 + }, + { + "type": "UPGRADE", + "address": 402653184, + "size": 327680 + } + ] + } + ] + } +} \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_crypto.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_crypto.py new file mode 100644 index 00000000000..f73b4b73ee6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_crypto.py @@ -0,0 +1,116 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from jwcrypto import jwk, jws, jwt +from jwcrypto.common import base64url_decode +from jwcrypto.common import json_decode +from datetime import datetime +import json +import copy + +class crypto : + + def create_jwk() : + key = jwk.JWK.generate(kty='EC', crv='P-256', use='sig') + pub_key= json.loads( key.export(private_key=False) ) + priv_key= json.loads( key.export(private_key=True) ) + + print( "create_jwk()= " + json.dumps( pub_key, indent=4 ) ) + return priv_key,pub_key + + def create_jwt( payload , key ) : + token= jwt.JWT( header={"alg": "ES256"},claims=payload ) + token.make_signed_token( jwk.JWK( **key ) ) + txt= token.serialize(compact=True) + + print( "create_jwt()= " + json.dumps( crypto.readable_jwt(txt) ,indent=4 )) + return txt + + def readable_jwt( txt ) : + """ + Convert a JWT token in base64url into a readable dictionary object + with decoded payload and header for printing and logging + """ + lst= txt.split('.') + readable= {} + readable["protected"]= json_decode(base64url_decode(lst[0])) + readable["payload"]= json_decode(base64url_decode(lst[1])) + readable["signature"]= lst[2] + + # create readable timestamps for exp/iat claims + payload= readable["payload"] + if "iat" in payload : + t= payload["iat"] + if isinstance(t,int) : + t= datetime.fromtimestamp(t).isoformat(' ') + payload["iat"]= t + if "exp" in payload : + t= payload["exp"] + if isinstance(t,int) : + t= datetime.fromtimestamp(t).isoformat(' ') + payload["exp"]= t + + print(json.dumps(readable,indent=4,sort_keys=False)) + return readable + + def dump_jwt( txt,file_name ) : + """ + Dumps a JWT dictionary object into a text file + """ + with open(file_name,"w") as f : + f.write(txt) + f.close() + + def read_jwt( file_name ) : + """ + Reads a JWT dictionary object from a text file + """ + with open(file_name,"r") as f : + txt = f.read() + f.close() + + return txt + + def jwt_payload( txt ) : + """ + Returns the payload of a JWT without validating it's signature + Sometimes used for tokens that contain a public key in its payload, where the signature proves possesion of the corresponding private key + In that case, the payload is needed to obtain the public key with which to then validate the JWT + """ + # split the token + lst= txt.split('.') + payload= lst[1] + obj= json_decode(base64url_decode(payload)) + return obj + + def validate_jwt( txt , key ) : + """ + Validates a signed JWT + """ + try : + jwt.JWT(key=jwk.JWK(**key),jwt=txt) + print( " JWT signature is valid" ) + return True + except : + print( " JWT signature is not valid" ) + return False + + def create_x509_cert( pub_key , priv_key , prod_id , die_id=None , dev_id=None ) : + """ + TODO: create a X.509 certificate here certifying pub_key, signed with private_key + """ + cert= "CertificateToBeDone(die_id={},dev_id={},prod_id={})".format(die_id,dev_id,prod_id) + return cert + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_customer.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_customer.py new file mode 100644 index 00000000000..4433ac92d78 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_customer.py @@ -0,0 +1,50 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from cyprov_entity import Entity +from cyprov_crypto import crypto + +# Customer Entity +class CustomerEntity(Entity): + def __init__(self, state_name, audit_name) : + Entity.__init__(self, state_name, audit_name) + if "custom_priv_key" not in self.state: + d = dict() + d["custom_priv_key"] = self.state + self.state = d + + def create_entity(self, kid) : + """ + Creates the Customer entity. + Creates the Customer main key-pair and returns nothing. + """ + customer_priv_key, customer_pub_key = crypto.create_jwk() + customer_priv_key["kid"] = str(kid) + customer_pub_key["kid"] = str(kid) + self.state["custom_priv_key"] = customer_priv_key + self.state["custom_pub_key"] = customer_pub_key + self.state_loaded = True + + def get_pub_key(self): + if "custom_pub_key" not in self.state: + key = dict(self.state["custom_priv_key"]) + del key["d"] + else: + key = self.state["custom_pub_key"] + return key + + def get_priv_key(self): + return self.state["custom_priv_key"] + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_entity.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_entity.py new file mode 100644 index 00000000000..456e2ead237 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_entity.py @@ -0,0 +1,46 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import json + +# Cypress Entity +class Entity : + def __init__( self , state_name , audit_name ) : + self.state_name= state_name + self.state_loaded= False + self.audit_name= audit_name + Entity.load_state(self) + + def load_state( self ) : + try : + with open(self.state_name,"r+") as f : + self.state= json.loads(f.read()) + f.close() + self.state_loaded= True + except FileNotFoundError: + self.state= {} + self.state_loaded= False + + def save_state( self ) : + if not self.state_loaded : + raise Exception( "Internal error - state not loaded" ) + with open(self.state_name,"w") as f : + f.write( json.dumps( self.state,indent=4 ) ) + f.close() + + def append_audit_record( self,record ) : + with open(self.audit_name,"a") as f : + f.write( json.dumps(record,indent=4) + "\n" ) + f.close() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_hsm.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_hsm.py new file mode 100644 index 00000000000..f4e1789921f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_hsm.py @@ -0,0 +1,443 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +from cyprov_types import types +from cyprov_entity import Entity +from cyprov_crypto import crypto +from datetime import datetime +from datetime import timedelta + + +# HSM Entity +class HsmEntity(Entity): + def __init__(self, state_name, audit_name): + Entity.__init__(self, state_name, audit_name) + + def create_entity(self): + """ + Creates the HSM entity. + Creates the hsm_priv_key,hsm_pub_key key-pair. + """ + hsm_priv_key, hsm_pub_key = crypto.create_jwk() + self.state["hsm_priv_key"] = hsm_priv_key + self.state["hsm_pub_key"] = hsm_pub_key + + def request_disti_authorization(self): + """ + HSM creates a request for authorization to Distributor + It includes just the HSM public key and a one week expiration limit + We use a JWT to prove knowledge of the private key and convey an expiration limit + """ + hsm_priv_key = self.state["hsm_priv_key"] + hsm_pub_key = self.state["hsm_pub_key"] + + # create the request + exp = datetime.now() + timedelta(7) + payload = {} + payload["type"] = types.HSM_REQ_DISTI_AUTH + payload["hsm_pub_key"] = hsm_pub_key + payload["iat"] = int(datetime.now().timestamp()) + payload["exp"] = int(exp.timestamp()) + auth_req = crypto.create_jwt(payload, hsm_priv_key) + + # Create audit record + record = {} + record["type"] = types.HSM_REQ_DISTI_AUTH + record["iat"] = datetime.now().isoformat(' ') + record["auth_req"] = crypto.readable_jwt(auth_req) + self.append_audit_record(record) + + return auth_req + + def install_disti_auth(self, disti_auth): + """ + Install distributor authorization. + Returns nothingraise Exception( + """ + hsm_pub_key = self.state["hsm_pub_key"] + + # Validate the distributor authorization + disti_auth_payload = crypto.jwt_payload(disti_auth) + disti_pub_key = disti_auth_payload["disti_pub_key"] + if not crypto.validate_jwt(disti_auth, disti_pub_key): + raise Exception("Invalid signature for distributor authorization") + if disti_auth_payload["type"] != types.DISTI_AUTH_HSM: + raise Exception("Invalid type for distributor authorization") + if disti_auth_payload["hsm_pub_key"] != hsm_pub_key: + raise Exception("Distributor authorization is not for this HSM") + if datetime.fromtimestamp(disti_auth_payload["exp"]) < datetime.now(): + raise Exception("Distributor authorization expired") + + # install distributor key and authorization + self.state["disti_pub_key"] = disti_pub_key + self.state["disti_auth"] = disti_auth + self.state["disti_auth_readable"] = crypto.readable_jwt(disti_auth) + + # create audit record + record = {} + record["type"] = types.DISTI_AUTH_HSM + record["iat"] = datetime.now().isoformat(' ') + record["disti_auth"] = crypto.readable_jwt(disti_auth) + self.append_audit_record(record) + + def request_cy_authorization(self, cy_pub_key=None): + """ + HSM creates a request for authorization to CY + It contains the HSM public key, the distributor authorization and a 1 week expiration + The JWT proves knowledge of the private key and the distributor authorization is used by CY to identify the request + """ + hsm_priv_key = self.state["hsm_priv_key"] + hsm_pub_key = self.state["hsm_pub_key"] + disti_auth = self.state["disti_auth"] + + # create the authorization request + exp = datetime.now() + timedelta(7) + payload = {} + payload["type"] = types.HSM_REQ_CY_AUTH + payload["hsm_pub_key"] = hsm_pub_key + payload["disti_auth"] = disti_auth + payload["iat"] = int(datetime.now().timestamp()) + payload["exp"] = int(exp.timestamp()) + if cy_pub_key != None: + payload["cy_pub_key"] = cy_pub_key + auth_req = crypto.create_jwt(payload, hsm_priv_key) + + # create audit record + cy_auth_readable = crypto.readable_jwt(auth_req) + cy_auth_readable["payload"]["disti_auth"] = crypto.readable_jwt(cy_auth_readable["payload"]["disti_auth"]) + record = {} + record["type"] = types.HSM_REQ_CY_AUTH + record["iat"] = datetime.now().isoformat(' ') + record["cy_auth_req"] = cy_auth_readable + self.append_audit_record(record) + + # install the cy_pub_key if one is given (allows for explicit binding to Cypress or some other supplier) + self.state["cy_pub_key"] = cy_pub_key + + return auth_req + + def install_cy_auth(self, cy_auth, cy_pub_key=None): + """ + Install Cypress authorization. + First checks the signature on the token and then just stores it + The expiration date on the token is enforced by the HSM only (since device has not time). + The authorization privilages (which may contain serial number and/or wounding limitations) are enforced by the device. + """ + hsm_pub_key = self.state["hsm_pub_key"] + + # validate the authorization + cy_auth_payload = crypto.jwt_payload(cy_auth) + if cy_pub_key == None: + cy_pub_key = cy_auth_payload["cy_pub_key"] + elif cy_auth_payload["cy_pub_key"] != cy_pub_key: + raise Exception("Cypress authorization is not from Cypress") + if not crypto.validate_jwt(cy_auth, cy_pub_key): + raise Exception("Invalid signature for CY HSM authorization") + if cy_auth_payload["type"] != types.CY_AUTH_HSM: + raise Exception("Invalid type for CY HSM authoriation") + if datetime.fromtimestamp(cy_auth_payload["exp"]) < datetime.now(): + raise Exception("CY HSM authorization is expired") + if cy_auth_payload["cy_pub_key"] != cy_pub_key: + raise Exception("Authorization appears to be not from Cypress") + + # install the authorization + self.state["cy_pub_key"] = cy_pub_key + self.state["cy_auth"] = cy_auth + self.state["cy_auth_readable"] = crypto.readable_jwt(cy_auth) + self.state["products"] = {} + + # create audit record + record = {} + record["type"] = types.CY_AUTH_HSM + record["iat"] = datetime.now().isoformat(' ') + record["cy_auth"] = crypto.readable_jwt(cy_auth) + self.append_audit_record(record) + + def create_signing_key(self, prod_id): + """ + Creates a signing-key package that an OEM uses to create its chain of trust + One or more OEM projects may share the same signing key + An HSM can maintain multiple signing keys for multiple OEMs, identified by a string "prod_id" + HSM operator must make sure that "prod_id" is unique across all of its customers, e.g. by including the customer name or ID + """ + cy_auth = self.state["cy_auth"] + disti_auth = self.state["disti_auth"] + hsm_priv_key = self.state["hsm_priv_key"] + + # create the signing key + signing_priv_key, signing_pub_key = crypto.create_jwk() + + # create the token + exp = datetime.now() + timedelta(7) + payload = {} + payload["type"] = types.HSM_SIGNING_KEY_PKG + payload["iat"] = int(datetime.now().timestamp()) + payload["exp"] = int(exp.timestamp()) + payload["prod_id"] = prod_id + payload["signing_pub_key"] = signing_pub_key + payload["cy_auth"] = cy_auth + payload["disti_auth"] = disti_auth + signing_pkg = crypto.create_jwt(payload, hsm_priv_key) + + # store signing key for later use + prod = {} + prod["iat"] = int(datetime.now().timestamp()) + prod["signing_priv_key"] = signing_priv_key + prod["signing_pub_key"] = signing_pub_key + self.state["products"][prod_id] = prod + + # create audit record + signing_pkg_readable = crypto.readable_jwt(signing_pkg) + signing_pkg_readable["payload"]["cy_auth"] = crypto.readable_jwt(signing_pkg_readable["payload"]["cy_auth"]) + signing_pkg_readable["payload"]["disti_auth"] = crypto.readable_jwt( + signing_pkg_readable["payload"]["disti_auth"]) + record = {} + record["type"] = types.HSM_SIGNING_KEY_PKG + record["iat"] = datetime.now().isoformat(' ') + record["signing_pkg"] = signing_pkg_readable + self.append_audit_record(record) + + return signing_pkg + + def install_rot_authorization(self, rot_auth_pkg): + """ + The HSM checks the response package and the rot_auth token itself and simply stores it for later use + """ + hsm_pub_key = self.state["hsm_pub_key"] + + rot_auth_pkg_payload = crypto.jwt_payload(rot_auth_pkg) + prod_id = rot_auth_pkg_payload["prod_id"] + rot_auth = rot_auth_pkg_payload["rot_auth"] + chain_of_trust = rot_auth_pkg_payload["chain_of_trust"] + + # validate the RoT authorization + rot_auth_payload = crypto.jwt_payload(rot_auth) + oem_pub_key = rot_auth_payload["oem_pub_key"] + if not crypto.validate_jwt(rot_auth, oem_pub_key): + raise Exception("Invalid signature on OEM root-of-trust authorization") + if rot_auth_payload["type"] != types.OEM_ROT_AUTH: + raise Exception("Invalid type for OEM root-of-trust authorization") + if rot_auth_payload["hsm_pub_key"] != hsm_pub_key: + raise Exception("Invalid HSM public key in OEM root-of-trust authorization") + if rot_auth_payload["prod_id"] != prod_id: + raise Exception("Invalid prod_id in OEM root-of-trust authorization") + + # validate the package itself + if not crypto.validate_jwt(rot_auth_pkg, oem_pub_key): + raise Exception("Invalid signature on OEM root-of-trust authorization package") + if rot_auth_pkg_payload["type"] != types.OEM_ROT_AUTH_PKG: + raise Exception("Invalid type for OEM root-of-trust authorization package") + if datetime.fromtimestamp(rot_auth_pkg_payload["exp"]) < datetime.now(): + raise Exception("OEM root-of-trust authorization package is expired") + + # store the result for later usage + prod = self.state["products"][prod_id] + prod["oem_pub_key"] = oem_pub_key + prod["rot_auth"] = rot_auth + prod["rot_auth_readable"] = crypto.readable_jwt(rot_auth) + prod["chain_of_trust"] = chain_of_trust + + # create audit record + rot_auth_pkg_readable = crypto.readable_jwt(rot_auth_pkg) + rot_auth_pkg_readable["payload"]["rot_auth"] = crypto.readable_jwt(rot_auth_pkg_readable["payload"]["rot_auth"]) + record = {} + record["type"] = types.OEM_ROT_AUTH_PKG + record["iat"] = datetime.now().isoformat(' ') + record["rot_auth_pkg"] = rot_auth_pkg_readable + self.append_audit_record(record) + + def create_rot_command(self, prod_id): + """ + The cy_auth token means Cypress authorized the HSM for provisioning + The rot_auth token means that the OEM authorized the HSM to provision RoT on its behalf + Together, they form the RoT command to the device + """ + hsm_priv_key = self.state["hsm_priv_key"] + cy_auth = self.state["cy_auth"] + rot_auth = self.state["products"][prod_id]["rot_auth"] + + # check CY authorization has not expired + cy_auth_payload = crypto.jwt_payload(cy_auth) + if datetime.fromtimestamp(cy_auth_payload["exp"]) < datetime.now(): + raise Exception("Cypress authorization for HSM expired") + + # create the RoT command + payload = {} + payload["type"] = types.HSM_ROT_CMD + payload["prod_id"] = prod_id + payload["cy_auth"] = cy_auth + payload["rot_auth"] = rot_auth + rot_cmd = crypto.create_jwt(payload, hsm_priv_key) + + # create audit record + rot_cmd_readable = crypto.readable_jwt(rot_cmd) + rot_cmd_readable["payload"]["cy_auth"] = crypto.readable_jwt(rot_cmd_readable["payload"]["cy_auth"]) + rot_cmd_readable["payload"]["rot_auth"] = crypto.readable_jwt(rot_cmd_readable["payload"]["rot_auth"]) + record = {} + record["type"] = types.HSM_ROT_CMD + record["iat"] = datetime.now().isoformat() + record["rot_cmd"] = rot_cmd_readable + self.append_audit_record(record) + + return rot_cmd + + def accept_provision_authorization(self, prov_auth): + """ + Accepts a provisioning request from an OEM, that is authorized by the distributor + prov_req= jwt( payload={ OEM_PROV_REQ , blob } , key=oem_priv_key ) + prov_auth= jwt( payload={ DISTI_PROV_AUTH , prov_req , cnt , exp } , key=disti_priv_key ) + When successful 'installs' the provisioning request in the HSM as the active request for given prod_id + """ + disti_pub_key = self.state["disti_pub_key"] + + # validate the Disti's command + prov_auth_payload = crypto.jwt_payload(prov_auth) + if not crypto.validate_jwt(prov_auth, disti_pub_key): + raise Exception("Invalid signature for provisioning authorization") + if prov_auth_payload["type"] != types.DISTI_PROV_AUTH: + raise Exception("Invalid type for provisioning authorization") + prov_req = prov_auth_payload["prov_req"] + prov_req_cnt = prov_auth_payload["cnt"] + prov_req_exp = datetime.fromtimestamp(prov_auth_payload["exp"]) + + # validate the OEM's provisioning request + prov_req_payload = crypto.jwt_payload(prov_req) + prod_id = prov_req_payload["prod_id"] + oem_pub_key = self.state["products"][prod_id]["oem_pub_key"] + if not crypto.validate_jwt(prov_req, oem_pub_key): + raise Exception("Invalid signature for provisioning request") + + # install the provisioning request for execution + prod = self.state["products"][prod_id] + prod["prov_req"] = prov_req + prod["prov_req_readable"] = crypto.readable_jwt(prov_req) + prod["prov_req_cnt"] = prov_req_cnt + prod["prov_req_exp"] = int(prov_req_exp.timestamp()) + + # create audit record + record = {} + record["type"] = types.DISTI_PROV_AUTH + record["iat"] = datetime.now().isoformat(' ') + record["prod_id"] = prod_id + record["prov_req"] = crypto.readable_jwt(prov_req) + self.append_audit_record(record) + + def create_provision_cmd(self, prod_id, dev_rsp, image_jwt_file): + """ + Creates and returns a provisioning command prov_cmd that can be send to a device. + prov_req= jwt( payload={ OEM_PROV_REQ , blob } , key=oem_priv_key ) + chain_of_trust= [ x509_certs ] + hsm_auth= jwt( payload={ CY_HSM_AUTH , hsm_pub_key , auth } , key=cy_priv_key ) + prov_cmd= jwt( payload={ HSM_PROV_CMD , prov_req , chain_of_trust , hsm_auth } , key=hsm_priv_key ) + Requires the device response to the RoT command (which contains the device identity and keys). + dev_rsp= jwt( payload= { DEV_ROT_RSP , prod_id,die_id,dev_id, dev_pub_key } , key=dev_priv_key ) + There must be an active provisioning request in the HSM for the given product ID. + """ + prod = self.state["products"][prod_id] + oem_pub_key = prod["oem_pub_key"] + signing_priv_key = prod["signing_priv_key"] + chain_of_trust = prod["chain_of_trust"] + prov_req = prod["prov_req"] + prov_req_cnt = prod["prov_req_cnt"] + prov_req_exp = datetime.fromtimestamp(prod["prov_req_exp"]) + hsm_priv_key = self.state["hsm_priv_key"] + cy_auth = self.state["cy_auth"] + image_cert = crypto.read_jwt(image_jwt_file) + + # validate the OEM's provisioning request + if prov_req_exp < datetime.now(): + raise Exception("Provisioning request expired") + if prov_req_cnt <= 0: + raise Exception("Provisioning request count exceeded") + prov_req_cnt -= 1; + + # validate the device response + dev_rsp_payload = crypto.jwt_payload(dev_rsp) + dev_pub_key = dev_rsp_payload["dev_pub_key"] + die_id = dev_rsp_payload["die_id"] + dev_id = dev_rsp_payload["dev_id"] + if dev_rsp_payload["prod_id"] != prod_id: + raise Exception("Product ID in provision request does not match device (" + prod_id + ")") + if not crypto.validate_jwt(dev_rsp, dev_pub_key): + raise Exception("Invalid signature on device response to RoT command") + + # create the device chain of trust (X509) + dev_cert = crypto.create_x509_cert(prod_id=prod_id, die_id=die_id, dev_id=dev_id, pub_key=dev_pub_key, + priv_key=signing_priv_key) + chain_of_trust = chain_of_trust + [dev_cert] + + # create the provisioning command + payload = {} + payload["type"] = types.HSM_PROV_CMD + payload["prov_req"] = prov_req + payload["image_cert"] = image_cert + payload["chain_of_trust"] = chain_of_trust + payload["cy_auth"] = cy_auth + prov_cmd = crypto.create_jwt(payload, hsm_priv_key) + + # create audit record + prov_cmd_readable = crypto.readable_jwt(prov_cmd) + prov_cmd_readable["payload"]["cy_auth"] = crypto.readable_jwt(prov_cmd_readable["payload"]["cy_auth"]) + prov_cmd_readable["payload"]["prov_req"] = crypto.readable_jwt(prov_cmd_readable["payload"]["prov_req"]) + prov_cmd_readable["payload"]["image_cert"] = crypto.readable_jwt(prov_cmd_readable["payload"]["image_cert"]) + record = {} + record["type"] = types.HSM_PROV_CMD + record["iat"] = datetime.now().isoformat(' ') + record["prod_id"] = prod_id + record["dev_rsp"] = crypto.readable_jwt(dev_rsp) + record["prov_cmd"] = prov_cmd_readable + self.append_audit_record(record) + + self.state["products"][prod_id]["prov_req_cnt"] = prov_req_cnt + return prov_cmd + + def pack_rot_command(self, prod_id, cy_auth_file, rot_auth): + payload = {} + + payload['type'] = types.HSM_ROT_CMD + payload['prod_id'] = prod_id + payload['cy_auth'] = crypto.read_jwt(cy_auth_file) + payload['rot_auth'] = rot_auth + + hsm_priv_key = self.state["hsm_priv_key"] + rot_cmd = crypto.create_jwt(payload, hsm_priv_key) + + return rot_cmd + + def pack_provision_cmd(self, **kwargs): + payload = {} + print(kwargs) + + if kwargs is not None: + for k, v in kwargs.items(): + if type(v) is tuple: + sequence = [] + for cert_file in v: + with open(cert_file) as cert: + sequence.append(cert.read()) + payload[k] = sequence + else: + if os.path.isfile(v): + payload[k] = crypto.read_jwt(v) + else: + payload[k] = v + + payload['type'] = types.HSM_PROV_CMD + + hsm_priv_key = self.state['hsm_priv_key'] + prov_cmd = crypto.create_jwt(payload, hsm_priv_key) + + return prov_cmd diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_oem.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_oem.py new file mode 100644 index 00000000000..ae418abda5b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_oem.py @@ -0,0 +1,143 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from cyprov_entity import Entity +from cyprov_crypto import crypto +from cyprov_types import types +from datetime import datetime +from datetime import timedelta + +# Oem (Customr) Entity +class OemEntity(Entity) : + def __init__( self , state_name , audit_name ) : + Entity.__init__(self,state_name,audit_name) + + def create_entity( self , chain_of_trust=[] ) : + """ + Creates the Oem entity. + Creates the Oem main key-pair and returns nothing. + """ + oem_priv_key,oem_pub_key= crypto.create_jwk() + self.state["oem_priv_key"]= oem_priv_key + self.state["oem_pub_key"]= oem_pub_key + self.state["oem_chain_of_trust"]= chain_of_trust + + def create_rot_authorization( self , signing_pkg ) : + """ + OEM creates a root-of-trust authorization package based on the signing key package from the HSM + It's a JWT with two main parts: + - a rot_auth authorization token that is sent to the device + - a chain of X509 certificates that establishses the OEM's trust in the HSM signing key + Note that this chain is not used inside the device and used only by 3rd parties + """ + oem_pub_key= self.state["oem_pub_key"] + oem_priv_key= self.state["oem_priv_key"] + oem_chain_of_trust= self.state["oem_chain_of_trust"] + + # get HSM public key and check CY authorization + signing_pkg_payload= crypto.jwt_payload(signing_pkg) + cy_auth= signing_pkg_payload["cy_auth"] + cy_auth_payload= crypto.jwt_payload(cy_auth) + cy_pub_key= cy_auth_payload["cy_pub_key"] + hsm_pub_key= cy_auth_payload["hsm_pub_key"] + if not crypto.validate_jwt( cy_auth , cy_pub_key ) : + raise Exception( "Invalid signature on Cypress HSM authorization in request" ) + if cy_auth_payload["type"] != types.CY_AUTH_HSM : + raise Exception( "Invalid type for Cypress HSM authorization in request" ) + if datetime.fromtimestamp(cy_auth_payload["exp"]) < datetime.now() : + raise Exception( "Cypress HSM authorization expired" ) + + # validate HSM request itself + signing_pub_key= signing_pkg_payload["signing_pub_key"] + prod_id= signing_pkg_payload["prod_id"] + if not crypto.validate_jwt( signing_pkg , hsm_pub_key ) : + raise Exception( "Invalid signature on HSM signing key package" ) + if signing_pkg_payload["type"] != types.HSM_SIGNING_KEY_PKG : + raise Exception( "Invalid type on HSM signing key package" ) + if datetime.fromtimestamp(signing_pkg_payload["exp"]) < datetime.now() : + raise Exception( "HSM signing key package expired" ) + + # create the RoT transfer authorization (that will go to the device) + payload= {} + payload["type"]= types.OEM_ROT_AUTH + payload["oem_pub_key"]= oem_pub_key + payload["hsm_pub_key"]= hsm_pub_key + payload["prod_id"]= prod_id + payload["iat"]= int(datetime.now().timestamp()) + rot_auth= crypto.create_jwt( payload , oem_priv_key ) + + # create the chain of trust + cert= crypto.create_x509_cert( signing_pub_key , oem_priv_key , prod_id ) + chain_of_trust= oem_chain_of_trust + [ cert ] + + # create the response + exp= datetime.now() + timedelta(7) + payload= {} + payload["type"]= types.OEM_ROT_AUTH_PKG + payload["iat"]= int(datetime.now().timestamp()) + payload["exp"]= int(exp.timestamp()) + payload["prod_id"]= prod_id + payload["rot_auth"]= rot_auth + payload["chain_of_trust"]= chain_of_trust + rot_auth_pkg= crypto.create_jwt( payload , oem_priv_key ) + + # create audit record + signing_pkg_readable= crypto.readable_jwt(signing_pkg) + signing_pkg_readable["payload"]["cy_auth"]= crypto.readable_jwt(signing_pkg_readable["payload"]["cy_auth"]) + signing_pkg_readable["payload"]["disti_auth"]= crypto.readable_jwt(signing_pkg_readable["payload"]["disti_auth"]) + rot_auth_pkg_readable= crypto.readable_jwt(rot_auth_pkg) + rot_auth_pkg_readable["payload"]["rot_auth"]= crypto.readable_jwt(rot_auth_pkg_readable["payload"]["rot_auth"]) + record= {} + record["type"]= types.OEM_ROT_AUTH_PKG + record["iat"]= datetime.now().isoformat(' ') + record["signing_pkg"]= signing_pkg_readable + record["rot_auth_pkg"]= rot_auth_pkg_readable + self.append_audit_record(record) + + return rot_auth_pkg + + def create_provision_request( self , blob ) : + """ + The OEM can create a request for provisioning by signing a keys & policies blob with its private key + Note that blob must contain at least the prod_id field + """ + # create the request + oem_priv_key= self.state["oem_priv_key"] + prov_req= crypto.create_jwt( blob , oem_priv_key ) + + # create audit record + record= {} + record["type"]= types.OEM_PROV_REQ + record["iat"]= datetime.now().isoformat(' ') + record["prod_id"]= blob["prod_id"] + record["prov_req"]= crypto.readable_jwt(prov_req) + self.append_audit_record(record) + + return prov_req + + def pack_rot_auth( self, prod_id, hsm_pub_key ): + oem_pub_key = self.state["oem_pub_key"] + oem_priv_key = self.state["oem_priv_key"] + + payload= {} + payload["type"] = types.OEM_ROT_AUTH + payload["oem_pub_key"] = oem_pub_key + payload["hsm_pub_key"] = hsm_pub_key + payload["prod_id"] = prod_id + payload["iat"] = int(datetime.now().timestamp()) + rot_auth = crypto.create_jwt( payload , oem_priv_key ) + + return rot_auth + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_pem.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_pem.py new file mode 100644 index 00000000000..42f9bc4d967 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_pem.py @@ -0,0 +1,79 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from jwcrypto import jwk +import json + +def pretty_search(dict_or_list, key_to_search, search_for_first_only=False): + """ + Give it a dict or a list of dicts and a dict key (to get values of), + it will search through it and all containing dicts and arrays + for all values of dict key you gave, and will return you set of them + unless you wont specify search_for_first_only=True + + :param dict_or_list: + :param key_to_search: + :param search_for_first_only: + :return: + """ + search_result = set() + if isinstance(dict_or_list, dict): + for key in dict_or_list: + key_value = dict_or_list[key] + if key == key_to_search: + if search_for_first_only: + return key_value + else: + search_result.add(key_value) + if isinstance(key_value, dict) or isinstance(key_value, list) or isinstance(key_value, set): + _search_result = pretty_search(key_value, key_to_search, search_for_first_only) + if _search_result and search_for_first_only: + return _search_result + elif _search_result: + for result in _search_result: + search_result.add(result) + elif isinstance(dict_or_list, list) or isinstance(dict_or_list, set): + for element in dict_or_list: + if isinstance(element, list) or isinstance(element, set) or isinstance(element, dict): + _search_result = pretty_search(element, key_to_search, search_result) + if _search_result and search_for_first_only: + return _search_result + elif _search_result: + for result in _search_result: + search_result.add(result) + return search_result if search_result else None + +class PemKey: + + def __init__(self, jwk_file = None, item = None): + if jwk_file != None: + with open(jwk_file) as f: + jwk_str = f.read() + self.jwk = json.loads(jwk_str) + + if item != None: + self.jwk = pretty_search(self.jwk, item, search_for_first_only=True) + + def save(self, file = None, private_key=False): + key = jwk.JWK(**self.jwk) + pem_str = key.export_to_pem(private_key, password=None) + if file != None: + with open(file, 'wb') as f: + f.write(pem_str) + else: + print(pem_str) + + def load(self, jwk): + self.jwk = jwk diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_types.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_types.py new file mode 100644 index 00000000000..f5aa542f0da --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_types.py @@ -0,0 +1,29 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +class types : + HSM_REQ_DISTI_AUTH= "HSM_REQ_DISTI_AUTH" + DISTI_AUTH_HSM= "DISTI_AUTH_HSM" + HSM_REQ_CY_AUTH= "HSM_REQ_CY_AUTH" + CY_AUTH_HSM= "CY_AUTH_HSM" + HSM_SIGNING_KEY_PKG= "HSM_SIGNING_KEY_PKG" + OEM_ROT_AUTH= "OEM_ROT_AUTH" + OEM_ROT_AUTH_PKG= "OEM_ROT_AUTH_PKG" + OEM_PROV_REQ= "OEM_PROV_REQ" + DISTI_PROV_AUTH= "DISTI_PROV_AUTH" + CY_DEV_ID= "CY_DEV_ID" + HSM_ROT_CMD= "HSM_ROT_CMD" + HSM_PROV_CMD= "HSM_PROV_CMD" + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_packet.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_packet.py new file mode 100644 index 00000000000..75e98e29cf5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_packet.py @@ -0,0 +1,133 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +import sys +import json +import click + +# Default input values and pathes +PROD_NAME = 'my_thing' +CYPROV_LIB_PATH = './provisioning_lib' + +# Default output values and pathes +OEM_AUDIT_NAME = 'oem_log.json' +HSM_AUDIT_NAME = 'hsm_log.json' +PROV_REQ_JWT_FILE = 'prov_req.jwt' +ROT_AUTH_JWT_FILE = 'rot_auth.jwt' +PROV_JWT_FILE = 'prov_cmd.jwt' + +CUSTOMER_KEY_N = 5 + +sys.path.insert(0, CYPROV_LIB_PATH) +from cyprov_hsm import HsmEntity +from cyprov_oem import OemEntity +from cyprov_customer import CustomerEntity +from cyprov_crypto import crypto + + +def process_customer_keys(paths): + customer_key_n = len(paths) + customer = [] + if customer_key_n > 0: + customer_key_id = 6 + for i in range(customer_key_n): + customer_log = os.path.basename(paths[i]) + customer_log = os.path.splitext(customer_log)[0] + '_log.json' + customer.append(CustomerEntity(paths[i], customer_log)) + if not customer[i].state_loaded: + customer[i].create_entity(customer_key_id + i) + customer[i].save_state() + return customer + + +@click.command() +@click.option('--oem', 'oem_state_path', + default='../prebuild/oem_state.json', + help='OEM key file.') +@click.option('--hsm', 'hsm_state_path', + default='../prebuild/hsm_state.json', + help='HSM key file.') +@click.option('--cyboot', 'image_cert', + default='../prebuild/CypressBootloader_CM0p.jwt', + help='Cypress Bootloader image certificate.') +@click.option('--cyauth', 'cy_auth_path', + default='../prebuild/cy_auth.jwt', + help='Provisioning authorization certificate.') +@click.option('--policy', 'policy_path', + default='policy_single_stage_CM4.json', + help='Policy file.') +@click.option('--out', 'output_path', + default='../packet', + help='Output directory.') +@click.option('--ckey', 'cust_key_path', + default=None, + multiple=True, + help='Customer key that will be used for image signing. Use the option multiple times ' + 'to specify multiple keys.') +@click.option('--devcert', 'dev_cert', + default=[], + multiple=True, + help='Chain of trust certificate. Use the option multiple times to specify multiple certificates.') +def main(oem_state_path, hsm_state_path, image_cert, cy_auth_path, + policy_path, output_path, cust_key_path, dev_cert): + + if len(cust_key_path) > CUSTOMER_KEY_N: + raise Exception('Maximum number of customer keys must be {}!'.format(CUSTOMER_KEY_N)) + + prod_id = PROD_NAME + + oem_audit_path = os.path.join(output_path, OEM_AUDIT_NAME) + hsm_audit_path = os.path.join(output_path, HSM_AUDIT_NAME) + prov_req_jwt_path = os.path.join(output_path, PROV_REQ_JWT_FILE) + rot_auth_jwt_path = os.path.join(output_path, ROT_AUTH_JWT_FILE) + prov_jwt_path = os.path.join(output_path, PROV_JWT_FILE) + + if not os.path.exists(output_path): + os.makedirs(output_path) + + oem = OemEntity(oem_state_path, oem_audit_path) + hsm = HsmEntity(hsm_state_path, hsm_audit_path) + + with open(policy_path) as f: + json_str = f.read() + blob = json.loads(json_str) + blob['prod_id'] = prod_id + + customer = process_customer_keys(cust_key_path) + if len(customer) > 0: + blob['custom_pub_key'] = [key.get_pub_key() for key in customer] + + prov_req = oem.create_provision_request(blob) + crypto.dump_jwt(prov_req, prov_req_jwt_path) + + rot_auth_pkg = oem.pack_rot_auth(prod_id, hsm.state["hsm_pub_key"]) + crypto.dump_jwt(rot_auth_pkg, rot_auth_jwt_path) + + prov_cmd = hsm.pack_provision_cmd( + cy_auth=cy_auth_path, + image_cert=image_cert, + prov_req=prov_req, + rot_auth=rot_auth_pkg, + chain_of_trust=dev_cert) + crypto.dump_jwt(prov_cmd, prov_jwt_path) + + print('#' * 80) + print('Provisioning packet is created') + print('#' * 80) + + +if __name__ == "__main__": + main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/provision_device_runner.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/provision_device_runner.py new file mode 100644 index 00000000000..6b4c8282a29 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/provision_device_runner.py @@ -0,0 +1,80 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +import sys +import click +from execute.helper import get_target_name +from execute.enums import DebugCore +from execute.provision_device import provision_execution +from execute.programmer.programmer import ProgrammingTool +from prepare.provisioning_lib.cyprov_pem import PemKey + + +TOOL_NAME = 'pyocd' # Programming/debugging tool used for communication with device +ACCESS_PORT = DebugCore.debug_sys_ap # Access port used for device provisioning + + +@click.command() +@click.option('--prov-jwt', 'prov_cmd_jwt', + default='packet/prov_cmd.jwt', + type=click.STRING, + help='Path to provisioning JWT file (packet which contains all data necessary ' + 'for provisioning, including policy, authorization packets and keys)') +@click.option('--hex', 'cy_bootloader_hex', + default='prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex', + type=click.STRING, + help='Path to Cypress Bootloader HEX binary file') +@click.option('--pubkey-json', 'pub_key_json', + default='keys/dev_pub_key.json', + type=click.STRING, + help='File where to save public key in JSON format') +@click.option('--pubkey-pem', 'pub_key_pem', + default='keys/dev_pub_key.pem', + type=click.STRING, + help='File where to save public key in PEM format') +def main(prov_cmd_jwt, cy_bootloader_hex, pub_key_json, pub_key_pem): + """ + Parses command line arguments and provides high level support for + provisioning device with the specified programming tool. + :param prov_cmd_jwt: Path to provisioning JWT file (packet which contains + all data necessary for provisioning, including policy, authorization + packets and keys). + :param cy_bootloader_hex: Path to Cypress Bootloader program file. + :param pub_key_json: File where to save public key in JSON format. + :param pub_key_pem: File where to save public key in PEM format. + """ + # Verify arguments + target = get_target_name(TOOL_NAME, ACCESS_PORT) + if not target: + print('Invalid access port.') + sys.exit(1) + + test_status = False + tool = ProgrammingTool.create(TOOL_NAME) + if tool.connect(target): + test_status = provision_execution(tool, pub_key_json, prov_cmd_jwt, cy_bootloader_hex) + + if test_status: + # Read device response file and take device key from it + if os.path.exists(pub_key_json): + pem = PemKey(pub_key_json) + pem.save(pub_key_pem, private_key=False) + else: + sys.exit(1) + + +if __name__ == "__main__": + main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/requirements.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/requirements.txt new file mode 100644 index 00000000000..c24d45be803 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/requirements.txt @@ -0,0 +1,7 @@ +# To install next python modules, please execute command: +# python -m pip install -r requirements.txt + +cryptography>=2.4.2 +Click>=7.0 +intelhex>=2.2.1 +jwcrypto>=0.6.0 \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_large.hex b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_large.hex new file mode 100644 index 00000000000..3b8fa29b367 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_large.hex @@ -0,0 +1,1410 @@ +:020000041000EA +:20000000000100083101001000000000000000000000000000000000000000000000000095 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+:40024000FFF79EFF1F23019A9A4303D0D4211048FFF796FF012211001540B140B5400F203B6804408B431D433D600500B1008D408C40084B31001B68380063331A78BA18AE +:400280001368AB431C431460019AFFF787FFF7BD100400103C1000080230800803D001300238FCD1C046C0467047EFF3108072B6704780F310887047000052E3011041E2BB +:4002C00000C0A0E11EFF2F0110402DE90C30A0E101E0F1E500005EE3014042E201E0C3E40400001A02C08CE00C0053E10500000A01E0C3E4FBFFFFEA000054E303C0A0E1E7 +:400300000420A0E1F0FFFF1A1040BDE81EFF2FE10DC0A0E1F8DF2DE904B04CE20DC0A0E1F8DF2DE904B04CE200002140000025400000014000003440000024400000314064 +:400340000000324000001F4101010101010101010110101080550501053B04101C0101000FC000000000100001010101011D3A577896000820000010000F002000023F06D7 +:40038000080E00080009000A000B24282C303400100000009000000088000000080000008000000004F0000000F000002005A000D00100018001A0011000000004000000C4 +:4003C000400000004400000048000000800000000001000010020000880200000004000010040000200400004004000048040000800400008404000090040000C0070000E1 +:40040000C4070000C8070000CC070000004000002E2F68616C2F70646C2F647269766572732F736F757263652F63795F6770696F2E63002E2F68616C2F70646C2F64726907 +:40044000766572732F696E636C7564652F63795F6770696F2E68000000000000000000000000000000000000000000000000000000000000000000000000000000000000FA +:40048000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003C +:4004C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FC +:4005000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000BB +:40054000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007B +:40058000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B +:4005C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FB +:0200000490303A +:02000000FF3BC4 +:0200000490501A +:0C00000000000000000000000000FF3BBA +:00000001FF \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_pyocd_wrapper.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_pyocd_wrapper.py new file mode 100644 index 00000000000..a7365399832 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_pyocd_wrapper.py @@ -0,0 +1,301 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import sys +import os.path +import time +import unittest +from intelhex import IntelHex +sys.path.append(os.path.dirname(os.path.realpath(__file__))) +sys.path.append(os.path.dirname('../execute')) +from test_utility import * +from execute.programmer.programmer import ProgrammingTool +from execute.programmer.exceptions import ExtendedTransferFaultError + +TOOL = 'pyocd' +TARGET = 'cy8c64xx_cm4' +PROBE_ID = '19071301d90e140c00d90e1400000000000000002e127069' # DAP-Link +#PROBE_ID = '1A06199701047400' # CMSIS-DAP + +# PSoC6 BLE Memory Regions +RAM_ADDR = 0x08000000 +MAIN_ADDR = 0x10000000 +WORK_ADDR = 0x14000000 +SFLASH_ADDR = 0x16000000 + +# PSoC6 Register Addresses +CYREG_IPC2_STRUCT_ACQUIRE = 0x40230040 +CYREG_IPC2_STRUCT_DATA = 0x4023004c +CYREG_IPC2_STRUCT_NOTIFY = 0x40230048 +CYREG_GPIO_PORT_11_OUT = 0x40320580 +CYREG_CM4_POWER_CTRL = 0x40210080 +ENTRANCE_EXAM_SRAM_ADDR = 0x0802E000 +# Debug halting control and status register +CYREG_DHCSR = 0xE000EDF0 +S_HALT = (1 << 17) +S_LOCKUP = (1 << 19) + + +class TestReadWrite(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.tool = ProgrammingTool.create(TOOL) + cls.tool.connect(TARGET, probe_id=PROBE_ID) + create_test_bin() + print('[INFO] Program Main region with test data') + cls.tool.program(TEST_BIN, address=MAIN_ADDR) + print('[INFO] Program Work region with test data') + cls.tool.program(TEST_BIN, address=WORK_ADDR) + + @classmethod + def tearDownClass(cls): + cls.tool.disconnect() + + def test_read8_ram(self): + data = self.tool.read8(RAM_ADDR) + self.assertGreaterEqual(data, 0) + + def test_read8_flash_main_region(self): + data = self.tool.read8(MAIN_ADDR) + self.assertEqual(data, 0x41) + + def test_read8_flash_work_region(self): + data = self.tool.read8(WORK_ADDR) + self.assertEqual(data, 0x41) + + def test_read8_sflash(self): + data = self.tool.read8(SFLASH_ADDR) + self.assertEqual(data, 0x00) + + def test_read8_register32_negative(self): + with self.assertRaises(ExtendedTransferFaultError) as context: + self.tool.read8(CYREG_IPC2_STRUCT_DATA) + self.assertTrue('If address points to a register it should be aligned with the register size' + in str(context.exception)) + + def test_read16_ram(self): + data = self.tool.read16(RAM_ADDR) + self.assertGreater(data, 0) + + def test_read16_flash_main_region(self): + data = self.tool.read16(MAIN_ADDR) + self.assertEqual(data, 0x3141) + + def test_read16_flash_work_region(self): + data = self.tool.read16(WORK_ADDR) + self.assertEqual(data, 0x3141) + + def test_read16_register32_negative(self): + with self.assertRaises(ExtendedTransferFaultError) as context: + self.tool.read16(CYREG_IPC2_STRUCT_DATA) + self.assertTrue('If address points to a register it should be aligned with the register size' + in str(context.exception)) + + def test_read32_ram(self): + data = self.tool.read32(RAM_ADDR) + self.assertGreater(data, 0x00) + + def test_read32_flash_main_region(self): + data = self.tool.read32(MAIN_ADDR) + self.assertEqual(data, 0x32413141) + + def test_read32_not_exists_flash_region(self): + with self.assertRaises(ExtendedTransferFaultError): + self.tool.read32(0xFF00FF00) + + def test_read32_flash_work_region(self): + data = self.tool.read32(WORK_ADDR) + self.assertEqual(data, 0x32413141) + + def test_read32_register32(self): + data = self.tool.read32(CYREG_IPC2_STRUCT_DATA) + self.assertGreaterEqual(data, 0x00000000) + + def test_write8_ram(self): + self.tool.write8(RAM_ADDR, 0xCE) + data = self.tool.read8(RAM_ADDR) + self.assertEqual(0xCE, data) + + def test_write16_ram(self): + self.tool.write16(RAM_ADDR, 0xAC21) + data = self.tool.read16(RAM_ADDR) + self.assertEqual(0xAC21, data) + + def test_write32_ram(self): + self.tool.write32(RAM_ADDR, 0xDEADBEAF) + data = self.tool.read32(RAM_ADDR) + self.assertEqual(data, 0xDEADBEAF) + + def test_write32_CYREG_IPC2_STRUCT_ACQUIRE(self): + self.tool.write32(CYREG_IPC2_STRUCT_ACQUIRE, 0x80000000) + data = self.tool.read32(CYREG_IPC2_STRUCT_ACQUIRE) + byte = decomposite32(data)[3] + self.assertEqual(byte, 0x80) + + def test_write32_CYREG_IPC2_STRUCT_DATA(self): + self.tool.write32(CYREG_IPC2_STRUCT_DATA, 0xAFECAB91) + data = self.tool.read32(CYREG_IPC2_STRUCT_DATA) + self.assertEqual(data, 0xAFECAB91) + + def test_write32_CYREG_IPC2_STRUCT_NOTIFY(self): + self.tool.write32(CYREG_IPC2_STRUCT_NOTIFY, 0x00000001) + data = self.tool.read32(CYREG_IPC2_STRUCT_NOTIFY) + byte = decomposite32(data)[3] + self.assertEqual(byte, 0x00) + + def test_write32_ENTRANCE_EXAM_SRAM_ADDR(self): + self.tool.write32(ENTRANCE_EXAM_SRAM_ADDR, 0xD1A2B3C4) + data = self.tool.read32(ENTRANCE_EXAM_SRAM_ADDR) + self.assertEqual(data, 0xD1A2B3C4) + + def test_write32_ENTRANCE_EXAM_SRAM_ADDR_offset4(self): + self.tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x04, 0xABCABCFA) + data = self.tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x04) + self.assertEqual(data, 0xABCABCFA) + + def test_write32_ENTRANCE_EXAM_SRAM_ADDR_offset8(self): + self.tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x08, 0x12890735) + data = self.tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x08) + self.assertEqual(data, 0x12890735) + + def tet_read_write_core_regs(self): + value1 = self.tool.read_reg('r1') + self.tool.write_reg('r1', value1 + 10) + value2 = self.tool.read_reg('r1') + self.assertEqual(value1 + 10, value2) + + def test_read_strange_reg_negative(self): + with self.assertRaises(ValueError): + self.tool.read_reg('r200') + + +class TestProgramming(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.tool = ProgrammingTool.create(TOOL) + cls.tool.connect(TARGET, probe_id=PROBE_ID) + create_test_bin() + + @classmethod + def tearDownClass(cls): + cls.tool.disconnect() + + def test_erase(self): + self.tool.erase(MAIN_ADDR, 0x200) + match = False + i = 0 + while i < os.path.getsize(TEST_BIN): + data = self.tool.read8(MAIN_ADDR + i) + match = data == 0x00 + if not match: + break + i += 1 + self.assertTrue(match) + + def test_program_bin(self): + self.tool.erase(MAIN_ADDR, 0x200) + self.tool.program(TEST_BIN, address=MAIN_ADDR) + with open(TEST_BIN, 'rb') as file_obj: + exp_data = file_obj.read() + match = False + i = 0 + while i < len(exp_data): + data = self.tool.read8(MAIN_ADDR + i) + match = data == exp_data[i] + if not match: + break + i += 1 + self.assertTrue(match) + + def test_program_hex(self): + intel_hex = IntelHex() + intel_hex.loadhex(BLINKY_SMALL_HEX) + arr = intel_hex.gets(MAIN_ADDR, 0x400) + self.tool.erase(MAIN_ADDR, 0x400) + self.tool.program(BLINKY_SMALL_HEX) + match = False + i = 0 + while i < len(arr): + data = self.tool.read8(MAIN_ADDR + i) + match = data == arr[i] + if not match: + break + i += 1 + self.assertTrue(match) + + +class TestControlAPIs(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.tool = ProgrammingTool.create(TOOL) + cls.tool.connect(TARGET, probe_id=PROBE_ID) + + @classmethod + def tearDownClass(cls): + cls.tool.disconnect() + + def test_reset(self): + self.tool.write32(CYREG_GPIO_PORT_11_OUT, 0xDEADBEAF) + self.tool.reset() + self.assertEqual(self.tool.read32(CYREG_GPIO_PORT_11_OUT), 0x00) + + def test_halt_resume(self): + self.tool.reset() + if self.tool.read32(CYREG_CM4_POWER_CTRL) & 3 != 3: + self.tool.write32(CYREG_CM4_POWER_CTRL, 0x05fa0003) # CM4 is sleeping, trying to wake it up + dhcsr = self.tool.read32(CYREG_DHCSR) + if dhcsr & S_LOCKUP: + self.tool.halt() + dhcsr = self.tool.read32(CYREG_DHCSR) + self.tool.write_reg('xpsr', 0x01000000) # set thumb bit + else: + self.tool.halt() + dhcsr = self.tool.read32(CYREG_DHCSR) + self.assertTrue(dhcsr & S_HALT) + self.tool.resume() + dhcsr = self.tool.read32(CYREG_DHCSR) + self.assertFalse(dhcsr & S_HALT) + + #def test_reset_and_halt(self): + # self.tool.write32(CYREG_GPIO_PORT_11_OUT, 0xDEADBEAF) + # self.tool.reset_and_halt() + # self.assertEqual(self.tool.read32(CYREG_GPIO_PORT_11_OUT), 0x00) + # dhcsr = self.tool.read32(CYREG_DHCSR) + # self.assertTrue(dhcsr & S_HALT) + + @unittest.skip("HW frequency cannot be changed.") + def test_set_frequency(self): + self.tool.erase(MAIN_ADDR, 0xC000) + self.tool.set_frequency(100) + time_before_program = time.time() + self.tool.program(BLINKY_LARGE_HEX) + time1 = time.time() - time_before_program + self.tool.set_frequency(1200) + self.tool.erase(MAIN_ADDR, 0xC000) + time_before_program = time.time() + self.tool.program(BLINKY_LARGE_HEX) + time2 = time.time() - time_before_program + self.assertGreater(time1, time2) + + def test_connection(self): + self.tool.disconnect() + self.assertFalse(self.tool.session.is_open) + self.tool.connect(TARGET, probe_id=PROBE_ID) + self.assertTrue(self.tool.session.is_open) + + +if __name__ == '__main__': + ret = not unittest.main().wasSuccessful() + sys.exit(ret) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_utility.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_utility.py new file mode 100644 index 00000000000..ab890078539 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_utility.py @@ -0,0 +1,39 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +TEST_BIN = "test_data/test.bin" +BLINKY_SMALL_HEX = "test_data/blinky_small.hex" +BLINKY_LARGE_HEX = "test_data/blinky_large.hex" + + +def create_test_bin(): + with open(TEST_BIN, 'wb') as file: + file.write(b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' + b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' + b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' + b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' + b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' + b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' + b'A1A2A3B1B2B3111213FFA1A2A3B1B2B') + + +def decomposite32(value): + """ + Decomposites 32-bit value into byte array. + :param value: 32-bit value. + :return: Array of bytes. + """ + byte = value.to_bytes(4, 'little') + return byte diff --git a/targets/targets.json b/targets/targets.json index 30631738a95..eca61fd47ce 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8701,6 +8701,21 @@ "sectors": [[268443648, 512]], "bootloader_supported": true }, + "CY8CPROTO_064_SB": { + "inherits": ["MCU_PSOC6_M4"], + "supported_form_factors": ["ARDUINO"], + "extra_labels_add": ["PSOC6_01"], + "macros_add": ["CYB06447BZI_D54", + "PSOC6_DYNSRM_DISABLE=1", + "CY_CFG_SYSCLK_WCO_ENABLED=1", + "SEMAPHORE"], + "detect_code": ["1907"], + "forced_reset_timeout": 5, + "reset_method": "default", + "post_binary_hook": { + "function": "PSOC6Code.sign_image" + } + }, "CYW943012P6EVB_01": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], diff --git a/tools/targets/PSOC6.py b/tools/targets/PSOC6.py index 6896d773cf2..7ad96564f29 100644 --- a/tools/targets/PSOC6.py +++ b/tools/targets/PSOC6.py @@ -16,17 +16,22 @@ # import os +import sys + import platform import subprocess import errno from array import array from struct import (pack, unpack) -from shutil import copyfile -from intelhex import IntelHex +from shutil import copy2 +from intelhex import IntelHex, hex2bin, bin2hex from intelhex.compat import asbytes from ..config import ConfigException +from pathlib import Path, PurePath +import json + # The size of the program data in Cypress HEX files is limited to 0x80000000 # Higher addresses contain additional metadata (chip protection, eFuse data, etc..) CY_PROGRAM_SIZE = 0x80000000 @@ -44,6 +49,12 @@ # The address of the metadata checksum (4 bytes) CY_META_CHECKSUM_ADDR = 0x90500008 +# Secure Boot defines +MCUBOOT_HEADER_SIZE = 1024 +SPE_IMAGE_ID = 1 +NSPE_IMAGE_ID = 16 +SMIF_MEM_MAP_START = 0x18000000 + # Patch Cypress hex file: # - update checksum @@ -62,7 +73,7 @@ def patch(message_func, ihex, hexf, align=256): if start == CY_META_ADDR: # metadata section found in the original hex update_metadata = True - if start >= CY_PROGRAM_SIZE: + if start >= CY_PROGRAM_SIZE: continue segment = ihex.tobinarray(start, end) checksum += sum(segment) @@ -79,7 +90,7 @@ def patch(message_func, ihex, hexf, align=256): if update_metadata: signature = unpack('>L', ihex.tobinstr(start=CY_META_SILICON_ID_ADDR, size=4))[0] sigcheck = pack('>L', (checksum + signature) & 0x0FFFF) - ihex.frombytes(array('B',sigcheck), offset=CY_META_CHECKSUM_ADDR) + ihex.frombytes(array('B', sigcheck), offset=CY_META_CHECKSUM_ADDR) # align flash segments align_mask = align - 1 @@ -98,22 +109,25 @@ def patch(message_func, ihex, hexf, align=256): alignments.frombytes(ihex.tobinarray(end, aligned_end - 1), end) ihex.merge(alignments, 'ignore') + def merge_images(hexf0, hexf1=None): ihex = IntelHex() ihex.padding = 0x00 ihex.loadfile(hexf0, "hex") - if hexf1 is not None: + if hexf1 is not None: # Merge the CM0+ image ihex1 = IntelHex(hexf1) ihex.merge(ihex1, 'ignore') return ihex + def complete_func(message_func, elf0, hexf0, hexf1=None, dest=None): message_func("Postprocessing %s -> %s" % (elf0, hexf0)) ihex = merge_images(hexf0, hexf1) patch(message_func, ihex, hexf0) ihex.write_hex_file(dest if dest else hexf0, write_start_addr=False, byte_count=16) + # Find Cortex M0 image. def find_cm0_image(toolchain, resources, elf, hexf, hex_filename): if hex_filename is None: @@ -133,5 +147,327 @@ def find_cm0_image(toolchain, resources, elf, hexf, hex_filename): return m0hexf + +# check if policy parameters are consistent +def check_slots_integrity(toolchain, fw_cyb, target_data, fw_spe=None, fw_nspe=None): + slot0 = None + slot1 = None + + if fw_spe is None: + img_id = fw_nspe["id"] + + # check single stage scheme + if not (fw_cyb["launch"] == img_id): + # may be PSA NSPE part + if not fw_cyb["launch"] == SPE_IMAGE_ID: + toolchain.notify.debug("[PSOC6.sign_image] WARNING: ID of build image " + str(img_id) + + " does not correspond launch ID in CyBootloader - " + str(fw_cyb["launch"])) + else: + toolchain.notify.info("[PSOC6.sign_image] INFO: NSPE image ID is " + str(img_id) + + ". It will be launched by SPE part.") + + # check slots addresses and sizes if upgrade is set to True + for slot in fw_nspe["resources"]: + if slot["type"] == "BOOT": + slot0 = slot + + if fw_nspe["upgrade"] and True: + slot1 = slot + if slot["type"] == "UPGRADE": + try: + if fw_nspe["encrypt"] and True: + # mark slot1 image as one, that should be encrypted + slot1.update({'encrypt': True}) + toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE NSPE will" + " be ENCRYPTED per policy settings.") + except KeyError: + None + else: + toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE will not" + " be built per policy settings.") + break + if slot0 is None: + toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT section not found in policy resources") + raise Exception("imgtool finished execution with errors!") + + else: + # check if PSA targets flash map correspond to slots addresses and sizes in policy + if not (int(target_data["overrides"]["secure-rom-start"], 16) - MCUBOOT_HEADER_SIZE) ==\ + int(fw_spe["resources"][0]["address"]): + toolchain.notify.debug("[PSOC6.sign_image] WARNING: SPE start address " + "does not correspond BOOT slot start address defined in policy. " + "Check if MCUboot header offset 0x400 is included in SPE flash start") + + if not (int(target_data["overrides"]["non-secure-rom-start"], 16) - MCUBOOT_HEADER_SIZE) ==\ + int(fw_nspe["resources"][0]["address"]): + toolchain.notify.debug("[PSOC6.sign_image] WARNING: NSPE start address " + "does not correspond BOOT slot start address defined in policy. " + "Check if MCUboot header offset 0x400 is included in NSPE flash start") + + if (int(target_data["overrides"]["secure-rom-size"], 16) + MCUBOOT_HEADER_SIZE) >\ + int(fw_spe["resources"][0]["size"]): + toolchain.notify.debug("[PSOC6.sign_image] WARNING: SPE flash size " + "does not fit in BOOT slot size defined in policy.") + + if (int(target_data["overrides"]["non-secure-rom-size"], 16) + MCUBOOT_HEADER_SIZE) >\ + int(fw_nspe["resources"][0]["size"]): + toolchain.notify.debug("[PSOC6.sign_image] WARNING: NSPE flash size " + "does not fit in BOOT slot size defined in policy.") + + img_id = fw_spe["id"] + # check dual stage scheme + if img_id != 1: + toolchain.notify.debug("[PSOC6.sign_image] ERROR: Image ID of SPE image" + " is not equal to 1!") + raise Exception("imgtool finished execution with errors!") + + if not (fw_cyb["launch"] == img_id): + toolchain.notify.debug("[PSOC6.sign_image] ERROR: ID of build image" + " does not correspond launch ID in CyBootloader!") + raise Exception("imgtool finished execution with errors!") + + if not (fw_spe["launch"] == fw_nspe["id"]): + toolchain.notify.debug("[PSOC6.sign_image] ERROR: ID of NSPE image" + " does not correspond launch ID in SPE part!") + raise Exception("imgtool finished execution with errors!") + + + # check slots addresses and sizes if upgrade is set to True + for slot in fw_spe["resources"]: + if slot["type"] == "BOOT": + slot0 = slot + if fw_spe["upgrade"] and True: + if slot["type"] == "UPGRADE": + slot1 = slot + try: + if fw_spe["encrypt"] and True: + # mark slot1 image as one, that should be encrypted + slot1.update({'encrypt': True}) + toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE SPE will" + " be ENCRYPTED per policy settings.") + except KeyError: + None + else: + toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE will not" + " be produced per policy settings.") + if slot0 is None: + toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT section not found in policy resources") + raise Exception("imgtool finished execution with errors!") + + if slot1 is not None: + # bigger or equal to 0x18000000 in hex is a start of SMIF memory + if slot1["address"] >= SMIF_MEM_MAP_START: + toolchain.notify.info("[PSOC6.sign_image] INFO: UPGRADE slot will be resided in external flash") + + if slot0["size"] != slot1["size"]: + toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT and UPGRADE slots sizes are not equal") + + return [slot0, slot1, img_id] + else: + return [slot0, None, img_id] + + +# Resolve Secure Boot policy sections considering target +def process_target(toolchain, target): + + targets_json = Path("targets/targets.json") + cy_targets = Path("targets/TARGET_Cypress/TARGET_PSOC6/") + sb_params_file_name = Path("secure_image_parameters.json") + root_dir = Path(os.getcwd()) + + mbed_os_targets = root_dir / targets_json + + if not os.path.isfile(str(mbed_os_targets)): + # try location for tests + mbed_os_targets = root_dir / 'mbed-os' / targets_json + root_dir = root_dir / 'mbed-os' + if not os.path.isfile(str(mbed_os_targets)): + toolchain.notify.debug("[PSOC6.sign_image] ERROR: targets.json not found!") + raise Exception("imgtool finished execution with errors!") + + with open(str(mbed_os_targets)) as j: + json_str = j.read() + all_targets = json.loads(json_str) + j.close() + + processing_target = all_targets[target] + sb_params_file_path = root_dir / cy_targets / Path("TARGET_" + str(target)) / sb_params_file_name + + if os.path.isfile(str(sb_params_file_path)): + with open(str(sb_params_file_path)) as f: + json_str = f.read() + sb_config = json.loads(json_str) + f.close() + else: + toolchain.notify.debug("[PSOC6.sign_image] ERROR: secure_image_parametest.json not found!") + raise Exception("imgtool finished execution with errors!") + + sdk_path = root_dir / sb_config["sdk_path"] + + priv_key_path = sdk_path / Path(sb_config["priv_key_file"]) + + if not os.path.isfile(str(priv_key_path)): + toolchain.notify.debug("[PSOC6.sign_image] ERROR: Private key file not found in " + str(priv_key_path)) + raise Exception("imgtool finished execution with errors!") + + if "_PSA" in target: + # assume dual stage bootloading scheme + with open(sdk_path / Path(sb_config["policy_file"])) as p: + policy_str = p.read() + policy_file = json.loads(policy_str) + p.close() + + firmware_list = policy_file["boot_upgrade"]["firmware"] + + # collect firmware descriptions from policy for corresponding images + firmware_cyb_cm0p = firmware_list[0] + + if "_M0_" in target: + firmware_spe_cm0p = firmware_list[1] + firmware_nspe_cm4 = firmware_list[2] + + slots = check_slots_integrity(toolchain, fw_cyb=firmware_cyb_cm0p, fw_spe=firmware_spe_cm0p, + fw_nspe=firmware_nspe_cm4, target_data=processing_target) + else: + firmware_nspe_cm4 = firmware_list[2] + slots = check_slots_integrity(toolchain, fw_cyb=firmware_cyb_cm0p, fw_nspe=firmware_nspe_cm4, + target_data=processing_target) + else: + # consider single stage bootloading scheme + with open(sdk_path / Path(sb_config["policy_file"])) as p: + policy_str = p.read() + policy_file = json.loads(policy_str) + p.close() + + firmware_list = policy_file["boot_upgrade"]["firmware"] + firmware_cyb_cm0p = firmware_list[0] + firmware_nspe_cm4 = firmware_list[1] + slots = check_slots_integrity(toolchain, fw_cyb=firmware_cyb_cm0p, + fw_nspe=firmware_nspe_cm4, target_data=processing_target) + + target_sig_data = [{"img_data": sb_config["boot0"], "slot_data": slots[0], + "key_file": sb_config["priv_key_file"], "sdk_path": sdk_path, "id": slots[2]}] + + if slots[1] is not None: + target_sig_data.append({"img_data": sb_config["boot1"], "slot_data": slots[1], + "key_file": sb_config["priv_key_file"], "sdk_path": sdk_path, "id": slots[2]}) + # check if slot1 image sould be encrypted + try: + if slots[1]["encrypt"] is True: + + dev_pub_key = sdk_path / Path(sb_config["dev_pub_key_file"]) + if not os.path.isfile(str(dev_pub_key)): + toolchain.notify.debug("[PSOC6.sign_image] ERROR: Device public key file not found in " + str(dev_pub_key)) + raise Exception("imgtool finished execution with errors!") + + aes_key_file = sdk_path / Path(sb_config["aes_key_file"]) + if not os.path.isfile(str(aes_key_file)): + toolchain.notify.debug("[PSOC6.sign_image] ERROR: AES-128 key file not found in " + str(aes_key_file)) + raise Exception("imgtool finished execution with errors!") + + target_sig_data[1].update({"aes_key": sb_config["aes_key_file"], "dev_pub_key": sb_config["dev_pub_key_file"]}) + + except KeyError: + toolchain.notify.info("[PSOC6.sign_image] INFO: Image for slot UPGRADE would not be encrypted per policy settings") + + return target_sig_data + + +# Sign binary image using imgtool +def sign_image(toolchain, elf0, binf, hexf1=None): + + target_sig_data = None + # reserve name for separate NSPE image + out_cm4_hex = binf[:-4] + "_cm4.hex" + + # preserve original hex file from mbed-os build + mbed_hex = binf[:-4] + "_unsigned.hex" + copy2(binf, mbed_hex) + + # find target name and type before processing + for part in PurePath(binf).parts: + if "CY" in part: + target_sig_data = process_target(toolchain=toolchain, target=part) + + if target_sig_data is None: + toolchain.notify.debug("[PSOC6.sign_image] ERROR: Target not found!") + raise Exception("imgtool finished execution with errors!") + + for slot in target_sig_data: + # first check if image for slot under processing should be encrypted + try: + if slot["slot_data"]["encrypt"] is True: + # call encrypt_img to perform encryption + args = [sys.executable, str(slot["sdk_path"] / "encrypted_image_runner.py"), + "--sdk-path", str(slot["sdk_path"]), "--hex-file", os.getcwd() + '/' + mbed_hex, + "--key-priv", str(slot["sdk_path"] / slot["key_file"]), + "--key-pub", str(slot["sdk_path"] / slot["dev_pub_key"]), + "--key-aes", str(slot["sdk_path"] / slot["aes_key"]), + "--ver", str(slot["img_data"]["VERSION"]), "--img-id", str(slot["id"]), + "--rlb-count", str(slot["img_data"]["ROLLBACK_COUNTER"]), + "--slot-size", str(hex(slot["slot_data"]["size"])), + "--img-offset", str(slot["slot_data"]["address"])] + if slot["slot_data"]["type"] != "BOOT": + args.append("--pad") + process = subprocess.Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + + # catch standard process pipes outputs + stderr = process.communicate()[1] + stdout = process.communicate()[0] + rc = process.wait() + print(stdout.decode("utf-8")) + + if rc != 0: + toolchain.notify.debug("[PSOC6.sign_image] ERROR: Encryption script ended with error!") + toolchain.notify.debug("[PSOC6.sign_image] Message from encryption script: " + stderr.decode("utf-8")) + raise Exception("imgtool finished execution with errors!") + else: + toolchain.notify.info("[PSOC6.sign_image] SUCCESS: Image for slot " + + slot["slot_data"]["type"] + " is signed and encrypted with no errors!") + # all non ecrypted images take this path + except KeyError: + if slot["slot_data"]["type"] == "UPGRADE": + out_hex_name = binf[:-4] + "_upgrade.hex" + out_bin_name = out_hex_name[:-4] + "_signed.bin" + else: + out_hex_name = binf + out_bin_name = out_hex_name[:-4] + "_signed.bin" + + # call imgtool for signature + args = [sys.executable, str(slot["sdk_path"] / "imgtool/imgtool.py"), + "sign", "--key", str(slot["sdk_path"] / slot["key_file"]), + "--header-size", str(hex(MCUBOOT_HEADER_SIZE)), "--pad-header", "--align", "8", + "--version", str(slot["img_data"]["VERSION"]), "--image-id", + str(slot["id"]), "--rollback_counter", str(slot["img_data"]["ROLLBACK_COUNTER"]), + "--slot-size", str(hex(slot["slot_data"]["size"])), "--overwrite-only", + mbed_hex, out_hex_name] + if slot["slot_data"]["type"] != "BOOT": + args.append("--pad") + process = subprocess.Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + + # catch stderr outputs + stderr = process.communicate()[1] + rc = process.wait() + + if rc != 0: + toolchain.notify.debug("[PSOC6.sign_image] ERROR: Signature is not added!") + toolchain.notify.debug("[PSOC6.sign_image] Message from imgtool: " + stderr.decode("utf-8")) + raise Exception("imgtool finished execution with errors!") + else: + toolchain.notify.info("[PSOC6.sign_image] SUCCESS: Image for slot " + + slot["slot_data"]["type"] + " is signed with no errors!") + # preserve signed binary file + hex2bin(out_hex_name, out_bin_name) + + # preserve separate hex for cm4 + # 16 is image ID for NSPE image + if slot["id"] == NSPE_IMAGE_ID: + copy2(out_hex_name, out_cm4_hex) + + # produce hex file for slot1 + if slot["slot_data"]["type"] == "UPGRADE": + bin2hex(out_bin_name, out_hex_name, offset=int(slot["slot_data"]["address"])) + print("Image UPGRADE: " + out_hex_name + "\n") + def complete(toolchain, elf0, hexf0, hexf1=None): complete_func(toolchain.notify.debug, elf0, hexf0, hexf1) diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index 72fc498d580..566c85c7d84 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -675,6 +675,17 @@ def complete(t_self, resources, elf, binf): else: psoc6_complete(t_self, elf, binf) + @staticmethod + def sign_image(t_self, resources, elf, binf): + from tools.targets.PSOC6 import sign_image as psoc6_sign_image + if hasattr(t_self.target, "hex_filename"): + hex_filename = t_self.target.hex_filename + # Completing main image involves merging M0 image. + from tools.targets.PSOC6 import find_cm0_image + m0hexf = find_cm0_image(t_self, resources, elf, binf, hex_filename) + psoc6_sign_image(t_self, elf, binf, m0hexf) + else: + psoc6_sign_image(t_self, elf, binf) class ArmMuscaA1Code: """Musca-A1 Hooks""" From b15d54f5bf9b3111def625c63f7c8584507ce940 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Fri, 12 Jul 2019 13:05:41 +0300 Subject: [PATCH 02/16] Fixed IAR linker script. --- .../TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf index 3c0902869da..2eb6bbacd4d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf @@ -181,7 +181,7 @@ define block RAM_BSS {readwrite section .bss}; define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block RO {first section .intvec, readonly}; @@ -191,8 +191,8 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ -/* Flash */ -place at start of IROM1_region { block RO }; +/* Flash - Cortex-M4 application image */ +place in IROM1_region { block RO }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; /* Emulated EEPROM Flash area */ From 4db392c2f640a720fbce6d1c560153dfe54f8702 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Tue, 16 Jul 2019 17:40:44 +0300 Subject: [PATCH 03/16] Updated licenses in files, mentioned in commnets to https://github.com/ARMmbed/mbed-os/pull/11046 --- .../TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py | 15 +++++++++++++++ .../sb-tools/imgtool/create_aesHeader.py | 15 +++++++++++++++ .../TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py | 15 +++++++++++++++ .../sb-tools/imgtool/imgtool/keys/ecdsa.py | 15 +++++++++++++++ .../sb-tools/imgtool/imgtool/keys/ecdsa_test.py | 15 +++++++++++++++ .../sb-tools/imgtool/imgtool/keys/general.py | 15 +++++++++++++++ .../sb-tools/imgtool/imgtool/keys/rsa.py | 15 +++++++++++++++ .../sb-tools/imgtool/imgtool/keys/rsa_test.py | 15 +++++++++++++++ 8 files changed, 120 insertions(+) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py index 4165163263a..306c2691e59 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py @@ -1,4 +1,19 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + import click from cryptography.hazmat.primitives.ciphers import Cipher, algorithms, modes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py index b21307ed455..bc8dfec034b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py @@ -1,3 +1,18 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + import codecs import click diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py index 90d2a034299..4ffb561d16a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py @@ -1,4 +1,19 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + from cryptography.hazmat.backends import default_backend from cryptography.hazmat.primitives import hashes from cryptography.hazmat.primitives.asymmetric import ec diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py index f541d16d1a4..7ac66bbf02b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py @@ -1,3 +1,18 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + """ ECDSA key management """ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py index 8cb3220f802..877f33a1b15 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py @@ -1,3 +1,18 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + """ Tests for ECDSA keys """ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py index 3ba34cb186e..aca3fddfc61 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py @@ -1,3 +1,18 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + """General key class.""" import sys diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py index 4ddbfc646ea..eb1d0ebc4f3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py @@ -1,3 +1,18 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + """ RSA Key management """ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py index 81518780a61..e9bdb86375f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py @@ -1,3 +1,18 @@ +# Copyright 2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + """ Tests for RSA keys """ From 9d4a69720713fb0dd4c241647a2d315738df7d18 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Tue, 16 Jul 2019 18:12:28 +0300 Subject: [PATCH 04/16] Updated linker scripts and startup file for ARM - fixes tests-mbedmicro-rtos-mbed-heap_and_stack failure on ARM compiler. --- .../TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct | 26 +++------- .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 49 +++++++++++++++++-- .../TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld | 18 ++----- .../TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf | 4 +- 4 files changed, 57 insertions(+), 40 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct index 6d3b172fedd..542ebce868f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -67,11 +67,11 @@ #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 + #define MBED_RAM_START 0x08000000 #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0001E000 + #define MBED_RAM_SIZE 0x00020000 #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -133,24 +133,10 @@ #define EFUSE_START 0x90700000 #define EFUSE_SIZE 0x100000 -; Size and start address of the Cortex-M0+ application image -#define FLASH_CM0P_SIZE 0x40000 -#define FLASH_CM0P_START (FLASH_START + FLASH_SIZE - FLASH_CM0P_SIZE) - ; Size and start address of the Cortex-M4 application image -#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE) +#define FLASH_CM4_SIZE FLASH_SIZE #define FLASH_CM4_START FLASH_START - -; Cortex-M0+ application image -LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE -{ - .cy_m0p_image +0 FLASH_CM0P_SIZE - { - * (.cy_m0p_image) - } -} - ; Cortex-M4 application image LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE { @@ -184,13 +170,15 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + ARM_LIB_HEAP +0 { + * (HEAP) } ; Stack region growing down - ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE { + * (STACK) } ; Used for the digital signature of the secure application and the diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S index 023ea2184dc..5bd22714385 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -23,6 +23,36 @@ ; * limitations under the License. ; */ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00000400 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 THUMB @@ -33,9 +63,7 @@ EXPORT __Vectors_End EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$Base| -__Vectors DCD |Image$$ARM_LIB_STACK$$Base| ; Top of Stack - +__Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -635,7 +663,20 @@ pass_interrupt_dacs_IRQHandler ; User Initial Stack & Heap - IMPORT __use_two_region_memory + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + + ALIGN + + ENDIF END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld index 913663190b0..ebb6f76525c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -65,11 +65,11 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 + #define MBED_RAM_START 0x08000000 #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0001E000 + #define MBED_RAM_SIZE 0x00020000 #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -118,11 +118,8 @@ MEMORY efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ } -/* Size and start address of the Cortex-M0+ application image */ -FLASH_CM0P_SIZE = 0x40000; -FLASH_CM0P_START = ORIGIN(flash) + LENGTH(flash) - FLASH_CM0P_SIZE; /* Size and start address of the Cortex-M4 application image */ -FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE; +FLASH_CM4_SIZE = LENGTH(flash); FLASH_CM4_START = ORIGIN(flash); /* Library configurations */ @@ -164,15 +161,6 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { - /* Cortex-M0+ application image */ - .cy_m0p_image FLASH_CM0P_START : - { - . = ALIGN(4); - __cy_m0p_code_start = . ; - KEEP(*(.cy_m0p_image)) - __cy_m0p_code_end = . ; - } > flash - /* Cortex-M4 application image */ .text FLASH_CM4_START : { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf index 2eb6bbacd4d..67556454eb5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf @@ -66,11 +66,11 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08002000; + define symbol MBED_RAM_START = 0x08000000; } if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x0001E000; + define symbol MBED_RAM_SIZE = 0x00020000; } if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { From b8639a00ec4c743a52a9c41b4dae66e9fa44e008 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Tue, 16 Jul 2019 19:26:01 +0300 Subject: [PATCH 05/16] Updated CyBootloader hexes. --- .../CypressBootloader_CM0p.hex | 2429 ++++---- .../CypressBootloader_CM0p.jwt | 2 +- .../CypressBootloader_CM0p.hex | 5040 +++++++++-------- .../CypressBootloader_CM0p.jwt | 2 +- 4 files changed, 3771 insertions(+), 3702 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex index 05f2ecc028d..ed18b2a5472 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex @@ -13,9 +13,9 @@ :1000B0009D4B0D109D4B0D109D4B0D109D4B0D102C :1000C00010B5064C2378002B07D1054B002B02D02E :1000D000044800E000BF0123237010BDECA7020814 -:1000E00000000000008B0D10044B10B5002B03D056 +:1000E00000000000508C0D10044B10B5002B03D005 :1000F0000349044800E000BF10BDC04600000000F6 -:10010000F0A70208008B0D100021124B124A10B507 +:10010000F0A70208508C0D100021124B124A10B5B6 :10011000D8601C68002C06DB914202D101204042CD :1001200010BD0131F5E79142F8D00121996000211D :100130001C69002C03DA9142F0D00131F8E79142BA @@ -25,10 +25,10 @@ :100170000C000393FFF7C8FF002801D1019B236007 :1001800004B010BD13B5084BC47A986801A9C0B279 :10019000FFF7E4FF002803D1019B9C42804116BD7C -:1001A00001204042FBE7C04610AE02081FB5064BD7 +:1001A00001204042FBE7C046E8AD02081FB5064B00 :1001B0000004C018029001AB02A801910393FFF75D :1001C000A3FF05B000BDC0460001003610B5034BCB -:1001D000C17A9868C0B2FFF7E9FF10BD10AE0208FF +:1001D000C17A9868C0B2FFF7E9FF10BDE8AD020828 :1001E000F0B50F000400002685B0BE4201D100200A :1001F0003EE0A0221F4BD2009A582378032A04D055 :10020000092B02D801361034EFE71B4A0A33DB0012 @@ -38,7 +38,7 @@ :10024000002815D1237B2900AB71637BA068EB717B :10025000E3896B8102F04AFB002809D1A06802F013 :1002600025FC002804D1A06802F008FC0028C9D0B1 -:1002700005B0F0BD0000214010AE020870B50600C8 +:1002700005B0F0BD00002140E8AD020870B50600F1 :100280000024104AA3019B180F491A68A3015B18A8 :100290001B68002A04DA0134102CF2D1002070BD52 :1002A000002BF8DB094B3100E518AD01280002F006 @@ -76,9 +76,9 @@ :1004A000002815D10A210D48FFF712FF00280FD1AF :1004B00004210B48FFF741FF002809D10121094819 :1004C000FFF770FF04E02000FFF7A8FF0028DED050 -:1004D00010BDC046AC7B0D10A87A0D10B47A0D107B -:1004E000547B0D10947B0D1010B501210148FFF7CE -:1004F00077FE10BD5C7C0D100022124B124910B526 +:1004D00010BDC0462C7C0D10287B0D10347B0D10F8 +:1004E000D47B0D10147C0D1010B501210148FFF7CD +:1004F00077FE10BDDC7C0D100022124B124910B5A6 :10050000D8601C68002C05DB8A4201D1012010BD97 :100510000132F6E78A42F9D001229A6000220B49A3 :100520001C69002C03DA8A42F0D00132F8E78A42D3 @@ -125,50 +125,50 @@ :1007B00010BDC04600030035F0B58DB01D0012AB72 :1007C00040CB02921B780F000393002305AA04A9D3 :1007D0000493059300F03DF9041E3BD1204B3A00F1 -:1007E00000930599029B049806F050FC002834DD24 +:1007E00000930599029B049806F08EFC002834DDE6 :1007F000022007AA06A9FF300694079401F0AEF97B :10080000002803D12900069800F0F4FF812007AAF0 :1008100006A9400001F0A2F9652400281ED131008C :10082000069800F077FD041E14D108A9380000F0E6 :1008300028F9041E0ED131000B9800F063FB041E52 :1008400008D1039A29000B9800F03AF9040008989F -:1008500006F0B2FB20000DB0F0BD14246442F9E7AD +:1008500006F0F0FB20000DB0F0BD14246442F9E76F :10086000005F2D00F0B51F00002387B002910392B6 :1008700004A905AA0493059300F0EBF8041E2ED1F9 -:10088000059800F07FF8040006F0C0FE051E31D088 -:100890001A4B0200009305992300049806F0F6FB1A -:1008A000002822DD280006F0E1FB061E20D0010012 +:10088000059800F07FF8040006F0FEFE051E31D04A +:100890001A4B0200009305992300049806F034FCDB +:1008A000002822DD280006F01FFC061E20D00100D3 :1008B000134800F09FF8002814D00069002811D0D8 :1008C000039B220000930197029B2900FFF774FF0E -:1008D0000400300006F070FB280006F0A1FE2000A6 +:1008D0000400300006F0AEFB280006F0DFFE20002A :1008E00007B0F0BD01246442F3E714246442F3E747 :1008F0000524FBE764246442F1E7C046005F2D0055 -:100900006C7C0D1010B5010004000B4806F08CFF44 -:10091000002398420DD02100084806F085FF0123EE -:10092000002806D02100064806F07EFF43424341DE -:100930005B00180010BDC046737D0D107C7D0D104E -:10094000887D0D1010B5010004000B4806F06CFF07 -:10095000002398420DD02100084806F065FF0123CE -:10096000002806D02100064806F05EFF43424341BE -:100970005B00180010BDC0468D7D0D10967D0D10DA -:100980009E7D0D1003235843800898430430704720 +:10090000EC7C0D1010B5010004000B4806F0CAFF86 +:10091000002398420DD02100084806F0C3FF0123B0 +:10092000002806D02100064806F0BCFF43424341A0 +:100930005B00180010BDC046F37D0D10FC7D0D104E +:10094000087E0D1010B5010004000B4806F0AAFF48 +:10095000002398420DD02100084806F0A3FF012390 +:10096000002806D02100064806F09CFF4342434180 +:100970005B00180010BDC0460D7E0D10167E0D10D8 +:100980001E7E0D100323584380089843043070479F :10099000F8B5C3680D000860062B21D18468124F9A :1009A000002C01D12000F8BD266A002E06D03100AF -:1009B0000E4806F039FF002802D16C602468EFE78A -:1009C00031000B4806F030FF002801D1AC60F5E79C -:1009D0003100380006F028FF0028EFD1EC60EDE789 -:1009E00002204042DFE7C046B57D0D10A67D0D1008 -:1009F000AC7D0D10F0B507000D00002491B001AEE4 +:1009B0000E4806F077FF002802D16C602468EFE74C +:1009C00031000B4806F06EFF002801D1AC60F5E75E +:1009D0003100380006F066FF0028EFD1EC60EDE74B +:1009E00002204042DFE7C046357E0D10267E0D1006 +:1009F0002C7E0D10F0B507000D00002491B001AE63 :100A0000002D02D1280011B0F0BD296A002904D0C0 -:100A1000380006F009FF0028F4D0AB68002B06D0A0 +:100A1000380006F047FF0028F4D0AB68002B06D062 :100A20000E2C12D8A200955101341D00E8E72B6866 :100A3000002BFAD1002C0AD0013CA3009B591B6863 :100A4000002BF2D1002CF7D1EFE70025DAE72500E3 -:100A5000D8E7F8B50E002E21170006F0D7FE041EC9 -:100A60000CD0451C2E21280006F0D0FE002805D011 +:100A5000D8E7F8B50E002E21170006F015FF041E8A +:100A60000CD0451C2E21280006F00EFF002805D0D2 :100A7000001B0138386000203560F8BD1620404268 -:100A8000FBE770B5050000200C0006F07BFA28009B -:100A900006F0ECFA002803D02100FFF779FF70BDC3 +:100A8000FBE770B5050000200C0006F0B9FA28005D +:100A900006F02AFB002803D02100FFF779FF70BD84 :100AA00005204042FBE7002304220133002901D145 :100AB000904203D952001D2BF7D102331800704722 :100AC000F0B589B005900C000100C24807920027DC @@ -194,9 +194,9 @@ :100C000002997D48FFF7F6FE002804D0836801931F :100C1000019B002B03D1029B1B68029361E70199A2 :100C20007648FFF7E7FE00284AD0036974491800A8 -:100C3000039306F0F9FD002842D07249039806F0AC -:100C4000F3FD00283CD000266F4AB3009958039862 -:100C500006F0EAFD071E05D00136172EF4D1052750 +:100C3000039306F037FE002842D07249039806F06D +:100C400031FE00283CD000266F4AB3009958039823 +:100C500006F028FE071E05D00136172EF4D1052711 :100C6000183E7F4201996948FFF7C4FE002801D071 :100C70008369069301996648FFF7BCFE002804D0FB :100C8000C1698069FFF70FFF0490731C18D0049BA3 @@ -204,7 +204,7 @@ :100CA00004D1320006990A32D20011512622FF32B5 :100CB0009B5C012B04D10A36F600049BA6197360D5 :100CC000019B1B68A3E73668002E00D012E721E7DE -:100CD0004C49380006F0A8FD002800D0FFE03100A4 +:100CD0004C49380006F0E6FD002800D0FFE0310066 :100CE0004A48FFF787FE002806D02300FF331B7C0D :100CF000012B01D18369636131004548FFF77AFE1A :100D0000002800D1EBE02300FF331B7C012B00D037 @@ -220,12 +220,12 @@ :100DA0001F48FFF727FE00280BD063191A001932DD :100DB000FF321278012A04D102326A439B188269F9 :100DC0005A6202350A2D2DD03668D4E7A07007008C -:100DD000C9E7C046737D0D10DC7C0D10917C0D10B1 -:100DE000987C0D10BA7D0D10A27C0D10AA7C0D1000 -:100DF000B97C0D10C07C0D10757C0D10C27D0D10DE -:100E00007F7C0D10847C0D10C0A00208127E0D1096 -:100E10008C7C0D10CA7C0D10D77C0D10DF7C0D1062 -:100E2000E97C0D1005992F48FFF7E4FD051E20D041 +:100DD000C9E7C046F37D0D105C7D0D10117D0D102F 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-:10FFF0000000000000000000000000000000862D4E +:10FFF000000000000000000000000000000028D306 :04000005100D4EDFAD :00000001FF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt index 1484a8ef3da..ddb28220334 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt @@ -1 +1 @@ -eyJhbGciOiJFUzI1NiJ9.eyJjeV9wdWJfa2V5Ijp7ImNydiI6IlAtMjU2Iiwia2lkIjoiMyIsImt0eSI6IkVDIiwidXNlIjoic2lnIiwieCI6IlNiOGxUcHlfcGQzTnJVVGtoSXpnMmp6TTM3dU5xTml1dDhXQy1RdjNYTVEiLCJ5IjoiQ3R3Q2k0YXJYc2pFRDVUVm1yX3ZQbFAya2UxMzNLSzdsUDdTel9JWmlERSJ9LCJleHAiOjE1Nzc3NDMyMDAsImlhdCI6MTU2MjMzOTY0MywiaW1hZ2VfYWRkcmVzcyI6MjY5Mjg3NDI0LCJpbWFnZV9maWxlIjoiQ3lwcmVzc0Jvb3Rsb2FkZXJfQ00wcC5oZXgiLCJpbWFnZV9oYXNoIjpbMTkyLDIxNiwyMDMsNjUsMTQxLDc5LDgwLDE0NCwxOTYsMzUsNTAsNDUsMTI5LDEzNCwyNSwyNDksOTUsMzgsMTgzLDY1LDI0MiwxMTEsNzAsNDcsOTksNTksMTkzLDE0MSw5OSw5OCwyMjQsMTE2XSwiaW1hZ2VfaWQiOjAsImltYWdlX3ZlcnNpb24iOiIxLjAuMC45IiwicG9saWN5X3RlbXBsYXRlIjoiIn0.N3VTh3_2F7H9HlOKNBzWCzlO3THIVjxKHL9AGc0KkL0GavZ4TU6k3O7grXi4ZxZNR9eGUWWHx6lxGpeYYg3D-g \ No newline at end of file +eyJhbGciOiJFUzI1NiJ9.eyJjeV9wdWJfa2V5Ijp7ImNydiI6IlAtMjU2Iiwia2lkIjoiMyIsImt0eSI6IkVDIiwidXNlIjoic2lnIiwieCI6IlNiOGxUcHlfcGQzTnJVVGtoSXpnMmp6TTM3dU5xTml1dDhXQy1RdjNYTVEiLCJ5IjoiQ3R3Q2k0YXJYc2pFRDVUVm1yX3ZQbFAya2UxMzNLSzdsUDdTel9JWmlERSJ9LCJleHAiOjE1Nzc3NDMyMDAsImlhdCI6MTU2MzI4NjA3NiwiaW1hZ2VfYWRkcmVzcyI6MjY5Mjg3NDI0LCJpbWFnZV9maWxlIjoiQ3lwcmVzc0Jvb3Rsb2FkZXJfQ00wcC5oZXgiLCJpbWFnZV9oYXNoIjpbMTY3LDExNSwxMTUsNjIsNiwyMjEsMTIsMjM0LDE0MiwzNyw0NiwyNTQsMjM5LDI0OCw2MCwxNTcsOTksNCwxOTcsMTc1LDIxNiw4MCwxMDIsNDYsMTY5LDE5NiwxNzgsNTMsOTQsNDksMjMxLDIwMl0sImltYWdlX2lkIjowLCJpbWFnZV92ZXJzaW9uIjoiMS4wLjAuMTI1IiwicG9saWN5X3RlbXBsYXRlIjoiIn0.kC_8cSqHKBHl1770umc1em1ZhuwjSHKxY1TigIBjcPVd_Gnr2X4LcMGIB6biwVWWYmtONF7k87XXfpM4NqByAg \ No newline at end of file From 7e8d5692616543df7e2cb17ac1bb0d8853b6cb13 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Tue, 16 Jul 2019 19:27:32 +0300 Subject: [PATCH 06/16] Added example x.509 certificate for provisioning. --- targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md | 10 +++++++--- .../TARGET_PSOC6/sb-tools/prepare/example_cert.pem | 10 ++++++++++ 2 files changed, 17 insertions(+), 3 deletions(-) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/example_cert.pem diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md index c28419aba83..89e19bdc2ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md @@ -2,6 +2,8 @@ This directory contains tools and scripts for generating keys, preparing provisi These files are relevant to CY8CPROTO_064_SB or CY8CPROTO_064_SB_M0_PSA, CY8CPROTO_064_SB_PSA targets. Version of Python required is 3.7+ +**_NOTE_:** Detailed description about Secure Boot tools availabe on this link https://www.cypress.com/secureboot-sdk-user-guide + # DEVICE PROVISIONING ## 1. Generate new keys by executing the following commands from ./keys: @@ -15,7 +17,7 @@ Version of Python required is 3.7+ python keygen.py --aes aes.key -**_NOTE_:** DO NOT COMMIT any new keys to repository. --- +**_NOTE_:** DO NOT COMMIT any new keys to repository. ## 2. Create provisioning packets: Use *provisioning_packet.py* from ./prepare folder. @@ -33,11 +35,13 @@ Options: * To create packet for CY8CPROTO_064_SB target using single-stage policy (CM4 only): - python provisioning_packet.py --policy policy_single_stage_CM4.json --out ../packet --cyboot ../prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt --ckey ../keys/USERAPP_CM4_KEY.json + python provisioning_packet.py --policy policy_single_stage_CM4.json --out ../packet --cyboot ../prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt --ckey ../keys/USERAPP_CM4_KEY.json --devcert example_cert.pem * To use external memory (via SMIF) as staging(upgrade) area (slot_1) of NSPE (CM4) image use policy file with corresponding name: - python provisioning_packet.py --policy policy_single_stage_CM4_smif.json --out ../packet --cyboot ../prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt --ckey ../keys/USERAPP_CM4_KEY.json + python provisioning_packet.py --policy policy_single_stage_CM4_smif.json --out ../packet --cyboot ../prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt --ckey ../keys/USERAPP_CM4_KEY.json --devcert example_cert.pem + + The certificate in above examples is signed with OEM key from ./prebuild folder. Prebuild folder contains CyBootloader_WithLogs and CyBootloader_Release with corresponding *.hex and *.jwt files. * WithLogs prints execution results to terminal. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/example_cert.pem b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/example_cert.pem new file mode 100644 index 00000000000..ebc4b43f9d8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/example_cert.pem @@ -0,0 +1,10 @@ +-----BEGIN CERTIFICATE----- +MIIBTzCB9qADAgECAhQCJF8kCV5oVGofjI+lrnVsCSI+cjAKBggqhkjOPQQDAjAg +MR4wHAYDVQQDDBVDeXByZXNzIFNlbWljb25kdWN0b3IwHhcNMTkwNzE1MTkzNzQ3 +WhcNMjAwNzE0MTkzNzQ3WjAeMRwwGgYDVQQDDBNFeGFtcGxlIGNlcnRpZmljYXRl +MFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDQgAEvfb7/jewTxpFVINcXdrZQJBArC5i +grN0BLc783FigrP2sEFQpfOmPUDkrt/E+0Rol2x+jsmP/CwXstNktz6w86MQMA4w +DAYDVR0TAQH/BAIwADAKBggqhkjOPQQDAgNIADBFAiEA3I3zaBbwMzSJ6xU9ngUM +Dyk4XstQF3tLzmvBRUkX8woCICk0YiVqk4tD2wvgUYkPztBKu6tVl/OqF2Ee+aQs +uwQc +-----END CERTIFICATE----- From 74c5ea6517362abaad29c82d05aaf4ad9efa2eb6 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Wed, 17 Jul 2019 15:58:02 +0300 Subject: [PATCH 07/16] Updated BSD license file content. --- .../Other/bsd_base64_license.txt | 109 ++++++++---------- 1 file changed, 46 insertions(+), 63 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt index d95796bd1b5..8ab19243a91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt @@ -1,63 +1,46 @@ -Oracle Binary Code License Agreement for the Java SE Platform Products and JavaFX - -ORACLE AMERICA, INC. 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You can find more information about the data Oracle collects as a result of your Software download at http://www.oracle.com/technetwork/java/javase/documentation/index.html. - -For inquiries please contact: Oracle America, Inc., 500 Oracle Parkway, - -Redwood Shores, California 94065, USA. - -Last updated 21 September 2017 \ No newline at end of file +/* + * $ Copyright Cypress Semiconductor $ + */ +/* $OpenBSD: base64.c,v 1.3 1997/11/08 20:46:55 deraadt Exp $ */ + +/* + * Copyright (c) 1996 by Internet Software Consortium. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND INTERNET SOFTWARE CONSORTIUM DISCLAIMS + * ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL INTERNET SOFTWARE + * CONSORTIUM BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS + * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + */ + +/* + * Portions Copyright (c) 1995 by International Business Machines, Inc. + * + * International Business Machines, Inc. (hereinafter called IBM) grants + * permission under its copyrights to use, copy, modify, and distribute this + * Software with or without fee, provided that the above copyright notice and + * all paragraphs of this notice appear in all copies, and that the name of IBM + * not be used in connection with the marketing of any product incorporating + * the Software or modifications thereof, without specific, written prior + * permission. + * + * To the extent it has a right to do so, IBM grants an immunity from suit + * under its patents, if any, for the use, sale or manufacture of products to + * the extent that such products are used for performing Domain Name System + * dynamic updates in TCP/IP networks by means of the Software. No immunity is + * granted for any product per se or for any other function of any product. + * + * THE SOFTWARE IS PROVIDED "AS IS", AND IBM DISCLAIMS ALL WARRANTIES, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE. IN NO EVENT SHALL IBM BE LIABLE FOR ANY SPECIAL, + * DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE, EVEN + * IF IBM IS APPRISED OF THE POSSIBILITY OF SUCH DAMAGES. + */ \ No newline at end of file From f22e488083027a536248ef32ad092223c389b228 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Fri, 26 Jul 2019 00:21:49 +0300 Subject: [PATCH 08/16] Added sb-tools requirements to main mbed-os requirements file. --- requirements.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/requirements.txt b/requirements.txt index e8a6f9a4620..747d9e26006 100644 --- a/requirements.txt +++ b/requirements.txt @@ -26,3 +26,8 @@ cmsis-pack-manager>=0.2.3,<0.3.0 pywin32==224;platform_system=='Windows' wmi==1.4.9;platform_system=='Windows' psutil==5.6.2 +cryptography>=2.4.2 +Click>=7.0 +intelhex>=2.2.1 +jwcrypto>=0.6.0 +pathlib>=19.1.1 From 5262cf1f87236920a7fc4fd795e740d843dbcba0 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Tue, 30 Jul 2019 15:30:20 +0300 Subject: [PATCH 09/16] Updated python module requirements.txt --- requirements.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/requirements.txt b/requirements.txt index 747d9e26006..187317660ba 100644 --- a/requirements.txt +++ b/requirements.txt @@ -28,6 +28,5 @@ wmi==1.4.9;platform_system=='Windows' psutil==5.6.2 cryptography>=2.4.2 Click>=7.0 -intelhex>=2.2.1 jwcrypto>=0.6.0 -pathlib>=19.1.1 +pathlib>=1.0.1 From 74e873a0454f5a63c49dbbce6c581316581e09c4 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Wed, 7 Aug 2019 17:21:59 +0300 Subject: [PATCH 10/16] Updated README.md --- targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md index 89e19bdc2ef..d9866dba135 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md @@ -1,6 +1,7 @@ +#### Version of Python required is 3.7+ + This directory contains tools and scripts for generating keys, preparing provisioning packets and execution of provisioning. These files are relevant to CY8CPROTO_064_SB or CY8CPROTO_064_SB_M0_PSA, CY8CPROTO_064_SB_PSA targets. -Version of Python required is 3.7+ **_NOTE_:** Detailed description about Secure Boot tools availabe on this link https://www.cypress.com/secureboot-sdk-user-guide @@ -80,7 +81,7 @@ Secure Boot enabled targets support image upgrades, if specified by policy. Ther The upgrade images types are determined by the following policy setting (firmware sections): -- **_"smif_id":_** 0, - should be set to 2 if AUGUST_CYW43012 target is used, 1 - if CY8CPROTO_064_SB, 0 - SMIF disabled +- **_"smif_id":_** should be set to 1 for CY8CPROTO_064_SB onboard SMIF, default is 0 - SMIF disabled - **_"upgrade":_** true/false, - should be set to *true* if UPGRADE supported, *false* - if disabled - **_"encrypt":_** true/false, - should be set to *true* if encrypted UPGRADE supported, *false* - if disabled - **_"encrypt_key_id":_** 1, - should remain unchanged, means that Device Key will be used in ECDH/HKDF protocol From 44401b5917e291bfc06e8322be613ab815b6c517 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Wed, 14 Aug 2019 01:13:14 +0300 Subject: [PATCH 11/16] Added licenses types for python packets to LICENSE.md, updated versions definition in requirements.txt --- LICENSE.md | 3 +++ requirements.txt | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/LICENSE.md b/LICENSE.md index 4891943d11a..e3a1bc6227d 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -54,3 +54,6 @@ The Python modules used by Mbed tools are used under the following licenses: - [pywin32](https://pypi.org/project/pywin32/) - PSF - [wmi](https://pypi.org/project/WMI/) - MIT - [psutil](https://pypi.org/project/psutil/) - BSD +- [click](https://pypi.org/project/click/) - BSD-3-Clause +- [cryptography](https://pypi.org/project/cryptography/) - BSD, Apache-2.0 +- [jwcrypto](https://pypi.org/project/jwcrypto/) - LGPLv3+ diff --git a/requirements.txt b/requirements.txt index 187317660ba..02433ec4409 100644 --- a/requirements.txt +++ b/requirements.txt @@ -26,7 +26,7 @@ cmsis-pack-manager>=0.2.3,<0.3.0 pywin32==224;platform_system=='Windows' wmi==1.4.9;platform_system=='Windows' psutil==5.6.2 -cryptography>=2.4.2 -Click>=7.0 -jwcrypto>=0.6.0 +cryptography>=2.4.x,<2.5 +Click>=7.0,<7.1 +jwcrypto>=0.6,<0.7 pathlib>=1.0.1 From 515555e7bacc396f8f98e4a96fd9fd4e7ef47827 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Sat, 24 Aug 2019 01:27:54 +0300 Subject: [PATCH 12/16] Removed scripts for provisiongs from repository, made fixes per PR comments, adjusted Readme.md --- LICENSE.md | 1 - requirements.txt | 1 - .../secure_image_parameters.json | 2 +- .../TARGET_PSOC6/sb-tools/.gitignore | 2 +- .../TARGET_PSOC6/sb-tools/README.md | 88 +- .../sb-tools/entrance_exam_runner.py | 45 - .../sb-tools/execute/entrance_exam.py | 68 - .../TARGET_PSOC6/sb-tools/execute/enums.py | 30 - .../sb-tools/execute/gen_data_from_json.py | 38 - .../TARGET_PSOC6/sb-tools/execute/helper.py | 59 - .../sb-tools/execute/p6_memory_map.py | 17 - .../TARGET_PSOC6/sb-tools/execute/p6_reg.py | 95 - .../sb-tools/execute/programmer/__init__.py | 18 - .../sb-tools/execute/programmer/base.py | 179 - .../sb-tools/execute/programmer/exceptions.py | 23 - .../sb-tools/execute/programmer/programmer.py | 29 - .../execute/programmer/pyocd_wrapper.py | 272 -- .../sb-tools/execute/provision_device.py | 105 - .../TARGET_PSOC6/sb-tools/execute/sys_call.py | 198 - .../TARGET_PSOC6/sb-tools/keys/keygen.py | 73 - .../{prepare => policy}/example_cert.pem | 0 .../policy_single_stage_CM4.json | 0 .../policy_single_stage_CM4_smif.json | 2 +- .../CypressBootloader_CM0p.hex | 2396 ----------- .../CypressBootloader_CM0p.jwt | 1 - .../CypressBootloader_CM0p.hex | 3762 ----------------- .../CypressBootloader_CM0p.jwt | 1 - .../TARGET_PSOC6/sb-tools/prebuild/LICENSE | 51 - .../sb-tools/prebuild/cy_auth.jwt | 1 - .../sb-tools/prebuild/hsm_state.json | 18 - .../sb-tools/prebuild/oem_state.json | 18 - .../Apache/LICENSE-2.0.txt | 202 - .../third_party_licenses/Apache/README.txt | 5 - .../MIT/cjason-license.txt | 23 - .../Other/bsd_base64_license.txt | 46 - .../prepare/provisioning_lib/cyprov_crypto.py | 116 - .../provisioning_lib/cyprov_customer.py | 50 - .../prepare/provisioning_lib/cyprov_entity.py | 46 - .../prepare/provisioning_lib/cyprov_hsm.py | 443 -- .../prepare/provisioning_lib/cyprov_oem.py | 143 - .../prepare/provisioning_lib/cyprov_pem.py | 79 - .../prepare/provisioning_lib/cyprov_types.py | 29 - .../sb-tools/prepare/provisioning_packet.py | 133 - .../sb-tools/provision_device_runner.py | 80 - .../TARGET_PSOC6/sb-tools/requirements.txt | 7 - .../sb-tools/test/test_data/blinky_large.hex | 1410 ------ .../sb-tools/test/test_data/blinky_small.hex | 30 - .../sb-tools/test/test_pyocd_wrapper.py | 301 -- .../sb-tools/test/test_utility.py | 39 - tools/targets/PSOC6.py | 194 +- tools/targets/__init__.py | 12 +- 51 files changed, 121 insertions(+), 10860 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/entrance_exam_runner.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/entrance_exam.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/enums.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/gen_data_from_json.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/helper.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_memory_map.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_reg.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/__init__.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/base.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/exceptions.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/programmer.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/pyocd_wrapper.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/provision_device.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/sys_call.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/keygen.py rename targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/{prepare => policy}/example_cert.pem (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/{prepare => policy}/policy_single_stage_CM4.json (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/{prepare => policy}/policy_single_stage_CM4_smif.json (98%) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.hex delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/LICENSE delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/cy_auth.jwt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/hsm_state.json delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/oem_state.json delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/LICENSE-2.0.txt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/README.txt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/MIT/cjason-license.txt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_crypto.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_customer.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_entity.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_hsm.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_oem.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_pem.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_types.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_packet.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/provision_device_runner.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/requirements.txt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_large.hex delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_small.hex delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_pyocd_wrapper.py delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_utility.py diff --git a/LICENSE.md b/LICENSE.md index e3a1bc6227d..831caa12b00 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -56,4 +56,3 @@ The Python modules used by Mbed tools are used under the following licenses: - [psutil](https://pypi.org/project/psutil/) - BSD - [click](https://pypi.org/project/click/) - BSD-3-Clause - [cryptography](https://pypi.org/project/cryptography/) - BSD, Apache-2.0 -- [jwcrypto](https://pypi.org/project/jwcrypto/) - LGPLv3+ diff --git a/requirements.txt b/requirements.txt index 02433ec4409..40b86802c0f 100644 --- a/requirements.txt +++ b/requirements.txt @@ -28,5 +28,4 @@ wmi==1.4.9;platform_system=='Windows' psutil==5.6.2 cryptography>=2.4.x,<2.5 Click>=7.0,<7.1 -jwcrypto>=0.6,<0.7 pathlib>=1.0.1 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json index 7e2c874a4b6..b66402fccc5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json @@ -13,5 +13,5 @@ "priv_key_file": "keys/USERAPP_CM4_KEY_PRIV.pem", "aes_key_file": "keys/image-aes-128.key", "dev_pub_key_file": "keys/dev_pub_key.pem", - "policy_file": "prepare/policy_single_stage_CM4.json" + "policy_file": "policy/policy_single_stage_CM4.json" } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore index 601bb601e2c..23a0757e7cf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore @@ -1 +1 @@ -packet \ No newline at end of file +packet diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md index d9866dba135..8819df6beaa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md @@ -1,77 +1,9 @@ #### Version of Python required is 3.7+ -This directory contains tools and scripts for generating keys, preparing provisioning packets and execution of provisioning. -These files are relevant to CY8CPROTO_064_SB or CY8CPROTO_064_SB_M0_PSA, CY8CPROTO_064_SB_PSA targets. +This directory contains scripts for adding signatures . +These files are relevant to CY8CPROTO_064_SB target. -**_NOTE_:** Detailed description about Secure Boot tools availabe on this link https://www.cypress.com/secureboot-sdk-user-guide - -# DEVICE PROVISIONING - -## 1. Generate new keys by executing the following commands from ./keys: - - *Create keys for image signing:* - - python keygen.py -k 8 --jwk USERAPP_CM4_KEY.json --pem-priv USERAPP_CM4_KEY_PRIV.pem - - *Create key for image encryption:* - - python keygen.py --aes aes.key - - -**_NOTE_:** DO NOT COMMIT any new keys to repository. - -## 2. Create provisioning packets: -Use *provisioning_packet.py* from ./prepare folder. - -Options: - - --oem OEM key file. - --hsm HSM key file. - --cyboot Cypress Bootloader image certificate. - --cyauth Provisioning authorization certificate. - --policy Policy file. - --out Output directory. - --ckey Customer key that will be used for image signing. Use the option multiple times to specify multiple keys. - --devcert Chain of trust certificate. Use the option multiple times to specify multiple certificates. - -* To create packet for CY8CPROTO_064_SB target using single-stage policy (CM4 only): - - python provisioning_packet.py --policy policy_single_stage_CM4.json --out ../packet --cyboot ../prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt --ckey ../keys/USERAPP_CM4_KEY.json --devcert example_cert.pem - -* To use external memory (via SMIF) as staging(upgrade) area (slot_1) of NSPE (CM4) image use policy file with corresponding name: - - python provisioning_packet.py --policy policy_single_stage_CM4_smif.json --out ../packet --cyboot ../prebuild/CyBootloader_Release/CypressBootloader_CM0p.jwt --ckey ../keys/USERAPP_CM4_KEY.json --devcert example_cert.pem - - The certificate in above examples is signed with OEM key from ./prebuild folder. - -Prebuild folder contains CyBootloader_WithLogs and CyBootloader_Release with corresponding *.hex and *.jwt files. - * WithLogs prints execution results to terminal. - * Release does not print to terminal and boots up silently. - -**_NOTE:_** CypressBootloader_CM0p.jwt and CypressBootloader_CM0p.hex must be used in pair from the same directory in provisioning packet generation (.packets/prov_cmd.jwt) and provisioning procedure itself. - -## 3. Run entrance exam - - python entrance_exam_runner.py - -## 4. Perform provisioning: -**_ATTENTION:_** Proceed to **UPGRADE IMAGES** section first if UPGRADE image is needed. - -Execute *provision_device_runner.py*. -The script will run with the default arguments if no arguments specified. - -Default arguments can be overridden with a custom: - - --prov-jwt Path to provisioning JWT file (packet which contains all data necessary for provisioning, including policy, authorization packets and keys) - --hex Path to Cypress Bootloader HEX binary file - --pubkey-json File where to save public key in JSON format - --pubkey-pem File where to save public key in PEM format - -*Example:* - - python provision_device_runner.py --prov-jwt packet/prov_cmd.jwt --hex prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex --pubkey-json keys/dev_pub_key.json --pubkey-pem keys/dev_pub_key.pem - -**_NOTE:_** PSoC6 supply voltage of 2.5V is required to perform provisioning. +**_NOTE_:** Before starting work with Cypress Secure Boot enabled target please read User Guide https://www.cypress.com/secureboot-sdk-user-guide ## UPGRADE IMAGES @@ -87,9 +19,9 @@ The upgrade images types are determined by the following policy setting (firmwar - **_"encrypt_key_id":_** 1, - should remain unchanged, means that Device Key will be used in ECDH/HKDF protocol Requirements: -- Policy with **_smif.json** from prepare/ folder should be used. +- Policy with **_smif.json** from policy/ folder should be used. For encrypted image: -- aes.key generated, as described in **DEVICE_PROVISIONING - 1** +- aes.key generated, as described in user guide - dev_pub_key.pem must be placed in keys/ folder (this key is generated in provisioning procedure) - secure_image_parameters.json file in the target directory must contain valid keys' paths @@ -110,7 +42,7 @@ Encrypted UPGRADE image: "encrypt": true, "encrypt_key_id": 1, -Modified policy file should be used for provisioning the device, as described in paragraph 4. +Modified policy file should be used for provisioning the device, as described in User Guide. Now mbed-os application or test can be built as described in section **TESTS**. Images for UPGRADE are generated at build time, according to policy. @@ -140,11 +72,3 @@ The generic HEX file (for example one that is produced by mbed-os build system) Run commands: mbed test --compile -m CY8CPROTO_064_SB -t GCC_ARM -n tests-mbed* -v - -# TROUBLESHOOTING: - -1. In case of messages like "unable to find device" execute "mbedls -m 1907:CY8CPROTO_064_SB", then check with "mbedls" if device is detected as CY8CPROTO_064_SB with code 1907. -2. Keys, from ./keys folder is used for signing images by default, these keys should be used for provisioning. -3. Consider using CyBootloader from CyBootloader_WithLogs folder. It produces logs, which are useful to understand whether CyBootloader works correctly. -4. When running application with SMIF and _smif.json policy the field "smif_id" should be set to 1 for CY8CPROTO_064_SB. -5. Low frequency quartz (32768 Hz) oscillator have to be soldered on CY8CPROTO_064_SB (not present in stock version of board). diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/entrance_exam_runner.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/entrance_exam_runner.py deleted file mode 100644 index ead6127934b..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/entrance_exam_runner.py +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import sys -from execute.enums import DebugCore -from execute.helper import get_target_name -from execute.programmer.programmer import ProgrammingTool -from execute.entrance_exam import entrance_exam - -TOOL_NAME = 'pyocd' # Programming/debugging tool used for communication with device -ACCESS_PORT = DebugCore.debug_sys_ap # Access port used for entrance exam - - -def main(): - """ - Provides high level support for entrance exam procedure. - """ - target = get_target_name(TOOL_NAME, ACCESS_PORT) - if not target: - print('Invalid access port.') - sys.exit(1) - - status = False - tool = ProgrammingTool.create(TOOL_NAME) - if tool.connect(target): - status = entrance_exam(tool) - - if not status: - sys.exit(1) - - -if __name__ == "__main__": - main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/entrance_exam.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/entrance_exam.py deleted file mode 100644 index 8757f02db33..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/entrance_exam.py +++ /dev/null @@ -1,68 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import os -from time import sleep -from execute.helper import check_mode -from execute.enums import ProtectionState -from execute.gen_data_from_json import ENTRANCE_EXAM_FW_STATUS_REG, ENTRANCE_EXAM_FW_STATUS_MASK, \ - ENTRANCE_EXAM_FW_STATUS_VAL, ENTRANCE_EXAM_REGION_HASH_ADDR, ENTRANCE_EXAM_REGION_HASH_SIZE, \ - ENTRANCE_EXAM_REGION_HASH_MODE, ENTRANCE_EXAM_REGION_HASH_EXPECTED_VAL -from execute.sys_call import region_hash - - -def entrance_exam(tool): - """ - Checks device life-cycle, Flashboot firmware and Flash state. - :param tool: Programming/debugging tool used for communication with device. - :return: True if entrance exam passed, otherwise False. - """ - # Check the device life-cycle stage - print('Check device protection state:') - if not check_mode(tool, ProtectionState.secure): - return False - - # Check if any firmware is launched by FlashBoot and running on the device - print(os.linesep + 'Read Flashboot firmware status:') - fb_firmware_status = tool.read32(ENTRANCE_EXAM_FW_STATUS_REG) - print(f'FB Firmware status = {hex(fb_firmware_status)}') - print(f'Received FB_FW_STATUS = {hex(fb_firmware_status & ENTRANCE_EXAM_FW_STATUS_MASK)}') - print(f'Expected FB_FW_STATUS = {hex(ENTRANCE_EXAM_FW_STATUS_VAL)}') - is_exam_pass = (fb_firmware_status & ENTRANCE_EXAM_FW_STATUS_MASK) == ENTRANCE_EXAM_FW_STATUS_VAL - if is_exam_pass: - print('PASS: FB Firmware status is as expected') - else: - print('FAIL: FB Firmware status is not as expected') - if fb_firmware_status == 0xA1000100: - print('Test firmware exists and running on CM4 core. Device is in SECURE UNCLAIMED mode') - elif fb_firmware_status == 0xA1000101: - print('Secure firmware exists and running on CM0p core. Device is in SECURE CLAIMED mode') - return False - - # Check flash for malicious firmware - print(os.linesep + 'Check if Main Flash of the device is empty:') - if region_hash(tool, ENTRANCE_EXAM_REGION_HASH_ADDR, ENTRANCE_EXAM_REGION_HASH_SIZE, - ENTRANCE_EXAM_REGION_HASH_MODE, ENTRANCE_EXAM_REGION_HASH_EXPECTED_VAL): - print('PASS: Flash value is as expected') - print() - print('*****************************************') - print(' ENTRANCE EXAM TEST PASSED ') - print('*****************************************') - tool.reset() - sleep(0.2) - else: - print('FAIL: Flash value is not as expected') - return False - return True diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/enums.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/enums.py deleted file mode 100644 index 7624fc3f129..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/enums.py +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from enum import IntEnum, Enum - - -class DebugCore(Enum): - """ - Provides set of access ports for programming/debugging. - """ - debug_cm0_ap, debug_cm4_ap, debug_sys_ap = range(3) - - -class ProtectionState(IntEnum): - """ - Provides set of device life-cycle stages. - """ - unknown, virgin, normal, secure, dead = range(5) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/gen_data_from_json.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/gen_data_from_json.py deleted file mode 100644 index b2b815e8798..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/gen_data_from_json.py +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -################################################################################# -# ENTRANCE EXAM REGISTER AND VARIABLE CONSTANTS -################################################################################# -ENTRANCE_EXAM_EFUSE_ASSET_HASH_BASE_REG = 0x402C0840 -ENTRANCE_EXAM_ASSET_HASH_LEN = 16 -ENTRANCE_EXAM_ASSET_HASH_ZEROS = 72 -ENTRANCE_EXAM_ASSET_HASH_EXPECTED_STR = "0xD9 0x1B 0x11 0xAA 0x5D 0x75 0x68 0x6A " \ - "0x12 0x10 0xE0 0x88 0x38 0xE1 0x2B 0x79" - -ENTRANCE_EXAM_LIFECYCLE_STAGE_REG = 0x402C082b -ENTRANCE_EXAM_LIFECYCLE_STAGE_EXPECTED_VAL = 0x01 - -ENTRANCE_EXAM_FW_STATUS_REG = 0x08044800 -ENTRANCE_EXAM_FW_STATUS_VAL = 0xF0000000 -ENTRANCE_EXAM_FW_STATUS_MASK = 0xF0800000 - -ENTRANCE_EXAM_SRAM_ADDR = 0x0802c000 -ENTRANCE_EXAM_SRAM_SIZE = 0x00004000 - -ENTRANCE_EXAM_REGION_HASH_ADDR = 0x10000000 -ENTRANCE_EXAM_REGION_HASH_SIZE = 0x000e0000 -ENTRANCE_EXAM_REGION_HASH_MODE = 255 -ENTRANCE_EXAM_REGION_HASH_EXPECTED_VAL = 0x00 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/helper.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/helper.py deleted file mode 100644 index 6264202c9e3..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/helper.py +++ /dev/null @@ -1,59 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from execute.enums import DebugCore, ProtectionState -from execute.p6_reg import CYREG_CPUSS_PROTECTION, CYREG_IPC2_STRUCT_DATA, CYREG_EFUSE_SECURE_HASH - - -def check_mode(tool, expected_mode: ProtectionState): - """ - Checks device protection state and compares with the expected. - :return: The device protection state. - """ - mode_name = expected_mode.name.upper() - if tool.read32(CYREG_CPUSS_PROTECTION) != int(expected_mode): - print(f'FAIL: Device is not in {mode_name} mode, error code: {hex(tool.read32(CYREG_IPC2_STRUCT_DATA))}') - print('Read Secure Hash from eFUSEs:') # 00 expected on virgin device - got_factory_hash = '' - i = 0 - while i < 24: - hash_byte_val = hex(tool.read8(CYREG_EFUSE_SECURE_HASH + i)) - got_factory_hash += hash_byte_val + ' ' - i += 1 - print(f"Received SECURE_HASH: '{got_factory_hash}'") - return False - print(f'PASS: Device is in {mode_name} mode') - return True - - -def get_target_name(tool_name, access_port): - """ - Gets name of the target based on programming tool and access port. - :param tool_name: The name of programming/debugging tool. - :param access_port: The access port used for communication. - :return: The target name. - """ - if tool_name == 'pyocd': - if access_port == DebugCore.debug_cm0_ap: - target = 'cy8c64xx_cm0' - elif access_port == DebugCore.debug_cm4_ap: - target = 'cy8c64xx_cm4' - elif access_port == DebugCore.debug_sys_ap: - target = 'cy8c64xx_cm4_full' - else: - raise ValueError(f"Unhandled access port value: '{access_port}'") - else: - raise ValueError(f"Unhandled programming tool: '{tool_name}'") - return target diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_memory_map.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_memory_map.py deleted file mode 100644 index 98700bf20cb..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_memory_map.py +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -FLASH_ADDRESS = 0x10000000 -FLASH_SIZE = 0x000e0000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_reg.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_reg.py deleted file mode 100644 index 2e8e630aed9..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/p6_reg.py +++ /dev/null @@ -1,95 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -################################################################################# -# PSOC6 BLE REGISTER ADDRESSES -################################################################################# -CYREG_IPC2_STRUCT_ACQUIRE = 0x40230040 # 0x40220040 2M -CYREG_IPC2_STRUCT_NOTIFY = 0x40230048 -CYREG_IPC2_STRUCT_DATA = 0x4023004C -CYREG_IPC2_STRUCT_DATA1 = 0x40230050 # for 2M only -CYREG_IPC2_STRUCT_LOCK_STATUS = 0x40230050 # 0x4023005C -CYREG_CPUSS_PROTECTION = 0x40210500 # 0x4023005C 2M - -CYREG_EFUSE_FACTORY_HASH = 0x402c082c -CYREG_EFUSE_LIFECYCLE_STAGE = 0x402c082b -CYREG_EFUSE_SECURE_HASH = 0x402c0814 -CYREG_EFUSE_LAST_BYTE = 0x402c0879 - -NVSTORE_AREA_1_ADDRESS = 0x100FB600 -NVSTORE_OEM_ADDRESS = 0x100FFA00 -NVSTORE_DEV_KEY_ADDRESS = 0x100FFC00 -NVSTORE_UDS_ADDRESS = 0x100FFE00 - -################################################################################# -# PSOC6 BLE SFLASH ADDRESSES -################################################################################# -SFLASH_TOC1_ADDR = 0x16007800 -SFLASH_TOC1_LEN = 0x1C -SFLASH_TOC2_ADDR = 0x16007c00 -SFLASH_TOC2_LEN = 0x30 -TOC1_ROW_IDX = 60 -TOC1_DUPL_ROW_IDX = 61 -TOC2_ROW_IDX = 62 -TOC2_DUPL_ROW_IDX = 63 -TOC1_BYTE_SIZE = 0x1C # Stored as 1st word of TOC1 -MAGIC_NUMBER1 = 0x01211219 # Stored as 2nd word of TOC1 -NUM_OBJECTS_TOC1 = 0x4 # Stored as 3rd word of TOC1 -SFLASH_TRIM_START_ADDR = 0x16000200 # Stored as 4th word of TOC1 -SFLASH_HV_PARAM_TABLE_ADDR = 0x16000400 -SRAM_HV_PARAM_TABLE_ADDR = 0x08001000 # Only for *C PSoC6ABLE2 silicon -SFLASH_UNIQUEID_START_ADDR = 0x16000600 # Stored as 5th word of TOC1 -FLASHBOOT_START_ADDR = 0x16002000 # Stored as 6th word of TOC1 -SFLASH_SYSCALL_TABLE_PTR_ADDR = 0x16000004 # Stored as 7th word of TOC1 -SFLASH_SYSCALL_TABLE_PTR = 0x16004100 -SFLASH_SKIP_HASH = 0x16000008 -SFLASH_FLL_CONTROL = 0x16000008 -SFLASH_NORMAL_ACCESS_CTL = 0x16000008 -MAGIC_NUMBER2 = 0x01211220 -SFLASH_FLL_EN_IDX = 0x2 - -################################################################################# -# CONSTANTS AND DEFINITIONS -################################################################################# -# any random SRAM address. Fixing it to 0x2000 for all sram_scratch purposes. -# SRAM_SCRATCH = 0x08046000 -# SRAM_SCRATCH_SIZE = 0x00000800 -FLASH_START_ADDR = 0x10000000 -FLASH_SHA256_STR_ADDR = 0x10000100 -FLASH_SHA256_STR_LEN = 12 -FLASH_SHA256_DIG_ADDR = 0x10000110 -FLASH_SIZE = 0x200000 # 2 MB for PSoC 6A-2M -SFLASH_START_ADDR = 0x16000000 -SFLASH_SIZE = 0x8000 - -GENERAL_TRIM_TABLE_HASH_ADDR = 0x16000200 -TRIM_START_ADDR = 0x16000203 -TRIM_TABLE_LEN_ADDR = 0x16000200 -WFLASH_START_ADDR = 0x14000000 -WFLASH_SIZE = 0x8000 -SRAM_START_ADDR = 0x08000000 -SRAM_SIZE = 0x48000 -# SRAM_PUB_ADDR = 0x08046800 # 2M: 0x080ff400 -ADDR_FMPARAMSTRUCT = 0x08000800 -FLASH_ROW_SIZE = 512 -# Number of trials -TRIAL_MAX = 300 -SYSTEM_RESET = 0x0 -ONLY_CM4_RESET = 0x1 -INVALIDRESETTYPE = 0x3 -R_ACCESS = 0x01 -W_ACCESS = 0x02 -X_ACCESS = 0x04 -NIL_ACCESS = 0x00 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/__init__.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/__init__.py deleted file mode 100644 index acba3a75512..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/__init__.py +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from . import base -from . import programmer -from . import pyocd_wrapper diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/base.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/base.py deleted file mode 100644 index 0bd3d25f101..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/base.py +++ /dev/null @@ -1,179 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from enum import Enum -from abc import ABCMeta, abstractmethod - - -class ResetType(Enum): - SW = 1, - HW = 2 - - -class Interface(Enum): - SWD = 1 - JTAG = 2 - - -class ProgrammerBase(metaclass=ABCMeta): - def __init__(self): - pass - - @abstractmethod - def connect(self, target_name=None, interface=None): - """ - Connects to target. - :param target_name: The target name. - :param interface: Debug interface. - :return: True if connected successfully, otherwise False. - """ - raise NotImplementedError() - - @abstractmethod - def disconnect(self): - """ - Disconnects from target. - """ - raise NotImplementedError() - - @abstractmethod - def set_frequency(self, value_khz): - """ - Sets probe frequency. - :param value_khz: Frequency in kHz. - """ - raise NotImplementedError() - - @abstractmethod - def halt(self): - """ - Halts the target. - """ - raise NotImplementedError() - - @abstractmethod - def resume(self): - """ - Resumes the execution - """ - raise NotImplementedError() - - @abstractmethod - def reset(self, reset_type=ResetType.SW): - """ - Resets the target. - :param reset_type: The reset type. - """ - raise NotImplementedError() - - @abstractmethod - def reset_and_halt(self, reset_type=ResetType.SW): - """ - Resets the target and halts the CPU immediately after reset. - :param reset_type: The reset type. - """ - raise NotImplementedError() - - @abstractmethod - def read8(self, address): - """ - Reads 8-bit value from specified memory location. - :param address: The memory address to read. - :return: The read value. - """ - raise NotImplementedError() - - @abstractmethod - def read16(self, address): - """ - Reads 16-bit value from specified memory location. - :param address: The memory address to read. - :return: The read value. - """ - raise NotImplementedError() - - @abstractmethod - def read32(self, address): - """ - Reads 32-bit value from specified memory location. - :param address: The memory address to read. - :return: The read value. - """ - raise NotImplementedError() - - @abstractmethod - def write8(self, address, value): - """ - Writes 8-bit value by specified memory location. - :param address: The memory address to write. - :param value: The 8-bit value to write. - """ - raise NotImplementedError() - - @abstractmethod - def write16(self, address, value): - """ - Writes 16-bit value by specified memory location. - :param address: The memory address to write. - :param value: The 16-bit value to write. - """ - raise NotImplementedError() - - @abstractmethod - def write32(self, address, value): - """ - Writes 32-bit value by specified memory location. - :param address: The memory address to write. - :param value: The 32-bit value to write. - """ - raise NotImplementedError() - - @abstractmethod - def read_reg(self, reg_name): - """ - Gets value of a core register. - :param reg_name: Core register name. - :return: The register value. - """ - raise NotImplementedError() - - @abstractmethod - def write_reg(self, reg_name, value): - """ - Sets value of a core register. - :param reg_name: Core register name. - :param value: The value to set. - """ - raise NotImplementedError() - - @abstractmethod - def erase(self, address, size): - """ - Erases entire device flash or specified sectors. - :param address: The memory location. - :param size: The memory size. - """ - raise NotImplementedError() - - @abstractmethod - def program(self, filename, file_format=None, address=None): - """ - Programs a file into flash. - :param filename: Path to a file. - :param file_format: File format. Default is to use the file's extension. - :param address: Base address used for the address where to flash a binary. - :return: True if programmed successfully, otherwise False. - """ - raise NotImplementedError() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/exceptions.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/exceptions.py deleted file mode 100644 index 0183ced9e30..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/exceptions.py +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from pyocd.core.exceptions import TransferFaultError - - -class ExtendedTransferFaultError(TransferFaultError): - def __str__(self): - desc = super().__str__() - desc += ' If address points to a register it should be aligned with the register size.' - return desc diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/programmer.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/programmer.py deleted file mode 100644 index 2beda8b8c70..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/programmer.py +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from execute.programmer.pyocd_wrapper import Pyocd - - -tools = { - 'pyocd': Pyocd -} - - -class ProgrammingTool: - @staticmethod - def create(name): - tool_type = tools[name] - tool = tool_type() - return tool diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/pyocd_wrapper.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/pyocd_wrapper.py deleted file mode 100644 index 076250a4fbc..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/programmer/pyocd_wrapper.py +++ /dev/null @@ -1,272 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from execute.programmer.base import ProgrammerBase, Interface, ResetType -from pyocd.core.helpers import ConnectHelper -from pyocd.core import exceptions -from pyocd.flash import loader -from pyocd.flash.loader import FlashEraser -from pyocd import coresight -from execute.programmer.exceptions import ExtendedTransferFaultError - - -class Pyocd(ProgrammerBase): - def __init__(self): - super(Pyocd, self).__init__() - self.session = None - self.board = None - self.target = None - self.probe = None - - def connect(self, target_name=None, interface=None, probe_id=None): - """ - Connects to target using default debug interface. - :param target_name: The target name. - :param interface: Debug interface. - :param probe_id: Probe serial number. - :return: True if connected successfully, otherwise False. - """ - if interface: - raise NotImplementedError - else: - if target_name: - options = { - 'target_override': target_name - } - else: - options = {} - self.session = ConnectHelper.session_with_chosen_probe(blocking=True, options=options, board_id=probe_id, unique_id=probe_id) - if self.session is None: - return False - self.board = self.session.board - try: - self.session.open() - except exceptions.TransferFaultError as e: - if not self.board.target.is_locked(): - print(f"Transfer fault while initializing board: {e}") - return False - except Exception as e: - print(f"Exception while initializing board: {e}") - return False - - self.target = self.board.target - self.probe = self.session.probe - - # Write infinite loop into RAM and start core execution - self.halt() - # B662 - CPSIE I - Enable IRQ by clearing PRIMASK - # E7FE - B - Jump to address (argument is an offset) - self.write32(0x08000000, 0xE7FEB662) - self.write_reg('pc', 0x08000000) - self.write_reg('sp', 0x08001000) - self.write_reg('xpsr', 0x01000000) - self.resume() - - return True - - def disconnect(self): - """ - Closes active connection. - """ - if self.session is None: - raise ValueError('Debug session is not initialized.') - self.session.close() - - def set_frequency(self, value_khz): - """ - Sets probe frequency. - :param value_khz: Frequency in kHz. - """ - if self.probe is None: - raise ValueError('Debug probe is not initialized.') - self.probe.set_clock(value_khz * 1000) - - def halt(self): - """ - Halts the target. - """ - if self.session is None: - raise ValueError('Debug session is not initialized.') - self.target.halt() - - def resume(self): - """ - Resumes the execution - """ - if self.target is None: - raise ValueError('Target is not initialized.') - self.target.resume() - - def reset(self, reset_type=ResetType.SW): - """ - Resets the target. - :param reset_type: The reset type. - """ - if self.target is None: - raise ValueError('Target is not initialized.') - self.target.reset(reset_type=reset_type) - - def reset_and_halt(self, reset_type=ResetType.SW): - """ - Resets the target and halts the CPU immediately after reset. - :param reset_type: The reset type. - """ - if self.target is None: - raise ValueError('Target is not initialized.') - self.target.reset_and_halt(reset_type=reset_type) - - def read8(self, address): - """ - Reads 8-bit value from specified memory location. - :param address: The memory address to read. - :return: The read value. - """ - if self.target is None: - raise ValueError('Target is not initialized.') - try: - data = self.target.read_memory(address, transfer_size=8) - except exceptions.TransferFaultError as e: - raise ExtendedTransferFaultError(e.fault_address, e.fault_length) - return data - - def read16(self, address): - """ - Reads 16-bit value from specified memory location. - :param address: The memory address to read. - :return: The read value. - """ - if self.target is None: - raise ValueError('Target is not initialized.') - if (address & 0x01) == 0: - try: - data = self.target.read_memory(address, transfer_size=16) - except exceptions.TransferFaultError as e: - raise ExtendedTransferFaultError(e.fault_address, e.fault_length) - return data - else: - raise ValueError('Address not aligned.') - - def read32(self, address): - """ - Reads 32-bit value from specified memory location. - :param address: The memory address to read. - :return: The read value. - """ - if self.target is None: - raise ValueError('Target is not initialized.') - if (address & 0x03) == 0: - try: - data = self.target.read_memory(address, transfer_size=32) - except exceptions.TransferFaultError as e: - raise ExtendedTransferFaultError(e.fault_address, e.fault_length) - return data - else: - raise ValueError('Address not aligned.') - - def write8(self, address, value): - """ - Writes 8-bit value by specified memory location. - :param address: The memory address to write. - :param value: The 8-bit value to write. - """ - if self.target is None: - raise ValueError('Target is not initialized.') - try: - data = self.target.write_memory(address, value, transfer_size=8) - except exceptions.TransferFaultError as e: - raise ExtendedTransferFaultError(e.fault_address, e.fault_length) - return data - - def write16(self, address, value): - """ - Writes 16-bit value by specified memory location. - :param address: The memory address to write. - :param value: The 16-bit value to write. - """ - if self.target is None: - raise ValueError('Target is not initialized.') - try: - data = self.target.write_memory(address, value, transfer_size=16) - except exceptions.TransferFaultError as e: - raise ExtendedTransferFaultError(e.fault_address, e.fault_length) - return data - - def write32(self, address, value): - """ - Writes 32-bit value by specified memory location. - :param address: The memory address to write. - :param value: The 32-bit value to write. - """ - if self.target is None: - raise ValueError('Target is not initialized.') - try: - data = self.target.write_memory(address, value, transfer_size=32) - except exceptions.TransferFaultError as e: - raise ExtendedTransferFaultError(e.fault_address, e.fault_length) - return data - - def read_reg(self, reg_name): - """ - Gets value of a core register. - :param reg_name: Core register name. - :return: The register value. - """ - reg = reg_name.lower() - if reg in coresight.cortex_m.CORE_REGISTER: - value = self.target.read_core_register(reg) - return value - else: - raise ValueError(f'Unknown core register {reg}.') - - def write_reg(self, reg_name, value): - """ - Sets value of a core register. - :param reg_name: Core register name. - :param value: The value to set. - :return: The register value. - """ - reg = reg_name.lower() - if reg in coresight.cortex_m.CORE_REGISTER: - self.target.write_core_register(reg, value) - else: - raise ValueError(f'Unknown core register {reg}.') - - def erase(self, address, size): - """ - Erases entire device flash or specified sectors. - :param address: The memory location. - :param size: The memory size. - """ - region = self.session.target.memory_map.get_region_for_address(address) - if not region: - raise ValueError('Address 0x%08x is not within a memory region.' % address) - if not region.is_flash: - raise ValueError('Address 0x%08x is not in flash.' % address) - eraser = FlashEraser(self.session, FlashEraser.Mode.SECTOR) - address_range = f"{hex(address)}-{hex(address + size)}" - eraser.erase([address_range]) - - def program(self, filename, file_format=None, address=None): - """ - Programs a file into flash. - :param filename: Path to a file. - :param file_format: File format. Default is to use the file's extension. - :param address: Base address used for the address where to flash a binary. - :return: True if programmed successfully, otherwise False. - """ - if self.session is None: - raise ValueError('Debug session is not initialized.') - programmer = loader.FileProgrammer(self.session, chip_erase='sector') - programmer.program(filename, base_address=address, file_format=file_format) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/provision_device.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/provision_device.py deleted file mode 100644 index cb135b2b543..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/provision_device.py +++ /dev/null @@ -1,105 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import os -from time import sleep -from execute.helper import check_mode -from execute.enums import ProtectionState -from execute.sys_call import get_prov_details, provision_keys_and_policies -from execute.p6_memory_map import FLASH_ADDRESS, FLASH_SIZE -from execute.gen_data_from_json import ENTRANCE_EXAM_FW_STATUS_REG, ENTRANCE_EXAM_FW_STATUS_MASK, \ - ENTRANCE_EXAM_FW_STATUS_VAL -from execute.p6_reg import CYREG_CPUSS_PROTECTION, NVSTORE_AREA_1_ADDRESS - - -def provision_execution(tool, pub_key_json, prov_cmd_jwt, cy_bootloader_hex): - """ - Programs Cypress Bootloader and calls system calls for device provisioning. - :param tool: Programming/debugging tool used for communication with device. - :param pub_key_json: File where to save public key in JSON format. - :param prov_cmd_jwt: Path to provisioning JWT file (packet which contains - all data necessary for provisioning, including policy, authorization - packets and keys). - :param cy_bootloader_hex: Path to Cypress Bootloader program file. - :return: True if provisioning passed, otherwise False. - """ - tool.set_frequency(200) - - print("CPUSS.PROTECTION state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD.") - print(hex(CYREG_CPUSS_PROTECTION), hex(tool.read32(CYREG_CPUSS_PROTECTION))) - - reset_device(tool) - result, key = get_prov_details(tool, 1) - print('Device public key has been read successfully.' if result else 'FAIL: Cannot read device public key.') - print(key) - - with open(os.path.join(pub_key_json), 'w') as json_file: - json_file.write(key) - - # Check the device life-cycle stage - print('Check device protection state') - if not check_mode(tool, ProtectionState.secure): - return False - - print(os.linesep + 'Erase main flash and TOC3:') - print('erasing...') - tool.erase(FLASH_ADDRESS, FLASH_SIZE) - reset_device(tool) - - print(os.linesep + 'Read FB Firmware status:') - fb_firmware_status = tool.read32(ENTRANCE_EXAM_FW_STATUS_REG) - print(f'FB Firmware status = {hex(fb_firmware_status)}') - # Print Expected and received LIFECYCLE_STAGE values - print(f'Received FB_FW_STATUS = {hex(fb_firmware_status & ENTRANCE_EXAM_FW_STATUS_MASK)}') - print(f'Expected FB_FW_STATUS = {hex(ENTRANCE_EXAM_FW_STATUS_VAL)}') - # Verify if received value is the same as expected - is_exam_pass = (fb_firmware_status & ENTRANCE_EXAM_FW_STATUS_MASK) == ENTRANCE_EXAM_FW_STATUS_VAL - print('PASS: FB Firmware status is as expected' if is_exam_pass else 'FAIL: FB Firmware status is not as expected') - - if is_exam_pass: - print(os.linesep + 'PROGRAMMING APP HEX:') - tool.program(cy_bootloader_hex) - reset_device(tool) - - if is_exam_pass: - print(os.linesep + 'Run provisioning syscall') - blow_secure_fuse = 1 # indicates whether to convert device to SECURE CLAIMED mode - is_exam_pass = provision_keys_and_policies(tool, blow_secure_fuse, os.path.join(prov_cmd_jwt)) - print(hex(NVSTORE_AREA_1_ADDRESS) + ': ', sep=' ', end='', flush=True) - if is_exam_pass: - i = 0 - while i < 8 * 4: # output 8 words - print(hex(tool.read32(NVSTORE_AREA_1_ADDRESS + i)) + ' ', sep=' ', end='', flush=True) - i += 4 - print(os.linesep) - else: - print('FAIL: Unexpected ProvisionKeysAndPolicies syscall response') - - if is_exam_pass: - print('*****************************************') - print(" PROVISIONING PASSED ") - print("*****************************************") - - reset_device(tool) - return is_exam_pass - - -def reset_device(tool): - """ - Resets device and waits for device initialization. - :param tool: Programming/debugging tool used for communication with device. - """ - tool.reset() - sleep(0.2) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/sys_call.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/sys_call.py deleted file mode 100644 index a74bc4fce42..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/execute/sys_call.py +++ /dev/null @@ -1,198 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import os -from execute.gen_data_from_json import ENTRANCE_EXAM_SRAM_ADDR, ENTRANCE_EXAM_SRAM_SIZE -from execute.p6_reg import CYREG_IPC2_STRUCT_ACQUIRE, CYREG_IPC2_STRUCT_DATA, CYREG_IPC2_STRUCT_NOTIFY, \ - CYREG_IPC2_STRUCT_LOCK_STATUS - -PROVISION_KEYS_AND_POLICIES_OPCODE = 0x33 # ProvisionKeysAndPolicies API opcode -GET_PROV_DETAILS_OPCODE = 0x37 # GetProvDetails() API opcode -REGION_HASH_OPCODE = 0x31 # RegionHash() API opcode - - -def region_hash(tool, address, length, mode, exp_value): - """ - Procedure calls RegionHash syscall over IPC and read response. - :param tool: Programming/debugging tool used for communication with device. - :param address: Region hash address. - :param length: Region hash size. - :param mode: Region hash mode. - :param exp_value: Region hash expected value. - :return: True if syscall executed successfully, otherwise False. - """ - # Acquire IPC structure - tool.write32(CYREG_IPC2_STRUCT_ACQUIRE, 0x80000000) - ipc_acquire = 0 - while (ipc_acquire & 0x80000000) == 0: - ipc_acquire = tool.read32(CYREG_IPC2_STRUCT_ACQUIRE) - - # Set RAM address and Opcode - op_code = (REGION_HASH_OPCODE << 24) + (exp_value << 16) + (mode << 8) + 0 - tool.write32(CYREG_IPC2_STRUCT_DATA, ENTRANCE_EXAM_SRAM_ADDR) - tool.write32(ENTRANCE_EXAM_SRAM_ADDR, op_code) - - scratch_addr = ENTRANCE_EXAM_SRAM_ADDR + 0x08 - tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x04, scratch_addr) - tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x08, length) - tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x0C, address) - - # IPC_STRUCT[ipc_id].IPC_NOTIFY - - tool.write32(CYREG_IPC2_STRUCT_NOTIFY, 0x00000001) - - # Wait on response - response = 0x80000000 - while (response & 0x80000000) != 0: - response = tool.read32(CYREG_IPC2_STRUCT_LOCK_STATUS) - response = tool.read32(ENTRANCE_EXAM_SRAM_ADDR) - - if (response & 0xFF000000) == 0xa0000000: - print('Region compare complete') - return True - else: - print('Region compare error response:') - print(hex(CYREG_IPC2_STRUCT_DATA), hex(tool.read32(CYREG_IPC2_STRUCT_DATA))) - print(hex(ENTRANCE_EXAM_SRAM_ADDR), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR))) - print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x04), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x04))) - print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x08), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x08))) - print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x0C), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x0C))) - return False - - -def get_prov_details(tool, key_id): - """ - Calls GetProvDetails syscall over IPC. - :param tool: Programming/debugging tool used for communication with device. - :param key_id: Public key ID. - :return: True if get provision details successfully, otherwise False. - """ - # Acquire IPC structure - tool.write32(CYREG_IPC2_STRUCT_ACQUIRE, 0x80000000) - print(hex(CYREG_IPC2_STRUCT_ACQUIRE), hex(tool.read32(CYREG_IPC2_STRUCT_ACQUIRE))) - ipc_acquire = 0 - while (ipc_acquire & 0x80000000) == 0: - ipc_acquire = tool.read32(CYREG_IPC2_STRUCT_ACQUIRE) - - # Set RAM address and Opcode - op_code = GET_PROV_DETAILS_OPCODE << 24 - tool.write32(CYREG_IPC2_STRUCT_DATA, ENTRANCE_EXAM_SRAM_ADDR) # IPC_STRUCT.DATA - tool.write32(ENTRANCE_EXAM_SRAM_ADDR, op_code) # SRAM_SCRATCH - - scratch_addr = ENTRANCE_EXAM_SRAM_ADDR + 0x08 - tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x04, scratch_addr) - tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x08, key_id) - tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x0C, 0x0) - - # IPC_STRUCT[ipc_id].IPC_NOTIFY - - tool.write32(CYREG_IPC2_STRUCT_NOTIFY, 0x00000001) - - # Wait on response - response = 0x80000000 - while (response & 0x80000000) != 0: - response = tool.read32(CYREG_IPC2_STRUCT_LOCK_STATUS) - response = tool.read32(ENTRANCE_EXAM_SRAM_ADDR) - - print(hex(CYREG_IPC2_STRUCT_DATA), hex(tool.read32(CYREG_IPC2_STRUCT_DATA))) - print(hex(ENTRANCE_EXAM_SRAM_ADDR), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR))) # Expected MSB=0xA0 - print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x04), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x04))) - print(hex(ENTRANCE_EXAM_SRAM_ADDR + 0x08), hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x08))) - - is_exam_pass = (response & 0xFF000000) == 0xa0000000 - if is_exam_pass: - scratch_addr = tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x04) - read_hash_size = tool.read32(scratch_addr + 0x00) - read_hash_addr = tool.read32(scratch_addr + 0x04) - - i = 0 - response = '' - while i < read_hash_size: - # Save data in string format - hash_byte_chr = chr(tool.read8(read_hash_addr + i)) - response += hash_byte_chr - i += 1 - response = response.strip() - else: - print(hex(CYREG_IPC2_STRUCT_DATA), tool.read32(CYREG_IPC2_STRUCT_DATA)) - print(hex(ENTRANCE_EXAM_SRAM_ADDR), tool.read32(ENTRANCE_EXAM_SRAM_ADDR)) - response = None - - return is_exam_pass, response - - -def provision_keys_and_policies(tool, blow_secure_efuse, filename): - """ - Calls ProvisionKeysAndPolicies syscall over IPC. - :param tool: Programming/debugging tool used for communication with device. - :param blow_secure_efuse: Indicates whether to convert device to SECURE CLAIMED mode. - :param filename: Path to provisioning JWT file (packet which contains - all data necessary for provisioning, including policy, authorization - packets and keys). - :return: True if sending provision keys and policies passed, otherwise False - """ - file_size = os.path.getsize(filename) - if file_size > ENTRANCE_EXAM_SRAM_SIZE: - print('JWT packet too long') - return False - - print('UDS eFuses will be blown' if blow_secure_efuse == 1 else 'UDS eFuses will NOT be blown') - print(f'JWT packet size: {file_size}') - with open(filename, 'r+') as jwt_file: - jwt_file.seek(0) - content = jwt_file.read() - jwt_chars = list(content) - - # Acquires IPC structure. - tool.write32(CYREG_IPC2_STRUCT_ACQUIRE, 0x80000000) - print(hex(CYREG_IPC2_STRUCT_ACQUIRE), hex(tool.read32(CYREG_IPC2_STRUCT_ACQUIRE))) - - ipc_acquire = 0 - while (ipc_acquire & 0x80000000) == 0: - ipc_acquire = tool.read32(CYREG_IPC2_STRUCT_ACQUIRE) - - # Set RAM address and Opcode - tool.write32(CYREG_IPC2_STRUCT_DATA, ENTRANCE_EXAM_SRAM_ADDR) - tool.write32(ENTRANCE_EXAM_SRAM_ADDR, (PROVISION_KEYS_AND_POLICIES_OPCODE << 24) + (blow_secure_efuse << 16)) - - scratch_addr = ENTRANCE_EXAM_SRAM_ADDR + 0x08 - tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x04, scratch_addr) - tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x08, file_size + 0x04) - scratch_addr = ENTRANCE_EXAM_SRAM_ADDR + 0x0C - - for char in jwt_chars: - tool.write8(scratch_addr, ord(char)) - scratch_addr += 1 - - # IPC_STRUCT[ipc_id].IPC_NOTIFY - - tool.write32(CYREG_IPC2_STRUCT_NOTIFY, 0x00000001) - print(hex(CYREG_IPC2_STRUCT_NOTIFY), hex(tool.read32(CYREG_IPC2_STRUCT_NOTIFY))) - # Wait on response - response = 0x80000000 - while (response & 0x80000000) != 0: - response = tool.read32(CYREG_IPC2_STRUCT_LOCK_STATUS) - - # Read response for test - print(hex(CYREG_IPC2_STRUCT_DATA), hex(tool.read32(CYREG_IPC2_STRUCT_DATA))) - print(hex(ENTRANCE_EXAM_SRAM_ADDR) + ': ', sep=' ', end='', flush=True) - i = 0 - while i < 4 * 4: # output 4 words - print(hex(tool.read32(ENTRANCE_EXAM_SRAM_ADDR)) + ' ', sep=' ', end='', flush=True) - i += 4 - print(os.linesep) - - response = tool.read32(ENTRANCE_EXAM_SRAM_ADDR) - result = (response & 0xFF000000) == 0xa0000000 - - print('ProvisionKeysAndPolicies', 'complete' if result else f'error response: {hex(response)}') - return result diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/keygen.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/keygen.py deleted file mode 100644 index f23e74a91f6..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/keygen.py +++ /dev/null @@ -1,73 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import os -import click -import json -from jwcrypto import jwk - -CUSTOMER_KEY_ID_MIN = 6 -CUSTOMER_KEY_ID_MAX = 10 - -kid_help = 'Key ID to define key slot number in the key storage. Key ID must be in range {}.' - -@click.command() -@click.option('-k', '--kid', 'kId', - type=click.IntRange(CUSTOMER_KEY_ID_MIN, CUSTOMER_KEY_ID_MAX), - default=CUSTOMER_KEY_ID_MIN, - help=kid_help.format(str(list(range(CUSTOMER_KEY_ID_MIN, CUSTOMER_KEY_ID_MAX+1))))) -@click.option('--jwk', 'jwKey', - type=click.File('w'), - default='key.json', - help='Name of the key in JWK format to create.') -@click.option('--pem-priv', 'pemPriv', - type=click.File('wb'), - default=None, - help='Name of the private key in PEM format to create. If it is not given PEM file will not be created.') -@click.option('--pem-pub', 'pemPub', - type=click.File('wb'), - default=None, - help='Name of the public key in PEM format to create. If it is not given PEM file will not be created.') -@click.option('--aes', 'aes', - type=click.File('w'), - default=None, - help='Name of the AES-128 key to create. If it is given only AES key wiil be created and JWK will not.') -def main(kId, jwKey, pemPriv, pemPub, aes): - if aes == None: - key = jwk.JWK.generate(kty='EC', crv='P-256', use='sig') - - keyJson = json.loads(key.export(private_key=True)) - keyJson['kid'] = str(kId) - - keyStr = json.dumps(keyJson, indent=4) - jwKey.write(keyStr) - - if pemPriv != None: - pemPriv.write(key.export_to_pem(private_key=True, password=None)) - - if pemPub != None: - pemPub.write(key.export_to_pem(private_key=False, password=None)) - - print(keyStr) - else: - key = os.urandom(16) - iv = os.urandom(16) - file = key.hex() + '\n' + iv.hex() - aes.write(file) - print('AES-128 KEY: ', key.hex(), sep='\t') - print('AES-128 IV:', iv.hex(), sep='\t') - -if __name__ == "__main__": - main() \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/example_cert.pem b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/example_cert.pem similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/example_cert.pem rename to targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/example_cert.pem diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4.json similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4.json rename to targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4.json diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4_smif.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_smif.json similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4_smif.json rename to targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_smif.json index 9bb1f75d0e0..36bb8fb840c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/policy_single_stage_CM4_smif.json +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_smif.json @@ -90,7 +90,7 @@ "id": 4, "monotonic": 0, "smif_id": 1, - "upgrade": true, + "upgrade": false, "encrypt": false, "encrypt_key_id": 1, "upgrade_auth": [ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex deleted file mode 100644 index ed18b2a5472..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex +++ /dev/null @@ -1,2396 +0,0 @@ -:02000004100DDD -:1000000000C00208334B0D100D000000A14B0D1075 -:1000100000000000000000000000000000000000E0 -:100020000000000000000000000000009D4B0D10CB -:1000300000000000000000009D4B0D109D4B0D10B6 -:100040009D4B0D109D4B0D109D4B0D109D4B0D109C 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-:04000005100D4EDFAD -:00000001FF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt deleted file mode 100644 index ddb28220334..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/CyBootloader_WithLogs/CypressBootloader_CM0p.jwt +++ /dev/null @@ -1 +0,0 @@ -eyJhbGciOiJFUzI1NiJ9.eyJjeV9wdWJfa2V5Ijp7ImNydiI6IlAtMjU2Iiwia2lkIjoiMyIsImt0eSI6IkVDIiwidXNlIjoic2lnIiwieCI6IlNiOGxUcHlfcGQzTnJVVGtoSXpnMmp6TTM3dU5xTml1dDhXQy1RdjNYTVEiLCJ5IjoiQ3R3Q2k0YXJYc2pFRDVUVm1yX3ZQbFAya2UxMzNLSzdsUDdTel9JWmlERSJ9LCJleHAiOjE1Nzc3NDMyMDAsImlhdCI6MTU2MzI4NjA3NiwiaW1hZ2VfYWRkcmVzcyI6MjY5Mjg3NDI0LCJpbWFnZV9maWxlIjoiQ3lwcmVzc0Jvb3Rsb2FkZXJfQ00wcC5oZXgiLCJpbWFnZV9oYXNoIjpbMTY3LDExNSwxMTUsNjIsNiwyMjEsMTIsMjM0LDE0MiwzNyw0NiwyNTQsMjM5LDI0OCw2MCwxNTcsOTksNCwxOTcsMTc1LDIxNiw4MCwxMDIsNDYsMTY5LDE5NiwxNzgsNTMsOTQsNDksMjMxLDIwMl0sImltYWdlX2lkIjowLCJpbWFnZV92ZXJzaW9uIjoiMS4wLjAuMTI1IiwicG9saWN5X3RlbXBsYXRlIjoiIn0.kC_8cSqHKBHl1770umc1em1ZhuwjSHKxY1TigIBjcPVd_Gnr2X4LcMGIB6biwVWWYmtONF7k87XXfpM4NqByAg \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/LICENSE b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/LICENSE deleted file mode 100644 index 7adfadddb21..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/LICENSE +++ /dev/null @@ -1,51 +0,0 @@ -Copyright (c) 2018-2019 Cypress Semiconductor Corporation - -Permissive Binary License - -Version 1.0, September 2015 - -Redistribution. Redistribution and use in binary form, without -modification, are permitted provided that the following conditions are -met: - -1) Redistributions must reproduce the above copyright notice and the - following disclaimer in the documentation and/or other materials - provided with the distribution. - -2) Unless to the extent explicitly permitted by law, no reverse - engineering, decompilation, or disassembly of this software is - permitted. - -3) Redistribution as part of a software development kit must include the - accompanying file named "DEPENDENCIES" and any dependencies listed in - that file. - -4) Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -Limited patent license. The copyright holders (and contributors) grant a -worldwide, non-exclusive, no-charge, royalty-free patent license to -make, have made, use, offer to sell, sell, import, and otherwise -transfer this software, where such license applies only to those patent -claims licensable by the copyright holders (and contributors) that are -necessarily infringed by this software. This patent license shall not -apply to any combinations that include this software. No hardware is -licensed hereunder. - -If you institute patent litigation against any entity (including a -cross-claim or counterclaim in a lawsuit) alleging that the software -itself infringes your patent(s), then your rights granted under this -license shall terminate as of the date such litigation is filed. - -DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND -CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT -NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/cy_auth.jwt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/cy_auth.jwt deleted file mode 100644 index ce5af311fca..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/cy_auth.jwt +++ /dev/null @@ -1 +0,0 @@ -eyJhbGciOiJFUzI1NiJ9.eyJhdXRoIjp7fSwiY3lfcHViX2tleSI6eyJjcnYiOiJQLTI1NiIsImtpZCI6IjMiLCJrdHkiOiJFQyIsInVzZSI6InNpZyIsIngiOiJTYjhsVHB5X3BkM05yVVRraEl6ZzJqek0zN3VOcU5pdXQ4V0MtUXYzWE1RIiwieSI6IkN0d0NpNGFyWHNqRUQ1VFZtcl92UGxQMmtlMTMzS0s3bFA3U3pfSVppREUifSwiZXhwIjoxNTc3NzQzMjAwLCJoc21fcHViX2tleSI6eyJjcnYiOiJQLTI1NiIsImtpZCI6IjQiLCJrdHkiOiJFQyIsInVzZSI6InNpZyIsIngiOiJzSk1zTi0ySm8yN2tjNTF3Vks3eEoyZlA5QkRrekFjMmZaRVpNbG9oSFhBIiwieSI6Ik1XbHV6bVhnWE92ZFFRRFlYM3l5MVRrOVFvSEwtOURaaHN3WnBZMFhlNVUifSwiaWF0IjoxNTUzNjg1NTczLCJ0eXBlIjoiQ1lfQVVUSF9IU00ifQ.oXeFYugOceM2XvnoWTEju8ByztA4OvFKrQxndIOts_nlgmRti2ddoHRGR86GMNCDfcHr54mXH33GkQ8D96DoGw \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/hsm_state.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/hsm_state.json deleted file mode 100644 index e2481709d9f..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/hsm_state.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "hsm_priv_key": { - "crv": "P-256", - "d": "d-r9nPjLka7g5BHiT7OexYV7na-ofuNfjPPN4XvP_yQ", - "kty": "EC", - "use": "sig", - "x": "sJMsN-2Jo27kc51wVK7xJ2fP9BDkzAc2fZEZMlohHXA", - "y": "MWluzmXgXOvdQQDYX3yy1Tk9QoHL-9DZhswZpY0Xe5U" - }, - "hsm_pub_key": { - "crv": "P-256", - "kty": "EC", - "use": "sig", - "kid": "4", - "x": "sJMsN-2Jo27kc51wVK7xJ2fP9BDkzAc2fZEZMlohHXA", - "y": "MWluzmXgXOvdQQDYX3yy1Tk9QoHL-9DZhswZpY0Xe5U" - } -} \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/oem_state.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/oem_state.json deleted file mode 100644 index 978cfbd2358..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/oem_state.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "oem_priv_key": { - "crv": "P-256", - "d": "JVozA1oRvg-zSotMUbrGebV3oBhBaF1mqUyEn_Fdcqc", - "kty": "EC", - "use": "sig", - "x": "vfb7_jewTxpFVINcXdrZQJBArC5igrN0BLc783FigrM", - "y": "9rBBUKXzpj1A5K7fxPtEaJdsfo7Jj_wsF7LTZLc-sPM" - }, - "oem_pub_key": { - "crv": "P-256", - "kty": "EC", - "use": "sig", - "kid": "5", - "x": "vfb7_jewTxpFVINcXdrZQJBArC5igrN0BLc783FigrM", - "y": "9rBBUKXzpj1A5K7fxPtEaJdsfo7Jj_wsF7LTZLc-sPM" - } -} \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/LICENSE-2.0.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/LICENSE-2.0.txt deleted file mode 100644 index 7a4a3ea2424..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/LICENSE-2.0.txt +++ /dev/null @@ -1,202 +0,0 @@ - - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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However, in accepting such obligations, You may act only - on Your own behalf and on Your sole responsibility, not on behalf - of any other Contributor, and only if You agree to indemnify, - defend, and hold each Contributor harmless for any liability - incurred by, or claims asserted against, such Contributor by reason - of your accepting any such warranty or additional liability. - - END OF TERMS AND CONDITIONS - - APPENDIX: How to apply the Apache License to your work. - - To apply the Apache License to your work, attach the following - boilerplate notice, with the fields enclosed by brackets "[]" - replaced with your own identifying information. (Don't include - the brackets!) The text should be enclosed in the appropriate - comment syntax for the file format. We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright [yyyy] [name of copyright owner] - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/README.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/README.txt deleted file mode 100644 index 3c082fb3baa..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Apache/README.txt +++ /dev/null @@ -1,5 +0,0 @@ -The following are licensed under the Apache 2.0 license: - -mcuboot -Mbed Crypto - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/MIT/cjason-license.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/MIT/cjason-license.txt deleted file mode 100644 index 9b4fcd8266b..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/MIT/cjason-license.txt +++ /dev/null @@ -1,23 +0,0 @@ -Copyright (c) 2009 Dave Gamble - -Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - -The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt deleted file mode 100644 index 8ab19243a91..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prebuild/third_party_licenses/Other/bsd_base64_license.txt +++ /dev/null @@ -1,46 +0,0 @@ -/* - * $ Copyright Cypress Semiconductor $ - */ -/* $OpenBSD: base64.c,v 1.3 1997/11/08 20:46:55 deraadt Exp $ */ - -/* - * Copyright (c) 1996 by Internet Software Consortium. - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND INTERNET SOFTWARE CONSORTIUM DISCLAIMS - * ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL INTERNET SOFTWARE - * CONSORTIUM BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL - * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR - * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS - * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS - * SOFTWARE. - */ - -/* - * Portions Copyright (c) 1995 by International Business Machines, Inc. - * - * International Business Machines, Inc. (hereinafter called IBM) grants - * permission under its copyrights to use, copy, modify, and distribute this - * Software with or without fee, provided that the above copyright notice and - * all paragraphs of this notice appear in all copies, and that the name of IBM - * not be used in connection with the marketing of any product incorporating - * the Software or modifications thereof, without specific, written prior - * permission. - * - * To the extent it has a right to do so, IBM grants an immunity from suit - * under its patents, if any, for the use, sale or manufacture of products to - * the extent that such products are used for performing Domain Name System - * dynamic updates in TCP/IP networks by means of the Software. No immunity is - * granted for any product per se or for any other function of any product. - * - * THE SOFTWARE IS PROVIDED "AS IS", AND IBM DISCLAIMS ALL WARRANTIES, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE. IN NO EVENT SHALL IBM BE LIABLE FOR ANY SPECIAL, - * DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER ARISING - * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE, EVEN - * IF IBM IS APPRISED OF THE POSSIBILITY OF SUCH DAMAGES. - */ \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_crypto.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_crypto.py deleted file mode 100644 index f73b4b73ee6..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_crypto.py +++ /dev/null @@ -1,116 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from jwcrypto import jwk, jws, jwt -from jwcrypto.common import base64url_decode -from jwcrypto.common import json_decode -from datetime import datetime -import json -import copy - -class crypto : - - def create_jwk() : - key = jwk.JWK.generate(kty='EC', crv='P-256', use='sig') - pub_key= json.loads( key.export(private_key=False) ) - priv_key= json.loads( key.export(private_key=True) ) - - print( "create_jwk()= " + json.dumps( pub_key, indent=4 ) ) - return priv_key,pub_key - - def create_jwt( payload , key ) : - token= jwt.JWT( header={"alg": "ES256"},claims=payload ) - token.make_signed_token( jwk.JWK( **key ) ) - txt= token.serialize(compact=True) - - print( "create_jwt()= " + json.dumps( crypto.readable_jwt(txt) ,indent=4 )) - return txt - - def readable_jwt( txt ) : - """ - Convert a JWT token in base64url into a readable dictionary object - with decoded payload and header for printing and logging - """ - lst= txt.split('.') - readable= {} - readable["protected"]= json_decode(base64url_decode(lst[0])) - readable["payload"]= json_decode(base64url_decode(lst[1])) - readable["signature"]= lst[2] - - # create readable timestamps for exp/iat claims - payload= readable["payload"] - if "iat" in payload : - t= payload["iat"] - if isinstance(t,int) : - t= datetime.fromtimestamp(t).isoformat(' ') - payload["iat"]= t - if "exp" in payload : - t= payload["exp"] - if isinstance(t,int) : - t= datetime.fromtimestamp(t).isoformat(' ') - payload["exp"]= t - - print(json.dumps(readable,indent=4,sort_keys=False)) - return readable - - def dump_jwt( txt,file_name ) : - """ - Dumps a JWT dictionary object into a text file - """ - with open(file_name,"w") as f : - f.write(txt) - f.close() - - def read_jwt( file_name ) : - """ - Reads a JWT dictionary object from a text file - """ - with open(file_name,"r") as f : - txt = f.read() - f.close() - - return txt - - def jwt_payload( txt ) : - """ - Returns the payload of a JWT without validating it's signature - Sometimes used for tokens that contain a public key in its payload, where the signature proves possesion of the corresponding private key - In that case, the payload is needed to obtain the public key with which to then validate the JWT - """ - # split the token - lst= txt.split('.') - payload= lst[1] - obj= json_decode(base64url_decode(payload)) - return obj - - def validate_jwt( txt , key ) : - """ - Validates a signed JWT - """ - try : - jwt.JWT(key=jwk.JWK(**key),jwt=txt) - print( " JWT signature is valid" ) - return True - except : - print( " JWT signature is not valid" ) - return False - - def create_x509_cert( pub_key , priv_key , prod_id , die_id=None , dev_id=None ) : - """ - TODO: create a X.509 certificate here certifying pub_key, signed with private_key - """ - cert= "CertificateToBeDone(die_id={},dev_id={},prod_id={})".format(die_id,dev_id,prod_id) - return cert - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_customer.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_customer.py deleted file mode 100644 index 4433ac92d78..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_customer.py +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from cyprov_entity import Entity -from cyprov_crypto import crypto - -# Customer Entity -class CustomerEntity(Entity): - def __init__(self, state_name, audit_name) : - Entity.__init__(self, state_name, audit_name) - if "custom_priv_key" not in self.state: - d = dict() - d["custom_priv_key"] = self.state - self.state = d - - def create_entity(self, kid) : - """ - Creates the Customer entity. - Creates the Customer main key-pair and returns nothing. - """ - customer_priv_key, customer_pub_key = crypto.create_jwk() - customer_priv_key["kid"] = str(kid) - customer_pub_key["kid"] = str(kid) - self.state["custom_priv_key"] = customer_priv_key - self.state["custom_pub_key"] = customer_pub_key - self.state_loaded = True - - def get_pub_key(self): - if "custom_pub_key" not in self.state: - key = dict(self.state["custom_priv_key"]) - del key["d"] - else: - key = self.state["custom_pub_key"] - return key - - def get_priv_key(self): - return self.state["custom_priv_key"] - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_entity.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_entity.py deleted file mode 100644 index 456e2ead237..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_entity.py +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import json - -# Cypress Entity -class Entity : - def __init__( self , state_name , audit_name ) : - self.state_name= state_name - self.state_loaded= False - self.audit_name= audit_name - Entity.load_state(self) - - def load_state( self ) : - try : - with open(self.state_name,"r+") as f : - self.state= json.loads(f.read()) - f.close() - self.state_loaded= True - except FileNotFoundError: - self.state= {} - self.state_loaded= False - - def save_state( self ) : - if not self.state_loaded : - raise Exception( "Internal error - state not loaded" ) - with open(self.state_name,"w") as f : - f.write( json.dumps( self.state,indent=4 ) ) - f.close() - - def append_audit_record( self,record ) : - with open(self.audit_name,"a") as f : - f.write( json.dumps(record,indent=4) + "\n" ) - f.close() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_hsm.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_hsm.py deleted file mode 100644 index f4e1789921f..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_hsm.py +++ /dev/null @@ -1,443 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import os -from cyprov_types import types -from cyprov_entity import Entity -from cyprov_crypto import crypto -from datetime import datetime -from datetime import timedelta - - -# HSM Entity -class HsmEntity(Entity): - def __init__(self, state_name, audit_name): - Entity.__init__(self, state_name, audit_name) - - def create_entity(self): - """ - Creates the HSM entity. - Creates the hsm_priv_key,hsm_pub_key key-pair. - """ - hsm_priv_key, hsm_pub_key = crypto.create_jwk() - self.state["hsm_priv_key"] = hsm_priv_key - self.state["hsm_pub_key"] = hsm_pub_key - - def request_disti_authorization(self): - """ - HSM creates a request for authorization to Distributor - It includes just the HSM public key and a one week expiration limit - We use a JWT to prove knowledge of the private key and convey an expiration limit - """ - hsm_priv_key = self.state["hsm_priv_key"] - hsm_pub_key = self.state["hsm_pub_key"] - - # create the request - exp = datetime.now() + timedelta(7) - payload = {} - payload["type"] = types.HSM_REQ_DISTI_AUTH - payload["hsm_pub_key"] = hsm_pub_key - payload["iat"] = int(datetime.now().timestamp()) - payload["exp"] = int(exp.timestamp()) - auth_req = crypto.create_jwt(payload, hsm_priv_key) - - # Create audit record - record = {} - record["type"] = types.HSM_REQ_DISTI_AUTH - record["iat"] = datetime.now().isoformat(' ') - record["auth_req"] = crypto.readable_jwt(auth_req) - self.append_audit_record(record) - - return auth_req - - def install_disti_auth(self, disti_auth): - """ - Install distributor authorization. - Returns nothingraise Exception( - """ - hsm_pub_key = self.state["hsm_pub_key"] - - # Validate the distributor authorization - disti_auth_payload = crypto.jwt_payload(disti_auth) - disti_pub_key = disti_auth_payload["disti_pub_key"] - if not crypto.validate_jwt(disti_auth, disti_pub_key): - raise Exception("Invalid signature for distributor authorization") - if disti_auth_payload["type"] != types.DISTI_AUTH_HSM: - raise Exception("Invalid type for distributor authorization") - if disti_auth_payload["hsm_pub_key"] != hsm_pub_key: - raise Exception("Distributor authorization is not for this HSM") - if datetime.fromtimestamp(disti_auth_payload["exp"]) < datetime.now(): - raise Exception("Distributor authorization expired") - - # install distributor key and authorization - self.state["disti_pub_key"] = disti_pub_key - self.state["disti_auth"] = disti_auth - self.state["disti_auth_readable"] = crypto.readable_jwt(disti_auth) - - # create audit record - record = {} - record["type"] = types.DISTI_AUTH_HSM - record["iat"] = datetime.now().isoformat(' ') - record["disti_auth"] = crypto.readable_jwt(disti_auth) - self.append_audit_record(record) - - def request_cy_authorization(self, cy_pub_key=None): - """ - HSM creates a request for authorization to CY - It contains the HSM public key, the distributor authorization and a 1 week expiration - The JWT proves knowledge of the private key and the distributor authorization is used by CY to identify the request - """ - hsm_priv_key = self.state["hsm_priv_key"] - hsm_pub_key = self.state["hsm_pub_key"] - disti_auth = self.state["disti_auth"] - - # create the authorization request - exp = datetime.now() + timedelta(7) - payload = {} - payload["type"] = types.HSM_REQ_CY_AUTH - payload["hsm_pub_key"] = hsm_pub_key - payload["disti_auth"] = disti_auth - payload["iat"] = int(datetime.now().timestamp()) - payload["exp"] = int(exp.timestamp()) - if cy_pub_key != None: - payload["cy_pub_key"] = cy_pub_key - auth_req = crypto.create_jwt(payload, hsm_priv_key) - - # create audit record - cy_auth_readable = crypto.readable_jwt(auth_req) - cy_auth_readable["payload"]["disti_auth"] = crypto.readable_jwt(cy_auth_readable["payload"]["disti_auth"]) - record = {} - record["type"] = types.HSM_REQ_CY_AUTH - record["iat"] = datetime.now().isoformat(' ') - record["cy_auth_req"] = cy_auth_readable - self.append_audit_record(record) - - # install the cy_pub_key if one is given (allows for explicit binding to Cypress or some other supplier) - self.state["cy_pub_key"] = cy_pub_key - - return auth_req - - def install_cy_auth(self, cy_auth, cy_pub_key=None): - """ - Install Cypress authorization. - First checks the signature on the token and then just stores it - The expiration date on the token is enforced by the HSM only (since device has not time). - The authorization privilages (which may contain serial number and/or wounding limitations) are enforced by the device. - """ - hsm_pub_key = self.state["hsm_pub_key"] - - # validate the authorization - cy_auth_payload = crypto.jwt_payload(cy_auth) - if cy_pub_key == None: - cy_pub_key = cy_auth_payload["cy_pub_key"] - elif cy_auth_payload["cy_pub_key"] != cy_pub_key: - raise Exception("Cypress authorization is not from Cypress") - if not crypto.validate_jwt(cy_auth, cy_pub_key): - raise Exception("Invalid signature for CY HSM authorization") - if cy_auth_payload["type"] != types.CY_AUTH_HSM: - raise Exception("Invalid type for CY HSM authoriation") - if datetime.fromtimestamp(cy_auth_payload["exp"]) < datetime.now(): - raise Exception("CY HSM authorization is expired") - if cy_auth_payload["cy_pub_key"] != cy_pub_key: - raise Exception("Authorization appears to be not from Cypress") - - # install the authorization - self.state["cy_pub_key"] = cy_pub_key - self.state["cy_auth"] = cy_auth - self.state["cy_auth_readable"] = crypto.readable_jwt(cy_auth) - self.state["products"] = {} - - # create audit record - record = {} - record["type"] = types.CY_AUTH_HSM - record["iat"] = datetime.now().isoformat(' ') - record["cy_auth"] = crypto.readable_jwt(cy_auth) - self.append_audit_record(record) - - def create_signing_key(self, prod_id): - """ - Creates a signing-key package that an OEM uses to create its chain of trust - One or more OEM projects may share the same signing key - An HSM can maintain multiple signing keys for multiple OEMs, identified by a string "prod_id" - HSM operator must make sure that "prod_id" is unique across all of its customers, e.g. by including the customer name or ID - """ - cy_auth = self.state["cy_auth"] - disti_auth = self.state["disti_auth"] - hsm_priv_key = self.state["hsm_priv_key"] - - # create the signing key - signing_priv_key, signing_pub_key = crypto.create_jwk() - - # create the token - exp = datetime.now() + timedelta(7) - payload = {} - payload["type"] = types.HSM_SIGNING_KEY_PKG - payload["iat"] = int(datetime.now().timestamp()) - payload["exp"] = int(exp.timestamp()) - payload["prod_id"] = prod_id - payload["signing_pub_key"] = signing_pub_key - payload["cy_auth"] = cy_auth - payload["disti_auth"] = disti_auth - signing_pkg = crypto.create_jwt(payload, hsm_priv_key) - - # store signing key for later use - prod = {} - prod["iat"] = int(datetime.now().timestamp()) - prod["signing_priv_key"] = signing_priv_key - prod["signing_pub_key"] = signing_pub_key - self.state["products"][prod_id] = prod - - # create audit record - signing_pkg_readable = crypto.readable_jwt(signing_pkg) - signing_pkg_readable["payload"]["cy_auth"] = crypto.readable_jwt(signing_pkg_readable["payload"]["cy_auth"]) - signing_pkg_readable["payload"]["disti_auth"] = crypto.readable_jwt( - signing_pkg_readable["payload"]["disti_auth"]) - record = {} - record["type"] = types.HSM_SIGNING_KEY_PKG - record["iat"] = datetime.now().isoformat(' ') - record["signing_pkg"] = signing_pkg_readable - self.append_audit_record(record) - - return signing_pkg - - def install_rot_authorization(self, rot_auth_pkg): - """ - The HSM checks the response package and the rot_auth token itself and simply stores it for later use - """ - hsm_pub_key = self.state["hsm_pub_key"] - - rot_auth_pkg_payload = crypto.jwt_payload(rot_auth_pkg) - prod_id = rot_auth_pkg_payload["prod_id"] - rot_auth = rot_auth_pkg_payload["rot_auth"] - chain_of_trust = rot_auth_pkg_payload["chain_of_trust"] - - # validate the RoT authorization - rot_auth_payload = crypto.jwt_payload(rot_auth) - oem_pub_key = rot_auth_payload["oem_pub_key"] - if not crypto.validate_jwt(rot_auth, oem_pub_key): - raise Exception("Invalid signature on OEM root-of-trust authorization") - if rot_auth_payload["type"] != types.OEM_ROT_AUTH: - raise Exception("Invalid type for OEM root-of-trust authorization") - if rot_auth_payload["hsm_pub_key"] != hsm_pub_key: - raise Exception("Invalid HSM public key in OEM root-of-trust authorization") - if rot_auth_payload["prod_id"] != prod_id: - raise Exception("Invalid prod_id in OEM root-of-trust authorization") - - # validate the package itself - if not crypto.validate_jwt(rot_auth_pkg, oem_pub_key): - raise Exception("Invalid signature on OEM root-of-trust authorization package") - if rot_auth_pkg_payload["type"] != types.OEM_ROT_AUTH_PKG: - raise Exception("Invalid type for OEM root-of-trust authorization package") - if datetime.fromtimestamp(rot_auth_pkg_payload["exp"]) < datetime.now(): - raise Exception("OEM root-of-trust authorization package is expired") - - # store the result for later usage - prod = self.state["products"][prod_id] - prod["oem_pub_key"] = oem_pub_key - prod["rot_auth"] = rot_auth - prod["rot_auth_readable"] = crypto.readable_jwt(rot_auth) - prod["chain_of_trust"] = chain_of_trust - - # create audit record - rot_auth_pkg_readable = crypto.readable_jwt(rot_auth_pkg) - rot_auth_pkg_readable["payload"]["rot_auth"] = crypto.readable_jwt(rot_auth_pkg_readable["payload"]["rot_auth"]) - record = {} - record["type"] = types.OEM_ROT_AUTH_PKG - record["iat"] = datetime.now().isoformat(' ') - record["rot_auth_pkg"] = rot_auth_pkg_readable - self.append_audit_record(record) - - def create_rot_command(self, prod_id): - """ - The cy_auth token means Cypress authorized the HSM for provisioning - The rot_auth token means that the OEM authorized the HSM to provision RoT on its behalf - Together, they form the RoT command to the device - """ - hsm_priv_key = self.state["hsm_priv_key"] - cy_auth = self.state["cy_auth"] - rot_auth = self.state["products"][prod_id]["rot_auth"] - - # check CY authorization has not expired - cy_auth_payload = crypto.jwt_payload(cy_auth) - if datetime.fromtimestamp(cy_auth_payload["exp"]) < datetime.now(): - raise Exception("Cypress authorization for HSM expired") - - # create the RoT command - payload = {} - payload["type"] = types.HSM_ROT_CMD - payload["prod_id"] = prod_id - payload["cy_auth"] = cy_auth - payload["rot_auth"] = rot_auth - rot_cmd = crypto.create_jwt(payload, hsm_priv_key) - - # create audit record - rot_cmd_readable = crypto.readable_jwt(rot_cmd) - rot_cmd_readable["payload"]["cy_auth"] = crypto.readable_jwt(rot_cmd_readable["payload"]["cy_auth"]) - rot_cmd_readable["payload"]["rot_auth"] = crypto.readable_jwt(rot_cmd_readable["payload"]["rot_auth"]) - record = {} - record["type"] = types.HSM_ROT_CMD - record["iat"] = datetime.now().isoformat() - record["rot_cmd"] = rot_cmd_readable - self.append_audit_record(record) - - return rot_cmd - - def accept_provision_authorization(self, prov_auth): - """ - Accepts a provisioning request from an OEM, that is authorized by the distributor - prov_req= jwt( payload={ OEM_PROV_REQ , blob } , key=oem_priv_key ) - prov_auth= jwt( payload={ DISTI_PROV_AUTH , prov_req , cnt , exp } , key=disti_priv_key ) - When successful 'installs' the provisioning request in the HSM as the active request for given prod_id - """ - disti_pub_key = self.state["disti_pub_key"] - - # validate the Disti's command - prov_auth_payload = crypto.jwt_payload(prov_auth) - if not crypto.validate_jwt(prov_auth, disti_pub_key): - raise Exception("Invalid signature for provisioning authorization") - if prov_auth_payload["type"] != types.DISTI_PROV_AUTH: - raise Exception("Invalid type for provisioning authorization") - prov_req = prov_auth_payload["prov_req"] - prov_req_cnt = prov_auth_payload["cnt"] - prov_req_exp = datetime.fromtimestamp(prov_auth_payload["exp"]) - - # validate the OEM's provisioning request - prov_req_payload = crypto.jwt_payload(prov_req) - prod_id = prov_req_payload["prod_id"] - oem_pub_key = self.state["products"][prod_id]["oem_pub_key"] - if not crypto.validate_jwt(prov_req, oem_pub_key): - raise Exception("Invalid signature for provisioning request") - - # install the provisioning request for execution - prod = self.state["products"][prod_id] - prod["prov_req"] = prov_req - prod["prov_req_readable"] = crypto.readable_jwt(prov_req) - prod["prov_req_cnt"] = prov_req_cnt - prod["prov_req_exp"] = int(prov_req_exp.timestamp()) - - # create audit record - record = {} - record["type"] = types.DISTI_PROV_AUTH - record["iat"] = datetime.now().isoformat(' ') - record["prod_id"] = prod_id - record["prov_req"] = crypto.readable_jwt(prov_req) - self.append_audit_record(record) - - def create_provision_cmd(self, prod_id, dev_rsp, image_jwt_file): - """ - Creates and returns a provisioning command prov_cmd that can be send to a device. - prov_req= jwt( payload={ OEM_PROV_REQ , blob } , key=oem_priv_key ) - chain_of_trust= [ x509_certs ] - hsm_auth= jwt( payload={ CY_HSM_AUTH , hsm_pub_key , auth } , key=cy_priv_key ) - prov_cmd= jwt( payload={ HSM_PROV_CMD , prov_req , chain_of_trust , hsm_auth } , key=hsm_priv_key ) - Requires the device response to the RoT command (which contains the device identity and keys). - dev_rsp= jwt( payload= { DEV_ROT_RSP , prod_id,die_id,dev_id, dev_pub_key } , key=dev_priv_key ) - There must be an active provisioning request in the HSM for the given product ID. - """ - prod = self.state["products"][prod_id] - oem_pub_key = prod["oem_pub_key"] - signing_priv_key = prod["signing_priv_key"] - chain_of_trust = prod["chain_of_trust"] - prov_req = prod["prov_req"] - prov_req_cnt = prod["prov_req_cnt"] - prov_req_exp = datetime.fromtimestamp(prod["prov_req_exp"]) - hsm_priv_key = self.state["hsm_priv_key"] - cy_auth = self.state["cy_auth"] - image_cert = crypto.read_jwt(image_jwt_file) - - # validate the OEM's provisioning request - if prov_req_exp < datetime.now(): - raise Exception("Provisioning request expired") - if prov_req_cnt <= 0: - raise Exception("Provisioning request count exceeded") - prov_req_cnt -= 1; - - # validate the device response - dev_rsp_payload = crypto.jwt_payload(dev_rsp) - dev_pub_key = dev_rsp_payload["dev_pub_key"] - die_id = dev_rsp_payload["die_id"] - dev_id = dev_rsp_payload["dev_id"] - if dev_rsp_payload["prod_id"] != prod_id: - raise Exception("Product ID in provision request does not match device (" + prod_id + ")") - if not crypto.validate_jwt(dev_rsp, dev_pub_key): - raise Exception("Invalid signature on device response to RoT command") - - # create the device chain of trust (X509) - dev_cert = crypto.create_x509_cert(prod_id=prod_id, die_id=die_id, dev_id=dev_id, pub_key=dev_pub_key, - priv_key=signing_priv_key) - chain_of_trust = chain_of_trust + [dev_cert] - - # create the provisioning command - payload = {} - payload["type"] = types.HSM_PROV_CMD - payload["prov_req"] = prov_req - payload["image_cert"] = image_cert - payload["chain_of_trust"] = chain_of_trust - payload["cy_auth"] = cy_auth - prov_cmd = crypto.create_jwt(payload, hsm_priv_key) - - # create audit record - prov_cmd_readable = crypto.readable_jwt(prov_cmd) - prov_cmd_readable["payload"]["cy_auth"] = crypto.readable_jwt(prov_cmd_readable["payload"]["cy_auth"]) - prov_cmd_readable["payload"]["prov_req"] = crypto.readable_jwt(prov_cmd_readable["payload"]["prov_req"]) - prov_cmd_readable["payload"]["image_cert"] = crypto.readable_jwt(prov_cmd_readable["payload"]["image_cert"]) - record = {} - record["type"] = types.HSM_PROV_CMD - record["iat"] = datetime.now().isoformat(' ') - record["prod_id"] = prod_id - record["dev_rsp"] = crypto.readable_jwt(dev_rsp) - record["prov_cmd"] = prov_cmd_readable - self.append_audit_record(record) - - self.state["products"][prod_id]["prov_req_cnt"] = prov_req_cnt - return prov_cmd - - def pack_rot_command(self, prod_id, cy_auth_file, rot_auth): - payload = {} - - payload['type'] = types.HSM_ROT_CMD - payload['prod_id'] = prod_id - payload['cy_auth'] = crypto.read_jwt(cy_auth_file) - payload['rot_auth'] = rot_auth - - hsm_priv_key = self.state["hsm_priv_key"] - rot_cmd = crypto.create_jwt(payload, hsm_priv_key) - - return rot_cmd - - def pack_provision_cmd(self, **kwargs): - payload = {} - print(kwargs) - - if kwargs is not None: - for k, v in kwargs.items(): - if type(v) is tuple: - sequence = [] - for cert_file in v: - with open(cert_file) as cert: - sequence.append(cert.read()) - payload[k] = sequence - else: - if os.path.isfile(v): - payload[k] = crypto.read_jwt(v) - else: - payload[k] = v - - payload['type'] = types.HSM_PROV_CMD - - hsm_priv_key = self.state['hsm_priv_key'] - prov_cmd = crypto.create_jwt(payload, hsm_priv_key) - - return prov_cmd diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_oem.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_oem.py deleted file mode 100644 index ae418abda5b..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_oem.py +++ /dev/null @@ -1,143 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from cyprov_entity import Entity -from cyprov_crypto import crypto -from cyprov_types import types -from datetime import datetime -from datetime import timedelta - -# Oem (Customr) Entity -class OemEntity(Entity) : - def __init__( self , state_name , audit_name ) : - Entity.__init__(self,state_name,audit_name) - - def create_entity( self , chain_of_trust=[] ) : - """ - Creates the Oem entity. - Creates the Oem main key-pair and returns nothing. - """ - oem_priv_key,oem_pub_key= crypto.create_jwk() - self.state["oem_priv_key"]= oem_priv_key - self.state["oem_pub_key"]= oem_pub_key - self.state["oem_chain_of_trust"]= chain_of_trust - - def create_rot_authorization( self , signing_pkg ) : - """ - OEM creates a root-of-trust authorization package based on the signing key package from the HSM - It's a JWT with two main parts: - - a rot_auth authorization token that is sent to the device - - a chain of X509 certificates that establishses the OEM's trust in the HSM signing key - Note that this chain is not used inside the device and used only by 3rd parties - """ - oem_pub_key= self.state["oem_pub_key"] - oem_priv_key= self.state["oem_priv_key"] - oem_chain_of_trust= self.state["oem_chain_of_trust"] - - # get HSM public key and check CY authorization - signing_pkg_payload= crypto.jwt_payload(signing_pkg) - cy_auth= signing_pkg_payload["cy_auth"] - cy_auth_payload= crypto.jwt_payload(cy_auth) - cy_pub_key= cy_auth_payload["cy_pub_key"] - hsm_pub_key= cy_auth_payload["hsm_pub_key"] - if not crypto.validate_jwt( cy_auth , cy_pub_key ) : - raise Exception( "Invalid signature on Cypress HSM authorization in request" ) - if cy_auth_payload["type"] != types.CY_AUTH_HSM : - raise Exception( "Invalid type for Cypress HSM authorization in request" ) - if datetime.fromtimestamp(cy_auth_payload["exp"]) < datetime.now() : - raise Exception( "Cypress HSM authorization expired" ) - - # validate HSM request itself - signing_pub_key= signing_pkg_payload["signing_pub_key"] - prod_id= signing_pkg_payload["prod_id"] - if not crypto.validate_jwt( signing_pkg , hsm_pub_key ) : - raise Exception( "Invalid signature on HSM signing key package" ) - if signing_pkg_payload["type"] != types.HSM_SIGNING_KEY_PKG : - raise Exception( "Invalid type on HSM signing key package" ) - if datetime.fromtimestamp(signing_pkg_payload["exp"]) < datetime.now() : - raise Exception( "HSM signing key package expired" ) - - # create the RoT transfer authorization (that will go to the device) - payload= {} - payload["type"]= types.OEM_ROT_AUTH - payload["oem_pub_key"]= oem_pub_key - payload["hsm_pub_key"]= hsm_pub_key - payload["prod_id"]= prod_id - payload["iat"]= int(datetime.now().timestamp()) - rot_auth= crypto.create_jwt( payload , oem_priv_key ) - - # create the chain of trust - cert= crypto.create_x509_cert( signing_pub_key , oem_priv_key , prod_id ) - chain_of_trust= oem_chain_of_trust + [ cert ] - - # create the response - exp= datetime.now() + timedelta(7) - payload= {} - payload["type"]= types.OEM_ROT_AUTH_PKG - payload["iat"]= int(datetime.now().timestamp()) - payload["exp"]= int(exp.timestamp()) - payload["prod_id"]= prod_id - payload["rot_auth"]= rot_auth - payload["chain_of_trust"]= chain_of_trust - rot_auth_pkg= crypto.create_jwt( payload , oem_priv_key ) - - # create audit record - signing_pkg_readable= crypto.readable_jwt(signing_pkg) - signing_pkg_readable["payload"]["cy_auth"]= crypto.readable_jwt(signing_pkg_readable["payload"]["cy_auth"]) - signing_pkg_readable["payload"]["disti_auth"]= crypto.readable_jwt(signing_pkg_readable["payload"]["disti_auth"]) - rot_auth_pkg_readable= crypto.readable_jwt(rot_auth_pkg) - rot_auth_pkg_readable["payload"]["rot_auth"]= crypto.readable_jwt(rot_auth_pkg_readable["payload"]["rot_auth"]) - record= {} - record["type"]= types.OEM_ROT_AUTH_PKG - record["iat"]= datetime.now().isoformat(' ') - record["signing_pkg"]= signing_pkg_readable - record["rot_auth_pkg"]= rot_auth_pkg_readable - self.append_audit_record(record) - - return rot_auth_pkg - - def create_provision_request( self , blob ) : - """ - The OEM can create a request for provisioning by signing a keys & policies blob with its private key - Note that blob must contain at least the prod_id field - """ - # create the request - oem_priv_key= self.state["oem_priv_key"] - prov_req= crypto.create_jwt( blob , oem_priv_key ) - - # create audit record - record= {} - record["type"]= types.OEM_PROV_REQ - record["iat"]= datetime.now().isoformat(' ') - record["prod_id"]= blob["prod_id"] - record["prov_req"]= crypto.readable_jwt(prov_req) - self.append_audit_record(record) - - return prov_req - - def pack_rot_auth( self, prod_id, hsm_pub_key ): - oem_pub_key = self.state["oem_pub_key"] - oem_priv_key = self.state["oem_priv_key"] - - payload= {} - payload["type"] = types.OEM_ROT_AUTH - payload["oem_pub_key"] = oem_pub_key - payload["hsm_pub_key"] = hsm_pub_key - payload["prod_id"] = prod_id - payload["iat"] = int(datetime.now().timestamp()) - rot_auth = crypto.create_jwt( payload , oem_priv_key ) - - return rot_auth - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_pem.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_pem.py deleted file mode 100644 index 42f9bc4d967..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_pem.py +++ /dev/null @@ -1,79 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from jwcrypto import jwk -import json - -def pretty_search(dict_or_list, key_to_search, search_for_first_only=False): - """ - Give it a dict or a list of dicts and a dict key (to get values of), - it will search through it and all containing dicts and arrays - for all values of dict key you gave, and will return you set of them - unless you wont specify search_for_first_only=True - - :param dict_or_list: - :param key_to_search: - :param search_for_first_only: - :return: - """ - search_result = set() - if isinstance(dict_or_list, dict): - for key in dict_or_list: - key_value = dict_or_list[key] - if key == key_to_search: - if search_for_first_only: - return key_value - else: - search_result.add(key_value) - if isinstance(key_value, dict) or isinstance(key_value, list) or isinstance(key_value, set): - _search_result = pretty_search(key_value, key_to_search, search_for_first_only) - if _search_result and search_for_first_only: - return _search_result - elif _search_result: - for result in _search_result: - search_result.add(result) - elif isinstance(dict_or_list, list) or isinstance(dict_or_list, set): - for element in dict_or_list: - if isinstance(element, list) or isinstance(element, set) or isinstance(element, dict): - _search_result = pretty_search(element, key_to_search, search_result) - if _search_result and search_for_first_only: - return _search_result - elif _search_result: - for result in _search_result: - search_result.add(result) - return search_result if search_result else None - -class PemKey: - - def __init__(self, jwk_file = None, item = None): - if jwk_file != None: - with open(jwk_file) as f: - jwk_str = f.read() - self.jwk = json.loads(jwk_str) - - if item != None: - self.jwk = pretty_search(self.jwk, item, search_for_first_only=True) - - def save(self, file = None, private_key=False): - key = jwk.JWK(**self.jwk) - pem_str = key.export_to_pem(private_key, password=None) - if file != None: - with open(file, 'wb') as f: - f.write(pem_str) - else: - print(pem_str) - - def load(self, jwk): - self.jwk = jwk diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_types.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_types.py deleted file mode 100644 index f5aa542f0da..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_lib/cyprov_types.py +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -class types : - HSM_REQ_DISTI_AUTH= "HSM_REQ_DISTI_AUTH" - DISTI_AUTH_HSM= "DISTI_AUTH_HSM" - HSM_REQ_CY_AUTH= "HSM_REQ_CY_AUTH" - CY_AUTH_HSM= "CY_AUTH_HSM" - HSM_SIGNING_KEY_PKG= "HSM_SIGNING_KEY_PKG" - OEM_ROT_AUTH= "OEM_ROT_AUTH" - OEM_ROT_AUTH_PKG= "OEM_ROT_AUTH_PKG" - OEM_PROV_REQ= "OEM_PROV_REQ" - DISTI_PROV_AUTH= "DISTI_PROV_AUTH" - CY_DEV_ID= "CY_DEV_ID" - HSM_ROT_CMD= "HSM_ROT_CMD" - HSM_PROV_CMD= "HSM_PROV_CMD" - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_packet.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_packet.py deleted file mode 100644 index 75e98e29cf5..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/prepare/provisioning_packet.py +++ /dev/null @@ -1,133 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import os -import sys -import json -import click - -# Default input values and pathes -PROD_NAME = 'my_thing' -CYPROV_LIB_PATH = './provisioning_lib' - -# Default output values and pathes -OEM_AUDIT_NAME = 'oem_log.json' -HSM_AUDIT_NAME = 'hsm_log.json' -PROV_REQ_JWT_FILE = 'prov_req.jwt' -ROT_AUTH_JWT_FILE = 'rot_auth.jwt' -PROV_JWT_FILE = 'prov_cmd.jwt' - -CUSTOMER_KEY_N = 5 - -sys.path.insert(0, CYPROV_LIB_PATH) -from cyprov_hsm import HsmEntity -from cyprov_oem import OemEntity -from cyprov_customer import CustomerEntity -from cyprov_crypto import crypto - - -def process_customer_keys(paths): - customer_key_n = len(paths) - customer = [] - if customer_key_n > 0: - customer_key_id = 6 - for i in range(customer_key_n): - customer_log = os.path.basename(paths[i]) - customer_log = os.path.splitext(customer_log)[0] + '_log.json' - customer.append(CustomerEntity(paths[i], customer_log)) - if not customer[i].state_loaded: - customer[i].create_entity(customer_key_id + i) - customer[i].save_state() - return customer - - -@click.command() -@click.option('--oem', 'oem_state_path', - default='../prebuild/oem_state.json', - help='OEM key file.') -@click.option('--hsm', 'hsm_state_path', - default='../prebuild/hsm_state.json', - help='HSM key file.') -@click.option('--cyboot', 'image_cert', - default='../prebuild/CypressBootloader_CM0p.jwt', - help='Cypress Bootloader image certificate.') -@click.option('--cyauth', 'cy_auth_path', - default='../prebuild/cy_auth.jwt', - help='Provisioning authorization certificate.') -@click.option('--policy', 'policy_path', - default='policy_single_stage_CM4.json', - help='Policy file.') -@click.option('--out', 'output_path', - default='../packet', - help='Output directory.') -@click.option('--ckey', 'cust_key_path', - default=None, - multiple=True, - help='Customer key that will be used for image signing. Use the option multiple times ' - 'to specify multiple keys.') -@click.option('--devcert', 'dev_cert', - default=[], - multiple=True, - help='Chain of trust certificate. Use the option multiple times to specify multiple certificates.') -def main(oem_state_path, hsm_state_path, image_cert, cy_auth_path, - policy_path, output_path, cust_key_path, dev_cert): - - if len(cust_key_path) > CUSTOMER_KEY_N: - raise Exception('Maximum number of customer keys must be {}!'.format(CUSTOMER_KEY_N)) - - prod_id = PROD_NAME - - oem_audit_path = os.path.join(output_path, OEM_AUDIT_NAME) - hsm_audit_path = os.path.join(output_path, HSM_AUDIT_NAME) - prov_req_jwt_path = os.path.join(output_path, PROV_REQ_JWT_FILE) - rot_auth_jwt_path = os.path.join(output_path, ROT_AUTH_JWT_FILE) - prov_jwt_path = os.path.join(output_path, PROV_JWT_FILE) - - if not os.path.exists(output_path): - os.makedirs(output_path) - - oem = OemEntity(oem_state_path, oem_audit_path) - hsm = HsmEntity(hsm_state_path, hsm_audit_path) - - with open(policy_path) as f: - json_str = f.read() - blob = json.loads(json_str) - blob['prod_id'] = prod_id - - customer = process_customer_keys(cust_key_path) - if len(customer) > 0: - blob['custom_pub_key'] = [key.get_pub_key() for key in customer] - - prov_req = oem.create_provision_request(blob) - crypto.dump_jwt(prov_req, prov_req_jwt_path) - - rot_auth_pkg = oem.pack_rot_auth(prod_id, hsm.state["hsm_pub_key"]) - crypto.dump_jwt(rot_auth_pkg, rot_auth_jwt_path) - - prov_cmd = hsm.pack_provision_cmd( - cy_auth=cy_auth_path, - image_cert=image_cert, - prov_req=prov_req, - rot_auth=rot_auth_pkg, - chain_of_trust=dev_cert) - crypto.dump_jwt(prov_cmd, prov_jwt_path) - - print('#' * 80) - print('Provisioning packet is created') - print('#' * 80) - - -if __name__ == "__main__": - main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/provision_device_runner.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/provision_device_runner.py deleted file mode 100644 index 6b4c8282a29..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/provision_device_runner.py +++ /dev/null @@ -1,80 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import os -import sys -import click -from execute.helper import get_target_name -from execute.enums import DebugCore -from execute.provision_device import provision_execution -from execute.programmer.programmer import ProgrammingTool -from prepare.provisioning_lib.cyprov_pem import PemKey - - -TOOL_NAME = 'pyocd' # Programming/debugging tool used for communication with device -ACCESS_PORT = DebugCore.debug_sys_ap # Access port used for device provisioning - - -@click.command() -@click.option('--prov-jwt', 'prov_cmd_jwt', - default='packet/prov_cmd.jwt', - type=click.STRING, - help='Path to provisioning JWT file (packet which contains all data necessary ' - 'for provisioning, including policy, authorization packets and keys)') -@click.option('--hex', 'cy_bootloader_hex', - default='prebuild/CyBootloader_Release/CypressBootloader_CM0p.hex', - type=click.STRING, - help='Path to Cypress Bootloader HEX binary file') -@click.option('--pubkey-json', 'pub_key_json', - default='keys/dev_pub_key.json', - type=click.STRING, - help='File where to save public key in JSON format') -@click.option('--pubkey-pem', 'pub_key_pem', - default='keys/dev_pub_key.pem', - type=click.STRING, - help='File where to save public key in PEM format') -def main(prov_cmd_jwt, cy_bootloader_hex, pub_key_json, pub_key_pem): - """ - Parses command line arguments and provides high level support for - provisioning device with the specified programming tool. - :param prov_cmd_jwt: Path to provisioning JWT file (packet which contains - all data necessary for provisioning, including policy, authorization - packets and keys). - :param cy_bootloader_hex: Path to Cypress Bootloader program file. - :param pub_key_json: File where to save public key in JSON format. - :param pub_key_pem: File where to save public key in PEM format. - """ - # Verify arguments - target = get_target_name(TOOL_NAME, ACCESS_PORT) - if not target: - print('Invalid access port.') - sys.exit(1) - - test_status = False - tool = ProgrammingTool.create(TOOL_NAME) - if tool.connect(target): - test_status = provision_execution(tool, pub_key_json, prov_cmd_jwt, cy_bootloader_hex) - - if test_status: - # Read device response file and take device key from it - if os.path.exists(pub_key_json): - pem = PemKey(pub_key_json) - pem.save(pub_key_pem, private_key=False) - else: - sys.exit(1) - - -if __name__ == "__main__": - main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/requirements.txt b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/requirements.txt deleted file mode 100644 index c24d45be803..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/requirements.txt +++ /dev/null @@ -1,7 +0,0 @@ -# To install next python modules, please execute command: -# python -m pip install -r requirements.txt - -cryptography>=2.4.2 -Click>=7.0 -intelhex>=2.2.1 -jwcrypto>=0.6.0 \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_large.hex b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_large.hex deleted file mode 100644 index 3b8fa29b367..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_data/blinky_large.hex +++ /dev/null @@ -1,1410 +0,0 @@ -:020000041000EA -:20000000000100083101001000000000000000000000000000000000000000000000000095 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-:4005C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FB -:0200000490303A -:02000000FF3BC4 -:0200000490501A -:0C00000000000000000000000000FF3BBA -:00000001FF \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_pyocd_wrapper.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_pyocd_wrapper.py deleted file mode 100644 index a7365399832..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_pyocd_wrapper.py +++ /dev/null @@ -1,301 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import sys -import os.path -import time -import unittest -from intelhex import IntelHex -sys.path.append(os.path.dirname(os.path.realpath(__file__))) -sys.path.append(os.path.dirname('../execute')) -from test_utility import * -from execute.programmer.programmer import ProgrammingTool -from execute.programmer.exceptions import ExtendedTransferFaultError - -TOOL = 'pyocd' -TARGET = 'cy8c64xx_cm4' -PROBE_ID = '19071301d90e140c00d90e1400000000000000002e127069' # DAP-Link -#PROBE_ID = '1A06199701047400' # CMSIS-DAP - -# PSoC6 BLE Memory Regions -RAM_ADDR = 0x08000000 -MAIN_ADDR = 0x10000000 -WORK_ADDR = 0x14000000 -SFLASH_ADDR = 0x16000000 - -# PSoC6 Register Addresses -CYREG_IPC2_STRUCT_ACQUIRE = 0x40230040 -CYREG_IPC2_STRUCT_DATA = 0x4023004c -CYREG_IPC2_STRUCT_NOTIFY = 0x40230048 -CYREG_GPIO_PORT_11_OUT = 0x40320580 -CYREG_CM4_POWER_CTRL = 0x40210080 -ENTRANCE_EXAM_SRAM_ADDR = 0x0802E000 -# Debug halting control and status register -CYREG_DHCSR = 0xE000EDF0 -S_HALT = (1 << 17) -S_LOCKUP = (1 << 19) - - -class TestReadWrite(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.tool = ProgrammingTool.create(TOOL) - cls.tool.connect(TARGET, probe_id=PROBE_ID) - create_test_bin() - print('[INFO] Program Main region with test data') - cls.tool.program(TEST_BIN, address=MAIN_ADDR) - print('[INFO] Program Work region with test data') - cls.tool.program(TEST_BIN, address=WORK_ADDR) - - @classmethod - def tearDownClass(cls): - cls.tool.disconnect() - - def test_read8_ram(self): - data = self.tool.read8(RAM_ADDR) - self.assertGreaterEqual(data, 0) - - def test_read8_flash_main_region(self): - data = self.tool.read8(MAIN_ADDR) - self.assertEqual(data, 0x41) - - def test_read8_flash_work_region(self): - data = self.tool.read8(WORK_ADDR) - self.assertEqual(data, 0x41) - - def test_read8_sflash(self): - data = self.tool.read8(SFLASH_ADDR) - self.assertEqual(data, 0x00) - - def test_read8_register32_negative(self): - with self.assertRaises(ExtendedTransferFaultError) as context: - self.tool.read8(CYREG_IPC2_STRUCT_DATA) - self.assertTrue('If address points to a register it should be aligned with the register size' - in str(context.exception)) - - def test_read16_ram(self): - data = self.tool.read16(RAM_ADDR) - self.assertGreater(data, 0) - - def test_read16_flash_main_region(self): - data = self.tool.read16(MAIN_ADDR) - self.assertEqual(data, 0x3141) - - def test_read16_flash_work_region(self): - data = self.tool.read16(WORK_ADDR) - self.assertEqual(data, 0x3141) - - def test_read16_register32_negative(self): - with self.assertRaises(ExtendedTransferFaultError) as context: - self.tool.read16(CYREG_IPC2_STRUCT_DATA) - self.assertTrue('If address points to a register it should be aligned with the register size' - in str(context.exception)) - - def test_read32_ram(self): - data = self.tool.read32(RAM_ADDR) - self.assertGreater(data, 0x00) - - def test_read32_flash_main_region(self): - data = self.tool.read32(MAIN_ADDR) - self.assertEqual(data, 0x32413141) - - def test_read32_not_exists_flash_region(self): - with self.assertRaises(ExtendedTransferFaultError): - self.tool.read32(0xFF00FF00) - - def test_read32_flash_work_region(self): - data = self.tool.read32(WORK_ADDR) - self.assertEqual(data, 0x32413141) - - def test_read32_register32(self): - data = self.tool.read32(CYREG_IPC2_STRUCT_DATA) - self.assertGreaterEqual(data, 0x00000000) - - def test_write8_ram(self): - self.tool.write8(RAM_ADDR, 0xCE) - data = self.tool.read8(RAM_ADDR) - self.assertEqual(0xCE, data) - - def test_write16_ram(self): - self.tool.write16(RAM_ADDR, 0xAC21) - data = self.tool.read16(RAM_ADDR) - self.assertEqual(0xAC21, data) - - def test_write32_ram(self): - self.tool.write32(RAM_ADDR, 0xDEADBEAF) - data = self.tool.read32(RAM_ADDR) - self.assertEqual(data, 0xDEADBEAF) - - def test_write32_CYREG_IPC2_STRUCT_ACQUIRE(self): - self.tool.write32(CYREG_IPC2_STRUCT_ACQUIRE, 0x80000000) - data = self.tool.read32(CYREG_IPC2_STRUCT_ACQUIRE) - byte = decomposite32(data)[3] - self.assertEqual(byte, 0x80) - - def test_write32_CYREG_IPC2_STRUCT_DATA(self): - self.tool.write32(CYREG_IPC2_STRUCT_DATA, 0xAFECAB91) - data = self.tool.read32(CYREG_IPC2_STRUCT_DATA) - self.assertEqual(data, 0xAFECAB91) - - def test_write32_CYREG_IPC2_STRUCT_NOTIFY(self): - self.tool.write32(CYREG_IPC2_STRUCT_NOTIFY, 0x00000001) - data = self.tool.read32(CYREG_IPC2_STRUCT_NOTIFY) - byte = decomposite32(data)[3] - self.assertEqual(byte, 0x00) - - def test_write32_ENTRANCE_EXAM_SRAM_ADDR(self): - self.tool.write32(ENTRANCE_EXAM_SRAM_ADDR, 0xD1A2B3C4) - data = self.tool.read32(ENTRANCE_EXAM_SRAM_ADDR) - self.assertEqual(data, 0xD1A2B3C4) - - def test_write32_ENTRANCE_EXAM_SRAM_ADDR_offset4(self): - self.tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x04, 0xABCABCFA) - data = self.tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x04) - self.assertEqual(data, 0xABCABCFA) - - def test_write32_ENTRANCE_EXAM_SRAM_ADDR_offset8(self): - self.tool.write32(ENTRANCE_EXAM_SRAM_ADDR + 0x08, 0x12890735) - data = self.tool.read32(ENTRANCE_EXAM_SRAM_ADDR + 0x08) - self.assertEqual(data, 0x12890735) - - def tet_read_write_core_regs(self): - value1 = self.tool.read_reg('r1') - self.tool.write_reg('r1', value1 + 10) - value2 = self.tool.read_reg('r1') - self.assertEqual(value1 + 10, value2) - - def test_read_strange_reg_negative(self): - with self.assertRaises(ValueError): - self.tool.read_reg('r200') - - -class TestProgramming(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.tool = ProgrammingTool.create(TOOL) - cls.tool.connect(TARGET, probe_id=PROBE_ID) - create_test_bin() - - @classmethod - def tearDownClass(cls): - cls.tool.disconnect() - - def test_erase(self): - self.tool.erase(MAIN_ADDR, 0x200) - match = False - i = 0 - while i < os.path.getsize(TEST_BIN): - data = self.tool.read8(MAIN_ADDR + i) - match = data == 0x00 - if not match: - break - i += 1 - self.assertTrue(match) - - def test_program_bin(self): - self.tool.erase(MAIN_ADDR, 0x200) - self.tool.program(TEST_BIN, address=MAIN_ADDR) - with open(TEST_BIN, 'rb') as file_obj: - exp_data = file_obj.read() - match = False - i = 0 - while i < len(exp_data): - data = self.tool.read8(MAIN_ADDR + i) - match = data == exp_data[i] - if not match: - break - i += 1 - self.assertTrue(match) - - def test_program_hex(self): - intel_hex = IntelHex() - intel_hex.loadhex(BLINKY_SMALL_HEX) - arr = intel_hex.gets(MAIN_ADDR, 0x400) - self.tool.erase(MAIN_ADDR, 0x400) - self.tool.program(BLINKY_SMALL_HEX) - match = False - i = 0 - while i < len(arr): - data = self.tool.read8(MAIN_ADDR + i) - match = data == arr[i] - if not match: - break - i += 1 - self.assertTrue(match) - - -class TestControlAPIs(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.tool = ProgrammingTool.create(TOOL) - cls.tool.connect(TARGET, probe_id=PROBE_ID) - - @classmethod - def tearDownClass(cls): - cls.tool.disconnect() - - def test_reset(self): - self.tool.write32(CYREG_GPIO_PORT_11_OUT, 0xDEADBEAF) - self.tool.reset() - self.assertEqual(self.tool.read32(CYREG_GPIO_PORT_11_OUT), 0x00) - - def test_halt_resume(self): - self.tool.reset() - if self.tool.read32(CYREG_CM4_POWER_CTRL) & 3 != 3: - self.tool.write32(CYREG_CM4_POWER_CTRL, 0x05fa0003) # CM4 is sleeping, trying to wake it up - dhcsr = self.tool.read32(CYREG_DHCSR) - if dhcsr & S_LOCKUP: - self.tool.halt() - dhcsr = self.tool.read32(CYREG_DHCSR) - self.tool.write_reg('xpsr', 0x01000000) # set thumb bit - else: - self.tool.halt() - dhcsr = self.tool.read32(CYREG_DHCSR) - self.assertTrue(dhcsr & S_HALT) - self.tool.resume() - dhcsr = self.tool.read32(CYREG_DHCSR) - self.assertFalse(dhcsr & S_HALT) - - #def test_reset_and_halt(self): - # self.tool.write32(CYREG_GPIO_PORT_11_OUT, 0xDEADBEAF) - # self.tool.reset_and_halt() - # self.assertEqual(self.tool.read32(CYREG_GPIO_PORT_11_OUT), 0x00) - # dhcsr = self.tool.read32(CYREG_DHCSR) - # self.assertTrue(dhcsr & S_HALT) - - @unittest.skip("HW frequency cannot be changed.") - def test_set_frequency(self): - self.tool.erase(MAIN_ADDR, 0xC000) - self.tool.set_frequency(100) - time_before_program = time.time() - self.tool.program(BLINKY_LARGE_HEX) - time1 = time.time() - time_before_program - self.tool.set_frequency(1200) - self.tool.erase(MAIN_ADDR, 0xC000) - time_before_program = time.time() - self.tool.program(BLINKY_LARGE_HEX) - time2 = time.time() - time_before_program - self.assertGreater(time1, time2) - - def test_connection(self): - self.tool.disconnect() - self.assertFalse(self.tool.session.is_open) - self.tool.connect(TARGET, probe_id=PROBE_ID) - self.assertTrue(self.tool.session.is_open) - - -if __name__ == '__main__': - ret = not unittest.main().wasSuccessful() - sys.exit(ret) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_utility.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_utility.py deleted file mode 100644 index ab890078539..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/test/test_utility.py +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -TEST_BIN = "test_data/test.bin" -BLINKY_SMALL_HEX = "test_data/blinky_small.hex" -BLINKY_LARGE_HEX = "test_data/blinky_large.hex" - - -def create_test_bin(): - with open(TEST_BIN, 'wb') as file: - file.write(b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' - b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' - b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' - b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' - b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' - b'A1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FFA1A2A3B1B2B3111213FF' - b'A1A2A3B1B2B3111213FFA1A2A3B1B2B') - - -def decomposite32(value): - """ - Decomposites 32-bit value into byte array. - :param value: 32-bit value. - :return: Array of bytes. - """ - byte = value.to_bytes(4, 'little') - return byte diff --git a/tools/targets/PSOC6.py b/tools/targets/PSOC6.py index 7ad96564f29..fbe72bcde1d 100644 --- a/tools/targets/PSOC6.py +++ b/tools/targets/PSOC6.py @@ -55,6 +55,10 @@ NSPE_IMAGE_ID = 16 SMIF_MEM_MAP_START = 0x18000000 +class AddSignatureError(Exception): + """ A simple class that represents all the exceptions associated with + adding signature to Secure Boot image + """ # Patch Cypress hex file: # - update checksum @@ -150,6 +154,17 @@ def find_cm0_image(toolchain, resources, elf, hexf, hex_filename): # check if policy parameters are consistent def check_slots_integrity(toolchain, fw_cyb, target_data, fw_spe=None, fw_nspe=None): + """ + Function checks consistency of parameters presented in + policy file used for build of Secure Boot enabled target. + :param toolchain: Toolchain object of current build session + :param fw_cyb: CyBootloader firmware description from policy + :param target_data: Object contains description of + processing target from target.json + :param fw_spe: CM0p firmware descpription object from policy + :param fw_nspe: CM4 firmware descpription object from policy + :return: List of slots and image id corresponding to them + """ slot0 = None slot1 = None @@ -171,24 +186,23 @@ def check_slots_integrity(toolchain, fw_cyb, target_data, fw_spe=None, fw_nspe=N if slot["type"] == "BOOT": slot0 = slot - if fw_nspe["upgrade"] and True: + if fw_nspe["upgrade"] is True: slot1 = slot if slot["type"] == "UPGRADE": - try: - if fw_nspe["encrypt"] and True: - # mark slot1 image as one, that should be encrypted - slot1.update({'encrypt': True}) - toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE NSPE will" - " be ENCRYPTED per policy settings.") - except KeyError: - None + if fw_nspe.get("encrypt") is True: + # mark slot1 image as one, that should be encrypted + slot1.update({'encrypt': True}) + toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE NSPE will" + " be ENCRYPTED per policy settings.") + else: + pass else: toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE will not" " be built per policy settings.") break if slot0 is None: toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT section not found in policy resources") - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") else: # check if PSA targets flash map correspond to slots addresses and sizes in policy @@ -219,40 +233,38 @@ def check_slots_integrity(toolchain, fw_cyb, target_data, fw_spe=None, fw_nspe=N if img_id != 1: toolchain.notify.debug("[PSOC6.sign_image] ERROR: Image ID of SPE image" " is not equal to 1!") - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") if not (fw_cyb["launch"] == img_id): toolchain.notify.debug("[PSOC6.sign_image] ERROR: ID of build image" " does not correspond launch ID in CyBootloader!") - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") if not (fw_spe["launch"] == fw_nspe["id"]): toolchain.notify.debug("[PSOC6.sign_image] ERROR: ID of NSPE image" " does not correspond launch ID in SPE part!") - raise Exception("imgtool finished execution with errors!") - + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") # check slots addresses and sizes if upgrade is set to True for slot in fw_spe["resources"]: if slot["type"] == "BOOT": slot0 = slot - if fw_spe["upgrade"] and True: + if fw_spe["upgrade"] is True: if slot["type"] == "UPGRADE": slot1 = slot - try: - if fw_spe["encrypt"] and True: - # mark slot1 image as one, that should be encrypted - slot1.update({'encrypt': True}) - toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE SPE will" - " be ENCRYPTED per policy settings.") - except KeyError: - None + if fw_spe.get("encrypt") is True: + # mark slot1 image as one, that should be encrypted + slot1.update({'encrypt': True}) + toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE SPE will" + " be ENCRYPTED per policy settings.") + else: + pass else: toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE will not" - " be produced per policy settings.") + " be produced per policy settings.") if slot0 is None: toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT section not found in policy resources") - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") if slot1 is not None: # bigger or equal to 0x18000000 in hex is a start of SMIF memory @@ -262,14 +274,18 @@ def check_slots_integrity(toolchain, fw_cyb, target_data, fw_spe=None, fw_nspe=N if slot0["size"] != slot1["size"]: toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT and UPGRADE slots sizes are not equal") - return [slot0, slot1, img_id] + return (slot0, slot1, img_id) else: - return [slot0, None, img_id] + return (slot0, None, img_id) -# Resolve Secure Boot policy sections considering target def process_target(toolchain, target): - + """ + Gathers and process information about target being built + :param toolchain: Toolchain object of current build session + :param target: Name of target being built + :return: List with all data needed for adding signature + """ targets_json = Path("targets/targets.json") cy_targets = Path("targets/TARGET_Cypress/TARGET_PSOC6/") sb_params_file_name = Path("secure_image_parameters.json") @@ -283,7 +299,7 @@ def process_target(toolchain, target): root_dir = root_dir / 'mbed-os' if not os.path.isfile(str(mbed_os_targets)): toolchain.notify.debug("[PSOC6.sign_image] ERROR: targets.json not found!") - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") with open(str(mbed_os_targets)) as j: json_str = j.read() @@ -300,7 +316,7 @@ def process_target(toolchain, target): f.close() else: toolchain.notify.debug("[PSOC6.sign_image] ERROR: secure_image_parametest.json not found!") - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") sdk_path = root_dir / sb_config["sdk_path"] @@ -308,7 +324,7 @@ def process_target(toolchain, target): if not os.path.isfile(str(priv_key_path)): toolchain.notify.debug("[PSOC6.sign_image] ERROR: Private key file not found in " + str(priv_key_path)) - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") if "_PSA" in target: # assume dual stage bootloading scheme @@ -347,35 +363,38 @@ def process_target(toolchain, target): target_sig_data = [{"img_data": sb_config["boot0"], "slot_data": slots[0], "key_file": sb_config["priv_key_file"], "sdk_path": sdk_path, "id": slots[2]}] - - if slots[1] is not None: + + if slots[1] is not None: target_sig_data.append({"img_data": sb_config["boot1"], "slot_data": slots[1], "key_file": sb_config["priv_key_file"], "sdk_path": sdk_path, "id": slots[2]}) # check if slot1 image sould be encrypted - try: - if slots[1]["encrypt"] is True: - - dev_pub_key = sdk_path / Path(sb_config["dev_pub_key_file"]) - if not os.path.isfile(str(dev_pub_key)): - toolchain.notify.debug("[PSOC6.sign_image] ERROR: Device public key file not found in " + str(dev_pub_key)) - raise Exception("imgtool finished execution with errors!") - - aes_key_file = sdk_path / Path(sb_config["aes_key_file"]) - if not os.path.isfile(str(aes_key_file)): - toolchain.notify.debug("[PSOC6.sign_image] ERROR: AES-128 key file not found in " + str(aes_key_file)) - raise Exception("imgtool finished execution with errors!") - - target_sig_data[1].update({"aes_key": sb_config["aes_key_file"], "dev_pub_key": sb_config["dev_pub_key_file"]}) - - except KeyError: + if slots[1].get("encrypt") is True: + + dev_pub_key = sdk_path / Path(sb_config["dev_pub_key_file"]) + if not os.path.isfile(str(dev_pub_key)): + toolchain.notify.debug("[PSOC6.sign_image] ERROR: Device public key file not found in " + str(dev_pub_key)) + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") + + aes_key_file = sdk_path / Path(sb_config["aes_key_file"]) + if not os.path.isfile(str(aes_key_file)): + toolchain.notify.debug("[PSOC6.sign_image] ERROR: AES-128 key file not found in " + str(aes_key_file)) + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") + + target_sig_data[1].update({"aes_key": sb_config["aes_key_file"], "dev_pub_key": sb_config["dev_pub_key_file"]}) + + else: toolchain.notify.info("[PSOC6.sign_image] INFO: Image for slot UPGRADE would not be encrypted per policy settings") return target_sig_data -# Sign binary image using imgtool -def sign_image(toolchain, elf0, binf, hexf1=None): - +def sign_image(toolchain, binf): + """ + Adds signature to a binary file being built, + prepares some intermediate binary artifacts. + :param toolchain: Toolchain object of current build session + :param binf: Binary file created for target + """ target_sig_data = None # reserve name for separate NSPE image out_cm4_hex = binf[:-4] + "_cm4.hex" @@ -391,41 +410,40 @@ def sign_image(toolchain, elf0, binf, hexf1=None): if target_sig_data is None: toolchain.notify.debug("[PSOC6.sign_image] ERROR: Target not found!") - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") for slot in target_sig_data: # first check if image for slot under processing should be encrypted - try: - if slot["slot_data"]["encrypt"] is True: - # call encrypt_img to perform encryption - args = [sys.executable, str(slot["sdk_path"] / "encrypted_image_runner.py"), - "--sdk-path", str(slot["sdk_path"]), "--hex-file", os.getcwd() + '/' + mbed_hex, - "--key-priv", str(slot["sdk_path"] / slot["key_file"]), - "--key-pub", str(slot["sdk_path"] / slot["dev_pub_key"]), - "--key-aes", str(slot["sdk_path"] / slot["aes_key"]), - "--ver", str(slot["img_data"]["VERSION"]), "--img-id", str(slot["id"]), - "--rlb-count", str(slot["img_data"]["ROLLBACK_COUNTER"]), - "--slot-size", str(hex(slot["slot_data"]["size"])), - "--img-offset", str(slot["slot_data"]["address"])] - if slot["slot_data"]["type"] != "BOOT": - args.append("--pad") - process = subprocess.Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE) - - # catch standard process pipes outputs - stderr = process.communicate()[1] - stdout = process.communicate()[0] - rc = process.wait() - print(stdout.decode("utf-8")) - - if rc != 0: - toolchain.notify.debug("[PSOC6.sign_image] ERROR: Encryption script ended with error!") - toolchain.notify.debug("[PSOC6.sign_image] Message from encryption script: " + stderr.decode("utf-8")) - raise Exception("imgtool finished execution with errors!") - else: - toolchain.notify.info("[PSOC6.sign_image] SUCCESS: Image for slot " + - slot["slot_data"]["type"] + " is signed and encrypted with no errors!") + if slot["slot_data"].get("encrypt") is True: + # call encrypt_img to perform encryption + args = [sys.executable, str(slot["sdk_path"] / "encrypted_image_runner.py"), + "--sdk-path", str(slot["sdk_path"]), "--hex-file", os.getcwd() + '/' + mbed_hex, + "--key-priv", str(slot["sdk_path"] / slot["key_file"]), + "--key-pub", str(slot["sdk_path"] / slot["dev_pub_key"]), + "--key-aes", str(slot["sdk_path"] / slot["aes_key"]), + "--ver", str(slot["img_data"]["VERSION"]), "--img-id", str(slot["id"]), + "--rlb-count", str(slot["img_data"]["ROLLBACK_COUNTER"]), + "--slot-size", str(hex(slot["slot_data"]["size"])), + "--img-offset", str(slot["slot_data"]["address"])] + if slot["slot_data"]["type"] != "BOOT": + args.append("--pad") + process = subprocess.Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + + # catch standard process pipes outputs + stderr = process.communicate()[1] + stdout = process.communicate()[0] + rc = process.wait() + toolchain.notify.info(stdout.decode("utf-8")) + + if rc != 0: + toolchain.notify.debug("[PSOC6.sign_image] ERROR: Encryption script ended with error!") + toolchain.notify.debug("[PSOC6.sign_image] Message from encryption script: " + stderr.decode("utf-8")) + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") + else: + toolchain.notify.info("[PSOC6.sign_image] SUCCESS: Image for slot " + + slot["slot_data"]["type"] + " is signed and encrypted with no errors!") # all non ecrypted images take this path - except KeyError: + else: if slot["slot_data"]["type"] == "UPGRADE": out_hex_name = binf[:-4] + "_upgrade.hex" out_bin_name = out_hex_name[:-4] + "_signed.bin" @@ -452,7 +470,7 @@ def sign_image(toolchain, elf0, binf, hexf1=None): if rc != 0: toolchain.notify.debug("[PSOC6.sign_image] ERROR: Signature is not added!") toolchain.notify.debug("[PSOC6.sign_image] Message from imgtool: " + stderr.decode("utf-8")) - raise Exception("imgtool finished execution with errors!") + raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") else: toolchain.notify.info("[PSOC6.sign_image] SUCCESS: Image for slot " + slot["slot_data"]["type"] + " is signed with no errors!") @@ -467,7 +485,11 @@ def sign_image(toolchain, elf0, binf, hexf1=None): # produce hex file for slot1 if slot["slot_data"]["type"] == "UPGRADE": bin2hex(out_bin_name, out_hex_name, offset=int(slot["slot_data"]["address"])) - print("Image UPGRADE: " + out_hex_name + "\n") + toolchain.notify.info("Image UPGRADE: " + out_hex_name + "\n") + def complete(toolchain, elf0, hexf0, hexf1=None): + """ + Merge CM4 and CM0 images to a single binary + """ complete_func(toolchain.notify.debug, elf0, hexf0, hexf1) diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index 566c85c7d84..743bff1049b 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -677,15 +677,11 @@ def complete(t_self, resources, elf, binf): @staticmethod def sign_image(t_self, resources, elf, binf): + """ + Calls sign_image function to add signature to Secure Boot binary file. + """ from tools.targets.PSOC6 import sign_image as psoc6_sign_image - if hasattr(t_self.target, "hex_filename"): - hex_filename = t_self.target.hex_filename - # Completing main image involves merging M0 image. - from tools.targets.PSOC6 import find_cm0_image - m0hexf = find_cm0_image(t_self, resources, elf, binf, hex_filename) - psoc6_sign_image(t_self, elf, binf, m0hexf) - else: - psoc6_sign_image(t_self, elf, binf) + psoc6_sign_image(t_self, binf) class ArmMuscaA1Code: """Musca-A1 Hooks""" From d289b967f79408e04696e8b65a9d26d18a8a767e Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Wed, 28 Aug 2019 01:07:30 +0300 Subject: [PATCH 13/16] Added check for python version before calling post build action. Fixed compilation for Python 2.7. --- tools/targets/__init__.py | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index 743bff1049b..c270f935875 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -679,9 +679,20 @@ def complete(t_self, resources, elf, binf): def sign_image(t_self, resources, elf, binf): """ Calls sign_image function to add signature to Secure Boot binary file. - """ - from tools.targets.PSOC6 import sign_image as psoc6_sign_image - psoc6_sign_image(t_self, binf) + """ + version = sys.version_info + + # check python version before calling post build as is supports only python3+ + if((version[0] < 3) is True): + t_self.notify.info("[PSOC6.sing_image] Be careful - produced HEX file was not signed and thus " + "is not compatible with Cypress Secure Boot target. " + "You are using Python " + str(sys.version[:5]) + + " which is not supported by CySecureTools. " + "Consider installing Python 3.7+ and rebuild target. " + "For more information refver to User Guide https://www.cypress.com/secureboot-sdk-user-guide") + else: + from tools.targets.PSOC6 import sign_image as psoc6_sign_image + psoc6_sign_image(t_self, binf) class ArmMuscaA1Code: """Musca-A1 Hooks""" From bfe1d04ba2e4bd96a5aa9ac70ebd315f884f811a Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Thu, 29 Aug 2019 12:45:38 +0300 Subject: [PATCH 14/16] Removed import of version specific python modules, improved imports organization in PSOC6.py, fixed per PR comments --- requirements.txt | 1 - tools/targets/PSOC6.py | 16 +++++++--------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/requirements.txt b/requirements.txt index 40b86802c0f..bcfb24342a6 100644 --- a/requirements.txt +++ b/requirements.txt @@ -28,4 +28,3 @@ wmi==1.4.9;platform_system=='Windows' psutil==5.6.2 cryptography>=2.4.x,<2.5 Click>=7.0,<7.1 -pathlib>=1.0.1 diff --git a/tools/targets/PSOC6.py b/tools/targets/PSOC6.py index fbe72bcde1d..8d2a4a72b23 100644 --- a/tools/targets/PSOC6.py +++ b/tools/targets/PSOC6.py @@ -17,21 +17,15 @@ import os import sys - -import platform import subprocess -import errno from array import array from struct import (pack, unpack) from shutil import copy2 +import json from intelhex import IntelHex, hex2bin, bin2hex -from intelhex.compat import asbytes from ..config import ConfigException -from pathlib import Path, PurePath -import json - # The size of the program data in Cypress HEX files is limited to 0x80000000 # Higher addresses contain additional metadata (chip protection, eFuse data, etc..) CY_PROGRAM_SIZE = 0x80000000 @@ -286,6 +280,8 @@ def process_target(toolchain, target): :param target: Name of target being built :return: List with all data needed for adding signature """ + from pathlib import Path + targets_json = Path("targets/targets.json") cy_targets = Path("targets/TARGET_Cypress/TARGET_PSOC6/") sb_params_file_name = Path("secure_image_parameters.json") @@ -395,6 +391,8 @@ def sign_image(toolchain, binf): :param toolchain: Toolchain object of current build session :param binf: Binary file created for target """ + from pathlib import PurePath + target_sig_data = None # reserve name for separate NSPE image out_cm4_hex = binf[:-4] + "_cm4.hex" @@ -446,10 +444,10 @@ def sign_image(toolchain, binf): else: if slot["slot_data"]["type"] == "UPGRADE": out_hex_name = binf[:-4] + "_upgrade.hex" - out_bin_name = out_hex_name[:-4] + "_signed.bin" else: out_hex_name = binf - out_bin_name = out_hex_name[:-4] + "_signed.bin" + + out_bin_name = out_hex_name[:-4] + "_signed.bin" # call imgtool for signature args = [sys.executable, str(slot["sdk_path"] / "imgtool/imgtool.py"), From c249bf97c2e5e492c717fd0aaaeda2d1e6f9cf0f Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Thu, 29 Aug 2019 22:23:16 +0300 Subject: [PATCH 15/16] Updated target files structure to align with the following BSP PR. --- .../GeneratedSource/cycfg.c | 0 .../GeneratedSource/cycfg.h | 0 .../GeneratedSource/cycfg.timestamp | 24 ++ .../GeneratedSource/cycfg_clocks.c | 0 .../GeneratedSource/cycfg_clocks.h | 0 .../GeneratedSource/cycfg_notices.h | 0 .../GeneratedSource/cycfg_peripherals.c | 0 .../GeneratedSource/cycfg_peripherals.h | 0 .../GeneratedSource/cycfg_pins.c | 0 .../GeneratedSource/cycfg_pins.h | 0 .../GeneratedSource/cycfg_qspi_memslot.c | 56 +-- .../GeneratedSource/cycfg_qspi_memslot.h | 32 +- .../GeneratedSource/cycfg_routing.c | 0 .../GeneratedSource/cycfg_routing.h | 0 .../GeneratedSource/cycfg_system.c | 29 ++ .../GeneratedSource/cycfg_system.h | 3 + .../GeneratedSource/qspi_config.cfg | 4 + .../design.modus | 22 +- .../TARGET_CY8CPROTO_064_SB/PeripheralNames.h | 3 +- .../TARGET_CY8CPROTO_064_SB/PeripheralPins.c | 361 +++++++++--------- .../TARGET_CY8CPROTO_064_SB/PinNames.h | 55 +-- .../{cybsp_cy8cproto_064_sb.c => cybsp.c} | 30 +- .../TARGET_CY8CPROTO_064_SB/cybsp.h | 36 ++ .../cybsp_cy8cproto_064_sb.h | 74 ---- .../TARGET_CY8CPROTO_064_SB/cybsp_types.h | 18 +- .../cycfg_qspi_memslot.cyqspi | 63 --- .../TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 0 .../TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S | 0 .../TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_01_cm4.S | 0 .../system_psoc6_cm4.c | 0 .../psoc6_static_srm.h | 85 ----- tools/targets/__init__.py | 2 +- 35 files changed, 378 insertions(+), 519 deletions(-) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg.h (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_clocks.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_clocks.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_notices.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_peripherals.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_peripherals.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_pins.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_pins.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_qspi_memslot.c (83%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_qspi_memslot.h (57%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_routing.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_routing.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_system.c (93%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/GeneratedSource/cycfg_system.h (96%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{ => COMPONENT_BSP_DESIGN_MODUS}/design.modus (97%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/{cybsp_cy8cproto_064_sb.c => cybsp.c} (67%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cycfg_qspi_memslot.cyqspi rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/{TARGET_MCU_PSOC6_M4 => }/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/{TARGET_MCU_PSOC6_M4 => }/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/{TARGET_MCU_PSOC6_M4 => }/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/{TARGET_MCU_PSOC6_M4 => }/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/{TARGET_MCU_PSOC6_M4 => }/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/{TARGET_MCU_PSOC6_M4 => }/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/{TARGET_MCU_PSOC6_M4 => }/system_psoc6_cm4.c (100%) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/psoc6_static_srm.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp new file mode 100644 index 00000000000..6911b5befd4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -0,0 +1,24 @@ +/******************************************************************************* +* File Name: cycfg.timestamp +* +* Description: +* Sentinel file for determining if generated source is up to date. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_clocks.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_notices.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_peripherals.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_pins.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c similarity index 83% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index d430d4908fd..b10821c9769 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -24,7 +24,7 @@ #include "cycfg_qspi_memslot.h" -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xEBU, @@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -78,7 +78,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x20U, @@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -114,7 +114,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x38U, @@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x03U, /* The size of the memory. */ .memSize = 0x1000000U, /* Specifies the Read command. */ - .readCmd = &S25FL128S_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = &S25FL128S_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = &S25FL128S_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = &S25FL128S_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ .eraseSize = 0x0001000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = &S25FL128S_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = &S25FL128S_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ .programSize = 0x0000200U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = &S25FL128S_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = &S25FL128S_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = &S25FL128S_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ .stsRegQuadEnableMask = 0x02U, /* The max time for the erase type-1 cycle-time in ms. */ - .eraseTime = 140U, + .eraseTime = 650U, /* The max time for the chip-erase cycle-time in ms. */ - .chipEraseTime = 40000U, + .chipEraseTime = 165000U, /* The max time for the page-program cycle-time in us. */ - .programTime = 250U + .programTime = 750U }; -cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, /* Flags. */ - .flags = CY_SMIF_FLAG_WR_EN, + .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN, /* The data-line selection options for a slave device. */ .dataSelect = CY_SMIF_DATA_SEL0, /* The base address the memory slave is mapped to in the PSoC memory map. @@ -239,19 +239,19 @@ cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 = .baseAddress = 0x18000000U, /* The size allocated in the PSoC memory map, for the memory slave device. The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ - .memMappedSize = 0x10000U, + .memMappedSize = 0x1000000U, /* If this memory device is one of the devices in the dual quad SPI configuration. Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = &deviceCfg_S25FL128S_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL128S_SlaveSlot_0 }; -cy_stc_smif_mem_config_t* smifMemConfigs[] = { +const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { &S25FL128S_SlaveSlot_0 }; -cy_stc_smif_block_config_t smifBlockConfig = +const cy_stc_smif_block_config_t smifBlockConfig = { /* The number of SMIF memories defined. */ .memCount = CY_SMIF_DEVICE_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h similarity index 57% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 116f1e52042..5e541bb902c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -28,22 +28,22 @@ #define CY_SMIF_DEVICE_NUM 1 -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd; -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd; -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd; -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd; -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd; -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd; -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd; -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd; -extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd; - -extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0; - -extern cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0; -extern cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM]; - -extern cy_stc_smif_block_config_t smifBlockConfig; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; + +extern const cy_stc_smif_block_config_t smifBlockConfig; #endif /*CY_SMIF_MEMCONFIG_H*/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_routing.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 42eb4f6cba9..b6c01928d46 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -38,6 +38,9 @@ #define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 #define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL #define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 #define CY_CFG_SYSCLK_ILO_ENABLED 1 #define CY_CFG_SYSCLK_IMO_ENABLED 1 #define CY_CFG_SYSCLK_CLKLF_ENABLED 1 @@ -52,6 +55,7 @@ #define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 #define CY_CFG_SYSCLK_WCO_ENABLED 1 #define CY_CFG_PWR_ENABLED 1 @@ -74,6 +78,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, .cco_Freq = 355U, }; +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +{ + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; __WEAK void cycfg_ClockStartupError(uint32_t error) { @@ -110,6 +122,12 @@ __STATIC_INLINE void Cy_SysClk_ClkHf2Init() Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); } +__STATIC_INLINE void Cy_SysClk_ClkHf3Init() +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); +} __STATIC_INLINE void Cy_SysClk_IloInit() { /* The WDT is unlocked in the default startup code */ @@ -145,6 +163,17 @@ __STATIC_INLINE void Cy_SysClk_ClkPeriInit() { Cy_SysClk_ClkPeriSetDivider(1U); } +__STATIC_INLINE void Cy_SysClk_Pll0Init() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} __STATIC_INLINE void Cy_SysClk_ClkSlowInit() { Cy_SysClk_ClkSlowSetDivider(0U); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index cc47de73c76..4bdd873358f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -43,6 +43,8 @@ extern "C" { #define CY_CFG_SYSCLK_CLKHF0 0UL #define srss_0_clock_0_hfclk_2_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF2 2UL +#define srss_0_clock_0_hfclk_3_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF3 3UL #define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U @@ -53,6 +55,7 @@ extern "C" { #define srss_0_clock_0_pathmux_3_ENABLED 1U #define srss_0_clock_0_pathmux_4_ENABLED 1U #define srss_0_clock_0_periclk_0_ENABLED 1U +#define srss_0_clock_0_pll_0_ENABLED 1U #define srss_0_clock_0_slowclk_0_ENABLED 1U #define srss_0_clock_0_wco_0_ENABLED 1U #define srss_0_power_0_ENABLED 1U diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg new file mode 100644 index 00000000000..61dc1091a66 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -0,0 +1,4 @@ +set SMIF_BANKS { + 0 {addr 0x18000000 size 0x1000000 psize 0x0000200 esize 0x0001000} +} + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/design.modus rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus index 8efc4fa4c1e..ad8992850d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -198,33 +198,33 @@ - + - + - + - + - + - + @@ -326,6 +326,10 @@ + + + + @@ -353,6 +357,12 @@ + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralNames.h index d2b32d667e8..e009c481df4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralNames.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralNames.h @@ -38,6 +38,7 @@ typedef enum { UART_7 = (int)SCB7_BASE, } UARTName; +#define DEVICE_SPI_COUNT CY_IP_MXSCB_INSTANCES typedef enum { SPI_0 = (int)SCB0_BASE, @@ -107,7 +108,7 @@ typedef enum { } DACName; typedef enum { - SMIF_0 = (int)SMIF0_BASE, + QSPI_0 = (int)SMIF0_BASE, } SMIFName; #ifdef __cplusplus diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c index cfd1be0c795..433e728ea3c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c @@ -24,71 +24,71 @@ #if DEVICE_SERIAL //*** SERIAL *** const PinMap PinMap_UART_RX[] = { - {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION( P0_2_SCB0_UART_RX)}, - {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION( P1_0_SCB7_UART_RX)}, - {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION( P2_0_SCB1_UART_RX)}, - {P3_0, UART_2, CYHAL_PIN_IN_FUNCTION( P3_0_SCB2_UART_RX)}, - {P4_0, UART_7, CYHAL_PIN_IN_FUNCTION( P4_0_SCB7_UART_RX)}, - {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION( P5_0_SCB5_UART_RX)}, - {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION( P6_0_SCB3_UART_RX)}, - {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION( P6_4_SCB6_UART_RX)}, - {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION( P7_0_SCB4_UART_RX)}, - {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION( P8_0_SCB4_UART_RX)}, - {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION( P9_0_SCB2_UART_RX)}, - {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION( P10_0_SCB1_UART_RX)}, - {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION( P11_0_SCB5_UART_RX)}, - {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION( P12_0_SCB6_UART_RX)}, - {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION( P13_0_SCB6_UART_RX)}, + {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)}, + {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)}, + {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)}, + {P3_0, UART_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_UART_RX)}, + {P4_0, UART_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_UART_RX)}, + {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, + {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)}, + {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, + {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)}, + {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)}, + {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, + {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, + {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)}, + {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)}, + {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)}, {NC, NC, 0} }; const PinMap PinMap_UART_TX[] = { - {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION( P0_3_SCB0_UART_TX)}, - {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION( P1_1_SCB7_UART_TX)}, - {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION( P2_1_SCB1_UART_TX)}, - {P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION( P3_1_SCB2_UART_TX)}, - {P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION( P4_1_SCB7_UART_TX)}, - {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION( P5_1_SCB5_UART_TX)}, - {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION( P6_1_SCB3_UART_TX)}, - {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION( P6_5_SCB6_UART_TX)}, - {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION( P7_1_SCB4_UART_TX)}, - {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION( P8_1_SCB4_UART_TX)}, - {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION( P9_1_SCB2_UART_TX)}, - {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION( P10_1_SCB1_UART_TX)}, - {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION( P11_1_SCB5_UART_TX)}, - {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION( P12_1_SCB6_UART_TX)}, - {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION( P13_1_SCB6_UART_TX)}, + {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)}, + {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)}, + {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)}, + {P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_UART_TX)}, + {P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_UART_TX)}, + {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, + {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)}, + {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, + {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, + {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)}, + {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, + {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, + {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)}, + {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)}, + {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)}, {NC, NC, 0} }; const PinMap PinMap_UART_RTS[] = { - {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION( P0_4_SCB0_UART_RTS)}, - {P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION( P1_2_SCB7_UART_RTS)}, - {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION( P2_2_SCB1_UART_RTS)}, - {P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION( P3_2_SCB2_UART_RTS)}, - {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION( P5_2_SCB5_UART_RTS)}, - {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION( P6_2_SCB3_UART_RTS)}, - {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION( P6_6_SCB6_UART_RTS)}, - {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION( P7_2_SCB4_UART_RTS)}, - {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION( P8_2_SCB4_UART_RTS)}, - {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION( P9_2_SCB2_UART_RTS)}, - {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION( P10_2_SCB1_UART_RTS)}, - {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION( P11_2_SCB5_UART_RTS)}, - {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION( P12_2_SCB6_UART_RTS)}, + {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, + {P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)}, + {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)}, + {P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_UART_RTS)}, + {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, + {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, + {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, + {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, + {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)}, + {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, + {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, + {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)}, + {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)}, {NC, NC, 0} }; const PinMap PinMap_UART_CTS[] = { - {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION( P0_5_SCB0_UART_CTS)}, - {P1_3, UART_7, CYHAL_PIN_IN_FUNCTION( P1_3_SCB7_UART_CTS)}, - {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION( P2_3_SCB1_UART_CTS)}, - {P3_3, UART_2, CYHAL_PIN_IN_FUNCTION( P3_3_SCB2_UART_CTS)}, - {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION( P5_3_SCB5_UART_CTS)}, - {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION( P6_3_SCB3_UART_CTS)}, - {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION( P6_7_SCB6_UART_CTS)}, - {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION( P7_3_SCB4_UART_CTS)}, - {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION( P8_3_SCB4_UART_CTS)}, - {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION( P9_3_SCB2_UART_CTS)}, - {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION( P10_3_SCB1_UART_CTS)}, - {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION( P11_3_SCB5_UART_CTS)}, - {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION( P12_3_SCB6_UART_CTS)}, + {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, + {P1_3, UART_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)}, + {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)}, + {P3_3, UART_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_UART_CTS)}, + {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, + {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, + {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, + {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)}, + {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)}, + {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, + {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, + {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)}, + {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)}, {NC, NC, 0} }; #endif // DEVICE_SERIAL @@ -97,39 +97,43 @@ const PinMap PinMap_UART_CTS[] = { #if DEVICE_I2C //*** I2C *** const PinMap PinMap_I2C_SCL[] = { - {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION( P0_2_SCB0_I2C_SCL)}, - {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION( P1_0_SCB7_I2C_SCL)}, - {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION( P2_0_SCB1_I2C_SCL)}, - {P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION( P3_0_SCB2_I2C_SCL)}, - {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION( P4_0_SCB7_I2C_SCL)}, - {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION( P5_0_SCB5_I2C_SCL)}, - {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION( P6_0_SCB3_I2C_SCL)}, - {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION( P6_4_SCB6_I2C_SCL)}, - {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION( P7_0_SCB4_I2C_SCL)}, - {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION( P8_0_SCB4_I2C_SCL)}, - {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION( P9_0_SCB2_I2C_SCL)}, - {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION( P10_0_SCB1_I2C_SCL)}, - {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION( P11_0_SCB5_I2C_SCL)}, - {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION( P12_0_SCB6_I2C_SCL)}, - {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION( P13_0_SCB6_I2C_SCL)}, + {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)}, + {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)}, + {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)}, + {P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_0_SCB2_I2C_SCL)}, + {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)}, + {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, + {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)}, + {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)}, + {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, + {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)}, + {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)}, + {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)}, + {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, + {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, + {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)}, + {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)}, + {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)}, {NC, NC, 0} }; const PinMap PinMap_I2C_SDA[] = { - {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION( P0_3_SCB0_I2C_SDA)}, - {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION( P1_1_SCB7_I2C_SDA)}, - {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION( P2_1_SCB1_I2C_SDA)}, - {P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION( P3_1_SCB2_I2C_SDA)}, - {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION( P4_1_SCB7_I2C_SDA)}, - {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION( P5_1_SCB5_I2C_SDA)}, - {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION( P6_1_SCB3_I2C_SDA)}, - {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION( P6_5_SCB6_I2C_SDA)}, - {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION( P7_1_SCB4_I2C_SDA)}, - {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION( P8_1_SCB4_I2C_SDA)}, - {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION( P9_1_SCB2_I2C_SDA)}, - {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION( P10_1_SCB1_I2C_SDA)}, - {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION( P11_1_SCB5_I2C_SDA)}, - {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION( P12_1_SCB6_I2C_SDA)}, - {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION( P13_1_SCB6_I2C_SDA)}, + {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)}, + {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)}, + {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)}, + {P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_1_SCB2_I2C_SDA)}, + {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)}, + {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, + {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)}, + {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)}, + {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, + {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)}, + {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, + {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)}, + {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, + {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, + {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)}, + {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)}, + {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)}, {NC, NC, 0} }; #endif // DEVICE_I2C @@ -137,71 +141,79 @@ const PinMap PinMap_I2C_SDA[] = { #if DEVICE_SPI //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_2_SCB0_SPI_MOSI)}, - {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_0_SCB7_SPI_MOSI)}, - {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_0_SCB1_SPI_MOSI)}, - {P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_0_SCB2_SPI_MOSI)}, - {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION( P4_0_SCB7_SPI_MOSI)}, - {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_0_SCB5_SPI_MOSI)}, - {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_0_SCB3_SPI_MOSI)}, - {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_4_SCB6_SPI_MOSI)}, - {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_0_SCB4_SPI_MOSI)}, - {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_0_SCB4_SPI_MOSI)}, - {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_0_SCB2_SPI_MOSI)}, - {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_0_SCB1_SPI_MOSI)}, - {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_0_SCB5_SPI_MOSI)}, - {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_0_SCB6_SPI_MOSI)}, - {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION( P13_0_SCB6_SPI_MOSI)}, + {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)}, + {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)}, + {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)}, + {P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_0_SCB2_SPI_MOSI)}, + {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)}, + {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, + {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)}, + {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)}, + {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, + {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)}, + {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)}, + {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)}, + {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, + {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, + {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)}, + {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)}, + {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)}, {NC, NC, 0} }; const PinMap PinMap_SPI_MISO[] = { - {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION( P0_3_SCB0_SPI_MISO)}, - {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION( P1_1_SCB7_SPI_MISO)}, - {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION( P2_1_SCB1_SPI_MISO)}, - {P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION( P3_1_SCB2_SPI_MISO)}, - {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION( P4_1_SCB7_SPI_MISO)}, - {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION( P5_1_SCB5_SPI_MISO)}, - {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION( P6_1_SCB3_SPI_MISO)}, - {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION( P6_5_SCB6_SPI_MISO)}, - {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION( P7_1_SCB4_SPI_MISO)}, - {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION( P8_1_SCB4_SPI_MISO)}, - {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION( P9_1_SCB2_SPI_MISO)}, - {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION( P10_1_SCB1_SPI_MISO)}, - {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION( P11_1_SCB5_SPI_MISO)}, - {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION( P12_1_SCB6_SPI_MISO)}, - {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION( P13_1_SCB6_SPI_MISO)}, + {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)}, + {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)}, + {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)}, + {P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P3_1_SCB2_SPI_MISO)}, + {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)}, + {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, + {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)}, + {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)}, + {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, + {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)}, + {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, + {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)}, + {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, + {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, + {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)}, + {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)}, + {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)}, {NC, NC, 0} }; const PinMap PinMap_SPI_SCLK[] = { - {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_4_SCB0_SPI_CLK)}, - {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_2_SCB7_SPI_CLK)}, - {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_2_SCB1_SPI_CLK)}, - {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_2_SCB2_SPI_CLK)}, - {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_2_SCB5_SPI_CLK)}, - {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_2_SCB3_SPI_CLK)}, - {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_6_SCB6_SPI_CLK)}, - {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_2_SCB4_SPI_CLK)}, - {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_2_SCB4_SPI_CLK)}, - {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_2_SCB2_SPI_CLK)}, - {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_2_SCB1_SPI_CLK)}, - {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_2_SCB5_SPI_CLK)}, - {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_2_SCB6_SPI_CLK)}, + {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, + {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)}, + {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)}, + {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)}, + {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, + {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, + {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)}, + {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, + {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)}, + {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, + {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)}, + {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, + {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, + {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)}, + {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)}, {NC, NC, 0} }; const PinMap PinMap_SPI_SSEL[] = { - {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_5_SCB0_SPI_SELECT0)}, - {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_3_SCB7_SPI_SELECT0)}, - {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_3_SCB1_SPI_SELECT0)}, - {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_3_SCB2_SPI_SELECT0)}, - {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_3_SCB5_SPI_SELECT0)}, - {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_3_SCB3_SPI_SELECT0)}, - {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_7_SCB6_SPI_SELECT0)}, - {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_3_SCB4_SPI_SELECT0)}, - {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_3_SCB4_SPI_SELECT0)}, - {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_3_SCB2_SPI_SELECT0)}, - {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_3_SCB1_SPI_SELECT0)}, - {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_3_SCB5_SPI_SELECT0)}, - {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_3_SCB6_SPI_SELECT0)}, + {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, + {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)}, + {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)}, + {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)}, + {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, + {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, + {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)}, + {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, + {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)}, + {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)}, + {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)}, + {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, + {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, + {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)}, + {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)}, {NC, NC, 0} }; #endif // DEVICE_SPI @@ -415,51 +427,48 @@ const PinMap PinMap_PWM_OUT[] = { #if DEVICE_ANALOGIN const PinMap PinMap_ADC[] = { - {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, - {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, - {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, - {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, - {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, - {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, - {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, - {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, {NC, NC, 0} }; #endif // DEVICE_ANALOGIN #if DEVICE_ANALOGOUT const PinMap PinMap_DAC[] = { - {P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_CTDAC)}, - {P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)}, // CTDAC connects to the P10_5 pin through the AMUXA bus + {P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, {NC, NC, 0} }; #endif // DEVICE_ANALOGIN #if DEVICE_QSPI -const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2 - {P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)}, - {NC, NC, 0} +const PinMap PinMap_QSPI_SCLK[] = { + {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, }; - -// Ensure that the spi_data pins are defined in the order 0 to 7 -const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2 - {P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0 - {P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1 - {P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2 - {P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3 - {P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4 - {P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5 - {P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6 - {P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7 - {NC, NC, 0} -}; - -// Ensure that the spi_select pins are defined in the order 0 to 3 -const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2 - {P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0 - {P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1 - {P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2 - {P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3 - {NC, NC, 0} +const PinMap PinMap_QSPI_SSEL[] = { + {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA0[] = { + {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA1[] = { + {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA2[] = { + {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA3[] = { + {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, }; #endif // DEVICE_QSPI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PinNames.h index faacf57baf1..e8ffc8ea40b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PinNames.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PinNames.h @@ -20,11 +20,8 @@ #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H -#include "cmsis.h" #include "PinNamesTypes.h" -#include "PortNames.h" #include "cyhal_pin_package.h" -#include "cyhal_utils.h" typedef cyhal_gpio_t PinName; @@ -68,16 +65,14 @@ typedef cyhal_gpio_t PinName; #define UART_RTS P5_2 #define UART_CTS P5_3 - // Reset pin unavailable +// Reset pin unavailable - -#define SWITCH2 P0_4 #define LED1 P13_7 #define LED2 P1_5 - #define LED_RED LED1 #define LED_GREEN LED2 +#define SWITCH2 P0_4 #define USER_BUTTON SWITCH2 #define BUTTON1 USER_BUTTON @@ -88,48 +83,20 @@ typedef cyhal_gpio_t PinName; #define QSPI_IO_3 P11_3 #define QSPI_SEL P11_2 - // Standardized interfaces names +#define QSPI_FLASH1_IO0 QSPI_IO_0 +#define QSPI_FLASH1_IO1 QSPI_IO_1 +#define QSPI_FLASH1_IO2 QSPI_IO_2 +#define QSPI_FLASH1_IO3 QSPI_IO_3 +#define QSPI_FLASH1_SCK QSPI_CLK +#define QSPI_FLASH1_CSN QSPI_SEL + +// Standardized interfaces names #define STDIO_UART_TX UART_TX #define STDIO_UART_RX UART_RX #define STDIO_UART_CTS UART_CTS #define STDIO_UART_RTS UART_RTS -#define CY_STDIO_UART_RX STDIO_UART_RX -#define CY_STDIO_UART_TX STDIO_UART_TX -#define CY_STDIO_UART_CTS STDIO_UART_CTS -#define CY_STDIO_UART_RTS STDIO_UART_RTS - -#define CY_BT_UART_RX BT_UART_RX -#define CY_BT_UART_TX BT_UART_TX -#define CY_BT_UART_CTS BT_UART_CTS -#define CY_BT_UART_RTS BT_UART_RTS - -#define CY_BT_PIN_POWER BT_PIN_POWER -#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE -#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE - - #define USBTX UART_TX #define USBRX UART_RX -#define AOUT P9_6 - -// PinName[15-0] = Port[15-8] + Pin[4-0] -static inline unsigned CY_PIN(PinName pin) -{ - return pin & 0x07; -} - -static inline unsigned CY_PORT(PinName pin) -{ - return (pin >> 8) & 0xFF; -} - -// Because MBED pin mapping API does not allow to map multiple instances of the PWM -// to be mapped to the same pin, we create special pin names to force 32-bit PWM unit -// usage instead of standard 16-bit PWM. - -#define PWM32(pin) CY_PIN_FORCE_PWM_32(pin) - - -#endif +#endif \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c similarity index 67% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c index 179bcc28cad..ea7e81e5927 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c @@ -1,9 +1,9 @@ /***************************************************************************//** -* \file cybsp_cy8cproto_064_sb.c +* \file CY8CPROTO-064-SB/cybsp.c * * Description: * Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-064-SB pioneer kit. +* CY8CPROTO-064-SB prototyping kit. * ******************************************************************************** * \copyright @@ -23,8 +23,7 @@ * limitations under the License. *******************************************************************************/ -//#include "cybsp_retarget.h" -#include "cybsp_cy8cproto_064_sb.h" +#include "cybsp.h" #include "cycfg.h" #if defined(__cplusplus) @@ -33,16 +32,25 @@ extern "C" { cy_rslt_t cybsp_init(void) { + cy_rslt_t result = CY_RSLT_SUCCESS; + init_cycfg_system(); - cy_rslt_t result = cybsp_led_init(CYBSP_USER_LED1); - result |= cybsp_led_init(CYBSP_USER_LED2); - result |= cybsp_btn_init(CYBSP_USER_BTN1); - -#if defined(CYBSP_RETARGET_ENABLED) - /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ + result = cybsp_register_sysclk_pm_callback(); + +#ifndef __MBED__ if (CY_RSLT_SUCCESS == result) { - result = cybsp_retarget_init(); + /* Initialize User LEDs */ + result |= cybsp_led_init(CYBSP_USER_LED1); + result |= cybsp_led_init(CYBSP_USER_LED2); + /* Initialize User Buttons */ + result |= cybsp_btn_init(CYBSP_USER_BTN1); + + /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_retarget_init(); + } } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h new file mode 100644 index 00000000000..afd1a4dd006 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h @@ -0,0 +1,36 @@ +/***************************************************************************//** +* \file CY8CPROTO-064-SB/cybsp.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CPROTO-064-SB prototyping kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cybsp_types.h" +#include "cybsp_core.h" +#ifndef __MBED__ +#include "cybsp_retarget.h" +#endif /* __MBED__ */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.h deleted file mode 100644 index 626a5fb73f9..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_cy8cproto_064_sb.h +++ /dev/null @@ -1,74 +0,0 @@ -/***************************************************************************//** -* \file cybsp_cy8cproto_064_sb.h -* -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-064-SB pioneer kit. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_bsp_cy8cproto_064_sb CY8CPROTO-064-SB -* \ingroup group_bsp -* \{ -* CY8CPROTO-064-SB PSoC 64 SecureBoot Prototyping Kit is a low-cost Prototyping -* Kit based on PSoC 64 SecureBoot MCU to enable customers to prototype and -* design with the PSoC 64 SecureBoot device. -* -*
Kit Features:
-*
    -*
  • PSoC 64 Secure MCU that combines IoT platform software, a root-of-trust with secure services, and the ultra-low power, hardware-based security capabilities of the PSoC 6 MCU architecture
    • -*
  • 128 Mb Serial NOR flash
    • -*
  • Full-speed USB device interface
    • -*
-* -*
Kit Contents:
-*
    -*
  • PSoC 64 SecureBoot Prototyping Board
    • -*
  • USB Type-A to Micro-B cable
    • -*
  • Quick start guide
    • -*
-* -* \defgroup group_bsp_cy8cproto_064_sb_macros Macros -* \defgroup group_bsp_cy8cproto_064_sb_functions Functions -* \defgroup group_bsp_cy8cproto_064_sb_enums Enumerated Types -*/ - -#pragma once - -#include -#include -#include "cybsp_api_core.h" -#include "cybsp_types.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** \cond INTERNAL */ - -// TODO: add BSP pin mappings - -/** \endcond */ - -#if defined(__cplusplus) -} -#endif - -/** \} group_bsp_cy8cproto_064_sb */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h index 553088655f8..7247a347f35 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h @@ -23,14 +23,6 @@ * limitations under the License. *******************************************************************************/ -/** -* \addtogroup group_bsp_cy8cproto_064_sb CY8CPROTO-064-SB -* \ingroup group_bsp -* \{ -* \defgroup group_bsp_cy8cproto_064_sb_macros Macros -* \defgroup group_bsp_cy8cproto_064_sb_enums Enumerated Types -*/ - #pragma once #include "cyhal.h" @@ -40,7 +32,7 @@ extern "C" { #endif /** -* \addtogroup group_bsp_cy8cproto_064_sb_macros +* \addtogroup group_bsp_pins Pin Mappings * \{ */ @@ -109,10 +101,10 @@ extern "C" { /** Pin: USB Device D- */ #define CYBSP_USB_DM P14_1 -/** \} group_bsp_cy8cproto_064_sb_macros */ +/** \} group_bsp_pins */ /** -* \addtogroup group_bsp_cy8cproto_064_sb_enums +* \addtogroup group_bsp_enums Enumerated Types * \{ */ @@ -148,10 +140,8 @@ typedef enum CYBSP_USER_BTN1 = CYBSP_SW2, } cybsp_btn_t; -/** \} group_bsp_cy8cproto_064_sb_enums */ +/** \} group_bsp_enums */ #if defined(__cplusplus) } #endif - -/** \} group_bsp_cy8cproto_064_sb */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cycfg_qspi_memslot.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cycfg_qspi_memslot.cyqspi deleted file mode 100644 index 3b668965d30..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cycfg_qspi_memslot.cyqspi +++ /dev/null @@ -1,63 +0,0 @@ - - - - PSoC 6.xml - - - 0 - S25FL128S - false - None - 0x18000000 - 0x10000 - 0x1800FFFF - true - false - QUAD_SPI_DATA_0_3 - S25FL128S - false - - - 1 - Not used - false - None - 0x18010000 - 0x10000 - 0x1801FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - 2 - Not used - false - None - 0x18020000 - 0x10000 - 0x1802FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - 3 - Not used - false - None - 0x18030000 - 0x10000 - 0x1803FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/psoc6_static_srm.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/psoc6_static_srm.h deleted file mode 100644 index f265e20da70..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/psoc6_static_srm.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * mbed Microcontroller Library - * Copyright (c) 2017-2018 Future Electronics - * Copyright (c) 2019 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - */ - -/* - * This file defines hardware resources reserved by device-generated code. These - * resources are accessed directly by the Peripheral Driver library (PDL). - * - * There are four classes of resources that must be declared here: - * 1 CYCFG_ASSIGNED_PORTS macro defines which ports and pins are reserved. - * You define these as a colon separated list of ports and pins reserved - * using macro SRM_PORT(port_num, pins), once for each reserved port. - * SRM_PORT macro arguments are port number (in the range 0 ... 14) and - * pins, which is a hex value with a bit set for each reserved pin on a port. - * - * 2 CYCFG_ASSIGNED_DIVIDERS macro defines which clock dividers are reserved. - * You define these as a colon separated list of dividers reserved - * using macro SRM_DIVIDER(type, reservations), once for each required - * divider type. - * SRM_DIVIDER arguments are divider type (one of cy_en_divider_types_t - * values) and reservations, which is a hex mask value with a bit set for - * each reserved divider of a given type. - * - * 3 CYCFG_ASSIGNED_SCBS macro defines which SCB blocks are reserved. - * You define these as a colon separated list of SCBs reserved using - * macro SRM_SCB(n), which argument is SCB number in a range 0 ... 7. - * - * 4 CYCFG_ASSIGNED_TCPWM macro defines which TCPWM blocks are reserved. - * You define these as a colon separated list of TCPWMs reserved using - * macro SRM_TCPWM(n), which argument is TCPWM number in a range 0 ... 31. - * - * Examples: - * #define CYCFG_ASSIGNED_PORTS SRM_PORT(0, 0x30), SRM_PORT(5, 0x03) - * - * #define CYCFG_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01) - * - * #define CYCFG_ASSIGNED_SCBS SRM_SCB(2) - * - * #define CYCFG_ASSIGNED_TCPWMS - * - */ - -/* P0_0 and P0_1 reserved for WCO, -* P1_0 reserved for CSD TX, -* P2_0 ... P2_5 reserved for SDHC -* P6-4, P6-6 and P6_7 reserved for SWD, -* P7_1, P7_2 and P7_7 reserved for CSD Capacitors -* P8_1 ... P8_7 reserved for CSD Buttons -* P11_2 ... P11_7 reserved for QSPI -* P14_0 ... P14_1 reserved for USB -*/ -#define CYCFG_ASSIGNED_PORTS SRM_PORT(0, 0x03), SRM_PORT(1, 0x01),\ - SRM_PORT(2, 0x3f), SRM_PORT(6, 0xd0),\ - SRM_PORT(7, 0x86), SRM_PORT(8, 0xfe),\ - SRM_PORT(11, 0xfc), SRM_PORT(14, 0x03) - -/* -* 8-bit divider 0 reserved for UDB -* 8-bit divider 4 reserved for CSD -* 16-bit divider 0 reserved for USB -*/ -#define CYCFG_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x11), \ - SRM_DIVIDER(CY_SYSCLK_DIV_16_BIT, 0x01) - -#define CYCFG_ASSIGNED_SCBS - -#define CYCFG_ASSIGNED_TCPWMS - -/* End of File */ diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index c270f935875..2d188b0de23 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -688,7 +688,7 @@ def sign_image(t_self, resources, elf, binf): "is not compatible with Cypress Secure Boot target. " "You are using Python " + str(sys.version[:5]) + " which is not supported by CySecureTools. " - "Consider installing Python 3.7+ and rebuild target. " + "Consider installing Python 3.4+ and rebuild target. " "For more information refver to User Guide https://www.cypress.com/secureboot-sdk-user-guide") else: from tools.targets.PSOC6 import sign_image as psoc6_sign_image From 9780c9018e14adecec1d3f36281cb8b822db9273 Mon Sep 17 00:00:00 2001 From: Roman Okhrimenko Date: Fri, 30 Aug 2019 16:00:09 +0300 Subject: [PATCH 16/16] Disabled QSPI for now --- .../TARGET_PSOC6/common/cybsp_serial_flash_prog.c | 4 ++-- targets/targets.json | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash_prog.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash_prog.c index 1948adcd619..c0306dc6fbd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash_prog.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash_prog.c @@ -41,7 +41,7 @@ extern "C" { #endif -#if defined(CYBSP_QSPI_SCK) +#if defined(CYBSP_QSPI_SCK) && (DEVICE_QSPI) #include "cycfg_qspi_memslot.h" typedef struct @@ -85,7 +85,7 @@ const uint32_t cyToc[128] = }; /** \} group_bsp_serial_flash_variables */ -#endif /* defined(CYBSP_QSPI_SCK) */ +#endif /* defined(CYBSP_QSPI_SCK) && (DEVICE_QSPI) */ #if defined(__cplusplus) } diff --git a/targets/targets.json b/targets/targets.json index eca61fd47ce..9e3d854e2e4 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8703,6 +8703,8 @@ }, "CY8CPROTO_064_SB": { "inherits": ["MCU_PSOC6_M4"], + "components_remove": ["QSPIF"], + "device_has_remove": ["QSPI"], "supported_form_factors": ["ARDUINO"], "extra_labels_add": ["PSOC6_01"], "macros_add": ["CYB06447BZI_D54",