From e74fbcd79ebaf7f2891a93669ff74b79b04e4b99 Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Wed, 17 Jul 2019 13:19:32 -0500 Subject: [PATCH 1/6] Add CC3220SF_Launchxl to Mbed OS --- .../blockdevice/COMPONENT_SD/mbed_lib.json | 6 + .../TARGET_CC3220SF/PeripheralPins.h | 35 + .../TARGET_CC32XX/TARGET_CC3220SF/PortNames.h | 33 + .../CC3220SF_LAUNCHXL.c | 286 ++ .../CC3220SF_LAUNCHXL.h | 220 ++ .../PeripheralNames.h | 58 + .../TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c | 116 + .../TARGET_CC3220SF_LAUNCHXL/PinNames.h | 161 + .../TargetConfiguration.ccxml | 14 + .../TARGET_CC3220SF/analogin_api.c | 57 + .../TARGET_CC32XX/TARGET_CC3220SF/device.h | 23 + .../TARGET_CC3220SF/device/CC3220SF.h | 346 ++ .../TARGET_CC3220SF/device/CC3220SF_Init.cpp | 160 + .../TARGET_CC3220SF/device/CC3220SF_Init.h | 30 + .../device/CC3220SF_WiFiInterface.cpp | 674 ++++ .../device/CC3220SF_WiFiInterface.h | 373 ++ .../device/TOOLCHAIN_ARM_STD/CC3220SF.sct | 104 + .../TOOLCHAIN_ARM_STD/startup_CC3220SF.S | 371 ++ .../device/TOOLCHAIN_GCC_ARM/gcc_arm.ld | 218 ++ .../TOOLCHAIN_GCC_ARM/startup_CC3220SF.S | 451 +++ .../device/TOOLCHAIN_IAR/CC3220SF.icf | 100 + .../device/TOOLCHAIN_IAR/startup_CC3220SF.S | 486 +++ .../device/cc3200_simplelink.cpp | 937 +++++ .../device/cc3200_simplelink.h | 330 ++ .../TARGET_CC3220SF/device/cmsis.h | 41 + .../TARGET_CC3220SF/device/cmsis_nvic.h | 39 + .../device/default_wifi_interface.cpp | 24 + .../TARGET_CC3220SF/device/system_CC3220SF.c | 64 + .../TARGET_CC3220SF/device/system_CC3220SF.h | 79 + .../device/wifi_event_handler.cpp | 514 +++ .../TARGET_CC32XX/TARGET_CC3220SF/flash_api.c | 84 + .../TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c | 102 + .../TARGET_CC3220SF/gpio_irq_api.c | 173 + .../TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c | 115 + .../TARGET_CC32XX/TARGET_CC3220SF/objects.h | 177 + .../TARGET_CC32XX/TARGET_CC3220SF/pinmap.c | 49 + .../TARGET_CC32XX/TARGET_CC3220SF/port_api.c | 108 + .../TARGET_CC3220SF/pwmout_api.c | 181 + .../TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c | 52 + .../TARGET_CC3220SF/serial_api.c | 405 ++ .../TARGET_CC3220SF/serial_object.h | 49 + .../TARGET_CC32XX/TARGET_CC3220SF/spi_api.c | 470 +++ .../TARGET_CC3220SF/ti/devices/DeviceFamily.h | 210 + .../ti/devices/cc32xx/driverlib/adc.c | 693 ++++ .../ti/devices/cc32xx/driverlib/adc.h | 118 + .../ti/devices/cc32xx/driverlib/camera.c | 603 +++ .../ti/devices/cc32xx/driverlib/camera.h | 132 + .../ti/devices/cc32xx/driverlib/cpu.c | 356 ++ .../ti/devices/cc32xx/driverlib/cpu.h | 85 + .../ti/devices/cc32xx/driverlib/crc.c | 306 ++ .../ti/devices/cc32xx/driverlib/crc.h | 99 + .../ti/devices/cc32xx/driverlib/debug.h | 68 + .../ti/devices/cc32xx/driverlib/flash.c | 864 +++++ .../ti/devices/cc32xx/driverlib/flash.h | 116 + .../ti/devices/cc32xx/driverlib/gpio.c | 717 ++++ .../ti/devices/cc32xx/driverlib/gpio.h | 141 + .../ti/devices/cc32xx/driverlib/hwspinlock.c | 270 ++ .../ti/devices/cc32xx/driverlib/hwspinlock.h | 86 + .../ti/devices/cc32xx/driverlib/i2s.c | 1013 +++++ .../ti/devices/cc32xx/driverlib/i2s.h | 219 ++ .../ti/devices/cc32xx/driverlib/interrupt.c | 770 ++++ .../ti/devices/cc32xx/driverlib/interrupt.h | 121 + .../ti/devices/cc32xx/driverlib/pin.c | 884 +++++ .../ti/devices/cc32xx/driverlib/pin.h | 192 + .../ti/devices/cc32xx/driverlib/prcm.c | 2752 +++++++++++++ .../ti/devices/cc32xx/driverlib/prcm.h | 368 ++ .../ti/devices/cc32xx/driverlib/rom.h | 2787 +++++++++++++ .../ti/devices/cc32xx/driverlib/rom_map.h | 3321 ++++++++++++++++ .../ti/devices/cc32xx/driverlib/rom_patch.h | 115 + .../ti/devices/cc32xx/driverlib/sdhost.c | 745 ++++ .../ti/devices/cc32xx/driverlib/sdhost.h | 205 + .../ti/devices/cc32xx/driverlib/shamd5.c | 1249 ++++++ .../ti/devices/cc32xx/driverlib/shamd5.h | 133 + .../ti/devices/cc32xx/driverlib/systick.c | 276 ++ .../ti/devices/cc32xx/driverlib/systick.h | 79 + .../ti/devices/cc32xx/driverlib/ti_aes.c | 1361 +++++++ .../ti/devices/cc32xx/driverlib/ti_aes.h | 219 ++ .../ti/devices/cc32xx/driverlib/ti_des.c | 888 +++++ .../ti/devices/cc32xx/driverlib/ti_des.h | 144 + .../ti/devices/cc32xx/driverlib/ti_i2c.c | 2053 ++++++++++ .../ti/devices/cc32xx/driverlib/ti_i2c.h | 362 ++ .../cc32xx/driverlib/ti_spi_driverlib.c | 1528 ++++++++ .../cc32xx/driverlib/ti_spi_driverlib.h | 164 + .../ti/devices/cc32xx/driverlib/ti_timer.c | 1105 ++++++ .../ti/devices/cc32xx/driverlib/ti_timer.h | 211 + .../ti/devices/cc32xx/driverlib/uart.c | 1501 +++++++ .../ti/devices/cc32xx/driverlib/uart.h | 235 ++ .../ti/devices/cc32xx/driverlib/udma.c | 1257 ++++++ .../ti/devices/cc32xx/driverlib/udma.h | 664 ++++ .../ti/devices/cc32xx/driverlib/utils.c | 99 + .../ti/devices/cc32xx/driverlib/utils.h | 81 + .../ti/devices/cc32xx/driverlib/version.h | 76 + .../ti/devices/cc32xx/driverlib/wdt.c | 492 +++ .../ti/devices/cc32xx/driverlib/wdt.h | 83 + .../ti/devices/cc32xx/inc/asmdefs.h | 227 ++ .../ti/devices/cc32xx/inc/hw_adc.h | 886 +++++ .../ti/devices/cc32xx/inc/hw_aes.h | 800 ++++ .../ti/devices/cc32xx/inc/hw_apps_config.h | 745 ++++ .../ti/devices/cc32xx/inc/hw_apps_rcm.h | 1504 +++++++ .../ti/devices/cc32xx/inc/hw_camera.h | 517 +++ .../ti/devices/cc32xx/inc/hw_common_reg.h | 1115 ++++++ .../ti/devices/cc32xx/inc/hw_des.h | 337 ++ .../ti/devices/cc32xx/inc/hw_dthe.h | 390 ++ .../ti/devices/cc32xx/inc/hw_flash_ctrl.h | 1860 +++++++++ .../ti/devices/cc32xx/inc/hw_gpio.h | 1347 +++++++ .../ti/devices/cc32xx/inc/hw_gprcm.h | 3320 ++++++++++++++++ .../ti/devices/cc32xx/inc/hw_hib1p2.h | 1748 +++++++++ .../ti/devices/cc32xx/inc/hw_hib3p3.h | 1136 ++++++ .../ti/devices/cc32xx/inc/hw_i2c.h | 501 +++ .../ti/devices/cc32xx/inc/hw_ints.h | 115 + .../ti/devices/cc32xx/inc/hw_mcasp.h | 1704 ++++++++ .../ti/devices/cc32xx/inc/hw_mcspi.h | 1743 +++++++++ .../ti/devices/cc32xx/inc/hw_memmap.h | 82 + .../ti/devices/cc32xx/inc/hw_mmchs.h | 1917 +++++++++ .../ti/devices/cc32xx/inc/hw_nvic.h | 1708 ++++++++ .../ti/devices/cc32xx/inc/hw_ocp_shared.h | 3443 +++++++++++++++++ .../ti/devices/cc32xx/inc/hw_shamd5.h | 1240 ++++++ .../ti/devices/cc32xx/inc/hw_stack_die_ctrl.h | 762 ++++ .../ti/devices/cc32xx/inc/hw_timer.h | 776 ++++ .../ti/devices/cc32xx/inc/hw_types.h | 74 + .../ti/devices/cc32xx/inc/hw_uart.h | 415 ++ .../ti/devices/cc32xx/inc/hw_udma.h | 334 ++ .../ti/devices/cc32xx/inc/hw_wdt.h | 129 + .../TARGET_CC3220SF/ti/drivers/Power.h | 607 +++ .../ti/drivers/dma/UDMACC32XX.c | 164 + .../ti/drivers/dma/UDMACC32XX.h | 208 + .../TARGET_CC3220SF/ti/drivers/dpl/ClockP.h | 323 ++ .../TARGET_CC3220SF/ti/drivers/dpl/DebugP.h | 170 + .../TARGET_CC3220SF/ti/drivers/dpl/HwiP.h | 294 ++ .../ti/drivers/dpl/HwiPCC32XX.cpp | 390 ++ .../TARGET_CC3220SF/ti/drivers/dpl/MutexP.cpp | 97 + .../TARGET_CC3220SF/ti/drivers/dpl/MutexP.h | 214 + .../ti/drivers/dpl/PowerCC32XX_mbed.cpp | 220 ++ .../ti/drivers/dpl/SemaphoreP.cpp | 137 + .../ti/drivers/dpl/SemaphoreP.h | 255 ++ .../TARGET_CC3220SF/ti/drivers/dpl/SwiP.h | 264 ++ .../TARGET_CC3220SF/ti/drivers/dpl/SystemP.h | 59 + .../ti/drivers/net/wifi/device.h | 731 ++++ .../ti/drivers/net/wifi/errors.h | 736 ++++ .../ti/drivers/net/wifi/eventreg.c | 381 ++ .../ti/drivers/net/wifi/eventreg.h | 153 + .../TARGET_CC3220SF/ti/drivers/net/wifi/fs.h | 850 ++++ .../ti/drivers/net/wifi/netapp.h | 1334 +++++++ .../ti/drivers/net/wifi/netcfg.h | 663 ++++ .../ti/drivers/net/wifi/netutil.h | 519 +++ .../ti/drivers/net/wifi/porting/cc_pal.cpp | 496 +++ .../ti/drivers/net/wifi/porting/cc_pal.h | 419 ++ .../ti/drivers/net/wifi/porting/user.h | 1332 +++++++ .../ti/drivers/net/wifi/simplelink.h | 1253 ++++++ .../ti/drivers/net/wifi/sl_socket.h | 1550 ++++++++ .../ti/drivers/net/wifi/slnetif/slnetifwifi.c | 453 +++ .../ti/drivers/net/wifi/slnetifwifi.h | 1230 ++++++ .../ti/drivers/net/wifi/source/device.c | 782 ++++ .../ti/drivers/net/wifi/source/driver.c | 3269 ++++++++++++++++ .../ti/drivers/net/wifi/source/driver.h | 515 +++ .../ti/drivers/net/wifi/source/flowcont.c | 61 + .../ti/drivers/net/wifi/source/flowcont.h | 58 + .../ti/drivers/net/wifi/source/fs.c | 832 ++++ .../ti/drivers/net/wifi/source/netapp.c | 1669 ++++++++ .../ti/drivers/net/wifi/source/netcfg.c | 151 + .../ti/drivers/net/wifi/source/netutil.c | 223 ++ .../ti/drivers/net/wifi/source/nonos.c | 119 + .../ti/drivers/net/wifi/source/nonos.h | 165 + .../ti/drivers/net/wifi/source/objInclusion.h | 345 ++ .../ti/drivers/net/wifi/source/protocol.h | 1346 +++++++ .../ti/drivers/net/wifi/source/sl_socket.c | 2011 ++++++++++ .../ti/drivers/net/wifi/source/spawn.c | 134 + .../ti/drivers/net/wifi/source/spawn.h | 60 + .../ti/drivers/net/wifi/source/wlan.c | 1208 ++++++ .../ti/drivers/net/wifi/trace.h | 226 ++ .../ti/drivers/net/wifi/wlan.h | 2282 +++++++++++ .../ti/drivers/power/PowerCC32XX.c | 1420 +++++++ .../ti/drivers/power/PowerCC32XX.h | 660 ++++ .../ti/drivers/spi/SPICC32XXDMA.c | 803 ++++ .../ti/drivers/spi/SPICC32XXDMA.h | 350 ++ .../TARGET_CC3220SF/ti/drivers/ti_SPI.c | 143 + .../TARGET_CC3220SF/ti/drivers/ti_SPI.h | 889 +++++ .../TARGET_CC3220SF/ti/drivers/utils/List.c | 182 + .../TARGET_CC3220SF/ti/drivers/utils/List.h | 269 ++ .../ti/drivers/utils/RingBuf.c | 142 + .../ti/drivers/utils/RingBuf.h | 149 + .../TARGET_CC3220SF/ti/net/slneterr.h | 674 ++++ .../TARGET_CC3220SF/ti/net/slnetif.h | 642 +++ .../TARGET_CC3220SF/ti/net/slnetsock.h | 1846 +++++++++ .../TARGET_CC3220SF/ti/net/slnetutils.h | 315 ++ .../TARGET_CC32XX/TARGET_CC3220SF/trng_api.c | 89 + .../TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c | 99 + targets/TARGET_TI/mbed_rtx.h | 30 + targets/targets.json | 38 + 189 files changed, 111504 insertions(+) create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PinNames.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/TargetConfiguration.ccxml create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.cpp create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/CC3220SF.sct create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/startup_CC3220SF.S create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/gcc_arm.ld create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/startup_CC3220SF.S create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/CC3220SF.icf create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/startup_CC3220SF.S create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis_nvic.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/default_wifi_interface.cpp create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/wifi_event_handler.cpp create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_object.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/DeviceFamily.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/debug.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_map.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_patch.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/systick.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/systick.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/version.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/asmdefs.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_adc.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_aes.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_config.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_rcm.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_camera.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_common_reg.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_des.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_dthe.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_flash_ctrl.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gpio.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gprcm.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib1p2.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib3p3.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_i2c.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ints.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcasp.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcspi.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_memmap.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mmchs.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_nvic.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ocp_shared.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_shamd5.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_timer.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_types.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_uart.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_udma.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_wdt.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Power.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/ClockP.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/DebugP.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiP.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiPCC32XX.cpp create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.cpp create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/PowerCC32XX_mbed.cpp create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.cpp create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SwiP.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SystemP.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/device.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/errors.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/fs.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netapp.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netcfg.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netutil.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.cpp create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/user.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/simplelink.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/sl_socket.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetif/slnetifwifi.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetifwifi.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/device.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/fs.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netapp.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netcfg.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netutil.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/objInclusion.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/protocol.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/sl_socket.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/wlan.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/trace.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/wlan.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.c create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slneterr.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetif.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetsock.h create mode 100755 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetutils.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c create mode 100644 targets/TARGET_TI/mbed_rtx.h diff --git a/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json index 476f1a17ffc..f78a057cf27 100644 --- a/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json @@ -165,6 +165,12 @@ "SPI_MISO": "D12", "SPI_CLK": "D13", "SPI_CS": "D10" + }, + "CC3220SF_LAUNCHXL": { + "SPI_MOSI": "D11", + "SPI_MISO": "D12", + "SPI_CLK": "D13", + "SPI_CS": "D10" } } } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h new file mode 100644 index 00000000000..9d4d30b4ed9 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h @@ -0,0 +1,35 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************GPIO***************/ +extern const PinMap PinMap_GPIO[]; + +/************PWM****************/ +extern const PinMap PinMap_PWM[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h new file mode 100644 index 00000000000..375c460af1b --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h @@ -0,0 +1,33 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c new file mode 100755 index 00000000000..47c9772384f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== CC3220SF_LAUNCHXL.c ======== + * This file is responsible for setting up the board specific items for the + * CC3220SF_LAUNCHXL board. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "CC3220SF_LAUNCHXL.h" + +/* + * =============================== Power =============================== + */ +/* + * This table defines the parking state to be set for each parkable pin + * during LPDS. (Device pins must be parked during LPDS to achieve maximum + * power savings.) If the pin should be left unparked, specify the state + * PowerCC32XX_DONT_PARK. For example, for a UART TX pin, the device + * will automatically park the pin in a high state during transition to LPDS, + * so the Power Manager does not need to explictly park the pin. So the + * corresponding entries in this table should indicate PowerCC32XX_DONT_PARK. + */ +PowerCC32XX_ParkInfo parkInfo[] = { +/* PIN PARK STATE PIN ALIAS (FUNCTION) + ----------------- ------------------------------ -------------------- */ + {PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10 */ + {PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11 */ + {PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12 */ + {PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13 */ + {PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14 */ + {PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15 */ + {PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16 */ + {PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17 */ + {PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN */ + {PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22 */ + {PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG) */ + {PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG) */ + {PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG) */ + {PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG) */ + {PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28 */ + {PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2 */ + {PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1 */ + {PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2 */ + {PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P */ + {PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0 */ + {PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N */ + {PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30 */ + {PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO1 (XDS_UART_RX) */ + {PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO2 (XDS_UART_TX) */ + {PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3 */ + {PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4 */ + {PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5 */ + {PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6 */ + {PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7 */ + {PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8 */ + {PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9 */ +}; + +/* + * This structure defines the configuration for the Power Manager. + * + * In this configuration the Power policy is disabled by default (because + * enablePolicy is set to false). The Power policy can be enabled dynamically + * at runtime by calling Power_enablePolicy(), or at build time, by changing + * enablePolicy to true in this structure. + */ +const PowerCC32XX_ConfigV1 PowerCC32XX_config = { + .policyInitFxn = &PowerCC32XX_initPolicy, + .policyFxn = &PowerCC32XX_sleepPolicy, + .enterLPDSHookFxn = NULL, + .resumeLPDSHookFxn = NULL, + .enablePolicy = false, + .enableGPIOWakeupLPDS = true, + .enableGPIOWakeupShutdown = true, + .enableNetworkWakeupLPDS = true, + .wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13, + .wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE, + .wakeupGPIOFxnLPDS = NULL, + .wakeupGPIOFxnLPDSArg = 0, + .wakeupGPIOSourceShutdown = PRCM_HIB_GPIO13, + .wakeupGPIOTypeShutdown = PRCM_HIB_RISE_EDGE, + .ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 | + PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4, + .keepDebugActiveDuringLPDS = false, + .ioRetentionShutdown = PRCM_IO_RET_GRP_1, + .pinParkDefs = parkInfo, + .numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo) +}; +/* + * =============================== SPI =============================== + */ +#include +#include + +SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT]; + +#ifdef TOOLCHAIN_GCC_ARM +__attribute__ ((aligned (32))) +#elif defined TOOLCHAIN_ARM +__attribute__ ((aligned (32))) +#elif defined TOOLCHAIN_IAR +#pragma data_alignment=32 +#endif +uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT]; + +const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = { + /* index 0 is reserved for LSPI that links to the NWP */ + { + .baseAddr = LSPI_BASE, + .intNum = INT_LSPI, + .intPriority = (~0), + .spiPRCM = PRCM_LSPI, + .csControl = SPI_SW_CTRL_CS, + .csPolarity = SPI_CS_ACTIVEHIGH, + .pinMode = SPI_4PIN_MODE, + .turboMode = SPI_TURBO_OFF, + .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CH12_LSPI_RX, + .txChannelIndex = UDMA_CH13_LSPI_TX, + .minDmaTransferSize = 100, + .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG, + .misoPin = SPICC32XXDMA_PIN_NO_CONFIG, + .clkPin = SPICC32XXDMA_PIN_NO_CONFIG, + .csPin = SPICC32XXDMA_PIN_NO_CONFIG + }, + { + .baseAddr = GSPI_BASE, + .intNum = INT_GSPI, + .intPriority = (~0), + .spiPRCM = PRCM_GSPI, + .csControl = SPI_HW_CTRL_CS, + .csPolarity = SPI_CS_ACTIVELOW, + .pinMode = SPI_4PIN_MODE, + .turboMode = SPI_TURBO_OFF, + .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CH6_GSPI_RX, + .txChannelIndex = UDMA_CH7_GSPI_TX, + .minDmaTransferSize = 10, + .mosiPin = SPICC32XXDMA_PIN_07_MOSI, + .misoPin = SPICC32XXDMA_PIN_06_MISO, + .clkPin = SPICC32XXDMA_PIN_05_CLK, + .csPin = SPICC32XXDMA_PIN_08_CS + } +}; + +const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = { + { + .fxnTablePtr = &SPICC32XXDMA_fxnTable, + .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0], + .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0] + }, + { + .fxnTablePtr = &SPICC32XXDMA_fxnTable, + .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1], + .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1] + } +}; + +const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT; + +/* + * =============================== DMA =============================== + */ +#include + +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(dmaControlTable, 1024) +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=1024 +#elif defined(__GNUC__) +__attribute__ ((aligned (1024))) +#endif +static tDMAControlTable dmaControlTable[64]; + +/* + * ======== dmaErrorFxn ======== + * This is the handler for the uDMA error interrupt. + */ +static void dmaErrorFxn(uintptr_t arg) +{ + int status = MAP_uDMAErrorStatusGet(); + MAP_uDMAErrorStatusClear(); + + /* Suppress unused variable warning */ + (void)status; + + while (1); +} + +UDMACC32XX_Object udmaCC3220SObject; + +const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = { + .controlBaseAddr = (void *)dmaControlTable, + .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn, + .intNum = INT_UDMAERR, + .intPriority = (~0) +}; + +const UDMACC32XX_Config UDMACC32XX_config = { + .object = &udmaCC3220SObject, + .hwAttrs = &udmaCC3220SHWAttrs +}; +/* + * =============================== General =============================== + */ +/* + * ======== CC3220SF_LAUNCHXL_initGeneral ======== + */ +void CC3220SF_LAUNCHXL_initGeneral(void) +{ + MAP_IntMasterEnable(); + //MAP_IntEnable(FAULT_SYSTICK); + PRCMCC3200MCUInit(); + //Power_init(); +} + +#if defined TOOLCHAIN_ARM +__attribute__((section("signature_section"))) +#elif defined TOOLCHAIN_IAR +#pragma default_variable_attributes = @ ".dbghdr" +#elif defined TOOLCHAIN_GCC_ARM +__attribute__ ((section (".dbghdr"))) +#endif +const unsigned long ulDebugHeader[]= +{ + 0x5AA5A55A, + 0x000FF800, + 0xEFA3247D +}; diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h new file mode 100755 index 00000000000..d33152ffc34 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file C3220SF_LAUNCHXL.h + * + * @brief CC3220 Board Specific APIs + * + * The CC3220SF_LAUNCHXL header file should be included in an application as + * follows: + * @code + * #include + * @endcode + * + * ============================================================================ + */ +#ifndef __CC3220SF_LAUNCHXL_H +#define __CC3220SF_LAUNCHXL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define CC3220SF_LAUNCHXL_GPIO_LED_OFF (0) +#define CC3220SF_LAUNCHXL_GPIO_LED_ON (1) + +/*! + * @def CC3220SF_LAUNCHXL_ADCName + * @brief Enum of ADC names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_ADCName { + CC3220SF_LAUNCHXL_ADC0 = 0, + CC3220SF_LAUNCHXL_ADC1, + + CC3220SF_LAUNCHXL_ADCCOUNT +} CC3220SF_LAUNCHXL_ADCName; + +/*! + * @def CC3220SF_LAUNCHXL_CaptureName + * @brief Enum of Capture names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_CaptureName { + CC3220SF_LAUNCHXL_CAPTURE0 = 0, + CC3220SF_LAUNCHXL_CAPTURE1, + + CC3220SF_LAUNCHXL_CAPTURECOUNT +} CC3220SF_LAUNCHXL_CaptureName; + +/*! + * @def CC3220SF_LAUNCHXL_CryptoName + * @brief Enum of Crypto names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_CryptoName { + CC3220SF_LAUNCHXL_CRYPTO0 = 0, + + CC3220SF_LAUNCHXL_CRYPTOCOUNT +} CC3220SF_LAUNCHXL_CryptoName; + +/*! + * @def CC3220SF_LAUNCHXL_GPIOName + * @brief Enum of GPIO names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_GPIOName { + CC3220SF_LAUNCHXL_GPIO_SW2 = 0, + CC3220SF_LAUNCHXL_GPIO_SW3, + CC3220SF_LAUNCHXL_SPI_MASTER_READY, + CC3220SF_LAUNCHXL_SPI_SLAVE_READY, + CC3220SF_LAUNCHXL_GPIO_LED_D7, + + /* + * CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the + * I2C and PWM peripherals. In order for those examples to work, these + * LEDs are taken out of gpioPinCOnfig[] + */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D6, */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D5, */ + + /* Sharp 96x96 LCD Pins */ + CC3220SF_LAUNCHXL_LCD_CS, + CC3220SF_LAUNCHXL_LCD_POWER, + CC3220SF_LAUNCHXL_LCD_ENABLE, + + CC3220SF_LAUNCHXL_GPIOCOUNT +} CC3220SF_LAUNCHXL_GPIOName; + +/*! + * @def CC3220SF_LAUNCHXL_I2CName + * @brief Enum of I2C names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_I2CName { + CC3220SF_LAUNCHXL_I2C0 = 0, + + CC3220SF_LAUNCHXL_I2CCOUNT +} CC3220SF_LAUNCHXL_I2CName; + +/*! + * @def CC3220SF_LAUNCHXL_I2SName + * @brief Enum of I2S names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_I2SName { + CC3220SF_LAUNCHXL_I2S0 = 0, + + CC3220SF_LAUNCHXL_I2SCOUNT +} CC3220SF_LAUNCHXL_I2SName; + +/*! + * @def CC3220SF_LAUNCHXL_PWMName + * @brief Enum of PWM names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_PWMName { + CC3220SF_LAUNCHXL_PWM6 = 0, + CC3220SF_LAUNCHXL_PWM7, + + CC3220SF_LAUNCHXL_PWMCOUNT +} CC3220SF_LAUNCHXL_PWMName; + +/*! + * @def CC3220SF_LAUNCHXL_SDFatFSName + * @brief Enum of SDFatFS names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDFatFSName { + CC3220SF_LAUNCHXL_SDFatFS0 = 0, + + CC3220SF_LAUNCHXL_SDFatFSCOUNT +} CC3220SF_LAUNCHXL_SDFatFSName; + +/*! + * @def CC3220SF_LAUNCHXL_SDName + * @brief Enum of SD names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDName { + CC3220SF_LAUNCHXL_SD0 = 0, + + CC3220SF_LAUNCHXL_SDCOUNT +} CC3220SF_LAUNCHXL_SDName; + +/*! + * @def CC3220SF_LAUNCHXL_SPIName + * @brief Enum of SPI names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SPIName { + CC3220SF_LAUNCHXL_SPI0 = 0, + CC3220SF_LAUNCHXL_SPI1, + + CC3220SF_LAUNCHXL_SPICOUNT +} CC3220SF_LAUNCHXL_SPIName; + +/*! + * @def CC3220SF_LAUNCHXL_TimerName + * @brief Enum of Timer names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_TimerName { + CC3220SF_LAUNCHXL_TIMER0 = 0, + CC3220SF_LAUNCHXL_TIMER1, + CC3220SF_LAUNCHXL_TIMER2, + + CC3220SF_LAUNCHXL_TIMERCOUNT +} CC3220SF_LAUNCHXL_TimerName; + +/*! + * @def CC3220SF_LAUNCHXL_UARTName + * @brief Enum of UARTs on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_UARTName { + CC3220SF_LAUNCHXL_UART0 = 0, + CC3220SF_LAUNCHXL_UART1, + + CC3220SF_LAUNCHXL_UARTCOUNT +} CC3220SF_LAUNCHXL_UARTName; + +/*! + * @def CC3220SF_LAUNCHXL_WatchdogName + * @brief Enum of Watchdogs on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_WatchdogName { + CC3220SF_LAUNCHXL_WATCHDOG0 = 0, + + CC3220SF_LAUNCHXL_WATCHDOGCOUNT +} CC3220SF_LAUNCHXL_WatchdogName; + +/*! + * @brief Initialize the general board specific settings + * + * This function initializes the general board specific settings. + */ +extern void CC3220SF_LAUNCHXL_initGeneral(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CC3220SF_LAUNCHXL_H */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h new file mode 100644 index 00000000000..a1cc02c6394 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)CC3220SF_UARTA0_BASE, + UART_1 = (int)CC3220SF_UARTA1_BASE +} UARTName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3 +} ADCName; + +typedef enum { + PWM_1 = 1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6 +} PWMName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +#define MBED_UART0 P55, P57 +#define MBED_UART1 P07, P08 +#define MBED_UARTUSB USBTX, USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c new file mode 100644 index 00000000000..f2fa9cf76de --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c @@ -0,0 +1,116 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************GPIO***************/ +const PinMap PinMap_GPIO[] = { + {PIN_50, CC3220SF_GPIOA0_BASE, 0}, //GPIO_00 (PM/Dig Mux) + {PIN_55, CC3220SF_GPIOA0_BASE, 1}, //GPIO_01 + {PIN_57, CC3220SF_GPIOA0_BASE, 2}, //GPIO_02 (Dig/ADC Mux) + {PIN_58, CC3220SF_GPIOA0_BASE, 3}, //GPIO_03 (Dig/ADC Mux) + {PIN_59, CC3220SF_GPIOA0_BASE, 4}, //GPIO_04 (Dig/ADC Mux) + {PIN_60, CC3220SF_GPIOA0_BASE, 5}, //GPIO_05 (Dig/ADC Mux) + {PIN_61, CC3220SF_GPIOA0_BASE, 6}, //GPIO_06 + {PIN_62, CC3220SF_GPIOA0_BASE, 7}, //GPIO_07 + + {PIN_63, CC3220SF_GPIOA1_BASE, 8}, //GPIO_08 + {PIN_64, CC3220SF_GPIOA1_BASE, 9}, //GPIO_09 + {PIN_01, CC3220SF_GPIOA1_BASE, 10}, //GPIO_10 + {PIN_02, CC3220SF_GPIOA1_BASE, 11}, //GPIO_11 + {PIN_03, CC3220SF_GPIOA1_BASE, 12}, //GPIO_12 + {PIN_04, CC3220SF_GPIOA1_BASE, 13}, //GPIO_13 + {PIN_05, CC3220SF_GPIOA1_BASE, 14}, //GPIO_14 + {PIN_06, CC3220SF_GPIOA1_BASE, 15}, //GPIO_15 + + {PIN_07, CC3220SF_GPIOA2_BASE, 16}, //GPIO_16 + {PIN_08, CC3220SF_GPIOA2_BASE, 17}, //GPIO_17 + //this is only here for reference + {PIN_XX, CC3220SF_GPIOA2_BASE, 18}, //GPIO_18 (Reserved) No package pin associate with this GPIO + {PIN_XX, CC3220SF_GPIOA2_BASE, 19}, //GPIO_19 (Reserved) No package pin associate with this GPIO + {PIN_XX, CC3220SF_GPIOA2_BASE, 20}, //GPIO_20 (Reserved) No package pin associate with this GPIO + {PIN_XX, CC3220SF_GPIOA2_BASE, 21}, //GPIO_21 (Reserved) No package pin associate with this GPIO + {PIN_15, CC3220SF_GPIOA2_BASE, 22}, //GPIO_22 + {PIN_16, CC3220SF_GPIOA2_BASE, 23}, //GPIO_23 + + {PIN_17, CC3220SF_GPIOA3_BASE, 24}, //GPIO_24 + // pin 21 is one of three that must have a passive pullup or pulldown resistor + // on board to configure the chip hardware power-up mode. Because of this, + // if this pin is used for digital functions, it must be output only. + {PIN_21, CC3220SF_GPIOA3_BASE, 25}, //GPIO_25 + //this is only here for reference + {PIN_XX, CC3220SF_GPIOA3_BASE, 26}, //GPIO_26 (Restricted Use; Antenna Selection 1 Only) No package pin associate with this GPIO + {PIN_XX, CC3220SF_GPIOA3_BASE, 27}, //GPIO_27 (Restricted Use; Antenna Selection 1 Only) No package pin associate with this GPIO + {PIN_18, CC3220SF_GPIOA3_BASE, 28}, //GPIO_28 + {PIN_20, CC3220SF_GPIOA3_BASE, 29}, //GPIO_29 + {PIN_53, CC3220SF_GPIOA3_BASE, 30}, //GPIO_30 (PM/Dig Mux) + {PIN_45, CC3220SF_GPIOA3_BASE, 31}, //GPIO_31 (PM/Dig Mux) + {NC, NC, 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PIN_01, PWM_1, 3}, + {PIN_02, PWM_2, 3}, + {PIN_17, PWM_3, 5}, + {PIN_19, PWM_4, 8}, + {PIN_21, PWM_5, 9}, + {PIN_64, PWM_6, 3}, +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PIN_01, UART_1, 7}, + {PIN_03, UART_0, 7}, + {PIN_07, UART_1, 5}, + {PIN_16, UART_1, 2}, + {PIN_53, UART_0, 9}, + {PIN_55, UART_0, 3}, + {PIN_55, UART_1, 6}, + {PIN_58, UART_1, 6}, + {PIN_62, UART_0, 11}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PIN_02, UART_1, 7}, + {PIN_04, UART_0, 7}, + {PIN_08, UART_1, 5}, + {PIN_17, UART_1, 2}, + {PIN_45, UART_0, 9}, + {PIN_45, UART_1, 2}, + {PIN_57, UART_0, 3}, + {PIN_57, UART_1, 6}, + {PIN_59, UART_1, 6}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PIN_50, UART_0, 3}, + {PIN_50, UART_1, 10}, + {PIN_52, UART_0, 6}, + {PIN_61, UART_0, 5}, + {PIN_62, UART_0, 10}, + {PIN_62, UART_1, 3}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PIN_50, UART_0, 12}, + {PIN_61, UART_0, 6}, + {PIN_61, UART_1, 3}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PinNames.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PinNames.h new file mode 100644 index 00000000000..ab2651d7016 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PinNames.h @@ -0,0 +1,161 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + P01 = 0x00000000, + P02 = 0x00000001, + P03 = 0x00000002, + P04 = 0x00000003, + P05 = 0x00000004, + P06 = 0x00000005, + P07 = 0x00000006, + P08 = 0x00000007, + P11 = 0x0000000A, + P12 = 0x0000000B, + P13 = 0x0000000C, + P14 = 0x0000000D, + P15 = 0x0000000E, + P16 = 0x0000000F, + P17 = 0x00000010, + P18 = 0x00000011, + P19 = 0x00000012, + P20 = 0x00000013, + P21 = 0x00000014, + P29 = 0x0000001C, + P30 = 0x0000001D, + P45 = 0x0000002C, + P46 = 0x0000002D, + P47 = 0x0000002E, + P48 = 0x0000002F, + P49 = 0x00000030, + P50 = 0x00000031, + P52 = 0x00000033, + P53 = 0x00000034, + P55 = 0x00000036, + P56 = 0x00000037, + P57 = 0x00000038, + P58 = 0x00000039, + P59 = 0x0000003A, + P60 = 0x0000003B, + P61 = 0x0000003C, + P62 = 0x0000003D, + P63 = 0x0000003E, + P64 = 0x0000003F, + + PIN_01 = P01, + PIN_02 = P02, + PIN_03 = P03, + PIN_04 = P04, + PIN_05 = P05, + PIN_06 = P06, + PIN_07 = P07, + PIN_08 = P08, + PIN_11 = P11, + PIN_12 = P12, + PIN_13 = P13, + PIN_14 = P14, + PIN_15 = P15, + PIN_16 = P16, + PIN_17 = P17, + PIN_18 = P18, + PIN_19 = P19, + PIN_20 = P20, + PIN_21 = P21, + PIN_29 = P29, + PIN_30 = P30, + PIN_45 = P45, + PIN_46 = P46, + PIN_47 = P47, + PIN_48 = P48, + PIN_49 = P49, + PIN_50 = P50, + PIN_52 = P52, + PIN_53 = P53, + PIN_55 = P55, + PIN_56 = P56, + PIN_57 = P57, + PIN_58 = P58, + PIN_59 = P59, + PIN_60 = P60, + PIN_61 = P61, + PIN_62 = P62, + PIN_63 = P63, + PIN_64 = P64, + + //LED 1 => RED, LED 2 => YELLOW, LED 3 = GREEN + LED1 = PIN_64, + LED2 = PIN_01, + LED3 = PIN_02, + + LED_RED = LED1, + LED_YELLOW = LED2, + LED_GREEN = LED3, + + // UART0 + USBTX = PIN_55, + USBRX = PIN_57, + + //Button + BUTTON1 = PIN_04, + BUTTON2 = PIN_15, + + //SPI1 + SPICC32XXDMA_MOSI = P07, + SPICC32XXDMA_MISO = P06, + SPICC32XXDMA_CLK = P05, + SPICC32XXDMA_CS = P08, + + // CI Shield + D10 = SPICC32XXDMA_CS, + D11 = SPICC32XXDMA_MOSI, + D12 = SPICC32XXDMA_MISO, + D13 = SPICC32XXDMA_CLK, + + // Not connected + NC = (int)0xFFFFFFFF, + PIN_RESERVED = NC, + PIN_XX = NC +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + OpenDrainPullUp = 4, + OpenDrainPullDown = 5, + Analog = 6, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/TargetConfiguration.ccxml b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/TargetConfiguration.ccxml new file mode 100644 index 00000000000..bb4ded18916 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/TargetConfiguration.ccxml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c new file mode 100644 index 00000000000..9368a8fa69a --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "PinNames.h" +#include "cmsis.h" + +#include +#include +#include +#include +#include + +#define ADC_DATA_MASK 0x3FFC //the data is from bit [13:2] +#define ADC_RESOLUTION 0xFFF + +void analogin_init(analogin_t *obj, PinName pin) { + ADCEnable(CC3220SF_ADC_BASE); + obj->pin = pin; + pin_mode(pin, Analog); + switch(pin){ + case PIN_57:obj->adc_ch = ADC_CH_0;break; + case PIN_58:obj->adc_ch = ADC_CH_1;break; + case PIN_59:obj->adc_ch = ADC_CH_2;break; + case PIN_60:obj->adc_ch = ADC_CH_3;break; + default: MBED_ASSERT(NC != (PinName)NC); + } + + ADCChannelEnable(CC3220SF_ADC_BASE, obj->adc_ch); +} + +uint16_t analogin_read_u16(analogin_t *obj) { + unsigned long adc_raw = ADCFIFORead(CC3220SF_ADC_BASE, obj->adc_ch); + + return (uint16_t) ((adc_raw & ADC_DATA_MASK) >> 2); +} + +float analogin_read(analogin_t *obj) { + uint16_t value = analogin_read_u16(obj); + return (float)value * (1.0f / (float)ADC_RESOLUTION); +} + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device.h new file mode 100644 index 00000000000..33ce58a44a1 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device.h @@ -0,0 +1,23 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h new file mode 100644 index 00000000000..feb3e90c50b --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h @@ -0,0 +1,346 @@ +/**************************************************************************//** + * @file CC3220SF.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for + * Device CC3220SF + * @version V5.00 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef CC3220SF_H +#define CC3220SF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +// mbed-os core_cm4.h adds offset of 16. Deduct 16 from the IRQ enums +#define INT_IRQn_OFFSET 16 + +typedef enum IRQn +{ +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== CC3220SF Specific Interrupt Numbers ========================================= */ + INT_GPIOA0_IRQn = 16 - INT_IRQn_OFFSET, // GPIO Port S0 + INT_GPIOA1_IRQn = 17 - INT_IRQn_OFFSET, // GPIO Port S1 + INT_GPIOA2_IRQn = 18 - INT_IRQn_OFFSET, // GPIO Port S2 + INT_GPIOA3_IRQn = 19 - INT_IRQn_OFFSET, // GPIO Port S3 + INT_UARTA0_IRQn = 21 - INT_IRQn_OFFSET, // UART0 Rx and Tx + INT_UARTA1_IRQn = 22 - INT_IRQn_OFFSET, // UART1 Rx and Tx + INT_I2CA0_IRQn = 24 - INT_IRQn_OFFSET, // I2C controller + INT_ADCCH0_IRQn = 30 - INT_IRQn_OFFSET, // ADC Sequence 0 + INT_ADCCH1_IRQn = 31 - INT_IRQn_OFFSET, // ADC Sequence 1 + INT_ADCCH2_IRQn = 32 - INT_IRQn_OFFSET, // ADC Sequence 2 + INT_ADCCH3_IRQn = 33 - INT_IRQn_OFFSET, // ADC Sequence 3 + INT_WDT_IRQn = 34 - INT_IRQn_OFFSET, // Watchdog Timer0 + INT_TIMERA0A_IRQn = 35 - INT_IRQn_OFFSET, // Timer 0 subtimer A + INT_TIMERA0B_IRQn = 36 - INT_IRQn_OFFSET, // Timer 0 subtimer B + INT_TIMERA1A_IRQn = 37 - INT_IRQn_OFFSET, // Timer 1 subtimer A + INT_TIMERA1B_IRQn = 38 - INT_IRQn_OFFSET, // Timer 1 subtimer B + INT_TIMERA2A_IRQn = 39 - INT_IRQn_OFFSET, // Timer 2 subtimer A + INT_TIMERA2B_IRQn = 40 - INT_IRQn_OFFSET, // Timer 2 subtimer B + INT_FLASH_IRQn = 45 - INT_IRQn_OFFSET, // FLASH Control + INT_TIMERA3A_IRQn = 51 - INT_IRQn_OFFSET, // Timer 3 subtimer A + INT_TIMERA3B_IRQn = 52 - INT_IRQn_OFFSET, // Timer 3 subtimer B + INT_UDMA_IRQn = 62 - INT_IRQn_OFFSET, // uDMA controller + INT_UDMAERR_IRQn = 63 - INT_IRQn_OFFSET, // uDMA Error + INT_SHA_IRQn = 164 - INT_IRQn_OFFSET, // SHA + INT_AES_IRQn = 167 - INT_IRQn_OFFSET, // AES + INT_DES_IRQn = 169 - INT_IRQn_OFFSET, // DES + INT_MMCHS_IRQn = 175 - INT_IRQn_OFFSET, // SDIO + INT_I2S_IRQn = 177 - INT_IRQn_OFFSET, // McAPS + INT_CAMERA_IRQn = 179 - INT_IRQn_OFFSET, // Camera + INT_NWPIC_IRQn = 187 - INT_IRQn_OFFSET, // Interprocessor communication + INT_PRCM_IRQn = 188 - INT_IRQn_OFFSET, // Power, Reset and Clock Module + INT_SSPI_IRQn = 191 - INT_IRQn_OFFSET, // Shared SPI + INT_GSPI_IRQn = 192 - INT_IRQn_OFFSET, // Generic SPI + INT_LSPI_IRQn = 193 - INT_IRQn_OFFSET // Link SPI +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the Arm Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */ +/* ToDo: define the correct core features for the CC3220SF */ +#define __MPU_PRESENT 1 /*!< Set to 1 if MPU is present */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< Set to 1 if FPU is present */ +#define __FPU_DP 0 /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */ +#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ +#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ +#define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< Arm Cortex-M4 processor and core peripherals */ +#include "system_CC3220SF.h" /*!< CC3220SF System */ + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPIO + */ +typedef struct +{ + __IO uint32_t DATA; /*!< Address offset : 0x00000000 */ + uint32_t RESERVED0[255]; + __IO uint32_t DIR; /*!< Address offset : 0x00000400 */ + __IO uint32_t IS; /*!< Address offset : 0x00000404 */ + __IO uint32_t IBE; /*!< Address offset : 0x00000408 */ + __IO uint32_t IEV; /*!< Address offset : 0x0000040C */ + __IO uint32_t IM; /*!< Address offset : 0x00000410 */ + __IO uint32_t RIS; /*!< Address offset : 0x00000414 */ + __IO uint32_t MIS; /*!< Address offset : 0x00000418 */ + __O uint32_t ICR; /*!< Address offset : 0x0000041C */ + __IO uint32_t AFSEL; /*!< Address offset : 0x00000420 */ + uint32_t RESERVED1[55]; + __IO uint32_t DR2R; /*!< Address offset : 0x00000500 */ + __IO uint32_t DR4R; /*!< Address offset : 0x00000504 */ + __IO uint32_t DR8R; /*!< Address offset : 0x00000508 */ + __IO uint32_t ODR; /*!< Address offset : 0x0000050C */ + __IO uint32_t PUR; /*!< Address offset : 0x00000510 */ + __IO uint32_t PDR; /*!< Address offset : 0x00000514 */ + __IO uint32_t SLR; /*!< Address offset : 0x00000518 */ + __IO uint32_t DEN; /*!< Address offset : 0x0000051C */ + __IO uint32_t LOCK; /*!< Address offset : 0x00000520 */ + __IO uint32_t CR; /*!< Address offset : 0x00000524 */ + __IO uint32_t AMSEL; /*!< Address offset : 0x00000528 */ + __IO uint32_t PCTL; /*!< Address offset : 0x0000052C ! This register is not used in cc3xx. ! */ + __IO uint32_t ADCCTL; /*!< Address offset : 0x00000530 ! This register is not used in cc3xx. ! */ + __IO uint32_t DMACTL; /*!< Address offset : 0x00000534 */ + __IO uint32_t SI; /*!< Address offset : 0x00000538 */ + uint32_t RESERVED2[677]; + __IO uint32_t PERIPHID4; /*!< Address offset : 0x00000FD0 */ + __IO uint32_t PERIPHID5; /*!< Address offset : 0x00000FD4 */ + __IO uint32_t PERIPHID6; /*!< Address offset : 0x00000FD8 */ + __IO uint32_t PERIPHID7; /*!< Address offset : 0x00000FDC */ + __IO uint32_t PERIPHID0; /*!< Address offset : 0x00000FE0 */ + __IO uint32_t PERIPHID1; /*!< Address offset : 0x00000FE4 */ + __IO uint32_t PERIPHID2; /*!< Address offset : 0x00000FE8 */ + __IO uint32_t PERIPHID3; /*!< Address offset : 0x00000FEC */ + __IO uint32_t PCELLID0; /*!< Address offset : 0x00000FF0 */ + __IO uint32_t PCELLID1; /*!< Address offset : 0x00000FF4 */ + __IO uint32_t PCELLID2; /*!< Address offset : 0x00000FF8 */ + __IO uint32_t PCELLID3; /*!< Address offset : 0x00000FFC */ +} CC3220SF_GPIO_TypeDef; + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/** + * @brief UART + */ +typedef struct +{ + __IO uint32_t DR; /*!< Data, Address offset : 0x00 */ + union { + __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */ + __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */ + }; + uint32_t RESERVED0[4]; + __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */ + uint32_t RESERVED1[1]; + __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */ + __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */ + __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */ + __IO uint32_t LCRH; /*!< Line Control, Address offset : 0x2C */ + __IO uint32_t CTL; /*!< Control, Address offset : 0x30 */ + __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */ + __IO uint32_t IM; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */ + __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */ + __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */ + __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */ + __IO uint32_t DMACTL; /*!< DMA Control, Address offset : 0x48 */ + __IO uint32_t LCTL; /*!< Address offset : 0x90 */ + __IO uint32_t LSS; /*!< Address offset : 0x94 */ + __IO uint32_t LTIM; /*!< Address offset : 0x98 */ + __IO uint32_t BITADDR; /*!< 9BITADDR Address offset : 0xA4 */ + __IO uint32_t BITMASK; /*!< 9BITMASK Address offset : 0xA8 */ + __IO uint32_t PP; /*!< Address offset : 0xFC0 */ + __IO uint32_t CC; /*!< Address offset : 0xFC8 */ +} CC3220SF_UART_TypeDef; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/* Peripheral and SRAM base address */ +#define CC3220SF_FLASH_BASE 0x01000000 +#define CC3220SF_SRAM_BASE 0x20000000 +#define CC3220SF_WDT_BASE 0x40000000 +#define CC3220SF_GPIOA0_BASE 0x40004000 +#define CC3220SF_GPIOA1_BASE 0x40005000 +#define CC3220SF_GPIOA2_BASE 0x40006000 +#define CC3220SF_GPIOA3_BASE 0x40007000 +#define CC3220SF_GPIOA4_BASE 0x40024000 +#define CC3220SF_UARTA0_BASE 0x4000C000 +#define CC3220SF_UARTA1_BASE 0x4000D000 +#define CC3220SF_I2CA0_BASE 0x40020000 +#define CC3220SF_TIMERA0_BASE 0x40030000 +#define CC3220SF_TIMERA1_BASE 0x40031000 +#define CC3220SF_TIMERA2_BASE 0x40032000 +#define CC3220SF_TIMERA3_BASE 0x40033000 +#define CC3220SF_STACKDIE_CTRL_BASE 0x400F5000 +#define CC3220SF_COMMON_REG_BASE 0x400F7000 +#define CC3220SF_FLASH_CONTROL_BASE 0x400FD000 +#define CC3220SF_SYSTEM_CONTROL_BASE 0x400FE000 +#define CC3220SF_UDMA_BASE 0x400FF000 +#define CC3220SF_SDHOST_BASE 0x44010000 +#define CC3220SF_CAMERA_BASE 0x44018000 +#define CC3220SF_I2S_BASE 0x4401C000 +#define CC3220SF_SSPI_BASE 0x44020000 +#define CC3220SF_GSPI_BASE 0x44021000 +#define CC3220SF_LSPI_BASE 0x44022000 +#define CC3220SF_ARCM_BASE 0x44025000 +#define CC3220SF_APPS_CONFIG_BASE 0x44026000 +#define CC3220SF_GPRCM_BASE 0x4402D000 +#define CC3220SF_OCP_SHARED_BASE 0x4402E000 +#define CC3220SF_ADC_BASE 0x4402E800 +#define CC3220SF_HIB1P2_BASE 0x4402F000 +#define CC3220SF_HIB3P3_BASE 0x4402F800 +#define CC3220SF_DTHE_BASE 0x44030000 +#define CC3220SF_SHAMD5_BASE 0x44035000 +#define CC3220SF_AES_BASE 0x44037000 +#define CC3220SF_DES_BASE 0x44039000 + +/** + * @} + */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/******************************************************************************/ +/* */ +/* GPIO */ +/* */ +/******************************************************************************/ + +#define CC3220SF_GPIO0 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA0_BASE) +#define CC3220SF_GPIO1 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA1_BASE) +#define CC3220SF_GPIO2 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA2_BASE) +#define CC3220SF_GPIO3 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA3_BASE) +#define CC3220SF_GPIO4 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA4_BASE) + +/******************************************************************************/ +/* */ +/* UART */ +/* */ +/******************************************************************************/ + +#define CC3220SF_UART0 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA0_BASE) +#define CC3220SF_UART1 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA1_BASE) + + +/** + * @} + */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* CC3220SF_H */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.cpp new file mode 100755 index 00000000000..267980a3cab --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.cpp @@ -0,0 +1,160 @@ +/* CC3220SF_Init.cpp + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "nsapi_types.h" +#include "ti/drivers/net/wifi/netcfg.h" +#include "ti/drivers/ti_SPI.h" +#include "ti/drivers/dma/UDMACC32XX.h" +#include "ti/drivers/net/wifi/sl_socket.h" +#include "ti/drivers/net/wifi/netapp.h" +#include "ti/drivers/net/wifi/wlan.h" +#include "mbed.h" +#include "cc3200_simplelink.h" +#include "CC3220SF_Init.h" + +#define CHANNEL_MASK_ALL (0x1FFF) +#define RSSI_TH_MAX (-95) +#define TASK_STACK_SIZE (2048) + +/* The SimpleLink host driver architecture mandate spawn thread to be created prior to calling Sl_start (turning the NWP on). */ +/* The purpose of this thread is to handle asynchronous events sent from the NWP. + * Every event is classified and later handled by the Host driver event handlers. */ +Thread sl_Task_thread(osPriorityNormal, TASK_STACK_SIZE, NULL, "sl_task_thread"); +Mutex sl_init_mutex; + +void sl_task_entry() +{ + sl_Task(NULL); +} + +int CC3220SF_initSimplelink(void) +{ + uint8_t ucConfigOpt; + uint8_t ucPower; + int32_t RetVal = -1; + int32_t Mode = -1; + uint32_t IfBitmap = 0; + SlWlanScanParamCommand_t ScanDefault = {0}; + SlWlanRxFilterOperationCommandBuff_t RxFilterIdMask = {{0}}; + static bool simplelink_powered = false; + + sl_init_mutex.lock(); + if (!simplelink_powered) + { + if (sl_Task_thread.start(callback(sl_task_entry)) != osOK) + { + printf("sl_Task failed\n"); + sl_init_mutex.unlock(); + return -1; + } + UDMACC32XX_init(); + SPI_init(); + + /* Turn NWP on */ + Mode = sl_Start(0, 0, 0); + if(Mode != ROLE_STA) + { + /* Set NWP role as STA */ + RetVal = sl_WlanSetMode(ROLE_STA); + assert(RetVal == 0); + + /* For changes to take affect, we restart the NWP */ + RetVal = sl_Stop(0); + assert(RetVal == 0); + + Mode = sl_Start(0, 0, 0); + assert(RetVal == 0); + } + + if(Mode != ROLE_STA) + { + printf("Failed to configure device to it's default state"); + sl_init_mutex.unlock(); + return -1; + } + + /* Set policy to auto only */ + RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION, SL_WLAN_CONNECTION_POLICY(1,0,0,0), NULL ,0); + assert(RetVal == 0); + + /* Disable Auto Provisioning */ + RetVal = sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP, 0xFF, 0, NULL, 0x0); + assert(RetVal == 0); + + /* Delete existing profiles */ + RetVal = sl_WlanProfileDel(0xFF); + assert(RetVal == 0); + + /* enable DHCP client */ + RetVal = sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_DHCP, 0, 0); + assert(RetVal == 0); + + /* Disable ipv6 */ + IfBitmap = !(SL_NETCFG_IF_IPV6_STA_LOCAL | SL_NETCFG_IF_IPV6_STA_GLOBAL); + RetVal = sl_NetCfgSet(SL_NETCFG_IF, SL_NETCFG_IF_STATE, sizeof(IfBitmap),(const unsigned char *)&IfBitmap); + assert(RetVal == 0); + + /* Configure scan parameters to default */ + ScanDefault.ChannelsMask = CHANNEL_MASK_ALL; + ScanDefault.RssiThreshold = RSSI_TH_MAX; + + RetVal = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS, sizeof(ScanDefault), (uint8_t *)&ScanDefault); + assert(RetVal == 0); + + /* Disable scans */ + ucConfigOpt = SL_WLAN_SCAN_POLICY(0, 0); + RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_SCAN , ucConfigOpt, NULL, 0); + assert(RetVal == 0); + + /* Set TX power lvl to max */ + ucPower = 0; + RetVal = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER, 1, (uint8_t *)&ucPower); + assert(RetVal == 0); + + /* Set NWP Power policy to 'normal' */ + RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_PM, SL_WLAN_NORMAL_POLICY, NULL, 0); + assert(RetVal == 0); + + /* Unregister mDNS services */ + RetVal = sl_NetAppMDNSUnRegisterService(0, 0, 0); + assert(RetVal == 0); + + /* Remove all 64 RX filters (8*8) */ + memset(RxFilterIdMask.FilterBitmap , 0xFF, 8); + + RetVal = sl_WlanSet(SL_WLAN_RX_FILTERS_ID, SL_WLAN_RX_FILTER_REMOVE, sizeof(SlWlanRxFilterOperationCommandBuff_t),(uint8_t *)&RxFilterIdMask); + assert(RetVal == 0); + + /* Set NWP role as STA */ + RetVal = sl_WlanSetMode(ROLE_STA); + assert(RetVal == 0); + + /* For changes to take affect, we restart the NWP */ + RetVal = sl_Stop(0/*SL_STOP_TIMEOUT*/); + assert(RetVal == 0); + + Mode = sl_Start(0, 0, 0); + if(ROLE_STA != Mode) + { + printf("Failed to configure device to its default state\n"); + sl_init_mutex.unlock(); + return -1; + } + simplelink_powered = true; + } + sl_init_mutex.unlock(); + return 0; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.h new file mode 100755 index 00000000000..1a577dba3ba --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.h @@ -0,0 +1,30 @@ +/* CC3220SF_Init.h + * + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CC3220SF_INIT_H +#define __CC3220SF_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +int CC3220SF_initSimplelink(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CC3220SF_INIT_H */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp new file mode 100644 index 00000000000..ac3703e48a5 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp @@ -0,0 +1,674 @@ +/* CC3220SF implementation of NetworkInterfaceAPI + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cc3200_simplelink.h" +#include "CC3220SF_WiFiInterface.h" + +#define CONNECT_TIMEOUT_MS (4000) +#define IP_SET_TIMEOUT_MS (2000) +#define READ_THREAD_SLEEP_MS (50) +#define SOCKET_TASK_STACK_SIZE (2048) + +CC3220SFInterface * CC3220SFInterface::cc3200sf_wifi_instance; + +CC3220SFInterface::CC3220SFInterface(): + _thread_read_socket(osPriorityNormal, SOCKET_TASK_STACK_SIZE, NULL, "read_socket_thread"), + _initialized(false), + _started(false), + _channel(6), + _connect_sem(0, 1), + _ip_set_sem(0, 1) +{ + memset(_id_in_use, 0, sizeof(_id_in_use)); + memset(_socket_obj, 0, sizeof(_socket_obj)); + memset(_cbs, 0, sizeof(_cbs)); + memset(_ssid, 0, sizeof(_ssid)); + memset(_pass, 0, sizeof(_pass)); + _security = NSAPI_SECURITY_UNKNOWN; + cc3200sf_wifi_instance = this; + _cc3200_simplelink.initialize(); + _thread_read_socket.start(callback(this, &CC3220SFInterface::_socket_background_thread)); +} + +nsapi_error_t CC3220SFInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, + uint8_t channel) +{ + nsapi_error_t ret_code; + + ret_code = set_credentials(ssid, pass, security); + if(ret_code) + { + printf ("set_credentials failed with 0x%x\n", ret_code); + return ret_code; + } + + return connect(); +} + +nsapi_error_t CC3220SFInterface::connect() +{ + nsapi_error_t status; + + if (strlen(_ssid) == 0) + { + return NSAPI_ERROR_NO_SSID; + } + + if(get_ip_address()) + { + return NSAPI_ERROR_IS_CONNECTED; + } + + _cc3200_simplelink.set_connection_status(NSAPI_STATUS_CONNECTING); + + status = _startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION); + if(status != NSAPI_ERROR_OK) + { + return status; + } + _started = true; + + if (!_cc3200_simplelink.dhcp(true, CC3200_SIMPLELINK::WIFI_ROLE_STATION)) + { + return NSAPI_ERROR_DHCP_FAILURE; + } + int connect_error = _cc3200_simplelink.connect(_ssid, _pass, _security); + if (connect_error) + { + return connect_error; + } + + // Connect is async call. Wait till connection completes + if (_connect_sem.try_acquire_for(CONNECT_TIMEOUT_MS) == false) + { + printf("Connection timed out\n"); + return NSAPI_ERROR_CONNECTION_TIMEOUT; + } + if (_ip_set_sem.try_acquire_for(IP_SET_TIMEOUT_MS) == false) + { + printf("IP address set timed out\n"); + } + else + { + _cc3200_simplelink.set_connection_status(NSAPI_STATUS_GLOBAL_UP); + } + + if (!get_ip_address()) + { + return NSAPI_ERROR_DHCP_FAILURE; + } + + return NSAPI_ERROR_OK; +} + +nsapi_error_t CC3220SFInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) +{ + if (!ssid) { + return NSAPI_ERROR_PARAMETER; + } + + if ((strlen(ssid) == 0) || (strlen(ssid) > 32)) { + return NSAPI_ERROR_PARAMETER; + } + + if ((security != NSAPI_SECURITY_NONE) && (strcmp(pass, "") == 0)) { + return NSAPI_ERROR_PARAMETER; + } + + switch (security) + { + case NSAPI_SECURITY_WPA: + case NSAPI_SECURITY_WPA2: + case NSAPI_SECURITY_WPA_WPA2: + case NSAPI_SECURITY_WEP: + if ((strlen(pass) < 8) || (strlen(pass) > 63)) { // 802.11 password 8-63 characters + return NSAPI_ERROR_PARAMETER; + } + break; + case NSAPI_SECURITY_NONE: + break; + default: + return NSAPI_ERROR_PARAMETER; + } + + if (security != NSAPI_SECURITY_NONE) + { + if(!pass) + { + return NSAPI_ERROR_PARAMETER; + } + } + + strncpy(_ssid, ssid, sizeof(_ssid)); + strncpy(_pass, pass, sizeof(_pass)); + _security = security; + + return NSAPI_ERROR_OK; +} + +nsapi_error_t CC3220SFInterface::set_channel(uint8_t channel) +{ + return NSAPI_ERROR_UNSUPPORTED; +} + +nsapi_error_t CC3220SFInterface::disconnect() +{ + nsapi_error_t status; + + _started = false; + _initialized = false; + + if (_cc3200_simplelink.disconnect()) + { + status = NSAPI_ERROR_OK; + _cc3200_simplelink.set_connection_status(NSAPI_STATUS_DISCONNECTED); + } + else + { + status = NSAPI_ERROR_DEVICE_ERROR; + } + return status; +} + +const char *CC3220SFInterface::get_ip_address() +{ + if(!_started) { + return NULL; + } + + const char *ip_buff = _cc3200_simplelink.getIPAddress(); + if(!ip_buff || std::strcmp(ip_buff, "0.0.0.0") == 0) { + return NULL; + } + + return ip_buff; +} + +const char *CC3220SFInterface::get_mac_address() +{ + return _cc3200_simplelink.getMACAddress(); +} + +const char *CC3220SFInterface::get_gateway() +{ + return _started ? _cc3200_simplelink.getGateway() : NULL; +} + +const char *CC3220SFInterface::get_netmask() +{ + return _started ? _cc3200_simplelink.getNetmask() : NULL; +} + +int8_t CC3220SFInterface::get_rssi() +{ + return _started ? _cc3200_simplelink.getRSSI() : 0; +} + +int CC3220SFInterface::scan(WiFiAccessPoint *res, unsigned count) +{ + nsapi_error_t status; + + status = _startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION); + if(status != NSAPI_ERROR_OK) { + return status; + } + + return _cc3200_simplelink.scan(res, count); +} + +nsapi_error_t CC3220SFInterface::_startup(const int8_t wifi_mode) +{ + if (!_started) { + if (!_cc3200_simplelink.startup(wifi_mode)) { + return NSAPI_ERROR_DEVICE_ERROR; + } + } + return NSAPI_ERROR_OK; +} + +void CC3220SFInterface::attach(mbed::Callback status_cb) +{ + _cc3200_simplelink.attach(status_cb); +} + +nsapi_connection_status_t CC3220SFInterface::get_connection_status() const +{ + return _cc3200_simplelink.get_connection_status(); +} + +nsapi_error_t CC3220SFInterface::socket_open(void **handle, nsapi_protocol_t proto) +{ + int32_t sd, i, ret = NSAPI_ERROR_PARAMETER; + + if (!handle) + { + return ret; + } + + _mutex.lock(); + for (i = 0; i < CC3220SF_SOCKET_COUNT; i++) { + if (_id_in_use[i] == false) + { + _id_in_use[i] = true; + break; + } + } + + if (i == CC3220SF_SOCKET_COUNT) { + _mutex.unlock(); + return NSAPI_ERROR_NO_SOCKET; + } + + struct cc3200_socket *socket = new struct cc3200_socket; + if (!socket) + { + _mutex.unlock(); + return NSAPI_ERROR_NO_SOCKET; + } + + sd = _cc3200_simplelink.open_socket(proto); + if (sd >= 0) // socket open succeeded + { + socket->id = i; + socket->sd = sd; + socket->proto = proto; + socket->connected = false; + socket->read_data_available = 0; + socket->data_to_read = 0; + socket->callback_pending = false; + *handle = socket; + _socket_obj[i] = (void *)socket; + ret = NSAPI_ERROR_OK; + } + else + { + delete socket; + *handle = NULL; + ret = NSAPI_ERROR_NO_SOCKET; + } + _mutex.unlock(); + return ret; +} + +nsapi_error_t CC3220SFInterface::socket_close(void *handle) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + int err = NSAPI_ERROR_OK; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + _mutex.lock(); + if (!_cc3200_simplelink.close_socket(socket->sd)) + { + err = NSAPI_ERROR_DEVICE_ERROR; + } + socket->connected = false; + socket->callback_pending = false; + _id_in_use[socket->id] = false; + _socket_obj[socket->id] = 0; + _mutex.unlock(); + delete socket; + return err; +} + +#if 0 +nsapi_error_t CC3220SFInterface::gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version) +{ + nsapi_addr_t ip_address; + ip_address.version = NSAPI_IPv4; + if (_cc3200_simplelink.dns_lookup(name, (char*)ip_address.bytes, sizeof(ip_address.bytes), version) == NSAPI_ERROR_OK) + { + address->set_addr(ip_address); + return NSAPI_ERROR_OK; + } + else + { + return NSAPI_ERROR_DNS_FAILURE; + } +} +#endif + +nsapi_error_t CC3220SFInterface::get_dns_server(int index, SocketAddress *address, const char *interface_name) +{ + nsapi_addr_t dns_address; + dns_address.version = NSAPI_IPv4; + if (_cc3200_simplelink.getDNS(dns_address.bytes, sizeof(dns_address.bytes)) == NSAPI_ERROR_OK) + { + address->set_addr(dns_address); + return NSAPI_ERROR_OK; + } + else + { + return NSAPI_ERROR_DNS_FAILURE; + } +} + +nsapi_error_t CC3220SFInterface::setsockopt(nsapi_socket_t handle, int level, + int optname, const void *optval, unsigned optlen) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (!socket) + { + return NSAPI_ERROR_NO_SOCKET; + } + _mutex.lock(); + nsapi_error_t retcode = _cc3200_simplelink.setsockopt(socket->sd, level, optname, optval, optlen); + _mutex.unlock(); + return retcode; +} + +nsapi_error_t CC3220SFInterface::getsockopt(nsapi_socket_t handle, int level, int optname, + void *optval, unsigned *optlen) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (!socket) + { + return NSAPI_ERROR_NO_SOCKET; + } + _mutex.lock(); + nsapi_error_t retcode = _cc3200_simplelink.getsockopt(socket->sd, level, optname, optval, optlen); + _mutex.unlock(); + + return retcode; +} + +int CC3220SFInterface::socket_bind(void *handle, const SocketAddress &address) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (!socket) + { + return NSAPI_ERROR_NO_SOCKET; + } + + _mutex.lock(); + + int ret = _cc3200_simplelink.bind_socket(socket->sd, address); + _mutex.unlock(); + return ret; +} + +int CC3220SFInterface::socket_listen(void *handle, int backlog) +{ + return NSAPI_ERROR_UNSUPPORTED; +} + +int CC3220SFInterface::socket_connect(void *handle, const SocketAddress &addr) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (!socket) + { + return NSAPI_ERROR_NO_SOCKET; + } + _mutex.lock(); + + int ret; + if (_cc3200_simplelink.connect_socket(socket->sd, addr) == NSAPI_ERROR_OK) + { + socket->connected= true; + ret = NSAPI_ERROR_OK; + } + else + { + printf("socket_connect failed\n"); + ret = NSAPI_ERROR_DEVICE_ERROR; + } + _mutex.unlock(); + return ret; +} + +int CC3220SFInterface::socket_accept(void *handle, void **socket, SocketAddress *address) +{ + // TODO + return NSAPI_ERROR_UNSUPPORTED; +} + +int CC3220SFInterface::socket_send(void *handle, const void *data, unsigned size) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (!socket) + { + return NSAPI_ERROR_NO_SOCKET; + } + _mutex.lock(); + int ret = _cc3200_simplelink.send(socket->sd, data, size); + if (ret > 0) + { + socket->callback_pending = true; + } + _mutex.unlock(); + + return ret; +} + +int CC3220SFInterface::socket_recv(void *handle, void *data, unsigned size) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (!socket) + { + return NSAPI_ERROR_NO_SOCKET; + } + _mutex.lock(); + socket->data_to_read = size; + int ret = _socket_receive_data(socket, data); + _mutex.unlock(); + + return ret; +} + +int CC3220SFInterface::socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned size) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (!socket) + { + return NSAPI_ERROR_NO_SOCKET; + } + + _mutex.lock(); + // Sending a datagram of length 0 is OK + int ret = _cc3200_simplelink.sendto_socket(socket->sd, data, size, address); + + if (ret >= 0) + { + socket->callback_pending = true; + } + _mutex.unlock(); + + return ret; +} + +int CC3220SFInterface::socket_recvfrom(void *handle, SocketAddress *address, void *buffer, unsigned size) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (!socket) + { + return NSAPI_ERROR_NO_SOCKET; + } + + _mutex.lock(); + // It's okay to receive 0 for a datagram protocol. Unlike TCP, it doesn't mean the peer has closed the connection. + socket->data_to_read = size; + int ret = _socket_receive_data(socket, buffer); + if (ret >= 0 && address) + { + *address = socket->addr; + } + _mutex.unlock(); + + return ret; +} + +void CC3220SFInterface::socket_attach(void *handle, void (*callback)(void *), void *data) +{ + struct cc3200_socket *socket = (struct cc3200_socket *)handle; + if (socket) + { + _mutex.lock(); + _cbs[socket->id].callback = callback; + _cbs[socket->id].data = data; + _mutex.unlock(); + } +} + +void CC3220SFInterface::_socket_background_thread() +{ + while (1) + { + for (int i = 0; i < CC3220SF_SOCKET_COUNT; i++) + { + _mutex.lock(); + if (_socket_obj[i]) + { + struct cc3200_socket *socket = (struct cc3200_socket *)_socket_obj[i]; + /* Check if an async event needs to be sent*/ + if ((socket->callback_pending) && _cbs[socket->id].callback) + { + _cbs[socket->id].callback(_cbs[socket->id].data); + socket->callback_pending = false; + } + /* Check if there is something to read for this socket. But if it */ + /* has already been read : don't read again */ + if ((socket->read_data_available == 0) && (socket->data_to_read) && _cbs[socket->id].callback) + { + int read_amount, bytes_to_receive = socket->data_to_read; + if (bytes_to_receive > MAX_RECV_PACKET_SIZE) + { + bytes_to_receive = MAX_RECV_PACKET_SIZE; + } + if (socket->proto == NSAPI_UDP) + { + read_amount = _cc3200_simplelink.recvfrom(socket->sd, socket->read_data_internal_buffer, bytes_to_receive, socket->addr); + } + else + { + read_amount= _cc3200_simplelink.recv(socket->sd, socket->read_data_internal_buffer, bytes_to_receive); + } + //printf("background receive %d %d\n", bytes_to_receive, read_amount); + if (read_amount > 0) + { + socket->read_data_available = read_amount; + // For UDP packet, no packet fragmentation, so none or all + if (socket->proto == NSAPI_UDP) + { + socket->data_to_read = 0; + } + else + { + socket->data_to_read -= read_amount; + } + } + else if ((read_amount < 0 && read_amount != NSAPI_ERROR_WOULD_BLOCK) || (read_amount == 0)) + { + /* Mark connection has been lost or closed */ + printf("Connection lost\n"); + socket->connected = false; + socket->data_to_read = 0; + } + + if (read_amount >= 0) + { + /* There is something to read in this socket*/ + _cbs[socket->id].callback(_cbs[socket->id].data); + } + } + } + _mutex.unlock(); + } + wait_ms(READ_THREAD_SLEEP_MS); + } +} + +// This function is expected to run with mutex protection +int CC3220SFInterface::_socket_receive_data(void *obj, void *data) +{ + int recv = 0; + char *ptr = (char *)data; + int bytes_to_receive = 0; + + cc3200_socket *socket = (cc3200_socket *)obj; + + if (socket->read_data_available == 0) + { + // Need to receive + int read_amount; + + // Simplelink can receive up to MAX_RECV_PACKET_SIZE + bytes_to_receive = socket->data_to_read; + if (bytes_to_receive > MAX_RECV_PACKET_SIZE) + { + bytes_to_receive = MAX_RECV_PACKET_SIZE; + } + if (socket->proto == NSAPI_UDP) // TODO: is this good enough to distinguish recvfrom and recv? + { + read_amount = _cc3200_simplelink.recvfrom(socket->sd, socket->read_data_internal_buffer, bytes_to_receive, socket->addr); + } + else + { + read_amount= _cc3200_simplelink.recv(socket->sd, socket->read_data_internal_buffer, bytes_to_receive); + } + //printf("foreground receive %d %d\n", bytes_to_receive, read_amount); + if (read_amount == 0) + { + // No data to read + socket->data_to_read = 0; + return 0; + } + if (read_amount > 0) + { + socket->read_data_available = read_amount; + } + else // read_amount < 0 + { + if (read_amount == NSAPI_ERROR_WOULD_BLOCK) + { + return NSAPI_ERROR_WOULD_BLOCK; + } + else + { + socket->connected = false; + printf("connection lost\n"); + socket->data_to_read = 0; + return NSAPI_ERROR_CONNECTION_LOST; + } + } + } + if (socket->read_data_available > 0) + { + // Data has been received or there's already data waiting to be copied into the buffer provided + uint32_t i = 0; + while (i < socket->read_data_available) + { + *ptr++ = socket->read_data_internal_buffer[i]; + i++; + } + recv += i; + + /* All the stored data has been read, reset buffer */ + memset(socket->read_data_internal_buffer, 0, sizeof(socket->read_data_internal_buffer)); + // For UDP packet, no packet fragmentation, so none or all + if (socket->proto == NSAPI_UDP) + { + socket->data_to_read = 0; + } + else + { + socket->data_to_read -= socket->read_data_available; + } + socket->read_data_available = 0; + } + return recv; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.h new file mode 100644 index 00000000000..8b14a9231e6 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.h @@ -0,0 +1,373 @@ +/* CC3220 implementation of NetworkInterfaceAPI + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef CC3220SF_INTERFACE_H +#define CC3220SF_INTERFACE_H + +#include "mbed.h" +#include "cc3200_simplelink.h" + +#define CC3220SF_SOCKET_COUNT (MAX_CONCURRENT_ACTIONS) +#define MAX_RECV_PACKET_SIZE (1544) + +/** TI (CC3220SF) interface class + * Implementation of the NetworkStack for TI CC3200 Simplelink stack + */ +class CC3220SFInterface: public NetworkStack, public WiFiInterface +{ +public: + /** + * @brief CC3220SFInterface default constructor + */ + + CC3220SFInterface(); + + /** Start the interface + * @return 0 on success, negative on failure + */ + virtual nsapi_error_t connect(); + + /** Start the interface + * + * Attempts to connect to a WiFi network. + * + * @param ssid Name of the network to connect to + * @param pass Security passphrase to connect to the network + * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) + * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) + * @return 0 on success, or error code on failure + */ + virtual nsapi_error_t connect(const char *ssid, const char *pass, + nsapi_security_t security = NSAPI_SECURITY_NONE, + uint8_t channel = 0); + + /** Set the WiFi network credentials + * + * @param ssid Name of the network to connect to + * @param pass Security passphrase to connect to the network + * @param security Type of encryption for connection + * (defaults to NSAPI_SECURITY_NONE) + * @return 0 on success, or error code on failure + */ + virtual nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); + + /** Set the WiFi network channel + * + * + * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) + * @return 0 on success, or error code on failure + */ + virtual nsapi_error_t set_channel(uint8_t channel); + + /** Stop the interface + * @return 0 on success, negative on failure + */ + virtual int disconnect(); + + /** Set a static IP address + * + * Configures this network interface to use a static IP address. + * Implicitly disables DHCP, which can be enabled in set_dhcp. + * Requires that the network is disconnected. + * + * @param address Null-terminated representation of the local IP address + * @param netmask Null-terminated representation of the local network mask + * @param gateway Null-terminated representation of the local gateway + * @return 0 on success, negative error code on failure + */ + //virtual nsapi_error_t set_network(const char *ip_address, const char *netmask, const char *gateway); + + /** Enable or disable DHCP on the network + * + * Requires that the network is disconnected + * + * @param dhcp False to disable dhcp (defaults to enabled) + * @return 0 on success, negative error code on failure + */ + //virtual nsapi_error_t set_dhcp(bool dhcp); + + /** Get the internally stored IP address + * @return IP address of the interface or null if not yet connected + */ + virtual const char *get_ip_address(); + + /** Get the internally stored MAC address + * @return MAC address of the interface + */ + virtual const char *get_mac_address(); + + /** Get the local gateway + * + * @return Null-terminated representation of the local gateway + * or null if no network mask has been recieved + */ + virtual const char *get_gateway(); + + /** Get the local network mask + * + * @return Null-terminated representation of the local network mask + * or null if no network mask has been recieved + */ + virtual const char *get_netmask(); + + /** Gets the current radio signal strength for active connection + * + * @return Connection strength in dBm (negative value) + */ + virtual int8_t get_rssi(); + + /** Scan for available networks + * + * The scan will + * If the network interface is set to non-blocking mode, scan will attempt to scan + * for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback + * is attached, the callback will be called when the operation has completed. + * @param res Pointer to allocated array to store discovered AP + * @param count Size of allocated @a res array, or 0 to only count available AP + * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error + * see @a nsapi_error + */ + virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, unsigned count); + + + /** Translates a hostname to an IP address with specific version + * + * The hostname may be either a domain name or an IP address. If the + * hostname is an IP address, no network transactions will be performed. + * + * If no stack-specific DNS resolution is provided, the hostname + * will be resolve using a UDP socket on the stack. + * + * @param address Destination for the host SocketAddress + * @param host Hostname to resolve + * @param version IP version of address to resolve, NSAPI_UNSPEC indicates + * version is chosen by the stack (defaults to NSAPI_UNSPEC) + * @return 0 on success, negative error code on failure + */ + using NetworkInterface::gethostbyname; + //virtual nsapi_error_t gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version); + + /** Add a domain name server to list of servers to query + * + * @param addr Destination for the host address + * @return 0 on success, negative error code on failure + */ + using NetworkInterface::add_dns_server; + + virtual nsapi_error_t get_dns_server(int index, SocketAddress *address, const char* interface_name = NULL); + + /** Set socket options + * + * The setsockopt allow an application to pass stack-specific hints + * to the underlying stack. For unsupported options, + * NSAPI_ERROR_UNSUPPORTED is returned and the socket is unmodified. + * + * @param handle Socket handle + * @param level Stack-specific protocol level + * @param optname Stack-specific option identifier + * @param optval Option value + * @param optlen Length of the option value + * @return 0 on success, negative error code on failure + */ + virtual nsapi_error_t setsockopt(nsapi_socket_t handle, int level, + int optname, const void *optval, unsigned optlen); + + /** Get socket options + * + * getsockopt allows an application to retrieve stack-specific options + * from the underlying stack using stack-specific level and option names, + * or to request generic options using levels from nsapi_socket_level_t. + * + * For unsupported options, NSAPI_ERROR_UNSUPPORTED is returned + * and the socket is unmodified. + * + * @param level Stack-specific protocol level or nsapi_socket_level_t + * @param optname Level-specific option name + * @param optval Destination for option value + * @param optlen Length of the option value + * @return 0 on success, negative error code on failure + */ + virtual nsapi_error_t getsockopt(nsapi_socket_t handle, int level, int optname, + void *optval, unsigned *optlen); + + /** Register callback for status reporting + * + * The specified status callback function will be called on status changes + * on the network. The parameters on the callback are the event type and + * event-type dependent reason parameter. + * + * @param status_cb The callback for status changes + */ + virtual void attach(mbed::Callback status_cb); + + /** Get the connection status + * + * @return The connection status according to ConnectionStatusType + */ + virtual nsapi_connection_status_t get_connection_status() const; + +protected: + /** Open a socket + * @param handle Handle in which to store new socket + * @param proto Type of socket to open, NSAPI_TCP or NSAPI_UDP + * @return 0 on success, negative on failure + */ + virtual int socket_open(void **handle, nsapi_protocol_t proto); + + /** Close the socket + * @param handle Socket handle + * @return 0 on success, negative on failure + * @note On failure, any memory associated with the socket must still + * be cleaned up + */ + virtual int socket_close(void *handle); + + /** Bind a server socket to a specific port + * @param handle Socket handle + * @param address Local address to listen for incoming connections on + * @return 0 on success, negative on failure. + */ + virtual int socket_bind(void *handle, const SocketAddress &address); + + /** Start listening for incoming connections + * @param handle Socket handle + * @param backlog Number of pending connections that can be queued up at any + * one time [Default: 1] + * @return 0 on success, negative on failure + */ + virtual int socket_listen(void *handle, int backlog); + + /** Connects this TCP socket to the server + * @param handle Socket handle + * @param address SocketAddress to connect to + * @return 0 on success, negative on failure + */ + virtual int socket_connect(void *handle, const SocketAddress &address); + + /** Accept a new connection. + * @param handle Handle in which to store new socket + * @param server Socket handle to server to accept from + * @return 0 on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_accept(void *handle, void **socket, SocketAddress *address); + + /** Send data to the remote host + * @param handle Socket handle + * @param data The buffer to send to the host + * @param size The length of the buffer to send + * @return Number of written bytes on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_send(void *handle, const void *data, unsigned size); + + /** Receive data from the remote host + * @param handle Socket handle + * @param data The buffer in which to store the data received from the host + * @param size The maximum length of the buffer + * @return Number of received bytes on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_recv(void *handle, void *data, unsigned size); + + /** Send a packet to a remote endpoint + * @param handle Socket handle + * @param address The remote SocketAddress + * @param data The packet to be sent + * @param size The length of the packet to be sent + * @return The number of written bytes on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned size); + + /** Receive a packet from a remote endpoint + * @param handle Socket handle + * @param address Destination for the remote SocketAddress or null + * @param buffer The buffer for storing the incoming packet data + * If a packet is too long to fit in the supplied buffer, + * excess bytes are discarded + * @param size The length of the buffer + * @return The number of received bytes on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_recvfrom(void *handle, SocketAddress *address, void *buffer, unsigned size); + + /** Register a callback on state change of the socket + * @param handle Socket handle + * @param callback Function to call on state change + * @param data Argument to pass to callback + * @note Callback may be called in an interrupt context. + */ + virtual void socket_attach(void *handle, void (*callback)(void *), void *data); + + /** Provide access to the NetworkStack object + * + * @return The underlying NetworkStack object + */ + virtual NetworkStack *get_stack() + { + return this; + } + +private: + static const int CC3220SF_SSID_MAX_LENGTH = 32; /* 32 is what 802.11 defines as longest possible name */ + static const int CC3220SF_PASSPHRASE_MAX_LENGTH = 63; /* The longest allowed passphrase */ + static const int CC3220SF_PASSPHRASE_MIN_LENGTH = 8; /* The shortest allowed passphrase */ + + struct { + void (*callback)(void *); + void *data; + } _cbs[CC3220SF_SOCKET_COUNT]; + + struct cc3200_socket { + int id; + int sd; + nsapi_protocol_t proto; + volatile bool connected; + char read_data_internal_buffer[MAX_RECV_PACKET_SIZE]; + volatile uint32_t read_data_available; + uint32_t data_to_read; + bool callback_pending; + SocketAddress addr; + }; + bool _id_in_use[CC3220SF_SOCKET_COUNT]; + void * _socket_obj[CC3220SF_SOCKET_COUNT]; // store addresses of socket handles + Mutex _mutex; + Thread _thread_read_socket; + CC3200_SIMPLELINK _cc3200_simplelink; + int _initialized; + int _started; + char _ssid[CC3220SF_SSID_MAX_LENGTH + 1]; /* 32 is what 802.11 defines as longest possible name; +1 for the \0 */ + nsapi_security_t _security; + uint8_t _channel; + char _pass[CC3220SF_PASSPHRASE_MAX_LENGTH + 1]; + + void _socket_background_thread(); + int _socket_receive_data(void *obj, void *data); + nsapi_error_t _init(void); + nsapi_error_t _startup(const int8_t wifi_mode); + Semaphore _connect_sem; + Semaphore _ip_set_sem; + static CC3220SFInterface * cc3200sf_wifi_instance; + friend void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent); + friend void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent); +}; +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/CC3220SF.sct b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/CC3220SF.sct new file mode 100644 index 00000000000..f015722ed09 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/CC3220SF.sct @@ -0,0 +1,104 @@ +#! armcc -E + +/* Device specific values */ +#define ROM_START 0x01000000 +#define ROM_SIZE 0x100000 +#define FLASH_HDR_START ROM_START +#define FLASH_HDR_SIZE 0x800 +#define RAM_START 0x20000000 +#define RAM_SIZE 0x40000 +#define VECTORS 195 /* This value must match NVIC_NUM_VECTORS */ + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((VECTORS * 4) + 7) & ~7) + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define Stack_Size MBED_BOOT_STACK_SIZE + +#if defined(MBED_APP_START) + /* + * There're two cases if MBED_APP_START is defined. + * Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build. + * In this build, include FLASH_HDR region. + */ + #define FLASH_HDR_INCLUDED 1 + + #if MBED_APP_START == ROM_START + #if defined(MBED_APP_SIZE) + #define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE) + #define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE) + #endif + #else + /* + * Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build. + * In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area + */ + #undef FLASH_HDR_INCLUDED + #define FLASH_HDR_INCLUDED 0 + #define ROM_EXEC_START MBED_APP_START + #if defined(MBED_APP_SIZE) + #define ROM_EXEC_SIZE MBED_APP_SIZE + #else + #define ROM_EXEC_SIZE (ROM_SIZE- (MBED_APP_START - ROM_START)) + #endif + #endif +#else + /* + * MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader. + * In this build, include FLASH_HDR region + */ + #define FLASH_HDR_INCLUDED 1 + #define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE) + #if defined(MBED_APP_SIZE) + #define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE) + #else + #define ROM_EXEC_SIZE (ROM_SIZE - FLASH_HDR_SIZE) + #endif +#endif + + +#if FLASH_HDR_INCLUDED == 1 +;#warning include cookie +LR_IROM1 ROM_START ROM_SIZE { + + ER_FLASH FLASH_HDR_START FLASH_HDR_SIZE { + *(signature_section, +Last) + } + + ER_IROM1 ROM_EXEC_START FIXED { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ;RW_IRAM1 (RAM_START + VECTORS_SIZE) (RAM_SIZE - VECTORS_SIZE) { ; RW data + RW_IRAM1 (0x20000000+0x308) (0x00040000-0x308) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -Stack_Size { ; stack + } +} +#else +;#warning exclude cookie +LR_IROM1 ROM_EXEC_START ROM_EXEC_SIZE { + + ER_IROM1 ROM_EXEC_START ROM_EXEC_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ;RW_IRAM1 (RAM_START + VECTORS_SIZE) (RAM_SIZE - VECTORS_SIZE) { ; RW data + RW_IRAM1 (0x20000000+0x308) (0x00040000-0x308) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_STACK (RAM_START + RAM_SIZE) EMPTY -Stack_Size { ; stack + } +} +#endif + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/startup_CC3220SF.S b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/startup_CC3220SF.S new file mode 100644 index 00000000000..9cb74756c46 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/startup_CC3220SF.S @@ -0,0 +1,371 @@ +;/* +; * Copyright (c) 2018-2019 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + +__initial_sp EQU 0x20040000 ; Top of RAM + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT_GPIOA0_IRQHandler ; /* 16 */ + DCD INT_GPIOA1_IRQHandler ; /* 17 */ + DCD INT_GPIOA2_IRQHandler ; /* 18 */ + DCD INT_GPIOA3_IRQHandler ; /* 19 */ + DCD 0 ; /* 20 Reserved interrupt */ + DCD INT_UARTA0_IRQHandler ; /* 21 */ + DCD INT_UARTA1_IRQHandler ; /* 22 */ + DCD 0 ; /* 23 Reserved interrupt */ + DCD INT_I2CA0_IRQHandler ; /* 24 */ + DCD 0 ; /* 25 Reserved interrupt */ + DCD 0 ; /* 26 Reserved interrupt */ + DCD 0 ; /* 27 Reserved interrupt */ + DCD 0 ; /* 28 Reserved interrupt */ + DCD 0 ; /* 29 Reserved interrupt */ + DCD INT_ADCCH0_IRQHandler ; /* 30 */ + DCD INT_ADCCH1_IRQHandler ; /* 31 */ + DCD INT_ADCCH2_IRQHandler ; /* 32 */ + DCD INT_ADCCH3_IRQHandler ; /* 33 */ + DCD INT_WDT_IRQHandler ; /* 34 */ + DCD INT_TIMERA0A_IRQHandler ; /* 35 */ + DCD INT_TIMERA0B_IRQHandler ; /* 36 */ + DCD INT_TIMERA1A_IRQHandler ; /* 37 */ + DCD INT_TIMERA1B_IRQHandler ; /* 38 */ + DCD INT_TIMERA2A_IRQHandler ; /* 39 */ + DCD INT_TIMERA2B_IRQHandler ; /* 40 */ + DCD 0 ; /* 41 Reserved interrupt */ + DCD 0 ; /* 42 Reserved interrupt */ + DCD 0 ; /* 43 Reserved interrupt */ + DCD 0 ; /* 44 Reserved interrupt */ + DCD INT_FLASH_IRQHandler ; /* 45 */ + DCD 0 ; /* 46 Reserved interrupt */ + DCD 0 ; /* 47 Reserved interrupt */ + DCD 0 ; /* 48 Reserved interrupt */ + DCD 0 ; /* 49 Reserved interrupt */ + DCD 0 ; /* 50 Reserved interrupt */ + DCD INT_TIMERA3A_IRQHandler ; /* 51 */ + DCD INT_TIMERA3B_IRQHandler ; /* 52 */ + DCD 0 ; /* 53 Reserved interrupt */ + DCD 0 ; /* 54 Reserved interrupt */ + DCD 0 ; /* 55 Reserved interrupt */ + DCD 0 ; /* 56 Reserved interrupt */ + DCD 0 ; /* 57 Reserved interrupt */ + DCD 0 ; /* 58 Reserved interrupt */ + DCD 0 ; /* 59 Reserved interrupt */ + DCD 0 ; /* 60 Reserved interrupt */ + DCD 0 ; /* 61 Reserved interrupt */ + DCD INT_UDMA_IRQHandler ; /* 62 */ + DCD INT_UDMAERR_IRQHandler ; /* 63 */ + DCD 0 ; /* 64 Reserved interrupt */ + DCD 0 ; /* 65 Reserved interrupt */ + DCD 0 ; /* 66 Reserved interrupt */ + DCD 0 ; /* 67 Reserved interrupt */ + DCD 0 ; /* 68 Reserved interrupt */ + DCD 0 ; /* 69 Reserved interrupt */ + DCD 0 ; /* 70 Reserved interrupt */ + DCD 0 ; /* 71 Reserved interrupt */ + DCD 0 ; /* 72 Reserved interrupt */ + DCD 0 ; /* 73 Reserved interrupt */ + DCD 0 ; /* 74 Reserved interrupt */ + DCD 0 ; /* 75 Reserved interrupt */ + DCD 0 ; /* 76 Reserved interrupt */ + DCD 0 ; /* 77 Reserved interrupt */ + DCD 0 ; /* 78 Reserved interrupt */ + DCD 0 ; /* 79 Reserved interrupt */ + DCD 0 ; /* 80 Reserved interrupt */ + DCD 0 ; /* 81 Reserved interrupt */ + DCD 0 ; /* 82 Reserved interrupt */ + DCD 0 ; /* 83 Reserved interrupt */ + DCD 0 ; /* 84 Reserved interrupt */ + DCD 0 ; /* 85 Reserved interrupt */ + DCD 0 ; /* 86 Reserved interrupt */ + DCD 0 ; /* 87 Reserved interrupt */ + DCD 0 ; /* 88 Reserved interrupt */ + DCD 0 ; /* 89 Reserved interrupt */ + DCD 0 ; /* 90 Reserved interrupt */ + DCD 0 ; /* 91 Reserved interrupt */ + DCD 0 ; /* 92 Reserved interrupt */ + DCD 0 ; /* 93 Reserved interrupt */ + DCD 0 ; /* 94 Reserved interrupt */ + DCD 0 ; /* 95 Reserved interrupt */ + DCD 0 ; /* 96 Reserved interrupt */ + DCD 0 ; /* 97 Reserved interrupt */ + DCD 0 ; /* 98 Reserved interrupt */ + DCD 0 ; /* 99 Reserved interrupt */ + DCD 0 ; /* 100 Reserved interrupt */ + DCD 0 ; /* 101 Reserved interrupt */ + DCD 0 ; /* 102 Reserved interrupt */ + DCD 0 ; /* 103 Reserved interrupt */ + DCD 0 ; /* 104 Reserved interrupt */ + DCD 0 ; /* 105 Reserved interrupt */ + DCD 0 ; /* 106 Reserved interrupt */ + DCD 0 ; /* 107 Reserved interrupt */ + DCD 0 ; /* 108 Reserved interrupt */ + DCD 0 ; /* 109 Reserved interrupt */ + DCD 0 ; /* 110 Reserved interrupt */ + DCD 0 ; /* 111 Reserved interrupt */ + DCD 0 ; /* 112 Reserved interrupt */ + DCD 0 ; /* 113 Reserved interrupt */ + DCD 0 ; /* 114 Reserved interrupt */ + DCD 0 ; /* 115 Reserved interrupt */ + DCD 0 ; /* 116 Reserved interrupt */ + DCD 0 ; /* 117 Reserved interrupt */ + DCD 0 ; /* 118 Reserved interrupt */ + DCD 0 ; /* 119 Reserved interrupt */ + DCD 0 ; /* 120 Reserved interrupt */ + DCD 0 ; /* 121 Reserved interrupt */ + DCD 0 ; /* 122 Reserved interrupt */ + DCD 0 ; /* 123 Reserved interrupt */ + DCD 0 ; /* 124 Reserved interrupt */ + DCD 0 ; /* 125 Reserved interrupt */ + DCD 0 ; /* 126 Reserved interrupt */ + DCD 0 ; /* 127 Reserved interrupt */ + DCD 0 ; /* 128 Reserved interrupt */ + DCD 0 ; /* 129 Reserved interrupt */ + DCD 0 ; /* 130 Reserved interrupt */ + DCD 0 ; /* 131 Reserved interrupt */ + DCD 0 ; /* 132 Reserved interrupt */ + DCD 0 ; /* 133 Reserved interrupt */ + DCD 0 ; /* 134 Reserved interrupt */ + DCD 0 ; /* 135 Reserved interrupt */ + DCD 0 ; /* 136 Reserved interrupt */ + DCD 0 ; /* 137 Reserved interrupt */ + DCD 0 ; /* 138 Reserved interrupt */ + DCD 0 ; /* 139 Reserved interrupt */ + DCD 0 ; /* 140 Reserved interrupt */ + DCD 0 ; /* 141 Reserved interrupt */ + DCD 0 ; /* 142 Reserved interrupt */ + DCD 0 ; /* 143 Reserved interrupt */ + DCD 0 ; /* 144 Reserved interrupt */ + DCD 0 ; /* 145 Reserved interrupt */ + DCD 0 ; /* 146 Reserved interrupt */ + DCD 0 ; /* 147 Reserved interrupt */ + DCD 0 ; /* 148 Reserved interrupt */ + DCD 0 ; /* 149 Reserved interrupt */ + DCD 0 ; /* 150 Reserved interrupt */ + DCD 0 ; /* 151 Reserved interrupt */ + DCD 0 ; /* 152 Reserved interrupt */ + DCD 0 ; /* 153 Reserved interrupt */ + DCD 0 ; /* 154 Reserved interrupt */ + DCD 0 ; /* 155 Reserved interrupt */ + DCD 0 ; /* 156 Reserved interrupt */ + DCD 0 ; /* 157 Reserved interrupt */ + DCD 0 ; /* 158 Reserved interrupt */ + DCD 0 ; /* 159 Reserved interrupt */ + DCD 0 ; /* 160 Reserved interrupt */ + DCD 0 ; /* 161 Reserved interrupt */ + DCD 0 ; /* 162 Reserved interrupt */ + DCD 0 ; /* 163 Reserved interrupt */ + DCD INT_SHA_IRQHandler ; /* 164 */ + DCD 0 ; /* 165 Reserved interrupt */ + DCD 0 ; /* 166 Reserved interrupt */ + DCD INT_AES_IRQHandler ; /* 167 */ + DCD 0 ; /* 168 Reserved interrupt */ + DCD INT_DES_IRQHandler ; /* 169 */ + DCD 0 ; /* 170 Reserved interrupt */ + DCD 0 ; /* 171 Reserved interrupt */ + DCD 0 ; /* 172 Reserved interrupt */ + DCD 0 ; /* 173 Reserved interrupt */ + DCD 0 ; /* 174 Reserved interrupt */ + DCD INT_MMCHS_IRQHandler ; /* 175 */ + DCD 0 ; /* 176 Reserved interrupt */ + DCD INT_I2S_IRQHandler ; /* 177 */ + DCD 0 ; /* 178 Reserved interrupt */ + DCD INT_CAMERA_IRQHandler ; /* 179 */ + DCD 0 ; /* 180 Reserved interrupt */ + DCD 0 ; /* 181 Reserved interrupt */ + DCD 0 ; /* 182 Reserved interrupt */ + DCD 0 ; /* 183 Reserved interrupt */ + DCD 0 ; /* 184 Reserved interrupt */ + DCD 0 ; /* 185 Reserved interrupt */ + DCD 0 ; /* 186 Reserved interrupt */ + DCD INT_NWPIC_IRQHandler ; /* 187 */ + DCD INT_PRCM_IRQHandler ; /* 188 */ + DCD 0 ; /* 189 Reserved interrupt */ + DCD 0 ; /* 190 Reserved interrupt */ + DCD INT_SSPI_IRQHandler ; /* 191 */ + DCD INT_GSPI_IRQHandler ; /* 192 */ + DCD INT_LSPI_IRQHandler ; /* 193 */ + DCD 0 ; /* 194 Reserved interrupt */ + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT_GPIOA0_IRQHandler [WEAK] + EXPORT INT_GPIOA1_IRQHandler [WEAK] + EXPORT INT_GPIOA2_IRQHandler [WEAK] + EXPORT INT_GPIOA3_IRQHandler [WEAK] + EXPORT INT_UARTA0_IRQHandler [WEAK] + EXPORT INT_UARTA1_IRQHandler [WEAK] + EXPORT INT_I2CA0_IRQHandler [WEAK] + EXPORT INT_ADCCH0_IRQHandler [WEAK] + EXPORT INT_ADCCH1_IRQHandler [WEAK] + EXPORT INT_ADCCH2_IRQHandler [WEAK] + EXPORT INT_ADCCH3_IRQHandler [WEAK] + EXPORT INT_WDT_IRQHandler [WEAK] + EXPORT INT_TIMERA0A_IRQHandler [WEAK] + EXPORT INT_TIMERA0B_IRQHandler [WEAK] + EXPORT INT_TIMERA1A_IRQHandler [WEAK] + EXPORT INT_TIMERA1B_IRQHandler [WEAK] + EXPORT INT_TIMERA2A_IRQHandler [WEAK] + EXPORT INT_TIMERA2B_IRQHandler [WEAK] + EXPORT INT_FLASH_IRQHandler [WEAK] + EXPORT INT_TIMERA3A_IRQHandler [WEAK] + EXPORT INT_TIMERA3B_IRQHandler [WEAK] + EXPORT INT_UDMA_IRQHandler [WEAK] + EXPORT INT_UDMAERR_IRQHandler [WEAK] + EXPORT INT_SHA_IRQHandler [WEAK] + EXPORT INT_AES_IRQHandler [WEAK] + EXPORT INT_DES_IRQHandler [WEAK] + EXPORT INT_MMCHS_IRQHandler [WEAK] + EXPORT INT_I2S_IRQHandler [WEAK] + EXPORT INT_CAMERA_IRQHandler [WEAK] + EXPORT INT_NWPIC_IRQHandler [WEAK] + EXPORT INT_PRCM_IRQHandler [WEAK] + EXPORT INT_SSPI_IRQHandler [WEAK] + EXPORT INT_GSPI_IRQHandler [WEAK] + EXPORT INT_LSPI_IRQHandler [WEAK] + +INT_GPIOA0_IRQHandler +INT_GPIOA1_IRQHandler +INT_GPIOA2_IRQHandler +INT_GPIOA3_IRQHandler +INT_UARTA0_IRQHandler +INT_UARTA1_IRQHandler +INT_I2CA0_IRQHandler +INT_ADCCH0_IRQHandler +INT_ADCCH1_IRQHandler +INT_ADCCH2_IRQHandler +INT_ADCCH3_IRQHandler +INT_WDT_IRQHandler +INT_TIMERA0A_IRQHandler +INT_TIMERA0B_IRQHandler +INT_TIMERA1A_IRQHandler +INT_TIMERA1B_IRQHandler +INT_TIMERA2A_IRQHandler +INT_TIMERA2B_IRQHandler +INT_FLASH_IRQHandler +INT_TIMERA3A_IRQHandler +INT_TIMERA3B_IRQHandler +INT_UDMA_IRQHandler +INT_UDMAERR_IRQHandler +INT_SHA_IRQHandler +INT_AES_IRQHandler +INT_DES_IRQHandler +INT_MMCHS_IRQHandler +INT_I2S_IRQHandler +INT_CAMERA_IRQHandler +INT_NWPIC_IRQHandler +INT_PRCM_IRQHandler +INT_SSPI_IRQHandler +INT_GSPI_IRQHandler +INT_LSPI_IRQHandler + + B . + + ENDP + + ALIGN + + END diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/gcc_arm.ld b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/gcc_arm.ld new file mode 100644 index 00000000000..25fa6835c35 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/gcc_arm.ld @@ -0,0 +1,218 @@ +/* Device specific values */ + +#define ROM_START 0x01000000 +#define ROM_SIZE 0x100000 +#define FLASH_HDR_START ROM_START +#define FLASH_HDR_SIZE 0x800 +#define RAM_START 0x20000000 +#define RAM_SIZE 0x40000 +#define VECTORS 195 /* This value must match NVIC_NUM_VECTORS */ + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((VECTORS * 4) + 7) & 0xFFFFFFF8) + +#if defined(MBED_APP_START) + /* + * There're two cases if MBED_APP_START is defined. + * Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build. + * In this build, include FLASH_HDR region. + */ + #define FLASH_HDR_INCLUDED 1 + + #if MBED_APP_START == ROM_START + #if defined(MBED_APP_SIZE) + #define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE) + #define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE) + #endif + #else + /* + * Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build. + * In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area + */ + #undef FLASH_HDR_INCLUDED + #define FLASH_HDR_INCLUDED 0 + #define ROM_EXEC_START MBED_APP_START + #if defined(MBED_APP_SIZE) + #define ROM_EXEC_SIZE MBED_APP_SIZE + #else + #define ROM_EXEC_SIZE (ROM_SIZE- (MBED_APP_START - ROM_START)) + #endif + #endif +#else + /* + * MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader. + * In this build, include FLASH_HDR region + */ + #define FLASH_HDR_INCLUDED 1 + #define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE) + #if defined(MBED_APP_SIZE) + #define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE) + #else + #define ROM_EXEC_SIZE (ROM_SIZE - FLASH_HDR_SIZE) + #endif +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + + +MEMORY +{ + FLASH_HDR (rx) : ORIGIN = FLASH_HDR_START, LENGTH = FLASH_HDR_SIZE + FLASH (rx) : ORIGIN = ROM_EXEC_START, LENGTH = ROM_EXEC_SIZE + RAM (rwx) : ORIGIN = RAM_START + VECTORS_SIZE, LENGTH = RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ +#if FLASH_HDR_INCLUDED == 1 + .dbghdr : ALIGN (2048) { + KEEP (*(.dbghdr)) + } > FLASH_HDR +#endif + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Location counter can end up 2byte aligned with narrow Thumb code but + __etext is assumed by startup code to be the LMA of a section in RAM + which must be 4byte aligned */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + . = ALIGN(4); + __end__ = .; + end = __end__; + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/startup_CC3220SF.S b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/startup_CC3220SF.S new file mode 100644 index 00000000000..cdf76314c4c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/startup_CC3220SF.S @@ -0,0 +1,451 @@ +/**************************************************************************//** + * @file startup_CC3220SF.S + * @brief CMSIS Cortex-M4 Core Device Startup File for + * Device CC3220SF + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x1000 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + + .section .isr_vector + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long INT_GPIOA0_IRQHandler /* 16 */ + .long INT_GPIOA1_IRQHandler /* 17 */ + .long INT_GPIOA2_IRQHandler /* 18 */ + .long INT_GPIOA3_IRQHandler /* 19 */ + .long 0 /* 20 Reserved interrupt */ + .long INT_UARTA0_IRQHandler /* 21 */ + .long INT_UARTA1_IRQHandler /* 22 */ + .long 0 /* 23 Reserved interrupt */ + .long INT_I2CA0_IRQHandler /* 24 */ + .long 0 /* 25 Reserved interrupt */ + .long 0 /* 26 Reserved interrupt */ + .long 0 /* 27 Reserved interrupt */ + .long 0 /* 28 Reserved interrupt */ + .long 0 /* 29 Reserved interrupt */ + .long INT_ADCCH0_IRQHandler /* 30 */ + .long INT_ADCCH1_IRQHandler /* 31 */ + .long INT_ADCCH2_IRQHandler /* 32 */ + .long INT_ADCCH3_IRQHandler /* 33 */ + .long INT_WDT_IRQHandler /* 34 */ + .long INT_TIMERA0A_IRQHandler /* 35 */ + .long INT_TIMERA0B_IRQHandler /* 36 */ + .long INT_TIMERA1A_IRQHandler /* 37 */ + .long INT_TIMERA1B_IRQHandler /* 38 */ + .long INT_TIMERA2A_IRQHandler /* 39 */ + .long INT_TIMERA2B_IRQHandler /* 40 */ + .long 0 /* 41 Reserved interrupt */ + .long 0 /* 42 Reserved interrupt */ + .long 0 /* 43 Reserved interrupt */ + .long 0 /* 44 Reserved interrupt */ + .long INT_FLASH_IRQHandler /* 45 */ + .long 0 /* 46 Reserved interrupt */ + .long 0 /* 47 Reserved interrupt */ + .long 0 /* 48 Reserved interrupt */ + .long 0 /* 49 Reserved interrupt */ + .long 0 /* 50 Reserved interrupt */ + .long INT_TIMERA3A_IRQHandler /* 51 */ + .long INT_TIMERA3B_IRQHandler /* 52 */ + .long 0 /* 53 Reserved interrupt */ + .long 0 /* 54 Reserved interrupt */ + .long 0 /* 55 Reserved interrupt */ + .long 0 /* 56 Reserved interrupt */ + .long 0 /* 57 Reserved interrupt */ + .long 0 /* 58 Reserved interrupt */ + .long 0 /* 59 Reserved interrupt */ + .long 0 /* 60 Reserved interrupt */ + .long 0 /* 61 Reserved interrupt */ + .long INT_UDMA_IRQHandler /* 62 */ + .long INT_UDMAERR_IRQHandler /* 63 */ + .long 0 /* 64 Reserved interrupt */ + .long 0 /* 65 Reserved interrupt */ + .long 0 /* 66 Reserved interrupt */ + .long 0 /* 67 Reserved interrupt */ + .long 0 /* 68 Reserved interrupt */ + .long 0 /* 69 Reserved interrupt */ + .long 0 /* 70 Reserved interrupt */ + .long 0 /* 71 Reserved interrupt */ + .long 0 /* 72 Reserved interrupt */ + .long 0 /* 73 Reserved interrupt */ + .long 0 /* 74 Reserved interrupt */ + .long 0 /* 75 Reserved interrupt */ + .long 0 /* 76 Reserved interrupt */ + .long 0 /* 77 Reserved interrupt */ + .long 0 /* 78 Reserved interrupt */ + .long 0 /* 79 Reserved interrupt */ + .long 0 /* 80 Reserved interrupt */ + .long 0 /* 81 Reserved interrupt */ + .long 0 /* 82 Reserved interrupt */ + .long 0 /* 83 Reserved interrupt */ + .long 0 /* 84 Reserved interrupt */ + .long 0 /* 85 Reserved interrupt */ + .long 0 /* 86 Reserved interrupt */ + .long 0 /* 87 Reserved interrupt */ + .long 0 /* 88 Reserved interrupt */ + .long 0 /* 89 Reserved interrupt */ + .long 0 /* 90 Reserved interrupt */ + .long 0 /* 91 Reserved interrupt */ + .long 0 /* 92 Reserved interrupt */ + .long 0 /* 93 Reserved interrupt */ + .long 0 /* 94 Reserved interrupt */ + .long 0 /* 95 Reserved interrupt */ + .long 0 /* 96 Reserved interrupt */ + .long 0 /* 97 Reserved interrupt */ + .long 0 /* 98 Reserved interrupt */ + .long 0 /* 99 Reserved interrupt */ + .long 0 /* 100 Reserved interrupt */ + .long 0 /* 101 Reserved interrupt */ + .long 0 /* 102 Reserved interrupt */ + .long 0 /* 103 Reserved interrupt */ + .long 0 /* 104 Reserved interrupt */ + .long 0 /* 105 Reserved interrupt */ + .long 0 /* 106 Reserved interrupt */ + .long 0 /* 107 Reserved interrupt */ + .long 0 /* 108 Reserved interrupt */ + .long 0 /* 109 Reserved interrupt */ + .long 0 /* 110 Reserved interrupt */ + .long 0 /* 111 Reserved interrupt */ + .long 0 /* 112 Reserved interrupt */ + .long 0 /* 113 Reserved interrupt */ + .long 0 /* 114 Reserved interrupt */ + .long 0 /* 115 Reserved interrupt */ + .long 0 /* 116 Reserved interrupt */ + .long 0 /* 117 Reserved interrupt */ + .long 0 /* 118 Reserved interrupt */ + .long 0 /* 119 Reserved interrupt */ + .long 0 /* 120 Reserved interrupt */ + .long 0 /* 121 Reserved interrupt */ + .long 0 /* 122 Reserved interrupt */ + .long 0 /* 123 Reserved interrupt */ + .long 0 /* 124 Reserved interrupt */ + .long 0 /* 125 Reserved interrupt */ + .long 0 /* 126 Reserved interrupt */ + .long 0 /* 127 Reserved interrupt */ + .long 0 /* 128 Reserved interrupt */ + .long 0 /* 129 Reserved interrupt */ + .long 0 /* 130 Reserved interrupt */ + .long 0 /* 131 Reserved interrupt */ + .long 0 /* 132 Reserved interrupt */ + .long 0 /* 133 Reserved interrupt */ + .long 0 /* 134 Reserved interrupt */ + .long 0 /* 135 Reserved interrupt */ + .long 0 /* 136 Reserved interrupt */ + .long 0 /* 137 Reserved interrupt */ + .long 0 /* 138 Reserved interrupt */ + .long 0 /* 139 Reserved interrupt */ + .long 0 /* 140 Reserved interrupt */ + .long 0 /* 141 Reserved interrupt */ + .long 0 /* 142 Reserved interrupt */ + .long 0 /* 143 Reserved interrupt */ + .long 0 /* 144 Reserved interrupt */ + .long 0 /* 145 Reserved interrupt */ + .long 0 /* 146 Reserved interrupt */ + .long 0 /* 147 Reserved interrupt */ + .long 0 /* 148 Reserved interrupt */ + .long 0 /* 149 Reserved interrupt */ + .long 0 /* 150 Reserved interrupt */ + .long 0 /* 151 Reserved interrupt */ + .long 0 /* 152 Reserved interrupt */ + .long 0 /* 153 Reserved interrupt */ + .long 0 /* 154 Reserved interrupt */ + .long 0 /* 155 Reserved interrupt */ + .long 0 /* 156 Reserved interrupt */ + .long 0 /* 157 Reserved interrupt */ + .long 0 /* 158 Reserved interrupt */ + .long 0 /* 159 Reserved interrupt */ + .long 0 /* 160 Reserved interrupt */ + .long 0 /* 161 Reserved interrupt */ + .long 0 /* 162 Reserved interrupt */ + .long 0 /* 163 Reserved interrupt */ + .long INT_SHA_IRQHandler /* 164 */ + .long 0 /* 165 Reserved interrupt */ + .long 0 /* 166 Reserved interrupt */ + .long INT_AES_IRQHandler /* 167 */ + .long 0 /* 168 Reserved interrupt */ + .long INT_DES_IRQHandler /* 169 */ + .long 0 /* 170 Reserved interrupt */ + .long 0 /* 171 Reserved interrupt */ + .long 0 /* 172 Reserved interrupt */ + .long 0 /* 173 Reserved interrupt */ + .long 0 /* 174 Reserved interrupt */ + .long INT_MMCHS_IRQHandler /* 175 */ + .long 0 /* 176 Reserved interrupt */ + .long INT_I2S_IRQHandler /* 177 */ + .long 0 /* 178 Reserved interrupt */ + .long INT_CAMERA_IRQHandler /* 179 */ + .long 0 /* 180 Reserved interrupt */ + .long 0 /* 181 Reserved interrupt */ + .long 0 /* 182 Reserved interrupt */ + .long 0 /* 183 Reserved interrupt */ + .long 0 /* 184 Reserved interrupt */ + .long 0 /* 185 Reserved interrupt */ + .long 0 /* 186 Reserved interrupt */ + .long INT_NWPIC_IRQHandler /* 187 */ + .long INT_PRCM_IRQHandler /* 188 */ + .long 0 /* 189 Reserved interrupt */ + .long 0 /* 190 Reserved interrupt */ + .long INT_SSPI_IRQHandler /* 191 */ + .long INT_GSPI_IRQHandler /* 192 */ + .long INT_LSPI_IRQHandler /* 193 */ + .long 0 /* 194 Reserved interrupt */ + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT_GPIOA0_IRQHandler + def_irq_handler INT_GPIOA1_IRQHandler + def_irq_handler INT_GPIOA2_IRQHandler + def_irq_handler INT_GPIOA3_IRQHandler + def_irq_handler INT_UARTA0_IRQHandler + def_irq_handler INT_UARTA1_IRQHandler + def_irq_handler INT_I2CA0_IRQHandler + def_irq_handler INT_ADCCH0_IRQHandler + def_irq_handler INT_ADCCH1_IRQHandler + def_irq_handler INT_ADCCH2_IRQHandler + def_irq_handler INT_ADCCH3_IRQHandler + def_irq_handler INT_WDT_IRQHandler + def_irq_handler INT_TIMERA0A_IRQHandler + def_irq_handler INT_TIMERA0B_IRQHandler + def_irq_handler INT_TIMERA1A_IRQHandler + def_irq_handler INT_TIMERA1B_IRQHandler + def_irq_handler INT_TIMERA2A_IRQHandler + def_irq_handler INT_TIMERA2B_IRQHandler + def_irq_handler INT_FLASH_IRQHandler + def_irq_handler INT_TIMERA3A_IRQHandler + def_irq_handler INT_TIMERA3B_IRQHandler + def_irq_handler INT_UDMA_IRQHandler + def_irq_handler INT_UDMAERR_IRQHandler + def_irq_handler INT_SHA_IRQHandler + def_irq_handler INT_AES_IRQHandler + def_irq_handler INT_DES_IRQHandler + def_irq_handler INT_MMCHS_IRQHandler + def_irq_handler INT_I2S_IRQHandler + def_irq_handler INT_CAMERA_IRQHandler + def_irq_handler INT_NWPIC_IRQHandler + def_irq_handler INT_PRCM_IRQHandler + def_irq_handler INT_SSPI_IRQHandler + def_irq_handler INT_GSPI_IRQHandler + def_irq_handler INT_LSPI_IRQHandler + .end diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/CC3220SF.icf b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/CC3220SF.icf new file mode 100644 index 00000000000..24760ca2876 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/CC3220SF.icf @@ -0,0 +1,100 @@ +/* Device specific values */ + +define symbol ROM_START = 0x01000000; +define symbol ROM_SIZE = 0x100000; +define symbol FLASH_HDR_START = ROM_START; +define symbol FLASH_HDR_SIZE = 0x800; +define symbol RAM_START = 0x20000000; +define symbol RAM_SIZE = 0x40000; +define symbol VECTORS = 195; /* This value must match NVIC_NUM_VECTORS */ + +/* Common - Do not change */ + +if (isdefinedsymbol(MBED_APP_START)) { + /* + * There're two cases if MBED_APP_START is defined. + * Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build. + * In this build, include FLASH_HDR region. + */ + if (MBED_APP_START == ROM_START) { + define symbol FLASH_HDR_INCLUDED = 1; + if (isdefinedsymbol(MBED_APP_SIZE)) { + define symbol ROM_EXEC_START = (ROM_START + FLASH_HDR_SIZE); + define symbol ROM_EXEC_SIZE = (MBED_APP_SIZE - FLASH_HDR_SIZE); + } + } + else { + /* + * Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build. + * In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area + */ + define symbol FLASH_HDR_INCLUDED = 0; + define symbol ROM_EXEC_START = MBED_APP_START; + if (isdefinedsymbol(MBED_APP_SIZE)) { + define symbol ROM_EXEC_SIZE= MBED_APP_SIZE; + } + else { + define symbol ROM_EXEC_SIZE = (ROM_SIZE- (MBED_APP_START - ROM_START)); + } + } +} +else { + /* + * MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader. + * In this build, include FLASH_HDR region + */ + define symbol FLASH_HDR_INCLUDED = 1; + define symbol ROM_EXEC_START = (ROM_START + FLASH_HDR_SIZE); + if (isdefinedsymbol (MBED_APP_SIZE)) { + define symbol ROM_EXEC_SIZE = (MBED_APP_SIZE - FLASH_HDR_SIZE); + } + else { + define symbol ROM_EXEC_SIZE = (ROM_SIZE - FLASH_HDR_SIZE); + } +} + + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; + +/* boot stack size*/ +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} +/* Place the boot stack at the top of the RAM */ +define symbol CSTACK_START = (RAM_START + RAM_SIZE - MBED_BOOT_STACK_SIZE); +define symbol CSTACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* The rest of RAM */ +define symbol RAM_REGION_START = (RAM_START + VECTORS_SIZE); +define symbol RAM_REGION_SIZE = (RAM_SIZE - VECTORS_SIZE - MBED_BOOT_STACK_SIZE); + +define memory mem with size = 4G; +/* ROM regions */ +define region FLASH_HDR_region = mem:[from FLASH_HDR_START size FLASH_HDR_SIZE]; +define region FLASH_region = mem:[from ROM_EXEC_START size ROM_EXEC_SIZE]; + +/* RAM regions */ +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; +define region CSTACK_region = mem:[from CSTACK_START size CSTACK_SIZE]; + +if (FLASH_HDR_INCLUDED == 1) { + keep {section .dbghdr}; + place in FLASH_HDR_region { readonly section .dbghdr }; +} + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: ROM_EXEC_START { readonly section .intvec }; + +place in FLASH_region { readonly }; + +define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +place in CSTACK_region { block CSTACK }; + +define symbol __size_heap__ = 0x10000; +define block HEAP with expanding size, alignment = 8, minimum size = __size_heap__ { }; +place in RAM_region { block HEAP, readwrite, zeroinit }; + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/startup_CC3220SF.S b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/startup_CC3220SF.S new file mode 100644 index 00000000000..04234fab247 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/startup_CC3220SF.S @@ -0,0 +1,486 @@ +;/**************************************************************************//** +; * @file startup_CC3220SF.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Device CC3220SF +; * @version V5.00 +; * @date 07. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT_GPIOA0_IRQHandler /* 16 */ + DCD INT_GPIOA1_IRQHandler /* 17 */ + DCD INT_GPIOA2_IRQHandler /* 18 */ + DCD INT_GPIOA3_IRQHandler /* 19 */ + DCD 0 /* 20 Reserved interrupt */ + DCD INT_UARTA0_IRQHandler /* 21 */ + DCD INT_UARTA1_IRQHandler /* 22 */ + DCD 0 /* 23 Reserved interrupt */ + DCD INT_I2CA0_IRQHandler /* 24 */ + DCD 0 /* 25 Reserved interrupt */ + DCD 0 /* 26 Reserved interrupt */ + DCD 0 /* 27 Reserved interrupt */ + DCD 0 /* 28 Reserved interrupt */ + DCD 0 /* 29 Reserved interrupt */ + DCD INT_ADCCH0_IRQHandler /* 30 */ + DCD INT_ADCCH1_IRQHandler /* 31 */ + DCD INT_ADCCH2_IRQHandler /* 32 */ + DCD INT_ADCCH3_IRQHandler /* 33 */ + DCD INT_WDT_IRQHandler /* 34 */ + DCD INT_TIMERA0A_IRQHandler /* 35 */ + DCD INT_TIMERA0B_IRQHandler /* 36 */ + DCD INT_TIMERA1A_IRQHandler /* 37 */ + DCD INT_TIMERA1B_IRQHandler /* 38 */ + DCD INT_TIMERA2A_IRQHandler /* 39 */ + DCD INT_TIMERA2B_IRQHandler /* 40 */ + DCD 0 /* 41 Reserved interrupt */ + DCD 0 /* 42 Reserved interrupt */ + DCD 0 /* 43 Reserved interrupt */ + DCD 0 /* 44 Reserved interrupt */ + DCD INT_FLASH_IRQHandler /* 45 */ + DCD 0 /* 46 Reserved interrupt */ + DCD 0 /* 47 Reserved interrupt */ + DCD 0 /* 48 Reserved interrupt */ + DCD 0 /* 49 Reserved interrupt */ + DCD 0 /* 50 Reserved interrupt */ + DCD INT_TIMERA3A_IRQHandler /* 51 */ + DCD INT_TIMERA3B_IRQHandler /* 52 */ + DCD 0 /* 53 Reserved interrupt */ + DCD 0 /* 54 Reserved interrupt */ + DCD 0 /* 55 Reserved interrupt */ + DCD 0 /* 56 Reserved interrupt */ + DCD 0 /* 57 Reserved interrupt */ + DCD 0 /* 58 Reserved interrupt */ + DCD 0 /* 59 Reserved interrupt */ + DCD 0 /* 60 Reserved interrupt */ + DCD 0 /* 61 Reserved interrupt */ + DCD INT_UDMA_IRQHandler /* 62 */ + DCD INT_UDMAERR_IRQHandler /* 63 */ + DCD 0 /* 64 Reserved interrupt */ + DCD 0 /* 65 Reserved interrupt */ + DCD 0 /* 66 Reserved interrupt */ + DCD 0 /* 67 Reserved interrupt */ + DCD 0 /* 68 Reserved interrupt */ + DCD 0 /* 69 Reserved interrupt */ + DCD 0 /* 70 Reserved interrupt */ + DCD 0 /* 71 Reserved interrupt */ + DCD 0 /* 72 Reserved interrupt */ + DCD 0 /* 73 Reserved interrupt */ + DCD 0 /* 74 Reserved interrupt */ + DCD 0 /* 75 Reserved interrupt */ + DCD 0 /* 76 Reserved interrupt */ + DCD 0 /* 77 Reserved interrupt */ + DCD 0 /* 78 Reserved interrupt */ + DCD 0 /* 79 Reserved interrupt */ + DCD 0 /* 80 Reserved interrupt */ + DCD 0 /* 81 Reserved interrupt */ + DCD 0 /* 82 Reserved interrupt */ + DCD 0 /* 83 Reserved interrupt */ + DCD 0 /* 84 Reserved interrupt */ + DCD 0 /* 85 Reserved interrupt */ + DCD 0 /* 86 Reserved interrupt */ + DCD 0 /* 87 Reserved interrupt */ + DCD 0 /* 88 Reserved interrupt */ + DCD 0 /* 89 Reserved interrupt */ + DCD 0 /* 90 Reserved interrupt */ + DCD 0 /* 91 Reserved interrupt */ + DCD 0 /* 92 Reserved interrupt */ + DCD 0 /* 93 Reserved interrupt */ + DCD 0 /* 94 Reserved interrupt */ + DCD 0 /* 95 Reserved interrupt */ + DCD 0 /* 96 Reserved interrupt */ + DCD 0 /* 97 Reserved interrupt */ + DCD 0 /* 98 Reserved interrupt */ + DCD 0 /* 99 Reserved interrupt */ + DCD 0 /* 100 Reserved interrupt */ + DCD 0 /* 101 Reserved interrupt */ + DCD 0 /* 102 Reserved interrupt */ + DCD 0 /* 103 Reserved interrupt */ + DCD 0 /* 104 Reserved interrupt */ + DCD 0 /* 105 Reserved interrupt */ + DCD 0 /* 106 Reserved interrupt */ + DCD 0 /* 107 Reserved interrupt */ + DCD 0 /* 108 Reserved interrupt */ + DCD 0 /* 109 Reserved interrupt */ + DCD 0 /* 110 Reserved interrupt */ + DCD 0 /* 111 Reserved interrupt */ + DCD 0 /* 112 Reserved interrupt */ + DCD 0 /* 113 Reserved interrupt */ + DCD 0 /* 114 Reserved interrupt */ + DCD 0 /* 115 Reserved interrupt */ + DCD 0 /* 116 Reserved interrupt */ + DCD 0 /* 117 Reserved interrupt */ + DCD 0 /* 118 Reserved interrupt */ + DCD 0 /* 119 Reserved interrupt */ + DCD 0 /* 120 Reserved interrupt */ + DCD 0 /* 121 Reserved interrupt */ + DCD 0 /* 122 Reserved interrupt */ + DCD 0 /* 123 Reserved interrupt */ + DCD 0 /* 124 Reserved interrupt */ + DCD 0 /* 125 Reserved interrupt */ + DCD 0 /* 126 Reserved interrupt */ + DCD 0 /* 127 Reserved interrupt */ + DCD 0 /* 128 Reserved interrupt */ + DCD 0 /* 129 Reserved interrupt */ + DCD 0 /* 130 Reserved interrupt */ + DCD 0 /* 131 Reserved interrupt */ + DCD 0 /* 132 Reserved interrupt */ + DCD 0 /* 133 Reserved interrupt */ + DCD 0 /* 134 Reserved interrupt */ + DCD 0 /* 135 Reserved interrupt */ + DCD 0 /* 136 Reserved interrupt */ + DCD 0 /* 137 Reserved interrupt */ + DCD 0 /* 138 Reserved interrupt */ + DCD 0 /* 139 Reserved interrupt */ + DCD 0 /* 140 Reserved interrupt */ + DCD 0 /* 141 Reserved interrupt */ + DCD 0 /* 142 Reserved interrupt */ + DCD 0 /* 143 Reserved interrupt */ + DCD 0 /* 144 Reserved interrupt */ + DCD 0 /* 145 Reserved interrupt */ + DCD 0 /* 146 Reserved interrupt */ + DCD 0 /* 147 Reserved interrupt */ + DCD 0 /* 148 Reserved interrupt */ + DCD 0 /* 149 Reserved interrupt */ + DCD 0 /* 150 Reserved interrupt */ + DCD 0 /* 151 Reserved interrupt */ + DCD 0 /* 152 Reserved interrupt */ + DCD 0 /* 153 Reserved interrupt */ + DCD 0 /* 154 Reserved interrupt */ + DCD 0 /* 155 Reserved interrupt */ + DCD 0 /* 156 Reserved interrupt */ + DCD 0 /* 157 Reserved interrupt */ + DCD 0 /* 158 Reserved interrupt */ + DCD 0 /* 159 Reserved interrupt */ + DCD 0 /* 160 Reserved interrupt */ + DCD 0 /* 161 Reserved interrupt */ + DCD 0 /* 162 Reserved interrupt */ + DCD 0 /* 163 Reserved interrupt */ + DCD INT_SHA_IRQHandler /* 164 */ + DCD 0 /* 165 Reserved interrupt */ + DCD 0 /* 166 Reserved interrupt */ + DCD INT_AES_IRQHandler /* 167 */ + DCD 0 /* 168 Reserved interrupt */ + DCD INT_DES_IRQHandler /* 169 */ + DCD 0 /* 170 Reserved interrupt */ + DCD 0 /* 171 Reserved interrupt */ + DCD 0 /* 172 Reserved interrupt */ + DCD 0 /* 173 Reserved interrupt */ + DCD 0 /* 174 Reserved interrupt */ + DCD INT_MMCHS_IRQHandler /* 175 */ + DCD 0 /* 176 Reserved interrupt */ + DCD INT_I2S_IRQHandler /* 177 */ + DCD 0 /* 178 Reserved interrupt */ + DCD INT_CAMERA_IRQHandler /* 179 */ + DCD 0 /* 180 Reserved interrupt */ + DCD 0 /* 181 Reserved interrupt */ + DCD 0 /* 182 Reserved interrupt */ + DCD 0 /* 183 Reserved interrupt */ + DCD 0 /* 184 Reserved interrupt */ + DCD 0 /* 185 Reserved interrupt */ + DCD 0 /* 186 Reserved interrupt */ + DCD INT_NWPIC_IRQHandler /* 187 */ + DCD INT_PRCM_IRQHandler /* 188 */ + DCD 0 /* 189 Reserved interrupt */ + DCD 0 /* 190 Reserved interrupt */ + DCD INT_SSPI_IRQHandler /* 191 */ + DCD INT_GSPI_IRQHandler /* 192 */ + DCD INT_LSPI_IRQHandler /* 193 */ + DCD 0 /* 194 Reserved interrupt */ + +__Vectors EQU __vector_table + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK INT_GPIOA0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_GPIOA0_IRQHandler + B INT_GPIOA0_IRQHandler + + PUBWEAK INT_GPIOA1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_GPIOA1_IRQHandler + B INT_GPIOA1_IRQHandler + + PUBWEAK INT_GPIOA2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_GPIOA2_IRQHandler + B INT_GPIOA2_IRQHandler + + PUBWEAK INT_GPIOA3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_GPIOA3_IRQHandler + B INT_GPIOA3_IRQHandler + + PUBWEAK INT_UARTA0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_UARTA0_IRQHandler + B INT_UARTA0_IRQHandler + + PUBWEAK INT_UARTA1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_UARTA1_IRQHandler + B INT_UARTA1_IRQHandler + + PUBWEAK INT_I2CA0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_I2CA0_IRQHandler + B INT_I2CA0_IRQHandler + + PUBWEAK INT_ADCCH0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_ADCCH0_IRQHandler + B INT_ADCCH0_IRQHandler + + PUBWEAK INT_ADCCH1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_ADCCH1_IRQHandler + B INT_ADCCH1_IRQHandler + + PUBWEAK INT_ADCCH2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_ADCCH2_IRQHandler + B INT_ADCCH2_IRQHandler + + PUBWEAK INT_ADCCH3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_ADCCH3_IRQHandler + B INT_ADCCH3_IRQHandler + + PUBWEAK INT_WDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_WDT_IRQHandler + B INT_WDT_IRQHandler + + PUBWEAK INT_TIMERA0A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_TIMERA0A_IRQHandler + B INT_TIMERA0A_IRQHandler + + PUBWEAK INT_TIMERA0B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_TIMERA0B_IRQHandler + B INT_TIMERA0B_IRQHandler + + PUBWEAK INT_TIMERA1A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_TIMERA1A_IRQHandler + B INT_TIMERA1A_IRQHandler + + PUBWEAK INT_TIMERA1B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_TIMERA1B_IRQHandler + B INT_TIMERA1B_IRQHandler + + PUBWEAK INT_TIMERA2A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_TIMERA2A_IRQHandler + B INT_TIMERA2A_IRQHandler + + PUBWEAK INT_TIMERA2B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_TIMERA2B_IRQHandler + B INT_TIMERA2B_IRQHandler + + PUBWEAK INT_FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_FLASH_IRQHandler + B INT_FLASH_IRQHandler + + PUBWEAK INT_TIMERA3A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_TIMERA3A_IRQHandler + B INT_TIMERA3A_IRQHandler + + PUBWEAK INT_TIMERA3B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_TIMERA3B_IRQHandler + B INT_TIMERA3B_IRQHandler + + PUBWEAK INT_UDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_UDMA_IRQHandler + B INT_UDMA_IRQHandler + + PUBWEAK INT_UDMAERR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_UDMAERR_IRQHandler + B INT_UDMAERR_IRQHandler + + PUBWEAK INT_SHA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_SHA_IRQHandler + B INT_SHA_IRQHandler + + PUBWEAK INT_AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_AES_IRQHandler + B INT_AES_IRQHandler + + PUBWEAK INT_DES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_DES_IRQHandler + B INT_DES_IRQHandler + + PUBWEAK INT_MMCHS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_MMCHS_IRQHandler + B INT_MMCHS_IRQHandler + + PUBWEAK INT_I2S_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_I2S_IRQHandler + B INT_I2S_IRQHandler + + PUBWEAK INT_CAMERA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_CAMERA_IRQHandler + B INT_CAMERA_IRQHandler + + PUBWEAK INT_NWPIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_NWPIC_IRQHandler + B INT_NWPIC_IRQHandler + + PUBWEAK INT_PRCM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_PRCM_IRQHandler + B INT_PRCM_IRQHandler + + PUBWEAK INT_SSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_SSPI_IRQHandler + B INT_SSPI_IRQHandler + + PUBWEAK INT_GSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_GSPI_IRQHandler + B INT_GSPI_IRQHandler + + PUBWEAK INT_LSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +INT_LSPI_IRQHandler + B INT_LSPI_IRQHandler + END diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp new file mode 100644 index 00000000000..7feee346011 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp @@ -0,0 +1,937 @@ +/* CC3200_SIMPLELINK Class + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "cc3200_simplelink.h" +#include "nsapi_types.h" +#include "ip4string.h" +#include "CC3220SF_Init.h" + +#define SOCKET_IS_NON_BLOCKING (1) + +#define SL_STOP_TIMEOUT (200) + +CC3200_SIMPLELINK::CC3200_SIMPLELINK() + : _connect_error(0), + _initialized(false), + _current_role(0), + _fail(false), + _closed(false), + _connection_status(NSAPI_STATUS_DISCONNECTED), + _connected_ssid(), + _connected_channel(0), + _timeout(CC3200_SIMPLELINK_MISC_TIMEOUT) +{ + memset(_ip_buffer, 0, sizeof(_ip_buffer)); + memset(_gateway_buffer, 0, sizeof(_gateway_buffer)); + memset(_netmask_buffer, 0, sizeof(_netmask_buffer)); + memset(_mac_buffer, 0, sizeof(_mac_buffer)); +} + +/*! + \brief Configure SimpleLink to default state. + + This routine configures the device to a default state. + It's important to note that this is one example for a 'restore to default state' + function, which meet the needs of this application, 'Network Terminal'. User who + wish to incorporate this function into he's app, must adjust the implementation + and make sure it meets he's needs. + + \return Upon successful completion, the function shall return 0. + In case of failure, this function would return -1. + +*/ +nsapi_error_t CC3200_SIMPLELINK::initialize() +{ + int ret = NSAPI_ERROR_OK; + + if (!_initialized) + { + ret = CC3220SF_initSimplelink(); + if (ret == 0) + { + _current_role = WIFI_ROLE_STATION; + _initialized = true; + } + else + { + printf("simplelink_powerup failed with %d", ret); + return NSAPI_ERROR_DEVICE_ERROR; + } + } + return NSAPI_ERROR_OK; +} + +bool CC3200_SIMPLELINK::startup(int role) +{ + int32_t ret_val = -1; + if (role != WIFI_ROLE_STATION && role != WIFI_ROLE_AP && role != WIFI_ROLE_P2P) + { + return false; + } + if (role != _current_role) + { + ret_val = sl_WlanSetMode(role); + assert(ret_val == 0); + + /* For changes to take affect, we restart the NWP */ + ret_val = sl_Stop(SL_STOP_TIMEOUT); + assert(ret_val == 0); + + ret_val = sl_Start(0, 0, 0); + assert(ret_val == 0); + _current_role = role; + } + return true; +} + +// TODO: This will involve file system write +bool CC3200_SIMPLELINK::dhcp(bool enabled, int role) +{ +#ifdef FILE_SYSTEM_ENABLE + int32_t ret_val = -1; + uint32_t config_id, config_option; + + if (role != WIFI_ROLE_STATION && role != WIFI_ROLE_AP) + { + return false; + } + + if (role == WIFI_ROLE_STATION) + { + config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; + } + else + { + config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; + } + if (enabled) + { + config_option = SL_NETCFG_ADDR_DHCP; + ret_val = sl_NetCfgSet(config_id, config_option, 0, 0); + } + else + { + config_option = SL_NETCFG_ADDR_STATIC; + SlNetCfgIpV4Args_t ipV4; + ipV4.Ip = (_u32)SL_IPV4_VAL(_ip_buffer[0],_ip_buffer[1],_ip_buffer[2],_ip_buffer[3]); // _u32 IP address + ipV4.IpMask = (_u32)SL_IPV4_VAL(_netmask_buffer[0],_netmask_buffer[1],_netmask_buffer[2],_netmask_buffer[3]); // _u32 Subnet mask for this STA/P2P + ipV4.IpGateway = (_u32)SL_IPV4_VAL(_gateway_buffer[0],_gateway_buffer[1],_gateway_buffer[2],_gateway_buffer[3]); // _u32 Default gateway address + ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(_dns_server_buffer[0],_dns_server_buffer[1],_dns_server_buffer[2],_dns_server_buffer[3]); // _u32 DNS server address + ret_val = sl_NetCfgSet(config_id, config_option, sizeof(SlNetCfgIpV4Args_t), (_u8 *)&ipV4); + } + if (ret_val == 0) + { + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + return true; + } + else + { + return false; + } +#else + return true; +#endif +} + +nsapi_error_t CC3200_SIMPLELINK::connect(const char *ssid, const char *passPhrase, nsapi_security_t security) +{ + nsapi_error_t status; + _i16 ret; + SlWlanSecParams_t sec_params; + + if (!ssid || (!passPhrase && security != NSAPI_SECURITY_NONE)) + { + printf("Invalid credentials\r\n"); + return NSAPI_ERROR_PARAMETER; + } + + status = initialize(); + if(status != NSAPI_ERROR_OK) + { + return status; + } + + strncpy(_connected_ssid, ssid, sizeof(_connected_ssid)); + + memset((void*)&sec_params, 0, sizeof(sec_params)); + + startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION); + if(status != NSAPI_ERROR_OK) + { + return status; + } + + sec_params.Key = (signed char*)passPhrase; + sec_params.KeyLen = strlen(passPhrase); + switch (security) { + case NSAPI_SECURITY_WPA: + case NSAPI_SECURITY_WPA2: + case NSAPI_SECURITY_WPA_WPA2: + sec_params.Type = SL_WLAN_SEC_TYPE_WPA_WPA2; + break; + case NSAPI_SECURITY_WEP: + sec_params.Type = SL_WLAN_SEC_TYPE_WEP; + break; + case NSAPI_SECURITY_NONE: + sec_params.Type = SL_WLAN_SEC_TYPE_OPEN; + break; + default: + return NSAPI_ERROR_PARAMETER; + } + ret = sl_WlanConnect((const _i8*)ssid,(const _i16)(strlen(ssid)),(const _u8 *)NULL, + (const SlWlanSecParams_t*)&sec_params ,(const SlWlanSecParamsExt_t*)NULL); + if (ret != SL_RET_CODE_OK) { + return NSAPI_ERROR_NO_CONNECTION; + } + + return NSAPI_ERROR_OK; +} + +bool CC3200_SIMPLELINK::disconnect() +{ + return (sl_WlanDisconnect() == 0); +} + +const char *CC3200_SIMPLELINK::getIPAddress() +{ + int i; + _u16 config_id; + _u8 ip4addr[4]; + + if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client + { + config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; + } + else + { + config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go + } + _u16 len = sizeof(SlNetCfgIpV4Args_t); + _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC + SlNetCfgIpV4Args_t ipV4 = {0}; + + sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4); + /*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", + (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", + (int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0), + (int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0), + (int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0), + (int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/ + for (i = 0; i < 4; i ++) + { + ip4addr[i] = SL_IPV4_BYTE(ipV4.Ip,(3-i)); + } + ip4tos((const void *)ip4addr, (char *)_ip_buffer); + + return _ip_buffer; +} + +const char *CC3200_SIMPLELINK::getMACAddress() +{ + _u16 macAddressLen = SL_MAC_ADDR_LEN; + _u16 ConfigOpt = 0; + _u8 macAddress[SL_MAC_ADDR_LEN]; + + sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,&ConfigOpt,&macAddressLen,macAddress); + // Format this into xx:xx:xx:xx:xx:xx + sprintf(_mac_buffer, "%2x:%2x:%2x:%2x:%2x:%2x",macAddress[0], macAddress[1], macAddress[2], macAddress[3], macAddress[4], macAddress[5]); + return _mac_buffer; +} + +const char *CC3200_SIMPLELINK::getGateway() +{ + int i; + _u16 config_id; + _u8 ip4addr[4]; + + if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client + { + config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; + } + else + { + config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go + } + _u16 len = sizeof(SlNetCfgIpV4Args_t); + _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC + SlNetCfgIpV4Args_t ipV4 = {0}; + + sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4); + /*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", + (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", + (int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0), + (int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0), + (int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0), + (int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/ + for (i = 0; i < 4; i ++) + { + ip4addr[i] = SL_IPV4_BYTE(ipV4.IpGateway,(3-i)); + } + ip4tos((const void *)ip4addr, (char *)_gateway_buffer); + return _gateway_buffer; +} + +const char *CC3200_SIMPLELINK::getNetmask() +{ + int i; + _u16 config_id; + _u8 ip4addr[4]; + + if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client + { + config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; + } + else + { + config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go + } + _u16 len = sizeof(SlNetCfgIpV4Args_t); + _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC + SlNetCfgIpV4Args_t ipV4 = {0}; + + sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4); + /*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", + (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", + (int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0), + (int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0), + (int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0), + (int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/ + for (i = 0; i < 4; i ++) + { + ip4addr[i] = SL_IPV4_BYTE(ipV4.IpMask,(3-i)); + } + ip4tos((const void *)ip4addr, (char *)_netmask_buffer); + return _netmask_buffer; +} + +nsapi_error_t CC3200_SIMPLELINK::getDNS(unsigned char* ip4addr, uint32_t size) +{ + int i; + _u16 config_id; + + if (ip4addr == NULL || size < 4) + { + return NSAPI_ERROR_PARAMETER; + } + if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client + { + config_id = SL_NETCFG_IPV4_STA_ADDR_MODE; + } + else + { + config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go + } + _u16 len = sizeof(SlNetCfgIpV4Args_t); + _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC + SlNetCfgIpV4Args_t ipV4 = {0}; + + sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4); + /*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", + (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", + (int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0), + (int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0), + (int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0), + (int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/ + for (i = 0; i < 4; i ++) + { + ip4addr[i] = SL_IPV4_BYTE(ipV4.IpDnsServer,(3-i)); + } + return NSAPI_ERROR_OK; +} + +int CC3200_SIMPLELINK::scan(WiFiAccessPoint *res, unsigned count) +{ + _u8 entries_count = MAX_SCAN_ENTRIES; + uint8_t triggeredScanTrials = 0; + _i16 ret = 0; + + if ((count != 0) && (count < MAX_SCAN_ENTRIES)) + { + entries_count = count; + } + + /* Get scan results from NWP - results would be placed inside the local buffer first */ + ret = sl_WlanGetNetworkList(0, entries_count, netEntries); + + /* If scan policy isn't set, invoking 'sl_WlanGetNetworkList()' for the first time triggers 'one shot' scan. + * The scan parameters would be according to the system persistent settings on enabled channels. + * For more information, see: + */ + + if(SL_ERROR_WLAN_GET_NETWORK_LIST_EAGAIN == ret) + { + while(triggeredScanTrials < MAX_SCAN_ATTEMPTS) + { + /* We wait for one second for the NWP to complete the initiated scan and collect results */ + wait_ms(1000); + + /* Collect results form one-shot scans.*/ + ret = sl_WlanGetNetworkList(0, entries_count, netEntries); + if(ret > 0) + { + break; + } + else + { + /* If NWP results aren't ready, try 'MAX_SCAN_ATTEMPTS' to get results */ + triggeredScanTrials++ ; + printf("Tried %d times", triggeredScanTrials); + } + } + + if (count == 0 || res == NULL) + { + if (ret > 0) + { + return ret; + } + else + { + printf("\n\r[scan] : Unable to retrieve the network list\n\r"); + return 0; + } + } + } + if (ret <= 0) + { + printf("\n\r[scan] : Unable to retrieve the network list\n\r"); + return 0; + } + // scan is successful if code reaches here. + if (res && count) + { + unsigned i; + + for (i = 0; i < count; i ++) + { + nsapi_wifi_ap_t ap; + netEntries[i].Ssid[netEntries[i].SsidLen] = 0; /* Ensure the SSID is null terminated */ + memset((void*)&ap, 0x00, sizeof(nsapi_wifi_ap_t)); + memcpy(ap.ssid, netEntries[i].Ssid, netEntries[i].SsidLen); + memcpy(ap.bssid, netEntries[i].Bssid, 6); + switch (SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(netEntries[i].SecurityInfo)) + { + case SL_WLAN_SECURITY_TYPE_BITMAP_OPEN: + ap.security = NSAPI_SECURITY_NONE; + break; + case SL_WLAN_SECURITY_TYPE_BITMAP_WEP: + ap.security = NSAPI_SECURITY_WEP; + break; + case SL_WLAN_SECURITY_TYPE_BITMAP_WPA: + ap.security = NSAPI_SECURITY_WPA; + break; + case SL_WLAN_SECURITY_TYPE_BITMAP_WPA2: + ap.security = NSAPI_SECURITY_WPA2; + break; + case (SL_WLAN_SECURITY_TYPE_BITMAP_WPA | SL_WLAN_SECURITY_TYPE_BITMAP_WPA2): + ap.security = NSAPI_SECURITY_WPA_WPA2; + break; + default: + ap.security = NSAPI_SECURITY_UNKNOWN; + break; + } + ap.rssi = netEntries[i].Rssi; + ap.channel = netEntries[i].Channel; + res[i] = WiFiAccessPoint(ap); + } + return count; + } + else // Either res == NULL or count == 0, return the number of scanned networks + { + return ret; + } +} + +nsapi_error_t CC3200_SIMPLELINK::set_channel(int channel) +{ + if (_current_role == WIFI_ROLE_STATION) + { + return NSAPI_ERROR_UNSUPPORTED; + } + + _i16 Status = sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_CHANNEL, 1, (unsigned char*)&channel); + if (Status == SL_RET_CODE_OK) + { + _connected_channel = channel; + return NSAPI_ERROR_OK; + } + else if (Status == SL_ERROR_INVALID_PARAM) + { + return NSAPI_ERROR_PARAMETER; + } + else + { + return NSAPI_ERROR_DEVICE_ERROR; + } +} + +nsapi_error_t CC3200_SIMPLELINK::dns_lookup(const char *name, char *ip, uint32_t ip_size, nsapi_version_t version) +{ + _i16 Status; + SlNetAppDnsClientTime_t Time; + Time.MaxResponseTime = 2000; // Max DNS retry timeout, DNS request timeout changed every retry, start with 100Ms up to MaxResponseTime Ms + Time.NumOfRetries = 30; // number DNS retries before sl_NetAppDnsGetHostByName failed + Status = sl_NetAppSet(SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, sizeof(Time), (_u8*)&Time); + if( Status ) + { + return NSAPI_ERROR_DNS_FAILURE; + } + if (name && ip) + { + if ((version == NSAPI_IPv4 || version == NSAPI_UNSPEC) && ip_size >= NSAPI_IPv4_BYTES) + { + if (sl_NetAppDnsGetHostByName((_i8*)name, strlen(name), (_u32 *)ip, SL_AF_INET) == 0) + { + printf("%s has ip %d.%d.%d.%d\n", name, (int)SL_IPV4_BYTE(*(_u32 *)ip,3),(int)SL_IPV4_BYTE(*(_u32 *)ip,2),(int)SL_IPV4_BYTE(*(_u32 *)ip,1),(int)SL_IPV4_BYTE(*(_u32 *)ip,0)); + return NSAPI_ERROR_OK; + } + else + { + printf("sl_NetAppDnsGetHostByName failed\n"); + return NSAPI_ERROR_DNS_FAILURE; + } + } + if (version == NSAPI_IPv6 && ip_size >= NSAPI_IPv6_BYTES) + { + if (sl_NetAppDnsGetHostByName((_i8*)name, strlen(name), (_u32 *)ip, SL_AF_INET6) == 0) + { + return NSAPI_ERROR_OK; + } + else + { + return NSAPI_ERROR_DNS_FAILURE; + } + } + } + return NSAPI_ERROR_DNS_FAILURE; +} + +int8_t CC3200_SIMPLELINK::getRSSI() +{ + int i; + // Match connected network + for (i = 0; i < MAX_SCAN_ENTRIES; i++) + { + if (strcmp((char*)netEntries[i].Ssid, _connected_ssid) == 0 && netEntries[i].Channel == _connected_channel) + { + break; + } + } + if (i < MAX_SCAN_ENTRIES) + { + return netEntries[i].Rssi; + } + else + { + printf("Unscanned network, initiate network scan to get valid RSSI.\n"); + return 0; + } +} + +int8_t CC3200_SIMPLELINK::get_current_wifi_mode() +{ + return _current_role; +} + +nsapi_connection_status_t CC3200_SIMPLELINK::get_connection_status() const +{ + return _connection_status; +} + +void CC3200_SIMPLELINK::set_connection_status(nsapi_connection_status_t status) +{ + _connection_status = status; + if(_connection_status_cb) + { + _connection_status_cb(NSAPI_EVENT_CONNECTION_STATUS_CHANGE, _connection_status); + } +} + +void CC3200_SIMPLELINK::attach(mbed::Callback status_cb) +{ + _connection_status_cb = status_cb; +} + +nsapi_error_t CC3200_SIMPLELINK::open_socket(nsapi_protocol_t proto) +{ + int32_t sock = 0; + + if (proto == NSAPI_TCP) + { + sock = sl_Socket(SL_AF_INET, SL_SOCK_STREAM, 0); + } + else if (proto == NSAPI_UDP) + { + sock = sl_Socket(SL_AF_INET, SL_SOCK_DGRAM, 0); + } + if (sock >= 0) + { + return sock; + } + else + { + printf("open_socket failed with %d\n", (int)sock); + return NSAPI_ERROR_NO_SOCKET; + } +} + +bool CC3200_SIMPLELINK::close_socket(uint32_t sock) +{ + int32_t retcode = 0; + + retcode = sl_Close(sock); + if (retcode == 0) + { + return true; + } + else + { + printf("close_socket failed with %d\n", (int)retcode); + return false; + } +} +nsapi_error_t CC3200_SIMPLELINK::setsockopt(uint32_t sd, int level, + int optname, const void *optval, unsigned optlen) +{ + _i16 retcode = sl_SetSockOpt((_i16)sd, level, optname, optval, optlen); + if (retcode == 0) + { + return NSAPI_ERROR_OK; + } + else + { + printf ("sl_SetSockOpt failed with %d\n", (int)retcode); + return NSAPI_ERROR_DEVICE_ERROR; + } +} + +nsapi_error_t CC3200_SIMPLELINK::getsockopt(uint32_t sd, int level, + int optname, void *optval, unsigned* optlen) +{ + _i16 retcode =sl_GetSockOpt((_i16)sd, level, optname, optval, (SlSocklen_t*)optlen); + if (retcode == 0) + { + return NSAPI_ERROR_OK; + } + else + { + printf ("sl_GetSockOpt failed with %d\n", (int)retcode); + return NSAPI_ERROR_DEVICE_ERROR; + } +} + +nsapi_error_t CC3200_SIMPLELINK::connect_socket(uint32_t sd, const SocketAddress &sock_addr) +{ + sockAddr_t sAddr; + SlSockAddr_t* sa; + int32_t addrSize; + int32_t status = -1; + short int nonBlocking = SOCKET_IS_NON_BLOCKING; + + _fill_sl_address(sAddr, sa, addrSize, sock_addr); + + if (1 == nonBlocking) + { + // non-blocking + status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, &nonBlocking, sizeof(nonBlocking)); + if(status < 0) + { + printf("sl_SetSockOpt failed with %d\n\r", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + } + status = -1; + while (status < 0) + { + status = sl_Connect((short int)sd, sa, (short int)addrSize); + // on a non-blocking connect, retry if SL_ERROR_BSD_EALREADY is returned + { + if (status == SL_ERROR_BSD_EALREADY && 1 == nonBlocking) + { + wait_ms(1); + continue; + } + else if (status < 0) + { + printf("sl_Connect failed with %d\n", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + } + } + return NSAPI_ERROR_OK; +} + +nsapi_error_t CC3200_SIMPLELINK::bind_socket(uint32_t sd, const SocketAddress &sock_addr) +{ + sockAddr_t sAddr; + SlSockAddr_t* sa; + int32_t addrSize; + int32_t status = -1; + + _fill_sl_address(sAddr, sa, addrSize, sock_addr); + + status = sl_Bind(sd, sa, addrSize); + if (status == 0) + { + return NSAPI_ERROR_OK; + } + else + { + printf ("sl_Bind failed with %d\n", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } +} + +int CC3200_SIMPLELINK::sendto_socket(uint32_t sd, const void * buf, uint32_t bufLen, const SocketAddress &sock_addr) +{ + sockAddr_t sAddr; + SlSockAddr_t* sa; + int32_t addrSize; + int32_t status = -1; + + _fill_sl_address(sAddr, sa, addrSize, sock_addr); + + while (1) + { + status = sl_SendTo(sd, buf, bufLen, 0, sa, addrSize); + if (status == SL_ERROR_BSD_EAGAIN && 1 == SOCKET_IS_NON_BLOCKING) + { + wait_ms(1); + continue; + } + else if (status < 0) + { + printf ("sl_SendTo failed with %d\n", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + break; + } + return status; +} + +int32_t CC3200_SIMPLELINK::send(int sd, const void *data, uint32_t size) +{ + int32_t status = -1; + + while (1) + { + status = sl_Send(sd, data, size, 0); + if (status == SL_ERROR_BSD_EAGAIN && 1 == SOCKET_IS_NON_BLOCKING) + { + wait_ms(1); + continue; + } + else if (status < 0) + { + printf ("sl_Send failed with %d\n", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + break; + } + return status; +} + +int32_t CC3200_SIMPLELINK::recv(int sd, void *data, uint32_t size) +{ + int32_t status = -1; + SlSockNonblocking_t BlockingOption; + struct SlTimeval_t TimeVal; + + BlockingOption.NonBlockingEnabled = SOCKET_IS_NON_BLOCKING; + + if (1 == SOCKET_IS_NON_BLOCKING) + { + // non-blocking + status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, (_u8*)&BlockingOption,sizeof(BlockingOption)); + if(status < 0) + { + printf("sl_SetSockOpt failed with %d\n\r", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + } + else + { + /* In case of blocking, a timeout for sl_RecvFrom will be set to TimeVal + * When timeout is expired sl_Recv will return SL_ERROR_BSD_EAGAIN */ + TimeVal.tv_sec = _timeout; + TimeVal.tv_usec = 0; + status = sl_SetSockOpt(sd,SL_SOL_SOCKET,SL_SO_RCVTIMEO, + (uint8_t *)&TimeVal, + sizeof(TimeVal)); + if(status < 0) + { + printf ("sl_SetSockOpt failed with %d\n", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + } + + memset((void *)data, 0, size); + + status = sl_Recv(sd, data, size, 0); + if(status == SL_ERROR_BSD_EAGAIN) + { + if (1 == SOCKET_IS_NON_BLOCKING) + { + return NSAPI_ERROR_WOULD_BLOCK; + } + else + { + printf ("Timeout expired before receiving packet\n"); + return NSAPI_ERROR_TIMEOUT; + } + } + else if(status < 0) + { + printf ("sl_Recv failed with %d\n", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + else + { + return status; + } +} + +int32_t CC3200_SIMPLELINK::recvfrom(uint32_t sd, void * buf, uint32_t size, SocketAddress &sock_addr) +{ + sockAddr_t sAddr; + SlSockAddr_t* sa; + int32_t addrSize; + int32_t status = -1; + SlSockNonblocking_t BlockingOption; + struct SlTimeval_t TimeVal; + nsapi_addr_t nsapi_addr = sock_addr.get_addr(); + + + BlockingOption.NonBlockingEnabled = SOCKET_IS_NON_BLOCKING; + + if (1 == SOCKET_IS_NON_BLOCKING) + { + // non-blocking + status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, (_u8*)&BlockingOption,sizeof(BlockingOption)); + if(status < 0) + { + printf("sl_SetSockOpt failed with %d\n\r", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + } + else + { + /* In case of blocking, a timeout for sl_RecvFrom will be set to TimeVal + * When timeout is expired sl_RecvFrom will return SL_ERROR_BSD_EAGAIN */ + TimeVal.tv_sec = _timeout; + TimeVal.tv_usec = 0; + status = sl_SetSockOpt(sd,SL_SOL_SOCKET,SL_SO_RCVTIMEO, + (uint8_t *)&TimeVal, + sizeof(TimeVal)); + if(status < 0) + { + printf ("sl_SetSockOpt failed with %d\n", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + } + + memset((void*)buf, 0, size); + + _fill_sl_address(sAddr, sa, addrSize, sock_addr); + + // sl_RecvFrom requires size to be 1-16000 bytes. Can't pass 0 + if (size == 0) + { + status = sl_RecvFrom(sd, buf, 1, 0, sa, (SlSocklen_t*)&addrSize); + } + else + { + status = sl_RecvFrom(sd, buf, size, 0, sa, (SlSocklen_t*)&addrSize); + } + if(status == SL_ERROR_BSD_EAGAIN) + { + if (1 == SOCKET_IS_NON_BLOCKING) + { + return NSAPI_ERROR_WOULD_BLOCK; + } + else + { + printf ("Timeout expired before receiving packet\n"); + return NSAPI_ERROR_TIMEOUT; + } + } + else if(status < 0) + { + printf ("sl_RecvFrom failed with %d\n", (int)status); + return NSAPI_ERROR_DEVICE_ERROR; + } + else if ((status > 0 && size > 0) || (status == 0 && size == 0)) + { + // Fill the ip and port + memset((void*)&nsapi_addr, 0, sizeof(nsapi_addr)); + bool ipv6 = (sock_addr.get_ip_version() == NSAPI_IPv6); + if (ipv6) + { + sock_addr.set_port(sl_Ntohs(sAddr.in6.sin6_port)); + nsapi_addr.version = NSAPI_IPv6; + *(unsigned long *)&nsapi_addr.bytes[0] = sAddr.in6.sin6_addr._S6_un._S6_u32[0]; + *(unsigned long *)&nsapi_addr.bytes[4] = sAddr.in6.sin6_addr._S6_un._S6_u32[1]; + *(unsigned long *)&nsapi_addr.bytes[8] = sAddr.in6.sin6_addr._S6_un._S6_u32[2]; + *(unsigned long *)&nsapi_addr.bytes[12] = sAddr.in6.sin6_addr._S6_un._S6_u32[3]; + sock_addr.set_addr(nsapi_addr); + } + else + { + sock_addr.set_port(sl_Ntohs(sAddr.in4.sin_port)); + nsapi_addr.version = NSAPI_IPv4; + *(unsigned int*)nsapi_addr.bytes = sAddr.in4.sin_addr.s_addr; + sock_addr.set_addr(nsapi_addr); + } + } + return status; +} + +void CC3200_SIMPLELINK::setTimeout(uint32_t timeout_ms) +{ + _timeout = timeout_ms; +} + +void CC3200_SIMPLELINK::_fill_sl_address(sockAddr_t &sAddr, SlSockAddr_t* &sa, int32_t &addrSize, const SocketAddress &sock_addr) +{ + nsapi_addr_t nsapi_addr = sock_addr.get_addr(); + bool ipv6 = (sock_addr.get_ip_version() == NSAPI_IPv6); + + memset((void*)&sAddr, 0, sizeof(sAddr)); + + if (ipv6) + { + sAddr.in6.sin6_family = SL_AF_INET6; + sAddr.in6.sin6_port = sl_Htons(sock_addr.get_port()); + sAddr.in6.sin6_flowinfo = 0; + + sAddr.in6.sin6_addr._S6_un._S6_u32[0] = *(unsigned long *)&nsapi_addr.bytes[0]; + sAddr.in6.sin6_addr._S6_un._S6_u32[1] = *(unsigned long *)&nsapi_addr.bytes[4]; + sAddr.in6.sin6_addr._S6_un._S6_u32[2] = *(unsigned long *)&nsapi_addr.bytes[8]; + sAddr.in6.sin6_addr._S6_un._S6_u32[3] = *(unsigned long *)&nsapi_addr.bytes[12]; + sa = (SlSockAddr_t*)&sAddr.in6; + addrSize = sizeof(SlSockAddrIn6_t); + } + else + { + sAddr.in4.sin_family = SL_AF_INET; + sAddr.in4.sin_port = sl_Htons(sock_addr.get_port()); + sAddr.in4.sin_addr.s_addr = *(unsigned int*)nsapi_addr.bytes; + sa = (SlSockAddr_t*)&sAddr.in4; + addrSize = sizeof(SlSockAddrIn_t); + } +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.h new file mode 100644 index 00000000000..424a99071b6 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.h @@ -0,0 +1,330 @@ + +/* CC3200_SIMPLELINK Class + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef CC3200_SIMPLELINK_H +#define CC3200_SIMPLELINK_H +#include "mbed.h" +#include +#include "nsapi_types.h" +#include "nsapi.h" +#include "rtos.h" +#include "netsocket/WiFiAccessPoint.h" +#include "ti/drivers/net/wifi/netcfg.h" +#include "ti/drivers/ti_SPI.h" +#include "ti/drivers/dma/UDMACC32XX.h" +#include "ti/drivers/net/wifi/sl_socket.h" +#include "ti/drivers/net/wifi/netapp.h" +#include "ti/drivers/net/wifi/wlan.h" + +#define MAX_SCAN_TIMEOUT (15000) +#define MAX_SCAN_ENTRIES (15) +#define MAX_SCAN_ATTEMPTS (10) + +#ifndef CC3200_SIMPLELINK_MISC_TIMEOUT +#define CC3200_SIMPLELINK_MISC_TIMEOUT 2000 +#endif + +/** + * This is the interface class to CC3200 Simplelink + */ +class CC3200_SIMPLELINK +{ +public: + CC3200_SIMPLELINK(); + + /** + * Initialize CC3200_SIMPLELINK to default state (STATION mode) + */ + nsapi_error_t initialize(); + + /** + * Startup the CC3200_SIMPLELINK + * + * @param role role of WIFI 0-Station, 2-AP, 3-P2P + * @return true only if it was setup correctly + */ + bool startup(int role); + + /** + * Reset CC3200_SIMPLELINK + * + * @return true only if CC3200_SIMPLELINK resets successfully + */ + //bool reset(void); + + /** + * Enable/Disable DHCP + * + * @param enabled DHCP enabled when true + * @param mode mode of DHCP 0-softAP, 1-station, 2-both + * @return true only if CC3200_SIMPLELINK enables/disables DHCP successfully + */ + bool dhcp(bool enabled, int mode); + + /** + * Connect CC3200 SimpleLink to AP + * + * @param ap the name of the AP + * @param passPhrase the password of AP + * @param security security type + * @return NSAPI_ERROR_OK only if CC3200 SimpleLink is connected successfully + */ + nsapi_error_t connect(const char *ap, const char *passPhrase, nsapi_security_t security); + + /** + * Disconnect CC3200 SimpleLink from AP + * + * @return true only if CC3200_SIMPLELINK is disconnected successfully + */ + bool disconnect(void); + + /** + * Get the IP address of CC3200 SimpleLink + * + * @return null-teriminated IP address or null if no IP address is assigned + */ + const char *getIPAddress(void); + + /** + * Get the MAC address of CC3200 SimpleLink + * + * @return null-terminated MAC address or null if no MAC address is assigned + */ + const char *getMACAddress(void); + + /** Get the local gateway + * + * @return Null-terminated representation of the local gateway + * or null if no network mask has been received + */ + const char *getGateway(); + + /** Get the local network mask + * + * @return Null-terminated representation of the local network mask + * or null if no network mask has been recieved + */ + const char *getNetmask(); + + /** Get DNS server address + * + * @param ipaddr Pointer to allocated array to store DNS server raw address + * @param len Size of the storage area + * @return NSAPI_ERROR_OK on success or other error codes on failure + */ + nsapi_error_t getDNS(unsigned char* ip4addr, uint32_t len); + + /* Return RSSI for active connection + * + * @return Measured RSSI + */ + int8_t getRSSI(); + + /** Scan for available networks + * + * @param ap Pointer to allocated array to store discovered AP + * @param limit Size of allocated @a res array, or 0 to only count available AP + * @return Number of entries in @a res, or if @a count was 0 number of available networks, negative on error + * see @a nsapi_error + */ + int scan(WiFiAccessPoint *res, unsigned count); + + /** Set channel + * + * @param channel channel to set + * @return NSAPI error code + */ + nsapi_error_t set_channel(int channel); + + /**Perform a dns query + * + * @param name Hostname to resolve + * @param ip Buffer to store IP address + * @return NSAPI error code + */ + nsapi_error_t dns_lookup(const char *name, char *ip, uint32_t ip_size, nsapi_version_t version); + + /** + * Open a socket + * + * @return handle of the opened socket only if socket opened successfully, 0 or error otherwise + */ + nsapi_error_t open_socket(nsapi_protocol_t proto); + + /** + * Close a socket + * + * @return true if socket was closed successfully, false otherwise + */ + bool close_socket(uint32_t sock); + + /** + * Set socket options + * + * @param sd socket descritor + * @param level protocol level for this option + * @param optname option name to interrogate + * @param optval points to the value for the option + * @param optlen length of the option value + * @return nsapi status + */ + nsapi_error_t setsockopt(uint32_t sd, int level, + int optname, const void *optval, unsigned optlen); + + /** + * Get socket options + * + * @param sd socket descriptor + * @param level protocol level for this option + * @param optname option name to interrogate + * @param optval points to the value for the option + * @param optlen length of the option value + * @return nsapi status + */ + nsapi_error_t getsockopt(uint32_t sd, int level, + int optname, void *optval, unsigned* optlen); + /** + * Initiate a connection on a socket (blocking) + * + * @param sd socket handle + * @param sock_addr SocketAddress structure + * @return nsapi status + */ + nsapi_error_t connect_socket(uint32_t sd, const SocketAddress &sock_addr); + + /** + * Assigns a socket an local address + * + * @param sd socket handle + * @param sock_addr SocketAddress structure + * + * @return nsapi status + */ + nsapi_error_t bind_socket(uint32_t sd, const SocketAddress &sock_addr); + + /** + * Write data to socket Initiate a connection on a socket (nonblocking) + * + * @param sd socket handle + * @param buf pointer to a buffer containing the data to be sent + * @param bufLen data length in bytes + * @param sock_addr SocketAddress structure + * @return a socket handle + */ + int sendto_socket(uint32_t sd, const void * buf, uint32_t bufLen, const SocketAddress &sock_addr); + + /** + * Sends data to an open socket (nonblocking) + * + * @param sd sd of socket to send to + * @param data data to be sent + * @param size number of bytes to be sent - max 1024 + * @return number of sent bytes on success, negative error code on failure + */ + int32_t send(int id, const void *data, uint32_t size); + + /** + * Receives stream data from an open TCP socket (nonblocking) + * + * @param sd sd to receive from + * @param data placeholder for returned information + * @param size number of bytes to be received + * @return the number of bytes received + */ + int32_t recv(int sd, void *data, uint32_t size); + + /** + * Receives data from socket + * + * @param sd sd to receive from + * @param buf placeholder for returned information + * @param size number of bytes to be received + * @param sock_addr SocketAddress structure + * @return the number of bytes received + */ + int32_t recvfrom(uint32_t sd, void * buf, uint32_t size, SocketAddress &sock_addr); + + /** + * Allows timeout to be changed between commands + * + * @param timeout_ms timeout of the connection + */ + void setTimeout(uint32_t timeout_ms=CC3200_SIMPLELINK_MISC_TIMEOUT); + + /** + * Attach a function to call whenever network state has changed + * + * @param func A pointer to a void function, or 0 to set as none + */ + void attach(mbed::Callback status_cb); + + /** + * Read default Wifi role + * + * return Station, AP or P2P + */ + int8_t get_current_wifi_mode(); + + /** + * Write default Wifi + */ + //bool set_default_wifi_mode(const int8_t mode); + + /** Get the connection status + * + * @return The connection status according to ConnectionStatusType + */ + nsapi_connection_status_t get_connection_status() const; + + /** Set the connection status + * + * @param status The connection status to set + */ + void set_connection_status(nsapi_connection_status_t status); + + static const int8_t WIFI_ROLE_STATION = 1; + static const int8_t WIFI_ROLE_AP = 2; + static const int8_t WIFI_ROLE_P2P = 3; + +private: + + typedef union{ + SlSockAddrIn6_t in6; /* Socket info for Ipv6 */ + SlSockAddrIn_t in4; /* Socket info for Ipv4 */ + }sockAddr_t; + + char _ip_buffer[NSAPI_IPv4_SIZE]; + char _gateway_buffer[NSAPI_IPv4_SIZE]; + char _netmask_buffer[NSAPI_IPv4_SIZE]; + char _mac_buffer[NSAPI_MAC_SIZE]; + char _dns_server_buffer[NSAPI_IPv4_SIZE]; + + int _connect_error; + bool _initialized; + int _current_role; + bool _fail; + bool _closed; + nsapi_connection_status_t _connection_status; + mbed::Callback _connection_status_cb; + char _connected_ssid[SL_WLAN_SSID_MAX_LENGTH+1]; /* 32 is what 802.11 defines as longest possible name; +1 for the \0 */ + int _connected_channel; + SlWlanNetworkEntry_t netEntries[MAX_SCAN_ENTRIES]; + int _timeout; + void _fill_sl_address(sockAddr_t &sAddr, SlSockAddr_t* &sa, int32_t &addrSize, const SocketAddress &sock_addr); +}; +#endif /* CC3200_SIMPLELINK_H_ */ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis.h new file mode 100644 index 00000000000..da2cc131f6c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis.h @@ -0,0 +1,41 @@ +/* CC3220SF CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in CC3220SF specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CC3220SF.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis_nvic.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis_nvic.h new file mode 100644 index 00000000000..64f735054de --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* CC3220SF CMSIS Library +* +* Copyright (c) 2006-2018 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (195) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/default_wifi_interface.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/default_wifi_interface.cpp new file mode 100644 index 00000000000..228042cd02c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/default_wifi_interface.cpp @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "CC3220SF_WiFiInterface.h" + +WiFiInterface *WiFiInterface::get_target_default_instance() +{ + static CC3220SFInterface wifi; + return &wifi; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c new file mode 100644 index 00000000000..8adc062c89d --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_CC3220SF.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + * Device CC3220SF + * @version V5.00 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "CC3220SF.h" +#include "../inc/hw_types.h" +#include "CC3220SF_LAUNCHXL.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +/* ToDo: add here your necessary defines for device initialization + following is an example for different system frequencies */ +#define XTAL (40000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (2 * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +/* ToDo: initialize SystemCoreClock with the system core clock frequency value + achieved after system intitialization. + This means system core clock frequency after call to SystemInit() */ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/ + + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ + +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ +} + +void SystemInit (void) +{ + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; + CC3220SF_LAUNCHXL_initGeneral(); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h new file mode 100644 index 00000000000..95ee0672a27 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h @@ -0,0 +1,79 @@ +/**************************************************************************//** + * @file system_CC3220SF.h + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for + * Device CC3220SF + * @version V5.00 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_CC3220SF_H /* ToDo: replace '' with your device name */ +#define SYSTEM_CC3220SF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "ti/drivers/net/wifi/wlan.h" + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +extern void PRCMMCUReset(unsigned char bIncludeSubsystem); +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __CC3200_SystemReset(void) +{ + /* Stop the NWP */ + _i16 retcode = sl_Stop(0); + if (retcode != 0 && retcode != SL_RET_CODE_DEV_NOT_STARTED) + { + printf("sl_stop failed with 0x%x\n", retcode); + } + + PRCMMCUReset(0); +} +#ifdef NVIC_SystemReset +#undef NVIC_SystemReset +#endif +#define NVIC_SystemReset __CC3200_SystemReset + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM__H */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/wifi_event_handler.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/wifi_event_handler.cpp new file mode 100755 index 00000000000..3cb50f356c8 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/wifi_event_handler.cpp @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/***************************************************************************** + + Application Name - Network terminal + + Application Overview - Network Terminal is a command line interface (cli) based application, + used to demonstrate the CC32XX/CC31XX networking capabilities. + It does that by offering a list of commands, divided into four silos: + + Wlan : Contains link layer functions like scan, connect, etc. + NetApp : Demonstrates the usage of networking applications. + Socket : Shows variety of socket API and responsible for sending and receiving packets. + Transceiver : Gives the user a direct interface to the NWP radio for RF tests, raw sockets (L1) and more. + + Application Details - Refer to 'Network Terminal' README.html + +*****************************************************************************/ + +/* Standard includes */ +#include +#include +#include +#include "rtos.h" + +#include +#include + +#define HANDLER_TRACE_ENABLE 0 + +/**************************************************************************** + LOCAL FUNCTION PROTOTYPES +****************************************************************************/ + + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ + + + +/***************************************************************************** + Callback Functions +*****************************************************************************/ + +/*! + \brief SimpleLinkWlanEventHandler + + This handler gets called whenever a WLAN event is reported + by the host driver / NWP. Here user can implement he's own logic + for any of these events. This handler is used by 'network_terminal' + application to show case the following scenarios: + + 1. Handling connection / Disconnection. + 2. Handling Addition of station / removal. + 3. RX filter match handler. + 4. P2P connection establishment. + + \param pWlanEvent - pointer to Wlan event data. + + \return void + + \note For more information, please refer to: user.h in the porting + folder of the host driver and the CC3120/CC3220 NWP programmer's + guide (SWRU455) sections 4.3.4, 4.4.5 and 4.5.5. + + \sa cmdWlanConnectCallback, cmdEnableFilterCallback, cmdWlanDisconnectCallback, + cmdP2PModecallback. + +*/ +void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) +{ + if(!pWlanEvent) + { + return; + } + + switch(pWlanEvent->Id) + { + case SL_WLAN_EVENT_CONNECT: + { + #if HANDLER_TRACE_ENABLE == 1 + printf("\n\r[WLAN EVENT] STA Connected to the AP: %s , " + "BSSID: %x:%x:%x:%x:%x:%x\n\r", + pWlanEvent->Data.Connect.SsidName, pWlanEvent->Data.Connect.Bssid[0], + pWlanEvent->Data.Connect.Bssid[1],pWlanEvent->Data.Connect.Bssid[2], + pWlanEvent->Data.Connect.Bssid[3],pWlanEvent->Data.Connect.Bssid[4], + pWlanEvent->Data.Connect.Bssid[5]); + #endif + CC3220SFInterface::cc3200sf_wifi_instance->_connect_sem.release(); + } + break; + + case SL_WLAN_EVENT_DISCONNECT: + { + SlWlanEventDisconnect_t *pEventData = NULL; + + pEventData = &pWlanEvent->Data.Disconnect; + + /* If the user has initiated 'Disconnect' request, + 'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED */ + if(SL_WLAN_DISCONNECT_USER_INITIATED == pEventData->ReasonCode) + { + #if HANDLER_TRACE_ENABLE == 1 + printf("\n\r[WLAN EVENT] Device disconnected from the AP\n\r"); + #endif + } + else + { + printf("\n\r[WLAN ERROR] Device disconnected from the AP\n\r"); + } + } + break; + + case SL_WLAN_EVENT_PROVISIONING_STATUS: + { + /* Do nothing, this suppress provisioning event is because simplelink is configured to default state. */ + } + break; + + case SL_WLAN_EVENT_STA_ADDED: + { + printf("\n\r[WLAN EVENT] STA was added to AP: BSSID: %x:%x:%x:%x:%x:%x\n\r", + pWlanEvent->Data.STAAdded.Mac[0],pWlanEvent->Data.STAAdded.Mac[1], + pWlanEvent->Data.STAAdded.Mac[2],pWlanEvent->Data.STAAdded.Mac[3], + pWlanEvent->Data.STAAdded.Mac[4],pWlanEvent->Data.STAAdded.Mac[5]); + } + break; + + case SL_WLAN_EVENT_STA_REMOVED: + { + printf("\n\r[WLAN EVENT] STA was removed from AP\n\r"); + } + break; + + case SL_WLAN_EVENT_RXFILTER: + { + SlWlanEventRxFilterInfo_t *triggred_filter = NULL; + + triggred_filter = &(pWlanEvent->Data.RxFilterInfo) ; + + printf("\n\r[WLAN EVENT] Rx filter match triggered. Set filters in filter bitmap :0x%x.\n\r", triggred_filter->UserActionIdBitmap[0]); + + /* + * User can write he's / her's rx filter match handler here. + * Be advised, you can use the 'triggred_filter' structure info to determine which filter + * has received a match. (Bit X is set if user action id X was passed to a filter that matched a packet.) + */ + } + break; + + case SL_WLAN_EVENT_P2P_DEVFOUND: + { + printf("\n\r[WLAN EVENT] P2P Remote device found\n\r"); + } + break; + + case SL_WLAN_EVENT_P2P_REQUEST: + { + printf("\n\r[WLAN EVENT] P2P Negotiation request received\n\r"); + } + break; + + case SL_WLAN_EVENT_P2P_CONNECT: + { + printf("n\r[WLAN EVENT] P2P connection was successfully completed as CLIENT\n\r"); + printf("n\rBSSID is %02x:%02x:%02x:%02x:%02x:%02x\n\r", + pWlanEvent->Data.STAAdded.Mac[0], + pWlanEvent->Data.STAAdded.Mac[1], + pWlanEvent->Data.STAAdded.Mac[2], + pWlanEvent->Data.STAAdded.Mac[3], + pWlanEvent->Data.STAAdded.Mac[4], + pWlanEvent->Data.STAAdded.Mac[5]); + } + break; + + case SL_WLAN_EVENT_P2P_CLIENT_ADDED: + { + printf("n\r[WLAN EVENT] P2P connection was successfully completed as GO\n\r"); + printf("n\rBSSID is %02x:%02x:%02x:%02x:%02x:%02x\n\r", + pWlanEvent->Data.P2PClientAdded.Mac[0], + pWlanEvent->Data.P2PClientAdded.Mac[1], + pWlanEvent->Data.P2PClientAdded.Mac[2], + pWlanEvent->Data.P2PClientAdded.Mac[3], + pWlanEvent->Data.P2PClientAdded.Mac[4], + pWlanEvent->Data.P2PClientAdded.Mac[5]); + } + break; + + case SL_WLAN_EVENT_P2P_DISCONNECT: + { + printf("\n\r[WLAN EVENT] STA disconnected from device.\n\r"); + } + break; + + default: + { + printf("\n\r[WLAN EVENT] Unexpected event [0x%x]\n\r", (unsigned int)pWlanEvent->Id); + } + break; + } +} + +/*! + \brief SimpleLinkNetAppEventHandler + + This handler gets called whenever a Netapp event is reported + by the host driver / NWP. Here user can implement he's own logic + for any of these events. This handler is used by 'network_terminal' + application to show case the following scenarios: + + 1. Handling IPv4 / IPv6 IP address acquisition. + 2. Handling IPv4 / IPv6 IP address Dropping. + + \param pNetAppEvent - pointer to Netapp event data. + + \return void + + \note For more information, please refer to: user.h in the porting + folder of the host driver and the CC3120/CC3220 NWP programmer's + guide (SWRU455) section 5.7 + +*/ +void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) +{ + if(!pNetAppEvent) + { + return; + } + + switch(pNetAppEvent->Id) + { + case SL_NETAPP_EVENT_IPV4_ACQUIRED: + { + #if HANDLER_TRACE_ENABLE == 1 + SlIpV4AcquiredAsync_t *pEventData = NULL; + + /* Ip Acquired Event Data */ + pEventData = &pNetAppEvent->Data.IpAcquiredV4; + + printf("\n\r[NETAPP EVENT] IP set to: IPv4=%d.%d.%d.%d , " + "Gateway=%d.%d.%d.%d\n\r", + + (unsigned int)SL_IPV4_BYTE(pEventData->Ip,3), + (unsigned int)SL_IPV4_BYTE(pEventData->Ip,2), + (unsigned int)SL_IPV4_BYTE(pEventData->Ip,1), + (unsigned int)SL_IPV4_BYTE(pEventData->Ip,0), + + (unsigned int)SL_IPV4_BYTE(pEventData->Gateway,3), + (unsigned int)SL_IPV4_BYTE(pEventData->Gateway,2), + (unsigned int)SL_IPV4_BYTE(pEventData->Gateway,1), + (unsigned int)SL_IPV4_BYTE(pEventData->Gateway,0)); + #endif + CC3220SFInterface::cc3200sf_wifi_instance->_ip_set_sem.release(); + } + break; + + case SL_NETAPP_EVENT_IPV6_ACQUIRED: + { + uint32_t i = 0; + + printf("\n\r[NETAPP EVENT] IP Acquired: IPv6="); + + for(i = 0; i < 3 ; i++) + { + printf("%04x:%04x:\n", ((unsigned int)(pNetAppEvent->Data.IpAcquiredV6.Ip[i]>>16) & 0xffff), (unsigned int)pNetAppEvent->Data.IpAcquiredV6.Ip[i] & 0xffff); + } + + printf("%04x:%04x\n", ((unsigned int)(pNetAppEvent->Data.IpAcquiredV6.Ip[3]>>16) & 0xffff), (unsigned int)pNetAppEvent->Data.IpAcquiredV6.Ip[3] & 0xffff); + } + break; + + case SL_NETAPP_EVENT_DHCPV4_LEASED: + { + printf("\n\r[NETAPP EVENT] IP Leased to Client: IP=%d.%d.%d.%d \n\r", + (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,3), (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,2), + (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,1), (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,0)); + } + break; + + case SL_NETAPP_EVENT_DHCPV4_RELEASED: + { + printf("\n\r[NETAPP EVENT] IP is released.\n\r"); + } + break; + + default: + { + printf("\n\r[NETAPP EVENT] Unexpected event [0x%x] \n\r", (unsigned int)pNetAppEvent->Id); + } + break; + } +} + +/*! + \brief SimpleLinkHttpServerEventHandler + + This handler gets called whenever a HTTP event is reported + by the NWP internal HTTP server. + + \param pHttpEvent - pointer to http event data. + + \param pHttpEvent - pointer to http response. + + \return void + + \note For more information, please refer to: user.h in the porting + folder of the host driver and the CC3120/CC3220 NWP programmer's + guide (SWRU455) chapter 9. + +*/ +void SimpleLinkHttpServerEventHandler(SlNetAppHttpServerEvent_t *pHttpEvent, + SlNetAppHttpServerResponse_t *pHttpResponse) +{ + /* Unused in this application */ +} + +/*! + \brief SimpleLinkGeneralEventHandler + + This handler gets called whenever a general error is reported + by the NWP / Host driver. Since these errors are not fatal, + application can handle them. + + \param pDevEvent - pointer to device error event. + + \return void + + \note For more information, please refer to: user.h in the porting + folder of the host driver and the CC3120/CC3220 NWP programmer's + guide (SWRU455) section 17.9. + +*/ +void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent) +{ + if(!pDevEvent) + { + return; + } + /* + Most of the general errors are not FATAL are are to be handled + appropriately by the application + */ + printf("\n\r[GENERAL EVENT] - ID=[%d] Sender=[%d]\n\n", + pDevEvent->Data.Error.Code, + pDevEvent->Data.Error.Source); +} + +/*! + \brief SimpleLinkSockEventHandler + + This handler gets called whenever a socket event is reported + by the NWP / Host driver. + + \param SlSockEvent_t - pointer to socket event data. + + \return void + + \note For more information, please refer to: user.h in the porting + folder of the host driver and the CC3120/CC3220 NWP programmer's + guide (SWRU455) section 7.6. + +*/ +void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) +{ + #if HANDLER_TRACE_ENABLE == 1 + printf("\n\r[INFO] - event detected: " + "Event=%d, AbortData=0x%x\n\r", + (unsigned int)pSock->Event, + (unsigned int)pSock->SocketAsyncEvent.SockTxFailData.Status); + #endif + +} + +/*! + \brief SimpleLinkFatalErrorEventHandler + + This handler gets called whenever a socket event is reported + by the NWP / Host driver. After this routine is called, the user's + application must restart the device in order to recover. + + \param slFatalErrorEvent - pointer to fatal error event. + + \return void + + \note For more information, please refer to: user.h in the porting + folder of the host driver and the CC3120/CC3220 NWP programmer's + guide (SWRU455) section 17.9. + +*/ +void SimpleLinkFatalErrorEventHandler(SlDeviceFatal_t *slFatalErrorEvent) +{ + + switch (slFatalErrorEvent->Id) + { + case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: + { + printf("\n\r[ERROR] - FATAL ERROR: Abort NWP event detected: " + "AbortType=%d, AbortData=0x%x\n\r", + (unsigned int)slFatalErrorEvent->Data.DeviceAssert.Code, + (unsigned int)slFatalErrorEvent->Data.DeviceAssert.Value); + } + break; + + case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: + { + printf("\n\r[ERROR] - FATAL ERROR: Driver Abort detected. \n\r"); + } + break; + + case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: + { + printf("\n\r[ERROR] - FATAL ERROR: No Cmd Ack detected " + "[cmd opcode = 0x%x] \n\r", + (unsigned int)slFatalErrorEvent->Data.NoCmdAck.Code); + } + break; + + case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: + { + printf("\n\r[ERROR] - FATAL ERROR: Sync loss detected n\r"); + } + break; + + case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: + { + printf("\n\r[ERROR] - FATAL ERROR: Async event timeout detected " + "[event opcode =0x%x] \n\r", + (unsigned int)slFatalErrorEvent->Data.CmdTimeout.Code); + } + break; + + default: + printf("\n\r[ERROR] - FATAL ERROR: Unspecified error detected \n\r"); + break; + } +} + +/*! + \brief SimpleLinkNetAppRequestEventHandler + + This handler gets called whenever a NetApp event is reported + by the NWP / Host driver. User can write he's logic to handle + the event here. + + \param pNetAppRequest - Pointer to NetApp request structure. + + \param pNetAppResponse - Pointer to NetApp request Response. + + \note For more information, please refer to: user.h in the porting + folder of the host driver and the CC3120/CC3220 NWP programmer's + guide (SWRU455) section 17.9. + + \return void + +*/ +void SimpleLinkNetAppRequestEventHandler(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse) +{ + /* Unused in this application */ +} + +/*! + \brief SimpleLinkNetAppRequestMemFreeEventHandler + + This handler gets called whenever the NWP is done handling with + the buffer used in a NetApp request. This allows the use of + dynamic memory with these requests. + + \param pNetAppRequest - Pointer to NetApp request structure. + + \param pNetAppResponse - Pointer to NetApp request Response. + + \note For more information, please refer to: user.h in the porting + folder of the host driver and the CC3120/CC3220 NWP programmer's + guide (SWRU455) section 17.9. + + \return void + +*/ +void SimpleLinkNetAppRequestMemFreeEventHandler(uint8_t *buffer) +{ + /* Unused in this application */ +} + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c new file mode 100644 index 00000000000..6ec865d6f81 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if DEVICE_FLASH + +#include "stdbool.h" +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "flash_api.h" +#include "ti/devices/cc32xx/driverlib/flash.h" + +#define CC3200_FLASH_SECTOR_SIZE 0x800 +#define CC3200_FLASH_PAGE_SIZE 0x4 +#define CC3200_FLASH_START_ADDRESS 0x01000000 +#define CC3200_FLASH_SIZE (1024*1024) + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + //FlashDisable(); + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + return FlashErase(address); +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + return FlashProgram((unsigned long *)data, (unsigned long)address, + (unsigned long)size); +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if ((address >= CC3200_FLASH_START_ADDRESS) && address < (CC3200_FLASH_START_ADDRESS + CC3200_FLASH_SIZE)) + { + return CC3200_FLASH_SECTOR_SIZE; + } + else + { + return MBED_FLASH_INVALID_SIZE; + } +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return CC3200_FLASH_PAGE_SIZE; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return CC3200_FLASH_START_ADDRESS; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return CC3200_FLASH_SIZE; +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c new file mode 100644 index 00000000000..e90551e7609 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c @@ -0,0 +1,102 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#include +#include +#include +#include +#include + + +uint32_t gpio_set(PinName pin) +{ + pin_function(pin, 0); + return (1); +} + +// function to initialise the gpio pin +// this links the board control bits for each pin +// with the object created for the pin +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + if (pin == (PinName)NC) + return; + + unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO); + obj->baseAddr = gpio_base; + obj->pin_mask = 1<<(pinmap_find_function(pin, PinMap_GPIO)%8); + + // determine PRCM GPIO CLOCK index + unsigned short prcm_peripheral = 0; + switch (gpio_base) + { + case CC3220SF_GPIOA0_BASE: + prcm_peripheral = PRCM_GPIOA0; + break; + case CC3220SF_GPIOA1_BASE: + prcm_peripheral = PRCM_GPIOA1; + break; + case CC3220SF_GPIOA2_BASE: + prcm_peripheral = PRCM_GPIOA2; + break; + case CC3220SF_GPIOA3_BASE: + prcm_peripheral = PRCM_GPIOA3; + break; + default: + break; + } + + // initialize GPIO PORT clock + PRCMPeripheralClkEnable(prcm_peripheral, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); + + // wait for GPIO clock to settle + while(!PRCMPeripheralStatusGet(prcm_peripheral)); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + obj->mode = mode; + //set the pin mux to be GPIO which is PIN MODE 0 + pin_mode(obj->pin, mode); + PinModeSet(obj->pin, PIN_MODE_0); + +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + obj->dir = direction; + GPIODirModeSet(obj->baseAddr, obj->pin_mask, direction); +} + +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin == NC); +} + +void gpio_write(gpio_t *obj, int value) +{ + GPIOPinWrite(obj->baseAddr, obj->pin_mask, value*obj->pin_mask); +} + +int gpio_read(gpio_t *obj) +{ + return (GPIOPinRead(obj->baseAddr, obj->pin_mask) != 0); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c new file mode 100644 index 00000000000..0b43c989744 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c @@ -0,0 +1,173 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "cmsis.h" +#include "PeripheralPins.h" + +#include +#include +#include +#include +#include +#include + +#define CHANNEL_NUM 32 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +static void handle_interrupt_in(unsigned long gpio_port) { + + uint32_t chan_base = 0; + switch ((unsigned long) gpio_port) + { + case CC3220SF_GPIOA0_BASE: + chan_base = 0; + break; + case CC3220SF_GPIOA1_BASE: + chan_base = 8; + break; + case CC3220SF_GPIOA2_BASE: + chan_base = 16; + break; + case CC3220SF_GPIOA3_BASE: + chan_base = 24; + break; + default: + return; + break; + } + + uint16_t pin_mask = 0x01; + for(int i = 0; i < 8; i++){ + + //checking for interrupt on each GPIO pin + if((GPIOIntStatus((unsigned long)gpio_port, true) & pin_mask) > 0){ + gpio_irq_event event = (gpio_irq_event)GPIOIntTypeGet((unsigned long)gpio_port, pin_mask); + if(event == GPIO_RISING_EDGE){ + event = IRQ_RISE; + } + else if(event == GPIO_FALLING_EDGE){ + event = IRQ_FALL; + } + + if(channel_ids[chan_base+i] == 0) + continue; + + irq_handler(channel_ids[chan_base+i], (gpio_irq_event)event); + + } + GPIOIntClear((unsigned long)gpio_port, pin_mask); + pin_mask = pin_mask<<1; + } + +} + +void gpio_irqA0(void) { + handle_interrupt_in(CC3220SF_GPIOA0_BASE); +} + +void gpio_irqA1(void) +{ + handle_interrupt_in(CC3220SF_GPIOA1_BASE); +} + +void gpio_irqA2(void) +{ + handle_interrupt_in(CC3220SF_GPIOA2_BASE); +} + +void gpio_irqA3(void) +{ + handle_interrupt_in(CC3220SF_GPIOA3_BASE); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + if (pin == NC) return -1; + + + + unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO); + unsigned long ch_num = pinmap_find_function(pin, PinMap_GPIO); + obj->baseAddr = gpio_base; + obj->pin = pin; + obj->ch = ch_num; + obj->pin_mask = 1<<(ch_num%8); + irq_handler = handler; + uint32_t vector = (uint32_t)gpio_irqA0; + switch (gpio_base) + { + case CC3220SF_GPIOA0_BASE: + vector = (uint32_t)gpio_irqA0; + obj->irq_offset = INT_GPIOA0_IRQn; + break; + case CC3220SF_GPIOA1_BASE: + vector = (uint32_t)gpio_irqA1; + obj->irq_offset = INT_GPIOA1_IRQn; + break; + case CC3220SF_GPIOA2_BASE: + vector = (uint32_t)gpio_irqA2; + obj->irq_offset = INT_GPIOA2_IRQn; + break; + case CC3220SF_GPIOA3_BASE: + vector = (uint32_t)gpio_irqA3; + obj->irq_offset = INT_GPIOA3_IRQn; + break; + default: + break; + } + channel_ids[obj->ch] = id; + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_offset); + NVIC_DisableIRQ((IRQn_Type)obj->irq_offset); + NVIC_SetVector((IRQn_Type)obj->irq_offset, vector); + NVIC_EnableIRQ((IRQn_Type)obj->irq_offset); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_ids[obj->ch] = 0; + GPIOIntDisable(obj->baseAddr, obj->pin_mask); +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + + if(enable){ + GPIOIntEnable(obj->baseAddr, obj->pin_mask); + } + else{ + GPIOIntDisable(obj->baseAddr, obj->pin_mask); + } + + switch(event){ + case IRQ_RISE:GPIOIntTypeSet(obj->baseAddr,obj->pin_mask, GPIO_RISING_EDGE); break; + case IRQ_FALL: GPIOIntTypeSet(obj->baseAddr,obj->pin_mask, GPIO_FALLING_EDGE); break; + default: break; + } + + +} + +void gpio_irq_enable(gpio_irq_t *obj) { + GPIOIntEnable(obj->baseAddr, obj->pin_mask); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + GPIOIntDisable(obj->baseAddr, obj->pin_mask); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c new file mode 100644 index 00000000000..5b3cd6bc484 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c @@ -0,0 +1,115 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if DEVICE_LPTICKER +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/driverlib/prcm.h" + +/******************************************************************************* + * lp_ticker implementation on this target is mapped on top of the sleep clock counter + * that is running in the lowest energy modes. The sleep clock counter is 48b running + * at 32.768KHz. This gives 0.03ms resolution for the low power timer which requires + * millisecond accuracy. + * + ******************************************************************************/ + +#include "lp_ticker_api.h" +#include "mbed_critical.h" + +// There's actually 48b but Mbed OS supports 32b only. +#define RTC_BITS 32u +#define RTC_FREQ 32768u + +static bool rtc_inited = false; + +const ticker_info_t* lp_ticker_get_info() +{ + static const ticker_info_t info = { + RTC_FREQ, // 32KHz + RTC_BITS // 32 bit counter + }; + return &info; +} + +void lp_ticker_init() +{ + if (PRCMRTCInUseGet() == true) + // When RTC is in use, slow clock counter can't be accessed + { + return; + } + if (!rtc_inited) { + NVIC_SetVector(INT_PRCM_IRQn, (uint32_t)lp_ticker_irq_handler); + NVIC_ClearPendingIRQ(INT_PRCM_IRQn); + NVIC_EnableIRQ(INT_PRCM_IRQn); + PRCMIntStatus(); // Read clears pending interrupts + rtc_inited = true; + } else { + PRCMIntDisable(PRCM_INT_SLOW_CLK_CTR); + } +} + +void lp_ticker_free() +{ + /* Disable the RTC if it was inited and is no longer in use by anyone. */ + if (rtc_inited) { + NVIC_DisableIRQ(INT_PRCM_IRQn); + rtc_inited = false; + } +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + // timestamp is defined as 32b. + core_util_critical_section_enter(); + // Clear pending interrupt + PRCMIntStatus(); + PRCMSlowClkCtrMatchSet(timestamp); + PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR); + core_util_critical_section_exit(); +} + +void lp_ticker_fire_interrupt(void) +{ + core_util_critical_section_enter(); + NVIC_SetPendingIRQ(INT_PRCM_IRQn); + core_util_critical_section_exit(); +} + +void lp_ticker_disable_interrupt() +{ + PRCMIntDisable(PRCM_INT_SLOW_CLK_CTR); +} + +void lp_ticker_clear_interrupt() +{ + PRCMIntStatus(); // Read clears pending interrupts +} + +timestamp_t lp_ticker_read() +{ + // Read forever until reaching two of the same + volatile unsigned long long read_previous, read_current; + do + { + read_previous = PRCMSlowClkCtrFastGet(); + read_current = PRCMSlowClkCtrFastGet(); + } while (read_previous != read_current); + + return read_current; +} + +#endif /* DEVICE_LPTICKER */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h new file mode 100644 index 00000000000..0f219473083 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h @@ -0,0 +1,177 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "stdbool.h" +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "serial_object.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + unsigned long baseAddr; + PinName pin; + PinMode mode; + PinDirection dir; + unsigned long pin_mask; +} gpio_t; + +struct gpio_irq_s { + unsigned long baseAddr; + uint32_t port; + PinName pin; + uint32_t ch; + unsigned long pin_mask; + unsigned long irq_offset; +}; + +struct port_s { + unsigned long baseAddr; + unsigned long peripheralId; + PortName port; + uint32_t mask; +}; + +struct pwmout_s { + uint32_t pwmPin; + PWMName pwm; +}; + +struct serial_s { + CC3220SF_UART_TypeDef *uart; + int index; + uint32_t baudRate; /*!< Baud rate for UART */ + unsigned int baseAddr; /*! UART Peripheral's base address */ + unsigned int intNum; /*! UART Peripheral's interrupt vector */ + unsigned int powerMgrId; /* Determined from base address */ + unsigned long peripheralId; /* Value that can be passed to PRCM functions */ + UART_LEN dataLength; /* Data length for UART */ + UART_STOP stopBits; /* Stop bits for UART */ + UART_PAR parityType; /* Parity bit type for UART */ +}; + +struct analogin_s{ + PinName pin; + unsigned long adc_ch; +}; + +struct trng_s { + uint32_t placeholder; +}; + +struct flash_s { + uint32_t placeholder; +}; + +typedef struct spi_clock_config_s { + + //! \param ulSPIClk is the rate of clock supplied to the SPI module. + uint32_t ulSPIClk; + + //! \param ulBitRate is the desired bit rate.(master mode) + uint32_t ulBitRate; + + //! + //! The SPI module can operate in either master or slave mode. The parameter + //! \e ulMode can be one of the following + //! -\b SPI_MODE_MASTER + //! -\b SPI_MODE_SLAVE + uint32_t ulMode; + + //! + //! The SPI module supports 4 sub modes based on SPI clock polarity and phase. + //! + //! 
+    //! Polarity Phase  Sub-Mode
+    //!   0       0        0
+    //!   0       1        1
+    //!   1       0        2
+    //!   1       1        3
+    //!
+ + //! Required sub mode can be select by setting \e ulSubMode parameter to one + //! of the following + //! - \b SPI_SUB_MODE_0 + //! - \b SPI_SUB_MODE_1 + //! - \b SPI_SUB_MODE_2 + //! - \b SPI_SUB_MODE_3 + uint32_t ulSubMode; + + //! The parameter \e ulConfig is logical OR of five values: the word length, + //! active level for chip select, software or hardware controlled chip select, + //! 3 or 4 pin mode and turbo mode. + //! mode. + //! + //! SPI support 8, 16 and 32 bit word lengths defined by:- + //! - \b SPI_WL_8 + //! - \b SPI_WL_16 + //! - \b SPI_WL_32 + //! + //! Active state of Chip Select can be defined by:- + //! - \b SPI_CS_ACTIVELOW + //! - \b SPI_CS_ACTIVEHIGH + //! + //! SPI chip select can be configured to be controlled either by hardware or + //! software:- + //! - \b SPI_SW_CS + //! - \b SPI_HW_CS + //! + //! The module can work in 3 or 4 pin mode defined by:- + //! - \b SPI_3PIN_MODE + //! - \b SPI_4PIN_MODE + //! + //! Turbo mode can be set on or turned off using:- + //! - \b SPI_TURBO_MODE_ON + //! - \b SPI_TURBO_MODE_OFF + uint32_t ulConfig; +} spi_clock_config_t; + +struct spi_s { + /*! SPI module number */ + uint32_t instance; + + /*! SPICC32XXDMA Peripheral's base address */ + uint32_t baseAddr; + + /*! SPI Word lengh */ + uint32_t word_length; + + /*! SPI clock configuration */ + spi_clock_config_t clock_config; + + /*! Is clock update needed */ + bool clock_update; + + /*! Is CS controlled by GPIO */ + bool cs_control_gpio; + +#if DEVICE_SPI_ASYNCH + uint32_t handler; + uint32_t mask; + uint32_t event; +#endif +}; +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c new file mode 100644 index 00000000000..fd00109b57b --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" + +#include +#include +#include +#include + +/** + * Configure pin (mode, speed, output type and pull-up/pull-down) + */ +void pin_function(PinName pin, int function) +{ + MBED_ASSERT(pin != (PinName)NC); +} + +/** + * Configure pin pull-up/pull-down + */ +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + switch(mode) { + case PullNone: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); break; + case PullUp: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PU); break; + case PullDown: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PD); break; + case OpenDrain: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD); break; + case OpenDrainPullUp: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PU); break; + case OpenDrainPullDown: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PD); break; + case Analog: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_ANALOG); break; + default: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); break; + } +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c new file mode 100644 index 00000000000..e29f98dbe56 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "PeripheralPins.h" + +#include +#include +#include +#include +#include + +#define NUM_PORTS 4 +#define NUM_PINS_PER_PORT 8 +#define PORT_MASK 0x3 + +static const uint8_t pinTable[] = { + /* 00 01 02 03 04 05 06 07 */ + PIN_50, PIN_55, PIN_57, PIN_58, PIN_59, PIN_60, PIN_61, PIN_62, + /* 08 09 10 11 12 13 14 15 */ + PIN_63, PIN_64, PIN_01, PIN_02, PIN_03, PIN_04, PIN_05, PIN_06, + /* 16 17 18 19 20 21 22 23 */ + PIN_07, PIN_08, PIN_XX, PIN_XX, PIN_XX, PIN_XX, PIN_15, PIN_16, + /* 24 25 26 27 28 29 30 31 */ + PIN_17, PIN_21, PIN_29, PIN_30, PIN_18, PIN_20, PIN_53, PIN_45, + /* 32 */ + PIN_52 +}; + +const uint16_t PortPinTypes[] = { + PIN_TYPE_STD, /* GPIO_CFG_IN_NOPULL */ + PIN_TYPE_STD_PU, /* GPIO_CFG_IN_PU */ + PIN_TYPE_STD_PD, /* GPIO_CFG_IN_PD */ + PIN_TYPE_OD, /* GPIO_CFG_OUT_OD_NOPULL */ + PIN_TYPE_OD_PU, /* GPIO_CFG_OUT_OD_PU */ + PIN_TYPE_OD_PD, /* GPIO_CFG_OUT_OD_PD */ + (uint16_t)PIN_TYPE_ANALOG // Revisit this, PIN_TYPE_ANALOG gets truncated to 16b +}; + +PinName port_pin(PortName port, int pin_n) { + int gpio_num = (port * 8) + pin_n; + PinName pin = (PinName)pinTable[gpio_num]; + return pin; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + obj->port = port; + obj->mask = mask; + + switch(port) { + case Port0: obj->baseAddr = CC3220SF_GPIOA0_BASE; obj->peripheralId = PRCM_GPIOA0; break; + case Port1: obj->baseAddr = CC3220SF_GPIOA1_BASE; obj->peripheralId = PRCM_GPIOA1; break; + case Port2: obj->baseAddr = CC3220SF_GPIOA2_BASE; obj->peripheralId = PRCM_GPIOA2; break; + case Port3: obj->baseAddr = CC3220SF_GPIOA3_BASE; obj->peripheralId = PRCM_GPIOA3; break; + } + + // initialize GPIO PORT clock + PRCMPeripheralClkEnable(obj->peripheralId, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); + // wait for GPIO clock to settle + while(!PRCMPeripheralStatusGet(obj->peripheralId)); + + for (int i = 0; i < 8; i++) { + if (obj->mask & (1 << i)) { + PinName pin = port_pin(obj->port, i); + PinModeSet(pin, PIN_MODE_0); + pin_mode(pin, PullNone); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + for (int i = 0; i < 8; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + switch (dir) { + case PIN_INPUT: GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_IN); break; + case PIN_OUTPUT: GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_OUT); break; + } +} + +void port_write(port_t *obj, int value) { + GPIOPinWrite(obj->baseAddr, obj->mask, value); +} + +int port_read(port_t *obj) { + return (int)(GPIOPinRead(obj->baseAddr, obj->mask)); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c new file mode 100644 index 00000000000..ea87b010672 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c @@ -0,0 +1,181 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const uint32_t timerBaseAddresses[4] = { + CC3220SF_TIMERA0_BASE, + CC3220SF_TIMERA1_BASE, + CC3220SF_TIMERA2_BASE, + CC3220SF_TIMERA3_BASE, +}; + +static const uint32_t timerHalves[2] = { + TIMER_A, + TIMER_B, +}; + +/*static const uint32_t gpioBaseAddresses[4] = { + CC3220SF_GPIOA0_BASE, + CC3220SF_GPIOA1_BASE, + CC3220SF_GPIOA2_BASE, + CC3220SF_GPIOA3_BASE, +};*/ + +/*static const uint32_t gpioPinIndexes[8] = { + GPIO_PIN_0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, +};*/ + +#define PinConfigTimerPort(config) (((config) >> 28) & 0xF) +#define PinConfigTimerHalf(config) (((config) >> 24) & 0xF) +#define PinConfigGPIOPort(config) (((config) >> 20) & 0xF) +#define PinConfigGPIOPinIndex(config) (((config) >> 16) & 0xF) +#define PinConfigPinMode(config) (((config) >> 8) & 0xF) +#define PinConfigPin(config) (((config) >> 0) & 0x3F) + +#define PWMTimerCC32XX_T0A (0x00 << 24) +#define PWMTimerCC32XX_T0B (0x01 << 24) +#define PWMTimerCC32XX_T1A (0x10 << 24) +#define PWMTimerCC32XX_T1B (0x11 << 24) +#define PWMTimerCC32XX_T2A (0x20 << 24) +#define PWMTimerCC32XX_T2B (0x21 << 24) +#define PWMTimerCC32XX_T3A (0x30 << 24) +#define PWMTimerCC32XX_T3B (0x31 << 24) + +#define PWMTimerCC32XX_GPIO9 (0x11 << 16) +#define PWMTimerCC32XX_GPIO10 (0x12 << 16) +#define PWMTimerCC32XX_GPIO11 (0x13 << 16) +#define PWMTimerCC32XX_GPIO24 (0x30 << 16) +#define PWMTimerCC32XX_GPIO25 (0x31 << 16) + +#define PWMTimerCC32XX_GPIONONE (0xFF << 16) + +#define PWMTimerCC32XX_PIN_01 (PWMTimerCC32XX_T3A | PWMTimerCC32XX_GPIO10 | 0x0300) +#define PWMTimerCC32XX_PIN_02 (PWMTimerCC32XX_T3B | PWMTimerCC32XX_GPIO11 | 0x0301) +#define PWMTimerCC32XX_PIN_17 (PWMTimerCC32XX_T0A | PWMTimerCC32XX_GPIO24 | 0x0510) +#define PWMTimerCC32XX_PIN_19 (PWMTimerCC32XX_T1B | PWMTimerCC32XX_GPIONONE | 0x0812) +#define PWMTimerCC32XX_PIN_21 (PWMTimerCC32XX_T1A | PWMTimerCC32XX_GPIO25 | 0x0914) +#define PWMTimerCC32XX_PIN_64 (PWMTimerCC32XX_T2B | PWMTimerCC32XX_GPIO9 | 0x033F) + +//static unsigned int pwm_clock_mhz; + +void pwmout_init(pwmout_t* obj, PinName pin) { + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + obj->pwm = pwm; + + switch(pin) { + case PIN_01: obj->pwmPin = PWMTimerCC32XX_PIN_01; break; + case PIN_02: obj->pwmPin = PWMTimerCC32XX_PIN_02; break; + case PIN_17: obj->pwmPin = PWMTimerCC32XX_PIN_17; break; + case PIN_19: obj->pwmPin = PWMTimerCC32XX_PIN_19; break; + case PIN_21: obj->pwmPin = PWMTimerCC32XX_PIN_21; break; + case PIN_64: obj->pwmPin = PWMTimerCC32XX_PIN_64; break; + default: break; + } + + uint32_t timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(obj->pwmPin)]; + uint16_t halfTimer = timerHalves[PinConfigTimerHalf(obj->pwmPin)]; + + MAP_TimerDisable(timerBaseAddr, halfTimer); + + /* + * The CC32XX SDK TimerConfigure API halts both timers when it is + * used to configure a single half timer. The code below performs + * the register operations necessary to configure each half timer + * individually. + */ + /* Enable CCP to IO path */ + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_GPT_TRIG_SEL) = 0xFF; + + /* Split the timer and configure it as a PWM */ + uint32_t timerConfigVal = ((halfTimer & (TIMER_CFG_A_PWM | TIMER_CFG_B_PWM)) | + TIMER_CFG_SPLIT_PAIR); + HWREG(timerBaseAddr + TIMER_O_CFG) |= (timerConfigVal >> 24); + if (halfTimer & TIMER_A) { + HWREG(timerBaseAddr + TIMER_O_TAMR) = timerConfigVal & 255; + } + else { + HWREG(timerBaseAddr + TIMER_O_TBMR) = (timerConfigVal >> 8) & 255; + } + + /* Set the peripheral output to active-high */ + MAP_TimerControlLevel(timerBaseAddr, halfTimer, true); + + uint16_t mode = PinConfigPinMode(obj->pwmPin); + + /* Start the timer & set pinmux to PWM mode */ + MAP_TimerEnable(timerBaseAddr, halfTimer); + MAP_PinTypeTimer((unsigned long)pin, (unsigned long)mode); +} + +void pwmout_free(pwmout_t* obj) { + // [TODO] +} + +void pwmout_write(pwmout_t* obj, float value) { + +} + +float pwmout_read(pwmout_t* obj) { + return 0; +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c new file mode 100644 index 00000000000..ed488ae419f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c @@ -0,0 +1,52 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "rtc_api.h" + +#if DEVICE_RTC +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/driverlib/prcm.h" + +void rtc_init(void) { + static bool rtc_initialized = false; + if (!rtc_initialized) + { + if (!PRCMRTCInUseGet()) + { + PRCMRTCInUseSet(); + } + rtc_initialized = true; + } +} + +void rtc_free(void) { +} + +int rtc_isenabled(void) { + return PRCMRTCInUseGet(); +} + +time_t rtc_read(void) { + unsigned long ulSecs = 0; + unsigned short usMsec = 0; + PRCMRTCGet(&ulSecs, &usMsec); + return ulSecs; +} + +void rtc_write(time_t t) { + PRCMRTCSet(t, 0); +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c new file mode 100644 index 00000000000..de15b60cdf8 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c @@ -0,0 +1,405 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include +#include +#include +#include +#include "mbed_assert.h" + +#include "serial_api.h" +#include "serial_object.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_api.h" +#include "PeripheralPins.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ +#define UART_NUM 2 + +static const uint32_t dataLength[] = { + UART_CONFIG_WLEN_5, /* UART_LEN_5 */ + UART_CONFIG_WLEN_6, /* UART_LEN_6 */ + UART_CONFIG_WLEN_7, /* UART_LEN_7 */ + UART_CONFIG_WLEN_8 /* UART_LEN_8 */ +}; + +static const uint32_t stopBits[] = { + UART_CONFIG_STOP_ONE, /* UART_STOP_ONE */ + UART_CONFIG_STOP_TWO /* UART_STOP_TWO */ +}; + +static const uint32_t parityType[] = { + UART_CONFIG_PAR_NONE, /* UART_PAR_NONE */ + UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN */ + UART_CONFIG_PAR_ODD, /* UART_PAR_ODD */ + UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO */ + UART_CONFIG_PAR_ONE /* UART_PAR_ONE */ +}; + +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +struct serial_global_data_s { + uint32_t serial_irq_id; + gpio_t sw_rts, sw_cts; + uint8_t count, rx_irq_set_flow, rx_irq_set_api; +}; + +static struct serial_global_data_s uart_data[UART_NUM]; + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + + obj->uart = (CC3220SF_UART_TypeDef *)uart; + + // Set default values for UART + obj->dataLength = UART_LEN_8; + obj->stopBits = UART_STOP_ONE; + obj->parityType = UART_PAR_NONE; + + switch (uart) { + case UART_0: { + obj->index = 0; + obj->baseAddr = CC3220SF_UARTA0_BASE; + obj->powerMgrId = 12; /*!< Resource ID: UART 0 */ + obj->intNum = INT_UARTA0_IRQn; + obj->peripheralId = PRCM_UARTA0; + } + break; + case UART_1: { + obj->index = 1; + obj->baseAddr = CC3220SF_UARTA1_BASE; + obj->powerMgrId = 13; /*!< Resource ID: UART 1 */ + obj->intNum = INT_UARTA1_IRQn; + obj->peripheralId = PRCM_UARTA1; + } + break; + } + + PRCMPeripheralClkEnable(obj->peripheralId, PRCM_RUN_MODE_CLK); + + // Pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + MAP_PinTypeUART(tx, pinmap_function(tx, PinMap_UART_TX)); + MAP_PinTypeUART(rx, pinmap_function(rx, PinMap_UART_RX)); + + MAP_UARTEnable(obj->baseAddr); + + // Set default baud rate and format + serial_baud(obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + // set rx/tx pins in PullUp mode + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + /* Set flow control */ + uart_data[obj->index].sw_rts.pin = NC; + uart_data[obj->index].sw_cts.pin = NC; + serial_set_flow_control(obj, FlowControlNone, NC, NC); + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + uart_data[obj->index].serial_irq_id = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->baudRate = baudrate; + + MAP_UARTConfigSetExpClk(obj->baseAddr, MAP_PRCMPeripheralClockGet(obj->peripheralId), + obj->baudRate, (dataLength[obj->dataLength] | + stopBits[obj->stopBits] | parityType[obj->parityType])); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || + (parity == ParityForced1) || (parity == ParityForced0)); + + stop_bits -= 1; + data_bits -= 5; + + switch (parity) { + case ParityNone: + obj->parityType = UART_PAR_NONE; + break; + case ParityOdd : + obj->parityType = UART_PAR_ODD; + break; + case ParityEven: + obj->parityType = UART_PAR_EVEN; + break; + case ParityForced1: + obj->parityType = UART_PAR_ONE; + break; + case ParityForced0: + obj->parityType = UART_PAR_ZERO; + break; + default: + obj->parityType = UART_PAR_NONE; + break; + } + + switch (data_bits) { + case 0: + obj->dataLength = UART_LEN_5; + break; + case 1: + obj->dataLength = UART_LEN_6; + break; + case 2: + obj->dataLength = UART_LEN_7; + break; + case 3: + obj->dataLength = UART_LEN_8; + break; + default: + obj->dataLength = UART_LEN_8; + break; + } + + switch (stop_bits) { + case 0: + obj->stopBits = UART_STOP_ONE; + break; + case 1: + obj->stopBits = UART_STOP_TWO; + break; + default: + obj->stopBits = UART_STOP_ONE; + break; + } + + MAP_UARTConfigSetExpClk(obj->baseAddr, MAP_PRCMPeripheralClockGet(obj->peripheralId), + obj->baudRate, (dataLength[obj->dataLength] | + stopBits[obj->stopBits] | parityType[obj->parityType])); +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t intstatus, uint32_t index, CC3220SF_UART_TypeDef *puart) +{ + SerialIrq irq_type; + if (intstatus & UART_INT_TX) { + irq_type = TxIrq; + } else { + irq_type = RxIrq; + } + uint32_t rxErrors = puart->RSR & 0x0000000F; + if (rxErrors) { + puart->ECR = 0; + } + if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) { + gpio_write(&uart_data[index].sw_rts, 1); + // Disable interrupt if it wasn't enabled by other part of the application + if (!uart_data[index].rx_irq_set_api) { + puart->IM &= ~(UART_INT_RX | UART_INT_RT); + } + } + if (uart_data[index].serial_irq_id != 0) { + if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) { + irq_handler(uart_data[index].serial_irq_id, irq_type); + } + } + if (irq_type == TxIrq) { + puart->ICR = UART_INT_TX; // clear TX interrupt + } else { + puart->ICR = UART_INT_RX; // clear RX interrupt + } +} + +void uart0_irq() +{ + uart_irq(CC3220SF_UART0->MIS, 0, (CC3220SF_UART_TypeDef *)CC3220SF_UART0); +} +void uart1_irq() +{ + uart_irq(CC3220SF_UART1->MIS, 1, (CC3220SF_UART_TypeDef *)CC3220SF_UART1); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + uart_data[obj->index].serial_irq_id = id; +} + +void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + + /* Clear interrupts */ + uint32_t status = MAP_UARTIntStatus(obj->baseAddr, true); + MAP_UARTIntClear(obj->baseAddr, status); + + switch ((int)obj->uart) { + case UART_0: + irq_n = INT_UARTA0_IRQn; + vector = (uint32_t)&uart0_irq; + break; + case UART_1: + irq_n = INT_UARTA1_IRQn; + vector = (uint32_t)&uart1_irq; + break; + } + + if (enable) { + if (irq == TxIrq) { + MAP_UARTIntEnable(obj->baseAddr, UART_INT_TX); + } else { + MAP_UARTIntEnable(obj->baseAddr, UART_INT_RX); + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + } else { + /* Disable IRQ */ + MAP_UARTIntDisable(obj->baseAddr, UART_INT_TX | UART_INT_RX); + NVIC_DisableIRQ(irq_n); + } +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if (RxIrq == irq) { + uart_data[obj->index].rx_irq_set_api = enable; + } + serial_irq_set_internal(obj, irq, enable); +} + +/*static void serial_flow_irq_set(serial_t *obj, uint32_t enable) +{ + uart_data[obj->index].rx_irq_set_flow = enable; + serial_irq_set_internal(obj, RxIrq, enable); +}*/ + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) +{ + while (!serial_readable(obj)); + return obj->uart->DR; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)); + obj->uart->DR = c; +} + +int serial_readable(serial_t *obj) +{ + return ((obj->uart->FR & UART_FR_RXFE) ? 0 : 1); +} + +int serial_writable(serial_t *obj) +{ + return ((obj->uart->FR & UART_FR_TXFF) ? 0 : 1); +} + +void serial_clear(serial_t *obj) +{ + obj->uart->DR = 0x00; +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + MAP_UARTBreakCtl(obj->baseAddr, true); +} + +void serial_break_clear(serial_t *obj) +{ + MAP_UARTBreakCtl(obj->baseAddr, false); +} + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + switch (type) { + case FlowControlRTS: + pinmap_pinout(rxflow, PinMap_UART_RTS); + MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_RX); + MAP_UARTModemControlSet(obj->baseAddr, UART_OUTPUT_RTS); + break; + + case FlowControlCTS: + pinmap_pinout(txflow, PinMap_UART_CTS); + MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_TX); + MAP_UARTModemControlClear(obj->baseAddr, UART_OUTPUT_RTS); + break; + + case FlowControlRTSCTS: + pinmap_pinout(rxflow, PinMap_UART_RTS); + pinmap_pinout(txflow, PinMap_UART_CTS); + MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); + MAP_UARTModemControlSet(obj->baseAddr, UART_OUTPUT_RTS); + break; + + case FlowControlNone: + MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_NONE); + MAP_UARTModemControlClear(obj->baseAddr, UART_OUTPUT_RTS); + break; + } +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_object.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_object.h new file mode 100644 index 00000000000..a3402ab7576 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_object.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SERIAL_OBJECT_H +#define MBED_SERIAL_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum UART_LEN_ { + UART_LEN_5 = 0, /*!< Data length is 5 bits */ + UART_LEN_6 = 1, /*!< Data length is 6 bits */ + UART_LEN_7 = 2, /*!< Data length is 7 bits */ + UART_LEN_8 = 3 /*!< Data length is 8 bits */ +} UART_LEN; + +typedef enum UART_STOP_ { + UART_STOP_ONE = 0, /*!< One stop bit */ + UART_STOP_TWO = 1 /*!< Two stop bits */ +} UART_STOP; + +typedef enum UART_PAR_ { + UART_PAR_NONE = 0, /*!< No parity */ + UART_PAR_EVEN = 1, /*!< Parity bit is even */ + UART_PAR_ODD = 2, /*!< Parity bit is odd */ + UART_PAR_ZERO = 3, /*!< Parity bit is always zero */ + UART_PAR_ONE = 4 /*!< Parity bit is always one */ +} UART_PAR; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c new file mode 100644 index 00000000000..2f8d8e19f7b --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c @@ -0,0 +1,470 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if DEVICE_SPI + +#include +#include "hal/spi_api.h" +#include "objects.h" +#include "ti/devices/cc32xx/inc/hw_ints.h" +#include "ti/devices/cc32xx/inc/hw_memmap.h" +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/driverlib/pin.h" +#include "ti/devices/cc32xx/driverlib/rom_map.h" +#include "ti/devices/cc32xx/driverlib/ti_spi_driverlib.h" +#include "ti/devices/cc32xx/driverlib/prcm.h" + +#define PIN_MODE_SPI 7 +#define SPI_WL_MASK 0xF80 + +/** + * Brief Reconfigure peripheral. + * + * If the peripheral has changed ownership clear old configuration and + * re-initialize the peripheral with the new settings. + * + * Parameter obj The object + */ +static void spi_configure_driver_instance(spi_t *obj) +{ +#if DEVICE_SPI_ASYNCH + struct spi_s *spi_inst = &obj->spi; +#else + struct spi_s *spi_inst = obj; +#endif + + if (spi_inst->clock_update) + { + SPIReset(spi_inst->baseAddr); + SPIConfigSetExpClk(spi_inst->baseAddr, spi_inst->clock_config.ulSPIClk, + spi_inst->clock_config.ulBitRate, spi_inst->clock_config.ulMode, + spi_inst->clock_config.ulSubMode, spi_inst->clock_config.ulConfig); + spi_inst->clock_update = false; + SPIEnable(spi_inst->baseAddr); + } +} + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * Parameter obj The SPI object to initialize + * Parameter mosi The pin to use for MOSI + * Parameter miso The pin to use for MISO + * Parameter sclk The pin to use for SCLK + * Parameter ssel The pin to use for SSEL + */ +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ +#if DEVICE_SPI_ASYNCH + struct spi_s *spi_inst = &obj->spi; +#else + struct spi_s *spi_inst = obj; +#endif + + /* Get instance based on requested pins. */ + spi_inst->instance = 1; + spi_inst->baseAddr = GSPI_BASE; + spi_inst->clock_config.ulConfig = SPI_4PIN_MODE; + spi_inst->clock_config.ulConfig |= SPI_HW_CTRL_CS; + spi_inst->clock_config.ulConfig |= SPI_CS_ACTIVELOW; + if (ssel == NC) + { + spi_inst->cs_control_gpio = true; + } + else + { + spi_inst->cs_control_gpio = false; + } + spi_inst->clock_config.ulConfig |= SPI_TURBO_OFF; +#if DEVICE_SPI_ASYNCH + /* Set default values for asynchronous variables. */ + spi_inst->handler = 0; + spi_inst->mask = 0; + spi_inst->event = 0; +#endif + + /* Configure GPIO pin if chip select has been set. */ + MAP_PinTypeSPI((unsigned long) mosi & 0xff, (unsigned long) PIN_MODE_SPI); + MAP_PinTypeSPI((unsigned long) miso & 0xff, (unsigned long) PIN_MODE_SPI); + MAP_PinTypeSPI((unsigned long) sclk & 0xff, (unsigned long) PIN_MODE_SPI); + if (ssel != NC) + { + MAP_PinTypeSPI((unsigned long) ssel & 0xff, (unsigned long) PIN_MODE_SPI); + } + spi_inst->clock_update = true; +} + +/** Release a SPI object + * + * TODO: spi_free is currently unimplemented + * This will require reference counting at the C++ level to be safe + * + * Return the pins owned by the SPI object to their reset state + * Disable the SPI peripheral + * Disable the SPI clock + * Parameter obj The SPI object to deinitialize + */ +void spi_free(spi_t *obj) +{ + +} + +/** Configure the SPI format + * + * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. + * The default bit order is MSB. + * Parameter obj The SPI object to configure + * Parameter bits The number of bits per frame + * Parameter mode The SPI mode (clock polarity, phase, and shift direction) + * Parameter slave Zero for master mode or non-zero for slave mode + */ +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + /* SPI module supports 8/16/32 bit transfers. */ + MBED_ASSERT(bits == 8 || bits == 16 || bits == 32); + /* SPI module doesn't support Mbed HAL Slave API. */ + MBED_ASSERT(slave == 0); + +#if DEVICE_SPI_ASYNCH + struct spi_s *spi_inst = &obj->spi; +#else + struct spi_s *spi_inst = obj; +#endif + if ((uint32_t)bits != spi_inst->word_length) + { + spi_inst->word_length = bits; + spi_inst->clock_update = true; + } + spi_inst->clock_config.ulConfig &= ~SPI_WL_MASK; + spi_inst->clock_config.ulConfig |= (bits - 1) << 7; + spi_inst->clock_config.ulMode = SPI_MODE_MASTER; + + // TI calls it submode + // SPI_SUB_MODE_0 - clk active high, sampling on the rising edge + // SPI_SUB_MODE_1 - clk active high, sampling on the falling edge + // SPI_SUB_MODE_2 - clk active low, sampling on the falling edge + // SPI_SUB_MODE_3 - clk active low, sampling on the rising edge + + /* Convert Mbed HAL mode to TI mode. */ + + if(mode == 0) { + if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_0) + { + spi_inst->clock_update = true; + } + spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_0; + } else if(mode == 1) { + if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_1) + { + spi_inst->clock_update = true; + } + spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_1; + } else if(mode == 2) { + if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_2) + { + spi_inst->clock_update = true; + } + spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_2; + } else if(mode == 3) { + if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_3) + { + spi_inst->clock_update = true; + } + spi_inst->clock_config.ulSubMode= SPI_SUB_MODE_3; + } + spi_configure_driver_instance(spi_inst); +} + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * Parameter obj The SPI object to configure + * Parameter hz The baud rate in Hz + */ +void spi_frequency(spi_t *obj, int hz) +{ +#if DEVICE_SPI_ASYNCH + struct spi_s *spi_inst = &obj->spi; +#else + struct spi_s *spi_inst = obj; +#endif + + spi_inst->clock_config.ulSPIClk = PRCMPeripheralClockGet(PRCM_GSPI); + if (spi_inst->clock_config.ulBitRate != (uint32_t)hz) + { + spi_inst->clock_update = true; + spi_inst->clock_config.ulBitRate = hz; + } + spi_configure_driver_instance(spi_inst); +} + +/** Write a byte out in master mode and receive a value + * + * Parameter obj The SPI peripheral to use for sending + * Parameter value The value to send + * Return Returns the value received during send + */ +int spi_master_write(spi_t *obj, int value) +{ +#if DEVICE_SPI_ASYNCH + struct spi_s *spi_inst = &obj->spi; +#else + struct spi_s *spi_inst = obj; +#endif + + uint32_t data_read = 0; + + /* Configure peripheral if necessary. */ + spi_configure_driver_instance(obj); + + if (!spi_inst->cs_control_gpio) + { + SPICSEnable(spi_inst->baseAddr); + } + /* Transfer a data word. */ + SPIDataPut(spi_inst->baseAddr, value); + SPIDataGet(spi_inst->baseAddr, (unsigned long *)&data_read); + if (!spi_inst->cs_control_gpio) + { + SPICSDisable(spi_inst->baseAddr); + } + return data_read & ((1 << spi_inst->word_length) - 1); +} + +/** Write a block out in master mode and receive a value + * + * The total number of bytes sent and received will be the maximum of + * tx_length and rx_length. The bytes written will be padded with the + * value 0xff. + * + * Parameter obj The SPI peripheral to use for sending + * Parameter tx_buffer Pointer to the byte-array of data to write to the device + * Parameter tx_length Number of bytes to write, may be zero + * Parameter rx_buffer Pointer to the byte-array of data to read from the device + * Parameter rx_length Number of bytes to read, may be zero + * Parameter write_fill Default data transmitted while performing a read + * @returns + * The number of bytes written and read from the device. This is + * maximum of tx_length and rx_length. + */ +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ +#if DEVICE_SPI_ASYNCH + struct spi_s *spi_inst = &obj->spi; +#else + struct spi_s *spi_inst = obj; +#endif + + int i, spi_words = 0, cs_flags = 0;; + + /* Configure peripheral if necessary. */ + spi_configure_driver_instance(obj); + + if (tx_length >= rx_length) + { + if (spi_inst->word_length == 16) + { + spi_words = (tx_length >> 1); + } + else if (spi_inst->word_length == 32) + { + spi_words = (tx_length >> 2); + } + else if (spi_inst->word_length == 8) + { + spi_words = tx_length; + } + + unsigned char *rx_temp = malloc(tx_length); + SPITransfer(spi_inst->baseAddr, (unsigned char *)tx_buffer, + (unsigned char *)rx_temp, (unsigned long) spi_words, + SPI_CS_ENABLE | SPI_CS_DISABLE); + // Copy the desired data from temp_rx + for (i = 0; i < rx_length; i ++) + { + rx_buffer[i] = rx_temp[i]; + } + free(rx_temp); + return (tx_length); + } + else // tx_length < rx_length + // Copy the data from tx_buffer to a temp buffer and fill the the rest of the tx_buffer with write_fill) + { + if (spi_inst->word_length == 16) + { + spi_words = (rx_length >> 1); + } + else if (spi_inst->word_length == 32) + { + spi_words = (rx_length >> 2); + } + else if (spi_inst->word_length == 8) + { + spi_words = rx_length; + } + + unsigned char *tx_temp = malloc(rx_length); + for (i = 0; i < tx_length; i ++) + { + tx_temp[i] = tx_buffer[i]; + } + for (i = tx_length; i < rx_length; i ++) + { + tx_temp[i] = write_fill; + } + if (!spi_inst->cs_control_gpio) + { + cs_flags = SPI_CS_ENABLE | SPI_CS_DISABLE; + } + SPITransfer(spi_inst->baseAddr, (unsigned char *)tx_temp, + (unsigned char *)rx_buffer, (unsigned long) spi_words, + cs_flags); + free(tx_temp); + return rx_length; + } + +} + +/** Checks if the specified SPI peripheral is in use + * + * Parameter obj The SPI peripheral to check + * Return non-zero if the peripheral is currently transmitting + */ +int spi_busy(spi_t *obj) +{ + /* Legacy API call. Always return zero. */ + return 0; +} + +/** Get the module number + * + * Parameter obj The SPI peripheral to check + * Return The module number + */ +uint8_t spi_get_module(spi_t *obj) +{ +#if DEVICE_SPI_ASYNCH + struct spi_s *spi_inst = &obj->spi; +#else + struct spi_s *spi_inst = obj; +#endif + + return spi_inst->instance; +} + +#if DEVICE_SPISLAVE + +/** Check if a value is available to read + * + * Parameter obj The SPI peripheral to check + * Return non-zero if a value is available + */ +int spi_slave_receive(spi_t *obj) +{ + return 0; +} + +/** Get a received value out of the SPI receive buffer in slave mode + * + * Blocks until a value is available + * Parameter obj The SPI peripheral to read + * Return The value received + */ +int spi_slave_read(spi_t *obj) +{ + return 0; +} + +/** Write a value to the SPI peripheral in slave mode + * + * Blocks until the SPI peripheral can be written to + * Parameter obj The SPI peripheral to write + * Parameter value The value to write + */ +void spi_slave_write(spi_t *obj, int value) +{ + return; +} + +#endif + +#if DEVICE_SPI_ASYNCH + +/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff + * + * Parameter obj The SPI object that holds the transfer information + * Parameter tx The transmit buffer + * Parameter tx_length The number of bytes to transmit + * Parameter rx The receive buffer + * Parameter rx_length The number of bytes to receive + * Parameter bit_width The bit width of buffer words + * Parameter event The logical OR of events to be registered + * Parameter handler SPI interrupt handler + * Parameter hint A suggestion for how to use DMA with this transfer + */ +void spi_master_transfer(spi_t *obj, + const void *tx, + size_t tx_length, + void *rx, + size_t rx_length, + uint8_t bit_width, + uint32_t handler, + uint32_t mask, + DMAUsage hint) +{ +} + +/** The asynchronous IRQ handler + * + * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination + * conditions, such as buffer overflows or transfer complete. + * Parameter obj The SPI object that holds the transfer information + * Return Event flags if a transfer termination condition was met; otherwise 0. + */ +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + /* Return latest event. */ + return obj->spi.event; +} + +/** Attempts to determine if the SPI peripheral is already in use + * + * If a temporary DMA channel has been allocated, peripheral is in use. + * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA + * channel were allocated. + * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check + * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if + * there are any bytes in the FIFOs. + * Parameter obj The SPI object to check for activity + * Return Non-zero if the SPI port is active or zero if it is not. + */ +uint8_t spi_active(spi_t *obj) +{ + /* Callback handler is non-zero when a transfer is in progress. */ + return (obj->spi.handler != 0); +} + +/** Abort an SPI transfer + * + * Parameter obj The SPI peripheral to stop + */ +void spi_abort_asynch(spi_t *obj) +{ +} + +#endif // DEVICE_SPI_ASYNCH + +#endif // DEVICE_SPI diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/DeviceFamily.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/DeviceFamily.h new file mode 100755 index 00000000000..8566650a7cf --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/DeviceFamily.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DeviceFamily.h + * + * @brief Infrastructure to select correct driverlib path and identify devices + * + * This module enables the selection of the correct driverlib path for the current + * device. It also facilitates the use of per-device conditional compilation + * to enable minor variations in drivers between devices. + * + * In order to use this functionality, DeviceFamily_XYZ must be defined as one of + * the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines + * are set based on DeviceFamily_XYZ. + */ + +#ifndef ti_devices_DeviceFamily__include +#define ti_devices_DeviceFamily__include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * DeviceFamily_ID_XYZ values. + * + * DeviceFamily_ID may be used in the preprocessor for conditional compilation. + * DeviceFamily_ID is set to one of these values based on the top level + * DeviceFamily_XYZ define. + */ +#define DeviceFamily_ID_CC13X0 1 +#define DeviceFamily_ID_CC26X0 2 +#define DeviceFamily_ID_CC26X0R2 3 +#define DeviceFamily_ID_CC13X2_V1 4 +#define DeviceFamily_ID_CC13X2_V2 5 +#define DeviceFamily_ID_CC13X2 DeviceFamily_ID_CC13X2_V1 +#define DeviceFamily_ID_CC26X2_V1 6 +#define DeviceFamily_ID_CC26X2_V2 7 +#define DeviceFamily_ID_CC26X2 DeviceFamily_ID_CC26X2_V1 +#define DeviceFamily_ID_CC3200 8 +#define DeviceFamily_ID_CC3220 9 +#define DeviceFamily_ID_MSP432P401x 10 +#define DeviceFamily_ID_MSP432P4x1xI 11 +#define DeviceFamily_ID_MSP432P4x1xT 12 +#define DeviceFamily_ID_MSP432E401Y 13 +#define DeviceFamily_ID_MSP432E411Y 14 + +/* + * DeviceFamily_PARENT_XYZ values. + * + * DeviceFamily_PARENT may be used in the preprocessor for conditional + * compilation. DeviceFamily_PARENT is set to one of these values based + * on the top-level DeviceFamily_XYZ define. + */ +#define DeviceFamily_PARENT_CC13X0_CC26X0 1 +#define DeviceFamily_PARENT_CC13X2_CC26X2 2 +#define DeviceFamily_PARENT_MSP432P401R 3 +#define DeviceFamily_PARENT_MSP432P4111 4 + +/* + * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and + * DeviceFamily_PARENT based on the DeviceFamily_XYZ define. + * If DeviceFamily_XYZ is undefined, a compiler error is thrown. If + * multiple DeviceFamily_XYZ are defined, the first one encountered is used. + */ +#if defined(DeviceFamily_CC13X0) + #define DeviceFamily_ID DeviceFamily_ID_CC13X0 + #define DeviceFamily_DIRECTORY cc13x0 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC13X2) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X2_V1) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2_V1 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X2_V2) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2_V2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC26X0) + #define DeviceFamily_ID DeviceFamily_ID_CC26X0 + #define DeviceFamily_DIRECTORY cc26x0 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC26X0R2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 + #define DeviceFamily_DIRECTORY cc26x0r2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC26X2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC26X2_V1) + #define DeviceFamily_ID DeviceFamily_ID_CC26X2_V1 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC26X2_V2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X2_V2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC3200) + #define DeviceFamily_ID DeviceFamily_ID_CC3200 + #define DeviceFamily_DIRECTORY cc32xx + +#elif defined(DeviceFamily_CC3220) + #define DeviceFamily_ID DeviceFamily_ID_CC3220 + #define DeviceFamily_DIRECTORY cc32xx + +#elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__) + #define DeviceFamily_ID DeviceFamily_ID_MSP432P401x + #define DeviceFamily_DIRECTORY msp432p4xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R + #if !defined(__MSP432P401R__) + #define __MSP432P401R__ + #endif + +#elif defined(DeviceFamily_MSP432P4x1xI) + #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI + #define DeviceFamily_DIRECTORY msp432p4xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 + #if !defined(__MSP432P4111__) + #define __MSP432P4111__ + #endif + +#elif defined(DeviceFamily_MSP432P4x1xT) + #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT + #define DeviceFamily_DIRECTORY msp432p4xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 + #if !defined(__MSP432P4111__) + #define __MSP432P4111__ + #endif + +#elif defined(DeviceFamily_MSP432E401Y) + #define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y + #define DeviceFamily_DIRECTORY msp432e4 + #if !defined(__MSP432E401Y__) + #define __MSP432E401Y__ + #endif + +#elif defined(DeviceFamily_MSP432E411Y) + #define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y + #define DeviceFamily_DIRECTORY msp432e4 + #if !defined(__MSP432E411Y__) + #define __MSP432E411Y__ + #endif +#else + #error "DeviceFamily_XYZ undefined. You must defined DeviceFamily_XYZ!" +#endif + +/*! + * @brief Macro to include correct driverlib path. + * + * @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined + * first. + * + * @param x A token containing the path of the file to include based on + * the root device folder. The preceding forward slash must be + * omitted. For example: + * - #include DeviceFamily_constructPath(inc/hw_memmap.h) + * - #include DeviceFamily_constructPath(driverlib/ssi.h) + * + * @return Returns an include path. + * + */ +#define DeviceFamily_constructPath(x) + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_DeviceFamily__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.c new file mode 100755 index 00000000000..c36561c9553 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.c @@ -0,0 +1,693 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// adc.c +// +// Driver for the ADC module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ADC_Analog_to_Digital_Converter_api +//! @{ +// +//***************************************************************************** +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ints.h" +#include "inc/hw_adc.h" +#include "inc/hw_apps_config.h" +#include "interrupt.h" +#include "adc.h" + + +//***************************************************************************** +// +//! Enables the ADC +//! +//! \param ulBase is the base address of the ADC +//! +//! This function sets the ADC global enable +//! +//! \return None. +// +//***************************************************************************** +void ADCEnable(unsigned long ulBase) +{ + // + // Set the global enable bit in the control register. + // + HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1; +} + +//***************************************************************************** +// +//! Disable the ADC +//! +//! \param ulBase is the base address of the ADC +//! +//! This function clears the ADC global enable +//! +//! \return None. +// +//***************************************************************************** +void ADCDisable(unsigned long ulBase) +{ + // + // Clear the global enable bit in the control register. + // + HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ; +} + +//***************************************************************************** +// +//! Enables specified ADC channel +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels +//! +//! This function enables specified ADC channel and configures the +//! pin as analog pin. +//! +//! \return None. +// +//***************************************************************************** +void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulCh; + + ulCh = (ulChannel == ADC_CH_0)? 0x02 : + (ulChannel == ADC_CH_1)? 0x04 : + (ulChannel == ADC_CH_2)? 0x08 : 0x10; + + HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh; +} + +//***************************************************************************** +// +//! Disables specified ADC channel +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channelsber +//! +//! This function disables specified ADC channel. +//! +//! \return None. +// +//***************************************************************************** +void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulCh; + + ulCh = (ulChannel == ADC_CH_0)? 0x02 : + (ulChannel == ADC_CH_1)? 0x04 : + (ulChannel == ADC_CH_2)? 0x08 : 0x10; + + HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh; +} + +//***************************************************************************** +// +//! Enables and registers ADC interrupt handler for specified channel +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels +//! \param pfnHandler is a pointer to the function to be called when the +//! ADC channel interrupt occurs. +//! +//! This function enables and registers ADC interrupt handler for specified +//! channel. Individual interrupt for each channel should be enabled using +//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear +//! the interrupt source. +//! +//! The parameter \e ulChannel should be one of the following +//! +//! - \b ADC_CH_0 for channel 0 +//! - \b ADC_CH_1 for channel 1 +//! - \b ADC_CH_2 for channel 2 +//! - \b ADC_CH_3 for channel 3 +//! +//! \return None. +// +//***************************************************************************** +void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel, + void (*pfnHandler)(void)) +{ + unsigned long ulIntNo; + + // + // Get the interrupt number associted with the specified channel + // + ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 : + (ulChannel == ADC_CH_1)? INT_ADCCH1 : + (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3; + + // + // Register the interrupt handler + // + IntRegister(ulIntNo,pfnHandler); + + // + // Enable ADC interrupt + // + IntEnable(ulIntNo); +} + + +//***************************************************************************** +// +//! Disables and unregisters ADC interrupt handler for specified channel +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels +//! +//! This function disables and unregisters ADC interrupt handler for specified +//! channel. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! The parameter \e ulChannel should be one of the following +//! +//! - \b ADC_CH_0 for channel 0 +//! - \b ADC_CH_1 for channel 1 +//! - \b ADC_CH_2 for channel 2 +//! - \b ADC_CH_3 for channel 3 +//! +//! \return None. +// +//***************************************************************************** +void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulIntNo; + + // + // Get the interrupt number associted with the specified channel + // + ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 : + (ulChannel == ADC_CH_1)? INT_ADCCH1 : + (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3; + + // + // Disable ADC interrupt + // + IntDisable(ulIntNo); + + // + // Unregister the interrupt handler + // + IntUnregister(ulIntNo); +} + +//***************************************************************************** +// +//! Enables individual interrupt sources for specified channel +//! +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated ADC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The parameter \e ulChannel should be one of the following +//! +//! - \b ADC_CH_0 for channel 0 +//! - \b ADC_CH_1 for channel 1 +//! - \b ADC_CH_2 for channel 2 +//! - \b ADC_CH_3 for channel 3 +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! - \b ADC_DMA_DONE for DMA done +//! - \b ADC_FIFO_OVERFLOW for FIFO over flow +//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow +//! - \b ADC_FIFO_EMPTY for FIFO empty +//! - \b ADC_FIFO_FULL for FIFO full +//! +//! \return None. +// +//***************************************************************************** +void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags) +{ + unsigned long ulOffset; + unsigned long ulDmaMsk; + + // + // Enable DMA Done interrupt + // + if(ulIntFlags & ADC_DMA_DONE) + { + ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: + (ulChannel == ADC_CH_1)?0x00002000: + (ulChannel == ADC_CH_2)?0x00004000:0x00008000; + + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; + } + + ulIntFlags = ulIntFlags & 0x0F; + // + // Get the interrupt enable register offset for specified channel + // + ulOffset = ADC_O_adc_ch0_irq_en + ulChannel; + + // + // Unmask the specified interrupts + // + HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf); +} + + +//***************************************************************************** +// +//! Disables individual interrupt sources for specified channel +//! +//! +//! \param ulBase is the base address of the ADC. +//! \param ulChannel is one of the valid ADC channels +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function disables the indicated ADC interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The parameters\e ulIntFlags and \e ulChannel should be as explained in +//! ADCIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags) +{ + unsigned long ulOffset; + unsigned long ulDmaMsk; + + // + // Disable DMA Done interrupt + // + if(ulIntFlags & ADC_DMA_DONE) + { + ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: + (ulChannel == ADC_CH_1)?0x00002000: + (ulChannel == ADC_CH_2)?0x00004000:0x00008000; + + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; + } + + // + // Get the interrupt enable register offset for specified channel + // + ulOffset = ADC_O_adc_ch0_irq_en + ulChannel; + + // + // Unmask the specified interrupts + // + HWREG(ulBase + ulOffset) &= ~ulIntFlags; +} + + +//***************************************************************************** +// +//! Gets the current channel interrupt status +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels +//! +//! This function returns the interrupt status of the specified ADC channel. +//! +//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable(). +//! +//! \return Return the ADC channel interrupt status, enumerated as a bit +//! field of values described in ADCIntEnable() +// +//***************************************************************************** +unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulOffset; + unsigned long ulDmaMsk; + unsigned long ulIntStatus; + + // + // Get DMA Done interrupt status + // + ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: + (ulChannel == ADC_CH_1)?0x00002000: + (ulChannel == ADC_CH_2)?0x00004000:0x00008000; + + ulIntStatus = HWREG(APPS_CONFIG_BASE + + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk; + + + // + // Get the interrupt enable register offset for specified channel + // + ulOffset = ADC_O_adc_ch0_irq_status + ulChannel; + + // + // Read ADC interrupt status + // + ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf; + + // + // Return the current interrupt status + // + return(ulIntStatus); +} + + +//***************************************************************************** +// +//! Clears the current channel interrupt sources +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! +//! This function clears individual interrupt source for the specified +//! ADC channel. +//! +//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void ADCIntClear(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags) +{ + unsigned long ulOffset; + unsigned long ulDmaMsk; + + // + // Clear DMA Done interrupt + // + if(ulIntFlags & ADC_DMA_DONE) + { + ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: + (ulChannel == ADC_CH_1)?0x00002000: + (ulChannel == ADC_CH_2)?0x00004000:0x00008000; + + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; + } + + // + // Get the interrupt enable register offset for specified channel + // + ulOffset = ADC_O_adc_ch0_irq_status + ulChannel; + + // + // Clear the specified interrupts + // + HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE)); +} + +//***************************************************************************** +// +//! Enables the ADC DMA operation for specified channel +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels +//! +//! This function enables the DMA operation for specified ADC channel +//! +//! The parameter \e ulChannel should be one of the following +//! +//! - \b ADC_CH_0 for channel 0 +//! - \b ADC_CH_1 for channel 1 +//! - \b ADC_CH_2 for channel 2 +//! - \b ADC_CH_3 for channel 3 +//! +//! \return None. +// +//***************************************************************************** +void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulBitMask; + + // + // Get the bit mask for enabling DMA for specified channel + // + ulBitMask = (ulChannel == ADC_CH_0)?0x01: + (ulChannel == ADC_CH_1)?0x04: + (ulChannel == ADC_CH_2)?0x10:0x40; + + // + // Enable DMA request for the specified channel + // + HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask; +} + +//***************************************************************************** +// +//! Disables the ADC DMA operation for specified channel +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels +//! +//! This function disables the DMA operation for specified ADC channel +//! +//! The parameter \e ulChannel should be one of the following +//! +//! - \b ADC_CH_0 for channel 0 +//! - \b ADC_CH_1 for channel 1 +//! - \b ADC_CH_2 for channel 2 +//! - \b ADC_CH_3 for channel 3 +//! +//! \return None. +// +//***************************************************************************** +void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulBitMask; + + // + // Get the bit mask for disabling DMA for specified channel + // + ulBitMask = (ulChannel == ADC_CH_0)?0x01: + (ulChannel == ADC_CH_1)?0x04: + (ulChannel == ADC_CH_2)?0x10:0x40; + + // + // Disable DMA request for the specified channel + // + HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask; +} + +//***************************************************************************** +// +//! Configures the ADC internal timer +//! +//! \param ulBase is the base address of the ADC +//! \param ulValue is wrap arround value of the timer +//! +//! This function Configures the ADC internal timer. The ADC timer is a 17 bit +//! used to timestamp the ADC data samples internally. +//! User can read the timestamp along with the sample from the FIFO register(s). +//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp +//! +//! The parameter \e ulValue can take any value between 0 - 2^17 +//! +//! \returns None. +// +//***************************************************************************** +void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue) +{ + unsigned long ulReg; + + // + // Read the currrent config + // + ulReg = HWREG(ulBase + ADC_O_adc_timer_configuration); + + // + // Mask and set timer count field + // + ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF)); + + // + // Set the timer count value + // + HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg; +} + +//***************************************************************************** +// +//! Resets ADC internal timer +//! +//! \param ulBase is the base address of the ADC +//! +//! This function resets 17-bit ADC internal timer +//! +//! \returns None. +// +//***************************************************************************** +void ADCTimerReset(unsigned long ulBase) +{ + // + // Reset the timer + // + HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24); +} + +//***************************************************************************** +// +//! Enables ADC internal timer +//! +//! \param ulBase is the base address of the ADC +//! +//! This function enables 17-bit ADC internal timer +//! +//! \returns None. +// +//***************************************************************************** +void ADCTimerEnable(unsigned long ulBase) +{ + // + // Enable the timer + // + HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25); +} + +//***************************************************************************** +// +//! Disables ADC internal timer +//! +//! \param ulBase is the base address of the ADC +//! +//! This function disables 17-bit ADC internal timer +//! +//! \returns None. +// +//***************************************************************************** +void ADCTimerDisable(unsigned long ulBase) +{ + // + // Disable the timer + // + HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25); +} + +//***************************************************************************** +// +//! Gets the current value of ADC internal timer +//! +//! \param ulBase is the base address of the ADC +//! +//! This function the current value of 17-bit ADC internal timer +//! +//! \returns Return the current value of ADC internal timer. +// +//***************************************************************************** +unsigned long ADCTimerValueGet(unsigned long ulBase) +{ + return(HWREG(ulBase + ADC_O_adc_timer_current_count)); +} + +//***************************************************************************** +// +//! Gets the current FIFO level for specified ADC channel +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels. +//! +//! This function returns the current FIFO level for specified ADC channel. +//! +//! The parameter \e ulChannel should be one of the following +//! +//! - \b ADC_CH_0 for channel 0 +//! - \b ADC_CH_1 for channel 1 +//! - \b ADC_CH_2 for channel 2 +//! - \b ADC_CH_3 for channel 3 +//! +//! \returns Return the current FIFO level for specified channel +// +//***************************************************************************** +unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulOffset; + + // + // Get the fifo level register offset for specified channel + // + ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel; + + // + // Return FIFO level + // + return(HWREG(ulBase + ulOffset) & 0x7); +} + +//***************************************************************************** +// +//! Reads FIFO for specified ADC channel +//! +//! \param ulBase is the base address of the ADC +//! \param ulChannel is one of the valid ADC channels. +//! +//! This function returns one data sample from the channel fifo as specified by +//! \e ulChannel parameter. +//! +//! The parameter \e ulChannel should be one of the following +//! +//! - \b ADC_CH_0 for channel 0 +//! - \b ADC_CH_1 for channel 1 +//! - \b ADC_CH_2 for channel 2 +//! - \b ADC_CH_3 for channel 3 +//! +//! \returns Return one data sample from the channel fifo. +// +//***************************************************************************** +unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel) +{ + unsigned long ulOffset; + + // + // Get the fifo register offset for specified channel + // + ulOffset = ADC_O_channel0FIFODATA + ulChannel; + + // + // Return FIFO level + // + return(HWREG(ulBase + ulOffset)); +} + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.h new file mode 100755 index 00000000000..6f7095050de --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.h @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// adc.h +// +// Defines and Macros for the ADC. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// Values that can be passed to APIs as ulChannel parameter +//***************************************************************************** +#define ADC_CH_0 0x00000000 +#define ADC_CH_1 0x00000008 +#define ADC_CH_2 0x00000010 +#define ADC_CH_3 0x00000018 + + +//***************************************************************************** +// +// Values that can be passed to ADCIntEnable(), ADCIntDisable() +// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus() +// +//***************************************************************************** +#define ADC_DMA_DONE 0x00000010 +#define ADC_FIFO_OVERFLOW 0x00000008 +#define ADC_FIFO_UNDERFLOW 0x00000004 +#define ADC_FIFO_EMPTY 0x00000002 +#define ADC_FIFO_FULL 0x00000001 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void ADCEnable(unsigned long ulBase); +extern void ADCDisable(unsigned long ulBase); +extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel); +extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel); +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags); +extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel, + unsigned long ulIntFlags); +extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel); +extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel); +extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue); +extern void ADCTimerEnable(unsigned long ulBase); +extern void ADCTimerDisable(unsigned long ulBase); +extern void ADCTimerReset(unsigned long ulBase); +extern unsigned long ADCTimerValueGet(unsigned long ulBase); +extern unsigned char ADCFIFOLvlGet(unsigned long ulBase, + unsigned long ulChannel); +extern unsigned long ADCFIFORead(unsigned long ulBase, + unsigned long ulChannel); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.c new file mode 100755 index 00000000000..4033f1501c6 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.c @@ -0,0 +1,603 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// camera.c +// +// Driver for the camera controller module +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup camera_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_camera.h" +#include "inc/hw_apps_config.h" +#include "interrupt.h" +#include "camera.h" + +//****************************************************************************** +// +//! Resets the Camera core +//! +//! \param ulBase is the base address of the camera module. +//! +//! This function resets the camera core +//! +//! \return None. +// +//****************************************************************************** +void CameraReset(unsigned long ulBase) +{ + // + // Reset the camera + // + HWREG(ulBase + CAMERA_O_CC_SYSCONFIG) = CAMERA_CC_SYSCONFIG_SOFT_RESET; + + // + // Wait for reset completion + // + while(!(HWREG(ulBase + CAMERA_O_CC_SYSSTATUS)& + CAMERA_CC_SYSSTATUS_RESET_DONE2)) + { + + } + +} + +//****************************************************************************** +// +//! Configures camera parameters +//! +//! \param ulBase is the base address of the camera module. +//! \param ulHSPol sets the HSync polarity +//! \param ulVSPol sets the VSync polarity +//! \param ulFlags are configuration flags +//! +//! This function sets different camera parameters. +//! +//! The parameter \e ulHSPol should be on the follwoing: +//! - \b CAM_HS_POL_HI +//! - \b CAM_HS_POL_LO +//! +//! The parameter \e ulVSPol should be on the follwoing: +//! - \b CAM_VS_POL_HI +//! - \b CAM_VS_POL_LO +//! +//! The parameter \e ulFlags can be logical OR of one or more of the follwoing +//! or 0: +//! - \b CAM_PCLK_RISE_EDGE +//! - \b CAM_PCLK_FALL_EDGE +//! - \b CAM_ORDERCAM_SWAP +//! - \b CAM_NOBT_SYNCHRO +//! - \b CAM_IF_SYNCHRO +//! +//! \return None. +// +//****************************************************************************** +void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol, + unsigned long ulVSPol, unsigned long ulFlags) +{ + unsigned long ulReg; + + // + // Read the register + // + ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL); + + // + // Set the requested parameter + // + ulFlags = (ulFlags|ulHSPol|ulVSPol); + ulReg = ((ulReg & ~(CAMERA_CC_CTRL_NOBT_SYNCHRO | + CAMERA_CC_CTRL_NOBT_HS_POL | + CAMERA_CC_CTRL_NOBT_VS_POL | + CAMERA_CC_CTRL_BT_CORRECT | + CAMERA_CC_CTRL_PAR_ORDERCAM | + CAMERA_CC_CTRL_PAR_CLK_POL )) | ulFlags); + + // + // Write the configuration + // + HWREG(ulBase + CAMERA_O_CC_CTRL)=ulReg; +} + + +//****************************************************************************** +// +//! Set the internal clock divider +//! +//! \param ulBase is the base address of the camera module. +//! \param ulCamClkIn is input to camera module +//! \param ulXClk defines the output required +//! +//! This function sets the internal clock divider based on \e ulCamClkIn to +//! generate XCLK as specified be \e ulXClk. Maximum suppoter division is 30 +//! +//! \return None. +// +//****************************************************************************** +void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn, + unsigned long ulXClk) +{ + unsigned long ulReg; + unsigned long ucDiv; + + // + // Read the register + // + ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK); + + // + // Mask XCLK divider value + // + ulReg &= ~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M); + + // + // Compute the divider + // + ucDiv = ((ulCamClkIn)/ulXClk); + + // + // Max supported division is 30 + // + if(ucDiv > 30) + { + return; + } + + // + // Set and write back the configuration + // + ulReg |= ucDiv; + HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg; +} + + +//****************************************************************************** +// +//! Sets the internal divide in specified mode +//! +//! \param ulBase is the base address of the camera module. +//! \param bXClkFlags decides the divide mode +//! +//! This function sets the internal divide in specified mode. +//! +//! The parameter \e bXClkFlags should be one of the following : +//! +//! - \b CAM_XCLK_STABLE_LO +//! - \b CAM_XCLK_STABLE_HI +//! - \b CAM_XCLK_DIV_BYPASS +//! +//! \return None. +// +//****************************************************************************** +void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags) +{ + unsigned long ulReg; + + // + // Read and Mask XTAL Divider config. + // + ulReg = (HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) & + ~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M)); + + // + // Set config. base on parameter flag + // + switch(bXClkFlags) + { + + case CAM_XCLK_STABLE_HI : ulReg |= 0x00000001; + break; + + case CAM_XCLK_DIV_BYPASS: ulReg |= 0x0000001F; + break; + } + + // + // Write the config. + // + HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg; +} + + +//****************************************************************************** +// +//! Enable camera DMA +//! +//! \param ulBase is the base address of the camera module. +//! +//! This function enables transfer request to DMA from camera. DMA specific +//! configuration has to be done seperately. +//! +//! \return None. +// +//****************************************************************************** +void CameraDMAEnable(unsigned long ulBase) +{ + // + // Enable DMA + // + HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= CAMERA_CC_CTRL_DMA_DMA_EN; +} + + +//****************************************************************************** +// +//! Disable camera DMA +//! +//! \param ulBase is the base address of the camera module. +//! +//! This function masks transfer request to DMA from camera. +//! +//! \return None. +// +//****************************************************************************** +void CameraDMADisable(unsigned long ulBase) +{ + // + // Disable DMA + // + HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_DMA_EN; +} + + + +//****************************************************************************** +// +//! Sets the FIFO threshold for DMA transfer request +//! +//! \param ulBase is the base address of the camera module. +//! \param ulThreshold specifies the FIFO threshold +//! +//! This function sets the FIFO threshold for DMA transfer request. +//! Parameter \e ulThreshold can range from 1 - 64 +//! +//! \return None. +// +//****************************************************************************** +void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold) +{ + // + // Read and Mask DMA threshold field + // + HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M; + // + // Write the new threshold value + // + HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= (ulThreshold -1); +} + + +//****************************************************************************** +// +//! Register camera interrupt handler +//! +//! \param ulBase is the base address of the camera module. +//! \param pfnHandler hold pointer to interrupt handler +//! +//! This function registers and enables global camera interrupt from the +//! interrupt controller. Individual camera interrupts source +//! should be enabled using \sa CameraIntEnable(). +//! +//! \return None. +// +//****************************************************************************** +void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler. + // + IntRegister(INT_CAMERA, pfnHandler); + + // + // Enable the Camera interrupt. + // + IntEnable(INT_CAMERA); +} + + +//****************************************************************************** +// +//! Un-Register camera interrupt handler +//! +//! \param ulBase is the base address of the camera module. +//! +//! This function unregisters and disables global camera interrupt from the +//! interrupt controller. +//! +//! \return None. +// +//****************************************************************************** +void CameraIntUnregister(unsigned long ulBase) +{ + // + // Disable the interrupt. + // + IntDisable(INT_CAMERA); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_CAMERA); +} + + +//****************************************************************************** +//! Enables individual camera interrupt sources. +//! +//! \param ulBase is the base address of the camera module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables individual camera interrupt sources. +//! +//! the parameter \e ulIntFlags should be logical OR of one or more of the +//! following: +//! +//! - \b CAM_INT_DMA +//! - \b CAM_INT_FE +//! - \b CAM_INT_FSC_ERR +//! - \b CAM_INT_FIFO_NOEMPTY +//! - \b CAM_INT_FIFO_FULL +//! - \b CAM_INT_FIFO_THR +//! - \b CAM_INT_FIFO_OF +//! - \b CAN_INT_FIFO_UR +//! +//! \return None. +// +//****************************************************************************** +void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // unmask Camera DMA done interrupt + // + if(ulIntFlags & CAM_INT_DMA) + { + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ((1<<8)); + } + + // + // Enable specific camera interrupts + // + HWREG(ulBase + CAMERA_O_CC_IRQENABLE) |= ulIntFlags; +} + + +//****************************************************************************** +//! Disables individual camera interrupt sources. +//! +//! \param ulBase is the base address of the camera module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables individual camera interrupt sources. +//! +//! The parameter \e ulIntFlags should be logical OR of one or more of the +//! values as defined in CameraIntEnable(). +//! +//! \return None. +// +//****************************************************************************** +void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Mask Camera DMA done interrupt + // + if(ulIntFlags & CAM_INT_DMA) + { + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ((1<<8)); + } + + // + // Disable specific camera interrupts + // + HWREG(ulBase + CAMERA_O_CC_IRQENABLE) &= ~ulIntFlags; +} + +//****************************************************************************** +// +//! Returns the current interrupt status, +//! +//! \param ulBase is the base address of the camera module. +//! \param ulBase is the base address of the camera module. +//! +//! This functions returns the current interrupt status for the camera. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in CameraIntEnable(). +//****************************************************************************** +unsigned long CameraIntStatus(unsigned long ulBase) +{ + unsigned ulIntFlag; + + // + // Read camera interrupt + // + ulIntFlag = HWREG(ulBase + CAMERA_O_CC_IRQSTATUS); + + // + // + // Read camera DMA doner interrupt + // + if(HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED) & (1<<8)) + { + ulIntFlag |= CAM_INT_DMA; + } + + // + // Return status + // + return(ulIntFlag); +} + + +//****************************************************************************** +//! Clears individual camera interrupt sources. +//! +//! \param ulBase is the base address of the camera module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be Clears. +//! +//! This function Clears individual camera interrupt sources. +//! +//! The parameter \e ulIntFlags should be logical OR of one or more of the +//! values as defined in CameraIntEnable(). +//! +//! \return None. +// +//****************************************************************************** +void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Clear DMA done int status + // + if(ulIntFlags & CAM_INT_DMA) + { + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ((1<<8)); + } + + // + // Clear the interrupts + // + HWREG(ulBase + CAMERA_O_CC_IRQSTATUS) = ulIntFlags; +} + +//****************************************************************************** +// +//! Starts image capture +//! +//! \param ulBase is the base address of the camera module. +//! +//! This function starts the image capture over the configured camera interface +//! This function should be called after configuring the camera module +//! completele +//! +//! \return None. +// +//****************************************************************************** +void CameraCaptureStart(unsigned long ulBase) +{ + // + // Set the mode + // + HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~0xF; + + // + // Enable image capture + // + HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_EN; +} + +//****************************************************************************** +// +//! Stops image capture +//! +//! \param ulBase is the base address of the camera module. +//! \param bImmediate is \b true to stop capture imeediately else \b flase. +//! +//! This function stops the image capture over the camera interface. +//! The capture is stopped either immediatelt or at the end of current frame +//! based on \e bImmediate parameter. +//! +//! \return None. +// +//****************************************************************************** +void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate) +{ + if(bImmediate) + { + // + // Stop capture immediately + // + HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_FRAME_TRIG; + } + else + { + // + // Stop capture at the end of frame + // + HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_FRAME_TRIG; + } + + // + // Request camera to stop capture + // + HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_EN; +} + + +//****************************************************************************** +// +//! Reads the camera buffer (FIFO) +//! +//! \param ulBase is the base address of the camera module. +//! \param pBuffer is the pointer to the read buffer +//! \param ucSize specifies the size to data to be read +//! +//! This function reads the camera buffer (FIFO). +//! +//! \return None. +// +//****************************************************************************** +void CameraBufferRead(unsigned long ulBase, unsigned long *pBuffer, + unsigned char ucSize) +{ + unsigned char *pCamBuff; + unsigned char i; + + // + // Initilize a pointer to ecamera buffer + // + pCamBuff = (unsigned char *)CAM_BUFFER_ADDR; + + // + // Read out requested data + // + for(i=0; i < ucSize; i++) + { + *(pBuffer+i) = *(pCamBuff + i); + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.h new file mode 100755 index 00000000000..a3c08f91bae --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// camera.h +// +// Prototypes and macros for the camera controller module. +// +//***************************************************************************** + +#ifndef __CAMERA_H__ +#define __CAMERA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// Macro defining Camera buffer address +//***************************************************************************** +#define CAM_BUFFER_ADDR 0x44018100 + + +//***************************************************************************** +// Value that can be passed to CameraXClkSet(). +//***************************************************************************** +#define CAM_XCLK_STABLE_LO 0x00 +#define CAM_XCLK_STABLE_HI 0x01 +#define CAM_XCLK_DIV_BYPASS 0x02 + + +//***************************************************************************** +// Value that can be passed to CameraIntEnable(), CameraIntDisable, +// CameraIntClear() or returned from CameraIntStatus(). +//***************************************************************************** +#define CAM_INT_DMA 0x80000000 +#define CAM_INT_FE 0x00010000 +#define CAM_INT_FIFO_NOEMPTY 0x00000010 +#define CAM_INT_FIFO_FULL 0x00000008 +#define CAM_INT_FIFO_THR 0x00000004 +#define CAM_INT_FIFO_OF 0x00000002 +#define CAN_INT_FIFO_UR 0x00000001 + + +//***************************************************************************** +// Value that can be passed to CameraXClkConfig(). +//***************************************************************************** +#define CAM_HS_POL_HI 0x00000000 +#define CAM_HS_POL_LO 0x00000200 +#define CAM_VS_POL_HI 0x00000000 +#define CAM_VS_POL_LO 0x00000100 + +#define CAM_PCLK_RISE_EDGE 0x00000000 +#define CAM_PCLK_FALL_EDGE 0x00000400 + +#define CAM_ORDERCAM_SWAP 0x00000800 +#define CAM_NOBT_SYNCHRO 0x00002000 +#define CAM_IF_SYNCHRO 0x00080000 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void CameraReset(unsigned long ulBase); +extern void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol, + unsigned long ulVSPol, unsigned long ulFlags); +extern void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn, + unsigned long ulXClk); +extern void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags); +extern void CameraDMAEnable(unsigned long ulBase); +extern void CameraDMADisable(unsigned long ulBase); +extern void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold); +extern void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void CameraIntUnregister(unsigned long ulBase); +extern void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long CameraIntStatus(unsigned long ulBase); +extern void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate); +extern void CameraCaptureStart(unsigned long ulBase); +extern void CameraBufferRead(unsigned long ulBase,unsigned long *pBuffer, + unsigned char ucSize); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif //__CAMERA_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.c new file mode 100755 index 00000000000..5b01ae09303 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.c @@ -0,0 +1,356 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// cpu.c +// +// Instruction wrappers for special CPU instructions needed by the +// +// +//***************************************************************************** +#include "cpu.h" + +//***************************************************************************** +// +// Wrapper function for the CPSID instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(gcc) +unsigned long __attribute__((naked)) +CPUcpsid(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " dsb \n" + " isb \n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " dsb \n" + " isb \n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif + +#if defined(arm_cc) +unsigned long +CPUcpsid(void) +{ + // TODO: Implement it! + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function returning the state of PRIMASK (indicating whether +// interrupts are enabled or disabled). +// +//***************************************************************************** +#if defined(gcc) +unsigned long __attribute__((naked)) +CPUprimask(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUprimask(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(arm_cc) +unsigned long +CPUprimask(void) +{ + // TODO: Implement it! + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK +// on entry. +// +//***************************************************************************** +#if defined(gcc) +unsigned long __attribute__((naked)) +CPUcpsie(void) +{ + unsigned long ulRet; + + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " dsb \n" + " isb \n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " dsb \n" + " isb \n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(arm_cc) +unsigned long +CPUcpsie(void) +{ + // TODO: Implement it! + return(0); +} +#endif + +//***************************************************************************** +// +// Wrapper function for the WFI instruction. +// +//***************************************************************************** +#if defined(gcc) +void __attribute__((naked)) +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" dsb \n" + " isb \n" + " wfi \n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUwfi(void) +{ + // + // Wait for the next interrupt. + // + __asm(" dsb \n" + " isb \n" + " wfi \n"); +} +#endif +#if defined(arm_cc) +void +CPUwfi(void) +{ + // TODO: Implement it! +} +#endif + +//***************************************************************************** +// +// Wrapper function for writing the BASEPRI register. +// +//***************************************************************************** +#if defined(gcc) +void __attribute__((naked)) +CPUbasepriSet(unsigned long ulNewBasepri) +{ + + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n" + " dsb \n" + " isb \n" + " bx lr\n"); +} +#endif +#if defined(ewarm) +void +CPUbasepriSet(unsigned long ulNewBasepri) +{ + // + // Set the BASEPRI register + // + __asm(" msr BASEPRI, r0\n" + " dsb \n" + " isb \n"); +} +#endif +#if defined(arm_cc) +void +CPUbasepriSet(unsigned long ulNewBasepri) +{ + // + // Set the BASEPRI register + // + // TODO: Implement it! +} +#endif + +//***************************************************************************** +// +// Wrapper function for reading the BASEPRI register. +// +//***************************************************************************** +#if defined(gcc) +unsigned long __attribute__((naked)) +CPUbasepriGet(void) +{ + unsigned long ulRet; + + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} +#endif +#if defined(ewarm) +unsigned long +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + __asm(" mrs r0, BASEPRI\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(arm_cc) +unsigned long +CPUbasepriGet(void) +{ + // + // Read BASEPRI + // + // TODO: Implement it + return(0); +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.h new file mode 100755 index 00000000000..0b968363fa3 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/cpu.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// cpu.h +// +// Prototypes for the CPU instruction wrapper functions. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// TODO, move this to tools +#ifdef TOOLCHAIN_GCC_ARM +#define gcc +#elif TOOLCHAIN_ARM +#define arm_cc +#elif defined TOOLCHAIN_IAR +#define ewarm +#endif + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern unsigned long CPUcpsid(void); +extern unsigned long CPUcpsie(void); +extern unsigned long CPUprimask(void); +extern void CPUwfi(void); +extern unsigned long CPUbasepriGet(void); +extern void CPUbasepriSet(unsigned long ulNewBasepri); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.c new file mode 100755 index 00000000000..46f31aae3c9 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.c @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// crc.c +// +// Driver for the CRC module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup CRC_Cyclic_Redundancy_Check_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dthe.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/crc.h" +#include "driverlib/debug.h" + +//***************************************************************************** +// +//! Set the configuration of CRC functionality with the EC module. +//! +//! \param ui32Base is the base address of the EC module. +//! \param ui32CRCConfig is the configuration of the CRC engine. +//! +//! This function configures the operation of the CRC engine within the EC +//! module. The configuration is specified with the \e ui32CRCConfig argument. +//! It is the logical OR of any of the following options: +//! +//! CRC Initialization Value +//! - \b EC_CRC_CFG_INIT_SEED - Initialize with seed value +//! - \b EC_CRC_CFG_INIT_0 - Initialize to all '0s' +//! - \b EC_CRC_CFG_INIT_1 - Initialize to all '1s' +//! +//! Input Data Size +//! - \b EC_CRC_CFG_SIZE_8BIT - Input data size of 8 bits +//! - \b EC_CRC_CFG_SIZE_32BIT - Input data size of 32 bits +//! +//! Post Process Reverse/Inverse +//! - \b EC_CRC_CFG_RESINV - Result inverse enable +//! - \b EC_CRC_CFG_OBR - Output reverse enable +//! +//! Input Bit Reverse +//! - \b EC_CRC_CFG_IBR - Bit reverse enable +//! +//! Endian Control +//! - \b EC_CRC_CFG_ENDIAN_SBHW - Swap byte in half-word +//! - \b EC_CRC_CFG_ENDIAN_SHW - Swap half-word +//! +//! Operation Type +//! - \b EC_CRC_CFG_TYPE_P8005 - Polynomial 0x8005 +//! - \b EC_CRC_CFG_TYPE_P1021 - Polynomial 0x1021 +//! - \b EC_CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7 +//! - \b EC_CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41 +//! - \b EC_CRC_CFG_TYPE_TCPCHKSUM - TCP checksum +//! +//! \return None. +// +//***************************************************************************** +void +CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DTHE_BASE); + ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) || + (ui32CRCConfig & CRC_CFG_INIT_0) || + (ui32CRCConfig & CRC_CFG_INIT_1) || + (ui32CRCConfig & CRC_CFG_SIZE_8BIT) || + (ui32CRCConfig & CRC_CFG_SIZE_32BIT) || + (ui32CRCConfig & CRC_CFG_RESINV) || + (ui32CRCConfig & CRC_CFG_OBR) || + (ui32CRCConfig & CRC_CFG_IBR) || + (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) || + (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) || + (ui32CRCConfig & CRC_CFG_TYPE_P8005) || + (ui32CRCConfig & CRC_CFG_TYPE_P1021) || + (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) || + (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) || + (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM)); + + // + // Write the control register with the configuration. + // + HWREG(ui32Base + DTHE_O_CRC_CTRL) = ui32CRCConfig; +} + +//***************************************************************************** +// +//! Write the seed value for CRC operations in the EC module. +//! +//! \param ui32Base is the base address of the EC module. +//! \param ui32Seed is the seed value. +//! +//! This function writes the seed value for use with CRC operations in the +//! EC module. This value is the start value for CRC operations. If this +//! value is not written, then the residual seed from the previous operation +//! is used as the starting value. +//! +//! \note The seed must be written only if \b EC_CRC_CFG_INIT_SEED is +//! set with the CRCConfigSet() function. +// +//***************************************************************************** +void +CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DTHE_BASE); + + // + // Write the seed value to the seed register. + // + HWREG(ui32Base + DTHE_O_CRC_SEED) = ui32Seed; +} + +//***************************************************************************** +// +//! Write data into the EC module for CRC operations. +//! +//! \param ui32Base is the base address of the EC module. +//! \param ui32Data is the data to be written. +//! +//! This function writes either 8 or 32 bits of data into the EC module for +//! CRC operations. The distinction between 8 and 32 bits of data is made +//! when the \b EC_CRC_CFG_SIZE_8BIT or \b EC_CRC_CFG_SIZE_32BIT flag +//! is set using the CRCConfigSet() function. +//! +//! When writing 8 bits of data, ensure the data is in the least signficant +//! byte position. The remaining bytes should be written with zero. For +//! example, when writing 0xAB, \e ui32Data should be 0x000000AB. +//! +//! \return None +// +//***************************************************************************** +void +CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DTHE_BASE); + + // + // Write the data + // + HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data; +} + +//***************************************************************************** +// +//! Reads the result of a CRC operation in the EC module. +//! +//! \param ui32Base is the base address of the EC module. +//! +//! This function reads either the unmodified CRC result or the post +//! processed CRC result from the EC module. The post-processing options +//! are selectable through \b EC_CRC_CFG_RESINV and \b EC_CRC_CFG_OBR +//! parameters in the CRCConfigSet() function. +//! +//! \return The CRC result. +// +//***************************************************************************** +uint32_t +CRCResultRead(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DTHE_BASE); + + // + // return value. + // + return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP)); + +} + +//***************************************************************************** +// +//! Process data to generate a CRC with the EC module. +//! +//! \param ui32Base is the base address of the EC module. +//! \param puiDataIn is a pointer to an array of data that is processed. +//! \param ui32DataLength is the number of data items that are processed +//! to produce the CRC. +//! \param ui32Config the config parameter to determine the CRC mode +//! +//! This function processes an array of data to produce a CRC result. +//! This function takes the CRC mode as the parameter. +//! +//! The data in the array pointed to be \e pui32DataIn is either an array +//! of bytes or an array or words depending on the selection of the input +//! data size options \b EC_CRC_CFG_SIZE_8BIT and +//! \b EC_CRC_CFG_SIZE_32BIT. +//! +//! This function returns either the unmodified CRC result or the +//! post- processed CRC result from the EC module. The post-processing +//! options are selectable through \b EC_CRC_CFG_RESINV and +//! \b EC_CRC_CFG_OBR parameters. +//! +//! \return The CRC result. +// +//***************************************************************************** +uint32_t +CRCDataProcess(uint32_t ui32Base, void *puiDataIn, + uint32_t ui32DataLength, uint32_t ui32Config) +{ + uint8_t *pui8DataIn; + uint32_t *pui32DataIn; + + // + // Check the arguments. + // + ASSERT(ui32Base == DTHE_BASE); + + // + // See if the CRC is operating in 8-bit or 32-bit mode. + // + if(ui32Config & DTHE_CRC_CTRL_SIZE) + { + // + // The CRC is operating in 8-bit mode, so create an 8-bit pointer to + // the data. + // + pui8DataIn = (uint8_t *)puiDataIn; + + // + // Loop through the input data. + // + while(ui32DataLength--) + { + // + // Write the next data byte. + // + HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui8DataIn++; + } + } + else + { + // + // The CRC is operating in 32-bit mode, so loop through the input data. + // + pui32DataIn = (uint32_t *)puiDataIn; + while(ui32DataLength--) + { + // + // Write the next data word. + // + HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui32DataIn++; + } + } + + // + // Return the result. + // + return(CRCResultRead(ui32Base)); +} + + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.h new file mode 100755 index 00000000000..5e8d3f5e74c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/crc.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// crc.h +// +// Defines and Macros for CRC module. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_CRC_H__ +#define __DRIVERLIB_CRC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used in the ui32Config argument of the +// ECConfig function. +// +//***************************************************************************** +#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed +#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s' +#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s' +#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size +#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size +#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable +#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable +#define CRC_CFG_IBR 0x00000080 // Bit reverse enable +#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word +#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word +#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005 +#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021 +#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7 +#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41 +#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum + +//***************************************************************************** +// +// Function prototypes. +// +//***************************************************************************** +extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig); +extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn, + uint32_t ui32DataLength, uint32_t ui32Config); +extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data); +extern uint32_t CRCResultRead(uint32_t ui32Base); +extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_CRC_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/debug.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/debug.h new file mode 100755 index 00000000000..cef10a43ab9 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/debug.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// debug.h +// +// Macros for assisting debug of the driver library. +// +//***************************************************************************** +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.c new file mode 100755 index 00000000000..890a0447728 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.c @@ -0,0 +1,864 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// flash.c +// +// Driver for programming the on-chip flash. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_flash_ctrl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ints.h" +#include "inc/hw_gprcm.h" +#include "inc/hw_hib1p2.h" +#include "inc/hw_hib3p3.h" +#include "inc/hw_common_reg.h" +#include "inc/hw_stack_die_ctrl.h" +#include "debug.h" +#include "flash.h" +#include "utils.h" +#include "interrupt.h" + +#define HAVE_WRITE_BUFFER 1 + + + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Program Enable (FMPPE) register. +// +//***************************************************************************** +static const unsigned long g_pulFMPPERegs[] = +{ + FLASH_FMPPE0, + FLASH_FMPPE1, + FLASH_FMPPE2, + FLASH_FMPPE3, + FLASH_FMPPE4, + FLASH_FMPPE5, + FLASH_FMPPE6, + FLASH_FMPPE7, + FLASH_FMPPE8, + FLASH_FMPPE9, + FLASH_FMPPE10, + FLASH_FMPPE11, + FLASH_FMPPE12, + FLASH_FMPPE13, + FLASH_FMPPE14, + FLASH_FMPPE15 + + +}; + +//***************************************************************************** +// +// An array that maps the specified memory bank to the appropriate Flash +// Memory Protection Read Enable (FMPRE) register. +// +//***************************************************************************** +static const unsigned long g_pulFMPRERegs[] = +{ + FLASH_FMPRE0, + FLASH_FMPRE1, + FLASH_FMPRE2, + FLASH_FMPRE3, + FLASH_FMPRE4, + FLASH_FMPRE5, + FLASH_FMPRE6, + FLASH_FMPRE7, + FLASH_FMPRE8, + FLASH_FMPRE9, + FLASH_FMPRE10, + FLASH_FMPRE11, + FLASH_FMPRE12, + FLASH_FMPRE13, + FLASH_FMPRE14, + FLASH_FMPRE15, +}; + +//***************************************************************************** +// +//! Flash Disable +//! +//! This function Disables the internal Flash. +//! +//! \return None. +// +//***************************************************************************** +void +FlashDisable() +{ + + // + // Wait for Flash Busy to get cleared + // + while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) + & GPRCM_TOP_DIE_ENABLE_FLASH_BUSY)) + { + + } + + // + // Assert reset + // + HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000; + + // + // 50 usec Delay Loop + // + UtilsDelay((50*80)/3); + + // + // Disable TDFlash + // + HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0; + + // + // 50 usec Delay Loop + // + UtilsDelay((50*80)/3); + + HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; + + // + // 50 usec Delay Loop + // + UtilsDelay((50*80)/3); +} + + +//***************************************************************************** +// +//! Erases a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be erased. +//! +//! This function will erase a 2 kB block of the on-chip flash. After erasing, +//! the block will be filled with 0xFF bytes. Read-only and execute-only +//! blocks cannot be erased. +//! +//! This function will not return until the block has been erased. +//! +//! \return Returns 0 on success, or -1 if an invalid block address was +//! specified or the block is write-protected. +// +//***************************************************************************** +long +FlashErase(unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1))); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) + = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_ERMISC); + + // Erase the block. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) + = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE; + + // + // Wait until the block has been erased. + // + while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE) + { + } + + // + // Return an error if an access violation or erase error occurred. + // + if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) + & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | + FLASH_CTRL_FCRIS_ERRIS)) + + + { + return(-1); + } + + // + // Success. + // + return(0); +} + + +//***************************************************************************** +// +//! Erases a block of flash but does not wait for completion. +//! +//! \param ulAddress is the start address of the flash block to be erased. +//! +//! This function will erase a 2 kB block of the on-chip flash. After erasing, +//! the block will be filled with 0xFF bytes. Read-only and execute-only +//! blocks cannot be erased. +//! +//! This function will return immediately after commanding the erase operation. +//! Applications making use of the function can determine completion state by +//! using a flash interrupt handler or by polling FlashIntStatus. +//! +//! \return None. +// +//***************************************************************************** +void +FlashEraseNonBlocking(unsigned long ulAddress) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1))); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = + (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_ERMISC); + + // + // Command the flash controller to erase the block. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE; +} + + +//***************************************************************************** +// +//! Erases a complele flash at shot. +//! +//! This function erases a complele flash at shot +//! +//! \return Returns 0 on success, or -1 if the block is write-protected. +// +//***************************************************************************** +long +FlashMassErase() +{ + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = + (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_ERMISC); + + // + // Command the flash controller for mass erase. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = + FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1; + + // + // Wait until mass erase completes. + // + while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_MERASE1) + { + + } + + // + // Return an error if an access violation or erase error occurred. + // + if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) + & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | + FLASH_CTRL_FCRIS_ERRIS)) + { + return -1; + } + + // + // Success. + // + return 0; +} + +//***************************************************************************** +// +//! Erases a complele flash at shot but does not wait for completion. +//! +//! +//! This function will not return until the Flash has been erased. +//! +//! \return None. +// +//***************************************************************************** +void +FlashMassEraseNonBlocking() +{ + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = + (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_ERMISC); + + // + // Command the flash controller for mass erase. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = + FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1; + +} + +//***************************************************************************** +// +//! Programs flash. +//! +//! \param pulData is a pointer to the data to be programmed. +//! \param ulAddress is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ulCount is the number of bytes to be programmed. Must be a multiple +//! of four. +//! +//! This function will program a sequence of words into the on-chip flash. +//! Each word in a page of flash can only be programmed one time between an +//! erase of that page; programming a word multiple times will result in an +//! unpredictable value in that word of flash. +//! +//! Since the flash is programmed one word at a time, the starting address and +//! byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function will not return until the data has been programmed. +//! +//! \return Returns 0 on success, or -1 if a programming error is encountered. +// +//***************************************************************************** +long +FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & 3)); + ASSERT(!(ulCount & 3)); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) + = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC); + + + // + // See if this device has a write buffer. + // + +#if HAVE_WRITE_BUFFER + { + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Set the address of this block of words. for 1 MB + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F); + + // + // Loop over the words in this 32-word block. + // + while(((ulAddress & 0x7C) || + (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) && + (ulCount != 0)) + { + // + // Write this word into the write buffer. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + + (ulAddress & 0x7C)) = *pulData++; + ulAddress += 4; + ulCount -= 4; + } + + // + // Program the contents of the write buffer into flash. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) + = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF; + + // + // Wait until the write buffer has been programmed. + // + while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) & FLASH_CTRL_FMC2_WRBUF) + { + } + } + } +#else + { + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Program the next word. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE; + + // + // Wait until the word has been programmed. + // + while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_WRITE) + { + } + + // + // Increment to the next word. + // + pulData++; + ulAddress += 4; + ulCount -= 4; + } + } +#endif + // + // Return an error if an access violation occurred. + // + + if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | + FLASH_CTRL_FCRIS_INVDRIS | FLASH_CTRL_FCRIS_PROGRIS)) + + { + return(-1); + } + + // + // Success. + // + return(0); +} + + +//***************************************************************************** +// +//! Programs flash but does not poll for completion. +//! +//! \param pulData is a pointer to the data to be programmed. +//! \param ulAddress is the starting address in flash to be programmed. Must +//! be a multiple of four. +//! \param ulCount is the number of bytes to be programmed. Must be a multiple +//! of four. +//! +//! This function will start programming one or more words into the on-chip +//! flash and return immediately. The number of words that can be programmed +//! in a single call depends the part on which the function is running. For +//! parts without support for a flash write buffer, only a single word may be +//! programmed on each call to this function (\e ulCount must be 1). If a +//! write buffer is present, up to 32 words may be programmed on condition +//! that the block being programmed does not straddle a 32 word address +//! boundary. For example, wherease 32 words can be programmed if the address +//! passed is 0x100 (a multiple of 128 bytes or 32 words), only 31 words could +//! be programmed at 0x104 since attempting to write 32 would cross the 32 +//! word boundary at 0x180. +//! +//! Since the flash is programmed one word at a time, the starting address and +//! byte count must both be multiples of four. It is up to the caller to +//! verify the programmed contents, if such verification is required. +//! +//! This function will return immediately after commanding the erase operation. +//! Applications making use of the function can determine completion state by +//! using a flash interrupt handler or by polling FlashIntStatus. +//! +//! \return 0 if the write was started successfully, -1 if there was an error. +// +//***************************************************************************** +long +FlashProgramNonBlocking(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount) +{ + // + // Check the arguments. + // + ASSERT(!(ulAddress & 3)); + ASSERT(!(ulCount & 3)); + + // + // Clear the flash access and error interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) + = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | + FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC); + + // + // See if this device has a write buffer. + // + +#if HAVE_WRITE_BUFFER + { + // + // Make sure the address/count specified doesn't straddle a 32 word + // boundary. + // + if(((ulAddress + (ulCount - 1)) & ~0x7F) != (ulAddress & ~0x7F)) + { + return(-1); + } + + // + // Loop over the words to be programmed. + // + while(ulCount) + { + // + // Set the address of this block of words. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F); + + // + // Loop over the words in this 32-word block. + // + while(((ulAddress & 0x7C) || (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) && + (ulCount != 0)) + { + // + // Write this word into the write buffer. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + (ulAddress & 0x7C)) = *pulData++; + ulAddress += 4; + ulCount -= 4; + } + + // + // Program the contents of the write buffer into flash. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF; + } + } +#else + { + // + // We don't have a write buffer so we can only write a single word. + // + if(ulCount > 1) + { + return(-1); + } + + // + // Write a single word. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData; + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE; + } +#endif + // + // Success. + // + return(0); +} + + +//***************************************************************************** +// +//! Gets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be queried. +//! +//! This function gets the current protection for the specified 2-kB block +//! of flash. Each block can be read/write, read-only, or execute-only. +//! Read/write blocks can be read, executed, erased, and programmed. Read-only +//! blocks can be read and executed. Execute-only blocks can only be executed; +//! processor and debugger data reads are not allowed. +//! +//! \return Returns the protection setting for this block. See +//! FlashProtectSet() for possible values. +// +//***************************************************************************** +tFlashProtection +FlashProtectGet(unsigned long ulAddress) +{ + unsigned long ulFMPRE, ulFMPPE; + unsigned long ulBank; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + + // + // Calculate the Flash Bank from Base Address, and mask off the Bank + // from ulAddress for subsequent reference. + // + ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 16); + ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1); + + // + // Read the appropriate flash protection registers for the specified + // flash bank. + // + ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]); + ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]); + + // + // Check the appropriate protection bits for the block of memory that + // is specified by the address. + // + switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & + FLASH_FMP_BLOCK_0) << 1) | + ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) + { + // + // This block is marked as execute only (that is, it can not be erased + // or programmed, and the only reads allowed are via the instruction + // fetch interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (that is, it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This sets the handler to be called when the flash interrupt occurs. The +//! flash controller can generate an interrupt when an invalid flash access +//! occurs, such as trying to program or erase a read-only block, or trying to +//! read from an execute-only block. It can also generate an interrupt when a +//! program or erase operation has completed. The interrupt will be +//! automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function will clear the handler to be called when the flash interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH); +} + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values. +//! +//! Enables the indicated flash controller interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values. +//! +//! Disables the indicated flash controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the flash controller. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_CTRL_PROGRAM and \b FLASH_CTRL_ACCESS. +// +//***************************************************************************** +unsigned long +FlashIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)); + } + else + { + return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)); + } +} + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_AMISC values. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. This must be done in the interrupt handler to keep it +//! from being called again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +FlashIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = ulIntFlags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.h new file mode 100755 index 00000000000..75cf0cfd8db --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// flash.h +// +// Prototypes for the flash driver. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask +#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask +#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask +#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask +#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask +#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void FlashDisable(void); +extern long FlashErase(unsigned long ulAddress); +extern void FlashEraseNonBlocking(unsigned long ulAddress); +extern long FlashMassErase(void); +extern void FlashMassEraseNonBlocking(void); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern long FlashProgramNonBlocking(unsigned long *pulData, + unsigned long ulAddress, + unsigned long ulCount); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.c new file mode 100755 index 00000000000..e2c5ff2aa89 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.c @@ -0,0 +1,717 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// gpio.c +// +// Driver for the GPIO module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup GPIO_General_Purpose_InputOutput_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_gpio.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_common_reg.h" +#include "debug.h" +#include "gpio.h" +#include "interrupt.h" + + +//***************************************************************************** +// +//! \internal +//! Checks a GPIO base address. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function determines if a GPIO port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +GPIOBaseValid(unsigned long ulPort) +{ + return((ulPort == GPIOA0_BASE) || + (ulPort == GPIOA1_BASE) || + (ulPort == GPIOA2_BASE) || + (ulPort == GPIOA3_BASE) || + (ulPort == GPIOA4_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the GPIO interrupt number. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! Given a GPIO base address, returns the corresponding interrupt number. +//! +//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +long +GPIOGetIntNumber(unsigned long ulPort) +{ + unsigned int ulInt; + + // + // Determine the GPIO interrupt number for the given module. + // + switch(ulPort) + { + case GPIOA0_BASE: + { + ulInt = INT_GPIOA0; + break; + } + + case GPIOA1_BASE: + { + ulInt = INT_GPIOA1; + break; + } + + case GPIOA2_BASE: + { + ulInt = INT_GPIOA2; + break; + } + + case GPIOA3_BASE: + { + ulInt = INT_GPIOA3; + break; + } + + default: + { + return(-1); + } + } + + // + // Return GPIO interrupt number. + // + return(ulInt); +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulPinIO is the pin direction and/or mode. +//! +//! This function will set the specified pin(s) on the selected GPIO port +//! as either an input or output under software control, or it will set the +//! pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as +//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin +//! will be programmed as a software controlled output. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note GPIOPadConfigSet() must also be used to configure the corresponding +//! pad(s) in order for them to propagate the signal to/from the GPIO. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT)); + + // + // Set the pin direction and mode. + // + HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ? + (HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) : + (HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the direction and mode of a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +unsigned long +GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulDir; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // Not needed because pin mask is pass in directly + //ucPin = 1 << ucPin; + + // + // Return the pin direction and mode. + // + ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR); + return(((ulDir & ucPin) ? 1 : 0)); +} + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ulIntType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin(s) on the selected GPIO port. +//! +//! The parameter \e ulIntType is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_FALLING_EDGE +//! - \b GPIO_RISING_EDGE +//! - \b GPIO_BOTH_EDGES +//! - \b GPIO_LOW_LEVEL +//! - \b GPIO_HIGH_LEVEL +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note In order to avoid any spurious interrupts, the user must +//! ensure that the GPIO inputs remain stable for the duration of +//! this function. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT((ulIntType == GPIO_FALLING_EDGE) || + (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) || + (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL)); + + // + // Set the pin interrupt type. + // + HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ? + (HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) : + (HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins))); + HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ? + (HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) : + (HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins))); + HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ? + (HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) : + (HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins))); +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPin is the pin number. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling edge, rising edge, or +//! both edge detected interrupt, or it can be configured as a low level or +//! high level detected interrupt. The type of interrupt detection mechanism +//! is returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIOIntTypeSet(). +// +//***************************************************************************** +unsigned long +GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulIBE, ulIS, ulIEV; + + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // Not needed because using the pin mask is pass in directly + //ucPin = 1 << ucPin; + + // + // Return the pin interrupt type. + // + ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE); + ulIS = HWREG(ulPort + GPIO_O_GPIO_IS); + ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV); + return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | + ((ulIEV & ucPin) ? 4 : 0)); +} + +//***************************************************************************** +// +//! Enables the specified GPIO interrupts. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ulIntFlags is the bit mask of the interrupt sources to enable. +//! +//! This function enables the indicated GPIO interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done +//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. +//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. +//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. +//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. +//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. +//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. +//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. +//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Enable the interrupts. + // + HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables the specified GPIO interrupts. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ulIntFlags is the bit mask of the interrupt sources to disable. +//! +//! This function disables the indicated GPIO interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done +//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. +//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. +//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. +//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. +//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. +//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. +//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. +//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Disable the interrupts. + // + HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets interrupt status for the specified GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in GPIOIntEnable(). +// +//***************************************************************************** +long +GPIOIntStatus(unsigned long ulPort, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ulPort + GPIO_O_GPIO_MIS)); + } + else + { + return(HWREG(ulPort + GPIO_O_GPIO_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the interrupt for the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! Clears the interrupt for the specified pin(s). +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to GPIOIntEnable(). +//! +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Clear the interrupts. + // + HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling +//! function. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function will also enable the corresponding GPIO interrupt +//! in the interrupt controller; individual pin interrupts and interrupt +//! sources must be enabled with GPIOIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Register the interrupt handler. + // + IntRegister(ulPort, pfnIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ulPort); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for a GPIO port. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function will unregister the interrupt handler for the specified +//! GPIO port. This function will also disable the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntUnregister(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Disable the GPIO interrupt. + // + IntDisable(ulPort); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulPort); +} + +//***************************************************************************** +// +//! Reads the values present of the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! +//! The values at the specified pin(s) are read, as specified by \e ucPins. +//! Values are returned for both input and output pin(s), and the value +//! for pin(s) that are not specified by \e ucPins are set to 0. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +long +GPIOPinRead(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Return the pin value(s). + // + return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2)))); +} + +//***************************************************************************** +// +//! Writes a value to the specified pin(s). +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins is the bit-packed representation of the pin(s). +//! \param ucVal is the value to write to the pin(s). +//! +//! Writes the corresponding bit values to the output pin(s) specified by +//! \e ucPins. Writing to a pin configured as an input pin has no effect. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Write the pins. + // + HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal; +} + +//***************************************************************************** +// +//! Enables a GPIO port as a trigger to start a DMA transaction. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function enables a GPIO port to be used as a trigger to start a uDMA +//! transaction. The GPIO pin will still generate interrupts if the interrupt is +//! enabled for the selected pin. +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerEnable(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + if(ulPort == GPIOA0_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1; + } + else if(ulPort == GPIOA1_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2; + } + else if(ulPort == GPIOA2_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4; + } + else if(ulPort == GPIOA3_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8; + } +} + +//***************************************************************************** +// +//! Disables a GPIO port as a trigger to start a DMA transaction. +//! +//! \param ulPort is the base address of the GPIO port. +//! +//! This function disables a GPIO port to be used as a trigger to start a uDMA +//! transaction. This function can be used to disable this feature if it was +//! enabled via a call to GPIODMATriggerEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +GPIODMATriggerDisable(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT(GPIOBaseValid(ulPort)); + + // + // Set the pin as a DMA trigger. + // + if(ulPort == GPIOA0_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1; + } + else if(ulPort == GPIOA1_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2; + } + else if(ulPort == GPIOA2_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4; + } + else if(ulPort == GPIOA3_BASE) + { + HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8; + } +} + + +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.h new file mode 100755 index 00000000000..e1560089403 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/gpio.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// gpio.h +// +// Defines and Macros for GPIO API. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions +// in the ulIntFlags parameter. +// +//***************************************************************************** +#define GPIO_INT_DMA 0x00000100 +#define GPIO_INT_PIN_0 0x00000001 +#define GPIO_INT_PIN_1 0x00000002 +#define GPIO_INT_PIN_2 0x00000004 +#define GPIO_INT_PIN_3 0x00000008 +#define GPIO_INT_PIN_4 0x00000010 +#define GPIO_INT_PIN_5 0x00000020 +#define GPIO_INT_PIN_6 0x00000040 +#define GPIO_INT_PIN_7 0x00000080 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern void GPIODMATriggerEnable(unsigned long ulPort); +extern void GPIODMATriggerDisable(unsigned long ulPort); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags); +extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags); +extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags); +extern void GPIOIntRegister(unsigned long ulPort, + void (*pfnIntHandler)(void)); +extern void GPIOIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern long GPIOGetIntNumber(unsigned long ulPort); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.c new file mode 100755 index 00000000000..b4b87e75fee --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.c @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// hwspinlock.c +// +// Driver for the Apps-NWP spinlock +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup HwSpinLock_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ints.h" +#include "inc/hw_common_reg.h" +#include "hwspinlock.h" + +//***************************************************************************** +// Global semaphore register list +//***************************************************************************** +static const uint32_t HwSpinLock_RegLst[]= +{ + COMMON_REG_BASE + COMMON_REG_O_SPI_Properties_Register +}; + +//***************************************************************************** +// +//! Acquire specified spin lock. +//! +//! \param ui32LockID is one of the valid spin lock. +//! +//! This function acquires specified spin lock and will not retun util the +//! specified lock is acquired. +//! +//! The parameter \e ui32LockID should \b HWSPINLOCK_MCSPIS0. +//! +//! return None. +// +//***************************************************************************** +void HwSpinLockAcquire(uint32_t ui32LockID) +{ + uint32_t ui32BitPos; + uint32_t ui32SemVal; + uint32_t ui32RegAddr; + + // + // Extract the bit position from the + // LockID + // + ui32BitPos = ((ui32LockID >> 16) & 0x0FFF); + ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF]; + + // + // Set the corresponding + // ownership bits to 'b01 + // + ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos)); + + // + // Retry untill we succeed + // + do + { + HWREG(ui32RegAddr) = ui32SemVal; + } + while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) ); + +} + +//***************************************************************************** +// +//! Try to acquire specified spin lock. +//! +//! \param ui32LockID is one of the valid spin lock. +//! \param ui32Retry is the number of reties. +//! +//! This function tries acquire specified spin lock in \e ui32Retry retries. +//! +//! The parameter \e ui32Retry can be any value between 0 and 2^32. +//! +//! return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry) +{ + uint32_t ui32BitPos; + uint32_t ui32SemVal; + uint32_t ui32RegAddr; + + // + // Extract the bit position from the + // LockID + // + ui32BitPos = ((ui32LockID >> 16) & 0x0FFF); + ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF]; + + // + // Set the corresponding + // ownership bits to 'b01 + // + ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos)); + + // + // Check for 0 retry. + // + if(ui32Retry == 0) + { + ui32Retry = 1; + } + + // + // Retry the number of times specified + // + do + { + HWREG(ui32RegAddr) = ui32SemVal; + ui32Retry--; + } + while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) && ui32Retry ); + + + // + // Check the semaphore status + // + if(HWREG(ui32RegAddr) & (1 << ui32BitPos )) + { + return 0; + } + else + { + return -1; + } +} + +//***************************************************************************** +// +//! Release a previously owned spin lock +//! +//! \param ui32LockID is one of the valid spin lock. +//! +//! This function releases previously owned spin lock. +//! +//! \return None. +// +//***************************************************************************** +void HwSpinLockRelease(uint32_t ui32LockID) +{ + uint32_t ui32BitPos; + uint32_t ui32SemVal; + + // + // Extract the bit position from the + // lock id. + // + ui32BitPos = ((ui32LockID >> 16) & 0x00FF); + + // + // Release the spin lock, only if already owned + // + if(HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) & (1 << ui32BitPos )) + { + ui32SemVal = (0xFFFFFFFF & ~(0x3 << ui32BitPos)); + HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) = ui32SemVal; + } +} + +//***************************************************************************** +// +//! Get the current or previous ownership status. +//! +//! \param ui32LockID is one of the valid spin lock. +//! \param bCurrentStatus is \b true for current status, \b flase otherwise +//! +//! This function gets the current or previous ownership status of the +//! specified spin lock based on \e bCurrentStatus parameter. +//! +//! \return Returns \b HWSPINLOCK_OWNER_APPS, \b HWSPINLOCK_OWNER_NWP or +//! \b HWSPINLOCK_OWNER_NONE. +// +//***************************************************************************** +uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus) +{ + uint32_t ui32BitPos; + uint32_t ui32SemVal; + + if(bCurrentStatus) + { + // + // Extract the bit position from the + // lock id. + // + ui32BitPos = ((ui32LockID >> 16) & 0x00FF); + + // + // return semaphore + // + return((HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) >> ui32BitPos ) & 0x3 ); + } + else + { + // + // Extract the bit position + // + ui32BitPos = ((ui32LockID >> 24) & 0xFF); + + // + // Identify which register to read + // + if((ui32LockID & 0xF) > 4) + { + ui32SemVal = ((HWREG(COMMON_REG_BASE + + COMMON_REG_O_SEMAPHORE_PREV_OWNER1) >> ui32BitPos ) & 0x3); + } + else + { + ui32SemVal = ((HWREG(COMMON_REG_BASE + + COMMON_REG_O_SEMAPHORE_PREV_OWNER2) >> ui32BitPos ) & 0x3); + } + + // + // return the owner + // + return ui32SemVal; + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.h new file mode 100755 index 00000000000..70277321208 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// hwspinlock.h +// +// Prototypes for the Apps-NWP spinlock. +// +//***************************************************************************** + +#ifndef __HWSPINLOCK_H__ +#define __HWSPINLOCK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// values that can be passed to API as ui32LockID parameter +//***************************************************************************** +#define HWSPINLOCK_SSPI 0x02000000 + +//***************************************************************************** +// Values that are returned from HwSpinLockTest() +//***************************************************************************** +#define HWSPINLOCK_OWNER_APPS 0x00000001 +#define HWSPINLOCK_OWNER_NWP 0x00000002 +#define HWSPINLOCK_OWNER_NONE 0x00000000 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void HwSpinLockAcquire(uint32_t ui32LockID); +extern int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry); +extern void HwSpinLockRelease(uint32_t ui32LockID); +extern uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HWSPINLOCK_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.c new file mode 100755 index 00000000000..8f4c00a17d8 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.c @@ -0,0 +1,1013 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// i2s.c +// +// Driver for the I2S interface. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup I2S_api +//! @{ +// +//***************************************************************************** +#include "inc/hw_types.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_mcasp.h" +#include "inc/hw_apps_config.h" +#include "interrupt.h" +#include "i2s.h" + +//***************************************************************************** +// Macros +//***************************************************************************** +#define MCASP_GBL_RCLK 0x00000001 +#define MCASP_GBL_RHCLK 0x00000002 +#define MCASP_GBL_RSER 0x00000004 +#define MCASP_GBL_RSM 0x00000008 +#define MCASP_GBL_RFSYNC 0x00000010 +#define MCASP_GBL_XCLK 0x00000100 +#define MCASP_GBL_XHCLK 0x00000200 +#define MCASP_GBL_XSER 0x00000400 +#define MCASP_GBL_XSM 0x00000800 +#define MCASP_GBL_XFSYNC 0x00001000 + + +//***************************************************************************** +// +//! \internal +//! Releases the specifed submodule out of reset. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulFlag is one of the valid sub module. +//! +//! This function Releases the specifed submodule out of reset. +//! +//! \return None. +// +//***************************************************************************** +static void I2SGBLEnable(unsigned long ulBase, unsigned long ulFlag) +{ + unsigned long ulReg; + + // + // Read global control register + // + ulReg = HWREG(ulBase + MCASP_O_GBLCTL); + + // + // Remove the sub modules reset as specified by ulFlag parameter + // + ulReg |= ulFlag; + + // + // Write the configuration + // + HWREG(ulBase + MCASP_O_GBLCTL) = ulReg; + + // + // Wait for write completeion + // + while(HWREG(ulBase + MCASP_O_GBLCTL) != ulReg) + { + + } + +} + +//***************************************************************************** +// +//! Enables transmit and/or receive. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulMode is one of the valid modes. +//! +//! This function enables the I2S module in specified mode. The parameter +//! \e ulMode should be one of the following +//! +//! -\b I2S_MODE_TX_ONLY +//! -\b I2S_MODE_TX_RX_SYNC +//! +//! \return None. +// +//***************************************************************************** +void I2SEnable(unsigned long ulBase, unsigned long ulMode) +{ + // + // FSYNC and Bit clock are output only in master mode + // + if( HWREG(ulBase + MCASP_O_ACLKXCTL) & 0x20) + { + // + // Set FSYNC anc BitClk as output + // + HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000; + } + + + if(ulMode & 0x2) + { + // + // Remove Rx HCLK reset + // + I2SGBLEnable(ulBase, MCASP_GBL_RHCLK); + + // + // Remove Rx XCLK reset + // + I2SGBLEnable(ulBase, MCASP_GBL_RCLK); + + // + // Enable Rx SERDES(s) + // + I2SGBLEnable(ulBase, MCASP_GBL_RSER); + + // + // Enable Rx state machine + // + I2SGBLEnable(ulBase, MCASP_GBL_RSM); + + // + // Enable FSync generator + // + I2SGBLEnable(ulBase, MCASP_GBL_RFSYNC); + } + + + // + // Remove Tx HCLK reset + // + I2SGBLEnable(ulBase, MCASP_GBL_XHCLK); + + // + // Remove Tx XCLK reset + // + I2SGBLEnable(ulBase, MCASP_GBL_XCLK); + + + if(ulMode & 0x1) + { + // + // Enable Tx SERDES(s) + // + I2SGBLEnable(ulBase, MCASP_GBL_XSER); + + // + // Enable Tx state machine + // + I2SGBLEnable(ulBase, MCASP_GBL_XSM); + } + + // + // Enable FSync generator + // + I2SGBLEnable(ulBase, MCASP_GBL_XFSYNC); +} + +//***************************************************************************** +// +//! Disables transmit and/or receive. +//! +//! \param ulBase is the base address of the I2S module. +//! +//! This function disables transmit and/or receive from I2S module. +//! +//! \return None. +// +//***************************************************************************** +void I2SDisable(unsigned long ulBase) +{ + // + // Reset all sub modules + // + HWREG(ulBase + MCASP_O_GBLCTL) = 0; + + // + // Wait for write to complete + // + while( HWREG(ulBase + MCASP_O_GBLCTL) != 0) + { + + } +} + +//***************************************************************************** +// +//! Waits to send data over the specified data line +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulDataLine is one of the valid data lines. +//! \param ulData is the data to be transmitted. +//! +//! This function sends the \e ucData to the transmit register for the +//! specified data line. If there is no space available, this +//! function waits until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine, + unsigned long ulData) +{ + // + // Compute register the offeset + // + ulDataLine = (ulDataLine-1) << 2; + + // + // Wait for free space in fifo + // + while(!( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA)) + { + + } + + // + // Write Data into the FIFO + // + HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData; +} + +//***************************************************************************** +// +//! Sends data over the specified data line +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulDataLine is one of the valid data lines. +//! \param ulData is the data to be transmitted. +//! +//! This function writes the \e ucData to the transmit register for +//! the specified data line. This function does not block, so if there is no +//! space available, then \b -1 is returned, and the application must retry the +//! function later. +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +long I2SDataPutNonBlocking(unsigned long ulBase, unsigned long ulDataLine, + unsigned long ulData) +{ + + // + // Compute register the offeset + // + ulDataLine = (ulDataLine-1) << 2; + + // + // Send Data if fifo has free space + // + if( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA) + { + // + // Write data into the FIFO + // + HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData; + return 0; + } + + // + // FIFO is full + // + return(-1); +} + +//***************************************************************************** +// +//! Waits for data from the specified data line. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulDataLine is one of the valid data lines. +//! \param pulData is pointer to receive data variable. +//! +//! This function gets data from the receive register for the specified +//! data line. If there are no data available, this function waits until a +//! receive before returning. +//! +//! \return None. +// +//***************************************************************************** +void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine, + unsigned long *pulData) +{ + + // + // Compute register the offeset + // + ulDataLine = (ulDataLine-1) << 2; + + // + // Wait for atleat on word in FIFO + // + while(!(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA)) + { + + } + + // + // Read the Data + // + *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine); +} + + +//***************************************************************************** +// +//! Receives data from the specified data line. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulDataLine is one of the valid data lines. +//! \param pulData is pointer to receive data variable. +//! +//! This function gets data from the receive register for the specified +//! data line. +//! +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +long I2SDataGetNonBlocking(unsigned long ulBase, unsigned long ulDataLine, + unsigned long *pulData) +{ + + // + // Compute register the offeset + // + ulDataLine = (ulDataLine-1) << 2; + + // + // Check if data is available in FIFO + // + if(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA) + { + // + // Read the Data + // + *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine); + return 0; + } + + // + // FIFO is empty + // + return -1; +} + + +//***************************************************************************** +// +//! Sets the configuration of the I2S module. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulI2SClk is the rate of the clock supplied to the I2S module. +//! \param ulBitClk is the desired bit rate. +//! \param ulConfig is the data format. +//! +//! This function configures the I2S for operation in the specified data +//! format. The bit rate is provided in the \e ulBitClk parameter and the data +//! format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the slot size +//! the data read/write port select, Master or Slave mode +//! +//! Follwoing selects the Master-Slave mode +//! -\b I2S_MODE_MASTER +//! -\b I2S_MODE_SLAVE +//! +//! Following selects the slot size: +//! -\b I2S_SLOT_SIZE_24 +//! -\b I2S_SLOT_SIZE_16 +//! +//! Following selects the data read/write port: +//! -\b I2S_PORT_DMA +//! -\b I2S_PORT_CPU +//! +//! \return None. +// +//***************************************************************************** +void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk, + unsigned long ulBitClk, unsigned long ulConfig) +{ + unsigned long ulHClkDiv; + unsigned long ulClkDiv; + unsigned long ulSlotSize; + unsigned long ulBitMask; + + // + // Calculate clock dividers + // + ulHClkDiv = ((ulI2SClk/ulBitClk)-1); + ulClkDiv = 0; + + // + // Check if HCLK divider is overflowing + // + if(ulHClkDiv > 0xFFF) + { + ulHClkDiv = 0xFFF; + + // + // Calculate clock divider + // + ulClkDiv = ((ulI2SClk/(ulBitClk * (ulHClkDiv + 1))) & 0x1F); + } + + // + // + // + ulClkDiv = ((ulConfig & I2S_MODE_SLAVE )?0x80:0xA0|ulClkDiv); + + HWREG(ulBase + MCASP_O_ACLKXCTL) = ulClkDiv; + + HWREG(ulBase + MCASP_O_AHCLKXCTL) = (0x8000|ulHClkDiv); + + // + // Write the Tx format register + // + HWREG(ulBase + MCASP_O_TXFMT) = (0x18000 | (ulConfig & 0x7FFF)); + + // + // Write the Rx format register + // + HWREG(ulBase + MCASP_O_RXFMT) = (0x18000 | ((ulConfig >> 16) &0x7FFF)); + + // + // Check if in master mode + // + if( ulConfig & I2S_MODE_SLAVE) + { + // + // Configure Tx FSync generator in I2S mode + // + HWREG(ulBase + MCASP_O_TXFMCTL) = 0x111; + + // + // Configure Rx FSync generator in I2S mode + // + HWREG(ulBase + MCASP_O_RXFMCTL) = 0x111; + } + else + { + // + // Configure Tx FSync generator in I2S mode + // + HWREG(ulBase + MCASP_O_TXFMCTL) = 0x113; + + // + // Configure Rx FSync generator in I2S mode + // + HWREG(ulBase + MCASP_O_RXFMCTL) = 0x113; + } + + // + // Compute Slot Size + // + ulSlotSize = ((((ulConfig & 0xFF) >> 4) + 1) * 2); + + // + // Creat the bit mask + // + ulBitMask = (0xFFFFFFFF >> (32 - ulSlotSize)); + + // + // Set Tx bit valid mask + // + HWREG(ulBase + MCASP_O_TXMASK) = ulBitMask; + + // + // Set Rx bit valid mask + // + HWREG(ulBase + MCASP_O_RXMASK) = ulBitMask; + + // + // Set Tx slot valid mask + // + HWREG(ulBase + MCASP_O_TXTDM) = 0x3; + + // + // Set Rx slot valid mask + // + HWREG(ulBase + MCASP_O_RXTDM) = 0x3; +} + +//***************************************************************************** +// +//! Configure and enable transmit FIFO. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulTxLevel is the transmit FIFO DMA request level. +//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO. +//! +//! This function configures and enable I2S transmit FIFO. +//! +//! The parameter \e ulTxLevel sets the level at which transmit DMA requests +//! are generated. This should be non-zero integer multiple of number of +//! serializers enabled as transmitters +//! +//! The parameter \e ulWordsPerTransfer sets the number of words that are +//! transferred from the transmit FIFO to the data line(s). This value must +//! equal the number of serializers used as transmitters. +//! +//! \return None. +// +//***************************************************************************** +void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulWordsPerTransfer) +{ + // + // Set transmit FIFO configuration and + // enable it + // + HWREG(ulBase + MCASP_0_WFIFOCTL) = ((1 <<16) | ((ulTxLevel & 0xFF) << 8) + | (ulWordsPerTransfer & 0x1F)); + +} + +//***************************************************************************** +// +//! Disables transmit FIFO. +//! +//! \param ulBase is the base address of the I2S module. +//! +//! This function disables the I2S transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +void I2STxFIFODisable(unsigned long ulBase) +{ + // + // Disable transmit FIFO. + // + HWREG(ulBase + MCASP_0_WFIFOCTL) = 0; +} + +//***************************************************************************** +// +//! Configure and enable receive FIFO. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulRxLevel is the receive FIFO DMA request level. +//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO. +//! +//! This function configures and enable I2S receive FIFO. +//! +//! The parameter \e ulRxLevel sets the level at which receive DMA requests +//! are generated. This should be non-zero integer multiple of number of +//! serializers enabled as receivers. +//! +//! The parameter \e ulWordsPerTransfer sets the number of words that are +//! transferred to the receive FIFO from the data line(s). This value must +//! equal the number of serializers used as receivers. +//! +//! \return None. +// +//***************************************************************************** +void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel, + unsigned long ulWordsPerTransfer) +{ + // + // Set FIFO configuration + // + HWREG(ulBase + MCASP_0_RFIFOCTL) = ( (1 <<16) | ((ulRxLevel & 0xFF) << 8) + | (ulWordsPerTransfer & 0x1F)); + +} + +//***************************************************************************** +// +//! Disables receive FIFO. +//! +//! \param ulBase is the base address of the I2S module. +//! +//! This function disables the I2S receive FIFO. +//! +//! \return None. +// +//***************************************************************************** +void I2SRxFIFODisable(unsigned long ulBase) +{ + // + // Disable receive FIFO. + // + HWREG(ulBase + MCASP_0_RFIFOCTL) = 0; +} + +//***************************************************************************** +// +//! Get the transmit FIFO status. +//! +//! \param ulBase is the base address of the I2S module. +//! +//! This function gets the number of 32-bit words currently in the transmit +//! FIFO. +//! +//! \return Returns transmit FIFO status. +// +//***************************************************************************** +unsigned long I2STxFIFOStatusGet(unsigned long ulBase) +{ + // + // Return transmit FIFO level + // + return HWREG(ulBase + MCASP_0_WFIFOSTS); +} + +//***************************************************************************** +// +//! Get the receive FIFO status. +//! +//! \param ulBase is the base address of the I2S module. +//! +//! This function gets the number of 32-bit words currently in the receive +//! FIFO. +//! +//! \return Returns receive FIFO status. +// +//***************************************************************************** +unsigned long I2SRxFIFOStatusGet(unsigned long ulBase) +{ + // + // Return receive FIFO level + // + return HWREG(ulBase + MCASP_0_RFIFOSTS); +} + +//***************************************************************************** +// +//! Configure the serializer in specified mode. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulDataLine is the data line (serilizer) to be configured. +//! \param ulSerMode is the required serializer mode. +//! \param ulInActState sets the inactive state of the data line. +//! +//! This function configure and enable the serializer associated with the given +//! data line in specified mode. +//! +//! The paramenter \e ulDataLine selects to data line to be configured and +//! can be one of the following: +//! -\b I2S_DATA_LINE_0 +//! -\b I2S_DATA_LINE_1 +//! +//! The parameter \e ulSerMode can be one of the following: +//! -\b I2S_SER_MODE_TX +//! -\b I2S_SER_MODE_RX +//! -\b I2S_SER_MODE_DISABLE +//! +//! The parameter \e ulInActState can be one of the following +//! -\b I2S_INACT_TRI_STATE +//! -\b I2S_INACT_LOW_LEVEL +//! -\b I2S_INACT_LOW_HIGH +//! +//! \return Returns receive FIFO status. +// +//***************************************************************************** +void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine, + unsigned long ulSerMode, unsigned long ulInActState) +{ + if( ulSerMode == I2S_SER_MODE_TX) + { + // + // Set the data line in output mode + // + HWREG(ulBase + MCASP_O_PDIR) |= ulDataLine; + } + else + { + // + // Set the data line in input mode + // + HWREG(ulBase + MCASP_O_PDIR) &= ~ulDataLine; + } + + // + // Set the serializer configuration. + // + HWREG(ulBase + MCASP_O_XRSRCTL0 + ((ulDataLine-1) << 2)) + = (ulSerMode | ulInActState); +} + +//***************************************************************************** +// +//! Enables individual I2S interrupt sources. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! -\b I2S_INT_XUNDRN +//! -\b I2S_INT_XSYNCERR +//! -\b I2S_INT_XLAST +//! -\b I2S_INT_XDATA +//! -\b I2S_INT_XSTAFRM +//! -\b I2S_INT_XDMA +//! -\b I2S_INT_ROVRN +//! -\b I2S_INT_RSYNCERR +//! -\b I2S_INT_RLAST +//! -\b I2S_INT_RDATA +//! -\b I2S_INT_RSTAFRM +//! -\b I2S_INT_RDMA +//! +//! \return None. +// +//***************************************************************************** +void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + + // + // Enable DMA done interrupts + // + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR ) + |= ((ulIntFlags &0xC0000000) >> 20); + + // + // Enable specific Tx Interrupts + // + HWREG(ulBase + MCASP_O_EVTCTLX) |= (ulIntFlags & 0xFF); + + // + // Enable specific Rx Interrupts + // + HWREG(ulBase + MCASP_O_EVTCTLR) |= ((ulIntFlags >> 16) & 0xFF); +} + +//***************************************************************************** +// +//! Disables individual I2S interrupt sources. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to I2SIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Disable DMA done interrupts + // + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) + |= ((ulIntFlags &0xC0000000) >> 20); + + // + // Disable specific Tx Interrupts + // + HWREG(ulBase + MCASP_O_EVTCTLX) &= ~(ulIntFlags & 0xFF); + + // + // Disable specific Rx Interrupts + // + HWREG(ulBase + MCASP_O_EVTCTLR) &= ~((ulIntFlags >> 16) & 0xFF); +} + + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the I2S module. +//! +//! This function returns the raw interrupt status for I2S enumerated +//! as a bit field of values: +//! -\b I2S_STS_XERR +//! -\b I2S_STS_XDMAERR +//! -\b I2S_STS_XSTAFRM +//! -\b I2S_STS_XDATA +//! -\b I2S_STS_XLAST +//! -\b I2S_STS_XSYNCERR +//! -\b I2S_STS_XUNDRN +//! -\b I2S_STS_XDMA +//! -\b I2S_STS_RERR +//! -\b I2S_STS_RDMAERR +//! -\b I2S_STS_RSTAFRM +//! -\b I2S_STS_RDATA +//! -\b I2S_STS_RLAST +//! -\b I2S_STS_RSYNCERR +//! -\b I2S_STS_ROVERN +//! -\b I2S_STS_RDMA +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described above. +// +//***************************************************************************** +unsigned long I2SIntStatus(unsigned long ulBase) +{ + unsigned long ulStatus; + + // + // Get DMA interrupt status + // + ulStatus = + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW) << 20; + + ulStatus &= 0xC0000000; + + // + // Read Tx Interrupt status + // + ulStatus |= HWREG(ulBase + MCASP_O_TXSTAT); + + // + // Read Rx Interrupt status + // + ulStatus |= HWREG(ulBase + MCASP_O_RXSTAT) << 16; + + // + // Return the status + // + return ulStatus; +} + +//***************************************************************************** +// +//! Clears I2S interrupt sources. +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulStatFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2S interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the value +//! describe in I2SIntStatus(). +//! +//! \return None. +// +//***************************************************************************** +void I2SIntClear(unsigned long ulBase, unsigned long ulStatFlags) +{ + // + // Clear DMA done interrupts + // + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) + |= ((ulStatFlags &0xC0000000) >> 20); + + // + // Clear Tx Interrupt + // + HWREG(ulBase + MCASP_O_TXSTAT) = ulStatFlags & 0x1FF ; + + // + // Clear Rx Interrupt + // + HWREG(ulBase + MCASP_O_RXSTAT) = (ulStatFlags >> 16) & 0x1FF; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a I2S interrupt. +//! +//! \param ulBase is the base address of the I2S module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2S interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! I2S interrupts must be enabled via I2SIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler + // + IntRegister(INT_I2S,pfnHandler); + + // + // Enable the interrupt + // + IntEnable(INT_I2S); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a I2S interrupt. +//! +//! \param ulBase is the base address of the I2S module. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a I2S interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void I2SIntUnregister(unsigned long ulBase) +{ + // + // Disable interrupt + // + IntDisable(INT_I2S); + + // + // Unregister the handler + // + IntUnregister(INT_I2S); + +} + +//***************************************************************************** +// +//! Set the active slots for Trasmitter +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulActSlot is the bit-mask of activ slots +//! +//! This function sets the active slots for the transmitter. By default both +//! the slots are active. The parameter \e ulActSlot is logical OR follwoing +//! values: +//! -\b I2S_ACT_SLOT_EVEN +//! -\b I2S_ACT_SLOT_ODD +//! +//! \return None. +// +//***************************************************************************** +void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot) +{ + HWREG(ulBase + MCASP_O_TXTDM) = ulActSlot; +} + +//***************************************************************************** +// +//! Set the active slots for Receiver +//! +//! \param ulBase is the base address of the I2S module. +//! \param ulActSlot is the bit-mask of activ slots +//! +//! This function sets the active slots for the receiver. By default both +//! the slots are active. The parameter \e ulActSlot is logical OR follwoing +//! values: +//! -\b I2S_ACT_SLOT_EVEN +//! -\b I2S_ACT_SLOT_ODD +//! +//! \return None. +// +//***************************************************************************** +void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot) +{ + HWREG(ulBase + MCASP_O_RXTDM) = ulActSlot; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.h new file mode 100755 index 00000000000..260308fe7e1 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.h @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// i2s.h +// +// Defines and Macros for the I2S. +// +//***************************************************************************** + +#ifndef __I2S_H__ +#define __I2S_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// I2S DMA ports. +// +//***************************************************************************** +#define I2S_TX_DMA_PORT 0x4401E200 +#define I2S_RX_DMA_PORT 0x4401E280 + +//***************************************************************************** +// +// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter. +// +//***************************************************************************** +#define I2S_SLOT_SIZE_8 0x00300032 +#define I2S_SLOT_SIZE_16 0x00700074 +#define I2S_SLOT_SIZE_24 0x00B000B6 + + +#define I2S_PORT_CPU 0x00080008 +#define I2S_PORT_DMA 0x00000000 + +#define I2S_MODE_MASTER 0x00000000 +#define I2S_MODE_SLAVE 0x00008000 + +//***************************************************************************** +// +// Values that can be passed as ulDataLine parameter. +// +//***************************************************************************** +#define I2S_DATA_LINE_0 0x00000001 +#define I2S_DATA_LINE_1 0x00000002 + +//***************************************************************************** +// +// Values that can be passed to I2SSerializerConfig() as the ulSerMode +// parameter. +// +//***************************************************************************** +#define I2S_SER_MODE_TX 0x00000001 +#define I2S_SER_MODE_RX 0x00000002 +#define I2S_SER_MODE_DISABLE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to I2SSerializerConfig() as the ulInActState +// parameter. +// +//***************************************************************************** +#define I2S_INACT_TRI_STATE 0x00000000 +#define I2S_INACT_LOW_LEVEL 0x00000008 +#define I2S_INACT_HIGH_LEVEL 0x0000000C + +//***************************************************************************** +// +// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the +// ulIntFlags parameter. +// +//***************************************************************************** +#define I2S_INT_XUNDRN 0x00000001 +#define I2S_INT_XSYNCERR 0x00000002 +#define I2S_INT_XLAST 0x00000010 +#define I2S_INT_XDATA 0x00000020 +#define I2S_INT_XSTAFRM 0x00000080 +#define I2S_INT_XDMA 0x80000000 +#define I2S_INT_ROVRN 0x00010000 +#define I2S_INT_RSYNCERR 0x00020000 +#define I2S_INT_RLAST 0x00100000 +#define I2S_INT_RDATA 0x00200000 +#define I2S_INT_RSTAFRM 0x00800000 +#define I2S_INT_RDMA 0x40000000 + + +//***************************************************************************** +// +// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet +// +//***************************************************************************** +#define I2S_ACT_SLOT_EVEN 0x00000001 +#define I2S_ACT_SLOT_ODD 0x00000002 + +//***************************************************************************** +// +// Values that can be passed to I2SIntClear() as the +// ulIntFlags parameter and returned from I2SIntStatus(). +// +//***************************************************************************** +#define I2S_STS_XERR 0x00000100 +#define I2S_STS_XDMAERR 0x00000080 +#define I2S_STS_XSTAFRM 0x00000040 +#define I2S_STS_XDATA 0x00000020 +#define I2S_STS_XLAST 0x00000010 +#define I2S_STS_XSYNCERR 0x00000002 +#define I2S_STS_XUNDRN 0x00000001 +#define I2S_STS_XDMA 0x80000000 +#define I2S_STS_RERR 0x01000000 +#define I2S_STS_RDMAERR 0x00800000 +#define I2S_STS_RSTAFRM 0x00400000 +#define I2S_STS_RDATA 0x00200000 +#define I2S_STS_RLAST 0x00100000 +#define I2S_STS_RSYNCERR 0x00020000 +#define I2S_STS_ROVERN 0x00010000 +#define I2S_STS_RDMA 0x40000000 + +//***************************************************************************** +// +// Values that can be passed to I2SEnable() as the ulMode parameter. +// +//***************************************************************************** +#define I2S_MODE_TX_ONLY 0x00000001 +#define I2S_MODE_TX_RX_SYNC 0x00000003 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void I2SEnable(unsigned long ulBase, unsigned long ulMode); +extern void I2SDisable(unsigned long ulBase); + +extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine, + unsigned long ulData); +extern long I2SDataPutNonBlocking(unsigned long ulBase, + unsigned long ulDataLine, unsigned long ulData); + +extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine, + unsigned long *pulData); +extern long I2SDataGetNonBlocking(unsigned long ulBase, + unsigned long ulDataLine, unsigned long *pulData); + +extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk, + unsigned long ulBitClk, unsigned long ulConfig); + +extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulWordsPerTransfer); +extern void I2STxFIFODisable(unsigned long ulBase); +extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel, + unsigned long ulWordsPerTransfer); +extern void I2SRxFIFODisable(unsigned long ulBase); +extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase); +extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase); + +extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine, + unsigned long ulSerMode, unsigned long ulInActState); + +extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long I2SIntStatus(unsigned long ulBase); +extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void I2SIntUnregister(unsigned long ulBase); +extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot); +extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif //__I2S_H__ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.c new file mode 100755 index 00000000000..a4a447129b0 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.c @@ -0,0 +1,770 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// interrupt.c +// +// Driver for the NVIC Interrupt Controller. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +static const unsigned long g_pulPriority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +static const unsigned long g_pulRegs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, + NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, + NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, + NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, + NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37, + NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43, + NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48 + +}; + + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt enable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulEnRegs[] = +{ + NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt disable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulDisRegs[] = +{ + NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt pend for that interrupt. +// +//***************************************************************************** +static const unsigned long g_pulPendRegs[] = +{ + NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5 +}; + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt unpend for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulUnpendRegs[] = +{ + NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4, + NVIC_UNPEND5 +}; + + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! tBoolean, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +tBoolean +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! tBoolean, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +tBoolean +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + return(CPUcpsid()); +} +//***************************************************************************** +// +//! Sets the NVIC VTable base. +//! +//! \param ulVtableBase specifies the new base address of VTable +//! +//! This function is used to specify a new base address for the VTable. +//! This function must be called before using IntRegister() for registering +//! any interrupt handler. +//! +//! +//! \return None. +// +//***************************************************************************** +void +IntVTableBaseSet(unsigned long ulVtableBase) +{ + HWREG(NVIC_VTABLE) = ulVtableBase; +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can preempt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! +//! \return None. +// +//***************************************************************************** +void +IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) +{ + unsigned long *ulNvicTbl; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE); + ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +IntUnregister(unsigned long ulInterrupt) +{ + unsigned long *ulNvicTbl; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE); + ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler; +} + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ulBits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the CC3200 , three bits are available for hardware interrupt +//! prioritization and therefore priority grouping values of three through +//! seven have the same effect. +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityGroupingSet(unsigned long ulBits) +{ + // + // Check the arguments. + // + ASSERT(ulBits < NUM_PRIORITY); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; +} + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +unsigned long +IntPriorityGroupingGet(void) +{ + unsigned long ulLoop, ulValue; + + // + // Read the priority grouping. + // + ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++) + { + // + // Stop looping if this value matches. + // + if(ulValue == g_pulPriority[ulLoop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ulLoop); +} + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param ucPriority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. When multiple +//! interrupts are asserted simultaneously, the ones with the highest priority +//! are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities; priority 0 is the highest +//! interrupt priority. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3), so any prioritization must be performed in +//! those bits. The remaining bits can be used to sub-prioritize the interrupt +//! sources, and may be used by the hardware priority mechanism on a future +//! part. This arrangement allows priorities to migrate to different NVIC +//! implementations without changing the gross prioritization of the +//! interrupts. +//! +//! The parameter \e ucPriority can be any one of the following +//! -\b INT_PRIORITY_LVL_0 +//! -\b INT_PRIORITY_LVL_1 +//! -\b INT_PRIORITY_LVL_2 +//! -\b INT_PRIORITY_LVL_3 +//! -\b INT_PRIORITY_LVL_4 +//! -\b INT_PRIORITY_LVL_5 +//! -\b INT_PRIORITY_LVL_6 +//! -\b INT_PRIORITY_LVL_7 +//! +//! \return None. +// +//***************************************************************************** +void +IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); + ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); + ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); + HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. See IntPrioritySet() for +//! a definition of the priority value. +//! +//! \return Returns the interrupt priority, or -1 if an invalid interrupt was +//! specified. +// +//***************************************************************************** +long +IntPriorityGet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & + 0xFF); +} + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntEnable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt >= 16) + { + // + // Enable the general interrupt. + // + HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + __asm(" dsb "); + __asm(" isb "); + } +} + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntDisable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt >= 16) + { + // + // Disable the general interrupt. + // + HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + __asm(" dsb "); + __asm(" isb "); + } + +} + +//***************************************************************************** +// +//! Pends an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be pended. +//! +//! The specified interrupt is pended in the interrupt controller. This will +//! cause the interrupt controller to execute the corresponding interrupt +//! handler at the next available time, based on the current interrupt state +//! priorities. For example, if called by a higher priority interrupt handler, +//! the specified interrupt handler will not be called until after the current +//! interrupt handler has completed execution. The interrupt must have been +//! enabled for it to be called. +//! +//! \return None. +// +//***************************************************************************** +void +IntPendSet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to pend. + // + if(ulInterrupt == FAULT_NMI) + { + // + // Pend the NMI interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_PENDSV) + { + // + // Pend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Pend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + __asm(" dsb "); + __asm(" isb "); + } + else if(ulInterrupt >= 16) + { + // + // Pend the general interrupt. + // + HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + __asm(" dsb "); + __asm(" isb "); + } + +} + +//***************************************************************************** +// +//! Unpends an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be unpended. +//! +//! The specified interrupt is unpended in the interrupt controller. This will +//! cause any previously generated interrupts that have not been handled yet +//! (due to higher priority interrupts or the interrupt no having been enabled +//! yet) to be discarded. +//! +//! \return None. +// +//***************************************************************************** +void +IntPendClear(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to unpend. + // + if(ulInterrupt == FAULT_PENDSV) + { + // + // Unpend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Unpend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if(ulInterrupt >= 16) + { + // + // Unpend the general interrupt. + // + HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) = + 1 << ((ulInterrupt - 16) & 31); + } +} + +//***************************************************************************** +// +//! Sets the priority masking level +//! +//! \param ulPriorityMask is the priority level that will be masked. +//! +//! This function sets the interrupt priority masking level so that all +//! interrupts at the specified or lesser priority level is masked. This +//! can be used to globally disable a set of interrupts with priority below +//! a predetermined threshold. A value of 0 disables priority +//! masking. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3), so any +//! prioritization must be performed in those bits. +//! +//! \return None. +// +//***************************************************************************** +void +IntPriorityMaskSet(unsigned long ulPriorityMask) +{ + CPUbasepriSet(ulPriorityMask); +} + +//***************************************************************************** +// +//! Gets the priority masking level +//! +//! This function gets the current setting of the interrupt priority masking +//! level. The value returned is the priority level such that all interrupts +//! of that and lesser priority are masked. A value of 0 means that priority +//! masking is disabled. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3), so any +//! prioritization must be performed in those bits. +//! +//! \return Returns the value of the interrupt priority level mask. +// +//***************************************************************************** +unsigned long +IntPriorityMaskGet(void) +{ + return(CPUbasepriGet()); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.h new file mode 100755 index 00000000000..876f7a4e0e1 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// interrupt.h +// +// Prototypes for the NVIC Interrupt Controller Driver. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + unsigned long ulPtr; +} +uVectorEntry; + + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. +// +//***************************************************************************** +#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) + +//***************************************************************************** +// Interrupt priority levels +//***************************************************************************** +#define INT_PRIORITY_LVL_0 0x00 +#define INT_PRIORITY_LVL_1 0x20 +#define INT_PRIORITY_LVL_2 0x40 +#define INT_PRIORITY_LVL_3 0x60 +#define INT_PRIORITY_LVL_4 0x80 +#define INT_PRIORITY_LVL_5 0xA0 +#define INT_PRIORITY_LVL_6 0xC0 +#define INT_PRIORITY_LVL_7 0xE0 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean IntMasterEnable(void); +extern tBoolean IntMasterDisable(void); +extern void IntVTableBaseSet(unsigned long ulVtableBase); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); +extern void IntPendSet(unsigned long ulInterrupt); +extern void IntPendClear(unsigned long ulInterrupt); +extern void IntPriorityMaskSet(unsigned long ulPriorityMask); +extern unsigned long IntPriorityMaskGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.c new file mode 100755 index 00000000000..79b77ba9b77 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.c @@ -0,0 +1,884 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// pin.c +// +// Mapping of peripherals to pins. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pin_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_ocp_shared.h" +#include "pin.h" + +//***************************************************************************** +// Macros +//***************************************************************************** +#define PAD_MODE_MASK 0x0000000F +#define PAD_STRENGTH_MASK 0x000000E0 +#define PAD_TYPE_MASK 0x00000310 +#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \ + OCP_SHARED_O_GPIO_PAD_CONFIG_0)) + +//***************************************************************************** +// PIN to PAD matrix +//***************************************************************************** +static const unsigned long g_ulPinToPadMap[64] = +{ + 10,11,12,13,14,15,16,17,255,255,18, + 19,20,21,22,23,24,40,28,29,25,255, + 255,255,255,255,255,255,255,255,255,255,255, + 255,255,255,255,255,255,255,255,255,255,255, + 31,255,255,255,255,0,255,32,30,255,1, + 255,2,3,4,5,6,7,8,9 +}; + + +//***************************************************************************** +// +//! Configures pin mux for the specified pin. +//! +//! \param ulPin is a valid pin. +//! \param ulPinMode is one of the valid mode +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular SOC pin. Only one peripheral function at a +//! time can be associated with a pin, and each peripheral function should +//! only be associated with a single pin at a time. +//! +//! \return none +// +//***************************************************************************** +void PinModeSet(unsigned long ulPin,unsigned long ulPinMode) +{ + + unsigned long ulPad; + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Set the mode. + // + HWREG(ulPad) = (((HWREG(ulPad) & ~PAD_MODE_MASK) | ulPinMode) & ~(3<<10)); + +} + +//***************************************************************************** +// +//! Gets current pin mux configuration of specified pin. +//! +//! \param ulPin is a valid pin. +//! +//! This function get the current configuration of the pin mux. +//! +//! \return Returns current pin mode if \e ulPin is valid, 0xFF otherwise. +// +//***************************************************************************** +unsigned long PinModeGet(unsigned long ulPin) +{ + + unsigned long ulPad; + + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ; + + // + // return the mode. + // + return (HWREG(ulPad) & PAD_MODE_MASK); + +} + +//***************************************************************************** +// +//! Sets the direction of the specified pin(s). +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinIO is the pin direction and/or mode. +//! +//! This function configures the specified pin(s) as either input only or +//! output only or it configures the pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b PIN_DIR_MODE_IN +//! - \b PIN_DIR_MODE_OUT +//! - \b PIN_DIR_MODE_HW +//! +//! where \b PIN_DIR_MODE_IN specifies that the pin is programmed as a +//! input only, \b PIN_DIR_MODE_OUT specifies that the pin is +//! programmed output only, and \b PIN_DIR_MODE_HW specifies that the pin is +//! placed under hardware control. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO) +{ + unsigned long ulPad; + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Set the direction + // + HWREG(ulPad) = ((HWREG(ulPad) & ~0xC00) | ulPinIO); +} + +//***************************************************************************** +// +//! Gets the direction of a pin. +//! +//! \param ulPin is one of the valid pin. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input only +//! or output only, or it can be under hardware control. The type of control +//! and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +unsigned long PinDirModeGet(unsigned long ulPin) +{ + unsigned long ulPad; + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Return the direction + // + return ((HWREG(ulPad) & 0xC00)); +} + +//***************************************************************************** +// +//! Gets Pin output drive strength and Type +//! +//! \param ulPin is one of the valid pin +//! \param pulPinStrength is pointer to storage for output drive strength +//! \param pulPinType is pinter to storage for pin type +//! +//! This function gets the pin type and output drive strength for the pin +//! specified by \e ulPin parameter. Parameters \e pulPinStrength and +//! \e pulPinType corresponds to the values used in PinConfigSet(). +//! +//! +//! \return None. +// +//***************************************************************************** +void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength, + unsigned long *pulPinType) +{ + + unsigned long ulPad; + + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + + // + // Get the type + // + *pulPinType = (HWREG(ulPad) & PAD_TYPE_MASK); + + // + // Get the output drive strength + // + *pulPinStrength = (HWREG(ulPad) & PAD_STRENGTH_MASK); + +} + +//***************************************************************************** +// +//! Configure Pin output drive strength and Type +//! +//! \param ulPin is one of the valid pin +//! \param ulPinStrength is logical OR of valid output drive strengths. +//! \param ulPinType is one of the valid pin type. +//! +//! This function sets the pin type and strength for the pin specified by +//! \e ulPin parameter. +//! +//! The parameter \e ulPinStrength should be one of the following +//! - \b PIN_STRENGTH_2MA +//! - \b PIN_STRENGTH_4MA +//! - \b PIN_STRENGTH_6MA +//! +//! +//! The parameter \e ulPinType should be one of the following +//! For standard type +//! +//! - \b PIN_TYPE_STD +//! - \b PIN_TYPE_STD_PU +//! - \b PIN_TYPE_STD_PD +//! +//! And for Open drain type +//! +//! - \b PIN_TYPE_OD +//! - \b PIN_TYPE_OD_PU +//! - \b PIN_TYPE_OD_PD +//! +//! \return None. +// +//***************************************************************************** +void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength, + unsigned long ulPinType) +{ + + unsigned long ulPad; + + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Write the register + // + if(ulPinType == PIN_TYPE_ANALOG) + { + // + // Isolate the input + // + HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8)); + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Isolate the output + // + HWREG(ulPad) = 0xC00; + + } + else + { + // + // Enable the input + // + HWREG(0x4402E144) &= ~((0x80 << ulPad) & (0x1E << 8)); + + // + // Calculate the register address + // + ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); + + // + // Write the configuration + // + HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) | + (ulPinStrength | ulPinType )); + } + + +} + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by UART peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The UART pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! +//! \note This function cannot be used to turn any pin into a UART pin; it +//! only sets the pin mode and configures it for proper UART operation. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode) +{ + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD); +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by I2C peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The I2C pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! the pin. +//! +//! +//! \note This function cannot be used to turn any pin into a I2C pin; it +//! only sets the pin mode and configures it for proper I2C operation. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode) +{ + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for open-drain operation with a weak pull-up. + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_OD_PU); +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by SPI peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The SPI pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a SPI pin; it +//! only sets the pin mode and configures it for proper SPI operation. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode) +{ + + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); + +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by I2S peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The I2S pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a I2S pin; it +//! only sets the pin mode and configures it for proper I2S operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode) +{ + + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); + +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by Timer peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The timer PWM pins must be properly configured for the Timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin; other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! +//! \note This function cannot be used to turn any pin into a timer PWM pin; it +//! only sets the pin mode and configures it for proper timer PWM operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode) +{ + + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by Camera peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The Camera pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a Camera pin; it +//! only sets the pin mode and configures it for proper Camera operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode) +{ + + // + // Set the pin to specified mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Set the pin for standard operation + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); + +} + + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by GPIO peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! \param bOpenDrain is one to decide either OpenDrain or STD +//! +//! The GPIO pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \return None. +// +//***************************************************************************** +void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,tBoolean bOpenDrain) +{ + + // + // Set the pin for standard push-pull operation. + // + if(bOpenDrain) + { + PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_OD); + } + else + { + PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_STD); + } + + // + // Set the pin to specified mode + // + PinModeSet(ulPin, ulPinMode); + +} + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by ADC +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The ADC pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a ADC pin; it +//! only sets the pin mode and configures it for proper ADC operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode) +{ + // + // Configure the Pin + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_ANALOG); +} + +//***************************************************************************** +// +//! Sets the pin mode and configures the pin for use by SD Host peripheral +//! +//! \param ulPin is one of the valid pin. +//! \param ulPinMode is one of the valid pin mode. +//! +//! The MMC pins must be properly configured for the peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin. +//! +//! +//! \note This function cannot be used to turn any pin into a SD Host pin; it +//! only sets the pin mode and configures it for proper SD Host operation. +//! +//! \return None. +// +//***************************************************************************** +void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode) +{ + // + // Set pin mode + // + PinModeSet(ulPin,ulPinMode); + + // + // Configure the Pin + // + PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD); + +} + + +//***************************************************************************** +// +//! Sets the hysteresis for all the pins +//! +//! \param ulHysteresis is one of the valid predefined hysterisys values +//! +//! This function sets the hysteresis vlaue for all the pins. The parameter +//! \e ulHysteresis can be on one the following: +//! -\b PIN_HYSTERESIS_OFF - To turn Off hysteresis, default on POR +//! -\b PIN_HYSTERESIS_10 - To turn On hysteresis, 10% +//! -\b PIN_HYSTERESIS_20 - To turn On hysteresis, 20% +//! -\b PIN_HYSTERESIS_30 - To turn On hysteresis, 30% +//! -\b PIN_HYSTERESIS_40 - To turn On hysteresis, 40% +//! +//! \return None. +// +//***************************************************************************** +void PinHysteresisSet(unsigned long ulHysteresis) +{ + unsigned long ulRegValue; + + // + // Read the current value + // + ulRegValue = (HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) + & ~(0x0000001C)); + + // + // Set the new Hysteresis + // + if( ulHysteresis != PIN_HYSTERESIS_OFF ) + { + ulRegValue |= (ulHysteresis & 0x0000001C); + } + + // + // Write the new value + // + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) = ulRegValue; +} + +//***************************************************************************** +// +//! Sets the level of the pin when locked +//! +//! \param ulPin is one of the valid pin. +//! \param ucLevel is the level the pin drives when locked +//! +//! This function sets the pin level when the pin is locked using +//! \sa PinLock() API. +//! +//! By default all pins are set to drive 0. +//! +//! \note Use case is to park the pins when entering LPDS +//! +//! \return None. +// +//***************************************************************************** +void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel) +{ + unsigned long ulPad; + + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Get the corresponding Pad + // + ulPad = g_ulPinToPadMap[ulPin & 0x3F]; + + // + // Get the required bit + // + ulPad = 1 << ulPad; + + if(ucLevel) + { + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) |= ulPad; + } + else + { + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) &= ~ulPad; + } + } +} + +//***************************************************************************** +// +//! Locks all the pins to configured level(s). +//! +//! \param ulOutEnable the bit-packed representation of pins to be set as output +//! +//! This function locks all the pins to the pre-configure level. By default +//! the pins are set to drive 0. Default level can be changed using +//! \sa PinLockLevelSet() API. +//! +//! The \e ulOutEnable paramter is bit-packed representation of pins that +//! are required to be enabled as output. If a bit is set 1, the corresponding +//! pin (as shown below) are set and locked as output. +//! +//! |------|-----------------------------------------------| +//! | Bit |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |------|-----------------------------------------------| +//! | Pin |xx|xx|20|19|30|29|21|17|16|15|14|13|12|11|08|07| +//! |------|-----------------------------------------------| +//! +//! |------|-----------------------------------------------| +//! | Bit |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |------|-----------------------------------------------| +//! | Pin |06|05|04|03|02|01|64|63|62|61|60|59|58|57|55|50| +//! |------|-----------------------------------------------| +//! +//! +//! \note Use case is to park the pins when entering LPDS +//! +//! \return None. +// +//***************************************************************************** +void PinLock(unsigned long ulOutEnable) +{ + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Enable/disable the pin(s) output + // + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_7 ) = ~ulOutEnable; + + // + // Lock the pins to selected levels + // + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) |= (3 << 24); + } +} + +//***************************************************************************** +// +//! Unlocks all the pins. +//! +//! This function unlocks all the pins and can be used for peripheral function. +//! +//! By default all the pins are in unlocked state. +//! +//! \note Use case is to un-park the pins when exiting LPDS +//! +//! \return None. +// +//***************************************************************************** +void PinUnlock() +{ + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Unlock the pins + // + HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) &= ~(3 << 24); + } +} + +//***************************************************************************** +// +// Gets pad number from pin number +// +// \param ulPin is a valid pin number +// +// This function return the pad corresponding to the specified pin +// +// \return Pad number on success, 0xFF otherwise +// +//***************************************************************************** +unsigned long PinToPadGet(unsigned long ulPin) +{ + // + // Return the corresponding Pad + // + return g_ulPinToPadMap[ulPin & 0x3F]; +} + + +//***************************************************************************** +// +// Gets pin number from pad number +// +// \param ulPad is a valid pad number +// +// This function return the pin corresponding to the specified pad +// +// \return Pin number on success, 0xFF otherwise +// +//***************************************************************************** +unsigned long PinFromPadGet(unsigned long ulPad) +{ + unsigned long ulPin; + + // + // search and return the pin number + // + for(ulPin=0; ulPin < sizeof(g_ulPinToPadMap)/4; ulPin++) + { + if(g_ulPinToPadMap[ulPin] == ulPad) + { + return ulPin; + } + } + + return 0xFF; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.h new file mode 100755 index 00000000000..ca4684018e0 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.h @@ -0,0 +1,192 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// pin.h +// +// Defines and Macros for the pin mux module +// +//***************************************************************************** + +#ifndef __PIN_H__ +#define __PIN_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// Macros Defining Pins +//***************************************************************************** + +#define PIN_01 0x00000000 +#define PIN_02 0x00000001 +#define PIN_03 0x00000002 +#define PIN_04 0x00000003 +#define PIN_05 0x00000004 +#define PIN_06 0x00000005 +#define PIN_07 0x00000006 +#define PIN_08 0x00000007 +#define PIN_11 0x0000000A +#define PIN_12 0x0000000B +#define PIN_13 0x0000000C +#define PIN_14 0x0000000D +#define PIN_15 0x0000000E +#define PIN_16 0x0000000F +#define PIN_17 0x00000010 +#define PIN_18 0x00000011 +#define PIN_19 0x00000012 +#define PIN_20 0x00000013 +#define PIN_21 0x00000014 +#define PIN_29 0x0000001C +#define PIN_30 0x0000001D +#define PIN_45 0x0000002C +#define PIN_46 0x0000002D +#define PIN_47 0x0000002E +#define PIN_48 0x0000002F +#define PIN_49 0x00000030 +#define PIN_50 0x00000031 +#define PIN_52 0x00000033 +#define PIN_53 0x00000034 +#define PIN_55 0x00000036 +#define PIN_56 0x00000037 +#define PIN_57 0x00000038 +#define PIN_58 0x00000039 +#define PIN_59 0x0000003A +#define PIN_60 0x0000003B +#define PIN_61 0x0000003C +#define PIN_62 0x0000003D +#define PIN_63 0x0000003E +#define PIN_64 0x0000003F + + +//***************************************************************************** +// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet() +//***************************************************************************** + +#define PIN_MODE_0 0x00000000 +#define PIN_MODE_1 0x00000001 +#define PIN_MODE_2 0x00000002 +#define PIN_MODE_3 0x00000003 +#define PIN_MODE_4 0x00000004 +#define PIN_MODE_5 0x00000005 +#define PIN_MODE_6 0x00000006 +#define PIN_MODE_7 0x00000007 +#define PIN_MODE_8 0x00000008 +#define PIN_MODE_9 0x00000009 +#define PIN_MODE_10 0x0000000A +#define PIN_MODE_11 0x0000000B +#define PIN_MODE_12 0x0000000C +#define PIN_MODE_13 0x0000000D +#define PIN_MODE_14 0x0000000E +#define PIN_MODE_15 0x0000000F +// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation +// PIN_MODE_255 should never be used in any user code. +#define PIN_MODE_255 0x000000FF + +//***************************************************************************** +// Macros that can be used with PinDirModeSet() and returned from +// PinDirModeGet(). +//***************************************************************************** +#define PIN_DIR_MODE_IN 0x00000C00 // Pin is input +#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output +#define PIN_DIR_MODE_HW 0x00000000 // Pin is peripheral function + +//***************************************************************************** +// Macros that can be used with PinConfigSet() +//***************************************************************************** +#define PIN_STRENGTH_2MA 0x00000020 +#define PIN_STRENGTH_4MA 0x00000040 +#define PIN_STRENGTH_6MA 0x00000060 + +#define PIN_TYPE_STD 0x00000000 +#define PIN_TYPE_STD_PU 0x00000100 +#define PIN_TYPE_STD_PD 0x00000200 + +#define PIN_TYPE_OD 0x00000010 +#define PIN_TYPE_OD_PU 0x00000110 +#define PIN_TYPE_OD_PD 0x00000210 +#define PIN_TYPE_ANALOG 0x10000000 + +//***************************************************************************** +// Macros that can be used with PinHysteresisSet() +//***************************************************************************** +#define PIN_HYSTERESIS_OFF 0x00000000 +#define PIN_HYSTERESIS_10 0x00000004 +#define PIN_HYSTERESIS_20 0x0000000C +#define PIN_HYSTERESIS_30 0x00000014 +#define PIN_HYSTERESIS_40 0x0000001C + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode); +extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO); +extern unsigned long PinDirModeGet(unsigned long ulPin); +extern unsigned long PinModeGet(unsigned long ulPin); +extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength, + unsigned long *pulPinType); +extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength, + unsigned long ulPinType); +extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode, + tBoolean bOpenDrain); +extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode); +extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode); +extern void PinHysteresisSet(unsigned long ulHysteresis); +extern void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel); +extern void PinLock(unsigned long ulOutEnable); +extern void PinUnlock(void); +extern unsigned long PinToPadGet(unsigned long ulPin); +extern unsigned long PinFromPadGet(unsigned long ulPad); + +#ifdef __cplusplus +} +#endif + +#endif //__PIN_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.c new file mode 100755 index 00000000000..6e408e8b80d --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.c @@ -0,0 +1,2752 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +//! \addtogroup PRCM_Power_Reset_Clock_Module_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_apps_rcm.h" +#include "inc/hw_gprcm.h" +#include "inc/hw_hib1p2.h" +#include "inc/hw_hib3p3.h" +#include "inc/hw_ocp_shared.h" +#include "inc/hw_common_reg.h" +#include "prcm.h" +#include "interrupt.h" +#include "cpu.h" +#include "flash.h" +#include "utils.h" +#include "pin.h" + + +//***************************************************************************** +// Macro definition +//***************************************************************************** +#define PRCM_SOFT_RESET 0x00000001 +#define PRCM_ENABLE_STATUS 0x00000002 +#define SYS_CLK 80000000 +#define XTAL_CLK 40000000 + + +//***************************************************************************** +// CC3200 does not have a true RTC capability. However, API(s) in this file +// provide an effective mechanism to support RTC feature in the device. +// +// The implementation to support RTC has been kept very simple. A set of +// HIB Memory Registers in conjunction with Slow Clock Counter are used +// to render RTC information to users. Core principle of design involves +// two steps (a) establish an association between user provided wall-clock +// and slow clock counter. (b) store reference value of this associattion +// in HIB Registers. This reference value and SCC value are then combined +// to create real-world calendar time. +// +// Across HIB cycles, value stored in HIB Registers is retained and slow +// clock counter continues to tick, thereby, this arragement is relevant +// and valid as long as device has a (tickle) battery power. +// +// Further, provision also has been made to set an alarm. When it RTC value +// matches that of set for alarm, an interrupt is generated. +// +// HIB MEM REG0 and REG1 are reserved for TI. +// +// If RTC feature is not used, then HIB REG2 & REG3 are available to user. +// +// Lower half of REG0 is used for TI HW ECO. +//***************************************************************************** +#define RTC_U64MSEC_MK(u32Secs, u16Msec) (((unsigned long long)u32Secs << 10)|\ + (u16Msec & 0x3FF)) + +#define RTC_SECS_IN_U64MSEC(u64Msec) ((unsigned long)(u64Msec >> 10)) +#define RTC_MSEC_IN_U64MSEC(u64Msec) ((unsigned short)(u64Msec & 0x3FF)) + +#define RTC_SECS_U32_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG3) +#define RTC_MSEC_U16_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2+2) + +#define RTC_U32SECS_REG (HWREG(RTC_SECS_U32_REG_ADDR)) +#define RTC_U16MSEC_REG (*(unsigned short*)RTC_MSEC_U16_REG_ADDR) + +//***************************************************************************** +// Register Access and Updates +// +// Tick of SCC has a resolution of 32768Hz, meaning 1 sec is equal to 32768 +// clock ticks. Ideal way of getting time in millisecond will involve floating +// point arithmetic (division by 32.768). To avoid this, we simply divide it by +// 32, which will give a range from 0 -1023(instead of 0-999). To use this +// output correctly we have to take care of this inaccuracy externally. +// following wrapper can be used to convert the value from cycles to +// millisecond: +// +// CYCLES_U16MS(cycles) ((cycles *1000)/ 1024), +// +// Similarly, before setting the value, it must be first converted (from ms to +// cycles). +// +// U16MS_CYCLES(msec) ((msec *1024)/1000) +// +// Note: There is a precision loss of 1 ms with the above scheme. +// +//***************************************************************************** +#define SCC_U64MSEC_GET() (PRCMSlowClkCtrGet() >> 5) +#define SCC_U64MSEC_MATCH_SET(u64Msec) (PRCMSlowClkCtrMatchSet(u64Msec << 5)) +#define SCC_U64MSEC_MATCH_GET() (PRCMSlowClkCtrMatchGet() >> 5) + +//***************************************************************************** +// +// Bit: 31 is used to indicate use of RTC. If set as '1', RTC feature is used. +// Bits: 30 to 26 are reserved, available to software for use +// Bits: 25 to 16 are used to save millisecond part of RTC reference. +// Bits: 15 to 0 are being used for HW Changes / ECO +// +//***************************************************************************** + +//***************************************************************************** +// Set RTC USE Bit +//***************************************************************************** +static void RTCUseSet(void) +{ + unsigned short usRegValue; + + usRegValue = RTC_U16MSEC_REG | (1 << 15); + + UtilsDelay((80*200)/3); + + RTC_U16MSEC_REG = usRegValue; +} + +//***************************************************************************** +// Checks if RTC-USE bit is set +//***************************************************************************** +static tBoolean IsRTCUsed(void) +{ + unsigned short usRegValue; + + usRegValue = RTC_U16MSEC_REG; + + UtilsDelay((80*200)/3); + + return ((usRegValue & (1 << 15))? true : false); +} + +//***************************************************************************** +// Read 16-bit mSecs +//***************************************************************************** +static unsigned short RTCU16MSecRegRead(void) +{ + unsigned short usRegValue; + + usRegValue = RTC_U16MSEC_REG; + + UtilsDelay((80*200)/3); + + return (usRegValue & 0x3FF); +} + +//***************************************************************************** +// Write 16-bit mSecs +//***************************************************************************** +static void RTCU16MSecRegWrite(unsigned short u16Msec) +{ + unsigned short usRegValue; + + usRegValue = RTC_U16MSEC_REG; + + UtilsDelay((80*200)/3); + + RTC_U16MSEC_REG = ((usRegValue & ~0x3FF) |u16Msec); +} + +//***************************************************************************** +// Read 32-bit Secs +//***************************************************************************** +static unsigned long RTCU32SecRegRead(void) +{ + return (PRCMHIBRegRead(RTC_SECS_U32_REG_ADDR)); +} + +//***************************************************************************** +// Write 32-bit Secs +//***************************************************************************** +static void RTCU32SecRegWrite(unsigned long u32Msec) +{ + PRCMHIBRegWrite(RTC_SECS_U32_REG_ADDR, u32Msec); +} + +//***************************************************************************** +// Macros +//***************************************************************************** +#define IS_RTC_USED() IsRTCUsed() +#define RTC_USE_SET() RTCUseSet() + +#define RTC_U16MSEC_REG_RD() RTCU16MSecRegRead() +#define RTC_U16MSEC_REG_WR(u16Msec) RTCU16MSecRegWrite(u16Msec) + +#define RTC_U32SECS_REG_RD() RTCU32SecRegRead() +#define RTC_U32SECS_REG_WR(u32Secs) RTCU32SecRegWrite(u32Secs) + +#define SELECT_SCC_U42BITS(u64Msec) (u64Msec & 0x3ffffffffff) + +//***************************************************************************** +// Global Peripheral clock and rest Registers +//***************************************************************************** +static const PRCM_PeriphRegs_t PRCM_PeriphRegsList[] = +{ + + {APPS_RCM_O_CAMERA_CLK_GATING, APPS_RCM_O_CAMERA_SOFT_RESET }, + {APPS_RCM_O_MCASP_CLK_GATING, APPS_RCM_O_MCASP_SOFT_RESET }, + {APPS_RCM_O_MMCHS_CLK_GATING, APPS_RCM_O_MMCHS_SOFT_RESET }, + {APPS_RCM_O_MCSPI_A1_CLK_GATING, APPS_RCM_O_MCSPI_A1_SOFT_RESET }, + {APPS_RCM_O_MCSPI_A2_CLK_GATING, APPS_RCM_O_MCSPI_A2_SOFT_RESET }, + {APPS_RCM_O_UDMA_A_CLK_GATING, APPS_RCM_O_UDMA_A_SOFT_RESET }, + {APPS_RCM_O_GPIO_A_CLK_GATING, APPS_RCM_O_GPIO_A_SOFT_RESET }, + {APPS_RCM_O_GPIO_B_CLK_GATING, APPS_RCM_O_GPIO_B_SOFT_RESET }, + {APPS_RCM_O_GPIO_C_CLK_GATING, APPS_RCM_O_GPIO_C_SOFT_RESET }, + {APPS_RCM_O_GPIO_D_CLK_GATING, APPS_RCM_O_GPIO_D_SOFT_RESET }, + {APPS_RCM_O_GPIO_E_CLK_GATING, APPS_RCM_O_GPIO_E_SOFT_RESET }, + {APPS_RCM_O_WDOG_A_CLK_GATING, APPS_RCM_O_WDOG_A_SOFT_RESET }, + {APPS_RCM_O_UART_A0_CLK_GATING, APPS_RCM_O_UART_A0_SOFT_RESET }, + {APPS_RCM_O_UART_A1_CLK_GATING, APPS_RCM_O_UART_A1_SOFT_RESET }, + {APPS_RCM_O_GPT_A0_CLK_GATING , APPS_RCM_O_GPT_A0_SOFT_RESET }, + {APPS_RCM_O_GPT_A1_CLK_GATING, APPS_RCM_O_GPT_A1_SOFT_RESET }, + {APPS_RCM_O_GPT_A2_CLK_GATING, APPS_RCM_O_GPT_A2_SOFT_RESET }, + {APPS_RCM_O_GPT_A3_CLK_GATING, APPS_RCM_O_GPT_A3_SOFT_RESET }, + {APPS_RCM_O_CRYPTO_CLK_GATING, APPS_RCM_O_CRYPTO_SOFT_RESET }, + {APPS_RCM_O_MCSPI_S0_CLK_GATING, APPS_RCM_O_MCSPI_S0_SOFT_RESET }, + {APPS_RCM_O_I2C_CLK_GATING, APPS_RCM_O_I2C_SOFT_RESET } + +}; + +//***************************************************************************** +// +//! Performs a software reset of a MCU and associated peripherals +//! +//! \param bIncludeSubsystem is \b true to reset associated peripherals. +//! +//! This function performs a software reset of a MCU and associated peripherals. +//! To reset the associated peripheral, the parameter \e bIncludeSubsystem +//! should be set to \b true. +//! +//! \return None. +// +//***************************************************************************** +void PRCMMCUReset(tBoolean bIncludeSubsystem) +{ + if(bIncludeSubsystem) + { + // + // Reset Apps processor and associated peripheral + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2; + } + else + { + // + // Reset Apps processor only + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1; + } + + // + // Wait for system to enter hibernate + // + __asm(" wfi\n"); + + // + // Infinite loop + // + while(1) + { + + } +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function returns the reason(s) for a reset. The reset reason are:- +//! -\b PRCM_POWER_ON - Device is powering up. +//! -\b PRCM_LPDS_EXIT - Device is exiting from LPDS. +//! -\b PRCM_CORE_RESET - Device is exiting soft core only reset +//! -\b PRCM_MCU_RESET - Device is exiting soft subsystem reset. +//! -\b PRCM_WDT_RESET - Device was reset by watchdog. +//! -\b PRCM_SOC_RESET - Device is exting SOC reset. +//! -\b PRCM_HIB_EXIT - Device is exiting hibernate. +//! +//! \return Returns one of the cause defined above. +// +//***************************************************************************** +unsigned long PRCMSysResetCauseGet() +{ + unsigned long ulWakeupStatus; + + // + // Read the Reset status + // + ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF); + + // + // For hibernate do additional check. + // + if(ulWakeupStatus == PRCM_POWER_ON) + { + if(PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS) & 0x1) + { + ulWakeupStatus = PRCM_HIB_EXIT; + + if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000280)) == 0x00000280 ) + { + ulWakeupStatus = PRCM_WDT_RESET; + } + } + } + else if((ulWakeupStatus == PRCM_LPDS_EXIT) && + !(HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG1) & (1 <<2)) ) + { + if(HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x1<<8)) + { + ulWakeupStatus = PRCM_POWER_ON; + } + } + + // + // Return status. + // + return ulWakeupStatus; +} + +//***************************************************************************** +// +//! Enable clock(s) to peripheral. +//! +//! \param ulPeripheral is one of the valid peripherals +//! \param ulClkFlags are bitmask of clock(s) to be enabled. +//! +//! This function enables the clock for the specified peripheral. Peripherals +//! are by default clock gated (disabled) and generates a bus fault if +//! accessed. +//! +//! The parameter \e ulClkFlags can be logical OR of the following: +//! -\b PRCM_RUN_MODE_CLK - Ungates clock to the peripheral +//! -\b PRCM_SLP_MODE_CLK - Keeps the clocks ungated in sleep. +//! +//! \return None. +// +//***************************************************************************** +void +PRCMPeripheralClkEnable(unsigned long ulPeripheral, unsigned long ulClkFlags) +{ + // + // Enable the specified peripheral clocks, Nothing to be done for PRCM_ADC + // as it is a dummy define for pinmux utility code generation + // + if(ulPeripheral != PRCM_ADC) + { + HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags; + } + + // + // Checking ROM Version less than 2.x.x. + // Only for driverlib backward compatibility + // + if( (HWREG(0x00000400) & 0xFFFF) < 2 ) + { + // + // Set the default clock for camera + // + if(ulPeripheral == PRCM_CAMERA) + { + HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404; + } + } +} + +//***************************************************************************** +// +//! Disables clock(s) to peripheral. +//! +//! \param ulPeripheral is one of the valid peripherals +//! \param ulClkFlags are bitmask of clock(s) to be enabled. +//! +//! This function disable the clock for the specified peripheral. Peripherals +//! are by default clock gated (disabled) and generated a bus fault if +//! accessed. +//! +//! The parameter \e ulClkFlags can be logical OR bit fields as defined in +//! PRCMEnablePeripheral(). +//! +//! \return None. +// +//***************************************************************************** +void +PRCMPeripheralClkDisable(unsigned long ulPeripheral, unsigned long ulClkFlags) +{ + // + // Disable the specified peripheral clocks + // + HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) &= ~ulClkFlags; +} + +//***************************************************************************** +// +//! Gets the input clock for the specified peripheral. +//! +//! \param ulPeripheral is one of the valid peripherals. +//! +//! This function gets the input clock for the specified peripheral. +//! +//! The parameter \e ulPeripheral has the same definition as that in +//! PRCMPeripheralClkEnable(); +//! +//! \return Returns input clock frequency for specified peripheral. +// +//***************************************************************************** +unsigned long +PRCMPeripheralClockGet(unsigned long ulPeripheral) +{ + unsigned long ulClockFreq; + unsigned long ulHiPulseDiv; + unsigned long ulLoPulseDiv; + + // + // Get the clock based on specified peripheral. + // + if(((ulPeripheral == PRCM_SSPI) | (ulPeripheral == PRCM_LSPI) + | (ulPeripheral == PRCM_GSPI))) + { + return XTAL_CLK; + } + else if(ulPeripheral == PRCM_CAMERA) + { + ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) >> 8) & 0x07); + ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN)& 0xFF); + } + else if(ulPeripheral == PRCM_SDHOST) + { + ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) >> 8) & 0x07); + ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN)& 0xFF); + } + else + { + return SYS_CLK; + } + + // + // Compute the clock freq. from the divider value + // + ulClockFreq = (240000000/((ulHiPulseDiv + 1) + (ulLoPulseDiv + 1))); + + // + // Return the clock rate. + // + return ulClockFreq; +} + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ulPeripheral is one of the valid peripheral. +//! +//! This function does soft reset of the specified peripheral +//! +//! \return None. +// +//***************************************************************************** +void +PRCMPeripheralReset(unsigned long ulPeripheral) +{ + volatile unsigned long ulDelay; + + if( ulPeripheral != PRCM_DTHE) + { + // + // Assert the reset + // + HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg) + |= PRCM_SOFT_RESET; + // + // Delay a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Deassert the reset + // + HWREG(ARCM_BASE+PRCM_PeriphRegsList[ulPeripheral].ulRstReg) + &= ~PRCM_SOFT_RESET; + } +} + +//***************************************************************************** +// +//! Determines if a peripheral is ready. +//! +//! \param ulPeripheral is one of the valid modules +//! +//! This function determines if a particular peripheral is ready to be +//! accessed. The peripheral may be in a non-ready state if it is not enabled, +//! is being held in reset, or is in the process of becoming ready after being +//! enabled or taken out of reset. +//! +//! \return Returns \b true if the peripheral is ready, \b false otherwise. +// +//***************************************************************************** +tBoolean +PRCMPeripheralStatusGet(unsigned long ulPeripheral) +{ + unsigned long ReadyBit; + + // + // Read the ready bit status + // + ReadyBit = HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg); + ReadyBit = ReadyBit & PRCM_ENABLE_STATUS; + + if (ReadyBit) + { + // + // Module is ready + // + return(true); + } + else + { + // + // Module is not ready + // + return(false); + } +} + +//***************************************************************************** +// +//! Configure I2S fracactional divider +//! +//! \param ulI2CClkFreq is the required input clock for McAPS module +//! +//! This function configures I2S fractional divider. By default this +//! divider is set to output 24 Mhz clock to I2S module. +//! +//! The minimum frequency that can be obtained by configuring this divider is +//! +//! (240000KHz/1023.99) = 234.377 KHz +//! +//! \return None. +// +//***************************************************************************** +void +PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq) +{ + unsigned long long ullDiv; + unsigned short usInteger; + unsigned short usFrac; + + ullDiv = (((unsigned long long)240000000 * 65536)/ulI2CClkFreq); + + usInteger = (ullDiv/65536); + usFrac = (ullDiv%65536); + + HWREG(ARCM_BASE + APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0) = + ((usInteger & 0x3FF) << 16 | usFrac); +} + +//***************************************************************************** +// +//! Sets the LPDS exit PC and SP restore vlaues. +//! +//! \param ulStackPtr is the SP restore value. +//! \param ulProgCntr is the PC restore value +//! +//! This function sets the LPDS exit PC and SP restore vlaues. Setting +//! \e ulProgCntr to a non-zero value, forces bootloader to jump to that +//! address with Stack Pointer initialized to \e ulStackPtr on LPDS exit, +//! otherwise the application's vector table entries are used. +//! +//! \return None. +// +//***************************************************************************** +void +PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr) +{ + // + // ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Set The SP Value + // + HWREG(0x4402E160) = ulStackPtr; + + // + // Set The PC Value + // + HWREG(0x4402E198) = ulProgCntr; + + } + else + { + // + // Set The SP Value + // + HWREG(0x4402E18C) = ulStackPtr; + + // + // Set The PC Value + // + HWREG(0x4402E190) = ulProgCntr; + } +} + +//***************************************************************************** +// +//! Puts the system into Low Power Deel Sleep (LPDS) power mode. +//! +//! This function puts the system into Low Power Deel Sleep (LPDS) power mode. +//! A call to this function never returns and the execution starts from Reset. +//! \sa PRCMLPDSRestoreInfoSet(). +//! +//! \return None. +//! +//! \note External debugger will always disconnect whenever the system +//! enters LPDS and debug interface is shutdown until next POR reset. In order +//! to avoid this and allow for connecting back the debugger after waking up +//! from LPDS \sa PRCMLPDSEnterKeepDebugIf(). +//! +// +//***************************************************************************** +void +PRCMLPDSEnter() +{ + unsigned long ulChipId; + + // + // Read the Chip ID + // + ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); + + // + // Check if flash exists + // + if( (0x11 == ulChipId) || (0x19 == ulChipId)) + { + + // + // Disable the flash + // + FlashDisable(); + } + +#ifndef KEEP_TESTPD_ALIVE + + // + // Disable TestPD + // + HWREG(0x4402E168) |= (1<<9); +#endif + + // + // Set bandgap duty cycle to 1 + // + HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; + + // + // Request LPDS + // + HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) + = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ; + + // + // Wait for system to enter LPDS + // + __asm(" wfi\n"); + + // + // Infinite loop + // + while(1) + { + + } + +} + + +//***************************************************************************** +// +//! Puts the system into Low Power Deel Sleep (LPDS) power mode keeping +//! debug interface alive. +//! +//! This function puts the system into Low Power Deel Sleep (LPDS) power mode +//! keeping debug interface alive. A call to this function never returns and the +//! execution starts from Reset \sa PRCMLPDSRestoreInfoSet(). +//! +//! \return None. +//! +//! \note External debugger will always disconnect whenever the system +//! enters LPDS, using this API will allow connecting back the debugger after +//! waking up from LPDS. This API is recommended for development purposes +//! only as it adds to the current consumption of the system. +//! +// +//***************************************************************************** +void +PRCMLPDSEnterKeepDebugIf() +{ + unsigned long ulChipId; + + // + // Read the Chip ID + // + ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); + + // + // Check if flash exists + // + if( (0x11 == ulChipId) || (0x19 == ulChipId)) + { + + // + // Disable the flash + // + FlashDisable(); + } + + // + // Set bandgap duty cycle to 1 + // + HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; + + // + // Request LPDS + // + HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) + = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ; + + // + // Wait for system to enter LPDS + // + __asm(" wfi\n"); + + // + // Infinite loop + // + while(1) + { + + } + +} + +//***************************************************************************** +// +//! Enable the individual LPDS wakeup source(s). +//! +//! \param ulLpdsWakeupSrc is logical OR of wakeup sources. +//! +//! This function enable the individual LPDS wakeup source(s) and following +//! three wakeup sources (\e ulLpdsWakeupSrc ) are supported by the device. +//! -\b PRCM_LPDS_HOST_IRQ +//! -\b PRCM_LPDS_GPIO +//! -\b PRCM_LPDS_TIMER +//! +//! \return None. +// +//***************************************************************************** +void +PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc) +{ + unsigned long ulRegVal; + + // + // Read the current wakup sources + // + ulRegVal = HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG); + + // + // Enable individual wakeup source + // + ulRegVal = ((ulRegVal | ulLpdsWakeupSrc) & 0x91); + + // + // Set the configuration in the register + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) = ulRegVal; +} + +//***************************************************************************** +// +//! Disable the individual LPDS wakeup source(s). +//! +//! \param ulLpdsWakeupSrc is logical OR of wakeup sources. +//! +//! This function enable the individual LPDS wakeup source(s) and following +//! three wake up sources (\e ulLpdsWakeupSrc ) are supported by the device. +//! -\b PRCM_LPDS_HOST_IRQ +//! -\b PRCM_LPDS_GPIO +//! -\b PRCM_LPDS_TIMER +//! +//! \return None. +// +//***************************************************************************** +void +PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc) +{ + HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) &= ~ulLpdsWakeupSrc; +} + + +//***************************************************************************** +// +//! Get LPDS wakeup cause +//! +//! This function gets LPDS wakeup caouse +//! +//! \return Returns values enumerated as described in +//! PRCMLPDSWakeupSourceEnable(). +// +//***************************************************************************** +unsigned long +PRCMLPDSWakeupCauseGet() +{ + return (HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_SRC)); +} + +//***************************************************************************** +// +//! Sets LPDS wakeup Timer +//! +//! \param ulTicks is number of 32.768 KHz clocks +//! +//! This function sets internal LPDS wakeup timer running at 32.768 KHz. The +//! timer is only configured if the parameter \e ulTicks is in valid range i.e. +//! from 21 to 2^32. +//! +//! \return Returns \b true on success, \b false otherwise. +// +//***************************************************************************** +void +PRCMLPDSIntervalSet(unsigned long ulTicks) +{ + // + // Check sleep is atleast for 21 cycles + // If not set the sleep time to 21 cycles + // + if( ulTicks < 21) + { + ulTicks = 21; + } + + HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG) = ulTicks; + HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG) = ulTicks-20; +} + +//***************************************************************************** +// +//! Selects the GPIO for LPDS wakeup +//! +//! \param ulGPIOPin is one of the valid GPIO fro LPDS wakeup. +//! \param ulType is the wakeup trigger type. +//! +//! This function setects the wakeup GPIO for LPDS wakeup and can be +//! used to select one out of 7 pre-defined GPIO(s). +//! +//! The parameter \e ulLpdsGPIOSel should be one of the following:- +//! -\b PRCM_LPDS_GPIO2 +//! -\b PRCM_LPDS_GPIO4 +//! -\b PRCM_LPDS_GPIO13 +//! -\b PRCM_LPDS_GPIO17 +//! -\b PRCM_LPDS_GPIO11 +//! -\b PRCM_LPDS_GPIO24 +//! -\b PRCM_LPDS_GPIO26 +//! +//! The parameter \e ulType sets the trigger type and can be one of the +//! following: +//! - \b PRCM_LPDS_LOW_LEVEL +//! - \b PRCM_LPDS_HIGH_LEVEL +//! - \b PRCM_LPDS_FALL_EDGE +//! - \b PRCM_LPDS_RISE_EDGE +//! +//! \return None. +// +//***************************************************************************** +void +PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType) +{ + // + // Set the wakeup GPIO + // + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL, ulGPIOPin); + + // + // Set the trigger type. + // + HWREG(GPRCM_BASE + GPRCM_O_APPS_GPIO_WAKE_CONF) = (ulType & 0x3); +} + +//***************************************************************************** +// +//! Puts the system into Sleep. +//! +//! This function puts the system into sleep power mode. System exits the power +//! state on any one of the available interrupt. On exit from sleep mode the +//! function returns to the calling function with all the processor core +//! registers retained. +//! +//! \return None. +// +//***************************************************************************** +void +PRCMSleepEnter() +{ + // + // Request Sleep + // + CPUwfi(); +} + +//***************************************************************************** +// +//! Enable SRAM column retention during LPDS Power mode(s) +//! +//! \param ulSramColSel is bit mask of valid SRAM columns. +//! \param ulModeFlags is the bit mask of power modes. +//! +//! This functions enables the SRAM retention. The device supports configurable +//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is of +//! 64 KB size. +//! +//! The parameter \e ulSramColSel should be logical OR of the following:- +//! -\b PRCM_SRAM_COL_1 +//! -\b PRCM_SRAM_COL_2 +//! -\b PRCM_SRAM_COL_3 +//! -\b PRCM_SRAM_COL_4 +//! +//! The parameter \e ulModeFlags selects the power modes and sholud be logical +//! OR of one or more of the following +//! -\b PRCM_SRAM_LPDS_RET +//! +//! \return None. +// +//**************************************************************************** +void +PRCMSRAMRetentionEnable(unsigned long ulSramColSel, unsigned long ulModeFlags) +{ + if(ulModeFlags & PRCM_SRAM_LPDS_RET) + { + // + // Configure LPDS SRAM retention register + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) = (ulSramColSel & 0xF); + } +} + +//***************************************************************************** +// +//! Disable SRAM column retention during LPDS Power mode(s). +//! +//! \param ulSramColSel is bit mask of valid SRAM columns. +//! \param ulFlags is the bit mask of power modes. +//! +//! This functions disable the SRAM retention. The device supports configurable +//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is +//! of 64 KB size. +//! +//! The parameter \e ulSramColSel should be logical OR of the following:- +//! -\b PRCM_SRAM_COL_1 +//! -\b PRCM_SRAM_COL_2 +//! -\b PRCM_SRAM_COL_3 +//! -\b PRCM_SRAM_COL_4 +//! +//! The parameter \e ulFlags selects the power modes and sholud be logical OR +//! of one or more of the following +//! -\b PRCM_SRAM_LPDS_RET +//! +//! \return None. +// +//**************************************************************************** +void +PRCMSRAMRetentionDisable(unsigned long ulSramColSel, unsigned long ulFlags) +{ + if(ulFlags & PRCM_SRAM_LPDS_RET) + { + // + // Configure LPDS SRAM retention register + // + HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) &= ~(ulSramColSel & 0xF); + } +} + + +//***************************************************************************** +// +//! Enables individual HIB wakeup source(s). +//! +//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources. +//! +//! This function enables individual HIB wakeup source(s). The paramter +//! \e ulHIBWakupSrc is the bit mask of HIB wakeup sources and should be +//! logical OR of one or more of the follwoing :- +//! -\b PRCM_HIB_SLOW_CLK_CTR +//! -\b PRCM_HIB_GPIO2 +//! -\b PRCM_HIB_GPIO4 +//! -\b PRCM_HIB_GPIO13 +//! -\b PRCM_HIB_GPIO17 +//! -\b PRCM_HIB_GPIO11 +//! -\b PRCM_HIB_GPIO24 +//! -\b PRCM_HIB_GPIO26 +//! +//! \return None. +// +//***************************************************************************** +void +PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc) +{ + unsigned long ulRegValue; + + // + // Read the RTC register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); + + // + // Enable the RTC as wakeup source if specified + // + ulRegValue |= (ulHIBWakupSrc & 0x1); + + // + // Enable HIB wakeup sources + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); + + // + // REad the GPIO wakeup configuration register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN); + + // + // Enable the specified GPIOs a wakeup sources + // + ulRegValue |= ((ulHIBWakupSrc>>16)&0xFF); + + // + // Write the new register configuration + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue); +} + +//***************************************************************************** +// +//! Disable individual HIB wakeup source(s). +//! +//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources. +//! +//! This function disable individual HIB wakeup source(s). The paramter +//! \e ulHIBWakupSrc is same as bit fileds defined in +//! PRCMEnableHibernateWakeupSource() +//! +//! \return None. +// +//***************************************************************************** +void +PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc) +{ + unsigned long ulRegValue; + + // + // Read the RTC register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); + + // + // Disable the RTC as wakeup source if specified + // + ulRegValue &= ~(ulHIBWakupSrc & 0x1); + + // + // Disable HIB wakeup sources + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); + + // + // Read the GPIO wakeup configuration register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN); + + // + // Enable the specified GPIOs a wakeup sources + // + ulRegValue &= ~((ulHIBWakupSrc>>16)&0xFF); + + // + // Write the new register configuration + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue); +} + + +//***************************************************************************** +// +//! Get hibernate wakeup cause +//! +//! This function gets the hibernate wakeup cause. +//! +//! \return Returns \b PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK or +//! \b PRCM_HIB_WAKEUP_CAUSE_GPIO +// +//***************************************************************************** +unsigned long +PRCMHibernateWakeupCauseGet() +{ + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + return ((PRCMHIBRegRead((OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8))>>2)&0x7); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +//! Sets Hibernate wakeup Timer +//! +//! \param ullTicks is number of 32.768 KHz clocks +//! +//! This function sets internal hibernate wakeup timer running at 32.768 KHz. +//! +//! \return Returns \b true on success, \b false otherwise. +// +//***************************************************************************** +void +PRCMHibernateIntervalSet(unsigned long long ullTicks) +{ + unsigned long long ullRTCVal; + + // + // Latch the RTC vlaue + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1); + + // + // Read latched values as 2 32-bit vlaues + // + ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW); + ullRTCVal = ullRTCVal << 32; + ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW); + + // + // Add the interval + // + ullRTCVal = ullRTCVal + ullTicks; + + // + // Set RTC match value + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF, + (unsigned long)(ullRTCVal)); + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF, + (unsigned long)(ullRTCVal>>32)); +} + + +//***************************************************************************** +// +//! Selects the GPIO(s) for hibernate wakeup +//! +//! \param ulGPIOBitMap is the bit-map of valid hibernate wakeup GPIO. +//! \param ulType is the wakeup trigger type. +//! +//! This function setects the wakeup GPIO for hibernate and can be +//! used to select any combination of 7 pre-defined GPIO(s). +//! +//! This function enables individual HIB wakeup source(s). The paramter +//! \e ulGPIOBitMap should be one of the follwoing :- +//! -\b PRCM_HIB_GPIO2 +//! -\b PRCM_HIB_GPIO4 +//! -\b PRCM_HIB_GPIO13 +//! -\b PRCM_HIB_GPIO17 +//! -\b PRCM_HIB_GPIO11 +//! -\b PRCM_HIB_GPIO24 +//! -\b PRCM_HIB_GPIO26 +//! +//! The parameter \e ulType sets the trigger type and can be one of the +//! following: +//! - \b PRCM_HIB_LOW_LEVEL +//! - \b PRCM_HIB_HIGH_LEVEL +//! - \b PRCM_HIB_FALL_EDGE +//! - \b PRCM_HIB_RISE_EDGE +//! +//! \return None. +// +//***************************************************************************** +void +PRCMHibernateWakeUpGPIOSelect(unsigned long ulGPIOBitMap, unsigned long ulType) +{ + unsigned char ucLoop; + unsigned long ulRegValue; + + // + // Shift the bits to extract the GPIO selection + // + ulGPIOBitMap >>= 16; + + // + // Set the configuration for each GPIO + // + for(ucLoop=0; ucLoop < 7; ucLoop++) + { + if(ulGPIOBitMap & (1<>32)); +} + +//***************************************************************************** +// +//! Gets slow clock counter match value. +//! +//! This function gets the match value for slow clock counter. This is use +//! to interrupt the processor when RTC counts to the specified value. +//! +//! \return None. +// +//***************************************************************************** +unsigned long long PRCMSlowClkCtrMatchGet() +{ + unsigned long long ullValue; + + // + // Get RTC match value + // + ullValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF); + ullValue = ullValue<<32; + ullValue |= PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF); + + // + // Return the value + // + return ullValue; +} + + +//***************************************************************************** +// +//! Write to On-Chip Retention (OCR) register. +//! +//! This function writes to On-Chip retention register. The device supports two +//! 4-byte OCR register which are retained across all power mode. +//! +//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1. +//! +//! These registers are shared by the RTC implementation (if Driverlib RTC +//! APIs are used), ROM, and user application. +//! +//! When RTC APIs in use: +//! +//! |-----------------------------------------------| +//! | INDEX 1 | +//! |-----------------------------------------------| +//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |-----------------------------------------------| +//! | Reserved by RTC APIs - YY | +//! |-----------------------------------------------| +//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |-----------------------------------------------| +//! | Reserved by RTC APIs - YY | +//! |-----------------------------------------------| +//! +//! +//! |-----------------------------------------------| +//! | INDEX 0 | +//! |-----------------------------------------------| +//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |-----------------------------------------------| +//! | Reserved by RTC APIs - YY | +//! |-----------------------------------------------| +//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |-----------------------------------------------| +//! |YY| For User Application |XX| +//! |-----------------------------------------------| +//! +//! YY => Reserved by RTC APIs. If Driverlib RTC APIs are used +//! XX => Reserved by ROM +//! +//! +//! When RTC APIs are not in use: +//! +//! |-----------------------------------------------| +//! | INDEX 1 | +//! |-----------------------------------------------| +//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |-----------------------------------------------| +//! | For User Application | +//! |-----------------------------------------------| +//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |-----------------------------------------------| +//! | For User Application | +//! |-----------------------------------------------| +//! +//! +//! |-----------------------------------------------| +//! | INDEX 0 | +//! |-----------------------------------------------| +//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| +//! |-----------------------------------------------| +//! | For User Application | +//! |-----------------------------------------------| +//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +//! |-----------------------------------------------| +//! | For User Application |XX| +//! |-----------------------------------------------| +//! +//! XX => Reserved by ROM +//! +//! +//! +//! \return None. +// +//***************************************************************************** +void PRCMOCRRegisterWrite(unsigned char ucIndex, unsigned long ulRegValue) +{ + unsigned long ulVal; + + // + // Compuitr the offset + // + ucIndex = ucIndex << 2; + + // + // If bit 0 is reserved + // + if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && + (ucIndex == 0) ) + { + ulVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex); + ulRegValue = ((ulRegValue << 0x1) | (ulVal & (0x1))); + } + + // + // Write thr value + // + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex,ulRegValue); + +} + +//***************************************************************************** +// +//! Read from On-Chip Retention (OCR) register. +//! +//! This function reads from On-Chip retention register. The device supports two +//! 4-byte OCR register which are retained across all power mode. +//! +//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1. +//! +//! \sa PRCMOCRRegisterWrite() for the register usage details. +//! +//! \return None. +// +//***************************************************************************** +unsigned long PRCMOCRRegisterRead(unsigned char ucIndex) +{ + unsigned long ulRet; + + // + // Read the OCR register + // + ulRet = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2 + (ucIndex << 2)); + + // + // If bit 0 is reserved + // + if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && + (ucIndex == 0) ) + { + ulRet = ulRet >> 0x1; + } + + // + // Return the read value. + // + return ulRet; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the PRCM. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; +//! +//! \return None. +// +//***************************************************************************** +void PRCMIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler. + // + IntRegister(INT_PRCM, pfnHandler); + + // + // Enable the PRCM interrupt. + // + IntEnable(INT_PRCM); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the PRCM. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a PRCM interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None. +// +//***************************************************************************** +void PRCMIntUnregister() +{ + // + // Enable the UART interrupt. + // + IntDisable(INT_PRCM); + + // + // Register the interrupt handler. + // + IntUnregister(INT_PRCM); +} + +//***************************************************************************** +// +//! Enables individual PRCM interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated ARCM interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! -\b PRCM_INT_SLOW_CLK_CTR +//! +// +//***************************************************************************** +void PRCMIntEnable(unsigned long ulIntFlags) +{ + unsigned long ulRegValue; + + if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR ) + { + // + // Enable PRCM interrupt + // + HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) |= 0x4; + + // + // Enable RTC interrupt + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE); + ulRegValue |= 0x1; + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue); + } +} + +//***************************************************************************** +// +//! Disables individual PRCM interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated ARCM interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to PRCMEnableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +void PRCMIntDisable(unsigned long ulIntFlags) +{ + unsigned long ulRegValue; + + if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR ) + { + // + // Disable PRCM interrupt + // + HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) &= ~0x4; + + // + // Disable RTC interrupt + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE); + ulRegValue &= ~0x1; + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue); + } +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! This function returns the PRCM interrupt status of interrupts that are +//! allowed to reflect to the processor. The interrupts are cleared on read. +//! +//! \return Returns the current interrupt status. +// +//***************************************************************************** +unsigned long PRCMIntStatus() +{ + return HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS); +} + +//***************************************************************************** +// +//! Mark the function of RTC as being used +//! +//! This function marks in HW that feature to maintain calendar time in device +//! is being used. +//! +//! Specifically, this feature reserves user's HIB Register-1 accessed through +//! PRCMOCRRegisterWrite(1) for internal work / purpose, therefore, the stated +//! register is not available to user. Also, users must not excercise the Slow +//! Clock Counter API(s), if RTC has been set for use. +//! +//! The RTC feature, if set or marked, can be only reset either through reboot +//! or power cycle. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCInUseSet() +{ + RTC_USE_SET(); + return; +} + +//***************************************************************************** +// +//! Ascertain whether function of RTC is being used +//! +//! This function indicates whether function of RTC is being used on the device +//! or not. +//! +//! This routine should be utilized by the application software, when returning +//! from low-power, to confirm that RTC has been put to use and may not need to +//! set the value of the RTC. +//! +//! The RTC feature, if set or marked, can be only reset either through reboot +//! or power cycle. +//! +//! \return None. +// +//***************************************************************************** +tBoolean PRCMRTCInUseGet() +{ + return IS_RTC_USED()? true : false; +} + +//***************************************************************************** +// +//! Set the calendar time in the device. +//! +//! \param ulSecs refers to the seconds part of the calendar time +//! \param usMsec refers to the fractional (ms) part of the second +//! +//! This function sets the specified calendar time in the device. The calendar +//! time is outlined in terms of seconds and milliseconds. However, the device +//! makes no assumption about the origin or reference of the calendar time. +//! +//! The device uses the indicated calendar value to update and maintain the +//! wall-clock time across active and low power states. +//! +//! The function PRCMRTCInUseSet() must be invoked prior to use of this feature. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec) +{ + unsigned long long ullMsec = 0; + + if(IS_RTC_USED()) { + ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec) - SCC_U64MSEC_GET(); + + RTC_U32SECS_REG_WR(RTC_SECS_IN_U64MSEC(ullMsec)); + RTC_U16MSEC_REG_WR(RTC_MSEC_IN_U64MSEC(ullMsec)); + } + + return; +} + +//***************************************************************************** +// +//! Get the instantaneous calendar time from the device. +//! +//! \param ulSecs refers to the seconds part of the calendar time +//! \param usMsec refers to the fractional (ms) part of the second +//! +//! This function fetches the instantaneous value of the ticking calendar time +//! from the device. The calendar time is outlined in terms of seconds and +//! milliseconds. +//! +//! The device provides the calendar value that has been maintained across +//! active and low power states. +//! +//! The function PRCMRTCSet() must have been invoked once to set a reference. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec) +{ + unsigned long long ullMsec = 0; + + if(IS_RTC_USED()) { + ullMsec = RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), + RTC_U16MSEC_REG_RD()); + ullMsec += SCC_U64MSEC_GET(); + } + + *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec); + *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec); + + return; +} + +//***************************************************************************** +// +//! Set a calendar time alarm. +//! +//! \param ulSecs refers to the seconds part of the calendar time +//! \param usMsec refers to the fractional (ms) part of the second +//! +//! This function sets an wall-clock alarm in the device to be reported for a +//! futuristic calendar time. The calendar time is outlined in terms of seconds +//! and milliseconds. +//! +//! The device provides uses the calendar value that has been maintained across +//! active and low power states to report attainment of alarm time. +//! +//! The function PRCMRTCSet() must have been invoked once to set a reference. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec) +{ + unsigned long long ullMsec = 0; + + if(IS_RTC_USED()) { + ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec); + ullMsec -= RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), + RTC_U16MSEC_REG_RD()); + SCC_U64MSEC_MATCH_SET(SELECT_SCC_U42BITS(ullMsec)); + } + + return; +} + +//***************************************************************************** +// +//! Get a previously set calendar time alarm. +//! +//! \param ulSecs refers to the seconds part of the calendar time +//! \param usMsec refers to the fractional (ms) part of the second +//! +//! This function fetches from the device a wall-clock alarm that would have +//! been previously set in the device. The calendar time is outlined in terms +//! of seconds and milliseconds. +//! +//! If no alarm was set in the past, then this function would fetch a random +//! information. +//! +//! The function PRCMRTCMatchSet() must have been invoked once to set an alarm. +//! +//! \return None. +// +//***************************************************************************** +void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec) +{ + unsigned long long ullMsec = 0; + + if(IS_RTC_USED()) { + ullMsec = SCC_U64MSEC_MATCH_GET(); + ullMsec += RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), + RTC_U16MSEC_REG_RD()); + } + + *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec); + *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec); + + return; +} + +//***************************************************************************** +// +//! MCU Initialization Routine +//! +//! This function contains all the mandatory bug fixes, ECO enables, +//! initializations for both CC3200 and CC3220. +//! +//! \note \b ###IMPORTANT### : This is a routine which should be one of the +//! first things to be executed after control comes to MCU Application code. +//! +//! \return None +// +//***************************************************************************** +void PRCMCC3200MCUInit() +{ + + if( PRCMSysResetCauseGet() != PRCM_LPDS_EXIT ) + { + if( 0x00010001 == HWREG(0x00000400) ) + { + +#ifndef REMOVE_CC3200_ES_1_2_1_CODE + + unsigned long ulRegVal; + + // + // DIG DCDC NFET SEL and COT mode disable + // + HWREG(0x4402F010) = 0x30031820; + HWREG(0x4402F00C) = 0x04000000; + + UtilsDelay(32000); + + // + // ANA DCDC clock config + // + HWREG(0x4402F11C) = 0x099; + HWREG(0x4402F11C) = 0x0AA; + HWREG(0x4402F11C) = 0x1AA; + + // + // PA DCDC clock config + // + HWREG(0x4402F124) = 0x099; + HWREG(0x4402F124) = 0x0AA; + HWREG(0x4402F124) = 0x1AA; + + // + // TD Flash timing configurations in case of MCU WDT reset + // + if((HWREG(0x4402D00C) & 0xFF) == 0x00000005) + { + HWREG(0x400F707C) |= 0x01840082; + HWREG(0x400F70C4)= 0x1; + HWREG(0x400F70C4)= 0x0; + } + + // + // Take I2C semaphore + // + ulRegVal = HWREG(0x400F7000); + ulRegVal = (ulRegVal & ~0x3) | 0x1; + HWREG(0x400F7000) = ulRegVal; + + // + // Take GPIO semaphore + // + ulRegVal = HWREG(0x400F703C); + ulRegVal = (ulRegVal & ~0x3FF) | 0x155; + HWREG(0x400F703C) = ulRegVal; + + // + // Enable 32KHz internal RC oscillator + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_INT_OSC_CONF, 0x00000101); + + // + // Delay for a little bit. + // + UtilsDelay(8000); + + // + // Enable 16MHz clock + // + HWREG(HIB1P2_BASE+HIB1P2_O_CM_OSC_16M_CONFIG) = 0x00010008; + + // + // Delay for a little bit. + // + UtilsDelay(8000); + +#endif // REMOVE_CC3200_ES_1_2_1_CODE + + } + else + { + + unsigned long ulRegValue; + + // + // DIG DCDC LPDS ECO Enable + // + HWREG(0x4402F064) |= 0x800000; + + // + // Enable hibernate ECO for PG 1.32 devices only. With this ECO enabled, + // any hibernate wakeup source will be kept maked until the device enters + // hibernate completely (analog + digital) + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0, ulRegValue | (1<<4)); + + // + // Handling the clock switching (for 1.32 only) + // + HWREG(0x4402E16C) |= 0x3C; + } + + + // + // Enable uDMA + // + PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK); + + // + // Reset uDMA + // + PRCMPeripheralReset(PRCM_UDMA); + + // + // Disable uDMA + // + PRCMPeripheralClkDisable(PRCM_UDMA,PRCM_RUN_MODE_CLK); + + // + // Enable RTC + // + + PRCMHIBRegWrite(0x4402F804,0x1); + + // + // Enable Timers + // + PRCMPeripheralClkEnable(PRCM_TIMERA0,PRCM_RUN_MODE_CLK); + PRCMPeripheralClkEnable(PRCM_TIMERA1,PRCM_RUN_MODE_CLK); + PRCMPeripheralClkEnable(PRCM_TIMERA2,PRCM_RUN_MODE_CLK); + PRCMPeripheralClkEnable(PRCM_TIMERA3,PRCM_RUN_MODE_CLK); + + // + // Enable UART0 + // + PRCMPeripheralClkEnable(PRCM_UARTA0,PRCM_RUN_MODE_CLK); + PRCMPeripheralClkEnable(PRCM_UARTA1,PRCM_RUN_MODE_CLK); + + // + // Enable GPIOs + // + PRCMPeripheralClkEnable(PRCM_GPIOA0,PRCM_RUN_MODE_CLK); + PRCMPeripheralClkEnable(PRCM_GPIOA1,PRCM_RUN_MODE_CLK); + PRCMPeripheralClkEnable(PRCM_GPIOA2,PRCM_RUN_MODE_CLK); + PRCMPeripheralClkEnable(PRCM_GPIOA3,PRCM_RUN_MODE_CLK); + + // + // Enable SPI + // + PRCMPeripheralClkEnable(PRCM_GSPI,PRCM_RUN_MODE_CLK); + + // + // SWD mode + // + if(((HWREG(0x4402F0C8) & 0xFF) == 0x2)) + { + HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2); + HWREG(0x4402E114) = ((HWREG(0x4402E114) & ~0xC0F) | 0x2); + } + + // + // Override JTAG mux + // + HWREG(0x4402E184) |= 0x2; + + // + // Change UART pins(55,57) mode to PIN_MODE_0 if they are in PIN_MODE_1 + // + if (PinModeGet(PIN_55) == PIN_MODE_1) + { + PinModeSet(PIN_55,PIN_MODE_0); + } + if (PinModeGet(PIN_57) == PIN_MODE_1) + { + PinModeSet(PIN_57,PIN_MODE_0); + } + + // + // Change I2C pins(1,2) mode to PIN_MODE_0 if they are in PIN_MODE_1 + // + if (PinModeGet(PIN_01) == PIN_MODE_1) + { + PinModeSet(PIN_01,PIN_MODE_0); + } + if (PinModeGet(PIN_02) == PIN_MODE_1) + { + PinModeSet(PIN_02,PIN_MODE_0); + } + + // + // DIG DCDC VOUT trim settings based on PROCESS INDICATOR + // + if(((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE) + { + HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x32 << 18)); + } + else + { + HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x29 << 18)); + } + + // + // Enable SOFT RESTART in case of DIG DCDC collapse + // + HWREG(0x4402FC74) &= ~(0x10000000); + + // + // Required only if ROM version is lower than 2.x.x + // + if( (HWREG(0x00000400) & 0xFFFF) < 2 ) + { + // + // Disable the sleep for ANA DCDC + // + HWREG(0x4402F0A8) |= 0x00000004 ; + } + else if( (HWREG(0x00000400) >> 16) >= 1 ) + { + // + // Enable NWP force reset and HIB on WDT reset + // Enable direct boot path for flash + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= ((7<<5) | 0x1); + if((HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) & 0x1) ) + { + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) &= ~0x1; + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= (1<<9); + + // + // Clear the RTC hib wake up source + // + HWREG(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN) &= ~0x1; + + // + // Reset RTC match value + // + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF) = 0; + HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF) = 0; + + } + } + + unsigned long efuse_reg2; + unsigned long ulDevMajorVer, ulDevMinorVer; + // + // Read the device identification register + // + efuse_reg2= HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); + + // + // Read the ROM mojor and minor version + // + ulDevMajorVer = ((efuse_reg2 >> 28) & 0xF); + ulDevMinorVer = ((efuse_reg2 >> 24) & 0xF); + + if(((ulDevMajorVer == 0x3) && (ulDevMinorVer == 0)) || (ulDevMajorVer < 0x3)) + { + unsigned int Scratch, PreRegulatedMode; + + // 0x4402F840 => 6th bit “1†indicates device is in pre-regulated mode. + PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; + + if( PreRegulatedMode) + { + Scratch = HWREG(0x4402F028); + Scratch &= 0xFFFFFF7F; // <7:7> = 0 + HWREG(0x4402F028) = Scratch; + + Scratch = HWREG(0x4402F010); + Scratch &= 0x0FFFFFFF; // <31:28> = 0 + Scratch |= 0x10000000; // <31:28> = 1 + HWREG(0x4402F010) = Scratch; + } + else + { + Scratch = HWREG(0x4402F024); + + Scratch &= 0xFFFFFFF0; // <3:0> = 0 + Scratch |= 0x00000001; // <3:0> = 1 + Scratch &= 0xFFFFF0FF; // <11:8> = 0000 + Scratch |= 0x00000500; // <11:8> = 0101 + Scratch &= 0xFFFE7FFF; // <16:15> = 0000 + Scratch |= 0x00010000; // <16:15> = 10 + + HWREG(0x4402F024) = Scratch; + + Scratch = HWREG(0x4402F028); + + Scratch &= 0xFFFFFF7F; // <7:7> = 0 + Scratch &= 0x0FFFFFFF; // <31:28> = 0 + Scratch &= 0xFF0FFFFF; // <23:20> = 0 + Scratch |= 0x00300000; // <23:20> = 0011 + Scratch &= 0xFFF0FFFF; // <19:16> = 0 + Scratch |= 0x00030000; // <19:16> = 0011 + + HWREG(0x4402F028) = Scratch; + HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 + } + } + else + { + unsigned int Scratch, PreRegulatedMode; + + // 0x4402F840 => 6th bit “1†indicates device is in pre-regulated mode. + PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; + + Scratch = HWREG(0x4402F028); + Scratch &= 0xFFFFFF7F; // <7:7> = 0 + HWREG(0x4402F028) = Scratch; + + HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 + if( PreRegulatedMode) + { + HWREG(0x4402F010) |= 0x10000000; // <31:28> = 1 + } + } + } + else + { + unsigned long ulRegVal; + + // + // I2C Configuration + // + ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register); + ulRegVal = (ulRegVal & ~0x3) | 0x1; + HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = ulRegVal; + + // + // GPIO configuration + // + ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register); + ulRegVal = (ulRegVal & ~0x3FF) | 0x155; + HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = ulRegVal; + + } +} + +//***************************************************************************** +// +//! Reads 32-bit value from register at specified address +//! +//! \param ulRegAddr is the address of register to be read. +//! +//! This function reads 32-bit value from the register as specified by +//! \e ulRegAddr. +//! +//! \return Return the value of the register. +// +//***************************************************************************** +unsigned long PRCMHIBRegRead(unsigned long ulRegAddr) +{ + unsigned long ulValue; + + // + // Read the Reg value + // + ulValue = HWREG(ulRegAddr); + + // + // Wait for 200 uSec + // + UtilsDelay((80*200)/3); + + // + // Return the value + // + return ulValue; +} + +//***************************************************************************** +// +//! Writes 32-bit value to register at specified address +//! +//! \param ulRegAddr is the address of register to be read. +//! \param ulValue is the 32-bit value to be written. +//! +//! This function writes 32-bit value passed as \e ulValue to the register as +//! specified by \e ulRegAddr +//! +//! \return None +// +//***************************************************************************** +void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue) +{ + // + // Read the Reg value + // + HWREG(ulRegAddr) = ulValue; + + // + // Wait for 200 uSec + // + UtilsDelay((80*200)/3); +} + +//***************************************************************************** +// +//! \param ulDivider is clock frequency divider value +//! \param ulWidth is the width of the high pulse +//! +//! This function sets the input frequency for camera module. +//! +//! The frequency is calculated as follows: +//! +//! f_out = 240MHz/ulDivider; +//! +//! The parameter \e ulWidth sets the width of the high pulse. +//! +//! For e.g.: +//! +//! ulDivider = 4; +//! ulWidth = 2; +//! +//! f_out = 30 MHz and 50% duty cycle +//! +//! And, +//! +//! ulDivider = 4; +//! ulWidth = 1; +//! +//! f_out = 30 MHz and 25% duty cycle +//! +//! \return 0 on success, 1 on error +// +//***************************************************************************** +unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth) +{ + if(ulDivider > ulWidth && ulWidth != 0 ) + { + // + // Set the hifh pulse width + // + HWREG(ARCM_BASE + + APPS_RCM_O_CAMERA_CLK_GEN) = (((ulWidth & 0x07) -1) << 8); + + // + // Set the low pulse width + // + HWREG(ARCM_BASE + + APPS_RCM_O_CAMERA_CLK_GEN) = ((ulDivider - ulWidth - 1) & 0x07); + // + // Return success + // + return 0; + } + + // + // Success; + // + return 1; +} + +//***************************************************************************** +// +//! Enable the IO value retention +//! +//! \param ulIORetGrpFlags is one of the valid IO groups. +//! +//! This function enables the IO retention for group of pins as specified by +//! \e ulIORetGrpFlags parameter. Enabling retention will immediately lock the +//! digital pins, in the specified group, to their current state (0 or 1). +//! Output pins can only be driven when retention is disabled. +//! +//! The parameter \e ulIORetGrpFlags can be logical OR of one or +//! more of the following: +//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface +//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 +//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 +//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 +//! +//! \note Use case is to park the pins when entering HIB. +//! +//! \return None. +// +//***************************************************************************** +void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags) +{ + unsigned long ulRegVal; + + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + // + // Disable IO Pad to ODI Path + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00001D00; + + // + // 0b'0 in bit 5 for JTAG PADS + // 0b'0 in bit 0 for all other IOs + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00000023); + + // + // Enable retention for GRP0 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 ) + { + ulRegVal = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF); + ulRegVal |= 0x5; + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF,ulRegVal); + } + + // + // Enable retention for GRP1 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 ) + { + ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); + ulRegVal |= ((0x3<<5)); + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0,ulRegVal); + } + + // + // Enable retention for GRP2 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 ) + { + ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); + ulRegVal |= 0x00000101; + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); + } + + // + // Enable retention for GRP3 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 ) + { + ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); + ulRegVal |= 0x00000204; + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); + } + } +} + +//***************************************************************************** +// +//! Disable the IO value retention +//! +//! \param ulIORetGrpFlags is one of the valid IO groups. +//! +//! This function disable the IO retention for group of pins as specified by +//! \e ulIORetGrpFlags parameter. Disabling retention will unlock the +//! digital pins in the specified group. Output pins can only be driven when +//! retention is disabled. +//! +//! The parameter \e ulIORetGrpFlags can be logical OR of one or +//! more of the following: +//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface +//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 +//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 +//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 +//! +//! \note Use case is to un-park the pins when exiting HIB +//! +//! \return None. +// +//***************************************************************************** +void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags) +{ + unsigned long ulRegVal; + + // + // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater + // + if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) + { + + // + // Enable IO Pad to ODI Path + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00001D00); + + // + // 0b'1 in bit 5 for JTAG PADS + // 0b'1 in bit 0 for all other IOs + // + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00000023; + + // + // Disable retention for GRP0 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 ) + { + ulRegVal = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF); + ulRegVal &= ~0x5; + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF,ulRegVal); + } + + // + // Disable retention for GRP1 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 ) + { + ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); + ulRegVal &= ~((0x3<<5)); + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0,ulRegVal); + } + + // + // Disable retention for GRP2 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 ) + { + ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); + ulRegVal &= ~0x00000101; + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); + + } + + // + // Disable retention for GRP3 + // + if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 ) + { + ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); + ulRegVal &= ~0x00000204; + PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); + } + + } +} + +//***************************************************************************** +// +//! Gets the device type +//! +//! This function returns bit-packed value representing the device type +//! +//! The returned value is logical OR of one or more of the following:- +//! +//! -\b PRCM_DEV_TYPE_FLAG_R - R variant +//! -\b PRCM_DEV_TYPE_FLAG_F - F variant +//! -\b PRCM_DEV_TYPE_FLAG_Z - Z variant +//! -\b PRCM_DEV_TYPE_FLAG_SECURE - Device is secure +//! -\b PRCM_DEV_TYPE_FLAG_PRE_PROD - Device is a pre-production part +//! -\b PRCM_DEV_TYPE_FLAG_3200 - Device is CC3200 +//! -\b PRCM_DEV_TYPE_FLAG_3220 - Device is CC3220 +//! -\b PRCM_DEV_TYPE_FLAG_REV1 - Device Rev 1 +//! -\b PRCM_DEV_TYPE_FLAG_REV2 - Device Rev 2 +//! +//! Pre-defined helper macros:- +//! +//! -\b PRCM_DEV_TYPE_PRE_CC3200R - Pre-Production CC3200R +//! -\b PRCM_DEV_TYPE_PRE_CC3200F - Pre-Production CC3200F +//! -\b PRCM_DEV_TYPE_PRE_CC3200Z - Pre-Production CC3200Z +//! -\b PRCM_DEV_TYPE_CC3200R - Production CC3200R +//! -\b PRCM_DEV_TYPE_PRE_CC3220R - Pre-Production CC3220R +//! -\b PRCM_DEV_TYPE_PRE_CC3220F - Pre-Production CC3220F +//! -\b PRCM_DEV_TYPE_PRE_CC3220Z - Pre-Production CC3220Z +//! -\b PRCM_DEV_TYPE_CC3220R - Production CC3220R +//! -\b PRCM_DEV_TYPE_PRE_CC3220RS - Pre-Production CC3220RS +//! -\b PRCM_DEV_TYPE_PRE_CC3220FS - Pre-Production CC3220FS +//! -\b PRCM_DEV_TYPE_PRE_CC3220ZS - Pre-Production CC3220ZS +//! -\b PRCM_DEV_TYPE_CC3220RS - Production CC3220RS +//! -\b PRCM_DEV_TYPE_CC3220FS - Production CC3220FS +//! +//! \return Returns, bit-packed value representing the device type, +//! or 0 if device is unknown +// +//***************************************************************************** +unsigned long PRCMDeviceTypeGet() +{ + unsigned long ulDevType; + unsigned long ulChipId; + unsigned long ulDevMajorVer; + unsigned long ulDevMinorVer; + + // + // Read the device identification register + // + ulChipId = HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); + + // + // Read the ROM mojor and minor version + // + ulDevMajorVer = ((ulChipId >> 28) & 0xF); + ulDevMinorVer = ((ulChipId >> 24) & 0xF); + + + ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); + + // + // Get the device variant from the chip id + // + switch((ulChipId & 0xF)) + { + // + // It is R variant + // + case 0x0: + ulDevType = PRCM_DEV_TYPE_FLAG_R; + break; + + // + // It is F variant, non secure F variant is always Pre-Production + // + case 0x1: + ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_PRE_PROD; + break; + + // + // It is Z variant and is always Pre-Production + // + case 0x3: + ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_PRE_PROD; + break; + + // + // It is Secure R + // + case 0x8: + ulDevType = PRCM_DEV_TYPE_FLAG_R|PRCM_DEV_TYPE_FLAG_SECURE; + break; + + // + // It is Secure F + // + case 0x9: + ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_SECURE; + break; + + // + // It is secure Z variant and variant is always Pre-Production + // + case 0xB: + ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_SECURE| + PRCM_DEV_TYPE_FLAG_PRE_PROD; + break; + + // + // Undefined variant + // + default: + ulDevType = 0x0; + } + + if( ulDevType != 0 ) + { + if( ulDevMajorVer == 0x3 ) + { + ulDevType |= PRCM_DEV_TYPE_FLAG_3220; + } + else if( ulDevMajorVer == 0x2 ) + { + ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220); + + if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0) ) + { + if(ulDevMinorVer == 0x0) + { + ulDevType |= PRCM_DEV_TYPE_FLAG_REV1; + } + else + { + ulDevType |= PRCM_DEV_TYPE_FLAG_REV2; + } + } + else + { + if(ulDevMinorVer == 0x1) + { + ulDevType |= PRCM_DEV_TYPE_FLAG_REV1; + } + } + } + else + { + if(ulDevMinorVer == 0x4) + { + if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0)) + { + ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220); + } + else + { + ulDevType |= PRCM_DEV_TYPE_FLAG_3200; + } + } + else + { + ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3200); + } + } + } + + + return ulDevType; +} + + + +//**************************************************************************** +// +//! Used to trigger a hibernate cycle for the device using RTC +//! +//! This API can be used to do a clean reboot of device. +//! +//! \note This routine should only be exercised after all the network processing +//! has been stopped. To stop network processing use \b sl_stop API from +//! simplelink library. +//! +//! \return None +// +//**************************************************************************** +void PRCMHibernateCycleTrigger() +{ + unsigned long ulRegValue; + unsigned long long ullRTCVal; + + // + // Read the RTC register + // + ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); + + // + // Enable the RTC as wakeup source if specified + // + ulRegValue |= (PRCM_HIB_SLOW_CLK_CTR & 0x1); + + // + // Enable HIB wakeup sources + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); + + // + // Latch the RTC vlaue + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1); + + // + // Read latched values as 2 32-bit vlaues + // + ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW); + ullRTCVal = ullRTCVal << 32; + ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW); + + // + //Considering worst case execution times of ROM,RAM,Flash value of 160 is used + // + ullRTCVal = ullRTCVal + 160; + + // + // Set RTC match value + // + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF, + (unsigned long)(ullRTCVal)); + PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF, + (unsigned long)(ullRTCVal>>32)); + // + // Note : Any addition of code after this line would need a change in + // ullTicks Interval currently set to 160 + // + + // + // Request hibernate. + // + PRCMHIBRegWrite((HIB3P3_BASE+HIB3P3_O_MEM_HIB_REQ),0x1); + + // + // Wait for system to enter hibernate + // + __asm(" wfi\n"); + + // + // Infinite loop + // + while(1) + { + + } +} + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.h new file mode 100755 index 00000000000..73785aa9756 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.h @@ -0,0 +1,368 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// prcm.h +// +// Prototypes for the PRCM control driver. +// +//***************************************************************************** + +#ifndef __PRCM_H__ +#define __PRCM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Peripheral clock and reset control registers +// +//***************************************************************************** +typedef struct _PRCM_PeripheralRegs_ +{ + +unsigned long ulClkReg; +unsigned long ulRstReg; + +}PRCM_PeriphRegs_t; + +//***************************************************************************** +// Values that can be passed to PRCMPeripheralEnable() and +// PRCMPeripheralDisable() +//***************************************************************************** +#define PRCM_RUN_MODE_CLK 0x00000001 +#define PRCM_SLP_MODE_CLK 0x00000100 + +//***************************************************************************** +// Values that can be passed to PRCMSRAMRetentionEnable() and +// PRCMSRAMRetentionDisable() as ulSramColSel. +//***************************************************************************** +#define PRCM_SRAM_COL_1 0x00000001 +#define PRCM_SRAM_COL_2 0x00000002 +#define PRCM_SRAM_COL_3 0x00000004 +#define PRCM_SRAM_COL_4 0x00000008 + +//***************************************************************************** +// Values that can be passed to PRCMSRAMRetentionEnable() and +// PRCMSRAMRetentionDisable() as ulModeFlags. +//***************************************************************************** +#define PRCM_SRAM_LPDS_RET 0x00000002 + +//***************************************************************************** +// Values that can be passed to PRCMLPDSWakeupSourceEnable(), +// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable(). +//***************************************************************************** +#define PRCM_LPDS_HOST_IRQ 0x00000080 +#define PRCM_LPDS_GPIO 0x00000010 +#define PRCM_LPDS_TIMER 0x00000001 + +//***************************************************************************** +// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type +//***************************************************************************** +#define PRCM_LPDS_LOW_LEVEL 0x00000002 +#define PRCM_LPDS_HIGH_LEVEL 0x00000000 +#define PRCM_LPDS_FALL_EDGE 0x00000001 +#define PRCM_LPDS_RISE_EDGE 0x00000003 + +//***************************************************************************** +// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() +//***************************************************************************** +#define PRCM_LPDS_GPIO2 0x00000000 +#define PRCM_LPDS_GPIO4 0x00000001 +#define PRCM_LPDS_GPIO13 0x00000002 +#define PRCM_LPDS_GPIO17 0x00000003 +#define PRCM_LPDS_GPIO11 0x00000004 +#define PRCM_LPDS_GPIO24 0x00000005 +#define PRCM_LPDS_GPIO26 0x00000006 + +//***************************************************************************** +// Values that can be passed to PRCMHibernateWakeupSourceEnable(), +// PRCMHibernateWakeupSourceDisable(). +//***************************************************************************** +#define PRCM_HIB_SLOW_CLK_CTR 0x00000001 + +//***************************************************************************** +// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType +//***************************************************************************** +#define PRCM_HIB_LOW_LEVEL 0x00000000 +#define PRCM_HIB_HIGH_LEVEL 0x00000001 +#define PRCM_HIB_FALL_EDGE 0x00000002 +#define PRCM_HIB_RISE_EDGE 0x00000003 + +//***************************************************************************** +// Values that can be passed to PRCMHibernateWakeupSourceEnable(), +// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect() +//***************************************************************************** +#define PRCM_HIB_GPIO2 0x00010000 +#define PRCM_HIB_GPIO4 0x00020000 +#define PRCM_HIB_GPIO13 0x00040000 +#define PRCM_HIB_GPIO17 0x00080000 +#define PRCM_HIB_GPIO11 0x00100000 +#define PRCM_HIB_GPIO24 0x00200000 +#define PRCM_HIB_GPIO26 0x00400000 + +//***************************************************************************** +// Values that will be returned from PRCMSysResetCauseGet(). +//***************************************************************************** +#define PRCM_POWER_ON 0x00000000 +#define PRCM_LPDS_EXIT 0x00000001 +#define PRCM_CORE_RESET 0x00000003 +#define PRCM_MCU_RESET 0x00000004 +#define PRCM_WDT_RESET 0x00000005 +#define PRCM_SOC_RESET 0x00000006 +#define PRCM_HIB_EXIT 0x00000007 + +//***************************************************************************** +// Values that can be passed to PRCMHibernateWakeupCauseGet(). +//***************************************************************************** +#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002 +#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004 + +//***************************************************************************** +// Values that can be passed to PRCMSEnableInterrupt +//***************************************************************************** +#define PRCM_INT_SLOW_CLK_CTR 0x00004000 + +//***************************************************************************** +// Values that can be passed to PRCMPeripheralClkEnable(), +// PRCMPeripheralClkDisable(), PRCMPeripheralReset() +//***************************************************************************** +#define PRCM_CAMERA 0x00000000 +#define PRCM_I2S 0x00000001 +#define PRCM_SDHOST 0x00000002 +#define PRCM_GSPI 0x00000003 +#define PRCM_LSPI 0x00000004 +#define PRCM_UDMA 0x00000005 +#define PRCM_GPIOA0 0x00000006 +#define PRCM_GPIOA1 0x00000007 +#define PRCM_GPIOA2 0x00000008 +#define PRCM_GPIOA3 0x00000009 +#define PRCM_GPIOA4 0x0000000A +#define PRCM_WDT 0x0000000B +#define PRCM_UARTA0 0x0000000C +#define PRCM_UARTA1 0x0000000D +#define PRCM_TIMERA0 0x0000000E +#define PRCM_TIMERA1 0x0000000F +#define PRCM_TIMERA2 0x00000010 +#define PRCM_TIMERA3 0x00000011 +#define PRCM_DTHE 0x00000012 +#define PRCM_SSPI 0x00000013 +#define PRCM_I2CA0 0x00000014 +// Note : PRCM_ADC is a dummy define for pinmux utility code generation +// PRCM_ADC should never be used in any user code. +#define PRCM_ADC 0x000000FF + + +//***************************************************************************** +// Values that can be passed to PRCMIORetEnable() and PRCMIORetDisable() +//***************************************************************************** +#define PRCM_IO_RET_GRP_0 0x00000001 +#define PRCM_IO_RET_GRP_1 0x00000002 +#define PRCM_IO_RET_GRP_2 0x00000004 +#define PRCM_IO_RET_GRP_3 0x00000008 + +//***************************************************************************** +// Macros definig the device type +//***************************************************************************** +#define PRCM_DEV_TYPE_FLAG_R 0x00000001 +#define PRCM_DEV_TYPE_FLAG_F 0x00000002 +#define PRCM_DEV_TYPE_FLAG_Z 0x00000004 +#define PRCM_DEV_TYPE_FLAG_SECURE 0x00000008 +#define PRCM_DEV_TYPE_FLAG_PRE_PROD 0x00000010 +#define PRCM_DEV_TYPE_FLAG_3200 0x00000020 +#define PRCM_DEV_TYPE_FLAG_3220 0x00000040 +#define PRCM_DEV_TYPE_FLAG_REV1 0x00010000 +#define PRCM_DEV_TYPE_FLAG_REV2 0x00020000 + +//***************************************************************************** +// Pre-defined helper macros +//***************************************************************************** +#define PRCM_DEV_TYPE_PRE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3200| \ + PRCM_DEV_TYPE_FLAG_R) + +#define PRCM_DEV_TYPE_PRE_CC3200F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3200| \ + PRCM_DEV_TYPE_FLAG_F) + +#define PRCM_DEV_TYPE_PRE_CC3200Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3200| \ + PRCM_DEV_TYPE_FLAG_Z) + +#define PRCM_DEV_TYPE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3200| \ + PRCM_DEV_TYPE_FLAG_R) + +#define PRCM_DEV_TYPE_PRE_CC3220R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_R) + +#define PRCM_DEV_TYPE_PRE_CC3220F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_F) + +#define PRCM_DEV_TYPE_PRE_CC3220Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_Z) + +#define PRCM_DEV_TYPE_CC3220R (PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_R) + + +#define PRCM_DEV_TYPE_PRE_CC3220RS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_R| \ + PRCM_DEV_TYPE_FLAG_SECURE) + +#define PRCM_DEV_TYPE_PRE_CC3220FS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_F| \ + PRCM_DEV_TYPE_FLAG_SECURE) + +#define PRCM_DEV_TYPE_PRE_CC3220ZS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_Z| \ + PRCM_DEV_TYPE_FLAG_SECURE) + +#define PRCM_DEV_TYPE_CC3220RS (PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_R| \ + PRCM_DEV_TYPE_FLAG_SECURE) + +#define PRCM_DEV_TYPE_CC3220FS (PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_F| \ + PRCM_DEV_TYPE_FLAG_SECURE) + + +#define PRCM_DEV_TYPE_PRE_CC3220Z1 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_Z| \ + PRCM_DEV_TYPE_FLAG_REV1) + +#define PRCM_DEV_TYPE_PRE_CC3220Z2 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ + PRCM_DEV_TYPE_FLAG_3220| \ + PRCM_DEV_TYPE_FLAG_Z| \ + PRCM_DEV_TYPE_FLAG_REV2) + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PRCMMCUReset(tBoolean bIncludeSubsystem); +extern unsigned long PRCMSysResetCauseGet(void); + +extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral, + unsigned long ulClkFlags); +extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral, + unsigned long ulClkFlags); +extern void PRCMPeripheralReset(unsigned long ulPeripheral); +extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral); + +extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq); +extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral); + +extern void PRCMSleepEnter(void); + +extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel, + unsigned long ulFlags); +extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel, + unsigned long ulFlags); +extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP, + unsigned long ulRestorePC); +extern void PRCMLPDSEnter(void); +extern void PRCMLPDSIntervalSet(unsigned long ulTicks); +extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc); +extern unsigned long PRCMLPDSWakeupCauseGet(void); +extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, + unsigned long ulType); +extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc); + +extern void PRCMHibernateEnter(void); +extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc); +extern unsigned long PRCMHibernateWakeupCauseGet(void); +extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap, + unsigned long ulType); +extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc); +extern void PRCMHibernateIntervalSet(unsigned long long ullTicks); + +extern unsigned long long PRCMSlowClkCtrGet(void); +extern unsigned long long PRCMSlowClkCtrFastGet(void); +extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks); +extern unsigned long long PRCMSlowClkCtrMatchGet(void); + +extern void PRCMOCRRegisterWrite(unsigned char ucIndex, + unsigned long ulRegValue); +extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex); + +extern void PRCMIntRegister(void (*pfnHandler)(void)); +extern void PRCMIntUnregister(void); +extern void PRCMIntEnable(unsigned long ulIntFlags); +extern void PRCMIntDisable(unsigned long ulIntFlags); +extern unsigned long PRCMIntStatus(void); +extern void PRCMRTCInUseSet(void); +extern tBoolean PRCMRTCInUseGet(void); +extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec); +extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec); +extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec); +extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec); +extern void PRCMCC3200MCUInit(void); +extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr); +extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue); +extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider, + unsigned char ulWidth); +extern void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags); +extern void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags); +extern unsigned long PRCMDeviceTypeGet(void); +extern void PRCMLPDSEnterKeepDebugIf(void); +extern void PRCMHibernateCycleTrigger(void); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PRCM_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom.h new file mode 100755 index 00000000000..cac74cdde17 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom.h @@ -0,0 +1,2787 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// +//***************************************************************************** +// +// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND. +// +//***************************************************************************** + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// For backward compatibility with older Driverlib versions +// +//***************************************************************************** +#ifdef TARGET_IS_CC3200 +#define USE_CC3200_ROM_DRV_API +#endif + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((unsigned long *)0x0000040C) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) +#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[2])) +#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[3])) +#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[4])) +#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[5])) +#define ROM_PRCMTABLE ((unsigned long *)(ROM_APITABLE[6])) +#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[7])) +#define ROM_SPITABLE ((unsigned long *)(ROM_APITABLE[8])) +#define ROM_CAMERATABLE ((unsigned long *)(ROM_APITABLE[9])) +#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[10])) +#define ROM_PINTABLE ((unsigned long *)(ROM_APITABLE[11])) +#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[12])) +#define ROM_UTILSTABLE ((unsigned long *)(ROM_APITABLE[13])) +#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[14])) +#define ROM_HWSPINLOCKTABLE ((unsigned long *)(ROM_APITABLE[15])) +#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[16])) +#define ROM_AESTABLE ((unsigned long *)(ROM_APITABLE[17])) +#define ROM_DESTABLE ((unsigned long *)(ROM_APITABLE[18])) +#define ROM_SHAMD5TABLE ((unsigned long *)(ROM_APITABLE[19])) +#define ROM_CRCTABLE ((unsigned long *)(ROM_APITABLE[20])) +#define ROM_SDHOSTTABLE ((unsigned long *)(ROM_APITABLE[21])) +#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[22])) +#define ROM_CPUTABLE ((unsigned long *)(ROM_APITABLE[23])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntEnable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntMasterEnable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntMasterDisable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntDisable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityGroupingGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPrioritySet \ + ((void (*)(unsigned long ulInterrupt, \ + unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityGet \ + ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPendSet \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPendClear \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityMaskSet \ + ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntPriorityMaskGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntRegister \ + ((void (*)(unsigned long ulInterrupt, \ + void (*pfnHandler)(void)))ROM_INTERRUPTTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntUnregister \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_IntVTableBaseSet \ + ((void (*)(unsigned long ulVtableBase))ROM_INTERRUPTTABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_TIMERTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerControlLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bInvert))ROM_TIMERTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerControlEvent \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulEvent))ROM_TIMERTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerControlStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bStall))ROM_TIMERTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerPrescaleSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerPrescaleGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerPrescaleMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerLoadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerLoadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntRegister \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + void (*pfnHandler)(void)))ROM_TIMERTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntUnregister \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_TIMERTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerValueSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[22]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerDMAEventSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAEvent))ROM_TIMERTABLE[23]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_TimerDMAEventGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_TIMERTABLE[24]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTParityModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulParity))ROM_UARTTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTParityModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulRxLevel))ROM_UARTTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulTxLevel, \ + unsigned long *pulRxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long ulBaud, \ + unsigned long ulConfig))ROM_UARTTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long *pulBaud, \ + unsigned long *pulConfig))ROM_UARTTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFIFOEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFIFODisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharsAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharGetNonBlocking \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharGet \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharPutNonBlocking \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTCharPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTBreakCtl \ + ((void (*)(unsigned long ulBase, \ + tBoolean bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntRegister \ + ((void (*)(unsigned long ulBase, \ + void(*pfnHandler)(void)))ROM_UARTTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_UARTTABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[23]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[24]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[25]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTRxErrorGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[26]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTRxErrorClear \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[27]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTModemControlSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulControl))ROM_UARTTABLE[28]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTModemControlClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulControl))ROM_UARTTABLE[29]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTModemControlGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[30]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTModemStatusGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[31]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFlowControlSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_UARTTABLE[32]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTFlowControlGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[33]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTTxIntModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_UARTTABLE[34]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UARTTxIntModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[35]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the uDMA API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(unsigned long ulChannelStructIndex, \ + unsigned long ulMode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + unsigned long ulTransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAErrorStatusGet \ + ((unsigned long (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelEnable \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelDisable \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelIsEnabled \ + ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelRequest \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned long ulAttr))ROM_UDMATABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned long ulAttr))ROM_UDMATABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelAttributeGet \ + ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelControlSet \ + ((void (*)(unsigned long ulChannelStructIndex, \ + unsigned long ulControl))ROM_UDMATABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelSizeGet \ + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelModeGet \ + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAIntStatus \ + ((unsigned long (*)(void))ROM_UDMATABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAIntClear \ + ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned ulTaskCount, \ + void *pvTaskList, \ + unsigned long ulIsPeriphSG))ROM_UDMATABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAChannelAssign \ + ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAIntRegister \ + ((void (*)(unsigned long ulIntChannel, \ + void (*pfnHandler)(void)))ROM_UDMATABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_uDMAIntUnregister \ + ((void (*)(unsigned long ulIntChannel))ROM_UDMATABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogIntClear \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogRunning \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogLock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogUnlock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogLockState \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogReloadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLoadVal))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogReloadGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogValueGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogStallEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogStallDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogIntRegister \ + ((void (*)(unsigned long ulBase, \ + void(*pfnHandler)(void)))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_WatchdogIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CIntRegister \ + ((void (*)(uint32_t ui32Base, \ + void(pfnHandler)(void)))ROM_I2CTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CIntUnregister \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CTxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CTxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CRxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CRxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFOStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFODataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFODataPutNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFODataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CFIFODataGetNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t *pui8Data))ROM_I2CTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterBurstLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Length))ROM_I2CTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterBurstCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterGlitchFilterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveFIFOEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterBusBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Cmd))ROM_I2CTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[24]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[25]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[26]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[27]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[28]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[30]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[31]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Value))ROM_I2CTABLE[32]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_I2CTABLE[33]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(uint32_t ui32Base, \ + bool bACK))ROM_I2CTABLE[34]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterLineStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[35]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr, \ + bool bReceive))ROM_I2CTABLE[36]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[37]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[38]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[39]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveInit \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[41]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8AddrNum, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[42]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[44]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[45]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[46]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[47]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[48]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[49]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[50]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CSlaveStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[51]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32I2CClk, \ + bool bFast))ROM_I2CTABLE[52]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SPI API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIEnable \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDisable \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIReset \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSPIClk, \ + unsigned long ulBitRate, \ + unsigned long ulMode, \ + unsigned long ulSubMode, \ + unsigned long ulConfig))ROM_SPITABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long * pulData))ROM_SPITABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SPITABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SPITABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SPITABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIFIFOEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_SPITABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIFIFODisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_SPITABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIFIFOLevelSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulRxLevel))ROM_SPITABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIFIFOLevelGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulTxLevel, \ + unsigned long *pulRxLevel))ROM_SPITABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIWordCountSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulWordCount))ROM_SPITABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntRegister \ + ((void (*)(unsigned long ulBase, \ + void(*pfnHandler)(void)))ROM_SPITABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SPITABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SPITABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_SPITABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SPITABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDmaEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_SPITABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPIDmaDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_SPITABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPICSEnable \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPICSDisable \ + ((void (*)(unsigned long ulBase))ROM_SPITABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SPITransfer \ + ((long (*)(unsigned long ulBase, \ + unsigned char *ucDout, \ + unsigned char *ucDin, \ + unsigned long ulSize, \ + unsigned long ulFlags))ROM_SPITABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CAM API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraReset \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraParamsConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulHSPol, \ + unsigned long ulVSPol, \ + unsigned long ulFlags))ROM_CAMERATABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraXClkConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCamClkIn, \ + unsigned long ulXClk))ROM_CAMERATABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraXClkSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char bXClkFlags))ROM_CAMERATABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraDMAEnable \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraDMADisable \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraThresholdSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulThreshold))ROM_CAMERATABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntRegister \ + ((void (*)(unsigned long ulBase, \ + void (*pfnHandler)(void)))ROM_CAMERATABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CAMERATABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CAMERATABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_CAMERATABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CAMERATABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraCaptureStop \ + ((void (*)(unsigned long ulBase, \ + tBoolean bImmediate))ROM_CAMERATABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraCaptureStart \ + ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CameraBufferRead \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pBuffer, \ + unsigned char ucSize))ROM_CAMERATABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the FLASH API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashDisable \ + ((void (*)(void))ROM_FLASHTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashErase \ + ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashMassErase \ + ((long (*)(void))ROM_FLASHTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashMassEraseNonBlocking \ + ((void (*)(void))ROM_FLASHTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashEraseNonBlocking \ + ((void (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashProgram \ + ((long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_FLASHTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashProgramNonBlocking \ + ((long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_FLASHTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntRegister \ + ((void (*)(void (*pfnHandler)(void)))ROM_FLASHTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntUnregister \ + ((void (*)(void))ROM_FLASHTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Pin API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinModeSet \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinDirModeSet \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinIO))ROM_PINTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinDirModeGet \ + ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinModeGet \ + ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinConfigGet \ + ((void (*)(unsigned long ulPin, \ + unsigned long *pulPinStrength, \ + unsigned long *pulPinType))ROM_PINTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinConfigSet \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinStrength, \ + unsigned long ulPinType))ROM_PINTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeUART \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeI2C \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeSPI \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeI2S \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeTimer \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeCamera \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeGPIO \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode, \ + tBoolean bOpenDrain))ROM_PINTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeADC \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinTypeSDHost \ + ((void (*)(unsigned long ulPin, \ + unsigned long ulPinMode))ROM_PINTABLE[14]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinHysteresisSet \ + ((void (*)(unsigned long ulHysteresis))ROM_PINTABLE[15]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinLockLevelSet \ + ((void (*)(unsigned long ulPin, \ + unsigned char ucLevel))ROM_PINTABLE[16]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinLock \ + ((void (*)(unsigned long ulOutEnable))ROM_PINTABLE[17]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PinUnlock \ + ((void (*)(void))ROM_PINTABLE[18]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SYSTICK API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickIntRegister \ + ((void (*)(void (*pfnHandler)(void)))ROM_SYSTICKTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickIntUnregister \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickPeriodSet \ + ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickPeriodGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SysTickValueGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[8]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UTILS API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_UtilsDelay \ + ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2S API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_I2STABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long ulData))ROM_I2STABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long ulData))ROM_I2STABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long *pulData))ROM_I2STABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long *pulData))ROM_I2STABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulI2SClk, \ + unsigned long ulBitClk, \ + unsigned long ulConfig))ROM_I2STABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2STxFIFOEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulWordsPerTransfer))ROM_I2STABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2STxFIFODisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SRxFIFOEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRxLevel, \ + unsigned long ulWordsPerTransfer))ROM_I2STABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SRxFIFODisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2STxFIFOStatusGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SRxFIFOStatusGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SSerializerConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDataLine, \ + unsigned long ulSerMode, \ + unsigned long ulInActState))ROM_I2STABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntRegister \ + ((void (*)(unsigned long ulBase, \ + void (*pfnHandler)(void)))ROM_I2STABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[19]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2STxActiveSlotSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulActSlot))ROM_I2STABLE[20]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_I2SRxActiveSlotSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulActSlot))ROM_I2STABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIODirModeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulPinIO))ROM_GPIOTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIODirModeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntTypeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulIntType))ROM_GPIOTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntTypeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned long ulIntFlags))ROM_GPIOTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned long ulIntFlags))ROM_GPIOTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntStatus \ + ((long (*)(unsigned long ulPort, \ + tBoolean bMasked))ROM_GPIOTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntClear \ + ((void (*)(unsigned long ulPort, \ + unsigned long ulIntFlags))ROM_GPIOTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntRegister \ + ((void (*)(unsigned long ulPort, \ + void (*pfnIntHandler)(void)))ROM_GPIOTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOIntUnregister \ + ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOPinRead \ + ((long (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_GPIOPinWrite \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned char ucVal))ROM_GPIOTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the AES API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_AESTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESKey1Set \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESKey2Set \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESKey3Set \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key))ROM_AESTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIVSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8IVdata))ROM_AESTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESTagRead \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8TagData))ROM_AESTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Length))ROM_AESTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESAuthDataLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_AESTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest, \ + uint8_t ui8Length))ROM_AESTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest, \ + uint8_t ui8Length))ROM_AESTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t ui8Length))ROM_AESTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t ui8Length))ROM_AESTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t *pui8Dest, \ + uint32_t ui32Length))ROM_AESTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataMAC \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint32_t ui32Length, \ + uint8_t *pui8Tag))ROM_AESTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDataProcessAE \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t *pui8Dest, \ + uint32_t ui32Length, \ + uint8_t *pui8AuthSrc, \ + uint32_t ui32AuthLength, \ + uint8_t *pui8Tag))ROM_AESTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_AESTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntRegister \ + ((void (*)(uint32_t ui32Base, \ + void(*pfnHandler)(void)))ROM_AESTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIntUnregister \ + ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[22]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_AESIVGet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8IVdata))ROM_AESTABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the DES API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_DESTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest, \ + uint8_t ui8Length))ROM_DESTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest, \ + uint8_t ui8Length))ROM_DESTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t *pui8Dest, \ + uint32_t ui32Length))ROM_DESTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t ui8Length))ROM_DESTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src, \ + uint8_t ui8Length))ROM_DESTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntRegister \ + ((void (*)(uint32_t ui32Base, \ + void(*pfnHandler)(void)))ROM_DESTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_DESTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIntUnregister \ + ((void (*)(uint32_t ui32Base))ROM_DESTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESIVSet \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8IVdata))ROM_DESTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key))ROM_DESTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_DESDataLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_DESTABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SHAMD5 API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5ConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SHAMD5TABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8DataSrc, \ + uint32_t ui32DataLength, \ + uint8_t *pui8HashResult))ROM_SHAMD5TABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src))ROM_SHAMD5TABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8Src))ROM_SHAMD5TABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DMADisable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DMAEnable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5DataLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_SHAMD5TABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5HMACKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src))ROM_SHAMD5TABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5HMACPPKeyGenerate \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Key, \ + uint8_t *pui8PPKey))ROM_SHAMD5TABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5HMACPPKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Src))ROM_SHAMD5TABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5HMACProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint8_t *pui8DataSrc, \ + uint32_t ui32DataLength, \ + uint8_t *pui8HashResult))ROM_SHAMD5TABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntRegister \ + ((void (*)(uint32_t ui32Base, \ + void(*pfnHandler)(void)))ROM_SHAMD5TABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SHAMD5TABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5IntUnregister \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SHAMD5ResultRead \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8Dest))ROM_SHAMD5TABLE[17]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CRC API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCDataProcess \ + ((uint32_t (*)(uint32_t ui32Base, \ + void *puiDataIn, \ + uint32_t ui32DataLength, \ + uint32_t ui32Config))ROM_CRCTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_CRCTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCResultRead \ + ((uint32_t (*)(uint32_t ui32Base))ROM_CRCTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_CRCSeedSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seed))ROM_CRCTABLE[4]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SDHOST API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostCmdReset \ + ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostInit \ + ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostCmdSend \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulCmd, \ + unsigned ulArg))ROM_SDHOSTTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntRegister \ + ((void (*)(unsigned long ulBase, \ + void (*pfnHandler)(void)))ROM_SDHOSTTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntUnregister \ + ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SDHOSTTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SDHOSTTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SDHOSTTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostRespGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRespnse[4]))ROM_SDHOSTTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostBlockSizeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned short ulBlkSize))ROM_SDHOSTTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostBlockCountSet \ + ((void (*)(unsigned long ulBase, \ + unsigned short ulBlkCount))ROM_SDHOSTTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostDataNonBlockingWrite \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SDHOSTTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostDataNonBlockingRead \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SDHOSTTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostDataWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SDHOSTTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostDataRead \ + ((void (*)(unsigned long ulBase, \ + unsigned long *ulData))ROM_SDHOSTTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSDHostClk, \ + unsigned long ulCardClk))ROM_SDHOSTTABLE[17]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostCardErrorMaskSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulErrMask))ROM_SDHOSTTABLE[18]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_SDHostCardErrorMaskGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[19]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PRCM API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMMCUReset \ + ((void (*)(tBoolean bIncludeSubsystem))ROM_PRCMTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSysResetCauseGet \ + ((unsigned long (*)(void))ROM_PRCMTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralClkEnable \ + ((void (*)(unsigned long ulPeripheral, \ + unsigned long ulClkFlags))ROM_PRCMTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralClkDisable \ + ((void (*)(unsigned long ulPeripheral, \ + unsigned long ulClkFlags))ROM_PRCMTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralReset \ + ((void (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralStatusGet \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMI2SClockFreqSet \ + ((void (*)(unsigned long ulI2CClkFreq))ROM_PRCMTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMPeripheralClockGet \ + ((unsigned long (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSleepEnter \ + ((void (*)(void))ROM_PRCMTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSRAMRetentionEnable \ + ((void (*)(unsigned long ulSramColSel, \ + unsigned long ulFlags))ROM_PRCMTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSRAMRetentionDisable \ + ((void (*)(unsigned long ulSramColSel, \ + unsigned long ulFlags))ROM_PRCMTABLE[12]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSEnter \ + ((void (*)(void))ROM_PRCMTABLE[13]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSIntervalSet \ + ((void (*)(unsigned long ulTicks))ROM_PRCMTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSWakeupSourceEnable \ + ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSWakeupCauseGet \ + ((unsigned long (*)(void))ROM_PRCMTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSWakeUpGPIOSelect \ + ((void (*)(unsigned long ulGPIOPin, \ + unsigned long ulType))ROM_PRCMTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSWakeupSourceDisable \ + ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateEnter \ + ((void (*)(void))ROM_PRCMTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateWakeupSourceEnable \ + ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[20]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateWakeupCauseGet \ + ((unsigned long (*)(void))ROM_PRCMTABLE[21]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateWakeUpGPIOSelect \ + ((void (*)(unsigned long ulMultiGPIOBitMap, \ + unsigned long ulType))ROM_PRCMTABLE[22]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateWakeupSourceDisable \ + ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[23]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateIntervalSet \ + ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[24]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSlowClkCtrGet \ + ((unsigned long long (*)(void))ROM_PRCMTABLE[25]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSlowClkCtrMatchSet \ + ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[26]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSlowClkCtrMatchGet \ + ((unsigned long long (*)(void))ROM_PRCMTABLE[27]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMOCRRegisterWrite \ + ((void (*)(unsigned char ucIndex, \ + unsigned long ulRegValue))ROM_PRCMTABLE[28]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMOCRRegisterRead \ + ((unsigned long (*)(unsigned char ucIndex))ROM_PRCMTABLE[29]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntRegister \ + ((void (*)(void (*pfnHandler)(void)))ROM_PRCMTABLE[30]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntUnregister \ + ((void (*)(void))ROM_PRCMTABLE[31]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[32]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[33]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIntStatus \ + ((unsigned long (*)(void))ROM_PRCMTABLE[34]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCInUseSet \ + ((void (*)(void))ROM_PRCMTABLE[35]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCInUseGet \ + ((tBoolean (*)(void))ROM_PRCMTABLE[36]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCSet \ + ((void (*)(unsigned long ulSecs, \ + unsigned short usMsec))ROM_PRCMTABLE[37]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCGet \ + ((void (*)(unsigned long *ulSecs, \ + unsigned short *usMsec))ROM_PRCMTABLE[38]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCMatchSet \ + ((void (*)(unsigned long ulSecs, \ + unsigned short usMsec))ROM_PRCMTABLE[39]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMRTCMatchGet \ + ((void (*)(unsigned long *ulSecs, \ + unsigned short *usMsec))ROM_PRCMTABLE[40]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSRestoreInfoSet \ + ((void (*)(unsigned long ulRestoreSP, \ + unsigned long ulRestorePC))ROM_PRCMTABLE[41]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMSlowClkCtrFastGet \ + ((unsigned long long (*)(void))ROM_PRCMTABLE[42]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMCC3200MCUInit \ + ((void (*)(void))ROM_PRCMTABLE[43]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHIBRegRead \ + ((unsigned long (*)(unsigned long ulRegAddr))ROM_PRCMTABLE[44]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHIBRegWrite \ + ((void (*)(unsigned long ulRegAddr, \ + unsigned long ulValue))ROM_PRCMTABLE[45]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMCameraFreqSet \ + ((unsigned long (*)(unsigned char ulDivider, \ + unsigned char ulWidth))ROM_PRCMTABLE[46]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIORetentionEnable \ + ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[47]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMIORetentionDisable \ + ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[48]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMDeviceTypeGet \ + ((unsigned long (*)(void))ROM_PRCMTABLE[49]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMLPDSEnterKeepDebugIf \ + ((void (*)(void))ROM_PRCMTABLE[50]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_PRCMHibernateCycleTrigger \ + ((void (*)(void))ROM_PRCMTABLE[51]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the HWSPINLOCK API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_HwSpinLockAcquire \ + ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_HwSpinLockTryAcquire \ + ((int32_t (*)(uint32_t ui32LockID, \ + uint32_t ui32Retry))ROM_HWSPINLOCKTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_HwSpinLockRelease \ + ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_HwSpinLockTest \ + ((uint32_t (*)(uint32_t ui32LockID, \ + bool bCurrentStatus))ROM_HWSPINLOCKTABLE[3]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCEnable \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[0]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCDisable \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[1]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCChannelEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[2]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCChannelDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[3]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntRegister \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + void (*pfnHandler)(void)))ROM_ADCTABLE[4]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntUnregister \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[5]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulIntFlags))ROM_ADCTABLE[6]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulIntFlags))ROM_ADCTABLE[7]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[8]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulIntFlags))ROM_ADCTABLE[9]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[10]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[11]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulValue))ROM_ADCTABLE[14]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerEnable \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[15]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerDisable \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[16]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerReset \ + ((void (*)(unsigned long ulBase))ROM_ADCTABLE[17]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCTimerValueGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[18]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCFIFOLvlGet \ + ((unsigned char (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[19]) +#endif +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define ROM_ADCFIFORead \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_ADCTABLE[20]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CPU API. +// +//***************************************************************************** +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUcpsid \ + ((unsigned long (*)(void))ROM_CPUTABLE[0]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUcpsie \ + ((unsigned long (*)(void))ROM_CPUTABLE[1]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUprimask \ + ((unsigned long (*)(void))ROM_CPUTABLE[2]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUwfi \ + ((void (*)(void))ROM_CPUTABLE[3]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUbasepriGet \ + ((unsigned long (*)(void))ROM_CPUTABLE[4]) +#endif +#if defined(USE_CC3220_ROM_DRV_API) +#define ROM_CPUbasepriSet \ + ((void (*)(unsigned long ulNewBasepri))ROM_CPUTABLE[5]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions Directly. +// +//***************************************************************************** +#define ROM_UtilsDelayDirect \ + ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0]) + +#define ROM_PRCMLPDSEnterDirect \ + ((void (*)(void))ROM_PRCMTABLE[13]) + +#define ROM_PRCMLPDSEnterKeepDebugIfDirect \ + ((void (*)(void))ROM_PRCMTABLE[50]) + +#endif // __ROM_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_map.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_map.h new file mode 100755 index 00000000000..cb2e07e1fc5 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_map.h @@ -0,0 +1,3321 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// rom_map.h - Macros to facilitate calling functions in the ROM when they are +// available. +// +//***************************************************************************** +//***************************************************************************** +// +// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND. +// +//***************************************************************************** + +#ifndef __ROM_MAP_H__ +#define __ROM_MAP_H__ + +//***************************************************************************** +// Patched ROM APIs +//***************************************************************************** +#include "rom_patch.h" + +//***************************************************************************** +// +// Macros for the Interrupt API. +// +//***************************************************************************** +#ifdef ROM_IntEnable +#define MAP_IntEnable \ + ROM_IntEnable +#else +#define MAP_IntEnable \ + IntEnable +#endif +#ifdef ROM_IntMasterEnable +#define MAP_IntMasterEnable \ + ROM_IntMasterEnable +#else +#define MAP_IntMasterEnable \ + IntMasterEnable +#endif +#ifdef ROM_IntMasterDisable +#define MAP_IntMasterDisable \ + ROM_IntMasterDisable +#else +#define MAP_IntMasterDisable \ + IntMasterDisable +#endif +#ifdef ROM_IntDisable +#define MAP_IntDisable \ + ROM_IntDisable +#else +#define MAP_IntDisable \ + IntDisable +#endif +#ifdef ROM_IntPriorityGroupingSet +#define MAP_IntPriorityGroupingSet \ + ROM_IntPriorityGroupingSet +#else +#define MAP_IntPriorityGroupingSet \ + IntPriorityGroupingSet +#endif +#ifdef ROM_IntPriorityGroupingGet +#define MAP_IntPriorityGroupingGet \ + ROM_IntPriorityGroupingGet +#else +#define MAP_IntPriorityGroupingGet \ + IntPriorityGroupingGet +#endif +#ifdef ROM_IntPrioritySet +#define MAP_IntPrioritySet \ + ROM_IntPrioritySet +#else +#define MAP_IntPrioritySet \ + IntPrioritySet +#endif +#ifdef ROM_IntPriorityGet +#define MAP_IntPriorityGet \ + ROM_IntPriorityGet +#else +#define MAP_IntPriorityGet \ + IntPriorityGet +#endif +#ifdef ROM_IntPendSet +#define MAP_IntPendSet \ + ROM_IntPendSet +#else +#define MAP_IntPendSet \ + IntPendSet +#endif +#ifdef ROM_IntPendClear +#define MAP_IntPendClear \ + ROM_IntPendClear +#else +#define MAP_IntPendClear \ + IntPendClear +#endif +#ifdef ROM_IntPriorityMaskSet +#define MAP_IntPriorityMaskSet \ + ROM_IntPriorityMaskSet +#else +#define MAP_IntPriorityMaskSet \ + IntPriorityMaskSet +#endif +#ifdef ROM_IntPriorityMaskGet +#define MAP_IntPriorityMaskGet \ + ROM_IntPriorityMaskGet +#else +#define MAP_IntPriorityMaskGet \ + IntPriorityMaskGet +#endif +#ifdef ROM_IntRegister +#define MAP_IntRegister \ + ROM_IntRegister +#else +#define MAP_IntRegister \ + IntRegister +#endif +#ifdef ROM_IntUnregister +#define MAP_IntUnregister \ + ROM_IntUnregister +#else +#define MAP_IntUnregister \ + IntUnregister +#endif +#ifdef ROM_IntVTableBaseSet +#define MAP_IntVTableBaseSet \ + ROM_IntVTableBaseSet +#else +#define MAP_IntVTableBaseSet \ + IntVTableBaseSet +#endif + +//***************************************************************************** +// +// Macros for the Timer API. +// +//***************************************************************************** +#ifdef ROM_TimerEnable +#define MAP_TimerEnable \ + ROM_TimerEnable +#else +#define MAP_TimerEnable \ + TimerEnable +#endif +#ifdef ROM_TimerDisable +#define MAP_TimerDisable \ + ROM_TimerDisable +#else +#define MAP_TimerDisable \ + TimerDisable +#endif +#ifdef ROM_TimerConfigure +#define MAP_TimerConfigure \ + ROM_TimerConfigure +#else +#define MAP_TimerConfigure \ + TimerConfigure +#endif +#ifdef ROM_TimerControlLevel +#define MAP_TimerControlLevel \ + ROM_TimerControlLevel +#else +#define MAP_TimerControlLevel \ + TimerControlLevel +#endif +#ifdef ROM_TimerControlEvent +#define MAP_TimerControlEvent \ + ROM_TimerControlEvent +#else +#define MAP_TimerControlEvent \ + TimerControlEvent +#endif +#ifdef ROM_TimerControlStall +#define MAP_TimerControlStall \ + ROM_TimerControlStall +#else +#define MAP_TimerControlStall \ + TimerControlStall +#endif +#ifdef ROM_TimerPrescaleSet +#define MAP_TimerPrescaleSet \ + ROM_TimerPrescaleSet +#else +#define MAP_TimerPrescaleSet \ + TimerPrescaleSet +#endif +#ifdef ROM_TimerPrescaleGet +#define MAP_TimerPrescaleGet \ + ROM_TimerPrescaleGet +#else +#define MAP_TimerPrescaleGet \ + TimerPrescaleGet +#endif +#ifdef ROM_TimerPrescaleMatchSet +#define MAP_TimerPrescaleMatchSet \ + ROM_TimerPrescaleMatchSet +#else +#define MAP_TimerPrescaleMatchSet \ + TimerPrescaleMatchSet +#endif +#ifdef ROM_TimerPrescaleMatchGet +#define MAP_TimerPrescaleMatchGet \ + ROM_TimerPrescaleMatchGet +#else +#define MAP_TimerPrescaleMatchGet \ + TimerPrescaleMatchGet +#endif +#ifdef ROM_TimerLoadSet +#define MAP_TimerLoadSet \ + ROM_TimerLoadSet +#else +#define MAP_TimerLoadSet \ + TimerLoadSet +#endif +#ifdef ROM_TimerLoadGet +#define MAP_TimerLoadGet \ + ROM_TimerLoadGet +#else +#define MAP_TimerLoadGet \ + TimerLoadGet +#endif +#ifdef ROM_TimerValueGet +#define MAP_TimerValueGet \ + ROM_TimerValueGet +#else +#define MAP_TimerValueGet \ + TimerValueGet +#endif +#ifdef ROM_TimerMatchSet +#define MAP_TimerMatchSet \ + ROM_TimerMatchSet +#else +#define MAP_TimerMatchSet \ + TimerMatchSet +#endif +#ifdef ROM_TimerMatchGet +#define MAP_TimerMatchGet \ + ROM_TimerMatchGet +#else +#define MAP_TimerMatchGet \ + TimerMatchGet +#endif +#ifdef ROM_TimerIntRegister +#define MAP_TimerIntRegister \ + ROM_TimerIntRegister +#else +#define MAP_TimerIntRegister \ + TimerIntRegister +#endif +#ifdef ROM_TimerIntUnregister +#define MAP_TimerIntUnregister \ + ROM_TimerIntUnregister +#else +#define MAP_TimerIntUnregister \ + TimerIntUnregister +#endif +#ifdef ROM_TimerIntEnable +#define MAP_TimerIntEnable \ + ROM_TimerIntEnable +#else +#define MAP_TimerIntEnable \ + TimerIntEnable +#endif +#ifdef ROM_TimerIntDisable +#define MAP_TimerIntDisable \ + ROM_TimerIntDisable +#else +#define MAP_TimerIntDisable \ + TimerIntDisable +#endif +#ifdef ROM_TimerIntStatus +#define MAP_TimerIntStatus \ + ROM_TimerIntStatus +#else +#define MAP_TimerIntStatus \ + TimerIntStatus +#endif +#ifdef ROM_TimerIntClear +#define MAP_TimerIntClear \ + ROM_TimerIntClear +#else +#define MAP_TimerIntClear \ + TimerIntClear +#endif +#ifdef ROM_TimerValueSet +#define MAP_TimerValueSet \ + ROM_TimerValueSet +#else +#define MAP_TimerValueSet \ + TimerValueSet +#endif +#ifdef ROM_TimerDMAEventSet +#define MAP_TimerDMAEventSet \ + ROM_TimerDMAEventSet +#else +#define MAP_TimerDMAEventSet \ + TimerDMAEventSet +#endif +#ifdef ROM_TimerDMAEventGet +#define MAP_TimerDMAEventGet \ + ROM_TimerDMAEventGet +#else +#define MAP_TimerDMAEventGet \ + TimerDMAEventGet +#endif + +//***************************************************************************** +// +// Macros for the UART API. +// +//***************************************************************************** +#ifdef ROM_UARTParityModeSet +#define MAP_UARTParityModeSet \ + ROM_UARTParityModeSet +#else +#define MAP_UARTParityModeSet \ + UARTParityModeSet +#endif +#ifdef ROM_UARTParityModeGet +#define MAP_UARTParityModeGet \ + ROM_UARTParityModeGet +#else +#define MAP_UARTParityModeGet \ + UARTParityModeGet +#endif +#ifdef ROM_UARTFIFOLevelSet +#define MAP_UARTFIFOLevelSet \ + ROM_UARTFIFOLevelSet +#else +#define MAP_UARTFIFOLevelSet \ + UARTFIFOLevelSet +#endif +#ifdef ROM_UARTFIFOLevelGet +#define MAP_UARTFIFOLevelGet \ + ROM_UARTFIFOLevelGet +#else +#define MAP_UARTFIFOLevelGet \ + UARTFIFOLevelGet +#endif +#ifdef ROM_UARTConfigSetExpClk +#define MAP_UARTConfigSetExpClk \ + ROM_UARTConfigSetExpClk +#else +#define MAP_UARTConfigSetExpClk \ + UARTConfigSetExpClk +#endif +#ifdef ROM_UARTConfigGetExpClk +#define MAP_UARTConfigGetExpClk \ + ROM_UARTConfigGetExpClk +#else +#define MAP_UARTConfigGetExpClk \ + UARTConfigGetExpClk +#endif +#ifdef ROM_UARTEnable +#define MAP_UARTEnable \ + ROM_UARTEnable +#else +#define MAP_UARTEnable \ + UARTEnable +#endif +#ifdef ROM_UARTDisable +#define MAP_UARTDisable \ + ROM_UARTDisable +#else +#define MAP_UARTDisable \ + UARTDisable +#endif +#ifdef ROM_UARTFIFOEnable +#define MAP_UARTFIFOEnable \ + ROM_UARTFIFOEnable +#else +#define MAP_UARTFIFOEnable \ + UARTFIFOEnable +#endif +#ifdef ROM_UARTFIFODisable +#define MAP_UARTFIFODisable \ + ROM_UARTFIFODisable +#else +#define MAP_UARTFIFODisable \ + UARTFIFODisable +#endif +#ifdef ROM_UARTCharsAvail +#define MAP_UARTCharsAvail \ + ROM_UARTCharsAvail +#else +#define MAP_UARTCharsAvail \ + UARTCharsAvail +#endif +#ifdef ROM_UARTSpaceAvail +#define MAP_UARTSpaceAvail \ + ROM_UARTSpaceAvail +#else +#define MAP_UARTSpaceAvail \ + UARTSpaceAvail +#endif +#ifdef ROM_UARTCharGetNonBlocking +#define MAP_UARTCharGetNonBlocking \ + ROM_UARTCharGetNonBlocking +#else +#define MAP_UARTCharGetNonBlocking \ + UARTCharGetNonBlocking +#endif +#ifdef ROM_UARTCharGet +#define MAP_UARTCharGet \ + ROM_UARTCharGet +#else +#define MAP_UARTCharGet \ + UARTCharGet +#endif +#ifdef ROM_UARTCharPutNonBlocking +#define MAP_UARTCharPutNonBlocking \ + ROM_UARTCharPutNonBlocking +#else +#define MAP_UARTCharPutNonBlocking \ + UARTCharPutNonBlocking +#endif +#ifdef ROM_UARTCharPut +#define MAP_UARTCharPut \ + ROM_UARTCharPut +#else +#define MAP_UARTCharPut \ + UARTCharPut +#endif +#ifdef ROM_UARTBreakCtl +#define MAP_UARTBreakCtl \ + ROM_UARTBreakCtl +#else +#define MAP_UARTBreakCtl \ + UARTBreakCtl +#endif +#ifdef ROM_UARTBusy +#define MAP_UARTBusy \ + ROM_UARTBusy +#else +#define MAP_UARTBusy \ + UARTBusy +#endif +#ifdef ROM_UARTIntRegister +#define MAP_UARTIntRegister \ + ROM_UARTIntRegister +#else +#define MAP_UARTIntRegister \ + UARTIntRegister +#endif +#ifdef ROM_UARTIntUnregister +#define MAP_UARTIntUnregister \ + ROM_UARTIntUnregister +#else +#define MAP_UARTIntUnregister \ + UARTIntUnregister +#endif +#ifdef ROM_UARTIntEnable +#define MAP_UARTIntEnable \ + ROM_UARTIntEnable +#else +#define MAP_UARTIntEnable \ + UARTIntEnable +#endif +#ifdef ROM_UARTIntDisable +#define MAP_UARTIntDisable \ + ROM_UARTIntDisable +#else +#define MAP_UARTIntDisable \ + UARTIntDisable +#endif +#ifdef ROM_UARTIntStatus +#define MAP_UARTIntStatus \ + ROM_UARTIntStatus +#else +#define MAP_UARTIntStatus \ + UARTIntStatus +#endif +#ifdef ROM_UARTIntClear +#define MAP_UARTIntClear \ + ROM_UARTIntClear +#else +#define MAP_UARTIntClear \ + UARTIntClear +#endif +#ifdef ROM_UARTDMAEnable +#define MAP_UARTDMAEnable \ + ROM_UARTDMAEnable +#else +#define MAP_UARTDMAEnable \ + UARTDMAEnable +#endif +#ifdef ROM_UARTDMADisable +#define MAP_UARTDMADisable \ + ROM_UARTDMADisable +#else +#define MAP_UARTDMADisable \ + UARTDMADisable +#endif +#ifdef ROM_UARTRxErrorGet +#define MAP_UARTRxErrorGet \ + ROM_UARTRxErrorGet +#else +#define MAP_UARTRxErrorGet \ + UARTRxErrorGet +#endif +#ifdef ROM_UARTRxErrorClear +#define MAP_UARTRxErrorClear \ + ROM_UARTRxErrorClear +#else +#define MAP_UARTRxErrorClear \ + UARTRxErrorClear +#endif +#ifdef ROM_UARTModemControlSet +#define MAP_UARTModemControlSet \ + ROM_UARTModemControlSet +#else +#define MAP_UARTModemControlSet \ + UARTModemControlSet +#endif +#ifdef ROM_UARTModemControlClear +#define MAP_UARTModemControlClear \ + ROM_UARTModemControlClear +#else +#define MAP_UARTModemControlClear \ + UARTModemControlClear +#endif +#ifdef ROM_UARTModemControlGet +#define MAP_UARTModemControlGet \ + ROM_UARTModemControlGet +#else +#define MAP_UARTModemControlGet \ + UARTModemControlGet +#endif +#ifdef ROM_UARTModemStatusGet +#define MAP_UARTModemStatusGet \ + ROM_UARTModemStatusGet +#else +#define MAP_UARTModemStatusGet \ + UARTModemStatusGet +#endif +#ifdef ROM_UARTFlowControlSet +#define MAP_UARTFlowControlSet \ + ROM_UARTFlowControlSet +#else +#define MAP_UARTFlowControlSet \ + UARTFlowControlSet +#endif +#ifdef ROM_UARTFlowControlGet +#define MAP_UARTFlowControlGet \ + ROM_UARTFlowControlGet +#else +#define MAP_UARTFlowControlGet \ + UARTFlowControlGet +#endif +#ifdef ROM_UARTTxIntModeSet +#define MAP_UARTTxIntModeSet \ + ROM_UARTTxIntModeSet +#else +#define MAP_UARTTxIntModeSet \ + UARTTxIntModeSet +#endif +#ifdef ROM_UARTTxIntModeGet +#define MAP_UARTTxIntModeGet \ + ROM_UARTTxIntModeGet +#else +#define MAP_UARTTxIntModeGet \ + UARTTxIntModeGet +#endif + +//***************************************************************************** +// +// Macros for the uDMA API. +// +//***************************************************************************** +#ifdef ROM_uDMAChannelTransferSet +#define MAP_uDMAChannelTransferSet \ + ROM_uDMAChannelTransferSet +#else +#define MAP_uDMAChannelTransferSet \ + uDMAChannelTransferSet +#endif +#ifdef ROM_uDMAEnable +#define MAP_uDMAEnable \ + ROM_uDMAEnable +#else +#define MAP_uDMAEnable \ + uDMAEnable +#endif +#ifdef ROM_uDMADisable +#define MAP_uDMADisable \ + ROM_uDMADisable +#else +#define MAP_uDMADisable \ + uDMADisable +#endif +#ifdef ROM_uDMAErrorStatusGet +#define MAP_uDMAErrorStatusGet \ + ROM_uDMAErrorStatusGet +#else +#define MAP_uDMAErrorStatusGet \ + uDMAErrorStatusGet +#endif +#ifdef ROM_uDMAErrorStatusClear +#define MAP_uDMAErrorStatusClear \ + ROM_uDMAErrorStatusClear +#else +#define MAP_uDMAErrorStatusClear \ + uDMAErrorStatusClear +#endif +#ifdef ROM_uDMAChannelEnable +#define MAP_uDMAChannelEnable \ + ROM_uDMAChannelEnable +#else +#define MAP_uDMAChannelEnable \ + uDMAChannelEnable +#endif +#ifdef ROM_uDMAChannelDisable +#define MAP_uDMAChannelDisable \ + ROM_uDMAChannelDisable +#else +#define MAP_uDMAChannelDisable \ + uDMAChannelDisable +#endif +#ifdef ROM_uDMAChannelIsEnabled +#define MAP_uDMAChannelIsEnabled \ + ROM_uDMAChannelIsEnabled +#else +#define MAP_uDMAChannelIsEnabled \ + uDMAChannelIsEnabled +#endif +#ifdef ROM_uDMAControlBaseSet +#define MAP_uDMAControlBaseSet \ + ROM_uDMAControlBaseSet +#else +#define MAP_uDMAControlBaseSet \ + uDMAControlBaseSet +#endif +#ifdef ROM_uDMAControlBaseGet +#define MAP_uDMAControlBaseGet \ + ROM_uDMAControlBaseGet +#else +#define MAP_uDMAControlBaseGet \ + uDMAControlBaseGet +#endif +#ifdef ROM_uDMAChannelRequest +#define MAP_uDMAChannelRequest \ + ROM_uDMAChannelRequest +#else +#define MAP_uDMAChannelRequest \ + uDMAChannelRequest +#endif +#ifdef ROM_uDMAChannelAttributeEnable +#define MAP_uDMAChannelAttributeEnable \ + ROM_uDMAChannelAttributeEnable +#else +#define MAP_uDMAChannelAttributeEnable \ + uDMAChannelAttributeEnable +#endif +#ifdef ROM_uDMAChannelAttributeDisable +#define MAP_uDMAChannelAttributeDisable \ + ROM_uDMAChannelAttributeDisable +#else +#define MAP_uDMAChannelAttributeDisable \ + uDMAChannelAttributeDisable +#endif +#ifdef ROM_uDMAChannelAttributeGet +#define MAP_uDMAChannelAttributeGet \ + ROM_uDMAChannelAttributeGet +#else +#define MAP_uDMAChannelAttributeGet \ + uDMAChannelAttributeGet +#endif +#ifdef ROM_uDMAChannelControlSet +#define MAP_uDMAChannelControlSet \ + ROM_uDMAChannelControlSet +#else +#define MAP_uDMAChannelControlSet \ + uDMAChannelControlSet +#endif +#ifdef ROM_uDMAChannelSizeGet +#define MAP_uDMAChannelSizeGet \ + ROM_uDMAChannelSizeGet +#else +#define MAP_uDMAChannelSizeGet \ + uDMAChannelSizeGet +#endif +#ifdef ROM_uDMAChannelModeGet +#define MAP_uDMAChannelModeGet \ + ROM_uDMAChannelModeGet +#else +#define MAP_uDMAChannelModeGet \ + uDMAChannelModeGet +#endif +#ifdef ROM_uDMAIntStatus +#define MAP_uDMAIntStatus \ + ROM_uDMAIntStatus +#else +#define MAP_uDMAIntStatus \ + uDMAIntStatus +#endif +#ifdef ROM_uDMAIntClear +#define MAP_uDMAIntClear \ + ROM_uDMAIntClear +#else +#define MAP_uDMAIntClear \ + uDMAIntClear +#endif +#ifdef ROM_uDMAControlAlternateBaseGet +#define MAP_uDMAControlAlternateBaseGet \ + ROM_uDMAControlAlternateBaseGet +#else +#define MAP_uDMAControlAlternateBaseGet \ + uDMAControlAlternateBaseGet +#endif +#ifdef ROM_uDMAChannelScatterGatherSet +#define MAP_uDMAChannelScatterGatherSet \ + ROM_uDMAChannelScatterGatherSet +#else +#define MAP_uDMAChannelScatterGatherSet \ + uDMAChannelScatterGatherSet +#endif +#ifdef ROM_uDMAChannelAssign +#define MAP_uDMAChannelAssign \ + ROM_uDMAChannelAssign +#else +#define MAP_uDMAChannelAssign \ + uDMAChannelAssign +#endif +#ifdef ROM_uDMAIntRegister +#define MAP_uDMAIntRegister \ + ROM_uDMAIntRegister +#else +#define MAP_uDMAIntRegister \ + uDMAIntRegister +#endif +#ifdef ROM_uDMAIntUnregister +#define MAP_uDMAIntUnregister \ + ROM_uDMAIntUnregister +#else +#define MAP_uDMAIntUnregister \ + uDMAIntUnregister +#endif + +//***************************************************************************** +// +// Macros for the Watchdog API. +// +//***************************************************************************** +#ifdef ROM_WatchdogIntClear +#define MAP_WatchdogIntClear \ + ROM_WatchdogIntClear +#else +#define MAP_WatchdogIntClear \ + WatchdogIntClear +#endif +#ifdef ROM_WatchdogRunning +#define MAP_WatchdogRunning \ + ROM_WatchdogRunning +#else +#define MAP_WatchdogRunning \ + WatchdogRunning +#endif +#ifdef ROM_WatchdogEnable +#define MAP_WatchdogEnable \ + ROM_WatchdogEnable +#else +#define MAP_WatchdogEnable \ + WatchdogEnable +#endif +#ifdef ROM_WatchdogLock +#define MAP_WatchdogLock \ + ROM_WatchdogLock +#else +#define MAP_WatchdogLock \ + WatchdogLock +#endif +#ifdef ROM_WatchdogUnlock +#define MAP_WatchdogUnlock \ + ROM_WatchdogUnlock +#else +#define MAP_WatchdogUnlock \ + WatchdogUnlock +#endif +#ifdef ROM_WatchdogLockState +#define MAP_WatchdogLockState \ + ROM_WatchdogLockState +#else +#define MAP_WatchdogLockState \ + WatchdogLockState +#endif +#ifdef ROM_WatchdogReloadSet +#define MAP_WatchdogReloadSet \ + ROM_WatchdogReloadSet +#else +#define MAP_WatchdogReloadSet \ + WatchdogReloadSet +#endif +#ifdef ROM_WatchdogReloadGet +#define MAP_WatchdogReloadGet \ + ROM_WatchdogReloadGet +#else +#define MAP_WatchdogReloadGet \ + WatchdogReloadGet +#endif +#ifdef ROM_WatchdogValueGet +#define MAP_WatchdogValueGet \ + ROM_WatchdogValueGet +#else +#define MAP_WatchdogValueGet \ + WatchdogValueGet +#endif +#ifdef ROM_WatchdogIntStatus +#define MAP_WatchdogIntStatus \ + ROM_WatchdogIntStatus +#else +#define MAP_WatchdogIntStatus \ + WatchdogIntStatus +#endif +#ifdef ROM_WatchdogStallEnable +#define MAP_WatchdogStallEnable \ + ROM_WatchdogStallEnable +#else +#define MAP_WatchdogStallEnable \ + WatchdogStallEnable +#endif +#ifdef ROM_WatchdogStallDisable +#define MAP_WatchdogStallDisable \ + ROM_WatchdogStallDisable +#else +#define MAP_WatchdogStallDisable \ + WatchdogStallDisable +#endif +#ifdef ROM_WatchdogIntRegister +#define MAP_WatchdogIntRegister \ + ROM_WatchdogIntRegister +#else +#define MAP_WatchdogIntRegister \ + WatchdogIntRegister +#endif +#ifdef ROM_WatchdogIntUnregister +#define MAP_WatchdogIntUnregister \ + ROM_WatchdogIntUnregister +#else +#define MAP_WatchdogIntUnregister \ + WatchdogIntUnregister +#endif + +//***************************************************************************** +// +// Macros for the I2C API. +// +//***************************************************************************** +#ifdef ROM_I2CIntRegister +#define MAP_I2CIntRegister \ + ROM_I2CIntRegister +#else +#define MAP_I2CIntRegister \ + I2CIntRegister +#endif +#ifdef ROM_I2CIntUnregister +#define MAP_I2CIntUnregister \ + ROM_I2CIntUnregister +#else +#define MAP_I2CIntUnregister \ + I2CIntUnregister +#endif +#ifdef ROM_I2CTxFIFOConfigSet +#define MAP_I2CTxFIFOConfigSet \ + ROM_I2CTxFIFOConfigSet +#else +#define MAP_I2CTxFIFOConfigSet \ + I2CTxFIFOConfigSet +#endif +#ifdef ROM_I2CTxFIFOFlush +#define MAP_I2CTxFIFOFlush \ + ROM_I2CTxFIFOFlush +#else +#define MAP_I2CTxFIFOFlush \ + I2CTxFIFOFlush +#endif +#ifdef ROM_I2CRxFIFOConfigSet +#define MAP_I2CRxFIFOConfigSet \ + ROM_I2CRxFIFOConfigSet +#else +#define MAP_I2CRxFIFOConfigSet \ + I2CRxFIFOConfigSet +#endif +#ifdef ROM_I2CRxFIFOFlush +#define MAP_I2CRxFIFOFlush \ + ROM_I2CRxFIFOFlush +#else +#define MAP_I2CRxFIFOFlush \ + I2CRxFIFOFlush +#endif +#ifdef ROM_I2CFIFOStatus +#define MAP_I2CFIFOStatus \ + ROM_I2CFIFOStatus +#else +#define MAP_I2CFIFOStatus \ + I2CFIFOStatus +#endif +#ifdef ROM_I2CFIFODataPut +#define MAP_I2CFIFODataPut \ + ROM_I2CFIFODataPut +#else +#define MAP_I2CFIFODataPut \ + I2CFIFODataPut +#endif +#ifdef ROM_I2CFIFODataPutNonBlocking +#define MAP_I2CFIFODataPutNonBlocking \ + ROM_I2CFIFODataPutNonBlocking +#else +#define MAP_I2CFIFODataPutNonBlocking \ + I2CFIFODataPutNonBlocking +#endif +#ifdef ROM_I2CFIFODataGet +#define MAP_I2CFIFODataGet \ + ROM_I2CFIFODataGet +#else +#define MAP_I2CFIFODataGet \ + I2CFIFODataGet +#endif +#ifdef ROM_I2CFIFODataGetNonBlocking +#define MAP_I2CFIFODataGetNonBlocking \ + ROM_I2CFIFODataGetNonBlocking +#else +#define MAP_I2CFIFODataGetNonBlocking \ + I2CFIFODataGetNonBlocking +#endif +#ifdef ROM_I2CMasterBurstLengthSet +#define MAP_I2CMasterBurstLengthSet \ + ROM_I2CMasterBurstLengthSet +#else +#define MAP_I2CMasterBurstLengthSet \ + I2CMasterBurstLengthSet +#endif +#ifdef ROM_I2CMasterBurstCountGet +#define MAP_I2CMasterBurstCountGet \ + ROM_I2CMasterBurstCountGet +#else +#define MAP_I2CMasterBurstCountGet \ + I2CMasterBurstCountGet +#endif +#ifdef ROM_I2CMasterGlitchFilterConfigSet +#define MAP_I2CMasterGlitchFilterConfigSet \ + ROM_I2CMasterGlitchFilterConfigSet +#else +#define MAP_I2CMasterGlitchFilterConfigSet \ + I2CMasterGlitchFilterConfigSet +#endif +#ifdef ROM_I2CSlaveFIFOEnable +#define MAP_I2CSlaveFIFOEnable \ + ROM_I2CSlaveFIFOEnable +#else +#define MAP_I2CSlaveFIFOEnable \ + I2CSlaveFIFOEnable +#endif +#ifdef ROM_I2CSlaveFIFODisable +#define MAP_I2CSlaveFIFODisable \ + ROM_I2CSlaveFIFODisable +#else +#define MAP_I2CSlaveFIFODisable \ + I2CSlaveFIFODisable +#endif +#ifdef ROM_I2CMasterBusBusy +#define MAP_I2CMasterBusBusy \ + ROM_I2CMasterBusBusy +#else +#define MAP_I2CMasterBusBusy \ + I2CMasterBusBusy +#endif +#ifdef ROM_I2CMasterBusy +#define MAP_I2CMasterBusy \ + ROM_I2CMasterBusy +#else +#define MAP_I2CMasterBusy \ + I2CMasterBusy +#endif +#ifdef ROM_I2CMasterControl +#define MAP_I2CMasterControl \ + ROM_I2CMasterControl +#else +#define MAP_I2CMasterControl \ + I2CMasterControl +#endif +#ifdef ROM_I2CMasterDataGet +#define MAP_I2CMasterDataGet \ + ROM_I2CMasterDataGet +#else +#define MAP_I2CMasterDataGet \ + I2CMasterDataGet +#endif +#ifdef ROM_I2CMasterDataPut +#define MAP_I2CMasterDataPut \ + ROM_I2CMasterDataPut +#else +#define MAP_I2CMasterDataPut \ + I2CMasterDataPut +#endif +#ifdef ROM_I2CMasterDisable +#define MAP_I2CMasterDisable \ + ROM_I2CMasterDisable +#else +#define MAP_I2CMasterDisable \ + I2CMasterDisable +#endif +#ifdef ROM_I2CMasterEnable +#define MAP_I2CMasterEnable \ + ROM_I2CMasterEnable +#else +#define MAP_I2CMasterEnable \ + I2CMasterEnable +#endif +#ifdef ROM_I2CMasterErr +#define MAP_I2CMasterErr \ + ROM_I2CMasterErr +#else +#define MAP_I2CMasterErr \ + I2CMasterErr +#endif +#ifdef ROM_I2CMasterIntClear +#define MAP_I2CMasterIntClear \ + ROM_I2CMasterIntClear +#else +#define MAP_I2CMasterIntClear \ + I2CMasterIntClear +#endif +#ifdef ROM_I2CMasterIntDisable +#define MAP_I2CMasterIntDisable \ + ROM_I2CMasterIntDisable +#else +#define MAP_I2CMasterIntDisable \ + I2CMasterIntDisable +#endif +#ifdef ROM_I2CMasterIntEnable +#define MAP_I2CMasterIntEnable \ + ROM_I2CMasterIntEnable +#else +#define MAP_I2CMasterIntEnable \ + I2CMasterIntEnable +#endif +#ifdef ROM_I2CMasterIntStatus +#define MAP_I2CMasterIntStatus \ + ROM_I2CMasterIntStatus +#else +#define MAP_I2CMasterIntStatus \ + I2CMasterIntStatus +#endif +#ifdef ROM_I2CMasterIntEnableEx +#define MAP_I2CMasterIntEnableEx \ + ROM_I2CMasterIntEnableEx +#else +#define MAP_I2CMasterIntEnableEx \ + I2CMasterIntEnableEx +#endif +#ifdef ROM_I2CMasterIntDisableEx +#define MAP_I2CMasterIntDisableEx \ + ROM_I2CMasterIntDisableEx +#else +#define MAP_I2CMasterIntDisableEx \ + I2CMasterIntDisableEx +#endif +#ifdef ROM_I2CMasterIntStatusEx +#define MAP_I2CMasterIntStatusEx \ + ROM_I2CMasterIntStatusEx +#else +#define MAP_I2CMasterIntStatusEx \ + I2CMasterIntStatusEx +#endif +#ifdef ROM_I2CMasterIntClearEx +#define MAP_I2CMasterIntClearEx \ + ROM_I2CMasterIntClearEx +#else +#define MAP_I2CMasterIntClearEx \ + I2CMasterIntClearEx +#endif +#ifdef ROM_I2CMasterTimeoutSet +#define MAP_I2CMasterTimeoutSet \ + ROM_I2CMasterTimeoutSet +#else +#define MAP_I2CMasterTimeoutSet \ + I2CMasterTimeoutSet +#endif +#ifdef ROM_I2CSlaveACKOverride +#define MAP_I2CSlaveACKOverride \ + ROM_I2CSlaveACKOverride +#else +#define MAP_I2CSlaveACKOverride \ + I2CSlaveACKOverride +#endif +#ifdef ROM_I2CSlaveACKValueSet +#define MAP_I2CSlaveACKValueSet \ + ROM_I2CSlaveACKValueSet +#else +#define MAP_I2CSlaveACKValueSet \ + I2CSlaveACKValueSet +#endif +#ifdef ROM_I2CMasterLineStateGet +#define MAP_I2CMasterLineStateGet \ + ROM_I2CMasterLineStateGet +#else +#define MAP_I2CMasterLineStateGet \ + I2CMasterLineStateGet +#endif +#ifdef ROM_I2CMasterSlaveAddrSet +#define MAP_I2CMasterSlaveAddrSet \ + ROM_I2CMasterSlaveAddrSet +#else +#define MAP_I2CMasterSlaveAddrSet \ + I2CMasterSlaveAddrSet +#endif +#ifdef ROM_I2CSlaveDataGet +#define MAP_I2CSlaveDataGet \ + ROM_I2CSlaveDataGet +#else +#define MAP_I2CSlaveDataGet \ + I2CSlaveDataGet +#endif +#ifdef ROM_I2CSlaveDataPut +#define MAP_I2CSlaveDataPut \ + ROM_I2CSlaveDataPut +#else +#define MAP_I2CSlaveDataPut \ + I2CSlaveDataPut +#endif +#ifdef ROM_I2CSlaveDisable +#define MAP_I2CSlaveDisable \ + ROM_I2CSlaveDisable +#else +#define MAP_I2CSlaveDisable \ + I2CSlaveDisable +#endif +#ifdef ROM_I2CSlaveEnable +#define MAP_I2CSlaveEnable \ + ROM_I2CSlaveEnable +#else +#define MAP_I2CSlaveEnable \ + I2CSlaveEnable +#endif +#ifdef ROM_I2CSlaveInit +#define MAP_I2CSlaveInit \ + ROM_I2CSlaveInit +#else +#define MAP_I2CSlaveInit \ + I2CSlaveInit +#endif +#ifdef ROM_I2CSlaveAddressSet +#define MAP_I2CSlaveAddressSet \ + ROM_I2CSlaveAddressSet +#else +#define MAP_I2CSlaveAddressSet \ + I2CSlaveAddressSet +#endif +#ifdef ROM_I2CSlaveIntClear +#define MAP_I2CSlaveIntClear \ + ROM_I2CSlaveIntClear +#else +#define MAP_I2CSlaveIntClear \ + I2CSlaveIntClear +#endif +#ifdef ROM_I2CSlaveIntDisable +#define MAP_I2CSlaveIntDisable \ + ROM_I2CSlaveIntDisable +#else +#define MAP_I2CSlaveIntDisable \ + I2CSlaveIntDisable +#endif +#ifdef ROM_I2CSlaveIntEnable +#define MAP_I2CSlaveIntEnable \ + ROM_I2CSlaveIntEnable +#else +#define MAP_I2CSlaveIntEnable \ + I2CSlaveIntEnable +#endif +#ifdef ROM_I2CSlaveIntClearEx +#define MAP_I2CSlaveIntClearEx \ + ROM_I2CSlaveIntClearEx +#else +#define MAP_I2CSlaveIntClearEx \ + I2CSlaveIntClearEx +#endif +#ifdef ROM_I2CSlaveIntDisableEx +#define MAP_I2CSlaveIntDisableEx \ + ROM_I2CSlaveIntDisableEx +#else +#define MAP_I2CSlaveIntDisableEx \ + I2CSlaveIntDisableEx +#endif +#ifdef ROM_I2CSlaveIntEnableEx +#define MAP_I2CSlaveIntEnableEx \ + ROM_I2CSlaveIntEnableEx +#else +#define MAP_I2CSlaveIntEnableEx \ + I2CSlaveIntEnableEx +#endif +#ifdef ROM_I2CSlaveIntStatus +#define MAP_I2CSlaveIntStatus \ + ROM_I2CSlaveIntStatus +#else +#define MAP_I2CSlaveIntStatus \ + I2CSlaveIntStatus +#endif +#ifdef ROM_I2CSlaveIntStatusEx +#define MAP_I2CSlaveIntStatusEx \ + ROM_I2CSlaveIntStatusEx +#else +#define MAP_I2CSlaveIntStatusEx \ + I2CSlaveIntStatusEx +#endif +#ifdef ROM_I2CSlaveStatus +#define MAP_I2CSlaveStatus \ + ROM_I2CSlaveStatus +#else +#define MAP_I2CSlaveStatus \ + I2CSlaveStatus +#endif +#ifdef ROM_I2CMasterInitExpClk +#define MAP_I2CMasterInitExpClk \ + ROM_I2CMasterInitExpClk +#else +#define MAP_I2CMasterInitExpClk \ + I2CMasterInitExpClk +#endif + +//***************************************************************************** +// +// Macros for the SPI API. +// +//***************************************************************************** +#ifdef ROM_SPIEnable +#define MAP_SPIEnable \ + ROM_SPIEnable +#else +#define MAP_SPIEnable \ + SPIEnable +#endif +#ifdef ROM_SPIDisable +#define MAP_SPIDisable \ + ROM_SPIDisable +#else +#define MAP_SPIDisable \ + SPIDisable +#endif +#ifdef ROM_SPIReset +#define MAP_SPIReset \ + ROM_SPIReset +#else +#define MAP_SPIReset \ + SPIReset +#endif +#ifdef ROM_SPIConfigSetExpClk +#define MAP_SPIConfigSetExpClk \ + ROM_SPIConfigSetExpClk +#else +#define MAP_SPIConfigSetExpClk \ + SPIConfigSetExpClk +#endif +#ifdef ROM_SPIDataGetNonBlocking +#define MAP_SPIDataGetNonBlocking \ + ROM_SPIDataGetNonBlocking +#else +#define MAP_SPIDataGetNonBlocking \ + SPIDataGetNonBlocking +#endif +#ifdef ROM_SPIDataGet +#define MAP_SPIDataGet \ + ROM_SPIDataGet +#else +#define MAP_SPIDataGet \ + SPIDataGet +#endif +#ifdef ROM_SPIDataPutNonBlocking +#define MAP_SPIDataPutNonBlocking \ + ROM_SPIDataPutNonBlocking +#else +#define MAP_SPIDataPutNonBlocking \ + SPIDataPutNonBlocking +#endif +#ifdef ROM_SPIDataPut +#define MAP_SPIDataPut \ + ROM_SPIDataPut +#else +#define MAP_SPIDataPut \ + SPIDataPut +#endif +#ifdef ROM_SPIFIFOEnable +#define MAP_SPIFIFOEnable \ + ROM_SPIFIFOEnable +#else +#define MAP_SPIFIFOEnable \ + SPIFIFOEnable +#endif +#ifdef ROM_SPIFIFODisable +#define MAP_SPIFIFODisable \ + ROM_SPIFIFODisable +#else +#define MAP_SPIFIFODisable \ + SPIFIFODisable +#endif +#ifdef ROM_SPIFIFOLevelSet +#define MAP_SPIFIFOLevelSet \ + ROM_SPIFIFOLevelSet +#else +#define MAP_SPIFIFOLevelSet \ + SPIFIFOLevelSet +#endif +#ifdef ROM_SPIFIFOLevelGet +#define MAP_SPIFIFOLevelGet \ + ROM_SPIFIFOLevelGet +#else +#define MAP_SPIFIFOLevelGet \ + SPIFIFOLevelGet +#endif +#ifdef ROM_SPIWordCountSet +#define MAP_SPIWordCountSet \ + ROM_SPIWordCountSet +#else +#define MAP_SPIWordCountSet \ + SPIWordCountSet +#endif +#ifdef ROM_SPIIntRegister +#define MAP_SPIIntRegister \ + ROM_SPIIntRegister +#else +#define MAP_SPIIntRegister \ + SPIIntRegister +#endif +#ifdef ROM_SPIIntUnregister +#define MAP_SPIIntUnregister \ + ROM_SPIIntUnregister +#else +#define MAP_SPIIntUnregister \ + SPIIntUnregister +#endif +#ifdef ROM_SPIIntEnable +#define MAP_SPIIntEnable \ + ROM_SPIIntEnable +#else +#define MAP_SPIIntEnable \ + SPIIntEnable +#endif +#ifdef ROM_SPIIntDisable +#define MAP_SPIIntDisable \ + ROM_SPIIntDisable +#else +#define MAP_SPIIntDisable \ + SPIIntDisable +#endif +#ifdef ROM_SPIIntStatus +#define MAP_SPIIntStatus \ + ROM_SPIIntStatus +#else +#define MAP_SPIIntStatus \ + SPIIntStatus +#endif +#ifdef ROM_SPIIntClear +#define MAP_SPIIntClear \ + ROM_SPIIntClear +#else +#define MAP_SPIIntClear \ + SPIIntClear +#endif +#ifdef ROM_SPIDmaEnable +#define MAP_SPIDmaEnable \ + ROM_SPIDmaEnable +#else +#define MAP_SPIDmaEnable \ + SPIDmaEnable +#endif +#ifdef ROM_SPIDmaDisable +#define MAP_SPIDmaDisable \ + ROM_SPIDmaDisable +#else +#define MAP_SPIDmaDisable \ + SPIDmaDisable +#endif +#ifdef ROM_SPICSEnable +#define MAP_SPICSEnable \ + ROM_SPICSEnable +#else +#define MAP_SPICSEnable \ + SPICSEnable +#endif +#ifdef ROM_SPICSDisable +#define MAP_SPICSDisable \ + ROM_SPICSDisable +#else +#define MAP_SPICSDisable \ + SPICSDisable +#endif +#ifdef ROM_SPITransfer +#define MAP_SPITransfer \ + ROM_SPITransfer +#else +#define MAP_SPITransfer \ + SPITransfer +#endif + +//***************************************************************************** +// +// Macros for the CAM API. +// +//***************************************************************************** +#ifdef ROM_CameraReset +#define MAP_CameraReset \ + ROM_CameraReset +#else +#define MAP_CameraReset \ + CameraReset +#endif +#ifdef ROM_CameraParamsConfig +#define MAP_CameraParamsConfig \ + ROM_CameraParamsConfig +#else +#define MAP_CameraParamsConfig \ + CameraParamsConfig +#endif +#ifdef ROM_CameraXClkConfig +#define MAP_CameraXClkConfig \ + ROM_CameraXClkConfig +#else +#define MAP_CameraXClkConfig \ + CameraXClkConfig +#endif +#ifdef ROM_CameraXClkSet +#define MAP_CameraXClkSet \ + ROM_CameraXClkSet +#else +#define MAP_CameraXClkSet \ + CameraXClkSet +#endif +#ifdef ROM_CameraDMAEnable +#define MAP_CameraDMAEnable \ + ROM_CameraDMAEnable +#else +#define MAP_CameraDMAEnable \ + CameraDMAEnable +#endif +#ifdef ROM_CameraDMADisable +#define MAP_CameraDMADisable \ + ROM_CameraDMADisable +#else +#define MAP_CameraDMADisable \ + CameraDMADisable +#endif +#ifdef ROM_CameraThresholdSet +#define MAP_CameraThresholdSet \ + ROM_CameraThresholdSet +#else +#define MAP_CameraThresholdSet \ + CameraThresholdSet +#endif +#ifdef ROM_CameraIntRegister +#define MAP_CameraIntRegister \ + ROM_CameraIntRegister +#else +#define MAP_CameraIntRegister \ + CameraIntRegister +#endif +#ifdef ROM_CameraIntUnregister +#define MAP_CameraIntUnregister \ + ROM_CameraIntUnregister +#else +#define MAP_CameraIntUnregister \ + CameraIntUnregister +#endif +#ifdef ROM_CameraIntEnable +#define MAP_CameraIntEnable \ + ROM_CameraIntEnable +#else +#define MAP_CameraIntEnable \ + CameraIntEnable +#endif +#ifdef ROM_CameraIntDisable +#define MAP_CameraIntDisable \ + ROM_CameraIntDisable +#else +#define MAP_CameraIntDisable \ + CameraIntDisable +#endif +#ifdef ROM_CameraIntStatus +#define MAP_CameraIntStatus \ + ROM_CameraIntStatus +#else +#define MAP_CameraIntStatus \ + CameraIntStatus +#endif +#ifdef ROM_CameraIntClear +#define MAP_CameraIntClear \ + ROM_CameraIntClear +#else +#define MAP_CameraIntClear \ + CameraIntClear +#endif +#ifdef ROM_CameraCaptureStop +#define MAP_CameraCaptureStop \ + ROM_CameraCaptureStop +#else +#define MAP_CameraCaptureStop \ + CameraCaptureStop +#endif +#ifdef ROM_CameraCaptureStart +#define MAP_CameraCaptureStart \ + ROM_CameraCaptureStart +#else +#define MAP_CameraCaptureStart \ + CameraCaptureStart +#endif +#ifdef ROM_CameraBufferRead +#define MAP_CameraBufferRead \ + ROM_CameraBufferRead +#else +#define MAP_CameraBufferRead \ + CameraBufferRead +#endif + +//***************************************************************************** +// +// Macros for the FLASH API. +// +//***************************************************************************** +#ifdef ROM_FlashDisable +#define MAP_FlashDisable \ + ROM_FlashDisable +#else +#define MAP_FlashDisable \ + FlashDisable +#endif +#ifdef ROM_FlashErase +#define MAP_FlashErase \ + ROM_FlashErase +#else +#define MAP_FlashErase \ + FlashErase +#endif +#ifdef ROM_FlashMassErase +#define MAP_FlashMassErase \ + ROM_FlashMassErase +#else +#define MAP_FlashMassErase \ + FlashMassErase +#endif +#ifdef ROM_FlashMassEraseNonBlocking +#define MAP_FlashMassEraseNonBlocking \ + ROM_FlashMassEraseNonBlocking +#else +#define MAP_FlashMassEraseNonBlocking \ + FlashMassEraseNonBlocking +#endif +#ifdef ROM_FlashEraseNonBlocking +#define MAP_FlashEraseNonBlocking \ + ROM_FlashEraseNonBlocking +#else +#define MAP_FlashEraseNonBlocking \ + FlashEraseNonBlocking +#endif +#ifdef ROM_FlashProgram +#define MAP_FlashProgram \ + ROM_FlashProgram +#else +#define MAP_FlashProgram \ + FlashProgram +#endif +#ifdef ROM_FlashProgramNonBlocking +#define MAP_FlashProgramNonBlocking \ + ROM_FlashProgramNonBlocking +#else +#define MAP_FlashProgramNonBlocking \ + FlashProgramNonBlocking +#endif +#ifdef ROM_FlashIntRegister +#define MAP_FlashIntRegister \ + ROM_FlashIntRegister +#else +#define MAP_FlashIntRegister \ + FlashIntRegister +#endif +#ifdef ROM_FlashIntUnregister +#define MAP_FlashIntUnregister \ + ROM_FlashIntUnregister +#else +#define MAP_FlashIntUnregister \ + FlashIntUnregister +#endif +#ifdef ROM_FlashIntEnable +#define MAP_FlashIntEnable \ + ROM_FlashIntEnable +#else +#define MAP_FlashIntEnable \ + FlashIntEnable +#endif +#ifdef ROM_FlashIntDisable +#define MAP_FlashIntDisable \ + ROM_FlashIntDisable +#else +#define MAP_FlashIntDisable \ + FlashIntDisable +#endif +#ifdef ROM_FlashIntStatus +#define MAP_FlashIntStatus \ + ROM_FlashIntStatus +#else +#define MAP_FlashIntStatus \ + FlashIntStatus +#endif +#ifdef ROM_FlashIntClear +#define MAP_FlashIntClear \ + ROM_FlashIntClear +#else +#define MAP_FlashIntClear \ + FlashIntClear +#endif +#ifdef ROM_FlashProtectGet +#define MAP_FlashProtectGet \ + ROM_FlashProtectGet +#else +#define MAP_FlashProtectGet \ + FlashProtectGet +#endif + +//***************************************************************************** +// +// Macros for the Pin API. +// +//***************************************************************************** +#ifdef ROM_PinModeSet +#define MAP_PinModeSet \ + ROM_PinModeSet +#else +#define MAP_PinModeSet \ + PinModeSet +#endif +#ifdef ROM_PinDirModeSet +#define MAP_PinDirModeSet \ + ROM_PinDirModeSet +#else +#define MAP_PinDirModeSet \ + PinDirModeSet +#endif +#ifdef ROM_PinDirModeGet +#define MAP_PinDirModeGet \ + ROM_PinDirModeGet +#else +#define MAP_PinDirModeGet \ + PinDirModeGet +#endif +#ifdef ROM_PinModeGet +#define MAP_PinModeGet \ + ROM_PinModeGet +#else +#define MAP_PinModeGet \ + PinModeGet +#endif +#ifdef ROM_PinConfigGet +#define MAP_PinConfigGet \ + ROM_PinConfigGet +#else +#define MAP_PinConfigGet \ + PinConfigGet +#endif +#ifdef ROM_PinConfigSet +#define MAP_PinConfigSet \ + ROM_PinConfigSet +#else +#define MAP_PinConfigSet \ + PinConfigSet +#endif +#ifdef ROM_PinTypeUART +#define MAP_PinTypeUART \ + ROM_PinTypeUART +#else +#define MAP_PinTypeUART \ + PinTypeUART +#endif +#ifdef ROM_PinTypeI2C +#define MAP_PinTypeI2C \ + ROM_PinTypeI2C +#else +#define MAP_PinTypeI2C \ + PinTypeI2C +#endif +#ifdef ROM_PinTypeSPI +#define MAP_PinTypeSPI \ + ROM_PinTypeSPI +#else +#define MAP_PinTypeSPI \ + PinTypeSPI +#endif +#ifdef ROM_PinTypeI2S +#define MAP_PinTypeI2S \ + ROM_PinTypeI2S +#else +#define MAP_PinTypeI2S \ + PinTypeI2S +#endif +#ifdef ROM_PinTypeTimer +#define MAP_PinTypeTimer \ + ROM_PinTypeTimer +#else +#define MAP_PinTypeTimer \ + PinTypeTimer +#endif +#ifdef ROM_PinTypeCamera +#define MAP_PinTypeCamera \ + ROM_PinTypeCamera +#else +#define MAP_PinTypeCamera \ + PinTypeCamera +#endif +#ifdef ROM_PinTypeGPIO +#define MAP_PinTypeGPIO \ + ROM_PinTypeGPIO +#else +#define MAP_PinTypeGPIO \ + PinTypeGPIO +#endif +#ifdef ROM_PinTypeADC +#define MAP_PinTypeADC \ + ROM_PinTypeADC +#else +#define MAP_PinTypeADC \ + PinTypeADC +#endif +#ifdef ROM_PinTypeSDHost +#define MAP_PinTypeSDHost \ + ROM_PinTypeSDHost +#else +#define MAP_PinTypeSDHost \ + PinTypeSDHost +#endif +#ifdef ROM_PinHysteresisSet +#define MAP_PinHysteresisSet \ + ROM_PinHysteresisSet +#else +#define MAP_PinHysteresisSet \ + PinHysteresisSet +#endif +#ifdef ROM_PinLockLevelSet +#define MAP_PinLockLevelSet \ + ROM_PinLockLevelSet +#else +#define MAP_PinLockLevelSet \ + PinLockLevelSet +#endif +#ifdef ROM_PinLock +#define MAP_PinLock \ + ROM_PinLock +#else +#define MAP_PinLock \ + PinLock +#endif +#ifdef ROM_PinUnlock +#define MAP_PinUnlock \ + ROM_PinUnlock +#else +#define MAP_PinUnlock \ + PinUnlock +#endif + +//***************************************************************************** +// +// Macros for the SYSTICK API. +// +//***************************************************************************** +#ifdef ROM_SysTickEnable +#define MAP_SysTickEnable \ + ROM_SysTickEnable +#else +#define MAP_SysTickEnable \ + SysTickEnable +#endif +#ifdef ROM_SysTickDisable +#define MAP_SysTickDisable \ + ROM_SysTickDisable +#else +#define MAP_SysTickDisable \ + SysTickDisable +#endif +#ifdef ROM_SysTickIntRegister +#define MAP_SysTickIntRegister \ + ROM_SysTickIntRegister +#else +#define MAP_SysTickIntRegister \ + SysTickIntRegister +#endif +#ifdef ROM_SysTickIntUnregister +#define MAP_SysTickIntUnregister \ + ROM_SysTickIntUnregister +#else +#define MAP_SysTickIntUnregister \ + SysTickIntUnregister +#endif +#ifdef ROM_SysTickIntEnable +#define MAP_SysTickIntEnable \ + ROM_SysTickIntEnable +#else +#define MAP_SysTickIntEnable \ + SysTickIntEnable +#endif +#ifdef ROM_SysTickIntDisable +#define MAP_SysTickIntDisable \ + ROM_SysTickIntDisable +#else +#define MAP_SysTickIntDisable \ + SysTickIntDisable +#endif +#ifdef ROM_SysTickPeriodSet +#define MAP_SysTickPeriodSet \ + ROM_SysTickPeriodSet +#else +#define MAP_SysTickPeriodSet \ + SysTickPeriodSet +#endif +#ifdef ROM_SysTickPeriodGet +#define MAP_SysTickPeriodGet \ + ROM_SysTickPeriodGet +#else +#define MAP_SysTickPeriodGet \ + SysTickPeriodGet +#endif +#ifdef ROM_SysTickValueGet +#define MAP_SysTickValueGet \ + ROM_SysTickValueGet +#else +#define MAP_SysTickValueGet \ + SysTickValueGet +#endif + +//***************************************************************************** +// +// Macros for the UTILS API. +// +//***************************************************************************** +#if defined(USE_CC3200_ROM_DRV_API) || \ + defined(USE_CC3220_ROM_DRV_API) +#define MAP_UtilsDelay \ + ROM_UtilsDelay +#else +#define MAP_UtilsDelay \ + UtilsDelay +#endif + +//***************************************************************************** +// +// Macros for the I2S API. +// +//***************************************************************************** +#ifdef ROM_I2SEnable +#define MAP_I2SEnable \ + ROM_I2SEnable +#else +#define MAP_I2SEnable \ + I2SEnable +#endif +#ifdef ROM_I2SDisable +#define MAP_I2SDisable \ + ROM_I2SDisable +#else +#define MAP_I2SDisable \ + I2SDisable +#endif +#ifdef ROM_I2SDataPut +#define MAP_I2SDataPut \ + ROM_I2SDataPut +#else +#define MAP_I2SDataPut \ + I2SDataPut +#endif +#ifdef ROM_I2SDataPutNonBlocking +#define MAP_I2SDataPutNonBlocking \ + ROM_I2SDataPutNonBlocking +#else +#define MAP_I2SDataPutNonBlocking \ + I2SDataPutNonBlocking +#endif +#ifdef ROM_I2SDataGet +#define MAP_I2SDataGet \ + ROM_I2SDataGet +#else +#define MAP_I2SDataGet \ + I2SDataGet +#endif +#ifdef ROM_I2SDataGetNonBlocking +#define MAP_I2SDataGetNonBlocking \ + ROM_I2SDataGetNonBlocking +#else +#define MAP_I2SDataGetNonBlocking \ + I2SDataGetNonBlocking +#endif +#ifdef ROM_I2SConfigSetExpClk +#define MAP_I2SConfigSetExpClk \ + ROM_I2SConfigSetExpClk +#else +#define MAP_I2SConfigSetExpClk \ + I2SConfigSetExpClk +#endif +#ifdef ROM_I2STxFIFOEnable +#define MAP_I2STxFIFOEnable \ + ROM_I2STxFIFOEnable +#else +#define MAP_I2STxFIFOEnable \ + I2STxFIFOEnable +#endif +#ifdef ROM_I2STxFIFODisable +#define MAP_I2STxFIFODisable \ + ROM_I2STxFIFODisable +#else +#define MAP_I2STxFIFODisable \ + I2STxFIFODisable +#endif +#ifdef ROM_I2SRxFIFOEnable +#define MAP_I2SRxFIFOEnable \ + ROM_I2SRxFIFOEnable +#else +#define MAP_I2SRxFIFOEnable \ + I2SRxFIFOEnable +#endif +#ifdef ROM_I2SRxFIFODisable +#define MAP_I2SRxFIFODisable \ + ROM_I2SRxFIFODisable +#else +#define MAP_I2SRxFIFODisable \ + I2SRxFIFODisable +#endif +#ifdef ROM_I2STxFIFOStatusGet +#define MAP_I2STxFIFOStatusGet \ + ROM_I2STxFIFOStatusGet +#else +#define MAP_I2STxFIFOStatusGet \ + I2STxFIFOStatusGet +#endif +#ifdef ROM_I2SRxFIFOStatusGet +#define MAP_I2SRxFIFOStatusGet \ + ROM_I2SRxFIFOStatusGet +#else +#define MAP_I2SRxFIFOStatusGet \ + I2SRxFIFOStatusGet +#endif +#ifdef ROM_I2SSerializerConfig +#define MAP_I2SSerializerConfig \ + ROM_I2SSerializerConfig +#else +#define MAP_I2SSerializerConfig \ + I2SSerializerConfig +#endif +#ifdef ROM_I2SIntEnable +#define MAP_I2SIntEnable \ + ROM_I2SIntEnable +#else +#define MAP_I2SIntEnable \ + I2SIntEnable +#endif +#ifdef ROM_I2SIntDisable +#define MAP_I2SIntDisable \ + ROM_I2SIntDisable +#else +#define MAP_I2SIntDisable \ + I2SIntDisable +#endif +#ifdef ROM_I2SIntStatus +#define MAP_I2SIntStatus \ + ROM_I2SIntStatus +#else +#define MAP_I2SIntStatus \ + I2SIntStatus +#endif +#ifdef ROM_I2SIntClear +#define MAP_I2SIntClear \ + ROM_I2SIntClear +#else +#define MAP_I2SIntClear \ + I2SIntClear +#endif +#ifdef ROM_I2SIntRegister +#define MAP_I2SIntRegister \ + ROM_I2SIntRegister +#else +#define MAP_I2SIntRegister \ + I2SIntRegister +#endif +#ifdef ROM_I2SIntUnregister +#define MAP_I2SIntUnregister \ + ROM_I2SIntUnregister +#else +#define MAP_I2SIntUnregister \ + I2SIntUnregister +#endif +#ifdef ROM_I2STxActiveSlotSet +#define MAP_I2STxActiveSlotSet \ + ROM_I2STxActiveSlotSet +#else +#define MAP_I2STxActiveSlotSet \ + I2STxActiveSlotSet +#endif +#ifdef ROM_I2SRxActiveSlotSet +#define MAP_I2SRxActiveSlotSet \ + ROM_I2SRxActiveSlotSet +#else +#define MAP_I2SRxActiveSlotSet \ + I2SRxActiveSlotSet +#endif + +//***************************************************************************** +// +// Macros for the GPIO API. +// +//***************************************************************************** +#ifdef ROM_GPIODirModeSet +#define MAP_GPIODirModeSet \ + ROM_GPIODirModeSet +#else +#define MAP_GPIODirModeSet \ + GPIODirModeSet +#endif +#ifdef ROM_GPIODirModeGet +#define MAP_GPIODirModeGet \ + ROM_GPIODirModeGet +#else +#define MAP_GPIODirModeGet \ + GPIODirModeGet +#endif +#ifdef ROM_GPIOIntTypeSet +#define MAP_GPIOIntTypeSet \ + ROM_GPIOIntTypeSet +#else +#define MAP_GPIOIntTypeSet \ + GPIOIntTypeSet +#endif +#ifdef ROM_GPIODMATriggerEnable +#define MAP_GPIODMATriggerEnable \ + ROM_GPIODMATriggerEnable +#else +#define MAP_GPIODMATriggerEnable \ + GPIODMATriggerEnable +#endif +#ifdef ROM_GPIODMATriggerDisable +#define MAP_GPIODMATriggerDisable \ + ROM_GPIODMATriggerDisable +#else +#define MAP_GPIODMATriggerDisable \ + GPIODMATriggerDisable +#endif +#ifdef ROM_GPIOIntTypeGet +#define MAP_GPIOIntTypeGet \ + ROM_GPIOIntTypeGet +#else +#define MAP_GPIOIntTypeGet \ + GPIOIntTypeGet +#endif +#ifdef ROM_GPIOIntEnable +#define MAP_GPIOIntEnable \ + ROM_GPIOIntEnable +#else +#define MAP_GPIOIntEnable \ + GPIOIntEnable +#endif +#ifdef ROM_GPIOIntDisable +#define MAP_GPIOIntDisable \ + ROM_GPIOIntDisable +#else +#define MAP_GPIOIntDisable \ + GPIOIntDisable +#endif +#ifdef ROM_GPIOIntStatus +#define MAP_GPIOIntStatus \ + ROM_GPIOIntStatus +#else +#define MAP_GPIOIntStatus \ + GPIOIntStatus +#endif +#ifdef ROM_GPIOIntClear +#define MAP_GPIOIntClear \ + ROM_GPIOIntClear +#else +#define MAP_GPIOIntClear \ + GPIOIntClear +#endif +#ifdef ROM_GPIOIntRegister +#define MAP_GPIOIntRegister \ + ROM_GPIOIntRegister +#else +#define MAP_GPIOIntRegister \ + GPIOIntRegister +#endif +#ifdef ROM_GPIOIntUnregister +#define MAP_GPIOIntUnregister \ + ROM_GPIOIntUnregister +#else +#define MAP_GPIOIntUnregister \ + GPIOIntUnregister +#endif +#ifdef ROM_GPIOPinRead +#define MAP_GPIOPinRead \ + ROM_GPIOPinRead +#else +#define MAP_GPIOPinRead \ + GPIOPinRead +#endif +#ifdef ROM_GPIOPinWrite +#define MAP_GPIOPinWrite \ + ROM_GPIOPinWrite +#else +#define MAP_GPIOPinWrite \ + GPIOPinWrite +#endif + +//***************************************************************************** +// +// Macros for the AES API. +// +//***************************************************************************** +#ifdef ROM_AESConfigSet +#define MAP_AESConfigSet \ + ROM_AESConfigSet +#else +#define MAP_AESConfigSet \ + AESConfigSet +#endif +#ifdef ROM_AESKey1Set +#define MAP_AESKey1Set \ + ROM_AESKey1Set +#else +#define MAP_AESKey1Set \ + AESKey1Set +#endif +#ifdef ROM_AESKey2Set +#define MAP_AESKey2Set \ + ROM_AESKey2Set +#else +#define MAP_AESKey2Set \ + AESKey2Set +#endif +#ifdef ROM_AESKey3Set +#define MAP_AESKey3Set \ + ROM_AESKey3Set +#else +#define MAP_AESKey3Set \ + AESKey3Set +#endif +#ifdef ROM_AESIVSet +#define MAP_AESIVSet \ + ROM_AESIVSet +#else +#define MAP_AESIVSet \ + AESIVSet +#endif +#ifdef ROM_AESTagRead +#define MAP_AESTagRead \ + ROM_AESTagRead +#else +#define MAP_AESTagRead \ + AESTagRead +#endif +#ifdef ROM_AESDataLengthSet +#define MAP_AESDataLengthSet \ + ROM_AESDataLengthSet +#else +#define MAP_AESDataLengthSet \ + AESDataLengthSet +#endif +#ifdef ROM_AESAuthDataLengthSet +#define MAP_AESAuthDataLengthSet \ + ROM_AESAuthDataLengthSet +#else +#define MAP_AESAuthDataLengthSet \ + AESAuthDataLengthSet +#endif +#ifdef ROM_AESDataReadNonBlocking +#define MAP_AESDataReadNonBlocking \ + ROM_AESDataReadNonBlocking +#else +#define MAP_AESDataReadNonBlocking \ + AESDataReadNonBlocking +#endif +#ifdef ROM_AESDataRead +#define MAP_AESDataRead \ + ROM_AESDataRead +#else +#define MAP_AESDataRead \ + AESDataRead +#endif +#ifdef ROM_AESDataWriteNonBlocking +#define MAP_AESDataWriteNonBlocking \ + ROM_AESDataWriteNonBlocking +#else +#define MAP_AESDataWriteNonBlocking \ + AESDataWriteNonBlocking +#endif +#ifdef ROM_AESDataWrite +#define MAP_AESDataWrite \ + ROM_AESDataWrite +#else +#define MAP_AESDataWrite \ + AESDataWrite +#endif +#ifdef ROM_AESDataProcess +#define MAP_AESDataProcess \ + ROM_AESDataProcess +#else +#define MAP_AESDataProcess \ + AESDataProcess +#endif +#ifdef ROM_AESDataMAC +#define MAP_AESDataMAC \ + ROM_AESDataMAC +#else +#define MAP_AESDataMAC \ + AESDataMAC +#endif +#ifdef ROM_AESDataProcessAE +#define MAP_AESDataProcessAE \ + ROM_AESDataProcessAE +#else +#define MAP_AESDataProcessAE \ + AESDataProcessAE +#endif +#ifdef ROM_AESIntStatus +#define MAP_AESIntStatus \ + ROM_AESIntStatus +#else +#define MAP_AESIntStatus \ + AESIntStatus +#endif +#ifdef ROM_AESIntEnable +#define MAP_AESIntEnable \ + ROM_AESIntEnable +#else +#define MAP_AESIntEnable \ + AESIntEnable +#endif +#ifdef ROM_AESIntDisable +#define MAP_AESIntDisable \ + ROM_AESIntDisable +#else +#define MAP_AESIntDisable \ + AESIntDisable +#endif +#ifdef ROM_AESIntClear +#define MAP_AESIntClear \ + ROM_AESIntClear +#else +#define MAP_AESIntClear \ + AESIntClear +#endif +#ifdef ROM_AESIntRegister +#define MAP_AESIntRegister \ + ROM_AESIntRegister +#else +#define MAP_AESIntRegister \ + AESIntRegister +#endif +#ifdef ROM_AESIntUnregister +#define MAP_AESIntUnregister \ + ROM_AESIntUnregister +#else +#define MAP_AESIntUnregister \ + AESIntUnregister +#endif +#ifdef ROM_AESDMAEnable +#define MAP_AESDMAEnable \ + ROM_AESDMAEnable +#else +#define MAP_AESDMAEnable \ + AESDMAEnable +#endif +#ifdef ROM_AESDMADisable +#define MAP_AESDMADisable \ + ROM_AESDMADisable +#else +#define MAP_AESDMADisable \ + AESDMADisable +#endif +#ifdef ROM_AESIVGet +#define MAP_AESIVGet \ + ROM_AESIVGet +#else +#define MAP_AESIVGet \ + AESIVGet +#endif + +//***************************************************************************** +// +// Macros for the DES API. +// +//***************************************************************************** +#ifdef ROM_DESConfigSet +#define MAP_DESConfigSet \ + ROM_DESConfigSet +#else +#define MAP_DESConfigSet \ + DESConfigSet +#endif +#ifdef ROM_DESDataRead +#define MAP_DESDataRead \ + ROM_DESDataRead +#else +#define MAP_DESDataRead \ + DESDataRead +#endif +#ifdef ROM_DESDataReadNonBlocking +#define MAP_DESDataReadNonBlocking \ + ROM_DESDataReadNonBlocking +#else +#define MAP_DESDataReadNonBlocking \ + DESDataReadNonBlocking +#endif +#ifdef ROM_DESDataProcess +#define MAP_DESDataProcess \ + ROM_DESDataProcess +#else +#define MAP_DESDataProcess \ + DESDataProcess +#endif +#ifdef ROM_DESDataWrite +#define MAP_DESDataWrite \ + ROM_DESDataWrite +#else +#define MAP_DESDataWrite \ + DESDataWrite +#endif +#ifdef ROM_DESDataWriteNonBlocking +#define MAP_DESDataWriteNonBlocking \ + ROM_DESDataWriteNonBlocking +#else +#define MAP_DESDataWriteNonBlocking \ + DESDataWriteNonBlocking +#endif +#ifdef ROM_DESDMADisable +#define MAP_DESDMADisable \ + ROM_DESDMADisable +#else +#define MAP_DESDMADisable \ + DESDMADisable +#endif +#ifdef ROM_DESDMAEnable +#define MAP_DESDMAEnable \ + ROM_DESDMAEnable +#else +#define MAP_DESDMAEnable \ + DESDMAEnable +#endif +#ifdef ROM_DESIntClear +#define MAP_DESIntClear \ + ROM_DESIntClear +#else +#define MAP_DESIntClear \ + DESIntClear +#endif +#ifdef ROM_DESIntDisable +#define MAP_DESIntDisable \ + ROM_DESIntDisable +#else +#define MAP_DESIntDisable \ + DESIntDisable +#endif +#ifdef ROM_DESIntEnable +#define MAP_DESIntEnable \ + ROM_DESIntEnable +#else +#define MAP_DESIntEnable \ + DESIntEnable +#endif +#ifdef ROM_DESIntRegister +#define MAP_DESIntRegister \ + ROM_DESIntRegister +#else +#define MAP_DESIntRegister \ + DESIntRegister +#endif +#ifdef ROM_DESIntStatus +#define MAP_DESIntStatus \ + ROM_DESIntStatus +#else +#define MAP_DESIntStatus \ + DESIntStatus +#endif +#ifdef ROM_DESIntUnregister +#define MAP_DESIntUnregister \ + ROM_DESIntUnregister +#else +#define MAP_DESIntUnregister \ + DESIntUnregister +#endif +#ifdef ROM_DESIVSet +#define MAP_DESIVSet \ + ROM_DESIVSet +#else +#define MAP_DESIVSet \ + DESIVSet +#endif +#ifdef ROM_DESKeySet +#define MAP_DESKeySet \ + ROM_DESKeySet +#else +#define MAP_DESKeySet \ + DESKeySet +#endif +#ifdef ROM_DESDataLengthSet +#define MAP_DESDataLengthSet \ + ROM_DESDataLengthSet +#else +#define MAP_DESDataLengthSet \ + DESDataLengthSet +#endif + +//***************************************************************************** +// +// Macros for the SHAMD5 API. +// +//***************************************************************************** +#ifdef ROM_SHAMD5ConfigSet +#define MAP_SHAMD5ConfigSet \ + ROM_SHAMD5ConfigSet +#else +#define MAP_SHAMD5ConfigSet \ + SHAMD5ConfigSet +#endif +#ifdef ROM_SHAMD5DataProcess +#define MAP_SHAMD5DataProcess \ + ROM_SHAMD5DataProcess +#else +#define MAP_SHAMD5DataProcess \ + SHAMD5DataProcess +#endif +#ifdef ROM_SHAMD5DataWrite +#define MAP_SHAMD5DataWrite \ + ROM_SHAMD5DataWrite +#else +#define MAP_SHAMD5DataWrite \ + SHAMD5DataWrite +#endif +#ifdef ROM_SHAMD5DataWriteNonBlocking +#define MAP_SHAMD5DataWriteNonBlocking \ + ROM_SHAMD5DataWriteNonBlocking +#else +#define MAP_SHAMD5DataWriteNonBlocking \ + SHAMD5DataWriteNonBlocking +#endif +#ifdef ROM_SHAMD5DMADisable +#define MAP_SHAMD5DMADisable \ + ROM_SHAMD5DMADisable +#else +#define MAP_SHAMD5DMADisable \ + SHAMD5DMADisable +#endif +#ifdef ROM_SHAMD5DMAEnable +#define MAP_SHAMD5DMAEnable \ + ROM_SHAMD5DMAEnable +#else +#define MAP_SHAMD5DMAEnable \ + SHAMD5DMAEnable +#endif +#ifdef ROM_SHAMD5DataLengthSet +#define MAP_SHAMD5DataLengthSet \ + ROM_SHAMD5DataLengthSet +#else +#define MAP_SHAMD5DataLengthSet \ + SHAMD5DataLengthSet +#endif +#ifdef ROM_SHAMD5HMACKeySet +#define MAP_SHAMD5HMACKeySet \ + ROM_SHAMD5HMACKeySet +#else +#define MAP_SHAMD5HMACKeySet \ + SHAMD5HMACKeySet +#endif +#ifdef ROM_SHAMD5HMACPPKeyGenerate +#define MAP_SHAMD5HMACPPKeyGenerate \ + ROM_SHAMD5HMACPPKeyGenerate +#else +#define MAP_SHAMD5HMACPPKeyGenerate \ + SHAMD5HMACPPKeyGenerate +#endif +#ifdef ROM_SHAMD5HMACPPKeySet +#define MAP_SHAMD5HMACPPKeySet \ + ROM_SHAMD5HMACPPKeySet +#else +#define MAP_SHAMD5HMACPPKeySet \ + SHAMD5HMACPPKeySet +#endif +#ifdef ROM_SHAMD5HMACProcess +#define MAP_SHAMD5HMACProcess \ + ROM_SHAMD5HMACProcess +#else +#define MAP_SHAMD5HMACProcess \ + SHAMD5HMACProcess +#endif +#ifdef ROM_SHAMD5IntClear +#define MAP_SHAMD5IntClear \ + ROM_SHAMD5IntClear +#else +#define MAP_SHAMD5IntClear \ + SHAMD5IntClear +#endif +#ifdef ROM_SHAMD5IntDisable +#define MAP_SHAMD5IntDisable \ + ROM_SHAMD5IntDisable +#else +#define MAP_SHAMD5IntDisable \ + SHAMD5IntDisable +#endif +#ifdef ROM_SHAMD5IntEnable +#define MAP_SHAMD5IntEnable \ + ROM_SHAMD5IntEnable +#else +#define MAP_SHAMD5IntEnable \ + SHAMD5IntEnable +#endif +#ifdef ROM_SHAMD5IntRegister +#define MAP_SHAMD5IntRegister \ + ROM_SHAMD5IntRegister +#else +#define MAP_SHAMD5IntRegister \ + SHAMD5IntRegister +#endif +#ifdef ROM_SHAMD5IntStatus +#define MAP_SHAMD5IntStatus \ + ROM_SHAMD5IntStatus +#else +#define MAP_SHAMD5IntStatus \ + SHAMD5IntStatus +#endif +#ifdef ROM_SHAMD5IntUnregister +#define MAP_SHAMD5IntUnregister \ + ROM_SHAMD5IntUnregister +#else +#define MAP_SHAMD5IntUnregister \ + SHAMD5IntUnregister +#endif +#ifdef ROM_SHAMD5ResultRead +#define MAP_SHAMD5ResultRead \ + ROM_SHAMD5ResultRead +#else +#define MAP_SHAMD5ResultRead \ + SHAMD5ResultRead +#endif + +//***************************************************************************** +// +// Macros for the CRC API. +// +//***************************************************************************** +#ifdef ROM_CRCConfigSet +#define MAP_CRCConfigSet \ + ROM_CRCConfigSet +#else +#define MAP_CRCConfigSet \ + CRCConfigSet +#endif +#ifdef ROM_CRCDataProcess +#define MAP_CRCDataProcess \ + ROM_CRCDataProcess +#else +#define MAP_CRCDataProcess \ + CRCDataProcess +#endif +#ifdef ROM_CRCDataWrite +#define MAP_CRCDataWrite \ + ROM_CRCDataWrite +#else +#define MAP_CRCDataWrite \ + CRCDataWrite +#endif +#ifdef ROM_CRCResultRead +#define MAP_CRCResultRead \ + ROM_CRCResultRead +#else +#define MAP_CRCResultRead \ + CRCResultRead +#endif +#ifdef ROM_CRCSeedSet +#define MAP_CRCSeedSet \ + ROM_CRCSeedSet +#else +#define MAP_CRCSeedSet \ + CRCSeedSet +#endif + +//***************************************************************************** +// +// Macros for the SDHOST API. +// +//***************************************************************************** +#ifdef ROM_SDHostCmdReset +#define MAP_SDHostCmdReset \ + ROM_SDHostCmdReset +#else +#define MAP_SDHostCmdReset \ + SDHostCmdReset +#endif +#ifdef ROM_SDHostInit +#define MAP_SDHostInit \ + ROM_SDHostInit +#else +#define MAP_SDHostInit \ + SDHostInit +#endif +#ifdef ROM_SDHostCmdSend +#define MAP_SDHostCmdSend \ + ROM_SDHostCmdSend +#else +#define MAP_SDHostCmdSend \ + SDHostCmdSend +#endif +#ifdef ROM_SDHostIntRegister +#define MAP_SDHostIntRegister \ + ROM_SDHostIntRegister +#else +#define MAP_SDHostIntRegister \ + SDHostIntRegister +#endif +#ifdef ROM_SDHostIntUnregister +#define MAP_SDHostIntUnregister \ + ROM_SDHostIntUnregister +#else +#define MAP_SDHostIntUnregister \ + SDHostIntUnregister +#endif +#ifdef ROM_SDHostIntEnable +#define MAP_SDHostIntEnable \ + ROM_SDHostIntEnable +#else +#define MAP_SDHostIntEnable \ + SDHostIntEnable +#endif +#ifdef ROM_SDHostIntDisable +#define MAP_SDHostIntDisable \ + ROM_SDHostIntDisable +#else +#define MAP_SDHostIntDisable \ + SDHostIntDisable +#endif +#ifdef ROM_SDHostIntStatus +#define MAP_SDHostIntStatus \ + ROM_SDHostIntStatus +#else +#define MAP_SDHostIntStatus \ + SDHostIntStatus +#endif +#ifdef ROM_SDHostIntClear +#define MAP_SDHostIntClear \ + ROM_SDHostIntClear +#else +#define MAP_SDHostIntClear \ + SDHostIntClear +#endif +#ifdef ROM_SDHostRespGet +#define MAP_SDHostRespGet \ + ROM_SDHostRespGet +#else +#define MAP_SDHostRespGet \ + SDHostRespGet +#endif +#ifdef ROM_SDHostBlockSizeSet +#define MAP_SDHostBlockSizeSet \ + ROM_SDHostBlockSizeSet +#else +#define MAP_SDHostBlockSizeSet \ + SDHostBlockSizeSet +#endif +#ifdef ROM_SDHostBlockCountSet +#define MAP_SDHostBlockCountSet \ + ROM_SDHostBlockCountSet +#else +#define MAP_SDHostBlockCountSet \ + SDHostBlockCountSet +#endif +#ifdef ROM_SDHostDataNonBlockingWrite +#define MAP_SDHostDataNonBlockingWrite \ + ROM_SDHostDataNonBlockingWrite +#else +#define MAP_SDHostDataNonBlockingWrite \ + SDHostDataNonBlockingWrite +#endif +#ifdef ROM_SDHostDataNonBlockingRead +#define MAP_SDHostDataNonBlockingRead \ + ROM_SDHostDataNonBlockingRead +#else +#define MAP_SDHostDataNonBlockingRead \ + SDHostDataNonBlockingRead +#endif +#ifdef ROM_SDHostDataWrite +#define MAP_SDHostDataWrite \ + ROM_SDHostDataWrite +#else +#define MAP_SDHostDataWrite \ + SDHostDataWrite +#endif +#ifdef ROM_SDHostDataRead +#define MAP_SDHostDataRead \ + ROM_SDHostDataRead +#else +#define MAP_SDHostDataRead \ + SDHostDataRead +#endif +#ifdef ROM_SDHostSetExpClk +#define MAP_SDHostSetExpClk \ + ROM_SDHostSetExpClk +#else +#define MAP_SDHostSetExpClk \ + SDHostSetExpClk +#endif +#ifdef ROM_SDHostCardErrorMaskSet +#define MAP_SDHostCardErrorMaskSet \ + ROM_SDHostCardErrorMaskSet +#else +#define MAP_SDHostCardErrorMaskSet \ + SDHostCardErrorMaskSet +#endif +#ifdef ROM_SDHostCardErrorMaskGet +#define MAP_SDHostCardErrorMaskGet \ + ROM_SDHostCardErrorMaskGet +#else +#define MAP_SDHostCardErrorMaskGet \ + SDHostCardErrorMaskGet +#endif + +//***************************************************************************** +// +// Macros for the PRCM API. +// +//***************************************************************************** +#ifdef ROM_PRCMMCUReset +#define MAP_PRCMMCUReset \ + ROM_PRCMMCUReset +#else +#define MAP_PRCMMCUReset \ + PRCMMCUReset +#endif +#ifdef ROM_PRCMSysResetCauseGet +#define MAP_PRCMSysResetCauseGet \ + ROM_PRCMSysResetCauseGet +#else +#define MAP_PRCMSysResetCauseGet \ + PRCMSysResetCauseGet +#endif +#ifdef ROM_PRCMPeripheralClkEnable +#define MAP_PRCMPeripheralClkEnable \ + ROM_PRCMPeripheralClkEnable +#else +#define MAP_PRCMPeripheralClkEnable \ + PRCMPeripheralClkEnable +#endif +#ifdef ROM_PRCMPeripheralClkDisable +#define MAP_PRCMPeripheralClkDisable \ + ROM_PRCMPeripheralClkDisable +#else +#define MAP_PRCMPeripheralClkDisable \ + PRCMPeripheralClkDisable +#endif +#ifdef ROM_PRCMPeripheralReset +#define MAP_PRCMPeripheralReset \ + ROM_PRCMPeripheralReset +#else +#define MAP_PRCMPeripheralReset \ + PRCMPeripheralReset +#endif +#ifdef ROM_PRCMPeripheralStatusGet +#define MAP_PRCMPeripheralStatusGet \ + ROM_PRCMPeripheralStatusGet +#else +#define MAP_PRCMPeripheralStatusGet \ + PRCMPeripheralStatusGet +#endif +#ifdef ROM_PRCMI2SClockFreqSet +#define MAP_PRCMI2SClockFreqSet \ + ROM_PRCMI2SClockFreqSet +#else +#define MAP_PRCMI2SClockFreqSet \ + PRCMI2SClockFreqSet +#endif +#ifdef ROM_PRCMPeripheralClockGet +#define MAP_PRCMPeripheralClockGet \ + ROM_PRCMPeripheralClockGet +#else +#define MAP_PRCMPeripheralClockGet \ + PRCMPeripheralClockGet +#endif +#ifdef ROM_PRCMSleepEnter +#define MAP_PRCMSleepEnter \ + ROM_PRCMSleepEnter +#else +#define MAP_PRCMSleepEnter \ + PRCMSleepEnter +#endif +#ifdef ROM_PRCMSRAMRetentionEnable +#define MAP_PRCMSRAMRetentionEnable \ + ROM_PRCMSRAMRetentionEnable +#else +#define MAP_PRCMSRAMRetentionEnable \ + PRCMSRAMRetentionEnable +#endif +#ifdef ROM_PRCMSRAMRetentionDisable +#define MAP_PRCMSRAMRetentionDisable \ + ROM_PRCMSRAMRetentionDisable +#else +#define MAP_PRCMSRAMRetentionDisable \ + PRCMSRAMRetentionDisable +#endif +#ifdef ROM_PRCMLPDSEnter +#define MAP_PRCMLPDSEnter \ + ROM_PRCMLPDSEnter +#else +#define MAP_PRCMLPDSEnter \ + PRCMLPDSEnter +#endif +#ifdef ROM_PRCMLPDSIntervalSet +#define MAP_PRCMLPDSIntervalSet \ + ROM_PRCMLPDSIntervalSet +#else +#define MAP_PRCMLPDSIntervalSet \ + PRCMLPDSIntervalSet +#endif +#ifdef ROM_PRCMLPDSWakeupSourceEnable +#define MAP_PRCMLPDSWakeupSourceEnable \ + ROM_PRCMLPDSWakeupSourceEnable +#else +#define MAP_PRCMLPDSWakeupSourceEnable \ + PRCMLPDSWakeupSourceEnable +#endif +#ifdef ROM_PRCMLPDSWakeupCauseGet +#define MAP_PRCMLPDSWakeupCauseGet \ + ROM_PRCMLPDSWakeupCauseGet +#else +#define MAP_PRCMLPDSWakeupCauseGet \ + PRCMLPDSWakeupCauseGet +#endif +#ifdef ROM_PRCMLPDSWakeUpGPIOSelect +#define MAP_PRCMLPDSWakeUpGPIOSelect \ + ROM_PRCMLPDSWakeUpGPIOSelect +#else +#define MAP_PRCMLPDSWakeUpGPIOSelect \ + PRCMLPDSWakeUpGPIOSelect +#endif +#ifdef ROM_PRCMLPDSWakeupSourceDisable +#define MAP_PRCMLPDSWakeupSourceDisable \ + ROM_PRCMLPDSWakeupSourceDisable +#else +#define MAP_PRCMLPDSWakeupSourceDisable \ + PRCMLPDSWakeupSourceDisable +#endif +#ifdef ROM_PRCMHibernateEnter +#define MAP_PRCMHibernateEnter \ + ROM_PRCMHibernateEnter +#else +#define MAP_PRCMHibernateEnter \ + PRCMHibernateEnter +#endif +#ifdef ROM_PRCMHibernateWakeupSourceEnable +#define MAP_PRCMHibernateWakeupSourceEnable \ + ROM_PRCMHibernateWakeupSourceEnable +#else +#define MAP_PRCMHibernateWakeupSourceEnable \ + PRCMHibernateWakeupSourceEnable +#endif +#ifdef ROM_PRCMHibernateWakeupCauseGet +#define MAP_PRCMHibernateWakeupCauseGet \ + ROM_PRCMHibernateWakeupCauseGet +#else +#define MAP_PRCMHibernateWakeupCauseGet \ + PRCMHibernateWakeupCauseGet +#endif +#ifdef ROM_PRCMHibernateWakeUpGPIOSelect +#define MAP_PRCMHibernateWakeUpGPIOSelect \ + ROM_PRCMHibernateWakeUpGPIOSelect +#else +#define MAP_PRCMHibernateWakeUpGPIOSelect \ + PRCMHibernateWakeUpGPIOSelect +#endif +#ifdef ROM_PRCMHibernateWakeupSourceDisable +#define MAP_PRCMHibernateWakeupSourceDisable \ + ROM_PRCMHibernateWakeupSourceDisable +#else +#define MAP_PRCMHibernateWakeupSourceDisable \ + PRCMHibernateWakeupSourceDisable +#endif +#ifdef ROM_PRCMHibernateIntervalSet +#define MAP_PRCMHibernateIntervalSet \ + ROM_PRCMHibernateIntervalSet +#else +#define MAP_PRCMHibernateIntervalSet \ + PRCMHibernateIntervalSet +#endif +#ifdef ROM_PRCMSlowClkCtrGet +#define MAP_PRCMSlowClkCtrGet \ + ROM_PRCMSlowClkCtrGet +#else +#define MAP_PRCMSlowClkCtrGet \ + PRCMSlowClkCtrGet +#endif +#ifdef ROM_PRCMSlowClkCtrMatchSet +#define MAP_PRCMSlowClkCtrMatchSet \ + ROM_PRCMSlowClkCtrMatchSet +#else +#define MAP_PRCMSlowClkCtrMatchSet \ + PRCMSlowClkCtrMatchSet +#endif +#ifdef ROM_PRCMSlowClkCtrMatchGet +#define MAP_PRCMSlowClkCtrMatchGet \ + ROM_PRCMSlowClkCtrMatchGet +#else +#define MAP_PRCMSlowClkCtrMatchGet \ + PRCMSlowClkCtrMatchGet +#endif +#ifdef ROM_PRCMOCRRegisterWrite +#define MAP_PRCMOCRRegisterWrite \ + ROM_PRCMOCRRegisterWrite +#else +#define MAP_PRCMOCRRegisterWrite \ + PRCMOCRRegisterWrite +#endif +#ifdef ROM_PRCMOCRRegisterRead +#define MAP_PRCMOCRRegisterRead \ + ROM_PRCMOCRRegisterRead +#else +#define MAP_PRCMOCRRegisterRead \ + PRCMOCRRegisterRead +#endif +#ifdef ROM_PRCMIntRegister +#define MAP_PRCMIntRegister \ + ROM_PRCMIntRegister +#else +#define MAP_PRCMIntRegister \ + PRCMIntRegister +#endif +#ifdef ROM_PRCMIntUnregister +#define MAP_PRCMIntUnregister \ + ROM_PRCMIntUnregister +#else +#define MAP_PRCMIntUnregister \ + PRCMIntUnregister +#endif +#ifdef ROM_PRCMIntEnable +#define MAP_PRCMIntEnable \ + ROM_PRCMIntEnable +#else +#define MAP_PRCMIntEnable \ + PRCMIntEnable +#endif +#ifdef ROM_PRCMIntDisable +#define MAP_PRCMIntDisable \ + ROM_PRCMIntDisable +#else +#define MAP_PRCMIntDisable \ + PRCMIntDisable +#endif +#ifdef ROM_PRCMIntStatus +#define MAP_PRCMIntStatus \ + ROM_PRCMIntStatus +#else +#define MAP_PRCMIntStatus \ + PRCMIntStatus +#endif +#ifdef ROM_PRCMRTCInUseSet +#define MAP_PRCMRTCInUseSet \ + ROM_PRCMRTCInUseSet +#else +#define MAP_PRCMRTCInUseSet \ + PRCMRTCInUseSet +#endif +#ifdef ROM_PRCMRTCInUseGet +#define MAP_PRCMRTCInUseGet \ + ROM_PRCMRTCInUseGet +#else +#define MAP_PRCMRTCInUseGet \ + PRCMRTCInUseGet +#endif +#ifdef ROM_PRCMRTCSet +#define MAP_PRCMRTCSet \ + ROM_PRCMRTCSet +#else +#define MAP_PRCMRTCSet \ + PRCMRTCSet +#endif +#ifdef ROM_PRCMRTCGet +#define MAP_PRCMRTCGet \ + ROM_PRCMRTCGet +#else +#define MAP_PRCMRTCGet \ + PRCMRTCGet +#endif +#ifdef ROM_PRCMRTCMatchSet +#define MAP_PRCMRTCMatchSet \ + ROM_PRCMRTCMatchSet +#else +#define MAP_PRCMRTCMatchSet \ + PRCMRTCMatchSet +#endif +#ifdef ROM_PRCMRTCMatchGet +#define MAP_PRCMRTCMatchGet \ + ROM_PRCMRTCMatchGet +#else +#define MAP_PRCMRTCMatchGet \ + PRCMRTCMatchGet +#endif +#ifdef ROM_PRCMLPDSRestoreInfoSet +#define MAP_PRCMLPDSRestoreInfoSet \ + ROM_PRCMLPDSRestoreInfoSet +#else +#define MAP_PRCMLPDSRestoreInfoSet \ + PRCMLPDSRestoreInfoSet +#endif +#ifdef ROM_PRCMSlowClkCtrFastGet +#define MAP_PRCMSlowClkCtrFastGet \ + ROM_PRCMSlowClkCtrFastGet +#else +#define MAP_PRCMSlowClkCtrFastGet \ + PRCMSlowClkCtrFastGet +#endif +#ifdef ROM_PRCMCC3200MCUInit +#define MAP_PRCMCC3200MCUInit \ + ROM_PRCMCC3200MCUInit +#else +#define MAP_PRCMCC3200MCUInit \ + PRCMCC3200MCUInit +#endif +#ifdef ROM_PRCMHIBRegRead +#define MAP_PRCMHIBRegRead \ + ROM_PRCMHIBRegRead +#else +#define MAP_PRCMHIBRegRead \ + PRCMHIBRegRead +#endif +#ifdef ROM_PRCMHIBRegWrite +#define MAP_PRCMHIBRegWrite \ + ROM_PRCMHIBRegWrite +#else +#define MAP_PRCMHIBRegWrite \ + PRCMHIBRegWrite +#endif +#ifdef ROM_PRCMCameraFreqSet +#define MAP_PRCMCameraFreqSet \ + ROM_PRCMCameraFreqSet +#else +#define MAP_PRCMCameraFreqSet \ + PRCMCameraFreqSet +#endif +#ifdef ROM_PRCMIORetentionEnable +#define MAP_PRCMIORetentionEnable \ + ROM_PRCMIORetentionEnable +#else +#define MAP_PRCMIORetentionEnable \ + PRCMIORetentionEnable +#endif +#ifdef ROM_PRCMIORetentionDisable +#define MAP_PRCMIORetentionDisable \ + ROM_PRCMIORetentionDisable +#else +#define MAP_PRCMIORetentionDisable \ + PRCMIORetentionDisable +#endif +#ifdef ROM_PRCMDeviceTypeGet +#define MAP_PRCMDeviceTypeGet \ + ROM_PRCMDeviceTypeGet +#else +#define MAP_PRCMDeviceTypeGet \ + PRCMDeviceTypeGet +#endif +#ifdef ROM_PRCMLPDSEnterKeepDebugIf +#define MAP_PRCMLPDSEnterKeepDebugIf \ + ROM_PRCMLPDSEnterKeepDebugIf +#else +#define MAP_PRCMLPDSEnterKeepDebugIf \ + PRCMLPDSEnterKeepDebugIf +#endif +#ifdef ROM_PRCMHibernateCycleTrigger +#define MAP_PRCMHibernateCycleTrigger \ + ROM_PRCMHibernateCycleTrigger +#else +#define MAP_PRCMHibernateCycleTrigger \ + PRCMHibernateCycleTrigger +#endif + +//***************************************************************************** +// +// Macros for the HWSPINLOCK API. +// +//***************************************************************************** +#ifdef ROM_HwSpinLockAcquire +#define MAP_HwSpinLockAcquire \ + ROM_HwSpinLockAcquire +#else +#define MAP_HwSpinLockAcquire \ + HwSpinLockAcquire +#endif +#ifdef ROM_HwSpinLockTryAcquire +#define MAP_HwSpinLockTryAcquire \ + ROM_HwSpinLockTryAcquire +#else +#define MAP_HwSpinLockTryAcquire \ + HwSpinLockTryAcquire +#endif +#ifdef ROM_HwSpinLockRelease +#define MAP_HwSpinLockRelease \ + ROM_HwSpinLockRelease +#else +#define MAP_HwSpinLockRelease \ + HwSpinLockRelease +#endif +#ifdef ROM_HwSpinLockTest +#define MAP_HwSpinLockTest \ + ROM_HwSpinLockTest +#else +#define MAP_HwSpinLockTest \ + HwSpinLockTest +#endif + +//***************************************************************************** +// +// Macros for the ADC API. +// +//***************************************************************************** +#ifdef ROM_ADCEnable +#define MAP_ADCEnable \ + ROM_ADCEnable +#else +#define MAP_ADCEnable \ + ADCEnable +#endif +#ifdef ROM_ADCDisable +#define MAP_ADCDisable \ + ROM_ADCDisable +#else +#define MAP_ADCDisable \ + ADCDisable +#endif +#ifdef ROM_ADCChannelEnable +#define MAP_ADCChannelEnable \ + ROM_ADCChannelEnable +#else +#define MAP_ADCChannelEnable \ + ADCChannelEnable +#endif +#ifdef ROM_ADCChannelDisable +#define MAP_ADCChannelDisable \ + ROM_ADCChannelDisable +#else +#define MAP_ADCChannelDisable \ + ADCChannelDisable +#endif +#ifdef ROM_ADCIntRegister +#define MAP_ADCIntRegister \ + ROM_ADCIntRegister +#else +#define MAP_ADCIntRegister \ + ADCIntRegister +#endif +#ifdef ROM_ADCIntUnregister +#define MAP_ADCIntUnregister \ + ROM_ADCIntUnregister +#else +#define MAP_ADCIntUnregister \ + ADCIntUnregister +#endif +#ifdef ROM_ADCIntEnable +#define MAP_ADCIntEnable \ + ROM_ADCIntEnable +#else +#define MAP_ADCIntEnable \ + ADCIntEnable +#endif +#ifdef ROM_ADCIntDisable +#define MAP_ADCIntDisable \ + ROM_ADCIntDisable +#else +#define MAP_ADCIntDisable \ + ADCIntDisable +#endif +#ifdef ROM_ADCIntStatus +#define MAP_ADCIntStatus \ + ROM_ADCIntStatus +#else +#define MAP_ADCIntStatus \ + ADCIntStatus +#endif +#ifdef ROM_ADCIntClear +#define MAP_ADCIntClear \ + ROM_ADCIntClear +#else +#define MAP_ADCIntClear \ + ADCIntClear +#endif +#ifdef ROM_ADCDMAEnable +#define MAP_ADCDMAEnable \ + ROM_ADCDMAEnable +#else +#define MAP_ADCDMAEnable \ + ADCDMAEnable +#endif +#ifdef ROM_ADCDMADisable +#define MAP_ADCDMADisable \ + ROM_ADCDMADisable +#else +#define MAP_ADCDMADisable \ + ADCDMADisable +#endif +#ifdef ROM_ADCTimerConfig +#define MAP_ADCTimerConfig \ + ROM_ADCTimerConfig +#else +#define MAP_ADCTimerConfig \ + ADCTimerConfig +#endif +#ifdef ROM_ADCTimerEnable +#define MAP_ADCTimerEnable \ + ROM_ADCTimerEnable +#else +#define MAP_ADCTimerEnable \ + ADCTimerEnable +#endif +#ifdef ROM_ADCTimerDisable +#define MAP_ADCTimerDisable \ + ROM_ADCTimerDisable +#else +#define MAP_ADCTimerDisable \ + ADCTimerDisable +#endif +#ifdef ROM_ADCTimerReset +#define MAP_ADCTimerReset \ + ROM_ADCTimerReset +#else +#define MAP_ADCTimerReset \ + ADCTimerReset +#endif +#ifdef ROM_ADCTimerValueGet +#define MAP_ADCTimerValueGet \ + ROM_ADCTimerValueGet +#else +#define MAP_ADCTimerValueGet \ + ADCTimerValueGet +#endif +#ifdef ROM_ADCFIFOLvlGet +#define MAP_ADCFIFOLvlGet \ + ROM_ADCFIFOLvlGet +#else +#define MAP_ADCFIFOLvlGet \ + ADCFIFOLvlGet +#endif +#ifdef ROM_ADCFIFORead +#define MAP_ADCFIFORead \ + ROM_ADCFIFORead +#else +#define MAP_ADCFIFORead \ + ADCFIFORead +#endif + +//***************************************************************************** +// +// Macros for the CPU API. +// +//***************************************************************************** +#ifdef ROM_CPUcpsid +#define MAP_CPUcpsid \ + ROM_CPUcpsid +#else +#define MAP_CPUcpsid \ + CPUcpsid +#endif +#ifdef ROM_CPUcpsie +#define MAP_CPUcpsie \ + ROM_CPUcpsie +#else +#define MAP_CPUcpsie \ + CPUcpsie +#endif +#ifdef ROM_CPUprimask +#define MAP_CPUprimask \ + ROM_CPUprimask +#else +#define MAP_CPUprimask \ + CPUprimask +#endif +#ifdef ROM_CPUwfi +#define MAP_CPUwfi \ + ROM_CPUwfi +#else +#define MAP_CPUwfi \ + CPUwfi +#endif +#ifdef ROM_CPUbasepriGet +#define MAP_CPUbasepriGet \ + ROM_CPUbasepriGet +#else +#define MAP_CPUbasepriGet \ + CPUbasepriGet +#endif +#ifdef ROM_CPUbasepriSet +#define MAP_CPUbasepriSet \ + ROM_CPUbasepriSet +#else +#define MAP_CPUbasepriSet \ + CPUbasepriSet +#endif + +#endif // __ROM_MAP_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_patch.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_patch.h new file mode 100755 index 00000000000..985c6821152 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_patch.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// rom_patch.h - Macros to facilitate patching driverlib API's in the ROM. +// +// + +//***************************************************************************** +// +// List of API's in the ROM that need to be patched. +// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut +//***************************************************************************** + +#ifndef __ROM_PATCH_H__ +#define __ROM_PATCH_H__ + +#if defined(TARGET_IS_CC3200) || defined(USE_CC3200_ROM_DRV_API) +#undef ROM_ADCIntClear +#undef ROM_IntEnable +#undef ROM_IntDisable +#undef ROM_IntPendSet +#undef ROM_SDHostCardErrorMaskSet +#undef ROM_SDHostCardErrorMaskGet +#undef ROM_TimerConfigure +#undef ROM_TimerDMAEventSet +#undef ROM_TimerDMAEventGet +#undef ROM_SDHostDataNonBlockingWrite +#undef ROM_SDHostDataWrite +#undef ROM_SDHostDataRead +#undef ROM_SDHostDataNonBlockingRead +#undef ROM_PRCMSysResetCauseGet +#undef ROM_PRCMPeripheralClkEnable +#undef ROM_PRCMLPDSWakeUpGPIOSelect +#undef ROM_PRCMHibernateWakeupSourceEnable +#undef ROM_PRCMHibernateWakeupSourceDisable +#undef ROM_PRCMHibernateWakeupCauseGet +#undef ROM_PRCMHibernateIntervalSet +#undef ROM_PRCMHibernateWakeUpGPIOSelect +#undef ROM_PRCMHibernateEnter +#undef ROM_PRCMSlowClkCtrGet +#undef ROM_PRCMSlowClkCtrMatchSet +#undef ROM_PRCMSlowClkCtrMatchGet +#undef ROM_PRCMOCRRegisterWrite +#undef ROM_PRCMOCRRegisterRead +#undef ROM_PRCMIntEnable +#undef ROM_PRCMIntDisable +#undef ROM_PRCMRTCInUseSet +#undef ROM_PRCMRTCInUseGet +#undef ROM_PRCMRTCSet +#undef ROM_PRCMRTCGet +#undef ROM_PRCMRTCMatchSet +#undef ROM_PRCMRTCMatchGet +#undef ROM_PRCMPeripheralClkDisable +#undef ROM_PRCMPeripheralReset +#undef ROM_PRCMPeripheralStatusGet +#undef ROM_SPIConfigSetExpClk +#undef ROM_AESDataProcess +#undef ROM_DESDataProcess +#undef ROM_I2SEnable +#undef ROM_I2SConfigSetExpClk +#undef ROM_PinConfigSet +#undef ROM_PRCMLPDSEnter +#undef ROM_PRCMCC3200MCUInit +#undef ROM_SDHostIntStatus +#undef ROM_SDHostBlockCountSet +#undef ROM_UARTModemControlSet +#undef ROM_UARTModemControlClear +#undef ROM_CameraXClkSet +#undef ROM_PRCMMCUReset +#undef ROM_PRCMPeripheralClkEnable +#undef ROM_SPIDmaDisable +#endif + +#if defined(USE_CC3220_ROM_DRV_API) +#undef ROM_PRCMDeviceTypeGet +#undef ROM_SDHostDataNonBlockingRead +#undef ROM_PRCMIORetentionEnable +#undef ROM_PRCMIORetentionDisable +#undef ROM_PRCMCC3200MCUInit +#undef ROM_SHAMD5ConfigSet +#undef ROM_SHAMD5HMACKeySet +#endif + +#endif // __ROM_PATCH_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.c new file mode 100755 index 00000000000..722f46285b7 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.c @@ -0,0 +1,745 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// sdhost.c +// +// Driver for the SD Host (SDHost) Interface +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup Secure_Digital_Host_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_mmchs.h" +#include "inc/hw_ints.h" +#include "inc/hw_apps_config.h" +#include "interrupt.h" +#include "sdhost.h" + + +//***************************************************************************** +// +//! Configures SDHost module. +//! +//! \param ulBase is the base address of SDHost module. +//! +//! This function configures the SDHost module, enabling internal sub-modules. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostInit(unsigned long ulBase) +{ + // + // Assert module reset + // + HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2; + + // + // Wait for soft reset to complete + // + while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) ) + { + + } + + // + // Assert internal reset + // + HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24); + + // + // Wait for Reset to complete + // + while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) ) + { + + } + + // + // Set capability register, 1.8 and 3.0 V + // + HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24); + + // + // Select bus voltage, 3.0 V + // + HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9; + + // + // Power up the bus + // + HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8; + + // + // Wait for power on + // + while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) ) + { + + } + + HWREG(ulBase + MMCHS_O_CON) |= 1 << 21; + + // + // Un-mask all events + // + HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF; +} + + +//***************************************************************************** +// +//! Resets SDHost command line +//! +//! \param ulBase is the base address of SDHost module. +//! +//! This function assers a soft reset for the command line +//! +//! \return None. +// +//***************************************************************************** +void +SDHostCmdReset(unsigned long ulBase) +{ + HWREG(ulBase + MMCHS_O_SYSCTL) |= 1 << 25; + while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (1 << 25)) ) + { + + } +} + +//***************************************************************************** +// +//! Sends command over SDHost interface +//! +//! \param ulBase is the base address of SDHost module. +//! \param ulCmd is the command to send. +//! \param ulArg is the argument for the command. +//! +//! This function send command to the attached card over the SDHost interface. +//! +//! The \e ulCmd parameter can be one of \b SDHOST_CMD_0 to \b SDHOST_CMD_63. +//! It can be logically ORed with one or more of the following: +//! - \b SDHOST_MULTI_BLK for multi-block transfer +//! - \b SDHOST_WR_CMD if command is followed by write data +//! - \b SDHOST_RD_CMD if command is followed by read data +//! - \b SDHOST_DMA_EN if SDHost need to generate DMA request. +//! - \b SDHOST_RESP_LEN_136 if 136 bit response is expected +//! - \b SDHOST_RESP_LEN_48 if 48 bit response is expected +//! - \b SDHOST_RESP_LEN_48B if 48 bit response with busy bit is expected +//! +//! The parameter \e ulArg is the argument for the command +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +long +SDHostCmdSend(unsigned long ulBase, unsigned long ulCmd, unsigned ulArg) +{ + // + // Set Data Timeout + // + HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x000E0000; + + // + // Check for cmd inhabit + // + if( (HWREG(ulBase + MMCHS_O_PSTATE) & 0x1)) + { + return -1; + } + + // + // Set the argument + // + HWREG(ulBase + MMCHS_O_ARG) = ulArg; + + // + // Send the command + // + HWREG(ulBase + MMCHS_O_CMD) = ulCmd; + + return 0; +} + +//***************************************************************************** +// +//! Writes a data word into the SDHost write buffer. +//! +//! \param ulBase is the base address of SDHost module. +//! \param ulData is data word to be transfered. +//! +//! This function writes a single data word into the SDHost write buffer. The +//! function returns \b true if there was a space available in the buffer else +//! returns \b false. +//! +//! \return Return \b true on success, \b false otherwise. +// +//***************************************************************************** +tBoolean +SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData) +{ + + // + // See if there is a space in the write buffer + // + if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) ) + { + // + // Write the data into the buffer + // + HWREG(ulBase + MMCHS_O_DATA) = ulData; + + // + // Success. + // + return(true); + } + else + { + // + // No free sapce, failure. + // + return(false); + } +} + +//***************************************************************************** +// +//! Waits to write a data word into the SDHost write buffer. +//! +//! \param ulBase is the base address of SDHost module. +//! \param ulData is data word to be transfered. +//! +//! This function writes \e ulData into the SDHost write buffer. If there is no +//! space in the write buffer this function waits until there is a space +//! available before returning. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostDataWrite(unsigned long ulBase, unsigned long ulData) +{ + // + // Wait until space is available + // + while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) ) + { + + } + + // + // Write the data + // + HWREG(ulBase + MMCHS_O_DATA) = ulData; +} + + +//***************************************************************************** +// +//! Waits for a data word from the SDHost read buffer +//! +//! \param ulBase is the base address of SDHost module. +//! \param pulData is pointer to read data variable. +//! +//! This function reads a single data word from the SDHost read buffer. If there +//! is no data available in the buffer the function will wait until a data +//! word is received before returning. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostDataRead(unsigned long ulBase, unsigned long *pulData) +{ + // + // Wait until data is available + // + while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) ) + { + + } + + // + // Read the data + // + *pulData = HWREG(ulBase + MMCHS_O_DATA); +} + +//***************************************************************************** +// +//! Reads single data word from the SDHost read buffer +//! +//! \param ulBase is the base address of SDHost module. +//! \param pulData is pointer to read data variable. +//! +//! This function reads a data word from the SDHost read buffer. The +//! function returns \b true if there was data available in to buffer else +//! returns \b false. +//! +//! \return Return \b true on success, \b false otherwise. +// +//***************************************************************************** +tBoolean +SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData) +{ + + // + // See if there is any data in the read buffer. + // + if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) ) + { + // + // Read the data word. + // + *pulData = HWREG(ulBase + MMCHS_O_DATA); + + // + // Success + // + return(true); + } + else + { + // + // No data available, failure. + // + return(false); + } +} + + +//***************************************************************************** +// +//! Registers the interrupt handler for SDHost interrupt +//! +//! \param ulBase is the base address of SDHost module +//! \param pfnHandler is a pointer to the function to be called when the +//! SDHost interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! SDHost interrupts must be enabled via SDHostIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler. + // + IntRegister(INT_MMCHS, pfnHandler); + + // + // Enable the SDHost interrupt. + // + IntEnable(INT_MMCHS); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for SDHost interrupt +//! +//! \param ulBase is the base address of SDHost module +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a SDHost interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostIntUnregister(unsigned long ulBase) +{ + // + // Disable the SDHost interrupt. + // + IntDisable(INT_MMCHS); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_MMCHS); +} + +//***************************************************************************** +// +//! Enable individual interrupt source for the specified SDHost +//! +//! \param ulBase is the base address of SDHost module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SDHost interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! - \b SDHOST_INT_CC Command Complete interrupt +//! - \b SDHOST_INT_TC Transfer Complete interrupt +//! - \b SDHOST_INT_BWR Buffer Write Ready interrupt +//! - \b SDHOST_INT_BRR Buffer Read Ready interrupt +//! - \b SDHOST_INT_ERRI Error interrupt +//! - \b SDHOST_INT_CTO Command Timeout error interrupt +//! - \b SDHOST_INT_CEB Command End Bit error interrupt +//! - \b SDHOST_INT_DTO Data Timeout error interrupt +//! - \b SDHOST_INT_DCRC Data CRC error interrupt +//! - \b SDHOST_INT_DEB Data End Bit error +//! - \b SDHOST_INT_CERR Cart Status Error interrupt +//! - \b SDHOST_INT_BADA Bad Data error interrupt +//! - \b SDHOST_INT_DMARD Read DMA done interrupt +//! - \b SDHOST_INT_DMAWR Write DMA done interrupt +//! +//! Note that SDHOST_INT_ERRI can only be used with \sa SDHostIntStatus() +//! and is internally logical OR of all error status bits. Setting this bit +//! alone as \e ulIntFlags doesn't generates any interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags) +{ + // + // Enable DMA done interrupts + // + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = + (ulIntFlags >> 30); + + // + // Enable the individual interrupt sources + // + HWREG(ulBase + MMCHS_O_ISE) |= (ulIntFlags & 0x3FFFFFFF); +} + +//***************************************************************************** +// +//! Enable individual interrupt source for the specified SDHost +//! +//! \param ulBase is the base address of SDHost module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function disables the indicated SDHost interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to SDHostIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags) +{ + // + // Disable DMA done interrupts + // + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = + (ulIntFlags >> 30); + // + // Disable the individual interrupt sources + // + HWREG(ulBase + MMCHS_O_ISE) &= ~(ulIntFlags & 0x3FFFFFFF); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of SDHost module. +//! +//! This function returns the interrupt status for the specified SDHost. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in SDHostIntEnable(). +// +//***************************************************************************** +unsigned long +SDHostIntStatus(unsigned long ulBase) +{ + unsigned long ulIntStatus; + + // + // Get DMA done interrupt status + // + ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW); + ulIntStatus = (ulIntStatus << 30); + + // + // Return the status of individual interrupt sources + // + ulIntStatus |= (HWREG(ulBase + MMCHS_O_STAT) & 0x3FFFFFFF); + + return(ulIntStatus); +} + +//***************************************************************************** +// +//! Clears the individual interrupt sources. +//! +//! \param ulBase is the base address of SDHost module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SDHost interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to SDHostIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags) +{ + // + // Clear DMA done interrupts + // + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = + (ulIntFlags >> 30); + // + // Clear the individual interrupt sources + // + HWREG(ulBase + MMCHS_O_STAT) = (ulIntFlags & 0x3FFFFFFF); +} + +//***************************************************************************** +// +//! Sets the card status error mask. +//! +//! \param ulBase is the base address of SDHost module +//! \param ulErrMask is the bit mask of card status errors to be enabled +//! +//! This function sets the card status error mask for response type R1, R1b, +//! R5, R5b and R6 response. The parameter \e ulErrMask is the bit mask of card +//! status errors to be enabled, if the corresponding bits in the 'card status' +//! field of a respose are set then the host controller indicates a card error +//! interrupt status. Only bits referenced as type E (error) in status field in +//! the response can set a card status error. +//! +//! \return None +// +//***************************************************************************** +void +SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask) +{ + // + // Set the card status error mask + // + HWREG(ulBase + MMCHS_O_CSRE) = ulErrMask; +} + + +//***************************************************************************** +// +//! Gets the card status error mask. +//! +//! \param ulBase is the base address of SDHost module +//! +//! This function gets the card status error mask for response type R1, R1b, +//! R5, R5b and R6 response. +//! +//! \return Returns the current card status error. +// +//***************************************************************************** +unsigned long +SDHostCardErrorMaskGet(unsigned long ulBase) +{ + // + // Return the card status error mask + // + return(HWREG(ulBase + MMCHS_O_CSRE)); +} + +//***************************************************************************** +// +//! Sets the SD Card clock. +//! +//! \param ulBase is the base address of SDHost module +//! \param ulSDHostClk is the rate of clock supplied to SDHost module +//! \param ulCardClk is the required SD interface clock +//! +//! This function configures the SDHost interface to supply the specified clock +//! to the connected card. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, + unsigned long ulCardClk) +{ + unsigned long ulDiv; + + // + // Disable card clock + // + HWREG(ulBase + MMCHS_O_SYSCTL) &= ~0x4; + + // + // Enable internal clock + // + HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x1; + + ulDiv = ((ulSDHostClk/ulCardClk) & 0x3FF); + + // + // Set clock divider, + // + HWREG(ulBase + MMCHS_O_SYSCTL) = ((HWREG(ulBase + MMCHS_O_SYSCTL) & + ~0x0000FFC0)| (ulDiv) << 6); + + // + // Wait for clock to stablize + // + while( !(HWREG(ulBase + MMCHS_O_SYSCTL) & 0x2) ) + { + + } + + // + // Enable card clock + // + HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x4; +} + +//***************************************************************************** +// +//! Get the response for the last command. +//! +//! \param ulBase is the base address of SDHost module +//! \param ulRespnse is 128-bit response. +//! +//! This function gets the response from the SD card for the last command +//! send. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]) +{ + + // + // Read the responses. + // + ulRespnse[0] = HWREG(ulBase + MMCHS_O_RSP10); + ulRespnse[1] = HWREG(ulBase + MMCHS_O_RSP32); + ulRespnse[2] = HWREG(ulBase + MMCHS_O_RSP54); + ulRespnse[3] = HWREG(ulBase + MMCHS_O_RSP76); + +} + +//***************************************************************************** +// +//! Set the block size for data transfer +//! +//! \param ulBase is the base address of SDHost module +//! \param ulBlkSize is the transfer block size in bytes +//! +//! This function sets the block size the data transfer. +//! +//! The parameter \e ulBlkSize is size of each data block in bytes. +//! This should be in range 0 - 2^10. +//! +//! \return None. +// +//***************************************************************************** +void +SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize) +{ + // + // Set the block size + // + HWREG(ulBase + MMCHS_O_BLK) = ((HWREG(ulBase + MMCHS_O_BLK) & 0x00000FFF)| + (ulBlkSize & 0xFFF)); +} + +//***************************************************************************** +// +//! Set the block size and count for data transfer +//! +//! \param ulBase is the base address of SDHost module +//! \param ulBlkCount is the number of blocks +//! +//! This function sets block count for the data transfer. This needs to be set +//! for each block transfer. \sa SDHostBlockSizeSet() +//! +//! \return None. +// +//***************************************************************************** +void +SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount) +{ + unsigned long ulRegVal; + + // + // Read the current value + // + ulRegVal = HWREG(ulBase + MMCHS_O_BLK); + + // + // Set the number of blocks + // + HWREG(ulBase + MMCHS_O_BLK) = ((ulRegVal & 0x0000FFFF)| + (ulBlkCount << 16)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.h new file mode 100755 index 00000000000..456f95865fe --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// sdhost.h +// +// Defines and Macros for the SDHost. +// +//***************************************************************************** + +#ifndef __SDHOST_H__ +#define __SDHOST_H__ + + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +//{ +#endif + + +//***************************************************************************** +// Values that can be passed to SDHostRespGet(). +//***************************************************************************** +#define SDHOST_RESP_10 0x00000003 +#define SDHOST_RESP_32 0x00000002 +#define SDHOST_RESP_54 0x00000001 +#define SDHOST_RESP_76 0x00000000 + + +//***************************************************************************** +// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(), +// SDHostIntClear() ,and returned from SDHostIntStatus(). +//***************************************************************************** +#define SDHOST_INT_CC 0x00000001 +#define SDHOST_INT_TC 0x00000002 +#define SDHOST_INT_BWR 0x00000010 +#define SDHOST_INT_BRR 0x00000020 +#define SDHOST_INT_ERRI 0x00008000 +#define SDHOST_INT_CTO 0x00010000 +#define SDHOST_INT_CEB 0x00040000 +#define SDHOST_INT_DTO 0x00100000 +#define SDHOST_INT_DCRC 0x00200000 +#define SDHOST_INT_DEB 0x00400000 +#define SDHOST_INT_CERR 0x10000000 +#define SDHOST_INT_BADA 0x20000000 +#define SDHOST_INT_DMARD 0x40000000 +#define SDHOST_INT_DMAWR 0x80000000 + +//***************************************************************************** +// Values that can be passed to SDHostCmdSend(). +//***************************************************************************** +#define SDHOST_CMD_0 0x00000000 +#define SDHOST_CMD_1 0x01000000 +#define SDHOST_CMD_2 0x02000000 +#define SDHOST_CMD_3 0x03000000 +#define SDHOST_CMD_4 0x04000000 +#define SDHOST_CMD_5 0x05000000 +#define SDHOST_CMD_6 0x06000000 +#define SDHOST_CMD_7 0x07000000 +#define SDHOST_CMD_8 0x08000000 +#define SDHOST_CMD_9 0x09000000 +#define SDHOST_CMD_10 0x0A000000 +#define SDHOST_CMD_11 0x0B000000 +#define SDHOST_CMD_12 0x0C000000 +#define SDHOST_CMD_13 0x0D000000 +#define SDHOST_CMD_14 0x0E000000 +#define SDHOST_CMD_15 0x0F000000 +#define SDHOST_CMD_16 0x10000000 +#define SDHOST_CMD_17 0x11000000 +#define SDHOST_CMD_18 0x12000000 +#define SDHOST_CMD_19 0x13000000 +#define SDHOST_CMD_20 0x14000000 +#define SDHOST_CMD_21 0x15000000 +#define SDHOST_CMD_22 0x16000000 +#define SDHOST_CMD_23 0x17000000 +#define SDHOST_CMD_24 0x18000000 +#define SDHOST_CMD_25 0x19000000 +#define SDHOST_CMD_26 0x1A000000 +#define SDHOST_CMD_27 0x1B000000 +#define SDHOST_CMD_28 0x1C000000 +#define SDHOST_CMD_29 0x1D000000 +#define SDHOST_CMD_30 0x1E000000 +#define SDHOST_CMD_31 0x1F000000 +#define SDHOST_CMD_32 0x20000000 +#define SDHOST_CMD_33 0x21000000 +#define SDHOST_CMD_34 0x22000000 +#define SDHOST_CMD_35 0x23000000 +#define SDHOST_CMD_36 0x24000000 +#define SDHOST_CMD_37 0x25000000 +#define SDHOST_CMD_38 0x26000000 +#define SDHOST_CMD_39 0x27000000 +#define SDHOST_CMD_40 0x28000000 +#define SDHOST_CMD_41 0x29000000 +#define SDHOST_CMD_42 0x2A000000 +#define SDHOST_CMD_43 0x2B000000 +#define SDHOST_CMD_44 0x2C000000 +#define SDHOST_CMD_45 0x2D000000 +#define SDHOST_CMD_46 0x2E000000 +#define SDHOST_CMD_47 0x2F000000 +#define SDHOST_CMD_48 0x30000000 +#define SDHOST_CMD_49 0x31000000 +#define SDHOST_CMD_50 0x32000000 +#define SDHOST_CMD_51 0x33000000 +#define SDHOST_CMD_52 0x34000000 +#define SDHOST_CMD_53 0x35000000 +#define SDHOST_CMD_54 0x36000000 +#define SDHOST_CMD_55 0x37000000 +#define SDHOST_CMD_56 0x38000000 +#define SDHOST_CMD_57 0x39000000 +#define SDHOST_CMD_58 0x3A000000 +#define SDHOST_CMD_59 0x3B000000 +#define SDHOST_CMD_60 0x3C000000 +#define SDHOST_CMD_61 0x3D000000 +#define SDHOST_CMD_62 0x3E000000 +#define SDHOST_CMD_63 0x3F000000 + +//***************************************************************************** +// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend(). +//***************************************************************************** +#define SDHOST_MULTI_BLK 0x00000022 +#define SDHOST_DMA_EN 0x00000001 +#define SDHOST_WR_CMD 0x00200000 +#define SDHOST_RD_CMD 0x00200010 +#define SDHOST_RESP_LEN_136 0x00010000 +#define SDHOST_RESP_LEN_48 0x00020000 +#define SDHOST_RESP_LEN_48B 0x00030000 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void SDHostCmdReset(unsigned long ulBase); +extern void SDHostInit(unsigned long ulBase); +extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd, + unsigned ulArg); +extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void SDHostIntUnregister(unsigned long ulBase); +extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags); +extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags); +extern unsigned long SDHostIntStatus(unsigned long ulBase); +extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags); +extern void SDHostCardErrorMaskSet(unsigned long ulBase, + unsigned long ulErrMask); +extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase); +extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, + unsigned long ulCardClk); +extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]); +extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize); +extern void SDHostBlockCountSet(unsigned long ulBase, + unsigned short ulBlkCount); +extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase, + unsigned long ulData); +extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase, + unsigned long *pulData); +extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData); +extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +//} +#endif + +#endif // __SDHOST_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.c new file mode 100755 index 00000000000..bf0b20621ed --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.c @@ -0,0 +1,1249 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// shamd5.c +// +// Driver for the SHA/MD5 module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup SHA_Secure_Hash_Algorithm_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dthe.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_nvic.h" +#include "inc/hw_shamd5.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/shamd5.h" + +//***************************************************************************** +// +//! Enables the uDMA requests in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! +//! This function configures the DMA options of the SHA/MD5 module. +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5DMAEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Write the new configuration into the register. + // + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= + SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN; +} + +//***************************************************************************** +// +//! Disables the uDMA requests in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! +//! This function configures the DMA options of the SHA/MD5 module. +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5DMADisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Write the new configuration into the register. + // + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= + ~(SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN); +} + +//***************************************************************************** +// +//! Get the interrupt status of the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the current value of the IRQSTATUS register. The +//! value will be a logical OR of the following: +//! +//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. +//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after +//! a context switch. +//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. +//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. +//! +//! \return Interrupt status +// +//***************************************************************************** +uint32_t +SHAMD5IntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Temp; + uint32_t ui32IrqEnable; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Return the value of the IRQSTATUS register. + // + if(bMasked) + { + ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_MIS); + ui32IrqEnable = HWREG(ui32Base + SHAMD5_O_IRQENABLE); + return((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & + ui32IrqEnable) | (ui32Temp & 0x00000007) << 16); + } + else + { + ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_RIS); + return(HWREG(ui32Base + SHAMD5_O_IRQSTATUS) | + (ui32Temp & 0x00000007) << 16); + + } +} + +//***************************************************************************** +// +//! Enable interrupt sources in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32IntFlags contains desired interrupts to enable. +//! +//! This function enables interrupt sources in the SHA/MD5 module. +//! ui32IntFlags must be a logical OR of one or more of the following +//! values: +//! +//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. +//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after +//! a context switch. +//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. +//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || + (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || + (ui32IntFlags == SHAMD5_INT_INPUT_READY) || + (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); + + // + // Enable the interrupt sources. + // + HWREG(DTHE_BASE + DTHE_O_SHA_IM) &= ~((ui32IntFlags & 0x00070000) >> 16); + HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; + + // + // Enable all interrupts. + // + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_PIT_EN; +} + +//***************************************************************************** +// +//! Disable interrupt sources in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32IntFlags contains desired interrupts to disable. +//! +//! \e ui32IntFlags must be a logical OR of one or more of the following +//! values: +//! +//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. +//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after +//! a context switch. +//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. +//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || + (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || + (ui32IntFlags == SHAMD5_INT_INPUT_READY) || + (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); + + // + // Clear the corresponding flags disabling the interrupt sources. + // + HWREG(DTHE_BASE + DTHE_O_SHA_IM) |= ((ui32IntFlags & 0x00070000) >> 16); + HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); + + // + // If there are no interrupts enabled, then disable all interrupts. + // + if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0) + { + HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_PIT_EN; + } +} + +//***************************************************************************** +// +//! Clears interrupt sources in the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32IntFlags contains desired interrupts to disable. +//! +//! \e ui32IntFlags must be a logical OR of one or more of the following +//! values: +//! +//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. +//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after +//! a context switch. +//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. +//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || + (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || + (ui32IntFlags == SHAMD5_INT_INPUT_READY) || + (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); + + // + // Clear the corresponding flags disabling the interrupt sources. + // + HWREG(DTHE_BASE + DTHE_O_SHA_IC) = ((ui32IntFlags & 0x00070000) >> 16); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled SHA/MD5 interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables SHA/MD5 interrupts on the interrupt controller; +//! specific SHA/MD5 interrupt sources must be enabled using +//! SHAMD5IntEnable(). The interrupt handler being registered must clear +//! the source of the interrupt using SHAMD5IntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_SHA, pfnHandler); + + // + // Enable the interrupt + // + IntEnable(INT_SHA); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5IntUnregister(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_SHA); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SHA); +} + +//***************************************************************************** +// +//! Write the hash length to the SHA/MD5 module. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32Length is the hash length in bytes. +//! +//! This function writes the length of the hash data of the current operation +//! to the SHA/MD5 module. The value must be a multiple of 64 if the close +//! hash is not set in the mode register. +//! +//! \note When this register is written, hash processing is triggered. +//! +//! \return None. +// +//***************************************************************************** +void +SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + + // + // Set the LENGTH register and start processing. + // + HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length; +} + +//***************************************************************************** +// +//! Writes the mode in the SHA/MD5 module. +//! Sets the request value to SHAMD5_O_MODE register. +//! Each parameter defines one of the bit fields in the SHAMD5_O_MODE register. +//! +//! \param ui32Base is the base address of the SHA/MD5 module. +//! \param ui32CryptoMode sets the hash algorithm to be used. +//! \param algConstFlag sets the requested value to +//! SHAMD5_MODE_ALGO_CONSTANT bit field. +//! \param closeHashFlag sets the requested value to +//! SHAMD5_MODE_CLOSE_HASH bit field. +//! \param HMACKeyFlag sets the requested value to +//! SHAMD5_MODE_HMAC_KEY_PROC bit field. +//! \param HMACOuterHashFlag sets the requested value to +//! SHAMD5_MODE_HMAC_OUTER_HASH bit field. +//! +//! \return None +// +//***************************************************************************** +void +SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32CryptoMode, uint8_t algConstFlag, uint8_t closeHashFlag, + uint8_t HMACKeyFlag, uint8_t HMACOuterHashFlag) +{ + uint32_t RegData = 0; + + // + // Check the arguments. + // + ASSERT(ui32Base == SHAMD5_BASE); + ASSERT((ui32CryptoMode == SHAMD5_ALGO_MD5) || + (ui32CryptoMode == SHAMD5_ALGO_SHA1) || + (ui32CryptoMode == SHAMD5_ALGO_SHA224) || + (ui32CryptoMode == SHAMD5_ALGO_SHA256)); + + RegData = (uint32_t)( ui32CryptoMode | ((algConstFlag&0x1)< 0) && (ulPeriod <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; +} + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps, which +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +unsigned long +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter, which is +//! a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +unsigned long +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/systick.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/systick.h new file mode 100755 index 00000000000..b09e26e4099 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/systick.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// systick.h +// +// Prototypes for the SysTick driver. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.c new file mode 100755 index 00000000000..ecd02a30b76 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.c @@ -0,0 +1,1361 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// aes.c +// +// Driver for the AES module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup AES_Advanced_Encryption_Standard_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_aes.h" +#include "inc/hw_dthe.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_nvic.h" +#include "inc/hw_types.h" +#include "ti_aes.h" +#include "debug.h" +#include "interrupt.h" + +#define AES_BLOCK_SIZE_IN_BYTES 16 + +//***************************************************************************** +// +//! Configures the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32Config is the configuration of the AES module. +//! +//! This function configures the AES module based on the specified parameters. +//! It does not change any DMA- or interrupt-related parameters. +//! +//! The ui32Config parameter is a bit-wise OR of a number of configuration +//! flags. The valid flags are grouped based on their function. +//! +//! The direction of the operation is specified with only of following flags: +//! +//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode +//! - \b AES_CFG_DIR_DECRYPT - Decryption mode +//! +//! The key size is specified with only one of the following flags: +//! +//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits +//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits +//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits +//! +//! The mode of operation is specified with only one of the following flags. +//! +//! - \b AES_CFG_MODE_ECB - Electronic codebook mode +//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode +//! - \b AES_CFG_MODE_CFB - Cipher feedback mode +//! - \b AES_CFG_MODE_CTR - Counter mode +//! - \b AES_CFG_MODE_ICM - Integer counter mode +//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode +//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with +//! ciphertext stealing with previous/intermediate tweak value and j loaded +//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with +//! ciphertext stealing with key2, i and j loaded +//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with +//! ciphertext stealing with key2 and i loaded, j = 0 +//! - \b AES_CFG_MODE_F8 - F8 mode +//! - \b AES_CFG_MODE_F9 - F9 mode +//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication +//! code mode +//! - \b AES_CFG_MODE_GCM - Galois/counter mode +//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H +//! loaded and Y0-encrypted forced to zero +//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H +//! loaded and Y0-encrypted calculated internally +//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH +//! (both H and Y0-encrypted calculated internally) +//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode +//! +//! The following defines are used to specify the counter width. It is only +//! required to be defined when using CTR, CCM, or GCM modes, only one of the +//! following defines must be used to specify the counter width length: +//! +//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits +//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits +//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits +//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits +//! +//! Only one of the following defines must be used to specify the length field +//! for CCM operations (L): +//! +//! - \b AES_CFG_CCM_L_2 - 2 bytes +//! - \b AES_CFG_CCM_L_4 - 4 bytes +//! - \b AES_CFG_CCM_L_8 - 8 bytes +//! +//! Only one of the following defines must be used to specify the length of the +//! authentication field for CCM operations (M) through the \e ui32Config +//! argument in the AESConfigSet() function: +//! +//! - \b AES_CFG_CCM_M_4 - 4 bytes +//! - \b AES_CFG_CCM_M_6 - 6 bytes +//! - \b AES_CFG_CCM_M_8 - 8 bytes +//! - \b AES_CFG_CCM_M_10 - 10 bytes +//! - \b AES_CFG_CCM_M_12 - 12 bytes +//! - \b AES_CFG_CCM_M_14 - 14 bytes +//! - \b AES_CFG_CCM_M_16 - 16 bytes +//! +//! \return None. +// +//***************************************************************************** +void +AESConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) || + (ui32Config & AES_CFG_DIR_DECRYPT)); + ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) || + (ui32Config & AES_CFG_KEY_SIZE_192BIT) || + (ui32Config & AES_CFG_KEY_SIZE_256BIT)); + ASSERT((ui32Config & AES_CFG_MODE_ECB) || + (ui32Config & AES_CFG_MODE_CBC) || + (ui32Config & AES_CFG_MODE_CTR) || + (ui32Config & AES_CFG_MODE_ICM) || + (ui32Config & AES_CFG_MODE_CFB) || + (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) || + (ui32Config & AES_CFG_MODE_XTS_K2IJL) || + (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) || + (ui32Config & AES_CFG_MODE_F8) || + (ui32Config & AES_CFG_MODE_F9) || + (ui32Config & AES_CFG_MODE_CTR) || + (ui32Config & AES_CFG_MODE_CBCMAC) || + (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || + (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || + (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || + (ui32Config & AES_CFG_MODE_CCM)); + ASSERT(((ui32Config & AES_CFG_MODE_CTR) || + (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || + (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || + (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || + (ui32Config & AES_CFG_MODE_CCM)) && + ((ui32Config & AES_CFG_CTR_WIDTH_32) || + (ui32Config & AES_CFG_CTR_WIDTH_64) || + (ui32Config & AES_CFG_CTR_WIDTH_96) || + (ui32Config & AES_CFG_CTR_WIDTH_128))); + ASSERT((ui32Config & AES_CFG_MODE_CCM) && + ((ui32Config & AES_CFG_CCM_L_2) || + (ui32Config & AES_CFG_CCM_L_4) || + (ui32Config & AES_CFG_CCM_L_8)) && + ((ui32Config & AES_CFG_CCM_M_4) || + (ui32Config & AES_CFG_CCM_M_6) || + (ui32Config & AES_CFG_CCM_M_8) || + (ui32Config & AES_CFG_CCM_M_10) || + (ui32Config & AES_CFG_CCM_M_12) || + (ui32Config & AES_CFG_CCM_M_14) || + (ui32Config & AES_CFG_CCM_M_16))); + + // + // Backup the save context field before updating the register. + // + if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT) + { + ui32Config |= AES_CTRL_SAVE_CONTEXT; + } + + // + // Write the CTRL register with the new value + // + HWREG(ui32Base + AES_O_CTRL) = ui32Config; +} + +//***************************************************************************** +// +//! Writes the key 1 configuration registers, which are used for encryption or +//! decryption. +//! +//! \param ui32Base is the base address for the AES module. +//! \param pui8Key is an array of bytes, containing the key to be +//! configured. The least significant word in the 0th index. +//! \param ui32Keysize is the size of the key, which must be one of the +//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or +//! \b AES_CFG_KEY_SIZE_256. +//! +//! This function writes key 1 configuration registers based on the key +//! size. This function is used in all modes. +//! +//! \return None. +// +//***************************************************************************** +void +AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || + (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || + (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); + + // + // With all key sizes, the first 4 words are written. + // + HWREG(ui32Base + AES_O_KEY1_0) = * ((uint32_t *)(pui8Key + 0)); + HWREG(ui32Base + AES_O_KEY1_1) = * ((uint32_t *)(pui8Key + 4)); + HWREG(ui32Base + AES_O_KEY1_2) = * ((uint32_t *)(pui8Key + 8)); + HWREG(ui32Base + AES_O_KEY1_3) = * ((uint32_t *)(pui8Key + 12)); + + // + // The key is 192 or 256 bits. Write the next 2 words. + // + if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) + { + HWREG(ui32Base + AES_O_KEY1_4) = * ((uint32_t *)(pui8Key + 16)); + HWREG(ui32Base + AES_O_KEY1_5) = * ((uint32_t *)(pui8Key + 20)); + } + + // + // The key is 256 bits. Write the last 2 words. + // + if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) + { + HWREG(ui32Base + AES_O_KEY1_6) = * ((uint32_t *)(pui8Key + 24)); + HWREG(ui32Base + AES_O_KEY1_7) = * ((uint32_t *)(pui8Key + 28)); + } +} + +//***************************************************************************** +// +//! Writes the key 2 configuration registers, which are used for encryption or +//! decryption. +//! +//! \param ui32Base is the base address for the AES module. +//! \param pui8Key is an array of bytes, containing the key to be +//! configured. The least significant word in the 0th index. +//! \param ui32Keysize is the size of the key, which must be one of the +//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or +//! \b AES_CFG_KEY_SIZE_256. +//! +//! This function writes the key 2 configuration registers based on the key +//! size. This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes. +//! +//! \return None. +// +//***************************************************************************** +void +AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || + (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || + (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); + + // + // With all key sizes, the first 4 words are written. + // + HWREG(ui32Base + AES_O_KEY2_0) = * ((uint32_t *)(pui8Key + 0)); + HWREG(ui32Base + AES_O_KEY2_1) = * ((uint32_t *)(pui8Key + 4)); + HWREG(ui32Base + AES_O_KEY2_2) = * ((uint32_t *)(pui8Key + 8)); + HWREG(ui32Base + AES_O_KEY2_3) = * ((uint32_t *)(pui8Key + 12)); + + // + // The key is 192 or 256 bits. Write the next 2 words. + // + if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) + { + HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 16)); + HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 20)); + } + + // + // The key is 256 bits. Write the last 2 words. + // + if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) + { + HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 24)); + HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 28)); + } +} + +//***************************************************************************** +// +//! Writes key 3 configuration registers, which are used for encryption or +//! decryption. +//! +//! \param ui32Base is the base address for the AES module. +//! \param pui8Key is a pointer to an array bytes, containing +//! the key to be configured. The least significant word is in the 0th index. +//! +//! This function writes the key 2 configuration registers with key 3 data +//! used in CBC-MAC and F8 modes. This key is always 128 bits. +//! +//! \return None. +// +//***************************************************************************** +void +AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the key into the upper 4 key registers + // + HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 0)); + HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 4)); + HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 8)); + HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 12)); +} + +//***************************************************************************** +// +//! Writes the Initial Vector (IV) register, needed in some of the AES Modes. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8IVdata is an array of 16 bytes (128 bits), containing the IV +//! value to be configured. The least significant word is in the 0th index. +//! +//! This functions writes the initial vector registers in the AES module. +//! +//! \return None. +// +//***************************************************************************** +void +AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the initial vector registers. + // + HWREG(ui32Base + AES_O_IV_IN_0) = *((uint32_t *)(pui8IVdata+0)); + HWREG(ui32Base + AES_O_IV_IN_1) = *((uint32_t *)(pui8IVdata+4)); + HWREG(ui32Base + AES_O_IV_IN_2) = *((uint32_t *)(pui8IVdata+8)); + HWREG(ui32Base + AES_O_IV_IN_3) = *((uint32_t *)(pui8IVdata+12)); +} + + +//***************************************************************************** +// +//! Reads the Initial Vector (IV) register, needed in some of the AES Modes. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8IVdata is pointer to an array of 16 bytes. +//! +//! This functions reads the initial vector registers in the AES module. +//! +//! \return None. +// +//***************************************************************************** +void +AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the initial vector registers. + // + *((uint32_t *)(pui8IVdata+ 0)) = HWREG(ui32Base + AES_O_IV_IN_0); + *((uint32_t *)(pui8IVdata+ 4)) = HWREG(ui32Base + AES_O_IV_IN_1); + *((uint32_t *)(pui8IVdata+ 8)) = HWREG(ui32Base + AES_O_IV_IN_2); + *((uint32_t *)(pui8IVdata+12)) = HWREG(ui32Base + AES_O_IV_IN_3); +} + +//***************************************************************************** +// +//! Saves the tag registers to a user-defined location. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8TagData is pointer to the location that stores the tag data. +//! +//! This function stores the tag data for use authenticated encryption and +//! decryption operations. +//! +//! \return None. +// +//***************************************************************************** +void +AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Read the tag data. + // + *((uint32_t *)(pui8TagData+0)) = HWREG((ui32Base + AES_O_TAG_OUT_0)); + *((uint32_t *)(pui8TagData+4)) = HWREG((ui32Base + AES_O_TAG_OUT_1)); + *((uint32_t *)(pui8TagData+8)) = HWREG((ui32Base + AES_O_TAG_OUT_2)); + *((uint32_t *)(pui8TagData+12)) = HWREG((ui32Base + AES_O_TAG_OUT_3)); +} + +//***************************************************************************** +// +//! Used to set the write crypto data length in the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui64Length is the crypto data length in bytes. +//! +//! This function stores the cryptographic data length in blocks for all modes. +//! Data lengths up to (2^61 - 1) bytes are allowed. For GCM, any value up +//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used. For +//! basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the +//! length field, indicating that the length is infinite. +//! +//! When this function is called, the engine is triggered to start using +//! this context. +//! +//! \note This length does not include the authentication-only data used in +//! some modes. Use the AESAuthLengthSet() function to specify the +//! authentication data length. +//! +//! \return None +// +//***************************************************************************** +void +AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the length register by shifting the 64-bit ui64Length. + // + HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length); + HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32); +} + +//***************************************************************************** +// +//! Sets the optional additional authentication data (AAD) length. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32Length is the length in bytes. +//! +//! This function is only used to write the authentication data length in the +//! combined modes (GCM or CCM) and XTS mode. Supported AAD lengths for CCM +//! are from 0 to (2^16 - 28) bytes. For GCM, any value up to (2^32 - 1) can +//! be used. For XTS mode, this register is used to load j. Loading of j is +//! only required if j != 0. j represents the sequential number of the 128-bit +//! blocks inside the data unit. Consequently, j must be multiplied by 16 +//! when passed to this function, thereby placing the block number in +//! bits [31:4] of the register. +//! +//! When this function is called, the engine is triggered to start using +//! this context for GCM and CCM. +//! +//! \return None +// +//***************************************************************************** +void +AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the length into the register. + // + HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length; +} + +//***************************************************************************** +// +//! Reads plaintext/ciphertext from data registers without blocking. +//! This api writes data in blocks +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8Dest is a pointer to an array of words of data. +//! \param ui8Length the length can be from 1 to 16 +//! +//! This function reads a block of either plaintext or ciphertext out of the +//! AES module. If the output data is not ready, the function returns +//! false. If the read completed successfully, the function returns true. +//! A block is 16 bytes or 4 words. +//! +//! \return true or false. +// +//***************************************************************************** +bool +AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) +{ + volatile uint32_t pui32Dest[4]; + uint8_t ui8BytCnt; + uint8_t *pui8DestTemp; + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + if((ui8Length == 0)||(ui8Length>16)) + { + return(false); + } + + // + // Check if the output is ready before reading the data. If it not ready, + // return false. + // + if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) + { + return(false); + } + + // + // Read a block of data from the data registers + // + pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); + pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); + pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); + pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); + + // + //Copy the data to a block memory + // + pui8DestTemp = (uint8_t *)pui32Dest; + for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) + { + *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); + } + // + // Read successful, return true. + // + return(true); +} + + +//***************************************************************************** +// +//! Reads plaintext/ciphertext from data registers with blocking. +//! This api writes data in blocks +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8Dest is a pointer to an array of words. +//! \param ui8Length is the length of data in bytes to be read. +//! ui8Length can be from 1 to 16 +//! +//! This function reads a block of either plaintext or ciphertext out of the +//! AES module. If the output is not ready, the function waits until it +//! is ready. A block is 16 bytes or 4 words. +//! +//! \return None. +// +//***************************************************************************** + +void +AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) +{ + volatile uint32_t pui32Dest[4]; + uint8_t ui8BytCnt; + uint8_t *pui8DestTemp; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + if((ui8Length == 0)||(ui8Length>16)) + { + return; + } + + + // + // Wait for the output to be ready before reading the data. + // + while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) + { + } + + // + // Read a block of data from the data registers + // + pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); + pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); + pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); + pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); + // + //Copy the data to a block memory + // + pui8DestTemp = (uint8_t *)pui32Dest; + for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) + { + *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); + } + + return; +} + +//***************************************************************************** +// +//! Writes plaintext/ciphertext to data registers without blocking. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8Src is a pointer to an array of words of data. +//! \param ui8Length the length can be from 1 to 16 +//! +//! This function writes a block of either plaintext or ciphertext into the +//! AES module. If the input is not ready, the function returns false +//! If the write completed successfully, the function returns true. +//! +//! \return True or false. +// +//***************************************************************************** +bool +AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) +{ + volatile uint32_t pui32Src[4]={0,0,0,0}; + uint8_t ui8BytCnt; + uint8_t *pui8SrcTemp; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + if((ui8Length == 0)||(ui8Length>16)) + { + return(false); + } + + // + // Check if the input is ready. If not, then return false. + // + if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL)))) + { + return(false); + } + + + // + //Copy the data to a block memory + // + pui8SrcTemp = (uint8_t *)pui32Src; + for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) + { + *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); + } + // + // Write a block of data into the data registers. + // + HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; + HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; + HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; + HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; + + // + // Write successful, return true. + // + return(true); +} + + +//***************************************************************************** +// +//! Writes plaintext/ciphertext to data registers with blocking. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8Src is a pointer to an array of bytes. +//! \param ui8Length the length can be from 1 to 16 +//! +//! This function writes a block of either plaintext or ciphertext into the +//! AES module. If the input is not ready, the function waits until it is +//! ready before performing the write. +//! +//! \return None. +// +//***************************************************************************** + +void +AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) +{ + volatile uint32_t pui32Src[4]={0,0,0,0}; + uint8_t ui8BytCnt; + uint8_t *pui8SrcTemp; + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + if((ui8Length == 0)||(ui8Length>16)) + { + return; + } + // + // Wait for input ready. + // + while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) + { + } + + // + //Copy the data to a block memory + // + pui8SrcTemp = (uint8_t *)pui32Src; + for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) + { + *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); + } + + // + // Write a block of data into the data registers. + // + HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; + HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; + HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; + HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; +} + + +//***************************************************************************** +// +//! Used to process(transform) blocks of data, either encrypt or decrypt it. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8Src is a pointer to the memory location where the input data +//! is stored. +//! \param pui8Dest is a pointer to the memory location output is written. +//! \param ui32Length is the length of the cryptographic data in bytes. +//! +//! This function iterates the encryption or decryption mechanism number over +//! the data length. Before calling this function, ensure that the AES +//! module is properly configured the key, data size, mode, etc. Only ECB, +//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used. The data +//! is processed in 4-word (16-byte) blocks. +//! +//! \note This function only supports values of \e ui32Length less than 2^32, +//! because the memory size is restricted to between 0 to 2^32 bytes. +//! +//! \return Returns true if data was processed successfully. Returns false +//! if data processing failed. +// +//***************************************************************************** +bool +AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, + uint32_t ui32Length) +{ + uint32_t ui32Count, ui32BlkCount, ui32ByteCount; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the length register first, which triggers the engine to start + // using this context. + // + AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); + + // + // Now loop until the blocks are written. + // + ui32BlkCount = ui32Length/16; + for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui8Src + (ui32Count*16) ,16); + + // + // Read the data registers. + // + AESDataRead(ui32Base, pui8Dest + (ui32Count*16) ,16); + + } + + // + //Now handle the residue bytes + // + ui32ByteCount = ui32Length%16; + if(ui32ByteCount) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui8Src + (16*ui32BlkCount) ,ui32ByteCount); + + // + // Read the data registers. + // + AESDataRead(ui32Base, pui8Dest + (16*ui32BlkCount) ,ui32ByteCount); + } + + + + // + // Return true to indicate successful completion of the function. + // + return(true); +} +//***************************************************************************** +// +//! Used to generate message authentication code (MAC) using CBC-MAC and F9 mode. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8Src is a pointer to the memory location where the input data +//! is stored. +//! \param ui32Length is the length of the cryptographic data in bytes. +//! \param pui8Tag is a pointer to a 4-word array where the hash tag is +//! written. +//! +//! This function processes data to produce a hash tag that can be used tor +//! authentication. Before calling this function, ensure that the AES +//! module is properly configured the key, data size, mode, etc. Only +//! CBC-MAC and F9 modes should be used. +//! +//! \return Returns true if data was processed successfully. Returns false +//! if data processing failed. +// +//***************************************************************************** +bool +AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, uint32_t ui32Length, + uint8_t *pui8Tag) +{ + uint32_t ui32Count, ui32BlkCount, ui32ByteCount; + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Write the length register first, which triggers the engine to start + // using this context. + // + AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); + + // + // Write the data registers. + // + + // + // Now loop until the blocks are written. + // + ui32BlkCount = ui32Length/16; + for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui8Src + ui32Count*16 ,16); + } + + // + //Now handle the residue bytes + // + ui32ByteCount = ui32Length%16; + if(ui32ByteCount) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui8Src + (ui32Count*ui32BlkCount) ,ui32ByteCount); + } + + // + // Wait for the context data regsiters to be ready. + // + while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0) + { + } + + // + // Read the hash tag value. + // + AESTagRead(AES_BASE, pui8Tag); + + // + // Return true to indicate successful completion of the function. + // + return(true); +} + +//***************************************************************************** +// +//! Used for Authenticated encryption (AE) of the data. Processes and authenticates blocks of data, +//! either encrypt the data or decrypt the data. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pui8Src is a pointer to the memory location where the input data +//! is stored. The data must be padded to the 16-byte boundary. +//! \param pui8Dest is a pointer to the memory location output is written. +//! The space for written data must be rounded up to the 16-byte boundary. +//! \param ui32Length is the length of the cryptographic data in bytes. +//! \param pui8AuthSrc is a pointer to the memory location where the +//! additional authentication data is stored. The data must be padded to the +//! 16-byte boundary. +//! \param ui32AuthLength is the length of the additional authentication +//! data in bytes. +//! \param pui8Tag is a pointer to a 4-word array where the hash tag is +//! written. +//! +//! This function encrypts or decrypts blocks of data in addition to +//! authentication data. A hash tag is also produced. Before calling this +//! function, ensure that the AES module is properly configured the key, +//! data size, mode, etc. Only CCM and GCM modes should be used. +//! +//! \return Returns true if data was processed successfully. Returns false +//! if data processing failed. +// +//***************************************************************************** +bool +AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, + uint32_t ui32Length, uint8_t *pui8AuthSrc, + uint32_t ui32AuthLength, uint8_t *pui8Tag) +{ + uint32_t ui32Count; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Set the data length. + // + AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); + + // + // Set the additional authentication data length. + // + AESAuthDataLengthSet(AES_BASE, ui32AuthLength); + + // + // Now loop until the authentication data blocks are written. + // + for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui8AuthSrc + (ui32Count),16); + } + + // + // Now loop until the data blocks are written. + // + for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) + { + // + // Write the data registers. + // + AESDataWrite(ui32Base, pui8Src + (ui32Count),16); + + // + // + // Read the data registers. + // + AESDataRead(ui32Base, pui8Dest + (ui32Count),16); + } + + // + // Wait for the context data regsiters to be ready. + // + while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0) + { + } + + // + // Read the hash tag value. + // + AESTagRead(AES_BASE, pui8Tag); + + // + // Return true to indicate successful completion of the function. + // + return(true); +} + +//***************************************************************************** +// +//! Returns the current AES module interrupt status. +//! +//! \param ui32Base is the base address of the AES module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! \return Returns a bit mask of the interrupt sources, which is a logical OR +//! of any of the following: +//! +//! - \b AES_INT_CONTEXT_IN - Context interrupt +//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt. +//! - \b AES_INT_DATA_IN - Data input interrupt +//! - \b AES_INT_DATA_OUT - Data output interrupt +//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done +//! interrupt +//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt +// +//***************************************************************************** +uint32_t +AESIntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Temp; + uint32_t ui32IrqEnable; + + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Read the IRQ status register and return the value. + // + if(bMasked) + { + ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_MIS); + ui32IrqEnable = HWREG(ui32Base + AES_O_IRQENABLE); + return((HWREG(ui32Base + AES_O_IRQSTATUS) & + ui32IrqEnable) | ((ui32Temp & 0x0000000F) << 16)); + } + else + { + ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_RIS); + return(HWREG(ui32Base + AES_O_IRQSTATUS) | + ((ui32Temp & 0x0000000F) << 16)); + } +} + +//***************************************************************************** +// +//! Enables AES module interrupts. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to enable. +//! +//! This function enables the interrupts in the AES module. The \e ui32IntFlags +//! parameter is the logical OR of any of the following: +//! +//! - \b AES_INT_CONTEXT_IN - Context interrupt +//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt +//! - \b AES_INT_DATA_IN - Data input interrupt +//! - \b AES_INT_DATA_OUT - Data output interrupt +//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done +//! interrupt +//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \note Interrupts that have been previously been enabled are not disabled +//! when this function is called. +//! +//! \return None. +// +//***************************************************************************** +void +AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || + (ui32IntFlags == AES_INT_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DATA_IN) || + (ui32IntFlags == AES_INT_DATA_OUT) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DMA_DATA_IN) || + (ui32IntFlags == AES_INT_DMA_DATA_OUT)); + + // + // Set the flags. + // + HWREG(DTHE_BASE + DTHE_O_AES_IM) &= ~((ui32IntFlags & 0x000F0000) >> 16); + HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; +} + +//***************************************************************************** +// +//! Disables AES module interrupts. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. +//! +//! This function disables the interrupt sources in the AES module. The +//! \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b AES_INT_CONTEXT_IN - Context interrupt +//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt +//! - \b AES_INT_DATA_IN - Data input interrupt +//! - \b AES_INT_DATA_OUT - Data output interrupt +//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done +//! interrupt +//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \note The DMA done interrupts are the only interrupts that can be cleared. +//! The remaining interrupts can be disabled instead using AESIntDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || + (ui32IntFlags == AES_INT_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DATA_IN) || + (ui32IntFlags == AES_INT_DATA_OUT) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DMA_DATA_IN) || + (ui32IntFlags == AES_INT_DMA_DATA_OUT)); + + // + // Clear the flags. + // + HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x000F0000) >> 16); + HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); +} + +//***************************************************************************** +// +//! Clears AES module interrupts. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. +//! +//! This function clears the interrupt sources in the AES module. The +//! \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done +//! interrupt +//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \note Only the DMA done interrupts can be cleared. The remaining +//! interrupts should be disabled with AESIntDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || + (ui32IntFlags == AES_INT_DMA_DATA_IN) || + (ui32IntFlags == AES_INT_DMA_DATA_OUT)); + + HWREG(DTHE_BASE + DTHE_O_AES_IC) = ((ui32IntFlags >> 16) & 0x0000000F); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled AES interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables AES interrupts on the interrupt controller; specific AES +//! interrupt sources must be enabled using AESIntEnable(). The interrupt +//! handler being registered must clear the source of the interrupt using +//! AESIntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() is used to enable AES interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_AES, pfnHandler); + + // + // Enable the interrupt + // + IntEnable(INT_AES); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +AESIntUnregister(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_AES); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_AES); +} + +//***************************************************************************** +// +//! Enables uDMA requests for the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32Flags is a bit mask of the uDMA requests to be enabled. +//! +//! This function enables the uDMA request sources in the AES module. +//! The \e ui32Flags parameter is the logical OR of any of the following: +//! +//! - \b AES_DMA_DATA_IN +//! - \b AES_DMA_DATA_OUT +//! - \b AES_DMA_CONTEXT_IN +//! - \b AES_DMA_CONTEXT_OUT +//! +//! \return None. +// +//***************************************************************************** +void +AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Flags == AES_DMA_DATA_IN) || + (ui32Flags == AES_DMA_DATA_OUT) || + (ui32Flags == AES_DMA_CONTEXT_IN) || + (ui32Flags == AES_DMA_CONTEXT_OUT)); + + // + // Set the flags in the current register value. + // + HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags; +} + +//***************************************************************************** +// +//! Disables uDMA requests for the AES module. +//! +//! \param ui32Base is the base address of the AES module. +//! \param ui32Flags is a bit mask of the uDMA requests to be disabled. +//! +//! This function disables the uDMA request sources in the AES module. +//! The \e ui32Flags parameter is the logical OR of any of the +//! following: +//! +//! - \b AES_DMA_DATA_IN +//! - \b AES_DMA_DATA_OUT +//! - \b AES_DMA_CONTEXT_IN +//! - \b AES_DMA_CONTEXT_OUT +//! +//! \return None. +// +//***************************************************************************** +void +AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == AES_BASE); + ASSERT((ui32Flags == AES_DMA_DATA_IN) || + (ui32Flags == AES_DMA_DATA_OUT) || + (ui32Flags == AES_DMA_CONTEXT_IN) || + (ui32Flags == AES_DMA_CONTEXT_OUT)); + + // + // Clear the flags in the current register value. + // + HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.h new file mode 100755 index 00000000000..de5d2c68b8f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_aes.h @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// aes.h +// +// Defines and Macros for the AES module. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_AES_H__ +#define __DRIVERLIB_AES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used to specify the operation direction in the +// ui32Config argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_DIR_ENCRYPT 0x00000004 +#define AES_CFG_DIR_DECRYPT 0x00000000 + +//***************************************************************************** +// +// The following defines are used to specify the key size in the ui32Config +// argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_KEY_SIZE_128BIT 0x00000008 +#define AES_CFG_KEY_SIZE_192BIT 0x00000010 +#define AES_CFG_KEY_SIZE_256BIT 0x00000018 + +//***************************************************************************** +// +// The following defines are used to specify the mode of operation in the +// ui32Config argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_MODE_M 0x2007fe60 +#define AES_CFG_MODE_ECB 0x00000000 +#define AES_CFG_MODE_CBC 0x00000020 +#define AES_CFG_MODE_CTR 0x00000040 +#define AES_CFG_MODE_ICM 0x00000200 +#define AES_CFG_MODE_CFB 0x00000400 +#define AES_CFG_MODE_XTS_TWEAKJL \ + 0x00000800 +#define AES_CFG_MODE_XTS_K2IJL \ + 0x00001000 +#define AES_CFG_MODE_XTS_K2ILJ0 \ + 0x00001800 +#define AES_CFG_MODE_F8 0x00002000 +#define AES_CFG_MODE_F9 0x20004000 +#define AES_CFG_MODE_CBCMAC 0x20008000 +#define AES_CFG_MODE_GCM_HLY0ZERO \ + 0x20010040 +#define AES_CFG_MODE_GCM_HLY0CALC \ + 0x20020040 +#define AES_CFG_MODE_GCM_HY0CALC \ + 0x20030040 +#define AES_CFG_MODE_CCM 0x20040040 + +//***************************************************************************** +// +// The following defines are used to specify the counter width in the +// ui32Config argument in the AESConfig function. It is only required to +// be defined when using CTR, CCM, or GCM modes. Only one length is permitted. +// +//***************************************************************************** +#define AES_CFG_CTR_WIDTH_32 0x00000000 +#define AES_CFG_CTR_WIDTH_64 0x00000080 +#define AES_CFG_CTR_WIDTH_96 0x00000100 +#define AES_CFG_CTR_WIDTH_128 0x00000180 + +//***************************************************************************** +// +// The following defines are used to define the width of the length field for +// CCM operation through the ui32Config argument in the AESConfig function. +// This value is also known as L. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_CCM_L_2 0x00080000 +#define AES_CFG_CCM_L_4 0x00180000 +#define AES_CFG_CCM_L_8 0x00380000 + +//***************************************************************************** +// +// The following defines are used to define the length of the authentication +// field for CCM operations through the ui32Config argument in the AESConfig +// function. This value is also known as M. Only one is permitted. +// +//***************************************************************************** +#define AES_CFG_CCM_M_4 0x00400000 +#define AES_CFG_CCM_M_6 0x00800000 +#define AES_CFG_CCM_M_8 0x00c00000 +#define AES_CFG_CCM_M_10 0x01000000 +#define AES_CFG_CCM_M_12 0x01400000 +#define AES_CFG_CCM_M_14 0x01800000 +#define AES_CFG_CCM_M_16 0x01c00000 + +//***************************************************************************** +// +// Interrupt flags for use with the AESIntEnable, AESIntDisable, and +// AESIntStatus functions. +// +//***************************************************************************** +#define AES_INT_CONTEXT_IN 0x00000001 +#define AES_INT_CONTEXT_OUT 0x00000008 +#define AES_INT_DATA_IN 0x00000002 +#define AES_INT_DATA_OUT 0x00000004 +#define AES_INT_DMA_CONTEXT_IN 0x00010000 +#define AES_INT_DMA_CONTEXT_OUT 0x00020000 +#define AES_INT_DMA_DATA_IN 0x00040000 +#define AES_INT_DMA_DATA_OUT 0x00080000 + +//***************************************************************************** +// +// Defines used when enabling and disabling DMA requests in the +// AESEnableDMA and AESDisableDMA functions. +// +//***************************************************************************** +#define AES_DMA_DATA_IN 0x00000040 +#define AES_DMA_DATA_OUT 0x00000020 +#define AES_DMA_CONTEXT_IN 0x00000080 +#define AES_DMA_CONTEXT_OUT 0x00000100 + +//***************************************************************************** +// +// Function prototypes. +// +//***************************************************************************** +extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, + uint32_t ui32Keysize); +extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, + uint32_t ui32Keysize); +extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key); +extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata); +extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata); +extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData); +extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length); +extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length); +extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, + uint8_t ui8Length); +extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, + uint8_t ui8Length); +extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t ui8Length); +extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t ui8Length); +extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t *pui8Dest, + uint32_t ui32Length); +extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, + uint32_t ui32Length, + uint8_t *pui8Tag); +extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t *pui8Dest, uint32_t ui32Length, + uint8_t *pui8AuthSrc, uint32_t ui32AuthLength, + uint8_t *pui8Tag); +extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked); +extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void AESIntUnregister(uint32_t ui32Base); +extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); +extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_AES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.c new file mode 100755 index 00000000000..d6f40ca13ce --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.c @@ -0,0 +1,888 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// des.c +// +// Driver for the DES data transformation. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup DES_Data_Encryption_Standard_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_des.h" +#include "inc/hw_dthe.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "debug.h" +#include "ti_des.h" +#include "interrupt.h" + + +//***************************************************************************** +// +//! Configures the DES module for operation. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32Config is the configuration of the DES module. +//! +//! This function configures the DES module for operation. +//! +//! The \e ui32Config parameter is a bit-wise OR of a number of configuration +//! flags. The valid flags are grouped below based on their function. +//! +//! The direction of the operation is specified with one of the following two +//! flags. Only one is permitted. +//! +//! - \b DES_CFG_DIR_ENCRYPT - Encryption +//! - \b DES_CFG_DIR_DECRYPT - Decryption +//! +//! The operational mode of the DES engine is specified with one of the +//! following flags. Only one is permitted. +//! +//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode +//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode +//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode +//! +//! The selection of single DES or triple DES is specified with one of the +//! following two flags. Only one is permitted. +//! +//! - \b DES_CFG_SINGLE - Single DES +//! - \b DES_CFG_TRIPLE - Triple DES +//! +//! \return None. +// +//***************************************************************************** +void +DESConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Backup the save context field. + // + ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT); + + // + // Write the control register. + // + HWREG(ui32Base + DES_O_CTRL) = ui32Config; +} + +//***************************************************************************** +// +//! Sets the key used for DES operations. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui8Key is a pointer to an array that holds the key +//! +//! This function sets the key used for DES operations. +//! +//! \e pui8Key should be 64 bits long (2 words) if single DES is being used or +//! 192 bits (6 words) if triple DES is being used. +//! +//! \return None. +// +//***************************************************************************** +void +DESKeySet(uint32_t ui32Base, uint8_t *pui8Key) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Write the first part of the key. + // + HWREG(ui32Base + DES_O_KEY1_L) = * ((uint32_t *)(pui8Key + 0)); + HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4)); + + // + // If we are performing triple DES, then write the key registers for + // the second and third rounds. + // + if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE) + { + HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8)); + HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12)); + HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16)); + HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20)); + } +} + +//***************************************************************************** +// +//! Sets the initialization vector in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui8IVdata is a pointer to an array of 64 bits (2 words) of data to +//! be written into the initialization vectors registers. +//! +//! This function sets the initialization vector in the DES module. It returns +//! true if the registers were successfully written. If the context registers +//! cannot be written at the time the function was called, then false is +//! returned. +//! +//! \return True or false. +// +//***************************************************************************** +bool +DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Check to see if context registers can be overwritten. If not, return + // false. + // + if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0) + { + return(false); + } + + // + // Write the initialization vector registers. + // + HWREG(ui32Base + DES_O_IV_L) = *((uint32_t *) (pui8IVdata + 0)); + HWREG(ui32Base + DES_O_IV_H) = *((uint32_t *) (pui8IVdata + 4)); + + // + // Return true to indicate the write was successful. + // + return(true); +} + +//***************************************************************************** +// +//! Sets the crytographic data length in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32Length is the length of the data in bytes. +//! +//! This function writes the cryptographic data length into the DES module. +//! When this register is written, the engine is triggersed to start using +//! this context. +//! +//! \note Data lengths up to (2^32 - 1) bytes are allowed. +//! +//! \return None. +// +//***************************************************************************** +void +DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Write the length register. + // + HWREG(ui32Base + DES_O_LENGTH) = ui32Length; +} + +//***************************************************************************** +// +//! Reads plaintext/ciphertext from data registers without blocking +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui8Dest is a pointer to an array of 2 words. +//! \param ui8Length the length can be from 1 to 8 +//! +//! This function returns true if the data was ready when the function was +//! called. If the data was not ready, false is returned. +//! +//! \return True or false. +// +//***************************************************************************** +bool +DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) +{ + volatile uint32_t pui32Dest[2]; + uint8_t ui8BytCnt; + uint8_t *pui8DestTemp; + + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + if((ui8Length == 0)||(ui8Length>8)) + { + return(false); + } + + // + // Check to see if the data is ready to be read. + // + if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) + { + return(false); + } + + // + // Read two words of data from the data registers. + // + pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); + pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); + + // + //Copy the data to a block memory + // + pui8DestTemp = (uint8_t *)pui32Dest; + for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) + { + *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); + } + + // + // Return true to indicate a successful write. + // + return(true); +} + +//***************************************************************************** +// +//! Reads plaintext/ciphertext from data registers with blocking. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui8Dest is a pointer to an array of bytes. +//! \param ui8Length the length can be from 1 to 8 +//! +//! This function waits until the DES module is finished and encrypted or +//! decrypted data is ready. The output data is then stored in the pui8Dest +//! array. +//! +//! \return None +// +//***************************************************************************** +void +DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) +{ + volatile uint32_t pui32Dest[2]; + uint8_t ui8BytCnt; + uint8_t *pui8DestTemp; + + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + if((ui8Length == 0)||(ui8Length>8)) + { + return; + } + // + // Wait for data output to be ready. + // + while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0) + { + } + + // + // Read two words of data from the data registers. + // + pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); + pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); + + // + //Copy the data to a block memory + // + pui8DestTemp = (uint8_t *)pui32Dest; + for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) + { + *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); + } +} + +//***************************************************************************** +// +//! Writes plaintext/ciphertext to data registers without blocking +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui8Src is a pointer to an array of 2 words. +//! \param ui8Length the length can be from 1 to 8 +//! +//! This function returns false if the DES module is not ready to accept +//! data. It returns true if the data was written successfully. +//! +//! \return true or false. +// +//***************************************************************************** +bool +DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) +{ + + volatile uint32_t pui32Src[2]={0,0}; + uint8_t ui8BytCnt; + uint8_t *pui8SrcTemp; + + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + if((ui8Length == 0)||(ui8Length>8)) + { + return(false); + } + + // + // Check if the DES module is ready to encrypt or decrypt data. If it + // is not, return false. + // + if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL)))) + { + return(false); + } + + // + // Copy the data to a block memory + // + pui8SrcTemp = (uint8_t *)pui32Src; + for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) + { + *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); + } + + // + // Write the data. + // + HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; + HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; + + // + // Return true to indicate a successful write. + // + return(true); +} + +//***************************************************************************** +// +//! Writes plaintext/ciphertext to data registers without blocking +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui8Src is a pointer to an array of bytes. +//! \param ui8Length the length can be from 1 to 8 +//! +//! This function waits until the DES module is ready before writing the +//! data contained in the pui8Src array. +//! +//! \return None. +// +//***************************************************************************** +void +DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) +{ + volatile uint32_t pui32Src[2]={0,0}; + uint8_t ui8BytCnt; + uint8_t *pui8SrcTemp; + + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + if((ui8Length == 0)||(ui8Length>8)) + { + return; + } + + // + // Wait for the input ready bit to go high. + // + while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0) + { + } + + // + //Copy the data to a block memory + // + pui8SrcTemp = (uint8_t *)pui32Src; + for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) + { + *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); + } + + // + // Write the data. + // + HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; + HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; +} + +//***************************************************************************** +// +//! Processes blocks of data through the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pui8Src is a pointer to an array of words that contains the +//! source data for processing. +//! \param pui8Dest is a pointer to an array of words consisting of the +//! processed data. +//! \param ui32Length is the length of the cryptographic data in bytes. +//! It must be a multiple of eight. +//! +//! This function takes the data contained in the pui8Src array and processes +//! it using the DES engine. The resulting data is stored in the +//! pui8Dest array. The function blocks until all of the data has been +//! processed. If processing is successful, the function returns true. +//! +//! \note This functions assumes that the DES module has been configured, +//! and initialization values and keys have been written. +//! +//! \return true or false. +// +//***************************************************************************** +bool +DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, + uint32_t ui32Length) +{ + uint32_t ui32Count, ui32BlkCount, ui32ByteCount; + + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32Length % 8) == 0); + + // + // Write the length register first. This triggers the engine to start + // using this context. + // + HWREG(ui32Base + DES_O_LENGTH) = ui32Length; + + + // + // Now loop until the blocks are written. + // + ui32BlkCount = ui32Length/8; + for(ui32Count = 0; ui32Count > 16); + HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; +} + +//***************************************************************************** +// +//! Disables interrupts in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. +//! +//! This function disables interrupt sources in the DES module. +//! \e ui32IntFlags should be a logical OR of one or more of the following +//! values: +//! +//! - \b DES_INT_CONTEXT_IN - Context interrupt +//! - \b DES_INT_DATA_IN - Data input interrupt +//! - \b DES_INT_DATA_OUT - Data output interrupt +//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt +//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt +//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt +//! +//! \return None. +// +//***************************************************************************** +void +DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || + (ui32IntFlags & DES_INT_DATA_IN) || + (ui32IntFlags & DES_INT_DATA_OUT) || + (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_OUT)); + + // + // Clear the interrupts from the flags. + // + HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x00070000) >> 16); + HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); +} + +//***************************************************************************** +// +//! Clears interrupts in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. +//! +//! This function disables interrupt sources in the DES module. +//! \e ui32IntFlags should be a logical OR of one or more of the following +//! values: +//! +//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt +//! - \b DES_INT_DMA_DATA_IN - Data input interrupt +//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt +//! +//! \note The DMA done interrupts are the only interrupts that can be cleared. +//! The remaining interrupts can be disabled instead using DESIntDisable(). +//! +//! \return None. +// +//***************************************************************************** +void +DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_IN) || + (ui32IntFlags & DES_INT_DMA_DATA_OUT)); + + HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled DES interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables DES interrupts on the interrupt controller; specific DES +//! interrupt sources must be enabled using DESIntEnable(). The interrupt +//! handler being registered must clear the source of the interrupt using +//! DESIntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() should be used to enable DES interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_DES, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(INT_DES); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +DESIntUnregister(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_DES); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_DES); +} + +//***************************************************************************** +// +//! Enables DMA request sources in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32Flags is a bit mask of the DMA requests to be enabled. +//! +//! This function enables DMA request sources in the DES module. The +//! \e ui32Flags parameter should be the logical OR of any of the following: +//! +//! - \b DES_DMA_CONTEXT_IN - Context In +//! - \b DES_DMA_DATA_OUT - Data Out +//! - \b DES_DMA_DATA_IN - Data In +//! +//! \return None. +// +//***************************************************************************** +void +DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || + (ui32Flags & DES_DMA_DATA_OUT) || + (ui32Flags & DES_DMA_DATA_IN)); + + // + // Set the data in and data out DMA request enable bits. + // + HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags; +} + +//***************************************************************************** +// +//! Disables DMA request sources in the DES module. +//! +//! \param ui32Base is the base address of the DES module. +//! \param ui32Flags is a bit mask of the DMA requests to be disabled. +//! +//! This function disables DMA request sources in the DES module. The +//! \e ui32Flags parameter should be the logical OR of any of the following: +//! +//! - \b DES_DMA_CONTEXT_IN - Context In +//! - \b DES_DMA_DATA_OUT - Data Out +//! - \b DES_DMA_DATA_IN - Data In +//! +//! \return None. +// +//***************************************************************************** +void +DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == DES_BASE); + ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || + (ui32Flags & DES_DMA_DATA_OUT) || + (ui32Flags & DES_DMA_DATA_IN)); + + // + // Disable the DMA sources. + // + HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.h new file mode 100755 index 00000000000..ecd6ab61a5d --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_des.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// des.h +// +// Defines and Macros for the DES module. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_DES_H__ +#define __DRIVERLIB_DES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are used to specify the direction with the +// ui32Config argument in the DESConfig() function. Only one is permitted. +// +//***************************************************************************** +#define DES_CFG_DIR_DECRYPT 0x00000000 +#define DES_CFG_DIR_ENCRYPT 0x00000004 + +//***************************************************************************** +// +// The following defines are used to specify the operational with the +// ui32Config argument in the DESConfig() function. Only one is permitted. +// +//***************************************************************************** +#define DES_CFG_MODE_ECB 0x00000000 +#define DES_CFG_MODE_CBC 0x00000010 +#define DES_CFG_MODE_CFB 0x00000020 + +//***************************************************************************** +// +// The following defines are used to select between single DES and triple DES +// with the ui32Config argument in the DESConfig() function. Only one is +// permitted. +// +//***************************************************************************** +#define DES_CFG_SINGLE 0x00000000 +#define DES_CFG_TRIPLE 0x00000008 + +//***************************************************************************** +// +// The following defines are used with the DESIntEnable(), DESIntDisable() and +// DESIntStatus() functions. +// +//***************************************************************************** +#define DES_INT_CONTEXT_IN 0x00000001 +#define DES_INT_DATA_IN 0x00000002 +#define DES_INT_DATA_OUT 0x00000004 +#define DES_INT_DMA_CONTEXT_IN 0x00010000 +#define DES_INT_DMA_DATA_IN 0x00020000 +#define DES_INT_DMA_DATA_OUT 0x00040000 + +//***************************************************************************** +// +// The following defines are used with the DESEnableDMA() and DESDisableDMA() +// functions. +// +//***************************************************************************** +#define DES_DMA_CONTEXT_IN 0x00000080 +#define DES_DMA_DATA_OUT 0x00000040 +#define DES_DMA_DATA_IN 0x00000020 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, + uint8_t ui8Length); +extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, + uint8_t ui8Length); +extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t *pui8Dest, uint32_t ui32Length); +extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t ui8Length); +extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, + uint8_t ui8Length); +extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); +extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); +extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked); +extern void DESIntUnregister(uint32_t ui32Base); +extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata); +extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key); +extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_DES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.c new file mode 100644 index 00000000000..b4f0f6316f4 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.c @@ -0,0 +1,2053 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// i2c.c +// +// Driver for Inter-IC (I2C) bus block. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup I2C_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_i2c.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "debug.h" +#include "ti_i2c.h" +#include "interrupt.h" + +//***************************************************************************** +// +// A mapping of I2C base address to interrupt number. +// +//***************************************************************************** +static const uint32_t g_ppui32I2CIntMap[][2] = +{ + { I2CA0_BASE, INT_I2CA0}, +}; + +static const int_fast8_t g_i8I2CIntMapRows = + sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]); + +//***************************************************************************** +// +//! \internal +//! Checks an I2C base address. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function determines if a I2C module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_I2CBaseValid(uint32_t ui32Base) +{ + return((ui32Base == I2CA0_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the I2C interrupt number. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! Given a I2C base address, this function returns the corresponding +//! interrupt number. +//! +//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid. +// +//***************************************************************************** +static uint32_t +_I2CIntNumberGet(uint32_t ui32Base) +{ + int_fast8_t i8Idx, i8Rows; + const uint32_t (*ppui32I2CIntMap)[2]; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + ppui32I2CIntMap = g_ppui32I2CIntMap; + i8Rows = g_i8I2CIntMapRows; + + // + // Loop through the table that maps I2C base addresses to interrupt + // numbers. + // + for(i8Idx = 0; i8Idx < i8Rows; i8Idx++) + { + // + // See if this base address matches. + // + if(ppui32I2CIntMap[i8Idx][0] == ui32Base) + { + // + // Return the corresponding interrupt number. + // + return(ppui32I2CIntMap[i8Idx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(0); +} + +//***************************************************************************** +// +//! Initializes the I2C Master block. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. +//! \param bFast set up for fast data transfers. +//! +//! This function initializes operation of the I2C Master block by configuring +//! the bus speed for the master and enabling the I2C Master block. +//! +//! If the parameter \e bFast is \b true, then the master block is set up to +//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at +//! 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually +//! write the I2CMTPR after calling this function. For High Speed (3.4 Mbps) +//! mode, a specific command is used to switch to the faster clocks after the +//! initial communication with the slave is done at either 100 Kbps or +//! 400 Kbps. +//! +//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast) +{ + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ui32Base); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / + (2 * 10 * ui32SCLFreq)) - 1; + HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; + + // + // Check to see if this I2C peripheral is High-Speed enabled. If yes, also + // choose the fastest speed that is less than or equal to 3.4 Mbps. + // + if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) + { + ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) / + (2 * 3 * 3400000)) - 1; + HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; + } +} + +//***************************************************************************** +// +//! Initializes the I2C Slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr 7-bit slave address +//! +//! This function initializes operation of the I2C Slave block by configuring +//! the slave address and enabling the I2C Slave block. +//! +//! The parameter \e ui8SlaveAddr is the value that is compared against the +//! slave address sent by an I2C master. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // + // Must enable the device before doing anything else. + // + I2CSlaveEnable(ui32Base); + + // + // Set up the slave address. + // + HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! Sets the I2C slave address. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8AddrNum determines which slave address is set. +//! \param ui8SlaveAddr is the 7-bit slave address +//! +//! This function writes the specified slave address. The \e ui32AddrNum field +//! dictates which slave address is configured. For example, a value of 0 +//! configures the primary address and a value of 1 configures the secondary. +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + ASSERT(!(ui8AddrNum > 1)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // + // Determine which slave address is being set. + // + switch(ui8AddrNum) + { + // + // Set up the primary slave address. + // + case 0: + { + HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; + break; + } + + // + // Set up and enable the secondary slave address. + // + case 1: + { + HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; + break; + } + } +} + +//***************************************************************************** +// +//! Enables the I2C Master block. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function enables operation of the I2C Master block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the master block. + // + HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; +} + +//***************************************************************************** +// +//! Enables the I2C Slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! This fucntion enables operation of the I2C Slave block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the clock to the slave block. + // + HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; + + // + // Enable the slave. + // + HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; +} + +//***************************************************************************** +// +//! Disables the I2C master block. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function disables operation of the I2C master block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the master block. + // + HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); +} + +//***************************************************************************** +// +//! Disables the I2C slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! This function disables operation of the I2C slave block. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the slave. + // + HWREG(ui32Base + I2C_O_SCSR) = 0; + + // + // Disable the clock to the slave block. + // + HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2C module. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2C interrupt occurs. +//! +//! This function sets the handler to be called when an I2C interrupt occurs. +//! This function enables the global interrupt in the interrupt controller; +//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and +//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via I2CMasterIntClear() and +//! I2CSlaveIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the I2C port. + // + ui32Int = _I2CIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the I2C interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2C module. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function clears the handler to be called when an I2C interrupt +//! occurs. This function also masks off the interrupt in the interrupt r +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +I2CIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the I2C port. + // + ui32Int = _I2CIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables the I2C Master interrupt. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function enables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the master interrupt. + // + HWREG(ui32Base + I2C_O_MIMR) = 1; +} + +//***************************************************************************** +// +//! Enables individual I2C Master interrupt sources. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Master interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt +//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt +//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt +//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt +//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt +//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt +//! - \b I2C_MASTER_INT_START - Start Condition interrupt +//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt +//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt +//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt +//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt +//! - \b I2C_MASTER_INT_DATA - Data interrupt +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the master interrupt. + // + HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Enables the I2C Slave interrupt. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! This function enables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the slave interrupt. + // + HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; +} + +//***************************************************************************** +// +//! Enables individual I2C Slave interrupt sources. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Slave interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt +//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt +//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt +//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt +//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt +//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt +//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt +//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt +//! - \b I2C_SLAVE_INT_DATA - Data interrupt +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the slave interrupt. + // + HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables the I2C Master interrupt. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function disables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the master interrupt. + // + HWREG(ui32Base + I2C_O_MIMR) = 0; +} + +//***************************************************************************** +// +//! Disables individual I2C Master interrupt sources. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! This function disables the indicated I2C Master interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the master interrupt. + // + HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! Disables the I2C Slave interrupt. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! This function disables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the slave interrupt. + // + HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; +} + +//***************************************************************************** +// +//! Disables individual I2C Slave interrupt sources. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be +//! disabled. +//! +//! This function disables the indicated I2C Slave interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable the slave interrupt. + // + HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +bool +I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); + } + else + { + return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in I2CMasterIntEnableEx(). +// +//***************************************************************************** +uint32_t +I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + I2C_O_MMIS)); + } + else + { + return(HWREG(ui32Base + I2C_O_MRIS)); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +bool +I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false); + } + else + { + return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This function returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in I2CSlaveIntEnableEx(). +// +//***************************************************************************** +uint32_t +I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ui32Base + I2C_O_SMIS)); + } + else + { + return(HWREG(ui32Base + I2C_O_SRIS)); + } +} + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! The I2C Master interrupt source is cleared, so that it no longer +//! asserts. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear the I2C master interrupt source. + // + HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; + + // + // Workaround for I2C master interrupt clear errata for some + // devices. For later devices, this write is ignored and therefore + // harmless (other than the slight performance hit). + // + HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC; +} + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C Master interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear the I2C master interrupt source. + // + HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! The I2C Slave interrupt source is cleared, so that it no longer asserts. +//! This function must be called in the interrupt handler to keep the interrupt +//! from being triggered again immediately upon exit. +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC; +} + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C Slave interrupt sources are cleared, so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupt from being triggered again immediately upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the +//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). +//! +//! \note Because there is a write buffer in the Cortex-M processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! Sets the address that the I2C Master places on the bus. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui8SlaveAddr 7-bit slave address +//! \param bReceive flag indicating the type of communication with the slave +//! +//! This function configures the address that the I2C Master places on the +//! bus when initiating a transaction. When the \e bReceive parameter is set +//! to \b true, the address indicates that the I2C Master is initiating a +//! read from the slave; otherwise the address indicates that the I2C +//! Master is initiating a write to the slave. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, + bool bReceive) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // + // Set the address of the slave with which the master will communicate. + // + HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; +} + +//***************************************************************************** +// +//! Reads the state of the SDA and SCL pins. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function returns the state of the I2C bus by providing the real time +//! values of the SDA and SCL pins. +//! +//! +//! \return Returns the state of the bus with SDA in bit position 1 and SCL in +//! bit position 0. +// +//***************************************************************************** +uint32_t +I2CMasterLineStateGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the line state. + // + return(HWREG(ui32Base + I2C_O_MBMON)); +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C Master is busy. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \return Returns \b true if the I2C Master is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +bool +I2CMasterBusy(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the busy status. + // + if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-master environment to determine if +//! another master is currently using the bus. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +bool +I2CMasterBusBusy(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the bus busy status. + // + if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! Controls the state of the I2C Master module. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui32Cmd command to be issued to the I2C Master module. +//! +//! This function is used to control the state of the Master module send and +//! receive operations. The \e ui8Cmd parameter can be one of the following +//! values: +//! +//! - \b I2C_MASTER_CMD_SINGLE_SEND +//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \b I2C_MASTER_CMD_BURST_SEND_START +//! - \b I2C_MASTER_CMD_BURST_SEND_CONT +//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH +//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! - \b I2C_MASTER_CMD_QUICK_COMMAND +//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND +//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND +//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE +//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START +//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT +//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH +//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP +//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START +//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT +//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH +//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND)); + + // + // Send the command. + // + HWREG(ui32Base + I2C_O_MCS) = ui32Cmd; +} + +//***************************************************************************** +// +//! Gets the error status of the I2C Master module. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function is used to obtain the error status of the Master module send +//! and receive operations. +//! +//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE, +//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or +//! \b I2C_MASTER_ERR_ARB_LOST. +// +//***************************************************************************** +uint32_t +I2CMasterErr(uint32_t ui32Base) +{ + uint32_t ui32Err; + + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Get the raw error state + // + ui32Err = HWREG(ui32Base + I2C_O_MCS); + + // + // If the I2C master is busy, then all the other bit are invalid, and + // don't have an error to report. + // + if(ui32Err & I2C_MCS_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST)) + { + return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_ACK | I2C_MCS_ADRACK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui8Data data to be transmitted from the I2C Master. +//! +//! This function places the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Write the byte. + // + HWREG(ui32Base + I2C_O_MDR) = ui8Data; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! uint32_t. +// +//***************************************************************************** +uint32_t +I2CMasterDataGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Read a byte. + // + return(HWREG(ui32Base + I2C_O_MDR)); +} + +//***************************************************************************** +// +//! Sets the Master clock timeout value. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui32Value is the number of I2C clocks before the timeout is +//! asserted. +//! +//! This function enables and configures the clock low timeout feature in the +//! I2C peripheral. This feature is implemented as a 12-bit counter, with the +//! upper 8-bits being programmable. For example, to program a timeout of 20ms +//! with a 100kHz SCL frequency, \e ui32Value would be 0x7d. +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Write the timeout value. + // + HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value; +} + +//***************************************************************************** +// +//! Configures ACK override behavior of the I2C Slave. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param bEnable enables or disables ACK override. +//! +//! This function enables or disables ACK override, allowing the user +//! application to drive the value on SDA during the ACK cycle. +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable or disable based on bEnable. + // + if(bEnable) + { + HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; + } + else + { + HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; + } +} + +//***************************************************************************** +// +//! Writes the ACK value. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer. +//! +//! This function puts the desired ACK value on SDA during the ACK cycle. The +//! value written is only valid when ACK override is enabled using +//! I2CSlaveACKOverride(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // ACK or NACK based on the value of bACK. + // + if(bACK) + { + HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; + } + else + { + HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; + } +} + +//***************************************************************************** +// +//! Gets the I2C Slave module status +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! This function returns the action requested from a master, if any. +//! Possible values are: +//! +//! - \b I2C_SLAVE_ACT_NONE +//! - \b I2C_SLAVE_ACT_RREQ +//! - \b I2C_SLAVE_ACT_TREQ +//! - \b I2C_SLAVE_ACT_RREQ_FBR +//! - \b I2C_SLAVE_ACT_OWN2SEL +//! - \b I2C_SLAVE_ACT_QCMD +//! - \b I2C_SLAVE_ACT_QCMD_DATA +//! +//! \note Not all devices support the second I2C slave's own address +//! or the quick command function. Please consult the device data sheet to +//! determine if these features are supported. +//! +//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been +//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that +//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ +//! to indicate that an I2C master has requested that the I2C Slave module send +//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent +//! data to the I2C slave and the first byte following the slave's own address +//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C +//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick +//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the +//! data bit was set when the quick command was received. +// +//***************************************************************************** +uint32_t +I2CSlaveStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the slave status. + // + return(HWREG(ui32Base + I2C_O_SCSR)); +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C Slave. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8Data is the data to be transmitted from the I2C Slave +//! +//! This function places the supplied data into I2C Slave Data Register. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Write the byte. + // + HWREG(ui32Base + I2C_O_SDR) = ui8Data; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Slave. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! uint32_t. +// +//***************************************************************************** +uint32_t +I2CSlaveDataGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Read a byte. + // + return(HWREG(ui32Base + I2C_O_SDR)); +} + +//***************************************************************************** +// +//! Configures the I2C transmit (TX) FIFO. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! \param ui32Config is the configuration of the FIFO using specified macros. +//! +//! This configures the I2C peripheral's transmit FIFO. The transmit FIFO can +//! be used by the master or slave, but not both. The following macros are +//! used to configure the TX FIFO behavior for master or slave, with or without +//! DMA: +//! +//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE, +//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA +//! +//! To select the trigger level, one of the following macros should be used: +//! +//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2, +//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4, +//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6, +//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8 +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear transmit configuration data. + // + HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000; + + // + // Store new transmit configuration data. + // + HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; +} + +//***************************************************************************** +// +//! Flushes the transmit (TX) FIFO. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! +//! This function flushes the I2C transmit FIFO. +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CTxFIFOFlush(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Flush the TX FIFO. + // + HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH; +} + +//***************************************************************************** +// +//! Configures the I2C receive (RX) FIFO. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! \param ui32Config is the configuration of the FIFO using specified macros. +//! +//! This configures the I2C peripheral's receive FIFO. The receive FIFO can be +//! used by the master or slave, but not both. The following macros are used +//! to configure the RX FIFO behavior for master or slave, with or without DMA: +//! +//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE, +//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA +//! +//! To select the trigger level, one of the following macros should be used: +//! +//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2, +//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4, +//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6, +//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8 +//! +//! +//! \return None. +// +//***************************************************************************** +void +I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Clear receive configuration data. + // + HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff; + + // + // Store new receive configuration data. + // + HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; +} + +//***************************************************************************** +// +//! Flushes the receive (RX) FIFO. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! +//! This function flushes the I2C receive FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +I2CRxFIFOFlush(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Flush the TX FIFO. + // + HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH; +} + +//***************************************************************************** +// +//! Gets the current FIFO status. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! +//! This function retrieves the status for both the transmit (TX) and receive +//! (RX) FIFOs. The trigger level for the transmit FIFO is set using +//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet(). +//! +//! \return Returns the FIFO status, enumerated as a bit field containing +//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY, +//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and +//! \b I2C_FIFO_TX_EMPTY. +// +//***************************************************************************** +uint32_t +I2CFIFOStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Return the contents of the FIFO status register. + // + return(HWREG(ui32Base + I2C_O_FIFOSTATUS)); +} + +//***************************************************************************** +// +//! Writes a data byte to the I2C transmit FIFO. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! \param ui8Data is the data to be placed into the transmit FIFO. +//! +//! This function adds a byte of data to the I2C transmit FIFO. If there is +//! no space available in the FIFO, this function waits for space to become +//! available before returning. +//! +//! \return None. +// +//***************************************************************************** +void +I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Wait until there is space. + // + while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) + { + } + + // + // Place data into the FIFO. + // + HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; +} + +//***************************************************************************** +// +//! Writes a data byte to the I2C transmit FIFO. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! \param ui8Data is the data to be placed into the transmit FIFO. +//! +//! This function adds a byte of data to the I2C transmit FIFO. If there is +//! no space available in the FIFO, this function returns a zero. +//! +//! \return The number of elements added to the I2C transmit FIFO. +// +//***************************************************************************** +uint32_t +I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // If FIFO is full, return zero. + // + if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) + { + return(0); + } + else + { + HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; + return(1); + } +} + +//***************************************************************************** +// +//! Reads a byte from the I2C receive FIFO. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! +//! This function reads a byte of data from I2C receive FIFO and places it in +//! the location specified by the \e pui8Data parameter. If there is no data +//! available, this function waits until data is received before returning. +//! +//! \return The data byte. +// +//***************************************************************************** +uint32_t +I2CFIFODataGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Wait until there is data to read. + // + while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) + { + } + + // + // Read a byte. + // + return(HWREG(ui32Base + I2C_O_FIFODATA)); +} + +//***************************************************************************** +// +//! Reads a byte from the I2C receive FIFO. +//! +//! \param ui32Base is the base address of the I2C Master or Slave module. +//! \param pui8Data is a pointer where the read data is stored. +//! +//! This function reads a byte of data from I2C receive FIFO and places it in +//! the location specified by the \e pui8Data parameter. If there is no data +//! available, this functions returns 0. +//! +//! \return The number of elements read from the I2C receive FIFO. +// +//***************************************************************************** +uint32_t +I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // If nothing in the FIFO, return zero. + // + if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) + { + return(0); + } + else + { + *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA); + return(1); + } +} + +//***************************************************************************** +// +//! Set the burst length for a I2C master FIFO operation. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui8Length is the length of the burst transfer. +//! +//! This function configures the burst length for a I2C Master FIFO operation. +//! The burst field is limited to 8 bits or 256 bytes. The burst length +//! applies to a single I2CMCS BURST operation meaning that it specifies the +//! burst length for only the current operation (can be TX or RX). Each burst +//! operation must configure the burst length prior to writing the BURST bit +//! in the I2CMCS using I2CMasterControl(). +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255)); + + // + // Set the burst length. + // + HWREG(ui32Base + I2C_O_MBLEN) = ui8Length; +} + +//***************************************************************************** +// +//! Returns the current value of the burst transfer counter. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! This function returns the current value of the burst transfer counter that +//! is used by the FIFO mechanism. Software can use this value to determine +//! how many bytes remain in a transfer, or where in the transfer the burst +//! operation was if an error has occurred. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +I2CMasterBurstCountGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Get burst count. + // + return(HWREG(ui32Base + I2C_O_MBCNT)); +} + +//***************************************************************************** +// +//! Configures the I2C Master glitch filter. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param ui32Config is the glitch filter configuration. +//! +//! This function configures the I2C Master glitch filter. The value passed in +//! to \e ui32Config determines the sampling range of the glitch filter, which +//! is configurable between 1 and 32 system clock cycles. The default +//! configuration of the glitch filter is 0 system clock cycles, which means +//! that it's disabled. +//! +//! The \e ui32Config field should be any of the following values: +//! +//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED +//! - \b I2C_MASTER_GLITCH_FILTER_1 +//! - \b I2C_MASTER_GLITCH_FILTER_2 +//! - \b I2C_MASTER_GLITCH_FILTER_3 +//! - \b I2C_MASTER_GLITCH_FILTER_4 +//! - \b I2C_MASTER_GLITCH_FILTER_8 +//! - \b I2C_MASTER_GLITCH_FILTER_16 +//! - \b I2C_MASTER_GLITCH_FILTER_32 +//! +//! \return None. +// +//***************************************************************************** +void +I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Configure the glitch filter field of MTPR. + // + HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; +} + +//***************************************************************************** +// +//! Enables FIFO usage for the I2C Slave module. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui32Config is the desired FIFO configuration of the I2C Slave. +//! +//! This function configures the I2C Slave module to use the FIFO(s). This +//! function should be used in combination with I2CTxFIFOConfigSet() and/or +//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell +//! the FIFO hardware whether to interact with the I2C Master or Slave. The +//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and +//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config +//! field. +//! +//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(), +//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration. +//! Therefore, application software should call I2CSlaveEnable() followed by +//! I2CSlaveFIFOEnable() with the desired FIFO configuration. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Enable the FIFOs for the slave. + // + HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA; +} + +//***************************************************************************** +// +//! Disable FIFO usage for the I2C Slave module. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! This function disables the FIFOs for the I2C Slave. After calling this +//! this function, the FIFOs are disabled, but the Slave remains active. +//! +//! \return None. +// +//***************************************************************************** +void +I2CSlaveFIFODisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Disable slave FIFOs. + // + HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.h new file mode 100644 index 00000000000..bd4ee41cc28 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_i2c.h @@ -0,0 +1,362 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// i2c.h +// +// Prototypes for the I2C Driver. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_I2C_H__ +#define __DRIVERLIB_I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_QUICK_COMMAND \ + 0x00000027 +#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ + 0x00000013 +#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ + 0x00000042 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ + 0x00000040 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ + 0x0000004a +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ + 0x00000048 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master glitch filter configuration. +// +//***************************************************************************** +#define I2C_MASTER_GLITCH_FILTER_DISABLED \ + 0 +#define I2C_MASTER_GLITCH_FILTER_1 \ + 0x00010000 +#define I2C_MASTER_GLITCH_FILTER_2 \ + 0x00020000 +#define I2C_MASTER_GLITCH_FILTER_3 \ + 0x00030000 +#define I2C_MASTER_GLITCH_FILTER_4 \ + 0x00040000 +#define I2C_MASTER_GLITCH_FILTER_8 \ + 0x00050000 +#define I2C_MASTER_GLITCH_FILTER_16 \ + 0x00060000 +#define I2C_MASTER_GLITCH_FILTER_32 \ + 0x00070000 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 +#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave +#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command +#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +#define I2C_MASTER_INT_RX_FIFO_FULL \ + 0x00000800 // RX FIFO Full Interrupt +#define I2C_MASTER_INT_TX_FIFO_EMPTY \ + 0x00000400 // TX FIFO Empty Interrupt +#define I2C_MASTER_INT_RX_FIFO_REQ \ + 0x00000200 // RX FIFO Request Interrupt +#define I2C_MASTER_INT_TX_FIFO_REQ \ + 0x00000100 // TX FIFO Request Interrupt +#define I2C_MASTER_INT_ARB_LOST \ + 0x00000080 // Arb Lost Interrupt +#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt +#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt +#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt +#define I2C_MASTER_INT_TX_DMA_DONE \ + 0x00000008 // TX DMA Complete Interrupt +#define I2C_MASTER_INT_RX_DMA_DONE \ + 0x00000004 // RX DMA Complete Interrupt +#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt +#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +#define I2C_SLAVE_INT_RX_FIFO_FULL \ + 0x00000100 // RX FIFO Full Interrupt +#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ + 0x00000080 // TX FIFO Empty Interrupt +#define I2C_SLAVE_INT_RX_FIFO_REQ \ + 0x00000040 // RX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_FIFO_REQ \ + 0x00000020 // TX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_DMA_DONE \ + 0x00000010 // TX DMA Complete Interrupt +#define I2C_SLAVE_INT_RX_DMA_DONE \ + 0x00000008 // RX DMA Complete Interrupt +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave FIFO configuration macros. +// +//***************************************************************************** +#define I2C_SLAVE_TX_FIFO_ENABLE \ + 0x00000002 +#define I2C_SLAVE_RX_FIFO_ENABLE \ + 0x00000004 + +//***************************************************************************** +// +// I2C FIFO configuration macros. +// +//***************************************************************************** +#define I2C_FIFO_CFG_TX_MASTER 0x00000000 +#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 +#define I2C_FIFO_CFG_RX_MASTER 0x00000000 +#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 +#define I2C_FIFO_CFG_TX_MASTER_DMA \ + 0x00002000 +#define I2C_FIFO_CFG_TX_SLAVE_DMA \ + 0x0000a000 +#define I2C_FIFO_CFG_RX_MASTER_DMA \ + 0x20000000 +#define I2C_FIFO_CFG_RX_SLAVE_DMA \ + 0xa0000000 +#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 +#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 +#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 +#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 +#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 +#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 +#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 +#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 +#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 +#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 +#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 +#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 +#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 +#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 +#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 +#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 + +//***************************************************************************** +// +// I2C FIFO status. +// +//***************************************************************************** +#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ + 0x00040000 +#define I2C_FIFO_RX_FULL 0x00020000 +#define I2C_FIFO_RX_EMPTY 0x00010000 +#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ + 0x00000004 +#define I2C_FIFO_TX_FULL 0x00000002 +#define I2C_FIFO_TX_EMPTY 0x00000001 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void)); +extern void I2CIntUnregister(uint32_t ui32Base); +extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CTxFIFOFlush(uint32_t ui32Base); +extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CRxFIFOFlush(uint32_t ui32Base); +extern uint32_t I2CFIFOStatus(uint32_t ui32Base); +extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); +extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, + uint8_t ui8Data); +extern uint32_t I2CFIFODataGet(uint32_t ui32Base); +extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, + uint8_t *pui8Data); +extern void I2CMasterBurstLengthSet(uint32_t ui32Base, + uint8_t ui8Length); +extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); +extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, + uint32_t ui32Config); +extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CSlaveFIFODisable(uint32_t ui32Base); +extern bool I2CMasterBusBusy(uint32_t ui32Base); +extern bool I2CMasterBusy(uint32_t ui32Base); +extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); +extern uint32_t I2CMasterDataGet(uint32_t ui32Base); +extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CMasterDisable(uint32_t ui32Base); +extern void I2CMasterEnable(uint32_t ui32Base); +extern uint32_t I2CMasterErr(uint32_t ui32Base); +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); +extern void I2CMasterIntClear(uint32_t ui32Base); +extern void I2CMasterIntDisable(uint32_t ui32Base); +extern void I2CMasterIntEnable(uint32_t ui32Base); +extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); +extern void I2CMasterIntEnableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern void I2CMasterIntClearEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); +extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); +extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); +extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); +extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, + uint8_t ui8SlaveAddr, + bool bReceive); +extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); +extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CSlaveDisable(uint32_t ui32Base); +extern void I2CSlaveEnable(uint32_t ui32Base); +extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); +extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, + uint8_t ui8SlaveAddr); +extern void I2CSlaveIntClear(uint32_t ui32Base); +extern void I2CSlaveIntDisable(uint32_t ui32Base); +extern void I2CSlaveIntEnable(uint32_t ui32Base); +extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void I2CSlaveIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); +extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern uint32_t I2CSlaveStatus(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_I2C_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.c new file mode 100644 index 00000000000..7c19126021d --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.c @@ -0,0 +1,1528 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// spi.c +// +// Driver for the SPI. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup SPI_Serial_Peripheral_Interface_api +//! @{ +// +//***************************************************************************** + + +#include "inc/hw_ints.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_mcspi.h" +#include "inc/hw_apps_config.h" +#include "interrupt.h" +#include "ti_spi_driverlib.h" + + +//***************************************************************************** +// +// A mapping of SPI base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulSPIIntMap[][3] = +{ + { SSPI_BASE, INT_SSPI }, // Shared SPI + { GSPI_BASE, INT_GSPI }, // Generic SPI + { LSPI_BASE, INT_LSPI }, // LINK SPI +}; + +//***************************************************************************** +// +// A mapping of SPI base address to DMA done interrupt mask bit(s). +// +//***************************************************************************** +static const unsigned long g_ulSPIDmaMaskMap[][2]= +{ + {SSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK}, + {LSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK}, + {GSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK}, +}; + +//***************************************************************************** +// +//! \internal +//! Transfer bytes over SPI channel +//! +//! \param ulBase is the base address of SPI module +//! \param ucDout is the pointer to Tx data buffer or 0. +//! \param ucDin is pointer to Rx data buffer or 0 +//! \param ulCount is the size of data in bytes. +//! +//! This function transfers \e ulCount bytes of data over SPI channel. +//! +//! The function will not return until data has been transmitted +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout, + unsigned char *ucDin, unsigned long ulCount, + unsigned long ulFlags) +{ + unsigned long ulReadReg; + unsigned long ulWriteReg; + unsigned long ulStatReg; + unsigned long ulOutIncr; + unsigned long ulInIncr; + unsigned long ulTxDummy; + unsigned long ulRxDummy; + + // + // Initialize the variables + // + ulOutIncr = 1; + ulInIncr = 1; + + // + // Check if output buffer pointer is 0 + // + if(ucDout == 0) + { + ulOutIncr = 0; + ulTxDummy = 0xFFFFFFFF; + ucDout = (unsigned char *)&ulTxDummy; + } + + // + // Check if input buffer pointer is 0 + // + if(ucDin == 0) + { + ulInIncr = 0; + ucDin = (unsigned char *)&ulRxDummy; + } + + // + // Load the register addresses. + // + ulReadReg = (ulBase + MCSPI_O_RX0); + ulWriteReg = (ulBase + MCSPI_O_TX0); + ulStatReg = (ulBase + MCSPI_O_CH0STAT); + + // + // Enable CS based on Flag + // + if( ulFlags & SPI_CS_ENABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; + } + + while(ulCount) + { + // + // Wait for space in output register/FIFO. + // + while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) + { + } + + // + // Write the data + // + HWREG(ulWriteReg) = *ucDout; + + // + // Wait for data in input register/FIFO. + // + while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) + { + } + + // + // Read the data + // + *ucDin = HWREG(ulReadReg); + + // + // Increment pointers. + // + ucDout = ucDout + ulOutIncr; + ucDin = ucDin + ulInIncr; + + // + // Decrement the count. + // + ulCount--; + } + + // + // Disable CS based on Flag + // + if( ulFlags & SPI_CS_DISABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; + } + + return 0; +} + +//***************************************************************************** +// +//! \internal +//! Transfer half-words over SPI channel +//! +//! \param ulBase is the base address of SPI module +//! \param usDout is the pointer to Tx data buffer or 0. +//! \param usDin is pointer to Rx data buffer or 0 +//! \param ulCount is the size of data in bytes. +//! +//! This function transfers \e ulCount bytes of data over SPI channel. Since +//! the API sends a half-word at a time \e ulCount should be a multiple +//! of two. +//! +//! The function will not return until data has been transmitted +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +static long SPITransfer16(unsigned long ulBase, unsigned short *usDout, + unsigned short *usDin, unsigned long ulCount, + unsigned long ulFlags) +{ + unsigned long ulReadReg; + unsigned long ulWriteReg; + unsigned long ulStatReg; + unsigned long ulOutIncr; + unsigned long ulInIncr; + unsigned long ulTxDummy; + unsigned long ulRxDummy; + + // + // Initialize the variables. + // + ulOutIncr = 1; + ulInIncr = 1; + + // + // Check if count is multiple of half-word + // + if(ulCount%2) + { + return -1; + } + + // + // Compute number of half words. + // + ulCount = ulCount/2; + + // + // Check if output buffer pointer is 0 + // + if(usDout == 0) + { + ulOutIncr = 0; + ulTxDummy = 0xFFFFFFFF; + usDout = (unsigned short *)&ulTxDummy; + } + + // + // Check if input buffer pointer is 0 + // + if(usDin == 0) + { + ulInIncr = 0; + usDin = (unsigned short *)&ulRxDummy; + } + + // + // Load the register addresses. + // + ulReadReg = (ulBase + MCSPI_O_RX0); + ulWriteReg = (ulBase + MCSPI_O_TX0); + ulStatReg = (ulBase + MCSPI_O_CH0STAT); + + // + // Enable CS based on Flag + // + if( ulFlags & SPI_CS_ENABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; + } + + while(ulCount) + { + // + // Wait for space in output register/FIFO. + // + while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) + { + } + + // + // Write the data + // + HWREG(ulWriteReg) = *usDout; + + // + // Wait for data in input register/FIFO. + // + while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) + { + } + + // + // Read the data + // + *usDin = HWREG(ulReadReg); + + // + // Increment pointers. + // + usDout = usDout + ulOutIncr; + usDin = usDin + ulInIncr; + + // + // Decrement the count. + // + ulCount--; + } + + // + // Disable CS based on Flag + // + if( ulFlags & SPI_CS_DISABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; + } + + return 0; +} + +//***************************************************************************** +// +//! \internal +//! Transfer words over SPI channel +//! +//! \param ulBase is the base address of SPI module +//! \param ulDout is the pointer to Tx data buffer or 0. +//! \param ulDin is pointer to Rx data buffer or 0 +//! \param ulCount is the size of data in bytes. +//! +//! This function transfers \e ulCount bytes of data over SPI channel. Since +//! the API sends a word at a time \e ulCount should be a multiple of four. +//! +//! The function will not return until data has been transmitted +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout, + unsigned long *ulDin, unsigned long ulCount, + unsigned long ulFlags) +{ + unsigned long ulReadReg; + unsigned long ulWriteReg; + unsigned long ulStatReg; + unsigned long ulOutIncr; + unsigned long ulInIncr; + unsigned long ulTxDummy; + unsigned long ulRxDummy; + + // + // Initialize the variables. + // + ulOutIncr = 1; + ulInIncr = 1; + + // + // Check if count is multiple of word + // + if(ulCount%4) + { + return -1; + } + + // + // Compute the number of words to be transferd + // + ulCount = ulCount/4; + + // + // Check if output buffer pointer is 0 + // + if(ulDout == 0) + { + ulOutIncr = 0; + ulTxDummy = 0xFFFFFFFF; + ulDout = &ulTxDummy; + } + + // + // Check if input buffer pointer is 0 + // + if(ulDin == 0) + { + ulInIncr = 0; + ulDin = &ulRxDummy; + } + + + // + // Load the register addresses. + // + ulReadReg = (ulBase + MCSPI_O_RX0); + ulWriteReg = (ulBase + MCSPI_O_TX0); + ulStatReg = (ulBase + MCSPI_O_CH0STAT); + + // + // Enable CS based on Flag + // + if( ulFlags & SPI_CS_ENABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; + } + + while(ulCount) + { + // + // Wait for space in output register/FIFO. + // + while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) ) + { + } + + // + // Write the data + // + HWREG(ulWriteReg) = *ulDout; + + // + // Wait for data in input register/FIFO. + // + while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) ) + { + } + + // + // Read the data + // + *ulDin = HWREG(ulReadReg); + + // + // Increment pointers. + // + ulDout = ulDout + ulOutIncr; + ulDin = ulDin + ulInIncr; + + // + // Decrement the count. + // + ulCount--; + } + + // + // Disable CS based on Flag + // + if( ulFlags & SPI_CS_DISABLE) + { + HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; + } + + return 0; +} + +//***************************************************************************** +// +//! \internal +//! Gets the SPI interrupt number. +//! +//! \param ulBase is the base address of the SPI module +//! +//! Given a SPI base address, returns the corresponding interrupt number. +//! +//! \return Returns a SPI interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +SPIIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps SPI base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulSPIIntMap) / + sizeof(g_ppulSPIIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulSPIIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulSPIIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! \internal +//! Gets the SPI DMA interrupt mask bit. +//! +//! \param ulBase is the base address of the SPI module +//! +//! Given a SPI base address, DMA interrupt mask bit. +//! +//! \return Returns a DMA interrupt mask bit, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +SPIDmaMaskGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps SPI base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ulSPIDmaMaskMap) / + sizeof(g_ulSPIDmaMaskMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ulSPIDmaMaskMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ulSPIDmaMaskMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the SPI module +//! +//! This function enables the SPI channel for transmitting and receiving. +//! +//! \return None +//! +// +//***************************************************************************** +void +SPIEnable(unsigned long ulBase) +{ + // + // Set Channel Enable Bit + // + HWREG(ulBase + MCSPI_O_CH0CTRL) |= MCSPI_CH0CTRL_EN; +} + +//***************************************************************************** +// +//! Disables the transmitting and receiving. +//! +//! \param ulBase is the base address of the SPI module +//! +//! This function disables the SPI channel for transmitting and receiving. +//! +//! \return None +//! +// +//***************************************************************************** +void +SPIDisable(unsigned long ulBase) +{ + // + // Reset Channel Enable Bit + // + HWREG(ulBase + MCSPI_O_CH0CTRL) &= ~MCSPI_CH0CTRL_EN; +} + + +//***************************************************************************** +// +//! Enables the SPI DMA operation for transmitting and/or receving. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulFlags selectes the DMA signal for transmit and/or receive. +//! +//! This function enables transmit and/or receive DMA request based on the +//! \e ulFlags parameter. +//! +//! The parameter \e ulFlags is the logical OR of one or more of +//! the following : +//! - \b SPI_RX_DMA +//! - \b SPI_TX_DMA +//! +//! \return None. +// +//***************************************************************************** +void +SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Enable DMA based on ulFlags + // + HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags; +} + +//***************************************************************************** +// +//! Disables the SPI DMA operation for transmitting and/or receving. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulFlags selectes the DMA signal for transmit and/or receive. +//! +//! This function disables transmit and/or receive DMA request based on the +//! \e ulFlags parameter. +//! +//! The parameter \e ulFlags is the logical OR of one or more of +//! the following : +//! - \b SPI_RX_DMA +//! - \b SPI_TX_DMA +//! +//! \return None. +// +//***************************************************************************** +void +SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Disable DMA based on ulFlags + // + HWREG(ulBase + MCSPI_O_CH0CONF) &= ~ulFlags; +} + +//***************************************************************************** +// +//! Performs a software reset of the specified SPI module +//! +//! \param ulBase is the base address of the SPI module +//! +//! This function performs a software reset of the specified SPI module +//! +//! \return None. +// +//***************************************************************************** +void +SPIReset(unsigned long ulBase) +{ + + // + // Assert soft reset (auto clear) + // + HWREG(ulBase + MCSPI_O_SYSCONFIG) |= MCSPI_SYSCONFIG_SOFTRESET; + + // + // wait until reset is done + // + while(!(HWREG(ulBase + MCSPI_O_SYSSTATUS)& MCSPI_SYSSTATUS_RESETDONE)) + { + } +} + +//***************************************************************************** +// +//! Sets the configuration of a SPI module +//! +//! \param ulBase is the base address of the SPI module +//! \param ulSPIClk is the rate of clock supplied to the SPI module. +//! \param ulBitRate is the desired bit rate.(master mode) +//! \param ulMode is the mode of operation. +//! \param ulSubMode is one of the valid sub-modes. +//! \param ulConfig is logical OR of configuration paramaters. +//! +//! This function configures SPI port for operation in specified sub-mode and +//! required bit rated as specified by \e ulMode and \e ulBitRate parameters +//! respectively. +//! +//! The SPI module can operate in either master or slave mode. The parameter +//! \e ulMode can be one of the following +//! -\b SPI_MODE_MASTER +//! -\b SPI_MODE_SLAVE +//! +//! The SPI module supports 4 sub modes based on SPI clock polarity and phase. +//! +//! 
+//! Polarity Phase  Sub-Mode
+//!   0       0        0
+//!   0       1        1
+//!   1       0        2
+//!   1       1        3
+//!
+//! +//! Required sub mode can be select by setting \e ulSubMode parameter to one +//! of the following +//! - \b SPI_SUB_MODE_0 +//! - \b SPI_SUB_MODE_1 +//! - \b SPI_SUB_MODE_2 +//! - \b SPI_SUB_MODE_3 +//! +//! The parameter \e ulConfig is logical OR of five values: the word length, +//! active level for chip select, software or hardware controled chip select, +//! 3 or 4 pin mode and turbo mode. +//! mode. +//! +//! SPI support 8, 16 and 32 bit word lengths defined by:- +//! - \b SPI_WL_8 +//! - \b SPI_WL_16 +//! - \b SPI_WL_32 +//! +//! Active state of Chip[ Selece can be defined by:- +//! - \b SPI_CS_ACTIVELOW +//! - \b SPI_CS_ACTIVEHIGH +//! +//! SPI chip select can be configured to be controlled either by hardware or +//! software:- +//! - \b SPI_SW_CS +//! - \b SPI_HW_CS +//! +//! The module can work in 3 or 4 pin mode defined by:- +//! - \b SPI_3PIN_MODE +//! - \b SPI_4PIN_MODE +//! +//! Turbo mode can be set on or turned off using:- +//! - \b SPI_TURBO_MODE_ON +//! - \b SPI_TURBO_MODE_OFF +//! +//! \return None. +// +//***************************************************************************** +void +SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, + unsigned long ulBitRate, unsigned long ulMode, + unsigned long ulSubMode, unsigned long ulConfig) +{ + + unsigned long ulRegData; + unsigned long ulDivider; + + // + // Read MODULCTRL register + // + ulRegData = HWREG(ulBase + MCSPI_O_MODULCTRL); + + // + // Set Master mode with h/w chip select + // + ulRegData &= ~(MCSPI_MODULCTRL_MS | + MCSPI_MODULCTRL_SINGLE); + + // + // Enable software control Chip Select, Init delay + // and 3-pin mode + // + ulRegData |= (((ulConfig >> 24) | ulMode) & 0xFF); + + // + // Write the configuration + // + HWREG(ulBase + MCSPI_O_MODULCTRL) = ulRegData; + + // + // Set IS, DPE0, DPE1 based on master or slave mode + // + if(ulMode == SPI_MODE_MASTER) + { + ulRegData = 0x1 << 16; + } + else + { + ulRegData = 0x6 << 16; + } + + // + // Mask the configurations and set clock divider granularity + // to 1 cycle + // + ulRegData = (ulRegData & (~(MCSPI_CH0CONF_WL_M | + MCSPI_CH0CONF_EPOL | + MCSPI_CH0CONF_POL | + MCSPI_CH0CONF_PHA | + MCSPI_CH0CONF_TURBO ) | + MCSPI_CH0CONF_CLKG)); + + // + // Get the divider value + // + ulDivider = ((ulSPIClk/ulBitRate) - 1); + + // + // The least significant four bits of the divider is used fo configure + // CLKD in MCSPI_CHCONF next eight least significant bits are used to + // configure the EXTCLK in MCSPI_CHCTRL + // + ulRegData |= ((ulDivider & 0x0000000F) << 2); + HWREG(ulBase + MCSPI_O_CH0CTRL) = ((ulDivider & 0x00000FF0) << 4); + + // + // Set the protocol, CS polarity, word length + // and turbo mode + // + ulRegData = ((ulRegData | + ulSubMode) | (ulConfig & 0x0008FFFF)); + + // + // Write back the CONF register + // + HWREG(ulBase + MCSPI_O_CH0CONF) = ulRegData; + +} + +//***************************************************************************** +// +//! Receives a word from the specified port. +//! +//! \param ulBase is the base address of the SPI module. +//! \param pulData is pointer to receive data variable. +//! +//! This function gets a SPI word from the receive FIFO for the specified +//! port. +//! +//! \return Returns the number of elements read from the receive FIFO. +// +//***************************************************************************** +long +SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) +{ + unsigned long ulRegVal; + + // + // Read register status register + // + ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT); + + // + // Check is data is available + // + if(ulRegVal & MCSPI_CH0STAT_RXS) + { + *pulData = HWREG(ulBase + MCSPI_O_RX0); + return(1); + } + + return(0); +} + +//***************************************************************************** +// +//! Waits for the word to be received on the specified port. +//! +//! \param ulBase is the base address of the SPI module. +//! \param pulData is pointer to receive data variable. +//! +//! This function gets a SPI word from the receive FIFO for the specified +//! port. If there is no word available, this function waits until a +//! word is received before returning. +//! +//! \return Returns the word read from the specified port, cast as an +//! \e unsigned long. +// +//***************************************************************************** +void +SPIDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Wait for Rx data + // + while(!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS)) + { + } + + // + // Read the value + // + *pulData = HWREG(ulBase + MCSPI_O_RX0); +} + +//***************************************************************************** +// +//! Transmits a word on the specified port. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulData is data to be transmitted. +//! +//! This function transmits a SPI word on the transmit FIFO for the specified +//! port. +//! +//! \return Returns the number of elements written to the transmit FIFO. +//! +//***************************************************************************** +long +SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) +{ + unsigned long ulRegVal; + + // + // Read status register + // + ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT); + + // + // Write value into Tx register/FIFO + // if space is available + // + if(ulRegVal & MCSPI_CH0STAT_TXS) + { + HWREG(ulBase + MCSPI_O_TX0) = ulData; + return(1); + } + + return(0); +} + +//***************************************************************************** +// +//! Waits until the word is transmitted on the specified port. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulData is data to be transmitted. +//! +//! This function transmits a SPI word on the transmit FIFO for the specified +//! port. This function waits until the space is available on transmit FIFO +//! +//! \return None +//! +//***************************************************************************** +void +SPIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Wait for space in FIFO + // + while(!(HWREG(ulBase + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS)) + { + } + + // + // Write the data + // + HWREG(ulBase + MCSPI_O_TX0) = ulData; +} + +//***************************************************************************** +// +//! Enables the transmit and/or receive FIFOs. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulFlags selects the FIFO(s) to be enabled +//! +//! This function enables the transmit and/or receive FIFOs as specified by +//! \e ulFlags. +//! The parameter \e ulFlags shoulde be logical OR of one or more of the +//! following: +//! - \b SPI_TX_FIFO +//! - \b SPI_RX_FIFO +//! +//! \return None. +// +//***************************************************************************** +void +SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Set FIFO enable bits. + // + HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags; +} + +//***************************************************************************** +// +//! Disables the transmit and/or receive FIFOs. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulFlags selects the FIFO(s) to be enabled +//! +//! This function disables transmit and/or receive FIFOs. as specified by +//! \e ulFlags. +//! The parameter \e ulFlags shoulde be logical OR of one or more of the +//! following: +//! - \b SPI_TX_FIFO +//! - \b SPI_RX_FIFO +//! +//! \return None. +// +//***************************************************************************** +void +SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags) +{ + // + // Reset FIFO Enable bits. + // + HWREG(ulBase + MCSPI_O_CH0CONF) &= ~(ulFlags); +} + +//***************************************************************************** +// +//! Sets the FIFO level at which DMA requests or interrupts are generated. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulTxLevel is the Almost Empty Level for transmit FIFO. +//! \param ulRxLevel is the Almost Full Level for the receive FIFO. +//! +//! This function Sets the FIFO level at which DMA requests or interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel) +{ + unsigned long ulRegVal; + + // + // Read the current configuration + // + ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); + + // + // Mask and set new FIFO thresholds. + // + ulRegVal = ((ulRegVal & 0xFFFF0000) | (((ulRxLevel-1) << 8) | (ulTxLevel-1))); + + // + // Set the transmit and receive FIFO thresholds. + // + HWREG(ulBase + MCSPI_O_XFERLEVEL) = ulRegVal; + +} + +//***************************************************************************** +// +//! Gets the FIFO level at which DMA requests or interrupts are generated. +//! +//! \param ulBase is the base address of the SPI module +//! \param pulTxLevel is a pointer to storage for the transmit FIFO level +//! \param pulRxLevel is a pointer to storage for the receive FIFO level +//! +//! This function gets the FIFO level at which DMA requests or interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel) +{ + unsigned long ulRegVal; + + // + // Read the current configuration + // + ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); + + *pulTxLevel = (ulRegVal & 0xFF); + + *pulRxLevel = ((ulRegVal >> 8) & 0xFF); + +} + +//***************************************************************************** +// +//! Sets the word count. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulWordCount is number of SPI words to be transmitted. +//! +//! This function sets the word count, which is the number of SPI word to +//! be transferred on channel when using the FIFO buffer. +//! +//! \return None. +// +//***************************************************************************** +void +SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount) +{ + unsigned long ulRegVal; + + // + // Read the current configuration + // + ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); + + // + // Mask and set the word count + // + HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF)| + (ulWordCount & 0xFFFF) << 16); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a SPI interrupt. +//! +//! \param ulBase is the base address of the SPI module +//! \param pfnHandler is a pointer to the function to be called when the +//! SPI interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! SPI interrupts must be enabled via SPIIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Determine the interrupt number based on the SPI module + // + ulInt = SPIIntNumberGet(ulBase); + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the SPI interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a SPI interrupt. +//! +//! \param ulBase is the base address of the SPI module +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a SPI interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Determine the interrupt number based on the SPI module + // + ulInt = SPIIntNumberGet(ulBase); + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual SPI interrupt sources. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SPI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b SPI_INT_DMATX +//! - \b SPI_INT_DMARX +//! - \b SPI_INT_EOW +//! - \b SPI_INT_RX_OVRFLOW +//! - \b SPI_INT_RX_FULL +//! - \b SPI_INT_TX_UDRFLOW +//! - \b SPI_INT_TX_EMPTY +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + unsigned long ulDmaMsk; + + // + // Enable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMATX) + { + ulDmaMsk = SPIDmaMaskGet(ulBase); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; + } + + // + // Enable DMA Rx Interrupt + // + if(ulIntFlags & SPI_INT_DMARX) + { + ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; + } + + // + // Enable the specific Interrupts + // + HWREG(ulBase + MCSPI_O_IRQENABLE) |= (ulIntFlags & 0x0003000F); +} + + +//***************************************************************************** +// +//! Disables individual SPI interrupt sources. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated SPI interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to SPIIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + unsigned long ulDmaMsk; + + // + // Disable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMATX) + { + ulDmaMsk = SPIDmaMaskGet(ulBase); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; + } + + // + // Disable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMARX) + { + ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; + } + + // + // Disable the specific Interrupts + // + HWREG(ulBase + MCSPI_O_IRQENABLE) &= ~(ulIntFlags & 0x0003000F); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the SPI module +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the specified SPI. +//! The status of interrupts that are allowed to reflect to the processor can +//! be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in SPIIntEnable(). +// +//***************************************************************************** +unsigned long +SPIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + unsigned long ulIntStat; + unsigned long ulIntFlag; + unsigned long ulDmaMsk; + + // + // Get SPI interrupt status + // + ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F; + + if(bMasked) + { + ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE); + } + + // + // Get the interrupt bit + // + ulDmaMsk = SPIDmaMaskGet(ulBase); + + // + // Get the DMA interrupt status + // + if(bMasked) + { + ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED); + } + else + { + ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW); + } + + // + // Get SPI Tx DMA done status + // + if(ulIntStat & ulDmaMsk) + { + ulIntFlag |= SPI_INT_DMATX; + } + + // + // Get SPI Rx DMA done status + // + if(ulIntStat & (ulDmaMsk >> 1)) + { + ulIntFlag |= SPI_INT_DMARX; + } + + // + // Return status + // + return(ulIntFlag); +} + +//***************************************************************************** +// +//! Clears SPI interrupt sources. +//! +//! \param ulBase is the base address of the SPI module +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SPI interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to SPIIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + unsigned long ulDmaMsk; + + // + // Disable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMATX) + { + ulDmaMsk = SPIDmaMaskGet(ulBase); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; + } + + // + // Disable DMA Tx Interrupt + // + if(ulIntFlags & SPI_INT_DMARX) + { + ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; + } + + // + // Clear Interrupts + // + HWREG(ulBase + MCSPI_O_IRQSTATUS) = (ulIntFlags & 0x0003000F); +} + +//***************************************************************************** +// +//! Enables the chip select in software controlled mode +//! +//! \param ulBase is the base address of the SPI module. +//! +//! This function enables the Chip select in software controlled mode. The +//! active state of CS will depend on the configuration done via +//! \sa SPIConfigExpClkSet(). +//! +//! \return None. +// +//***************************************************************************** +void SPICSEnable(unsigned long ulBase) +{ + // + // Set Chip Select enable bit. + // + HWREG( ulBase+MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; +} + +//***************************************************************************** +// +//! Disables the chip select in software controlled mode +//! +//! \param ulBase is the base address of the SPI module. +//! +//! This function disables the Chip select in software controlled mode. The +//! active state of CS will depend on the configuration done via +//! sa SPIConfigSetExpClk(). +//! +//! \return None. +// +//***************************************************************************** +void SPICSDisable(unsigned long ulBase) +{ + // + // Reset Chip Select enable bit. + // + HWREG( ulBase+MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; +} + +//***************************************************************************** +// +//! Send/Receive data buffer over SPI channel +//! +//! \param ulBase is the base address of SPI module +//! \param ucDout is the pointer to Tx data buffer or 0. +//! \param ucDin is pointer to Rx data buffer or 0 +//! \param ulCount is the size of data in bytes. +//! \param ulFlags controlls chip select toggling. +//! +//! This function transfers \e ulCount bytes of data over SPI channel. Since +//! the API sends a SPI word at a time \e ulCount should be a multiple of +//! word length set using SPIConfigSetExpClk(). +//! +//! If the \e ucDout parameter is set to 0, the function will send 0xFF over +//! the SPI MOSI line. +//! +//! If the \e ucDin parameter is set to 0, the function will ignore data on SPI +//! MISO line. +//! +//! The parameter \e ulFlags is logical OR of one or more of the following +//! +//! - \b SPI_CS_ENABLE if CS needs to be enabled at start of transfer. +//! - \b SPI_CS_DISABLE if CS need to be disabled at the end of transfer. +//! +//! This function will not return until data has been transmitted +//! +//! \return Returns 0 on success, -1 otherwise. +// +//***************************************************************************** +long SPITransfer(unsigned long ulBase, unsigned char *ucDout, + unsigned char *ucDin, unsigned long ulCount, + unsigned long ulFlags) +{ + unsigned long ulWordLength; + long lRet; + + // + // Get the word length + // + ulWordLength = (HWREG(ulBase + MCSPI_O_CH0CONF) & MCSPI_CH0CONF_WL_M); + + // + // Check for word length. + // + if( !((ulWordLength == SPI_WL_8) || (ulWordLength == SPI_WL_16) || + (ulWordLength == SPI_WL_32)) ) + { + return -1; + } + + if( ulWordLength == SPI_WL_8 ) + { + // + // Do byte transfer + // + lRet = SPITransfer8(ulBase,ucDout,ucDin,ulCount,ulFlags); + } + else if( ulWordLength == SPI_WL_16 ) + { + + // + // Do half-word transfer + // + lRet = SPITransfer16(ulBase,(unsigned short *)ucDout, + (unsigned short *)ucDin,ulCount,ulFlags); + } + else + { + // + // Do word transfer + // + lRet = SPITransfer32(ulBase,(unsigned long *)ucDout, + (unsigned long *)ucDin,ulCount,ulFlags); + } + + // + // return + // + return lRet; + +} +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.h new file mode 100644 index 00000000000..6a2aa50c90f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_spi_driverlib.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// spi.h +// +// Defines and Macros for the SPI. +// +//***************************************************************************** + +#ifndef __SPI_H__ +#define __SPI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter +//***************************************************************************** +#define SPI_MODE_MASTER 0x00000000 +#define SPI_MODE_SLAVE 0x00000004 + +//***************************************************************************** +// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter +//***************************************************************************** +#define SPI_SUB_MODE_0 0x00000000 +#define SPI_SUB_MODE_1 0x00000001 +#define SPI_SUB_MODE_2 0x00000002 +#define SPI_SUB_MODE_3 0x00000003 + + +//***************************************************************************** +// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter +//***************************************************************************** +#define SPI_SW_CTRL_CS 0x01000000 +#define SPI_HW_CTRL_CS 0x00000000 +#define SPI_3PIN_MODE 0x02000000 +#define SPI_4PIN_MODE 0x00000000 +#define SPI_TURBO_ON 0x00080000 +#define SPI_TURBO_OFF 0x00000000 +#define SPI_CS_ACTIVEHIGH 0x00000000 +#define SPI_CS_ACTIVELOW 0x00000040 +#define SPI_WL_8 0x00000380 +#define SPI_WL_16 0x00000780 +#define SPI_WL_32 0x00000F80 + +//***************************************************************************** +// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable() +//***************************************************************************** +#define SPI_TX_FIFO 0x08000000 +#define SPI_RX_FIFO 0x10000000 + +//***************************************************************************** +// Values that can be passed to SPIDMAEnable() and SPIDMADisable() +//***************************************************************************** +#define SPI_RX_DMA 0x00008000 +#define SPI_TX_DMA 0x00004000 + +//***************************************************************************** +// Values that can be passed to SPIIntEnable(), SPIIntDiasble(), +// SPIIntClear() or returned from SPIStatus() +//***************************************************************************** +#define SPI_INT_DMATX 0x20000000 +#define SPI_INT_DMARX 0x10000000 +#define SPI_INT_EOW 0x00020000 +#define SPI_INT_WKS 0x00010000 +#define SPI_INT_RX_OVRFLOW 0x00000008 +#define SPI_INT_RX_FULL 0x00000004 +#define SPI_INT_TX_UDRFLOW 0x00000002 +#define SPI_INT_TX_EMPTY 0x00000001 + +//***************************************************************************** +// Values that can be passed to SPITransfer() +//***************************************************************************** +#define SPI_CS_ENABLE 0x00000001 +#define SPI_CS_DISABLE 0x00000002 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void SPIEnable(unsigned long ulBase); +extern void SPIDisable(unsigned long ulBase); +extern void SPIReset(unsigned long ulBase); +extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, + unsigned long ulBitRate, unsigned long ulMode, + unsigned long ulSubMode, unsigned long ulConfig); +extern long SPIDataGetNonBlocking(unsigned long ulBase, + unsigned long * pulData); +extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SPIDataPutNonBlocking(unsigned long ulBase, + unsigned long ulData); +extern void SPIDataPut(unsigned long ulBase, unsigned long ulData); +extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags); +extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags); +extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount); +extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void SPIIntUnregister(unsigned long ulBase); +extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags); +extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags); +extern void SPICSEnable(unsigned long ulBase); +extern void SPICSDisable(unsigned long ulBase); +extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout, + unsigned char *ucDin, unsigned long ulSize, + unsigned long ulFlags); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SPI_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.c new file mode 100644 index 00000000000..33689376a0e --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.c @@ -0,0 +1,1105 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// timer.c +// +// Driver for the timer module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup GPT_General_Purpose_Timer_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_timer.h" +#include "inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "ti_timer.h" + + +//***************************************************************************** +// +//! \internal +//! Checks a timer base address. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function determines if a timer module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +TimerBaseValid(unsigned long ulBase) +{ + return((ulBase == TIMERA0_BASE) || (ulBase == TIMERA1_BASE) || + (ulBase == TIMERA2_BASE) || (ulBase == TIMERA3_BASE)); +} +#endif + +//***************************************************************************** +// +//! Enables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function enables operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +TimerEnable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Enable the timer(s) module. + // + HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); +} + +//***************************************************************************** +// +//! Disables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to disable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function disables operation of the timer module. +//! +//! \return None. +// +//***************************************************************************** +void +TimerDisable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Disable the timer module. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & + (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); +} + +//***************************************************************************** +// +//! Configures the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulConfig is the configuration for the timer. +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured, and is left in the disabled +//! state. The 16/32-bit timer is comprised of two 16-bit timers that can +//! operate independently or be concatenated to form a 32-bit timer. +//! +//! The configuration is specified in \e ulConfig as one of the following +//! values: +//! +//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer +//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer +//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers +//! +//! When configured for a pair of half-width timers, each timer is separately +//! configured. The first timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the following values +//! and \e ulConfig: +//! +//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer +//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer +//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up +//! instead of down (not available on all parts) +//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture +//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture +//! - \b TIMER_CFG_A_PWM - Half-width PWM output +//! +//! Similarly, the second timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the corresponding +//! \b TIMER_CFG_B_* values and \e ulConfig. +//! +//! \return None. +// +//***************************************************************************** +void +TimerConfigure(unsigned long ulBase, unsigned long ulConfig) +{ + + ASSERT( (ulConfig == TIMER_CFG_ONE_SHOT) || + (ulConfig == TIMER_CFG_ONE_SHOT_UP) || + (ulConfig == TIMER_CFG_PERIODIC) || + (ulConfig == TIMER_CFG_PERIODIC_UP) || + (((ulConfig & 0xff000000) == TIMER_CFG_SPLIT_PAIR) && + ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) || + (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))))); + + + // + // Enable CCP to IO path + // + HWREG(0x440260B0) = 0xFF; + + // + // Disable the timers. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; + HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; +} + +//***************************************************************************** +// +//! Controls the output level. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bInvert specifies the output level. +//! +//! This function sets the PWM output level for the specified timer. If the +//! \e bInvert parameter is \b true, then the timer's output is made active +//! low; otherwise, it is made active high. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; + HWREG(ulBase + TIMER_O_CTL) = (bInvert ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} + +//***************************************************************************** +// +//! Controls the event type. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ulEvent specifies the type of event; must be one of +//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or +//! \b TIMER_EVENT_BOTH_EDGES. +//! +//! This function sets the signal edge(s) that triggers the timer when in +//! capture mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the event type. + // + ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M); + HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & + ~(TIMER_CTL_TAEVENT_M | + TIMER_CTL_TBEVENT_M)) | ulEvent); +} + +//***************************************************************************** +// +//! Controls the stall handling. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bStall specifies the response to a stall signal. +//! +//! This function controls the stall response for the specified timer. If the +//! \e bStall parameter is \b true, then the timer stops counting if the +//! processor enters debug mode; otherwise the timer keeps running while in +//! debug mode. +//! +//! \return None. +// +//***************************************************************************** +void +TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; + HWREG(ulBase + TIMER_O_CTL) = (bStall ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} + +//***************************************************************************** +// +//! Set the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale value which must be between 0 and 255 +//! (inclusive) for 16/32-bit timers. +//! +//! This function sets the value of the input clock prescaler. The prescaler +//! is only operational when in half-width mode and is used to extend the range +//! of the half-width timer modes. +//! +//! \return None. +// +//***************************************************************************** +void +TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescaler if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPR) = ulValue; + } + + // + // Set the timer B prescaler if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPR) = ulValue; + } +} + + +//***************************************************************************** +// +//! Get the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler. The prescaler +//! is only operational when in half-width mode and is used to extend the range +//! of the half-width timer modes. +//! +//! \return The value of the timer prescaler. +// +//***************************************************************************** + +unsigned long +TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : + HWREG(ulBase + TIMER_O_TBPR)); +} + +//***************************************************************************** +// +//! Set the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale match value which must be between 0 +//! and 255 (inclusive) for 16/32-bit timers. +//! +//! This function sets the value of the input clock prescaler match value. +//! When in a half-width mode that uses the counter match and the prescaler, +//! the prescale match effectively extends the range of the match. +//! +//! \note The availability of the prescaler match varies with the +//! part and timer mode in use. Please consult the datasheet for the part you +//! are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescale match if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPMR) = ulValue; + } + + // + // Set the timer B prescale match if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPMR) = ulValue; + } +} + +//***************************************************************************** +// +//! Get the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a half-width mode that uses the counter match and prescaler, the +//! prescale match effectively extends the range of the match. +//! +//! \note The availability of the prescaler match varies with the +//! part and timer mode in use. Please consult the datasheet for the part you +//! are using to determine whether this support is available. +//! +//! \return The value of the timer prescale match. +// +//***************************************************************************** +unsigned long +TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : + HWREG(ulBase + TIMER_O_TBPMR)); +} + +//***************************************************************************** +// +//! Sets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for full-width operation. +//! \param ulValue is the load value. +//! +//! This function sets the timer load value; if the timer is running then the +//! value is immediately loaded into the timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A load value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAILR) = ulValue; + } + + // + // Set the timer B load value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBILR) = ulValue; + } +} + +//***************************************************************************** +// +//! Gets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for full-width operation. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +unsigned long +TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate load value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : + HWREG(ulBase + TIMER_O_TBILR)); +} + +//***************************************************************************** +// +//! Gets the current timer value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +unsigned long +TimerValueGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate timer value. Ti SDK code reads TnR which is ticker count. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAV) : + HWREG(ulBase + TIMER_O_TBV)); +} + +//***************************************************************************** +// +//! Sets the current timer value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! \param ulValue is the new value of the timer to be set. +//! +//! This function sets the current value of the specified timer. +//! +//! \return None. +// +//***************************************************************************** +void +TimerValueSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Set the appropriate timer value. + // + if(ulTimer == TIMER_A) + { + HWREG(ulBase + TIMER_O_TAV) = ulValue; + } + else + { + HWREG(ulBase + TIMER_O_TBV) = ulValue; + } +} + + +//***************************************************************************** +// +//! Sets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the match value. +//! +//! This function sets the match value for a timer. This is used in capture +//! count mode to determine when to interrupt the processor and in PWM mode to +//! determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +void +TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A match value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; + } + + // + // Set the timer B match value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; + } +} + +//***************************************************************************** +// +//! Gets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//******************************************************************************** +unsigned long +TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : + HWREG(ulBase + TIMER_O_TBMATCHR)); +} + + +//***************************************************************************** +// +//! Registers an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! This function sets the handler to be called when a timer interrupt occurs. +//! In addition, this function enables the global interrupt in the interrupt +//! controller; specific timer interrupts must be enabled via TimerIntEnable(). +//! It is the interrupt handler's responsibility to clear the interrupt source +//! via TimerIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A : + ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A : + ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A))); + + // + // Register an interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase); + } + + // + // Register an interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase + 1, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase + 1); + } +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function clears the handler to be called when a timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + + ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A : + ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A : + ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A))); + + + + // + // Unregister the interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Disable the interrupt. + // + IntDisable(ulBase); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase); + } + + // + // Unregister the interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Disable the interrupt. + // + IntDisable(ulBase + 1); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase + 1); + } +} + +//***************************************************************************** +// +//! Enables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter must be the logical OR of any combination of +//! the following: +//! +//! - \b TIMER_CAPB_EVENT - Capture B event interrupt +//! - \b TIMER_CAPB_MATCH - Capture B match interrupt +//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt +//! - \b TIMER_CAPA_EVENT - Capture A event interrupt +//! - \b TIMER_CAPA_MATCH - Capture A match interrupt +//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the timer module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This function returns the interrupt status for the timer module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in TimerIntEnable(). +// +//***************************************************************************** +unsigned long +TimerIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : + HWREG(ulBase + TIMER_O_RIS)); +} + +//***************************************************************************** +// +//! Clears timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Enables the events that can trigger a DMA request. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulDMAEvent is a bit mask of the events that can trigger DMA. +//! +//! This function enables the timer events that can trigger the start of a DMA +//! sequence. The DMA trigger events are specified in the \e ui32DMAEvent +//! parameter by passing in the logical OR of the following values: +//! +//! - \b TIMER_DMA_MODEMATCH_B - The mode match DMA trigger for timer B is +//! enabled. +//! - \b TIMER_DMA_CAPEVENT_B - The capture event DMA trigger for timer B is +//! enabled. +//! - \b TIMER_DMA_CAPMATCH_B - The capture match DMA trigger for timer B is +//! enabled. +//! - \b TIMER_DMA_TIMEOUT_B - The timeout DMA trigger for timer B is enabled. +//! - \b TIMER_DMA_MODEMATCH_A - The mode match DMA trigger for timer A is +//! enabled. +//! - \b TIMER_DMA_CAPEVENT_A - The capture event DMA trigger for timer A is +//! enabled. +//! - \b TIMER_DMA_CAPMATCH_A - The capture match DMA trigger for timer A is +//! enabled. +//! - \b TIMER_DMA_TIMEOUT_A - The timeout DMA trigger for timer A is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Set the DMA triggers. + // + HWREG(ulBase + TIMER_O_DMAEV) = ulDMAEvent; +} + +//***************************************************************************** +// +//! Returns the events that can trigger a DMA request. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function returns the timer events that can trigger the start of a DMA +//! sequence. The DMA trigger events are the logical OR of the following +//! values: +//! +//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match DMA trigger for timer +//! B. +//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event DMA trigger for +//! timer B. +//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match DMA trigger for +//! timer B. +//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout DMA trigger for timer B. +//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match DMA trigger for timer +//! A. +//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event DMA trigger for +//! timer A. +//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match DMA trigger for +//! timer A. +//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout DMA trigger for timer A. +//! +//! \return The timer events that trigger the uDMA. +// +//***************************************************************************** +unsigned long +TimerDMAEventGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ulBase)); + + // + // Return the current DMA triggers. + // + return(HWREG(ulBase + TIMER_O_DMAEV)); +} +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.h new file mode 100644 index 00000000000..cd4275a164a --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/ti_timer.h @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// timer.h +// +// Prototypes for the timer module +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** + +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count + // timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count + // timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers + +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** + +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + + +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ulTimers parameter. +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B + +//***************************************************************************** +// +// Values that can be passed to TimerDMAEventSet() or returned from +// TimerDMAEventGet(). +// +//***************************************************************************** +#define TIMER_DMA_MODEMATCH_B 0x00000800 +#define TIMER_DMA_CAPEVENT_B 0x00000400 +#define TIMER_DMA_CAPMATCH_B 0x00000200 +#define TIMER_DMA_TIMEOUT_B 0x00000100 +#define TIMER_DMA_MODEMATCH_A 0x00000010 +#define TIMER_DMA_CAPEVENT_A 0x00000004 +#define TIMER_DMA_CAPMATCH_A 0x00000002 +#define TIMER_DMA_TIMEOUT_A 0x00000001 + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); + +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); + +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent); +extern unsigned long TimerDMAEventGet(unsigned long ulBase); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.c new file mode 100755 index 00000000000..5d386cdc9e7 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.c @@ -0,0 +1,1501 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// uart.c +// +// Driver for the UART. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup UART_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_uart.h" +#include "debug.h" +#include "interrupt.h" +#include "uart.h" + + +//***************************************************************************** +// +// A mapping of UART base address to interupt number. +// +//***************************************************************************** +static const unsigned long g_ppulUARTIntMap[][2] = +{ + { UARTA0_BASE, INT_UARTA0 }, + { UARTA1_BASE, INT_UARTA1 }, +}; + +//***************************************************************************** +// +//! \internal +//! Checks a UART base address. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function determines if a UART port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static tBoolean +UARTBaseValid(unsigned long ulBase) +{ + return((ulBase == UARTA0_BASE) || (ulBase == UARTA1_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Gets the UART interrupt number. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Given a UART base address, returns the corresponding interrupt number. +//! +//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid. +// +//***************************************************************************** +static long +UARTIntNumberGet(unsigned long ulBase) +{ + unsigned long ulIdx; + + // + // Loop through the table that maps UART base addresses to interrupt + // numbers. + // + for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) / + sizeof(g_ppulUARTIntMap[0])); ulIdx++) + { + // + // See if this base address matches. + // + if(g_ppulUARTIntMap[ulIdx][0] == ulBase) + { + // + // Return the corresponding interrupt number. + // + return(g_ppulUARTIntMap[ulIdx][1]); + } + } + + // + // The base address could not be found, so return an error. + // + return(-1); +} + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulParity specifies the type of parity to use. +//! +//! This function sets the type of parity to use for transmitting and expect +//! when receiving. The \e ulParity parameter must be one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two allow +//! direct control of the parity bit; it is always either one or zero based on +//! the mode. +//! +//! \return None. +// +//***************************************************************************** +void +UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulParity == UART_CONFIG_PAR_NONE) || + (ulParity == UART_CONFIG_PAR_EVEN) || + (ulParity == UART_CONFIG_PAR_ODD) || + (ulParity == UART_CONFIG_PAR_ONE) || + (ulParity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & + ~(UART_LCRH_SPS | UART_LCRH_EPS | + UART_LCRH_PEN)) | ulParity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +unsigned long +UARTParityModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the current parity setting. + // + return(HWREG(ulBase + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of +//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, +//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of +//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, +//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulTxLevel == UART_FIFO_TX1_8) || + (ulTxLevel == UART_FIFO_TX2_8) || + (ulTxLevel == UART_FIFO_TX4_8) || + (ulTxLevel == UART_FIFO_TX6_8) || + (ulTxLevel == UART_FIFO_TX7_8)); + ASSERT((ulRxLevel == UART_FIFO_RX1_8) || + (ulRxLevel == UART_FIFO_RX2_8) || + (ulRxLevel == UART_FIFO_RX4_8) || + (ulRxLevel == UART_FIFO_RX6_8) || + (ulRxLevel == UART_FIFO_RX7_8)); + + // + // Set the FIFO interrupt levels. + // + HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param ulBase is the base address of the UART port. +//! \param pulTxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, +//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param pulRxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, +//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Read the FIFO level register. + // + ulTemp = HWREG(ulBase + UART_O_IFLS); + + // + // Extract the transmit and receive FIFO levels. + // + *pulTxLevel = ulTemp & UART_IFLS_TX_M; + *pulRxLevel = ulTemp & UART_IFLS_RX_M; +} + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulUARTClk is the rate of the clock supplied to the UART module. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the data +//! format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). +//! +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig) +{ + unsigned long ulDiv; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT(ulBaud != 0); + + // + // Stop the UART. + // + UARTDisable(ulBase); + + // + // Is the required baud rate greater than the maximum rate supported + // without the use of high speed mode? + // + if((ulBaud * 16) > ulUARTClk) + { + // + // Enable high speed mode. + // + HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; + + // + // Half the supplied baud rate to compensate for enabling high speed + // mode. This allows the following code to be common to both cases. + // + ulBaud /= 2; + } + else + { + // + // Disable high speed mode. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); + } + + // + // Compute the fractional baud rate divider. + // + ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2; + + // + // Set the baud rate. + // + HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; + HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ulBase + UART_O_LCRH) = ulConfig; + + // + // Clear the flags register. + // + HWREG(ulBase + UART_O_FR) = 0; + + // + // Start the UART. + // + UARTEnable(ulBase); +} + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulUARTClk is the rate of the clock supplied to the UART module. +//! \param pulBaud is a pointer to storage for the baud rate. +//! \param pulConfig is a pointer to storage for the data format. +//! +//! The baud rate and data format for the UART is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e pulConfig is enumerated the same as the \e ulConfig parameter of +//! UARTConfigSetExpClk(). +//! +//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). +//! +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, unsigned long *pulConfig) +{ + unsigned long ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Compute the baud rate. + // + ulInt = HWREG(ulBase + UART_O_IBRD); + ulFrac = HWREG(ulBase + UART_O_FBRD); + *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac); + + // + // See if high speed mode enabled. + // + if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE) + { + // + // High speed mode is enabled so the actual baud rate is actually + // double what was just calculated. + // + *pulBaud *= 2; + } + + // + // Get the parity, data length, and number of stop bits. + // + *pulConfig = (HWREG(ulBase + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit +//! and receive FIFOs. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; + + // + // Enable RX, TX, and the UART. + // + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait for end of TX. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // + // Disable the UART. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFODisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! Sets the states of the RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulControl is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! This function sets the states of the RTS modem handshake outputs +//! from the UART. +//! +//! The \e ulControl parameter is the logical OR of any of the following: +//! +//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal +//! +//! \note The availability of hardware modem handshake signals varies with the +//! part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTModemControlSet(unsigned long ulBase, unsigned long ulControl) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + + ASSERT(ulBase == UARTA1_BASE); + ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0); + + // + // Set the appropriate modem control output bits. + // + ulTemp = HWREG(ulBase + UART_O_CTL); + ulTemp |= (ulControl & (UART_OUTPUT_RTS)); + HWREG(ulBase + UART_O_CTL) = ulTemp; +} + +//***************************************************************************** +// +//! Clears the states of the RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulControl is a bit-mapped flag indicating which modem control bits +//! should be set. +//! +//! This function clears the states of the RTS modem handshake outputs +//! from the UART. +//! +//! The \e ulControl parameter is the logical OR of any of the following: +//! +//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal +//! +//! \note The availability of hardware modem handshake signals varies with the +//! part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT(ulBase == UARTA1_BASE); + ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0); + + // + // Set the appropriate modem control output bits. + // + ulTemp = HWREG(ulBase + UART_O_CTL); + ulTemp &= ~(ulControl & (UART_OUTPUT_RTS)); + HWREG(ulBase + UART_O_CTL) = ulTemp; +} + +//***************************************************************************** +// +//! Gets the states of the RTS modem control signals. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current states of each of the UART modem +//! control signal, RTS. +//! +//! \note The availability of hardware modem handshake signals varies with the +//! part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return Returns the states of the handshake output signal. +// +//***************************************************************************** +unsigned long +UARTModemControlGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == UARTA1_BASE); + + return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS)); +} + +//***************************************************************************** +// +//! Gets the states of the CTS modem status signal. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current states of the UART modem status signal, +//! CTS. +//! +//! \note The availability of hardware modem handshake signals varies with the +//! part and UART in use. Please consult the datasheet for the part +//! you are using to determine whether this support is available. +//! +//! \return Returns the states of the handshake output signal +// +//***************************************************************************** +unsigned long +UARTModemStatusGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + + ASSERT(ulBase == UARTA1_BASE); + + return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_CTS)); +} + +//***************************************************************************** +// +//! Sets the UART hardware flow control mode to be used. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulMode indicates the flow control modes to be used. This parameter +//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and +//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) +//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. +//! +//! This function sets the required hardware flow control modes. If \e ulMode +//! contains flag \b UART_FLOWCONTROL_TX, data is only transmitted if the +//! incoming CTS signal is asserted. If \e ulMode contains flag +//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is +//! asserted only when there is space available in the receive FIFO. If no +//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be +//! passed. +//! +//! \note The availability of hardware flow control varies with the +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) +{ + // + // Check the arguments. + // + + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); + + // + // Set the flow control mode as requested. + // + HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & + ~(UART_FLOWCONTROL_TX | + UART_FLOWCONTROL_RX)) | ulMode); +} + +//***************************************************************************** +// +//! Returns the UART hardware flow control mode currently in use. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current hardware flow control mode. +//! +//! \note The availability of hardware flow control varies with the +//! part and UART in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns the current flow control mode in use. This is a +//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit +//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) +//! flow control is in use. If hardware flow control is disabled, +//! \b UART_FLOWCONTROL_NONE is returned. +// +//***************************************************************************** +unsigned long +UARTFlowControlGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + + ASSERT(UARTBaseValid(ulBase)); + + return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | + UART_FLOWCONTROL_RX)); +} + +//***************************************************************************** +// +//! Sets the operating mode for the UART transmit interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulMode is the operating mode for the transmit interrupt. It may be +//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle +//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO +//! level. +//! +//! This function allows the mode of the UART transmit interrupt to be set. By +//! default, the transmit interrupt is asserted when the FIFO level falls past +//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this +//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the +//! transmit interrupt is asserted once the transmitter is completely idle - +//! the transmit FIFO is empty and all bits, including any stop bits, have +//! cleared the transmitter. +//! +//! \note The availability of end-of-transmission mode varies with the +//! part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + ASSERT((ulMode == UART_TXINT_MODE_EOT) || + (ulMode == UART_TXINT_MODE_FIFO)); + + // + // Set or clear the EOT bit of the UART control register as appropriate. + // + HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & + ~(UART_TXINT_MODE_EOT | + UART_TXINT_MODE_FIFO)) | ulMode); +} + +//***************************************************************************** +// +//! Returns the current operating mode for the UART transmit interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current operating mode for the UART transmit +//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit +//! interrupt is currently set to be asserted once the transmitter is +//! completely idle - the transmit FIFO is empty and all bits, including any +//! stop bits, have cleared the transmitter. The return value is +//! \b UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon +//! the level of the transmit FIFO. +//! +//! \note The availability of end-of-transmission mode varies with the +//! part in use. Please consult the datasheet for the part you are +//! using to determine whether this support is available. +//! +//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. +// +//***************************************************************************** +unsigned long +UARTTxIntModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the current transmit interrupt mode. + // + return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT | + UART_TXINT_MODE_FIFO)); +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO or \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +tBoolean +UARTCharsAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the availability of characters. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO +//! or \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +tBoolean +UARTSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the availability of space. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. +//! +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 is returned if there are no characters present in the +//! receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +long +UARTCharGetNonBlocking(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ulBase + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. +// +//***************************************************************************** +long +UARTCharGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait until a char is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the char. + // + return(HWREG(ulBase + UART_O_DR)); +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! This function writes the character \e ucData to the transmit FIFO for the +//! specified port. This function does not block, so if there is no space +//! available, then a \b false is returned, and the application must retry the +//! function later. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO or \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +tBoolean +UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ulBase + UART_O_DR) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! This function sends the character \e ucData to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +void +UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Wait until space is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ulBase + UART_O_DR) = ucData; +} + +//***************************************************************************** +// +//! Causes a BREAK to be sent. +//! +//! \param ulBase is the base address of the UART port. +//! \param bBreakState controls the output level. +//! +//! Calling this function with \e bBreakState set to \b true asserts a break +//! condition on the UART. Calling this function with \e bBreakState set to +//! \b false removes the break condition. For proper transmission of a break +//! command, the break must be asserted for at least two complete frames. +//! +//! \return None. +// +//***************************************************************************** +void +UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Set the break condition as requested. + // + HWREG(ulBase + UART_O_LCRH) = + (bBreakState ? + (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) : + (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK))); +} + +//***************************************************************************** +// +//! Determines whether the UART transmitter is busy or not. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \b false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \return Returns \b true if the UART is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +tBoolean +UARTBusy(unsigned long ulBase) +{ + // + // Check the argument. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine if the UART is busy. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine the interrupt number based on the UART port. + // + + ulInt = UARTIntNumberGet(ulBase); + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ulInt); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a UART interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = UARTIntNumberGet(ulBase); + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter is the logical OR of any of the following: +//! +//! - \b UART_INT_OE - Overrun Error interrupt +//! - \b UART_INT_BE - Break Error interrupt +//! - \b UART_INT_PE - Parity Error interrupt +//! - \b UART_INT_FE - Framing Error interrupt +//! - \b UART_INT_RT - Receive Timeout interrupt +//! - \b UART_INT_TX - Transmit interrupt +//! - \b UART_INT_RX - Receive interrupt +//! - \b UART_INT_CTS - CTS interrupt +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) |= ulIntFlags; +} + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the UART port. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +unsigned long +UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + UART_O_MIS)); + } + else + { + return(HWREG(ulBase + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags +//! parameter to UARTIntEnable(). +//! +//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + UART_O_ICR) = ulIntFlags; +} + +//***************************************************************************** +// +//! Enable UART DMA operation. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulDMAFlags is a bit mask of the DMA features to enable. +//! +//! The specified UART DMA features are enabled. The UART can be +//! configured to use DMA for transmit or receive, and to disable +//! receive if an error occurs. The \e ulDMAFlags parameter is the +//! logical OR of any of the following values: +//! +//! - UART_DMA_RX - enable DMA for receive +//! - UART_DMA_TX - enable DMA for transmit +//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Set the requested bits in the UART DMA control register. + // + HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags; +} + +//***************************************************************************** +// +//! Disable UART DMA operation. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulDMAFlags is a bit mask of the DMA features to disable. +//! +//! This function is used to disable UART DMA features that were enabled +//! by UARTDMAEnable(). The specified UART DMA features are disabled. The +//! \e ulDMAFlags parameter is the logical OR of any of the following values: +//! +//! - UART_DMA_RX - disable DMA for receive +//! - UART_DMA_TX - disable DMA for transmit +//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error +//! +//! \return None. +// +//***************************************************************************** +void +UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Clear the requested bits in the UART DMA control register. + // + HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags; +} + +//***************************************************************************** +// +//! Gets current receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \return Returns a logical OR combination of the receiver error flags, +//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK +//! and \b UART_RXERROR_OVERRUN. +// +//***************************************************************************** +unsigned long +UARTRxErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Return the current value of the receive status register. + // + return(HWREG(ulBase + UART_O_RSR) & 0x0000000F); +} + +//***************************************************************************** +// +//! Clears all reported receiver errors. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function is used to clear all receiver error conditions reported via +//! UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRxErrorClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ulBase)); + + // + // Any write to the Error Clear Register will clear all bits which are + // currently set. + // + HWREG(ulBase + UART_O_ECR) = 0; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.h new file mode 100755 index 00000000000..ba03c2fb515 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/uart.h @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// uart.h +// +// Defines and Macros for the UART. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_DMATX 0x20000 // DMA Tx Done interrupt Mask +#define UART_INT_DMARX 0x10000 // DMA Rx Done interrupt Mask +#define UART_INT_EOT 0x800 // End of transfer interrupt Mask +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask +#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask + + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter +// and returned by UARTConfigGetExpClk in the pulConfig parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ulParity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and +// returned by UARTFIFOLevelGet in the pulTxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and +// returned by UARTFIFOLevelGet in the pulRxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTModemControlSet()and UARTModemControlClear() +// or returned from UARTModemControlGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 + +//***************************************************************************** +// +// Values that can be returned from UARTModemStatusGet(). +// +//***************************************************************************** +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +#define UART_FLOWCONTROL_TX 0x00008000 +#define UART_FLOWCONTROL_RX 0x00004000 +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO 0x00000000 +#define UART_TXINT_MODE_EOT 0x00000010 + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern void UARTFIFOEnable(unsigned long ulBase); +extern void UARTFIFODisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern tBoolean UARTBusy(unsigned long ulBase); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); +extern unsigned long UARTRxErrorGet(unsigned long ulBase); +extern void UARTRxErrorClear(unsigned long ulBase); +extern void UARTModemControlSet(unsigned long ulBase, + unsigned long ulControl); +extern void UARTModemControlClear(unsigned long ulBase, + unsigned long ulControl); +extern unsigned long UARTModemControlGet(unsigned long ulBase); +extern unsigned long UARTModemStatusGet(unsigned long ulBase); +extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTFlowControlGet(unsigned long ulBase); +extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTTxIntModeGet(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.c new file mode 100755 index 00000000000..001cbb8793a --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.c @@ -0,0 +1,1257 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// udma.c +// +// Driver for the micro-DMA controller. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uDMA_Micro_Direct_Memory_Access_api +//! @{ +// +//***************************************************************************** + + +#include "inc/hw_types.h" +#include "inc/hw_udma.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "debug.h" +#include "interrupt.h" +#include "udma.h" + + +//***************************************************************************** +// +//! Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAEnable(void) +{ + // + // Set the master enable bit in the config register. + // + HWREG(UDMA_BASE + UDMA_O_CFG) = UDMA_CFG_MASTEN; +} + +//***************************************************************************** +// +//! Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller cannot operate until re-enabled with uDMAEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMADisable(void) +{ + // + // Clear the master enable bit in the config register. + // + HWREG(UDMA_BASE + UDMA_O_CFG) = 0; +} + +//***************************************************************************** +// +//! Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +unsigned long +uDMAErrorStatusGet(void) +{ + // + // Return the uDMA error status. + // + return(HWREG(UDMA_BASE + UDMA_O_ERRCLR)); +} + +//***************************************************************************** +// +//! Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. This function should +//! be called from within the uDMA error interrupt handler to clear the +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAErrorStatusClear(void) +{ + // + // Clear the uDMA error interrupt. + // + HWREG(UDMA_BASE + UDMA_O_ERRCLR) = 1; +} + +//***************************************************************************** +// +//! Enables a uDMA channel for operation. +//! +//! \param ulChannelNum is the channel number to enable. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel is automatically disabled by +//! the uDMA controller. Therefore, this function should be called prior to +//! starting up any new transfer. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelEnable(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the enable set register. + // + HWREG(UDMA_BASE + UDMA_O_ENASET) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Disables a uDMA channel for operation. +//! +//! \param ulChannelNum is the channel number to disable. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! cannot respond to uDMA transfer requests until re-enabled via +//! uDMAChannelEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelDisable(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the enable clear register. + // + HWREG(UDMA_BASE + UDMA_O_ENACLR) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Checks if a uDMA channel is enabled for operation. +//! +//! \param ulChannelNum is the channel number to check. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! function can be used to check the status of a transfer, as the channel is +//! automatically disabled at the end of a transfer. +//! +//! \return Returns \b true if the channel is enabled, \b false if disabled. +// +//***************************************************************************** +tBoolean +uDMAChannelIsEnabled(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // AND the specified channel bit with the enable register and return the + // result. + // + return((HWREG(UDMA_BASE + UDMA_O_ENASET) & + (1 << (ulChannelNum & 0x1f))) ? true : false); +} + +//***************************************************************************** +// +//! Sets the base address for the channel control table. +//! +//! \param pControlTable is a pointer to the 1024-byte-aligned base address +//! of the uDMA channel control table. +//! +//! This function configures the base address of the channel control table. +//! This table resides in system memory and holds control information for each +//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base +//! address must be configured before any of the channel functions can be used. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels and the transfer modes that are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAControlBaseSet(void *pControlTable) +{ + // + // Check the arguments. + // + ASSERT(((unsigned long)pControlTable & ~0x3FF) == + (unsigned long)pControlTable); + ASSERT((unsigned long)pControlTable >= 0x20000000); + + // + // Program the base address into the register. + // + HWREG(UDMA_BASE + UDMA_O_CTLBASE) = (unsigned long)pControlTable; +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +void * +uDMAControlBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_BASE + UDMA_O_CTLBASE)); +} + +//***************************************************************************** +// +//! Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +void * +uDMAControlAlternateBaseGet(void) +{ + // + // Read the current value of the control base register and return it to + // the caller. + // + return((void *)HWREG(UDMA_BASE + UDMA_O_ALTBASE)); +} + +//***************************************************************************** +// +//! Requests a uDMA channel to start a transfer. +//! +//! \param ulChannelNum is the channel number on which to request a uDMA +//! transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This function could be used for performing a memory-to-memory +//! transfer or if for some reason, a transfer needs to be initiated by software +//! instead of the peripheral associated with that channel. +//! +//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then +//! the completion is signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion is signaled on the +//! peripheral's interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelRequest(unsigned long ulChannelNum) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // Set the bit for this channel in the software uDMA request register. + // + HWREG(UDMA_BASE + UDMA_O_SWREQ) = 1 << (ulChannelNum & 0x1f); +} + +//***************************************************************************** +// +//! Enables attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! \param ulAttr is a combination of attributes for the channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! The \e ulAttr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Set the useburst bit for this channel if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) = 1 << ulChannelNum; + } + + // + // Set the alternate control select bit for this channel, + // if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_BASE + UDMA_O_ALTSET) = 1 << ulChannelNum; + } + + // + // Set the high priority bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_BASE + UDMA_O_PRIOSET) = 1 << ulChannelNum; + } + + // + // Set the request mask bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_BASE + UDMA_O_REQMASKSET) = 1 << ulChannelNum; + } +} + +//***************************************************************************** +// +//! Disables attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! \param ulAttr is a combination of attributes for the channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! The \e ulAttr parameter is the logical OR of any of the following: +//! +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr) +{ + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Clear the useburst bit for this channel if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_USEBURST) + { + HWREG(UDMA_BASE + UDMA_O_USEBURSTCLR) = 1 << ulChannelNum; + } + + // + // Clear the alternate control select bit for this channel, if set in + // ulConfig. + // + if(ulAttr & UDMA_ATTR_ALTSELECT) + { + HWREG(UDMA_BASE + UDMA_O_ALTCLR) = 1 << ulChannelNum; + } + + // + // Clear the high priority bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(UDMA_BASE + UDMA_O_PRIOCLR) = 1 << ulChannelNum; + } + + // + // Clear the request mask bit for this channel, if set in ulConfig. + // + if(ulAttr & UDMA_ATTR_REQMASK) + { + HWREG(UDMA_BASE + UDMA_O_REQMASKCLR) = 1 << ulChannelNum; + } +} + +//***************************************************************************** +// +//! Gets the enabled attributes of a uDMA channel. +//! +//! \param ulChannelNum is the channel to configure. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \return Returns the logical OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst +//! mode. +//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel. +//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +unsigned long +uDMAChannelAttributeGet(unsigned long ulChannelNum) +{ + unsigned long ulAttr = 0; + + // + // Check the arguments. + // + ASSERT((ulChannelNum & 0xffff) < 32); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Check to see if useburst bit is set for this channel. + // + if(HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_USEBURST; + } + + // + // Check to see if the alternate control bit is set for this channel. + // + if(HWREG(UDMA_BASE + UDMA_O_ALTSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_ALTSELECT; + } + + // + // Check to see if the high priority bit is set for this channel. + // + if(HWREG(UDMA_BASE + UDMA_O_PRIOSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // + // Check to see if the request mask bit is set for this channel. + // + if(HWREG(UDMA_BASE + UDMA_O_REQMASKSET) & (1 << ulChannelNum)) + { + ulAttr |= UDMA_ATTR_REQMASK; + } + + // + // Return the configuration flags. + // + return(ulAttr); +} + +//***************************************************************************** +// +//! Sets the control parameters for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulControl is logical OR of several control values to set the control +//! parameters for the channel. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! parameters are typically not changed often. +//! +//! The \e ulChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. +//! +//! The \e ulControl parameter is the logical OR of five values: the data size, +//! the source address increment, the destination address increment, the +//! arbitration size, and the use burst flag. The choices available for each +//! of these values is described below. +//! +//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or +//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. +//! +//! Choose the source address increment from one of \b UDMA_SRC_INC_8, +//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or +//! to select non-incrementing. +//! +//! Choose the destination address increment from one of \b UDMA_DST_INC_8, +//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select +//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or +//! to select non-incrementing. +//! +//! The arbitration size determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size +//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, +//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 +//! items, in powers of 2. +//! +//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only +//! respond to burst requests at the tail end of a scatter-gather transfer. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelControlSet(unsigned long ulChannelStructIndex, + unsigned long ulControl) +{ + tDMAControlTable *pCtl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pCtl = (tDMAControlTable *)HWREG(UDMA_BASE+UDMA_O_CTLBASE); + + // + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + // + pCtl[ulChannelStructIndex].ulControl = + ((pCtl[ulChannelStructIndex].ulControl & + ~(UDMA_CHCTL_DSTINC_M | + UDMA_CHCTL_DSTSIZE_M | + UDMA_CHCTL_SRCINC_M | + UDMA_CHCTL_SRCSIZE_M | + UDMA_CHCTL_ARBSIZE_M | + UDMA_CHCTL_NXTUSEBURST)) | + ulControl); +} + +//***************************************************************************** +// +//! Sets the transfer parameters for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! \param ulMode is the type of uDMA transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ulTransferSize is the number of data items to transfer. +//! +//! This function is used to configure the parameters for a uDMA transfer. +//! These parameters are typically changed often. The function +//! uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \e ulChannelStructIndex parameter should be the logical OR of the +//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to +//! choose whether the primary or alternate data structure is used. +//! +//! The \e ulMode parameter should be one of the following values: +//! +//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. +//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once +//! started even if the request is removed. +//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the +//! primary and alternate control structures for the channel. This mode +//! allows use of ping-pong buffering for uDMA transfers. +//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather +//! transfer. +//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather +//! transfer. +//! +//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. For example, if the item size is set to 4-bytes, +//! these addresses must be 4-byte aligned. The compiler can take care of this +//! alignment if the pointers are pointing to storage of the appropriate +//! data type. +//! +//! The \e ulTransferSize parameter is the number of data items, not the number +//! of bytes. The value of this parameter should not exceed 1024. +//! +//! The two scatter-gather modes, memory and peripheral, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function looks for the \b UDMA_PRI_SELECT and +//! \b UDMA_ALT_SELECT flag along with the channel number and sets the +//! scatter-gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using uDMAChannelEnable() after calling +//! this function. The transfer does not begin until the channel has been +//! configured and enabled. Note that the channel is automatically disabled +//! after the transfer is completed, meaning that uDMAChannelEnable() must be +//! called again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results are unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelTransferSet(unsigned long ulChannelStructIndex, + unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr, + unsigned long ulTransferSize) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + unsigned long ulInc; + unsigned long ulBufferBytes; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); + ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((unsigned long)pvSrcAddr >= 0x20000000); + ASSERT((unsigned long)pvDstAddr >= 0x20000000); + ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024)); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); + + // + // Get the current control word value and mask off the mode and size + // fields. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // Adjust the mode if the alt control structure is selected. + // + if(ulChannelStructIndex & UDMA_ALT_SELECT) + { + if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ulMode |= UDMA_MODE_ALT_SELECT; + } + } + + // + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + // + ulControl |= ulMode | ((ulTransferSize - 1) << 4); + + // + // Get the address increment value for the source, from the control word. + // + ulInc = (ulControl & UDMA_CHCTL_SRCINC_M); + + // + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + // + if(ulInc != UDMA_SRC_INC_NONE) + { + ulInc = ulInc >> 26; + ulBufferBytes = ulTransferSize << ulInc; + pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulBufferBytes - 1); + } + + // + // Load the source ending address into the control block. + // + pControlTable[ulChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // + // Get the address increment value for the destination, from the control + // word. + // + ulInc = ulControl & UDMA_CHCTL_DSTINC_M; + + // + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + // + if(ulInc != UDMA_DST_INC_NONE) + { + // + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer must point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + // + if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ulChannelStructIndex | + UDMA_ALT_SELECT].ulSpare; + } + // + // Not a scatter-gather transfer, calculate end pointer normally. + // + else + { + ulInc = ulInc >> 30; + ulBufferBytes = ulTransferSize << ulInc; + pvDstAddr = (void *)((unsigned long)pvDstAddr + ulBufferBytes - 1); + } + } + + // + // Load the destination ending address into the control block. + // + pControlTable[ulChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // + // Write the new control word value. + // + pControlTable[ulChannelStructIndex].ulControl = ulControl; +} + +//***************************************************************************** +// +//! Configures a uDMA channel for scatter-gather mode. +//! +//! \param ulChannelNum is the uDMA channel number. +//! \param ulTaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ulIsPeriphSG is a flag to indicate it is a peripheral scatter-gather +//! transfer (else it is memory scatter-gather transfer) +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list and must pass a pointer to +//! the start of the task list as the \e pvTaskList parameter. The +//! \e ulTaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. The flag \e bIsPeriphSG should be used to indicate +//! if scatter-gather should be configured for peripheral or memory +//! operation. +//! +//! \sa uDMATaskStructEntry +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount, + void *pvTaskList, unsigned long ulIsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // + // Check the parameters + // + ASSERT((ulChannelNum & 0xffff) < 32); + ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ulTaskCount <= 1024); + ASSERT(ulTaskCount != 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelNum parameter, extract just the channel number + // from this parameter. + // + ulChannelNum &= 0x1f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); + + // + // Get a handy pointer to the task list + // + pTaskTable = (tDMAControlTable *)pvTaskList; + + // + // Compute the ending address for the source pointer. This address is the + // last element of the last task in the task table + // + pControlTable[ulChannelNum].pvSrcEndAddr = + &pTaskTable[ulTaskCount - 1].ulSpare; + + // + // Compute the ending address for the destination pointer. This address + // is the end of the alternate structure for this channel. + // + pControlTable[ulChannelNum].pvDstEndAddr = + &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare; + + // + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + // + pControlTable[ulChannelNum].ulControl = + (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | + UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | + UDMA_CHCTL_ARBSIZE_4 | + (((ulTaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | + (ulIsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : + UDMA_CHCTL_XFERMODE_MEM_SG)); +} + +//***************************************************************************** +// +//! Gets the current transfer size for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items is returned. If the transfer is +//! complete, then 0 is returned. +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +unsigned long +uDMAChannelSizeGet(unsigned long ulChannelStructIndex) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); + + // + // Get the current control word value and mask off all but the size field + // and the mode field. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); + + // + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer + // + if(ulControl == 0) + { + return(0); + } + + // + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + // + else + { + // + // Shift the size field and add one, then return to user. + // + return((ulControl >> 4) + 1); + } +} + +//***************************************************************************** +// +//! Gets the transfer mode for a uDMA channel control structure. +//! +//! \param ulChannelStructIndex is the logical OR of the uDMA channel number +//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. +//! +//! This function is used to get the transfer mode for the uDMA channel and +//! to query the status of a transfer on a channel. When the transfer is +//! complete the mode is \b UDMA_MODE_STOP. +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which is one of the following values: \b UDMA_MODE_STOP, +//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. +// +//***************************************************************************** +unsigned long +uDMAChannelModeGet(unsigned long ulChannelStructIndex) +{ + tDMAControlTable *pControlTable; + unsigned long ulControl; + + // + // Check the arguments. + // + ASSERT((ulChannelStructIndex & 0xffff) < 64); + ASSERT(HWREG(UDMA_O_CTLBASE) != 0); + + // + // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was + // passed as the ulChannelStructIndex parameter, extract just the channel + // index from this parameter. + // + ulChannelStructIndex &= 0x3f; + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); + + // + // Get the current control word value and mask off all but the mode field. + // + ulControl = (pControlTable[ulChannelStructIndex].ulControl & + UDMA_CHCTL_XFERMODE_M); + + // + // Check if scatter/gather mode, and if so, mask off the alt bit. + // + if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ulControl &= ~UDMA_MODE_ALT_SELECT; + } + + // + // Return the mode to the caller. + // + return(ulControl); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the uDMA controller. +//! +//! \param ulIntChannel identifies which uDMA interrupt is to be registered. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! This function registers and enables the handler to be called when the uDMA +//! controller generates an interrupt. The \e ulIntChannel parameter should be +//! one of the following: +//! +//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts +//! from the uDMA software channel (UDMA_CHANNEL_SW) +//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error +//! interrupts +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note The interrupt handler for the uDMA is for transfer completion when +//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The +//! interrupts for each peripheral channel are handled through the individual +//! peripheral interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(pfnHandler); + ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR)); + + // + // Register the interrupt handler. + // + IntRegister(ulIntChannel, pfnHandler); + + // + // Enable the memory management fault. + // + IntEnable(ulIntChannel); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the uDMA controller. +//! +//! \param ulIntChannel identifies which uDMA interrupt to unregister. +//! +//! This function disables and unregisters the handler to be called for the +//! specified uDMA interrupt. The \e ulIntChannel parameter should be one of +//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function +//! uDMAIntRegister(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntUnregister(unsigned long ulIntChannel) +{ + // + // Disable the interrupt. + // + IntDisable(ulIntChannel); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulIntChannel); +} + +//***************************************************************************** +// +//! Gets the uDMA controller channel interrupt status. +//! +//! This function is used to get the interrupt status of the uDMA controller. +//! The returned value is a 32-bit bit mask that indicates which channels are +//! requesting an interrupt. This function can be used from within an +//! interrupt handler to determine or confirm which uDMA channel has requested +//! an interrupt. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return Returns a 32-bit mask which indicates requesting uDMA channels. +//! There is a bit for each channel and a 1 indicates that the channel +//! is requesting an interrupt. Multiple bits can be set. +// +//***************************************************************************** +unsigned long +uDMAIntStatus(void) +{ + + + // + // Return the value of the uDMA interrupt status register + // + return(HWREG(UDMA_BASE + UDMA_O_CHIS)); +} + +//***************************************************************************** +// +//! Clears uDMA interrupt status. +//! +//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! This function clears bits in the uDMA interrupt status register according +//! to which bits are set in \e ulChanMask. There is one bit for each channel. +//! If a a bit is set in \e ulChanMask, then that corresponding channel's +//! interrupt status is cleared (if it was set). +//! +//! \note This function is only available on devices that have the DMA Channel +//! Interrupt Status Register (DMACHIS). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAIntClear(unsigned long ulChanMask) +{ + + // + // Clear the requested bits in the uDMA interrupt status register + // + HWREG(UDMA_BASE + UDMA_O_CHIS) = ulChanMask; +} + +//***************************************************************************** +// +//! Assigns a peripheral mapping for a uDMA channel. +//! +//! \param ulMapping is a macro specifying the peripheral assignment for +//! a channel. +//! +//! This function assigns a peripheral mapping to a uDMA channel. It is +//! used to select which peripheral is used for a uDMA channel. The parameter +//! \e ulMapping should be one of the macros named \b UDMA_CHn_tttt from the +//! header file \e udma.h. For example, to assign uDMA channel 8 to the +//! UARTA0 RX channel, the parameter should be the macro \b UDMA_CH8_UARTA0_RX. +//! +//! Please consult the data sheet for a table showing all the +//! possible peripheral assignments for the uDMA channels for a particular +//! device. +//! +//! \note This function is only available on devices that have the DMA Channel +//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for +//! your part. +//! +//! \return None. +// +//***************************************************************************** +void +uDMAChannelAssign(unsigned long ulMapping) +{ + unsigned long ulMapReg; + unsigned long ulMapShift; + unsigned long ulChannelNum; + + // + // Check the parameters + // + ASSERT((ulMapping & 0xffffff00) < 0x00050000); + + + // + // Extract the channel number and map encoding value from the parameter. + // + ulChannelNum = ulMapping & 0x1f; + ulMapping = ulMapping >> 16; + + // + // Find the uDMA channel mapping register and shift value to use for this + // channel + // + ulMapReg = UDMA_BASE + UDMA_O_CHMAP0 + ((ulChannelNum / 8) * 4); + ulMapShift = (ulChannelNum % 8) * 4; + + // + // Set the channel map encoding for this channel + // + HWREG(ulMapReg) = (HWREG(ulMapReg) & ~(0xf << ulMapShift)) | + ulMapping << ulMapShift; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.h new file mode 100755 index 00000000000..ca95de0d525 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/udma.h @@ -0,0 +1,664 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// udma.h +// +// Prototypes and macros for the uDMA controller. +// +//***************************************************************************** + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup uDMA_Micro_Direct_Memory_Access_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// A structure that defines an entry in the channel control table. These +// fields are used by the uDMA controller and normally it is not necessary for +// software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + // + // The ending source address of the data transfer. + // + volatile void *pvSrcEndAddr; + + // + // The ending destination address of the data transfer. + // + volatile void *pvDstEndAddr; + + // + // The channel control mode. + // + volatile unsigned long ulControl; + + // + // An unused location. + // + volatile unsigned long ulSpare; +} +tDMAControlTable; + +//***************************************************************************** +// +//! A helper macro for building scatter-gather task table entries. +//! +//! \param ulTransferCount is the count of items to transfer for this task. +//! \param ulItemSize is the bit size of the items to transfer for this task. +//! \param ulSrcIncrement is the bit size increment for source data. +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ulDstIncrement is the bit size increment for destination data. +//! \param pvDstAddr is the starting address of the destination data. +//! \param ulArbSize is the arbitration size to use for the transfer task. +//! \param ulMode is the transfer mode for this task. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! The \e ulTransferCount parameter is the number of items that will be +//! transferred by this task. It must be in the range 1-1024. +//! +//! The \e ulItemSize parameter is the bit size of the transfer data. It must +//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. +//! +//! The \e ulSrcIncrement parameter is the increment size for the source data. +//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, +//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. +//! +//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source +//! data. +//! +//! The \e ulDstIncrement parameter is the increment size for the destination +//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, +//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. +//! +//! The \e pvDstAddr parameter is a void pointer to the beginning of the +//! location where the data will be transferred. +//! +//! The \e ulArbSize parameter is the arbitration size for the transfer, and +//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on +//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in +//! powers of 2, from 1 to 1024. +//! +//! The \e ulMode parameter is the mode to use for this transfer task. It +//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, +//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note +//! that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +//! \verbatim +//! tDMAControlTable MyTaskList[] = +//! { +//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, +//! UDMA_SRC_INC_8, MySourceBuf, +//! UDMA_DST_INC_8, MyDestBuf, +//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), +//! uDMATaskStructEntry(Task2Count, ... ), +//! } +//! \endverbatim +//! +//! \return Nothing; this is not a function. +// +//***************************************************************************** +#define uDMATaskStructEntry(ulTransferCount, \ + ulItemSize, \ + ulSrcIncrement, \ + pvSrcAddr, \ + ulDstIncrement, \ + pvDstAddr, \ + ulArbSize, \ + ulMode) \ + { \ + (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ + ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \ + ((ulSrcIncrement) >> 26)) - 1]))), \ + (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \ + ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \ + ((ulDstIncrement) >> 30)) - 1]))), \ + (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \ + (((ulTransferCount) - 1) << 4) | \ + ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \ + } + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAModeSet() and returned +// uDMAModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// uDMA interrupt sources, to be passed to uDMAIntRegister() and +// uDMAIntUnregister(). +// +//***************************************************************************** +#define UDMA_INT_SW INT_UDMA +#define UDMA_INT_ERR INT_UDMAERR + +//***************************************************************************** + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xc0000000 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// Values that can be passed to uDMAChannelAssign() to select peripheral +// mapping for each channel. The channels named RESERVED may be assigned +// to a peripheral in future parts. +// +//***************************************************************************** +// +// Channel 0 +// +#define UDMA_CH0_TIMERA0_A 0x00000000 +#define UDMA_CH0_SHAMD5_CIN 0x00010000 +#define UDMA_CH0_SW 0x00030000 + +// +// Channel 1 +// +#define UDMA_CH1_TIMERA0_B 0x00000001 +#define UDMA_CH1_SHAMD5_DIN 0x00010001 +#define UDMA_CH1_SW 0x00030001 + +// +// Channel 2 +// +#define UDMA_CH2_TIMERA1_A 0x00000002 +#define UDMA_CH2_SHAMD5_COUT 0x00010002 +#define UDMA_CH2_SW 0x00030002 + +// +// Channel 3 +// +#define UDMA_CH3_TIMERA1_B 0x00000003 +#define UDMA_CH3_DES_CIN 0x00010003 +#define UDMA_CH3_SW 0x00030003 + +// +// Channel 4 +// +#define UDMA_CH4_TIMERA2_A 0x00000004 +#define UDMA_CH4_DES_DIN 0x00010004 +#define UDMA_CH4_I2S_RX 0x00020004 +#define UDMA_CH4_SW 0x00030004 + +// +// Channel 5 +// +#define UDMA_CH5_TIMERA2_B 0x00000005 +#define UDMA_CH5_DES_DOUT 0x00010005 +#define UDMA_CH5_I2S_TX 0x00020005 +#define UDMA_CH5_SW 0x00030005 + +// +// Channel 6 +// +#define UDMA_CH6_TIMERA3_A 0x00000006 +#define UDMA_CH6_GSPI_RX 0x00010006 +#define UDMA_CH6_GPIOA2 0x00020006 +#define UDMA_CH6_SW 0x00030006 + +// +// Channel 7 +// +#define UDMA_CH7_TIMERA3_B 0x00000007 +#define UDMA_CH7_GSPI_TX 0x00010007 +#define UDMA_CH7_GPIOA3 0x00020007 +#define UDMA_CH7_SW 0x00030007 + + +// +// Channel 8 +// +#define UDMA_CH8_UARTA0_RX 0x00000008 +#define UDMA_CH8_TIMERA0_A 0x00010008 +#define UDMA_CH8_TIMERA2_A 0x00020008 +#define UDMA_CH8_SW 0x00030008 + + +// +// Channel 9 +// +#define UDMA_CH9_UARTA0_TX 0x00000009 +#define UDMA_CH9_TIMERA0_B 0x00010009 +#define UDMA_CH9_TIMERA2_B 0x00020009 +#define UDMA_CH9_SW 0x00030009 + + +// +// Channel 10 +// +#define UDMA_CH10_UARTA1_RX 0x0000000A +#define UDMA_CH10_TIMERA1_A 0x0001000A +#define UDMA_CH10_TIMERA3_A 0x0002000A +#define UDMA_CH10_SW 0x0003000A + +// +// Channel 11 +// +#define UDMA_CH11_UARTA1_TX 0x0000000B +#define UDMA_CH11_TIMERA1_B 0x0001000B +#define UDMA_CH11_TIMERA3_B 0x0002000B +#define UDMA_CH11_SW 0x0003000B + + +// +// Channel 12 +// +#define UDMA_CH12_LSPI_RX 0x0000000C +#define UDMA_CH12_SW 0x0003000C + + +// +// Channel 13 +// +#define UDMA_CH13_LSPI_TX 0x0000000D +#define UDMA_CH13_SW 0x0003000D + + +// +// Channel 14 +// +#define UDMA_CH14_ADC_CH0 0x0000000E +#define UDMA_CH14_SDHOST_RX 0x0002000E +#define UDMA_CH14_SW 0x0003000E + + +// +// Channel 15 +// +#define UDMA_CH15_ADC_CH1 0x0000000F +#define UDMA_CH15_SDHOST_TX 0x0002000F +#define UDMA_CH15_SW 0x0003000F + + +// +// Channel 16 +// +#define UDMA_CH16_ADC_CH2 0x00000010 +#define UDMA_CH16_TIMERA2_A 0x00010010 +#define UDMA_CH16_SW 0x00030010 + + +// +// Channel 17 +// +#define UDMA_CH17_ADC_CH3 0x00000011 +#define UDMA_CH17_TIMERA2_B 0x00010011 +#define UDMA_CH17_SW 0x00030011 + +// +// Channel 18 +// +#define UDMA_CH18_GPIOA0 0x00000012 +#define UDMA_CH18_AES_CIN 0x00010012 +#define UDMA_CH18_I2S_RX 0x00020012 +#define UDMA_CH18_SW 0x00030012 + + +// +// Channel 19 +// +#define UDMA_CH19_GPOIA1 0x00000013 +#define UDMA_CH19_AES_COUT 0x00010013 +#define UDMA_CH19_I2S_TX 0x00020013 +#define UDMA_CH19_SW 0x00030013 + + +// +// Channel 20 +// +#define UDMA_CH20_GPIOA2 0x00000014 +#define UDMA_CH20_AES_DIN 0x00010014 +#define UDMA_CH20_SW 0x00030014 + + +// +// Channel 21 +// +#define UDMA_CH21_GPIOA3 0x00000015 +#define UDMA_CH21_AES_DOUT 0x00010015 +#define UDMA_CH21_SW 0x00030015 + + +// +// Channel 22 +// +#define UDMA_CH22_CAMERA 0x00000016 +#define UDMA_CH22_GPIOA4 0x00010016 +#define UDMA_CH22_SW 0x00030016 + + +// +// Channel 23 +// +#define UDMA_CH23_SDHOST_RX 0x00000017 +#define UDMA_CH23_TIMERA3_A 0x00010017 +#define UDMA_CH23_TIMERA2_A 0x00020017 +#define UDMA_CH23_SW 0x00030017 + + +// +// Channel 24 +// +#define UDMA_CH24_SDHOST_TX 0x00000018 +#define UDMA_CH24_TIMERA3_B 0x00010018 +#define UDMA_CH24_TIMERA2_B 0x00020018 +#define UDMA_CH24_SW 0x00030018 + + +// +// Channel 25 +// +#define UDMA_CH25_SSPI_RX 0x00000019 +#define UDMA_CH25_I2CA0_RX 0x00010019 +#define UDMA_CH25_SW 0x00030019 + + +// +// Channel 26 +// +#define UDMA_CH26_SSPI_TX 0x0000001A +#define UDMA_CH26_I2CA0_TX 0x0001001A +#define UDMA_CH26_SW 0x0003001A + + +// +// Channel 27 +// +#define UDMA_CH27_GPIOA0 0x0001001B +#define UDMA_CH27_SW 0x0003001B + + +// +// Channel 28 +// +#define UDMA_CH28_GPIOA1 0x0001001C +#define UDMA_CH28_SW 0x0003001C + + +// +// Channel 29 +// +#define UDMA_CH29_GPIOA4 0x0000001D +#define UDMA_CH29_SW 0x0003001D + + +// +// Channel 30 +// +#define UDMA_CH30_GSPI_RX 0x0000001E +#define UDMA_CH30_SDHOST_RX 0x0001001E +#define UDMA_CH30_I2CA0_RX 0x0002001E +#define UDMA_CH30_SW 0x0003001E + + +// +// Channel 31 +// +#define UDMA_CH31_GSPI_TX 0x0000001F +#define UDMA_CH31_SDHOST_TX 0x0001001F +#define UDMA_CH31_I2CA0_RX 0x0002001F +#define UDMA_CH31_SW 0x0003001F + +//***************************************************************************** +// +// The following are defines for the Micro Direct Memory Access (uDMA) offsets. +// +//***************************************************************************** +#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + + + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void uDMAEnable(void); +extern void uDMADisable(void); +extern unsigned long uDMAErrorStatusGet(void); +extern void uDMAErrorStatusClear(void); +extern void uDMAChannelEnable(unsigned long ulChannelNum); +extern void uDMAChannelDisable(unsigned long ulChannelNum); +extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum); +extern void uDMAControlBaseSet(void *pControlTable); +extern void *uDMAControlBaseGet(void); +extern void *uDMAControlAlternateBaseGet(void); +extern void uDMAChannelRequest(unsigned long ulChannelNum); +extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum, + unsigned long ulAttr); +extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum, + unsigned long ulAttr); +extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum); +extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex, + unsigned long ulControl); +extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, + unsigned long ulMode, void *pvSrcAddr, + void *pvDstAddr, + unsigned long ulTransferSize); +extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, + unsigned ulTaskCount, void *pvTaskList, + unsigned long ulIsPeriphSG); +extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex); +extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex); +extern void uDMAIntRegister(unsigned long ulIntChannel, + void (*pfnHandler)(void)); +extern void uDMAIntUnregister(unsigned long ulIntChannel); +extern unsigned long uDMAIntStatus(void); +extern void uDMAIntClear(unsigned long ulChanMask); +extern void uDMAChannelAssign(unsigned long ulMapping); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UDMA_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.c new file mode 100755 index 00000000000..18c93725348 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// utils.c +// +// Utility APIs +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup Utils_api +//! @{ +// +//***************************************************************************** +#include "utils.h" + + +//***************************************************************************** +// +//! Provides a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! This function provides a means of generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! The loop takes 3 cycles/loop. +//! +//! \return None. +// +//***************************************************************************** + +#if defined(ewarm) || defined(DOXYGEN) +void +UtilsDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne.n UtilsDelay\n"); +} +#endif + +#if defined(gcc) +void __attribute__((naked)) +UtilsDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne UtilsDelay\n" + " bx lr"); +} +#endif + +#if defined (arm_cc) +// Use C code for now. TODO, change to assembly if precision is needed. +void UtilsDelay(unsigned long ulCount) +{ + volatile unsigned long delay = (ulCount >> 2); + while (delay --); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.h new file mode 100755 index 00000000000..df74f04b0f2 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/utils.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// utils.h +// +// Prototypes and macros for utility APIs +// +//***************************************************************************** + +#ifndef __UTILS_H__ +#define __UTILS_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// TODO, move this to tools +#ifdef TOOLCHAIN_GCC_ARM +#define gcc +#elif defined TOOLCHAIN_ARM +#define arm_cc +#elif defined TOOLCHAIN_IAR +#define ewarm +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UtilsDelay(unsigned long ulCount); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif //__UTILS_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/version.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/version.h new file mode 100755 index 00000000000..db0b6878ea2 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/version.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// version.h +// +// Contains Driverlib version details +// +//***************************************************************************** + +#ifndef __DRIVERLIB_VERSION_H__ +#define __DRIVERLIB_VERSION_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#define DRIVERLIB_MAJOR_VERSION_NUM 01 +#define DRIVERLIB_MINOR_VERSION_NUM 51 +#define DRIVERLIB_PATCH_VERSION_NUM 03 +#define DRIVERLIB_BUILD_VERSION_NUM 00 +#define DRIVERLIB_RELEASE_DAY 15 +#define DRIVERLIB_RELEASE_MONTH 01 +#define DRIVERLIB_RELEASE_YEAR 2018 + +///////////////////////////////////////////// +// !!! Please update the changes.log file !!! +///////////////////////////////////////////// + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_VERSION_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.c new file mode 100755 index 00000000000..c0358b1691f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.c @@ -0,0 +1,492 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// wdt.c +// +// Driver for the Watchdog Timer Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup WDT_Watchdog_Timer_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_wdt.h" +#include "debug.h" +#include "interrupt.h" +#include "wdt.h" + +//***************************************************************************** +// +//! Determines if the watchdog timer is enabled. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will check to see if the watchdog timer is enabled. +//! +//! \return Returns \b true if the watchdog timer is enabled, and \b false +//! if it is not. +// +//***************************************************************************** +tBoolean +WatchdogRunning(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // See if the watchdog timer module is enabled, and return. + // + return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); +} + +//***************************************************************************** +// +//! Enables the watchdog timer. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will enable the watchdog timer counter and interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Enable the watchdog timer module. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} + +//***************************************************************************** +// +//! Enables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Locks out write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogLock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; +} + +//***************************************************************************** +// +//! Disables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogUnlock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Unlock watchdog register writes. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; +} + +//***************************************************************************** +// +//! Gets the state of the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Returns the lock state of the watchdog timer registers. +//! +//! \return Returns \b true if the watchdog timer registers are locked, and +//! \b false if they are not locked. +// +//***************************************************************************** +tBoolean +WatchdogLockState(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Get the lock state. + // + return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); +} + +//***************************************************************************** +// +//! Sets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulLoadVal is the load value for the watchdog timer. +//! +//! This function sets the value to load into the watchdog timer when the count +//! reaches zero for the first time; if the watchdog timer is running when this +//! function is called, then the value will be immediately loaded into the +//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Set the load register. + // + HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; +} + +//***************************************************************************** +// +//! Gets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \sa WatchdogReloadSet() +//! +//! \return None. +// +//***************************************************************************** +unsigned long +WatchdogReloadGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Get the load register. + // + return(HWREG(ulBase + WDT_O_LOAD)); +} + +//***************************************************************************** +// +//! Gets the current watchdog timer value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +unsigned long +WatchdogValueGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Get the current watchdog timer register value. + // + return(HWREG(ulBase + WDT_O_VALUE)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; the watchdog +//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via +//! WatchdogIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note This function will only register the standard watchdog interrupt +//! handler. To register the NMI watchdog handler, use IntRegister() +//! to register the handler for the \b FAULT_NMI interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Register the interrupt handler and + // Enable the watchdog timer interrupt. + // + IntRegister(INT_WDT, pfnHandler); + IntEnable(INT_WDT); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function will clear the handler to be called when a watchdog timer +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \note This function will only unregister the standard watchdog interrupt +//! handler. To unregister the NMI watchdog handler, use IntUnregister() +//! to unregister the handler for the \b FAULT_NMI interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Disable the interrupt + IntDisable(INT_WDT); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_WDT); +} + +//***************************************************************************** +// +//! Gets the current watchdog timer interrupt status. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the watchdog timer module. Either +//! the raw interrupt status or the status of interrupt that is allowed to +//! reflect to the processor can be returned. +//! +//! \return Returns the current interrupt status, where a 1 indicates that the +//! watchdog interrupt is active, and a 0 indicates that it is not active. +// +//***************************************************************************** +unsigned long +WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + WDT_O_MIS)); + } + else + { + return(HWREG(ulBase + WDT_O_RIS)); + } +} + +//***************************************************************************** +// +//! Clears the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \note Because there is a write buffer in the Cortex-M3 processor, it may +//! take several clock cycles before the interrupt source is actually cleared. +//! Therefore, it is recommended that the interrupt source be cleared early in +//! the interrupt handler (as opposed to the very last action) to avoid +//! returning from the interrupt handler before the interrupt source is +//! actually cleared. Failure to do so may result in the interrupt handler +//! being immediately reentered (because the interrupt controller still sees +//! the interrupt source asserted). +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Clear the interrupt source. + // + HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; +} + +//***************************************************************************** +// +//! Enables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring (typically almost immediately from a human time perspective) and +//! resetting the system (if reset is enabled). The watchdog will instead +//! expired after the appropriate number of processor cycles have been executed +//! while debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogStallEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Enable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; +} + +//***************************************************************************** +// +//! Disables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None. +// +//***************************************************************************** +void +WatchdogStallDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == WDT_BASE)); + + // + // Disable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.h new file mode 100755 index 00000000000..7a14d3fc0a0 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** +// +// wdt.h - Prototypes for the Watchdog Timer API +// +// + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallEnable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/asmdefs.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/asmdefs.h new file mode 100755 index 00000000000..de722a7ff27 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/asmdefs.h @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for code_red. +// +//***************************************************************************** +#ifdef codered + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // codered + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(gcc) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // rvmdk + +//***************************************************************************** +// +// The defines required for Sourcery G++. +// +//***************************************************************************** +#if defined(sourcerygxx) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // sourcerygxx + +#endif // __ASMDEF_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_adc.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_adc.h new file mode 100755 index 00000000000..d518bc3222b --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_adc.h @@ -0,0 +1,886 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ADC_CTRL 0x00000000 // ADC control register. +#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting +#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting +#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting +#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting +#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting +#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting +#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting +#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting +#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable + // register +#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable + // register +#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable + // register +#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable + // register +#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable + // register +#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable + // register +#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable + // register +#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable + // register +#define ADC_O_adc_ch0_irq_status \ + 0x00000044 // Channel 0 interrupt status + // register + +#define ADC_O_adc_ch1_irq_status \ + 0x00000048 // Channel 1 interrupt status + // register + +#define ADC_O_adc_ch2_irq_status \ + 0x0000004C + +#define ADC_O_adc_ch3_irq_status \ + 0x00000050 // Channel 3 interrupt status + // register + +#define ADC_O_adc_ch4_irq_status \ + 0x00000054 // Channel 4 interrupt status + // register + +#define ADC_O_adc_ch5_irq_status \ + 0x00000058 + +#define ADC_O_adc_ch6_irq_status \ + 0x0000005C // Channel 6 interrupt status + // register + +#define ADC_O_adc_ch7_irq_status \ + 0x00000060 // Channel 7 interrupt status + // register + +#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register +#define ADC_O_adc_timer_configuration \ + 0x00000068 // ADC timer configuration register + +#define ADC_O_adc_timer_current_count \ + 0x00000070 // ADC timer current count register + +#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register +#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register +#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register +#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register +#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register +#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register +#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register +#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register +#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register +#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status + // register +#define ADC_O_adc_ch2_fifo_lvl 0x0000009C +#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status + // register +#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status + // register +#define ADC_O_adc_ch5_fifo_lvl 0x000000A8 +#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status + // register +#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status + // register + +#define ADC_O_ADC_CH_ENABLE 0x000000B8 + +//****************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ADC_CTRL register. +// +//****************************************************************************** +#define ADC_ADC_CTRL_adc_cap_scale \ + 0x00000020 // ADC CAP SCALE. + +#define ADC_ADC_CTRL_adc_buf_bypass \ + 0x00000010 // ADC ANA CIO buffer bypass. + // Signal is modelled in ANA TOP. + // When '1': ADC buffer is bypassed. + +#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1: + // ADC buffer is enabled. +#define ADC_ADC_CTRL_adc_core_en \ + 0x00000004 // ANA ADC core en. This signal act + // as glbal enable to ADC CIO. When + // 1: ADC core is enabled. + +#define ADC_ADC_CTRL_adc_soft_reset \ + 0x00000002 // ADC soft reset. When '1' : reset + // ADC internal logic. + +#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC + // module is enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_gain register. +// +//****************************************************************************** +#define ADC_adc_ch0_gain_adc_channel0_gain_M \ + 0x00000003 // gain setting for ADC channel 0. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch0_gain_adc_channel0_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_gain register. +// +//****************************************************************************** +#define ADC_adc_ch1_gain_adc_channel1_gain_M \ + 0x00000003 // gain setting for ADC channel 1. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch1_gain_adc_channel1_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_gain register. +// +//****************************************************************************** +#define ADC_adc_ch2_gain_adc_channel2_gain_M \ + 0x00000003 // gain setting for ADC channel 2. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch2_gain_adc_channel2_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_gain register. +// +//****************************************************************************** +#define ADC_adc_ch3_gain_adc_channel3_gain_M \ + 0x00000003 // gain setting for ADC channel 3. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch3_gain_adc_channel3_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_gain register. +// +//****************************************************************************** +#define ADC_adc_ch4_gain_adc_channel4_gain_M \ + 0x00000003 // gain setting for ADC channel 4 + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch4_gain_adc_channel4_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_gain register. +// +//****************************************************************************** +#define ADC_adc_ch5_gain_adc_channel5_gain_M \ + 0x00000003 // gain setting for ADC channel 5. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch5_gain_adc_channel5_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_gain register. +// +//****************************************************************************** +#define ADC_adc_ch6_gain_adc_channel6_gain_M \ + 0x00000003 // gain setting for ADC channel 6 + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch6_gain_adc_channel6_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_gain register. +// +//****************************************************************************** +#define ADC_adc_ch7_gain_adc_channel7_gain_M \ + 0x00000003 // gain setting for ADC channel 7. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch7_gain_adc_channel7_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_dma_mode_en register. +// +//****************************************************************************** +#define ADC_adc_dma_mode_en_DMA_MODEenable_M \ + 0x000000FF // this register enable DMA mode. + // when '1' respective ADC channel + // is enabled for DMA. When '0' only + // interrupt mode is enabled. Bit 0: + // channel 0 DMA mode enable. Bit 1: + // channel 1 DMA mode enable. Bit 2: + // channel 2 DMA mode enable. Bit 3: + // channel 3 DMA mode enable. bit 4: + // channel 4 DMA mode enable. bit 5: + // channel 5 DMA mode enable. bit 6: + // channel 6 DMA mode enable. bit 7: + // channel 7 DMA mode enable. + +#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_timer_configuration register. +// +//****************************************************************************** +#define ADC_adc_timer_configuration_timeren \ + 0x02000000 // when '1' timer is enabled. + +#define ADC_adc_timer_configuration_timerreset \ + 0x01000000 // when '1' reset timer. + +#define ADC_adc_timer_configuration_timercount_M \ + 0x00FFFFFF // Timer count configuration. 17 + // bit counter is supported. Other + // MSB's are redundent. + +#define ADC_adc_timer_configuration_timercount_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_timer_current_count register. +// +//****************************************************************************** +#define ADC_adc_timer_current_count_timercurrentcount_M \ + 0x0001FFFF // Timer count configuration + +#define ADC_adc_timer_current_count_timercurrentcount_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel0FIFODATA register. +// +//****************************************************************************** +#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel1FIFODATA register. +// +//****************************************************************************** +#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel2FIFODATA register. +// +//****************************************************************************** +#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel3FIFODATA register. +// +//****************************************************************************** +#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel4FIFODATA register. +// +//****************************************************************************** +#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel5FIFODATA register. +// +//****************************************************************************** +#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel6FIFODATA register. +// +//****************************************************************************** +#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel7FIFODATA register. +// +//****************************************************************************** +#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0 + + + +#endif // __HW_ADC_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_aes.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_aes.h new file mode 100755 index 00000000000..574f7576f83 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_aes.h @@ -0,0 +1,800 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_AES_H__ +#define __HW_AES_H__ + +//***************************************************************************** +// +// The following are defines for the AES_P register offsets. +// +//***************************************************************************** +#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third + // key +#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit + // key) / CBC-MAC third key (MSW) +#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC + // third key (LSW) +#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit + // key) / CBC-MAC third key +#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key / + // Hash Key input +#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit + // key) + CCM/CBC-MAC second key + // (MSW) / Hash Key input (MSW) +#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key + // (LSW) / Hash Key input (LSW) +#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key / + // Hash Key input +#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key) +#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key) +#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key) +#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key) +#define AES_O_KEY1_2 0x00000030 // Key +#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key) +#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key) +#define AES_O_KEY1_1 0x0000003C // Key +#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input + // (LSW) +#define AES_O_IV_IN_1 0x00000044 // Initialization vector input +#define AES_O_IV_IN_2 0x00000048 // Initialization vector input +#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input + // (MSW) +#define AES_O_CTRL 0x00000050 // register determines the mode of + // operation of the AES Engine +#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers + // (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. +#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers + // (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. +#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The + // authentication length register + // store the authentication data + // length in bytes for combined + // modes only (GCM or CCM) Supported + // AAD-lengths for CCM are from 0 to + // (2^16 - 2^8) bytes. For GCM any + // value up to (2^32 - 1) bytes can + // be used. Once processing with + // this context is started@@ this + // length decrements to zero. A + // write to this register triggers + // the engine to start using this + // context for GCM and CCM. For XTS + // this register is optionally used + // to load ‘j’. Loading of ‘j’ is + // only required if ‘j’ != 0. ‘j’ is + // a 28-bit value and must be + // written to bits [31-4] of this + // register. ‘j’ represents the + // sequential number of the 128-bit + // block inside the data unit. For + // the first block in a unit@@ this + // value is zero. It is not required + // to provide a ‘j’ for each new + // data block within a unit. Note + // that it is possible to start with + // a ‘j’ unequal to zero; refer to + // Table 4 for more details. For a + // Host read operation@@ these + // registers return all-zeroes. +#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write + // plaintext/ciphertext (MSW) +#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write + // plaintext/ciphertext +#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write + // plaintext/ciphertext +#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write + // plaintext/ciphertext (LSW) +#define AES_O_TAG_OUT_0 0x00000070 +#define AES_O_TAG_OUT_1 0x00000074 +#define AES_O_TAG_OUT_2 0x00000078 +#define AES_O_TAG_OUT_3 0x0000007C +#define AES_O_REVISION 0x00000080 // Register AES_REVISION +#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This + // register configures the DMA + // signals and controls the IDLE and + // reset logic +#define AES_O_SYSSTATUS 0x00000088 +#define AES_O_IRQSTATUS 0x0000008C // This register indicates the + // interrupt status. If one of the + // interrupt bits is set the + // interrupt output will be asserted +#define AES_O_IRQENABLE 0x00000090 // This register contains an enable + // bit for each unique interrupt + // generated by the module. It + // matches the layout of + // AES_IRQSTATUS register. An + // interrupt is enabled when the bit + // in this register is set to ‘1’. + // An interrupt that is enabled is + // propagated to the SINTREQUEST_x + // output. All interrupts need to be + // enabled explicitly by writing + // this register. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_6 register. +// +//****************************************************************************** +#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_6_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_7 register. +// +//****************************************************************************** +#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_7_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_4 register. +// +//****************************************************************************** +#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_4_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_5 register. +// +//****************************************************************************** +#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_5_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_2 register. +// +//****************************************************************************** +#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_3 register. +// +//****************************************************************************** +#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_3_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_0 register. +// +//****************************************************************************** +#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_1 register. +// +//****************************************************************************** +#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_6 register. +// +//****************************************************************************** +#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_6_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_7 register. +// +//****************************************************************************** +#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_7_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_4 register. +// +//****************************************************************************** +#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_4_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_5 register. +// +//****************************************************************************** +#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_5_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_2 register. +// +//****************************************************************************** +#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_3 register. +// +//****************************************************************************** +#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_3_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_0 register. +// +//****************************************************************************** +#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_1 register. +// +//****************************************************************************** +#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_0 register. +// +//****************************************************************************** +#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_0_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_1 register. +// +//****************************************************************************** +#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_2 register. +// +//****************************************************************************** +#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_3 register. +// +//****************************************************************************** +#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_CTRL register. +// +//****************************************************************************** +#define AES_CTRL_CONTEXT_READY \ + 0x80000000 // If ‘1’@@ this read-only status + // bit indicates that the context + // data registers can be overwritten + // and the host is permitted to + // write the next context. + +#define AES_CTRL_SVCTXTRDY \ + 0x40000000 // If ‘1’@@ this read-only status + // bit indicates that an AES + // authentication TAG and/or IV + // block(s) is/are available for the + // host to retrieve. This bit is + // only asserted if the + // ‘save_context’ bit is set to ‘1’. + // The bit is mutual exclusive with + // the ‘context_ready’ bit. + +#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate + // that an authentication TAG or + // result IV needs to be stored as a + // result context. If this bit is + // set@@ context output DMA and/or + // interrupt will be asserted if the + // operation is finished and related + // signals are enabled. +#define AES_CTRL_CCM_M 0x01C00000 // Defines “M� that indicated the + // length of the authentication + // field for CCM operations; the + // authentication field length + // equals two times (the value of + // CCM-M plus one). Note that the + // AES Engine always returns a + // 128-bit authentication field@@ of + // which the M least significant + // bytes are valid. All values are + // supported. +#define AES_CTRL_CCM_S 22 +#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L� that indicated the + // width of the length field for CCM + // operations; the length field in + // bytes equals the value of CMM-L + // plus one. Supported values for L + // are (programmed value): 2 (1)@@ 4 + // (3) and 8 (7). +#define AES_CTRL_CCM_L_S 19 +#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a + // combined mode@@ using AES for + // both authentication and + // encryption. No additional mode + // selection is required. 0 Other + // mode selected 1 ccm mode selected +#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is + // a combined mode@@ using the + // Galois field multiplier GF(2^128) + // for authentication and AES-CTR + // mode for encryption@@ the bits + // specify the GCM mode. 0x0 No + // operation 0x1 GHASH with H loaded + // and Y0-encrypted forced to zero + // 0x2 GHASH with H loaded and + // Y0-encrypted calculated + // internally 0x3 Autonomous GHASH + // (both H and Y0-encrypted + // calculated internally) +#define AES_CTRL_GCM_S 16 +#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the + // Direction bit must be set to ‘1’ + // for this mode. 0 Other mode + // selected 1 cbcmac mode selected +#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the + // AES key size must be set to + // 128-bit for this mode. 0 Other + // mode selected 1 f9 selected +#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the + // AES key size must be set to + // 128-bit for this mode. 0 Other + // mode selected 1 f8 selected +#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected; + // the bits specify the XTS mode.01 + // = Previous/intermediate tweak + // value and ‘j’ loaded (value is + // loaded via IV@@ j is loaded via + // the AAD length register) 0x0 No + // operation 0x1 + // Previous/intermediate tweak value + // and ‘j’ loaded (value is loaded + // via IV@@ j is loaded via the AAD + // length register) 0x2 Key2@@ i and + // j loaded (i is loaded via IV@@ j + // is loaded via the AAD length + // register) 0x3 Key2 and i loaded@@ + // j=0 (i is loaded via IV) +#define AES_CTRL_XTS_S 11 +#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback + // mode (CFB128) is selected. 0 + // other mode selected 1 cfb + // selected +#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM) + // is selected@@ this is a counter + // mode with a 16-bit wide counter. + // 0 Other mode selected. 1 ICM mode + // selected +#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for + // AES-CTR mode 0x0 Counter is 32 + // bits 0x1 Counter is 64 bits 0x2 + // Counter is 128 bits 0x3 Counter + // is 192 bits +#define AES_CTRL_CTR_WIDTH_S 7 +#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for + // GCM and CCM@@ when + // encryption/decryption is + // required. 0 Other mode selected 1 + // Counter mode +#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc + // mode +#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is + // 128 bits. 0x2 Key is 192 bits 0x3 + // Key is 256 +#define AES_CTRL_KEY_SIZE_S 3 +#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt + // operation is performed. If set to + // ‘0’ a decrypt operation is + // performed. Read 0 decryption is + // selected Read 1 Encryption is + // selected +#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status + // bit indicates that the 16-byte + // input buffer is empty@@ and the + // host is permitted to write the + // next block of data. +#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status + // bit indicates that an AES output + // block is available for the host + // to retrieve. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_C_LENGTH_0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_C_LENGTH_1 register. +// +//****************************************************************************** +#define AES_C_LENGTH_1_LENGTH_M \ + 0x1FFFFFFF // Data length (MSW) length + // registers (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. + +#define AES_C_LENGTH_1_LENGTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_AUTH_LENGTH register. +// +//****************************************************************************** +#define AES_AUTH_LENGTH_AUTH_M \ + 0xFFFFFFFF // data + +#define AES_AUTH_LENGTH_AUTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_0 register. +// +//****************************************************************************** +#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_0_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_1 register. +// +//****************************************************************************** +#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_2 register. +// +//****************************************************************************** +#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_3 register. +// +//****************************************************************************** +#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register. +// +//****************************************************************************** +#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_0_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register. +// +//****************************************************************************** +#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_1_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register. +// +//****************************************************************************** +#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_2_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register. +// +//****************************************************************************** +#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW) +#define AES_TAG_OUT_3_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_REVISION register. +// +//****************************************************************************** +#define AES_REVISION_SCHEME_M 0xC0000000 +#define AES_REVISION_SCHEME_S 30 +#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define AES_REVISION_FUNC_S 16 +#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by + // IP design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define AES_REVISION_R_RTL_S 11 +#define AES_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X)@@ maintained + // by IP specification owner. X + // changes ONLY when: (1) There is a + // major feature addition. An + // example would be adding Master + // Mode to Utopia Level2. The Func + // field (or Class/Type in old PID + // format) will remain the same. X + // does NOT change due to: (1) Bug + // fixes (2) Change in feature + // parameters. + +#define AES_REVISION_X_MAJOR_S 8 +#define AES_REVISION_CUSTOM_M 0x000000C0 +#define AES_REVISION_CUSTOM_S 6 +#define AES_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y)@@ maintained + // by IP specification owner. Y + // changes ONLY when: (1) Features + // are scaled (up or down). + // Flexibility exists in that this + // feature scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R@@ S@@ X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless@@ the spec tracks + // the IP bugs. An RTL release (say + // for silicon PG1.1) that occurs + // due to bug fix should document + // the corresponding spec number + // (X.Y.S) in its release notes. + +#define AES_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSCONFIG register. +// +//****************************************************************************** +#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \ + 0x00000200 // If set to '1' the two context + // out requests + // (dma_req_context_out_en@@ Bit [8] + // above@@ and context_out interrupt + // enable@@ Bit [3] of AES_IRQENABLE + // register) are mapped on the + // corresponding data output request + // bit. In this case@@ the original + // ‘context out’ bit values are + // ignored. + +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ + 0x00000100 // If set to ‘1’@@ the DMA context + // output request is enabled (for + // context data out@@ e.g. TAG for + // authentication modes). 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // If set to ‘1’@@ the DMA context + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // If set to ‘1’@@ the DMA output + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // If set to ‘1’@@ the DMA input + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSSTATUS register. +// +//****************************************************************************** +#define AES_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQSTATUS register. +// +//****************************************************************************** +#define AES_IRQSTATUS_CONTEXT_OUT \ + 0x00000008 // This bit indicates + // authentication tag (and IV) + // interrupt(s) is/are active and + // triggers the interrupt output. + +#define AES_IRQSTATUS_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define AES_IRQSTATUS_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQENABLE register. +// +//****************************************************************************** +#define AES_IRQENABLE_CONTEXT_OUT \ + 0x00000008 // This bit indicates + // authentication tag (and IV) + // interrupt(s) is/are active and + // triggers the interrupt output. + +#define AES_IRQENABLE_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define AES_IRQENABLE_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + + + + +#endif // __HW_AES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_config.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_config.h new file mode 100755 index 00000000000..e5f26928ab5 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_config.h @@ -0,0 +1,745 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __HW_APPS_CONFIG_H__ +#define __HW_APPS_CONFIG_H__ + +//***************************************************************************** +// +// The following are defines for the APPS_CONFIG register offsets. +// +//***************************************************************************** +#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \ + 0x00000000 // Patch trap address Register + // array + +#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \ + 0x00000078 + +#define APPS_CONFIG_O_FAULT_STATUS_REG \ + 0x0000007C + +#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \ + 0x00000080 + +#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \ + 0x00000084 + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK \ + 0x0000008C + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \ + 0x00000090 + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \ + 0x00000094 + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \ + 0x00000098 + +#define APPS_CONFIG_O_DMA_DONE_INT_ACK \ + 0x0000009C + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \ + 0x000000A0 + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \ + 0x000000A4 + +#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \ + 0x000000A8 + +#define APPS_CONFIG_O_RESERVD_REG_0 \ + 0x000000AC + +#define APPS_CONFIG_O_GPT_TRIG_SEL \ + 0x000000B0 + +#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \ + 0x000000B4 + +#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \ + 0x000000B8 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \ + 0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus + // fault is generated for the + // address + // PATCH_TRAP_ADDR_REG[n][31:0] from + // Idcode bus. The exception routine + // should take care to jump to the + // location where the patch + // correspond to this address is + // kept. + +#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_PATCH_TRAP_EN_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \ + 0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus + // fault is generated for the + // address PATCH_TRAP_ADD[n][31:0] + // from Idcode bus. The exception + // routine should take care to jump + // to the location where the patch + // correspond to this address is + // kept. + +#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_FAULT_STATUS_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \ + 0x0000003E // This field shows because of + // which patch trap address the + // bus_fault is generated. If the + // PATCH_ERR bit is set, then it + // means the bus fault is generated + // because of + // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX] + +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1 +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \ + 0x00000001 // This bit is set when there is a + // bus fault because of patched + // address access to the Apps boot + // rom. Write 0 to clear this + // register. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \ + 0x00000001 // This bit is set when there is a + // an error in memss write access. + // And the address causing this + // error is captured in + // MEMSS_ERR_ADDR_REG. To capture + // the next error address one have + // to clear this bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \ + 0x0000F000 // 1= disable corresponding + // interrupt;0 = interrupt enabled + // bit 14: ADC channel 7 interrupt + // enable/disable bit 13: ADC + // channel 5 interrupt + // enable/disable bit 12: ADC + // channel 3 interrupt + // enable/disable bit 11: ADC + // channel 1 interrupt + // enable/disable + +#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \ + 0x00000800 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \ + 0x00000400 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \ + 0x00000200 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \ + 0x00000100 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \ + 0x00000080 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \ + 0x00000040 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \ + 0x00000020 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \ + 0x00000010 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \ + 0x00000008 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \ + 0x00000004 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \ + 0x00000002 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \ + 0x00000001 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \ + 0x0000F000 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect bit 14: ADC channel 7 DMA + // Done IRQ bit 13: ADC channel 5 + // DMA Done IRQ bit 12: ADC channel + // 3 DMA Done IRQ bit 11: ADC + // channel 1 DMA Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \ + 0x00000800 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \ + 0x00000400 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \ + 0x00000200 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \ + 0x00000100 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000080 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000040 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000020 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000010 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000008 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000004 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \ + 0x00000002 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \ + 0x00000001 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \ + 0x0000F000 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect bit 14: ADC channel 7 DMA + // Done IRQ mask bit 13: ADC channel + // 5 DMA Done IRQ mask bit 12: ADC + // channel 3 DMA Done IRQ mask bit + // 11: ADC channel 1 DMA Done IRQ + // mask + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000800 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000400 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \ + 0x00000200 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \ + 0x00000100 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000080 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000040 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000020 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000010 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000008 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000004 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000002 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000001 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 or 0 to clear all + // DMA_DONE interrupt; + +#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_ACK register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \ + 0x0000F000 // write 1 to clear corresponding + // interrupt; 0 = no effect; bit 14: + // ADC channel 7 DMA Done IRQ bit + // 13: ADC channel 5 DMA Done IRQ + // bit 12: ADC channel 3 DMA Done + // IRQ bit 11: ADC channel 1 DMA + // Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12 +#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \ + 0x00000800 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \ + 0x00000400 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \ + 0x00000200 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \ + 0x00000100 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \ + 0x00000080 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \ + 0x00000040 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \ + 0x00000020 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \ + 0x00000010 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \ + 0x00000008 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \ + 0x00000004 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \ + 0x00000002 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \ + 0x00000001 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \ + 0x0000F000 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask bit 14: ADC + // channel 7 DMA Done IRQ bit 13: + // ADC channel 5 DMA Done IRQ bit + // 12: ADC channel 3 DMA Done IRQ + // bit 11: ADC channel 1 DMA Done + // IRQ + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12 +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000800 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000400 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \ + 0x00000200 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \ + 0x00000100 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000080 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000040 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000020 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000010 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000008 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000004 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000002 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000001 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \ + 0x0000F000 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive bit 14: ADC channel 7 + // DMA Done IRQ bit 13: ADC channel + // 5 DMA Done IRQ bit 12: ADC + // channel 3 DMA Done IRQ bit 11: + // ADC channel 1 DMA Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12 +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \ + 0x00000800 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \ + 0x00000400 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \ + 0x00000200 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \ + 0x00000100 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000080 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000040 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000020 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000010 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000008 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000004 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \ + 0x00000002 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \ + 0x00000001 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \ + 0x00000001 // Write 1 to clear the LSB of + // FAULT_STATUS_REG + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_RESERVD_REG_0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_GPT_TRIG_SEL register. +// +//****************************************************************************** +#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \ + 0x000000FF // This bit is implemented for GPT + // trigger mode select. GPT IP + // support 2 modes: RTC mode and + // external trigger. When this bit + // is set to logic '1': enable + // external trigger mode for APPS + // GPT CP0 and CP1 pin. bit 0: when + // set '1' enable external GPT + // trigger 0 on GPIO0 CP0 pin else + // RTC mode is selected. bit 1: when + // set '1' enable external GPT + // trigger 1 on GPIO0 CP1 pin else + // RTC mode is selected. bit 2: when + // set '1' enable external GPT + // trigger 2 on GPIO1 CP0 pin else + // RTC mode is selected. bit 3: when + // set '1' enable external GPT + // trigger 3 on GPIO1 CP1 pin else + // RTC mode is selected. bit 4: when + // set '1' enable external GPT + // trigger 4 on GPIO2 CP0 pin else + // RTC mode is selected. bit 5: when + // set '1' enable external GPT + // trigger 5 on GPIO2 CP1 pin else + // RTC mode is selected. bit 6: when + // set '1' enable external GPT + // trigger 6 on GPIO3 CP0 pin else + // RTC mode is selected. bit 7: when + // set '1' enable external GPT + // trigger 7 on GPIO3 CP1 pin else + // RTC mode is selected. + +#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \ + 0x00000007 // Capture data from d2d_spare pads + +#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \ + 0x00000007 // Send data to d2d_spare pads - + // eventually this will get + // registered in top die + +#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0 + + + +#endif // __HW_APPS_CONFIG_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_rcm.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_rcm.h new file mode 100755 index 00000000000..997bccd8c2b --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_rcm.h @@ -0,0 +1,1504 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_APPS_RCM_H__ +#define __HW_APPS_RCM_H__ + +//***************************************************************************** +// +// The following are defines for the APPS_RCM register offsets. +// +//***************************************************************************** +#define APPS_RCM_O_CAMERA_CLK_GEN \ + 0x00000000 + +#define APPS_RCM_O_CAMERA_CLK_GATING \ + 0x00000004 + +#define APPS_RCM_O_CAMERA_SOFT_RESET \ + 0x00000008 + +#define APPS_RCM_O_MCASP_CLK_GATING \ + 0x00000014 + +#define APPS_RCM_O_MCASP_SOFT_RESET \ + 0x00000018 + +#define APPS_RCM_O_MMCHS_CLK_GEN \ + 0x00000020 + +#define APPS_RCM_O_MMCHS_CLK_GATING \ + 0x00000024 + +#define APPS_RCM_O_MMCHS_SOFT_RESET \ + 0x00000028 + +#define APPS_RCM_O_MCSPI_A1_CLK_GEN \ + 0x0000002C + +#define APPS_RCM_O_MCSPI_A1_CLK_GATING \ + 0x00000030 + +#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \ + 0x00000034 + +#define APPS_RCM_O_MCSPI_A2_CLK_GEN \ + 0x00000038 + +#define APPS_RCM_O_MCSPI_A2_CLK_GATING \ + 0x00000040 + +#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \ + 0x00000044 + +#define APPS_RCM_O_UDMA_A_CLK_GATING \ + 0x00000048 + +#define APPS_RCM_O_UDMA_A_SOFT_RESET \ + 0x0000004C + +#define APPS_RCM_O_GPIO_A_CLK_GATING \ + 0x00000050 + +#define APPS_RCM_O_GPIO_A_SOFT_RESET \ + 0x00000054 + +#define APPS_RCM_O_GPIO_B_CLK_GATING \ + 0x00000058 + +#define APPS_RCM_O_GPIO_B_SOFT_RESET \ + 0x0000005C + +#define APPS_RCM_O_GPIO_C_CLK_GATING \ + 0x00000060 + +#define APPS_RCM_O_GPIO_C_SOFT_RESET \ + 0x00000064 + +#define APPS_RCM_O_GPIO_D_CLK_GATING \ + 0x00000068 + +#define APPS_RCM_O_GPIO_D_SOFT_RESET \ + 0x0000006C + +#define APPS_RCM_O_GPIO_E_CLK_GATING \ + 0x00000070 + +#define APPS_RCM_O_GPIO_E_SOFT_RESET \ + 0x00000074 + +#define APPS_RCM_O_WDOG_A_CLK_GATING \ + 0x00000078 + +#define APPS_RCM_O_WDOG_A_SOFT_RESET \ + 0x0000007C + +#define APPS_RCM_O_UART_A0_CLK_GATING \ + 0x00000080 + +#define APPS_RCM_O_UART_A0_SOFT_RESET \ + 0x00000084 + +#define APPS_RCM_O_UART_A1_CLK_GATING \ + 0x00000088 + +#define APPS_RCM_O_UART_A1_SOFT_RESET \ + 0x0000008C + +#define APPS_RCM_O_GPT_A0_CLK_GATING \ + 0x00000090 + +#define APPS_RCM_O_GPT_A0_SOFT_RESET \ + 0x00000094 + +#define APPS_RCM_O_GPT_A1_CLK_GATING \ + 0x00000098 + +#define APPS_RCM_O_GPT_A1_SOFT_RESET \ + 0x0000009C + +#define APPS_RCM_O_GPT_A2_CLK_GATING \ + 0x000000A0 + +#define APPS_RCM_O_GPT_A2_SOFT_RESET \ + 0x000000A4 + +#define APPS_RCM_O_GPT_A3_CLK_GATING \ + 0x000000A8 + +#define APPS_RCM_O_GPT_A3_SOFT_RESET \ + 0x000000AC + +#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \ + 0x000000B0 + +#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \ + 0x000000B4 + +#define APPS_RCM_O_CRYPTO_CLK_GATING \ + 0x000000B8 + +#define APPS_RCM_O_CRYPTO_SOFT_RESET \ + 0x000000BC + +#define APPS_RCM_O_MCSPI_S0_CLK_GATING \ + 0x000000C8 + +#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \ + 0x000000CC + +#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \ + 0x000000D0 + +#define APPS_RCM_O_I2C_CLK_GATING \ + 0x000000D8 + +#define APPS_RCM_O_I2C_SOFT_RESET \ + 0x000000DC + +#define APPS_RCM_O_APPS_LPDS_REQ \ + 0x000000E4 + +#define APPS_RCM_O_APPS_TURBO_REQ \ + 0x000000EC + +#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \ + 0x00000108 + +#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \ + 0x0000010C + +#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \ + 0x00000110 + +#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \ + 0x00000114 + +#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \ + 0x00000118 + +#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \ + 0x00000120 + +#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \ + 0x00000124 + + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of Camera func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \ + 0x000000F8 + +#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3 +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of Camera func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable camera clk during + // deep-sleep mode + +#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable camera clk during + // sleep mode ; 0- Disable camera + // clk during sleep mode + +#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable camera clk during run + // mode ; 0- Disable camera clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \ + 0x00000002 // 1 - Camera clocks/resets are + // enabled ; 0 - Camera + // clocks/resets are disabled + +#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for Camera-core + // ; 0 - De-assert reset for + // Camera-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCASP clk during + // deep-sleep mode + +#define APPS_RCM_MCASP_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCASP clk during sleep + // mode ; 0- Disable MCASP clk + // during sleep mode + +#define APPS_RCM_MCASP_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCASP clk during run + // mode ; 0- Disable MCASP clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \ + 0x00000002 // 1 - MCASP Clocks/resets are + // enabled ; 0 - MCASP Clocks/resets + // are disabled + +#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for MCASP-core + // ; 0 - De-assert reset for + // MCASP-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MMCHS func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \ + 0x000000F8 + +#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3 +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MMCHS func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MMCHS clk during + // deep-sleep mode + +#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MMCHS clk during sleep + // mode ; 0- Disable MMCHS clk + // during sleep mode + +#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MMCHS clk during run + // mode ; 0- Disable MMCHS clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \ + 0x00000002 // 1 - MMCHS Clocks/resets are + // enabled ; 0 - MMCHS Clocks/resets + // are disabled + +#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for MMCHS-core + // ; 0 - De-assert reset for + // MMCHS-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud clk + // for MCSPI_A1 ; 1 - PLL divclk is + // used as baud clk for MCSPI_A1. + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11 +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A1 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3 +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A1 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCSPI_A1 clk during + // deep-sleep mode + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCSPI_A1 clk during + // sleep mode ; 0- Disable MCSPI_A1 + // clk during sleep mode + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCSPI_A1 clk during + // run mode ; 0- Disable MCSPI_A1 + // clk during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are + // enabled ; 0 - MCSPI_A1 + // Clocks/Resets are disabled + +#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for + // MCSPI_A1-core ; 0 - De-assert + // reset for MCSPI_A1-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud-clk + // for MCSPI_A2 ; 1 - PLL divclk is + // used as baud-clk for MCSPI_A2 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11 +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A2 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3 +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A2 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCSPI_A2 clk during + // deep-sleep mode + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCSPI_A2 clk during + // sleep mode ; 0- Disable MCSPI_A2 + // clk during sleep mode + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCSPI_A2 clk during + // run mode ; 0- Disable MCSPI_A2 + // clk during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are + // enabled ; 0 - MCSPI_A2 + // Clocks/Resets are disabled + +#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for + // MCSPI_A2-core ; 0 - De-assert + // reset for MCSPI_A2-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UDMA_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UDMA_A clk during + // deep-sleep mode 0 - Disable + // UDMA_A clk during deep-sleep mode + // ; + +#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UDMA_A clk during + // sleep mode 0 - Disable UDMA_A clk + // during sleep mode ; + +#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UDMA_A clk during run + // mode 0 - Disable UDMA_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UDMA_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \ + 0x00000002 // 1 - UDMA_A Clocks/Resets are + // enabled ; 0 - UDMA_A + // Clocks/Resets are disabled + +#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for DMA_A ; 0 - + // De-assert reset for DMA_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_A clk during + // deep-sleep mode 0 - Disable + // GPIO_A clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_A clk during + // sleep mode 0 - Disable GPIO_A clk + // during sleep mode ; + +#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_A clk during run + // mode 0 - Disable GPIO_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_A Clocks/Resets are + // enabled ; 0 - GPIO_A + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_A ; 0 + // - De-assert reset for GPIO_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_B_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_B clk during + // deep-sleep mode 0 - Disable + // GPIO_B clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_B clk during + // sleep mode 0 - Disable GPIO_B clk + // during sleep mode ; + +#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_B clk during run + // mode 0 - Disable GPIO_B clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_B_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_B Clocks/Resets are + // enabled ; 0 - GPIO_B + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_B ; 0 + // - De-assert reset for GPIO_B + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_C_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_C clk during + // deep-sleep mode 0 - Disable + // GPIO_C clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_C clk during + // sleep mode 0 - Disable GPIO_C clk + // during sleep mode ; + +#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_C clk during run + // mode 0 - Disable GPIO_C clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_C_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_C Clocks/Resets are + // enabled ; 0 - GPIO_C + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_C ; 0 + // - De-assert reset for GPIO_C + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_D_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_D clk during + // deep-sleep mode 0 - Disable + // GPIO_D clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_D clk during + // sleep mode 0 - Disable GPIO_D clk + // during sleep mode ; + +#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_D clk during run + // mode 0 - Disable GPIO_D clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_D_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_D Clocks/Resets are + // enabled ; 0 - GPIO_D + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_D ; 0 + // - De-assert reset for GPIO_D + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_E_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_E clk during + // deep-sleep mode 0 - Disable + // GPIO_E clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_E clk during + // sleep mode 0 - Disable GPIO_E clk + // during sleep mode ; + +#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_E clk during run + // mode 0 - Disable GPIO_E clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_E_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_E Clocks/Resets are + // enabled ; 0 - GPIO_E + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_E ; 0 + // - De-assert reset for GPIO_E + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_WDOG_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \ + 0x03000000 // "00" - Sysclk ; "01" - REF_CLK + // (38.4 MHz) ; "10/11" - Slow_clk + +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable WDOG_A clk during + // deep-sleep mode 0 - Disable + // WDOG_A clk during deep-sleep mode + // ; + +#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable WDOG_A clk during + // sleep mode 0 - Disable WDOG_A clk + // during sleep mode ; + +#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable WDOG_A clk during run + // mode 0 - Disable WDOG_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_WDOG_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \ + 0x00000002 // 1 - WDOG_A Clocks/Resets are + // enabled ; 0 - WDOG_A + // Clocks/Resets are disabled + +#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for WDOG_A ; 0 + // - De-assert reset for WDOG_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UART_A0 clk during + // deep-sleep mode 0 - Disable + // UART_A0 clk during deep-sleep + // mode ; + +#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9 +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UART_A0 clk during + // sleep mode 0 - Disable UART_A0 + // clk during sleep mode ; + +#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1 +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UART_A0 clk during + // run mode 0 - Disable UART_A0 clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \ + 0x00000002 // 1 - UART_A0 Clocks/Resets are + // enabled ; 0 - UART_A0 + // Clocks/Resets are disabled + +#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for UART_A0 ; 0 + // - De-assert reset for UART_A0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UART_A1 clk during + // deep-sleep mode 0 - Disable + // UART_A1 clk during deep-sleep + // mode ; + +#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9 +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UART_A1 clk during + // sleep mode 0 - Disable UART_A1 + // clk during sleep mode ; + +#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1 +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UART_A1 clk during + // run mode 0 - Disable UART_A1 clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \ + 0x00000002 // 1 - UART_A1 Clocks/Resets are + // enabled ; 0 - UART_A1 + // Clocks/Resets are disabled + +#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // UART_A1 ; 0 - De-assert the soft + // reset for UART_A1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A0 clock + // during deep-sleep ; 0 - Disable + // the GPT_A0 clock during + // deep-sleep + +#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A0 clock + // during sleep ; 0 - Disable the + // GPT_A0 clock during sleep + +#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A0 clock + // during run ; 0 - Disable the + // GPT_A0 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A0 clocks/resets are + // enabled ; 0 - GPT_A0 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A0 ; 0 - De-assert the soft + // reset for GPT_A0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A1 clock + // during deep-sleep ; 0 - Disable + // the GPT_A1 clock during + // deep-sleep + +#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A1 clock + // during sleep ; 0 - Disable the + // GPT_A1 clock during sleep + +#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A1 clock + // during run ; 0 - Disable the + // GPT_A1 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A1 clocks/resets are + // enabled ; 0 - GPT_A1 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A1 ; 0 - De-assert the soft + // reset for GPT_A1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A2_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A2 clock + // during deep-sleep ; 0 - Disable + // the GPT_A2 clock during + // deep-sleep + +#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A2 clock + // during sleep ; 0 - Disable the + // GPT_A2 clock during sleep + +#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A2 clock + // during run ; 0 - Disable the + // GPT_A2 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A2_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A2 clocks/resets are + // enabled ; 0 - GPT_A2 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A2 ; 0 - De-assert the soft + // reset for GPT_A2 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A3_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A3 clock + // during deep-sleep ; 0 - Disable + // the GPT_A3 clock during + // deep-sleep + +#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A3 clock + // during sleep ; 0 - Disable the + // GPT_A3 clock during sleep + +#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A3 clock + // during run ; 0 - Disable the + // GPT_A3 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A3_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A3 Clocks/resets are + // enabled ; 0 - GPT_A3 + // Clocks/resets are disabled + +#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A3 ; 0 - De-assert the soft + // reset for GPT_A3 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \ + 0x03FF0000 + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16 +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \ + 0x0000FFFF + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \ + 0x00010000 // 1 - Assert the reset for MCASP + // Frac-clk div; 0 - Donot assert + // the reset for MCASP frac clk-div + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \ + 0x000003FF + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CRYPTO_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable the Crypto clock + // during deep-sleep + +#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9 +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the Crypto clock + // during sleep ; 0 - Disable the + // Crypto clock during sleep + +#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1 +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the Crypto clock + // during run ; 0 - Disable the + // Crypto clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CRYPTO_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \ + 0x00000002 // 1 - Crypto clocks/resets are + // enabled ; 0 - Crypto + // clocks/resets are disabled + +#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // Crypto ; 0 - De-assert the soft + // reset for Crypto + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable the MCSPI_S0 clock + // during deep-sleep + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9 +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the MCSPI_S0 clock + // during sleep ; 0 - Disable the + // MCSPI_S0 clock during sleep + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1 +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the MCSPI_S0 clock + // during run ; 0 - Disable the + // MCSPI_S0 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are + // enabled ; 0 - MCSPI_S0 + // Clocks/resets are disabled + +#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // MCSPI_S0 ; 0 - De-assert the soft + // reset for MCSPI_S0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud-clk + // for MCSPI_S0 ; 1 - PLL divclk is + // used as buad-clk for MCSPI_S0 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_S0 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_S0 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_I2C_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the I2C Clock during + // deep-sleep 0 - Disable the I2C + // clock during deep-sleep + +#define APPS_RCM_I2C_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_I2C_CLK_GATING_NU1_S 9 +#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the I2C clock during + // sleep ; 0 - Disable the I2C clock + // during sleep + +#define APPS_RCM_I2C_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_I2C_CLK_GATING_NU2_S 1 +#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the I2C clock during + // run ; 0 - Disable the I2C clock + // during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_I2C_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \ + 0x00000002 // 1 - I2C Clocks/Resets are + // enabled ; 0 - I2C clocks/resets + // are disabled + +#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // Shared-I2C ; 0 - De-assert the + // soft reset for Shared-I2C + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_LPDS_REQ register. +// +//****************************************************************************** +#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \ + 0x00000001 // 1 - Request for LPDS + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_TURBO_REQ register. +// +//****************************************************************************** +#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \ + 0x00000001 // 1 - Request for TURBO + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \ + 0x00000002 // 1 - Enable the NWP to wake APPS + // from deep-sleep ; 0 - Disable NWP + // to wake APPS from deep-sleep + +#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \ + 0x00000001 // 1 - Enable deep-sleep wake timer + // in APPS RCM for deep-sleep; 0 - + // Disable deep-sleep wake timer in + // APPS RCM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \ + 0xFFFF0000 // Configuration (in slow_clks) + // which says when to request for + // OPP during deep-sleep exit + +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16 +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \ + 0x0000FFFF // Configuration (in slow_clks) + // which says when to request for + // WAKE during deep-sleep exit + +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register. +// +//****************************************************************************** +#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \ + 0x00000002 // 1- Enable the sleep wakeup due + // to NWP request. 0- Disable the + // sleep wakeup due to NWP request + +#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \ + 0x00000001 // 1- Enable the sleep wakeup due + // to sleep-timer; 0-Disable the + // sleep wakeup due to sleep-timer + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \ + 0xFFFFFFFF // Configuration (number of + // sysclks-80MHz) for the Sleep + // wakeup timer + +#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register. +// +//****************************************************************************** +#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \ + 0x00000001 // When 1 => APPS generated a wake + // request to NWP (When NWP is in + // any of its low-power modes : + // SLP/DSLP/LPDS) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register. +// +//****************************************************************************** +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \ + 0x00000008 // 1 - Indicates that deep-sleep + // timer expiry had caused the + // wakeup from deep-sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \ + 0x00000004 // 1 - Indicates that sleep timer + // expiry had caused the wakeup from + // sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \ + 0x00000002 // 1 - Indicates that NWP had + // caused the wakeup from deep-sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \ + 0x00000001 // 1 - Indicates that NWP had + // caused the wakeup from Sleep + + + + +#endif // __HW_APPS_RCM_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_camera.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_camera.h new file mode 100755 index 00000000000..11e4edb0e37 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_camera.h @@ -0,0 +1,517 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_CAMERA_H__ +#define __HW_CAMERA_H__ + +//***************************************************************************** +// +// The following are defines for the CAMERA register offsets. +// +//***************************************************************************** +#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP + // revision code ( Parallel Mode) +#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the + // various parameters of the OCP + // interface (CCP and Parallel Mode) +#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status + // information about the module + // excluding the interrupt status + // information (CCP and Parallel + // Mode) +#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups + // all the status of the module + // internal events that can generate + // an interrupt (CCP & Parallel + // Mode) +#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register + // allows to enable/disable the + // module internal sources of + // interrupt on an event-by-event + // basis (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the + // various parameters of the Camera + // Core block (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA + // interface of the Camera Core + // block (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value + // of the clock divisor used to + // generate the external clock + // (Parallel Mode) +#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to + // the FIFO and read from the FIFO + // (CCP & Parallel Mode) +#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status + // of some important variables of + // the camera core module (CCP & + // Parallel Mode) +#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values + // of the generic parameters of the + // module + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_REVISION register. +// +//****************************************************************************** +#define CAMERA_CC_REVISION_REV_M \ + 0x000000FF // IP revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 + +#define CAMERA_CC_REVISION_REV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_SYSCONFIG register. +// +//****************************************************************************** +#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \ + 0x00000018 // Slave interface power management + // req/ack control """00"" + // Force-idle. An idle request is + // acknoledged unconditionally" + // """01"" No-idle. An idle request + // is never acknowledged" """10"" + // reserved (Smart-idle not + // implemented)" + +#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3 +#define CAMERA_CC_SYSCONFIG_SOFT_RESET \ + 0x00000002 // Software reset. Set this bit to + // 1 to trigger a module reset. The + // bit is automatically reset by the + // hardware. During reset it always + // returns 0. 0 Normal mode 1 The + // module is reset + +#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \ + 0x00000001 // Internal OCP clock gating + // strategy 0 OCP clock is + // free-running 1 Automatic OCP + // clock gating strategy is applied + // based on the OCP interface + // activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_SYSSTATUS register. +// +//****************************************************************************** +#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \ + 0x00000001 // Internal Reset Monitoring 0 + // Internal module reset is on-going + // 1 Reset completed + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_IRQSTATUS register. +// +//****************************************************************************** +#define CAMERA_CC_IRQSTATUS_FS_IRQ \ + 0x00080000 // Frame Start has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_LE_IRQ \ + 0x00040000 // Line End has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_LS_IRQ \ + 0x00020000 // Line Start has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FE_IRQ \ + 0x00010000 // Frame End has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \ + 0x00000800 // FSP code error 0 Event false "1 + // Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \ + 0x00000400 // Frame Height Error 0 Event false + // "1 Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \ + 0x00000200 // False Synchronization Code 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \ + 0x00000100 // Shifted Synchronization Code 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \ + 0x00000010 // FIFO is not empty 0 Event false + // "1 Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \ + 0x00000008 // FIFO is full 0 Event false "1 + // Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \ + 0x00000004 // FIFO threshold has been reached + // 0 Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \ + 0x00000002 // FIFO overflow has occurred 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \ + 0x00000001 // FIFO underflow has occurred 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_IRQENABLE register. +// +//****************************************************************************** +#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \ + 0x00080000 // Frame Start Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \ + 0x00040000 // Line End Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \ + 0x00020000 // Line Start Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \ + 0x00010000 // Frame End Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \ + 0x00000800 // FSP code Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \ + 0x00000400 // Frame Height Error Interrupt + // Enable 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \ + 0x00000200 // False Synchronization Code + // Interrupt Enable 0 Event is + // masked 1 Event generates an + // interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \ + 0x00000100 // False Synchronization Code + // Interrupt Enable 0 Event is + // masked 1 Event generates an + // interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \ + 0x00000010 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \ + 0x00000008 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \ + 0x00000004 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \ + 0x00000002 // FIFO Overflow Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \ + 0x00000001 // FIFO Underflow Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +//****************************************************************************** +// +// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \ + 0x00080000 // Synchronize all camera sensor + // inputs This must be set during + // the configuration phase before + // CC_EN set to '1'. This can be + // used in very high frequency to + // avoid dependancy to the IO + // timings. 0 No synchro (most of + // applications) 1 Synchro enabled + // (should never be required) + +#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite + // states machines of the camera + // core module - by writing a 1 to + // this bit. must be applied when + // CC_EN = 0 Reads returns 0 +#define CAMERA_CC_CTRL_CC_FRAME_TRIG \ + 0x00020000 // Set the modality in which CC_EN + // works when a disabling of the + // sensor camera core is wanted "If + // CC_FRAME_TRIG = 1 by writing + // ""0"" to CC_EN" the module is + // disabled at the end of the frame + // "If CC_FRAME_TRIG = 0 by writing + // ""0"" to CC_EN" the module is + // disabled immediately + +#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of + // the camera core module "By + // writing ""1"" to this field the + // module is enabled." "By writing + // ""0"" to this field the module is + // disabled at" the end of the frame + // if CC_FRAM_TRIG =1 and is + // disabled immediately if + // CC_FRAM_TRIG = 0 +#define CAMERA_CC_CTRL_NOBT_SYNCHRO \ + 0x00002000 // Enables to start at the + // beginning of the frame or not in + // NoBT 0 Acquisition starts when + // Vertical synchro is high 1 + // Acquisition starts when Vertical + // synchro goes from low to high + // (beginning of the frame) - + // Recommended. + +#define CAMERA_CC_CTRL_BT_CORRECT \ + 0x00001000 // Enables the correction within + // the sync codes in BT mode 0 + // correction is not enabled 1 + // correction is enabled + +#define CAMERA_CC_CTRL_PAR_ORDERCAM \ + 0x00000800 // Enables swap between image-data + // in parallel mode 0 swap is not + // enabled 1 swap is enabled + +#define CAMERA_CC_CTRL_PAR_CLK_POL \ + 0x00000400 // Inverts the clock coming from + // the sensor in parallel mode 0 + // clock not inverted - data sampled + // on rising edge 1 clock inverted - + // data sampled on falling edge + +#define CAMERA_CC_CTRL_NOBT_HS_POL \ + 0x00000200 // Sets the polarity of the + // synchronization signals in NOBT + // parallel mode 0 CAM_P_HS is + // active high 1 CAM_P_HS is active + // low + +#define CAMERA_CC_CTRL_NOBT_VS_POL \ + 0x00000100 // Sets the polarity of the + // synchronization signals in NOBT + // parallel mode 0 CAM_P_VS is + // active high 1 CAM_P_VS is active + // low + +#define CAMERA_CC_CTRL_PAR_MODE_M \ + 0x0000000E // Sets the Protocol Mode of the + // Camera Core module in parallel + // mode (when CCP_MODE = 0) """000"" + // Parallel NOBT 8-bit" """001"" + // Parallel NOBT 10-bit" """010"" + // Parallel NOBT 12-bit" """011"" + // reserved" """100"" Parallet BT + // 8-bit" """101"" Parallel BT + // 10-bit" """110"" reserved" + // """111"" FIFO test mode. Refer to + // Table 12 - FIFO Write and Read + // access" + +#define CAMERA_CC_CTRL_PAR_MODE_S 1 +#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode + // 0 CCP mode disabled 1 CCP mode + // enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_CTRL_DMA register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_DMA_DMA_EN \ + 0x00000100 // Sets the number of dma request + // lines 0 DMA interface disabled + // The DMA request line stays + // inactive 1 DMA interface enabled + // The DMA request line is + // operational + +#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \ + 0x0000007F // Sets the threshold of the FIFO + // the assertion of the dmarequest + // line takes place when the + // threshold is reached. + // """0000000"" threshold set to 1" + // """0000001"" threshold set to 2" + // … """1111111"" threshold set to + // 128" + +#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_CTRL_XCLK register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \ + 0x0000001F // Sets the clock divisor value for + // CAM_XCLK generation. based on + // CAM_MCK (value of CAM_MCLK is + // 96MHz) """00000"" CAM_XCLK Stable + // Low Level" Divider not enabled + // """00001"" CAM_XCLK Stable High + // Level" Divider not enabled from 2 + // to 30 CAM_XCLK = CAM_MCLK / + // XCLK_DIV """11111"" Bypass - + // CAM_XCLK = CAM_MCLK" + +#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_FIFO_DATA register. +// +//****************************************************************************** +#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \ + 0xFFFFFFFF // Writes the 32-bit word into the + // FIFO Reads the 32-bit word from + // the FIFO + +#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the CAMERA_O_CC_TEST register. +// +//****************************************************************************** +#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \ + 0xFF000000 // FIFO READ Pointer This field + // shows the value of the FIFO read + // pointer Expected value ranges + // from 0 to 127 + +#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24 +#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \ + 0x00FF0000 // FIFO WRITE pointer This field + // shows the value of the FIFO write + // pointer Expected value ranges + // from 0 to 127 + +#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16 +#define CAMERA_CC_TEST_FIFO_LEVEL_M \ + 0x0000FF00 // FIFO level (how many 32-bit + // words the FIFO contains) This + // field shows the value of the FIFO + // level and can assume values from + // 0 to 128 + +#define CAMERA_CC_TEST_FIFO_LEVEL_S 8 +#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \ + 0x000000FF // FIFO level peak This field shows + // the max value of the FIFO level + // and can assume values from 0 to + // 128 + +#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_GEN_PAR register. +// +//****************************************************************************** +#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \ + 0x00000007 // Camera Core FIFO DEPTH generic + // parameter + +#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0 + + + +#endif // __HW_CAMERA_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_common_reg.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_common_reg.h new file mode 100755 index 00000000000..f296e1c533b --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_common_reg.h @@ -0,0 +1,1115 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_COMMON_REG_H__ +#define __HW_COMMON_REG_H__ + +//***************************************************************************** +// +// The following are defines for the COMMON_REG register offsets. +// +//***************************************************************************** +#define COMMON_REG_O_I2C_Properties_Register \ + 0x00000000 + +#define COMMON_REG_O_SPI_Properties_Register \ + 0x00000004 + +#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \ + 0x0000000C + +#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \ + 0x00000010 + +#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \ + 0x00000014 + +#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \ + 0x00000018 + +#define COMMON_REG_O_Flash_ctrl_reg \ + 0x0000001C + +#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \ + 0x00000024 + +#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \ + 0x00000028 + +#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \ + 0x0000002C + +#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \ + 0x00000030 + +#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \ + 0x00000034 + +#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \ + 0x00000038 + +#define COMMON_REG_O_GPIO_properties_register \ + 0x0000003C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \ + 0x00000040 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \ + 0x00000044 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \ + 0x00000048 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \ + 0x0000004C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \ + 0x00000050 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \ + 0x00000054 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \ + 0x00000058 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \ + 0x0000005C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \ + 0x00000060 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \ + 0x00000064 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \ + 0x00000068 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \ + 0x0000006C + +#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \ + 0x00000070 + +#define COMMON_REG_O_NW_SEMAPPHORE_PEND \ + 0x00000074 + +#define COMMON_REG_O_SEMAPHORE_STATUS \ + 0x00000078 + +#define COMMON_REG_O_IDMEM_TIM_Update \ + 0x0000007C + +#define COMMON_REG_O_FPGA_ROM_WR_EN \ + 0x00000080 + +#define COMMON_REG_O_NW_INT_MASK \ + 0x00000084 + +#define COMMON_REG_O_NW_INT_MASK_SET \ + 0x00000088 + +#define COMMON_REG_O_NW_INT_MASK_CLR \ + 0x0000008C + +#define COMMON_REG_O_NW_INT_STS_CLR \ + 0x00000090 + +#define COMMON_REG_O_NW_INT_ACK 0x00000094 +#define COMMON_REG_O_NW_INT_TRIG \ + 0x00000098 + +#define COMMON_REG_O_NW_INT_STS_MASKED \ + 0x0000009C + +#define COMMON_REG_O_NW_INT_STS_RAW \ + 0x000000A0 + +#define COMMON_REG_O_APPS_INT_MASK \ + 0x000000A4 + +#define COMMON_REG_O_APPS_INT_MASK_SET \ + 0x000000A8 + +#define COMMON_REG_O_APPS_INT_MASK_CLR \ + 0x000000AC + +#define COMMON_REG_O_APPS_INT_STS_CLR \ + 0x000000B0 + +#define COMMON_REG_O_APPS_INT_ACK \ + 0x000000B4 + +#define COMMON_REG_O_APPS_INT_TRIG \ + 0x000000B8 + +#define COMMON_REG_O_APPS_INT_STS_MASKED \ + 0x000000BC + +#define COMMON_REG_O_APPS_INT_STS_RAW \ + 0x000000C0 + +#define COMMON_REG_O_IDMEM_TIM_Updated \ + 0x000000C4 + +#define COMMON_REG_O_APPS_GPIO_TRIG_EN \ + 0x000000C8 + +#define COMMON_REG_O_EMU_DEBUG_REG \ + 0x000000CC + +#define COMMON_REG_O_SEMAPHORE_STATUS2 \ + 0x000000D0 + +#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \ + 0x000000D4 + +#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \ + 0x000000D8 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_I2C_Properties_Register register. +// +//****************************************************************************** +#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SPI_Properties_Register register. +// +//****************************************************************************** +#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register. +// +//****************************************************************************** +#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \ + 0x0000000F // Interrupt enable APPS bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_sh_resource_Interrupt_status register. +// +//****************************************************************************** +#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \ + 0x0000000F // Interrupt enable APPS bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register. +// +//****************************************************************************** +#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \ + 0x0000000F // Interrupt enable NWP bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NWP_sh_resource_Interrupt_status register. +// +//****************************************************************************** +#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \ + 0x0000000F // Interrupt enable NWP bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Flash_ctrl_reg register. +// +//****************************************************************************** +#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M0_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \ + 0x0003FFFF // Master 0 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M1_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \ + 0x0003FFFF // Master 1 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M2_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \ + 0x0003FFFF // Master 2 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M3_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \ + 0x0003FFFF // Master 3 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M4_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \ + 0x0003FFFF // Master 4 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M5_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \ + 0x0003FFFF // Master 5 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_GPIO_properties_register register. +// +//****************************************************************************** +#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \ + 0x000003FF // Shared GPIO configuration + // register. Bit [1:0] to configure + // GPIO0 Bit [3:2] to configure + // GPIO1 Bit [5:4] to configure + // GPIO2 Bit [7:6] to configure + // GPIO3 Bit [9:8] to configure + // GPIO4 each GPIO can be + // individully selected. When “00� + // GPIO is free resource. When “01� + // GPIO is APPS resource. When “10� + // GPIO is NWP resource. Writing 11 + // doesnt have any affect, i.e. If + // one write only relevant gpio + // semaphore and other bits are 1s, + // it'll not disturb the other + // semaphore bits. For example : Say + // If NW wants to take control of + // gpio-1, one should write + // 10'b11_1111_1011 and if one wants + // to release it write + // 10'b11_1111_0011. + +#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE1 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE2 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE3 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE4 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE5 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE6 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE7 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE8 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE9 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE10 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE11 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE12 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \ + 0xFFFFFFFF // APPS NW semaphore register - not + // reflected in status. + +#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_SEMAPPHORE_PEND register. +// +//****************************************************************************** +#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \ + 0xFFFFFFFF // APPS SEMAPOHORE STATUS + +#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_SEMAPPHORE_PEND register. +// +//****************************************************************************** +#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \ + 0xFFFFFFFF // NW SEMAPHORE STATUS + +#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_STATUS register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \ + 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore + // status of flash_control 7:6 + // :semaphore status of + // gpio_properties 5:4 + // :semaphore status of + // spi_propertie 1:0 :semaphore + // status of i2c_propertie + +#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_IDMEM_TIM_Update register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_FPGA_ROM_WR_EN register. +// +//****************************************************************************** +#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \ + 0x00000001 // when '1' enables Write into + // IDMEM CORE ROM, APPS ROM, NWP ROM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \ + 0xFFFFFFFF // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK_SET register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \ + 0xFFFFFFFF // write 1 to set corresponding bit + // in NW_INT_MASK;0 = no effect + +#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK_CLR register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // bit in NW_INT_MASK;0 = no effect + +#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_CLR register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt; 0 = no effect; + // interrupt is not lost if coincide + // with write operation + +#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_ACK register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt;0 = no effect + +#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_TRIG register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \ + 0xFFFFFFFF // Writing a 1 to a bit in this + // register causes the the Host CPU + // if enabled (not masked). This + // register is self-clearing. + // Writing 0 has no effect + +#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_MASKED register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by NW_INT mask + +#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_RAW register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \ + 0xFFFFFFFF // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK_SET register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \ + 0xFFFFFFFF // write 1 to set corresponding bit + // in APPS_INT_MASK;0 = no effect + +#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK_CLR register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // bit in APPS_INT_MASK;0 = no + // effect + +#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_CLR register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt; 0 = no effect; + // interrupt is not lost if coincide + // with write operation + +#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_ACK register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt;0 = no effect + +#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_TRIG register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \ + 0xFFFFFFFF // Writing a 1 to a bit in this + // register causes the the Host CPU + // if enabled (not masked). This + // register is self-clearing. + // Writing 0 has no effect + +#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_MASKED register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by APPS_INT mask + +#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_RAW register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_IDMEM_TIM_Updated register. +// +//****************************************************************************** +#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \ + 0x00000001 // toggle in this signal + // indicatesIDMEM_TIM_UPDATE + // register mentioned above is + // updated. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_GPIO_TRIG_EN register. +// +//****************************************************************************** +#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \ + 0x0000001F // APPS GPIO Trigger EN control. + // Bit 0: when '1' enable GPIO 0 + // trigger. This bit enables trigger + // for all GPIO 0 pins (GPIO 0 to + // GPIO7). Bit 1: when '1' enable + // GPIO 1 trigger. This bit enables + // trigger for all GPIO 1 pins ( + // GPIO8 to GPIO15). Bit 2: when '1' + // enable GPIO 2 trigger. This bit + // enables trigger for all GPIO 2 + // pins (GPIO16 to GPIO23). Bit 3: + // when '1' enable GPIO 3 trigger. + // This bit enables trigger for all + // GPIO 3 pins (GPIO24 to GPIO31). + // Bit 4: when '1' enable GPIO 4 + // trigger. This bit enables trigger + // for all GPIO 4 pins.(GPIO32 to + // GPIO39) + +#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_EMU_DEBUG_REG register. +// +//****************************************************************************** +#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \ + 0xFFFFFFFF // 0 th bit used for stalling APPS + // DMA and 1st bit is used for + // stalling NWP DMA for debug + // purpose. Other bits are unused. + +#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_STATUS2 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \ + 0x00FFFFFF // SEMAPHORE STATUS 23:22 + // :semaphore status of + // apps_nw_semaphore11 21:20 + // :semaphore status of + // apps_nw_semaphore11 19:18 + // :semaphore status of + // apps_nw_semaphore10 17:16 + // :semaphore status of + // apps_nw_semaphore9 15:14 + // :semaphore status of + // apps_nw_semaphore8 13:12 + // :semaphore status of + // apps_nw_semaphore7 11:10 + // :semaphore status of + // apps_nw_semaphore6 9:8 :semaphore + // status of apps_nw_semaphore5 7:6 + // :semaphore status of + // apps_nw_semaphore4 5:4 :semaphore + // status of apps_nw_semaphore3 3:2 + // :semaphore status of + // apps_nw_semaphore2 1:0 :semaphore + // status of apps_nw_semaphore1 + +#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \ + 0x0003FFFF // 1:0 : prvious owner of + // i2c_properties_reg[1:0] 3:2 : + // prvious owner of + // spi_properties_reg[1:0] 5:4 : + // prvious owner of + // gpio_properties_reg[1:0] 9:8 : + // prvious owner of + // gpio_properties_reg[3:2] 11:10 : + // prvious owner of + // gpio_properties_reg[5:4] 13:12 : + // prvious owner of + // gpio_properties_reg[7:6] 15:14 : + // prvious owner of + // gpio_properties_reg[9:8] 17:16 : + // prvious owner of + // flash_control_reg[1:0] + +#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \ + 0x00FFFFFF // 1:0 : previous owner of + // apps_nw_semaphore1_reg[1:0] 3:2 : + // previous owner of + // apps_nw_semaphore2_reg[1:0] 5:4 : + // previous owner of + // apps_nw_semaphore3_reg[1:0] 7:6 : + // previous owner of + // apps_nw_semaphore4_reg[1:0] 9:8 : + // previous owner of + // apps_nw_semaphore5_reg[1:0] 11:10 + // : previous owner of + // apps_nw_semaphore6_reg[1:0] 13:12 + // : previous owner of + // apps_nw_semaphore7_reg[1:0] 15:14 + // : previous owner of + // apps_nw_semaphore8_reg[1:0] 17:16 + // : previous owner of + // apps_nw_semaphore9_reg[1:0] 19:18 + // : previous owner of + // apps_nw_semaphore10_reg[1:0] + // 21:20 : previous owner of + // apps_nw_semaphore11_reg[1:0] + // 23:22 : previous owner of + // apps_nw_semaphore12_reg[1:0] + +#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0 + + + +#endif // __HW_COMMON_REG_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_des.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_des.h new file mode 100755 index 00000000000..7d8de2c32fc --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_des.h @@ -0,0 +1,337 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_DES_H__ +#define __HW_DES_H__ + +//***************************************************************************** +// +// The following are defines for the DES_P register offsets. +// +//***************************************************************************** +#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key +#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key +#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key +#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key +#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit + // key/192-bit key +#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit + // key/192-bit key +#define DES_O_IV_L 0x00000018 // Initialization vector LSW +#define DES_O_IV_H 0x0000001C // Initialization vector MSW +#define DES_O_CTRL 0x00000020 +#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data + // length in bytes for all modes. + // Once processing is started with + // this context this length + // decrements to zero. Data lengths + // up to (2^32 – 1) bytes are + // allowed. A write to this register + // triggers the engine to start + // using this context. For a Host + // read operation these registers + // return all-zeroes. +#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write + // encrypted/decrypted data. +#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write + // encrypted/decrypted data. +#define DES_O_REVISION 0x00000030 +#define DES_O_SYSCONFIG 0x00000034 +#define DES_O_SYSSTATUS 0x00000038 +#define DES_O_IRQSTATUS 0x0000003C // This register indicates the + // interrupt status. If one of the + // interrupt bits is set the + // interrupt output will be asserted +#define DES_O_IRQENABLE 0x00000040 // This register contains an enable + // bit for each unique interrupt + // generated by the module. It + // matches the layout of + // DES_IRQSTATUS register. An + // interrupt is enabled when the bit + // in this register is set to 1 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_L register. +// +//****************************************************************************** +#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3 +#define DES_KEY3_L_KEY3_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_H register. +// +//****************************************************************************** +#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3 +#define DES_KEY3_H_KEY3_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_L register. +// +//****************************************************************************** +#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2 +#define DES_KEY2_L_KEY2_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_H register. +// +//****************************************************************************** +#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2 +#define DES_KEY2_H_KEY2_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_L register. +// +//****************************************************************************** +#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1 +#define DES_KEY1_L_KEY1_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_H register. +// +//****************************************************************************** +#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1 +#define DES_KEY1_H_KEY1_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_L register. +// +//****************************************************************************** +#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC + // CFB modes +#define DES_IV_L_IV_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_H register. +// +//****************************************************************************** +#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC + // CFB modes +#define DES_IV_H_IV_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_CTRL register. +// +//****************************************************************************** +#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit + // indicates that the context data + // registers can be overwritten and + // the host is permitted to write + // the next context. +#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0 + // ecb mode 0x1 cbc mode 0x2 cfb + // mode 0x3 reserved +#define DES_CTRL_MODE_S 4 +#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES + // encryption/decryption. 0 des mode + // 1 tdes mode +#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0 + // decryption is selected 1 + // Encryption is selected +#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to + // encrypt/decrypt data +#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data + // decrypted/encrypted ready +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_LENGTH register. +// +//****************************************************************************** +#define DES_LENGTH_LENGTH_M 0xFFFFFFFF +#define DES_LENGTH_LENGTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_L register. +// +//****************************************************************************** +#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption +#define DES_DATA_L_DATA_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_H register. +// +//****************************************************************************** +#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption +#define DES_DATA_H_DATA_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_REVISION register. +// +//****************************************************************************** +#define DES_REVISION_SCHEME_M 0xC0000000 +#define DES_REVISION_SCHEME_S 30 +#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define DES_REVISION_FUNC_S 16 +#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define DES_REVISION_R_RTL_S 11 +#define DES_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. + +#define DES_REVISION_X_MAJOR_S 8 +#define DES_REVISION_CUSTOM_M 0x000000C0 +#define DES_REVISION_CUSTOM_S 6 +#define DES_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. + +#define DES_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSCONFIG register. +// +//****************************************************************************** +#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // If set to ‘1’ the DMA context + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // If set to ‘1’ the DMA output + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // If set to ‘1’ the DMA input + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSSTATUS register. +// +//****************************************************************************** +#define DES_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQSTATUS register. +// +//****************************************************************************** +#define DES_IRQSTATUS_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define DES_IRQSTATUS_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQENABLE register. +// +//****************************************************************************** +#define DES_IRQENABLE_M_DATA_OUT \ + 0x00000004 // If this bit is set to ‘1’ the + // secure data output interrupt is + // enabled. + +#define DES_IRQENABLE_M_DATA_IN \ + 0x00000002 // If this bit is set to ‘1’ the + // secure data input interrupt is + // enabled. + +#define DES_IRQENABLE_M_CONTEX_IN \ + 0x00000001 // If this bit is set to ‘1’ the + // secure context interrupt is + // enabled. + + + + +#endif // __HW_DES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_dthe.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_dthe.h new file mode 100755 index 00000000000..fa5d39450aa --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_dthe.h @@ -0,0 +1,390 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +//***************************************************************************** + +#ifndef __HW_DTHE_H__ +#define __HW_DTHE_H__ + +//***************************************************************************** +// +// The following are defines for the DTHE register offsets. +// +//***************************************************************************** +#define DTHE_O_SHA_IM 0x00000810 +#define DTHE_O_SHA_RIS 0x00000814 +#define DTHE_O_SHA_MIS 0x00000818 +#define DTHE_O_SHA_IC 0x0000081C +#define DTHE_O_AES_IM 0x00000820 +#define DTHE_O_AES_RIS 0x00000824 +#define DTHE_O_AES_MIS 0x00000828 +#define DTHE_O_AES_IC 0x0000082C +#define DTHE_O_DES_IM 0x00000830 +#define DTHE_O_DES_RIS 0x00000834 +#define DTHE_O_DES_MIS 0x00000838 +#define DTHE_O_DES_IC 0x0000083C +#define DTHE_O_EIP_CGCFG 0x00000A00 +#define DTHE_O_EIP_CGREQ 0x00000A04 +#define DTHE_O_CRC_CTRL 0x00000C00 +#define DTHE_O_CRC_SEED 0x00000C10 +#define DTHE_O_CRC_DIN 0x00000C14 +#define DTHE_O_CRC_RSLT_PP 0x00000C18 +#define DTHE_O_RAND_KEY0 0x00000F00 +#define DTHE_O_RAND_KEY1 0x00000F04 +#define DTHE_O_RAND_KEY2 0x00000F08 +#define DTHE_O_RAND_KEY3 0x00000F0C + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IMST register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is + // raised when DMA complets the + // output context movement from + // internal register +#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IRIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done +#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IMIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done +#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_ICIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done� + // flag +#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done� flag +#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done� flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IMST register. +// +//****************************************************************************** +#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is + // raised when DMA finishes writing + // last word of the process result +#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is + // raised when DMA complets the + // output context movement from + // internal register +#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IRIS register. +// +//****************************************************************************** +#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done +#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IMIS register. +// +//****************************************************************************** +#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done +#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_ICIS register. +// +//****************************************************************************** +#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement + // done� flag +#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done� + // flag +#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done� flag +#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done� flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IMST register. +// +//****************************************************************************** +#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is + // raised when DMA finishes writing + // last word of the process result +#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IRIS register. +// +//****************************************************************************** +#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IMIS register. +// +//****************************************************************************** +#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_ICIS register. +// +//****************************************************************************** +#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement + // done� flag +#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done� + // flag +#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done� flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_EIP_CGCFG register. +// +//****************************************************************************** +#define DTHE_EIP_CGCFG_EIP29_CFG \ + 0x00000010 // Clock gating protocol setting + // for EIP29T. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP75_CFG \ + 0x00000008 // Clock gating protocol setting + // for EIP75T. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP16_CFG \ + 0x00000004 // Clock gating protocol setting + // for DES. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP36_CFG \ + 0x00000002 // Clock gating protocol setting + // for AES. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP57_CFG \ + 0x00000001 // Clock gating protocol setting + // for SHAMD5. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_EIP_CGREQ register. +// +//****************************************************************************** +#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5� write “1� to lower + // bits [4:0] will set the bit. + // Write “0� will be ignored When + // “0x2� write “1� to lower bit + // [4:0] will clear the bit. Write + // “0� will be ignored for other key + // value, regular read write + // operation +#define DTHE_EIP_CGREQ_Key_S 28 +#define DTHE_EIP_CGREQ_EIP29_REQ \ + 0x00000010 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP75_REQ \ + 0x00000008 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP16_REQ \ + 0x00000004 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP36_REQ \ + 0x00000002 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP57_REQ \ + 0x00000001 // 0 – request clock gating 1 – + // request to un-gate the clock. + +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register. +// +//****************************************************************************** +#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED + // register context as starting + // value 10 – all “zero� 11 – all + // “one� This is self clearing. With + // first write to data register this + // value clears to zero and remain + // zero for rest of the operation + // unless written again +#define DTHE_CRC_CTRL_INIT_S 13 +#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8 + // bit +#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result + // before storing to CRC_RSLT_PP0 +#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result + // byte before storing to + // CRC_RSLT_PP0. applicable for all + // bytes in word +#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For + // all bytes in word +#define DTHE_CRC_CTRL_ENDIAN_M \ + 0x00000030 // Endian control [0] – swap byte + // in half-word [1] – swap half word + +#define DTHE_CRC_CTRL_ENDIAN_S 4 +#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 – + // polynomial 0x8005 0001 – + // polynomial 0x1021 0010 – + // polynomial 0x4C11DB7 0011 – + // polynomial 0x1EDC6F41 1000 – TCP + // checksum TYPE in DTHE_S_CRC_CTRL + // & DTHE_S_CRC_CTRL should be + // exclusive +#define DTHE_CRC_CTRL_TYPE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_SEED register. +// +//****************************************************************************** +#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and + // checksum operation. Please see + // CTRL register for more detail. + // This resister also holds the + // latest result of CRC or checksum + // operation +#define DTHE_CRC_SEED_SEED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_DIN register. +// +//****************************************************************************** +#define DTHE_CRC_DIN_DATA_IN_M \ + 0xFFFFFFFF // Input data for CRC or checksum + // operation + +#define DTHE_CRC_DIN_DATA_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_CRC_RSLT_PP register. +// +//****************************************************************************** +#define DTHE_CRC_RSLT_PP_RSLT_PP_M \ + 0xFFFFFFFF // Input data for CRC or checksum + // operation + +#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY0 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [31:0] +#define DTHE_RAND_KEY0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY1 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [63:32] +#define DTHE_RAND_KEY1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY2 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [95:34] +#define DTHE_RAND_KEY2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY3 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [127:96] +#define DTHE_RAND_KEY3_KEY_S 0 + + + +#endif // __HW_DTHE_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_flash_ctrl.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_flash_ctrl.h new file mode 100755 index 00000000000..ba68c123949 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_flash_ctrl.h @@ -0,0 +1,1860 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_FLASH_CTRL_H__ +#define __HW_FLASH_CTRL_H__ + +//***************************************************************************** +// +// The following are defines for the FLASH_CTRL register offsets. +// +//***************************************************************************** +#define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA) + // offset 0x000 During a write + // operation this register contains + // a 4-byte-aligned address and + // specifies where the data is + // written. During erase operations + // this register contains a 1 + // KB-aligned CPU byte address and + // specifies which block is erased. + // Note that the alignment + // requirements must be met by + // software or the results of the + // operation are unpredictable. +#define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset + // 0x004 This register contains the + // data to be written during the + // programming cycle or read during + // the read cycle. Note that the + // contents of this register are + // undefined for a read access of an + // execute-only block. This register + // is not used during erase cycles. +#define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC) + // offset 0x008 When this register + // is written the Flash memory + // controller initiates the + // appropriate access cycle for the + // location specified by the Flash + // Memory Address (FMA) register . + // If the access is a write access + // the data contained in the Flash + // Memory Data (FMD) register is + // written to the specified address. + // This register must be the final + // register written and initiates + // the memory operation. The four + // control bits in the lower byte of + // this register are used to + // initiate memory operations. +#define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt + // Status (FCRIS) offset 0x00C This + // register indicates that the Flash + // memory controller has an + // interrupt condition. An interrupt + // is sent to the interrupt + // controller only if the + // corresponding FCIM register bit + // is set. +#define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask + // (FCIM) offset 0x010 This register + // controls whether the Flash memory + // controller generates interrupts + // to the controller. +#define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked + // Interrupt Status and Clear + // (FCMISC) offset 0x014 This + // register provides two functions. + // First it reports the cause of an + // interrupt by indicating which + // interrupt source or sources are + // signalling the interrupt. Second + // it serves as the method to clear + // the interrupt reporting. +#define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2) + // offset 0x020 When this register + // is written the Flash memory + // controller initiates the + // appropriate access cycle for the + // location specified by the Flash + // Memory Address (FMA) register . + // If the access is a write access + // the data contained in the Flash + // Write Buffer (FWB) registers is + // written. This register must be + // the final register written as it + // initiates the memory operation. +#define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid + // (FWBVAL) offset 0x030 This + // register provides a bitwise + // status of which FWBn registers + // have been written by the + // processor since the last write of + // the Flash memory write buffer. + // The entries with a 1 are written + // on the next write of the Flash + // memory write buffer. This + // register is cleared after the + // write operation by hardware. A + // protection violation on the write + // operation also clears this + // status. Software can program the + // same 32 words to various Flash + // memory locations by setting the + // FWB[n] bits after they are + // cleared by the write operation. + // The next write operation then + // uses the same data as the + // previous one. In addition if a + // FWBn register change should not + // be written to Flash memory + // software can clear the + // corresponding FWB[n] bit to + // preserve the existing data when + // the next write operation occurs. +#define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0 + // This register indicates the size + // of the on-chip Flash memory. + // Important: This register should + // be used to determine the size of + // the Flash memory that is + // implemented on this + // microcontroller. However to + // support legacy software the DC0 + // register is available. A read of + // the DC0 register correctly + // identifies legacy memory sizes. + // Software must use the FSIZE + // register for memory sizes that + // are not listed in the DC0 + // register description. +#define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4 + // This register indicates the size + // of the on-chip SRAM. Important: + // This register should be used to + // determine the size of the SRAM + // that is implemented on this + // microcontroller. However to + // support legacy software the DC0 + // register is available. A read of + // the DC0 register correctly + // identifies legacy memory sizes. + // Software must use the SSIZE + // register for memory sizes that + // are not listed in the DC0 + // register description. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMA register. +// +//****************************************************************************** +#define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in + // Flash memory where operation is + // performed except for nonvolatile + // registers +#define FLASH_CTRL_FMA_OFFSET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMD register. +// +//****************************************************************************** +#define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write + // operation. +#define FLASH_CTRL_FMD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMC register. +// +//****************************************************************************** +#define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This + // field contains a write key which + // is used to minimize the incidence + // of accidental Flash memory + // writes. The value 0xA442 must be + // written into this field for a + // Flash memory write to occur. + // Writes to the FMC register + // without this WRKEY value are + // ignored. A read of this field + // returns the value 0. +#define FLASH_CTRL_FMC_WRKEY_S 16 +#define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit + // is used to commit writes to + // Flash-memory-resident registers + // and to monitor the progress of + // that process. Value Description 1 + // Set this bit to commit (write) + // the register value to a + // Flash-memory-resident register. + // When read a 1 indicates that the + // previous commit access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous commit access is + // complete. +#define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit + // is used to mass erase the Flash + // main memory and to monitor the + // progress of that process. Value + // Description 1 Set this bit to + // erase the Flash main memory. When + // read a 1 indicates that the + // previous mass erase access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous mass erase access is + // complete. +#define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory + // This bit is used to erase a page + // of Flash memory and to monitor + // the progress of that process. + // Value Description 1 Set this bit + // to erase the Flash memory page + // specified by the contents of the + // FMA register. When read a 1 + // indicates that the previous page + // erase access is not complete. 0 A + // write of 0 has no effect on the + // state of this bit. When read a 0 + // indicates that the previous page + // erase access is complete. +#define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + // This bit is used to write a word + // into Flash memory and to monitor + // the progress of that process. + // Value Description 1 Set this bit + // to write the data stored in the + // FMD register into the Flash + // memory location specified by the + // contents of the FMA register. + // When read a 1 indicates that the + // write update access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous write update access is + // complete. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FCRIS register. +// +//****************************************************************************** +#define FLASH_CTRL_FCRIS_PROGRIS \ + 0x00002000 // Program Verify Error Raw + // Interrupt Status Value + // Description 1 An interrupt is + // pending because the verify of a + // PROGRAM operation failed. 0 An + // interrupt has not occurred. This + // bit is cleared by writing a 1 to + // the PROGMISC bit in the FCMISC + // register. + +#define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because the + // verify of an ERASE operation + // failed. 0 An interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the ERMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_INVDRIS \ + 0x00000400 // Invalid Data Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because a + // bit that was previously + // programmed as a 0 is now being + // requested to be programmed as a + // 1. 0 An interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the INVMISC bit in + // the FCMISC register. + +#define FLASH_CTRL_FCRIS_VOLTRIS \ + 0x00000200 // Pump Voltage Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because the + // regulated voltage of the pump + // went out of spec during the Flash + // operation and the operation was + // terminated. 0 An interrupt has + // not occurred. This bit is cleared + // by writing a 1 to the VOLTMISC + // bit in the FCMISC register. + +#define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This + // bit provides status EEPROM + // operation. Value Description 1 An + // EEPROM interrupt has occurred. 0 + // An EEPROM interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the EMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status + // This bit provides status on + // programming cycles which are + // write or erase actions generated + // through the FMC or FMC2 register + // bits (see page 537 and page 549). + // Value Description 1 The + // programming or erase cycle has + // completed. 0 The programming or + // erase cycle has not completed. + // This status is sent to the + // interrupt controller when the + // PMASK bit in the FCIM register is + // set. This bit is cleared by + // writing a 1 to the PMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + // Value Description 1 A program or + // erase action was attempted on a + // block of Flash memory that + // contradicts the protection policy + // for that block as set in the + // FMPPEn registers. 0 No access has + // tried to improperly program or + // erase the Flash memory. This + // status is sent to the interrupt + // controller when the AMASK bit in + // the FCIM register is set. This + // bit is cleared by writing a 1 to + // the AMISC bit in the FCMISC + // register. +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register. +// +//****************************************************************************** +#define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the ILLARIS bit + // is set. 0 The ILLARIS interrupt + // is suppressed and not sent to the + // interrupt controller. +#define FLASH_CTRL_FCIM_PROGMASK \ + 0x00002000 // PROGVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the PROGRIS bit is set. 0 + // The PROGRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the PRERIS bit is set. 0 The + // PRERIS interrupt is suppressed + // and not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ERRIS bit is set. 0 The + // ERRIS interrupt is suppressed and + // not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_INVDMASK \ + 0x00000400 // Invalid Data Interrupt Mask + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the INVDRIS bit + // is set. 0 The INVDRIS interrupt + // is suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_VOLTMASK \ + 0x00000200 // VOLT Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the VOLTRIS bit is set. 0 + // The VOLTRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_LOCKMASK \ + 0x00000100 // LOCK Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the LOCKRIS bit is set. 0 + // The LOCKRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ERIS bit is set. 0 The + // ERIS interrupt is suppressed and + // not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This + // bit controls the reporting of the + // programming raw interrupt status + // to the interrupt controller. + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the PRIS bit is + // set. 0 The PRIS interrupt is + // suppressed and not sent to the + // interrupt controller. +#define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit + // controls the reporting of the + // access raw interrupt status to + // the interrupt controller. Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ARIS bit is set. 0 The + // ARIS interrupt is suppressed and + // not sent to the interrupt + // controller. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FCMISC register. +// +//****************************************************************************** +#define FLASH_CTRL_FCMISC_ILLMISC \ + 0x00004000 // Illegal Address Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled. Writing a + // 1 to this bit clears ILLAMISC and + // also the ILLARIS bit in the FCRIS + // register (see page 540). 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_PROGMISC \ + 0x00002000 // PROGVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // PROGMISC and also the PROGRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_PREMISC \ + 0x00001000 // PREVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // PREMISC and also the PRERIS bit + // in the FCRIS register . 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_ERMISC \ + 0x00000800 // ERVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // ERMISC and also the ERRIS bit in + // the FCRIS register 0 When read a + // 0 indicates that an interrupt has + // not occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_INVDMISC \ + 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled. Writing a + // 1 to this bit clears INVDMISC and + // also the INVDRIS bit in the FCRIS + // register (see page 540). 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_VOLTMISC \ + 0x00000200 // VOLT Masked Interrupt Status and + // Clear Value Description 1 When + // read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // VOLTMISC and also the VOLTRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_LOCKMISC \ + 0x00000100 // LOCK Masked Interrupt Status and + // Clear Value Description 1 When + // read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // LOCKMISC and also the LOCKRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // EMISC and also the ERIS bit in + // the FCRIS register 0 When read a + // 0 indicates that an interrupt has + // not occurred. A write of 0 has no + // effect on the state of this bit. +#define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled because a + // programming cycle completed. + // Writing a 1 to this bit clears + // PMISC and also the PRIS bit in + // the FCRIS register 0 When read a + // 0 indicates that a programming + // cycle complete interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. +#define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled + // because a program or erase action + // was attempted on a block of Flash + // memory that contradicts the + // protection policy for that block + // as set in the FMPPEn registers. + // Writing a 1 to this bit clears + // AMISC and also the ARIS bit in + // the FCRIS register 0 When read a + // 0 indicates that no improper + // accesses have occurred. A write + // of 0 has no effect on the state + // of this bit. +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register. +// +//****************************************************************************** +#define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This + // field contains a write key which + // is used to minimize the incidence + // of accidental Flash memory + // writes. The value 0xA442 must be + // written into this field for a + // write to occur. Writes to the + // FMC2 register without this WRKEY + // value are ignored. A read of this + // field returns the value 0. +#define FLASH_CTRL_FMC2_WRKEY_S 16 +#define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This + // bit is used to start a buffered + // write to Flash memory. Value + // Description 1 Set this bit to + // write the data stored in the FWBn + // registers to the location + // specified by the contents of the + // FMA register. When read a 1 + // indicates that the previous + // buffered Flash memory write + // access is not complete. 0 A write + // of 0 has no effect on the state + // of this bit. When read a 0 + // indicates that the previous + // buffered Flash memory write + // access is complete. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWBVAL register. +// +//****************************************************************************** +#define FLASH_CTRL_FWBVAL_FWBN_M \ + 0xFFFFFFFF // Flash Memory Write Buffer Value + // Description 1 The corresponding + // FWBn register has been updated + // since the last buffer write + // operation and is ready to be + // written to Flash memory. 0 The + // corresponding FWBn register has + // no new data to be written. Bit 0 + // corresponds to FWB0 offset 0x100 + // and bit 31 corresponds to FWB31 + // offset 0x13C. + +#define FLASH_CTRL_FWBVAL_FWBN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB4_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB5_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB6_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB7_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB8_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB9_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB10 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB10_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB11 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB11_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB12 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB12_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB13 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB13_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB14 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB14_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB15 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB15_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB16 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB16_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB17 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB17_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB18 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB18_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB19 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB19_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB20 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB20_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB21 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB21_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB22 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB22_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB23 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB23_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB24 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB24_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB25 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB25_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB26 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB26_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB27 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB27_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB28 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB28_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB29 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB29_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB30 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB30_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB31 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB31_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB32 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB32_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FSIZE register. +// +//****************************************************************************** +#define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of + // the on-chip Flash memory. Value + // Description 0x0003 8 KB of Flash + // 0x0007 16 KB of Flash 0x000F 32 + // KB of Flash 0x001F 64 KB of Flash + // 0x002F 96 KB of Flash 0x003F 128 + // KB of Flash 0x005F 192 KB of + // Flash 0x007F 256 KB of Flash +#define FLASH_CTRL_FSIZE_SIZE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_SSIZE register. +// +//****************************************************************************** +#define FLASH_CTRL_SSIZE_SRAM_SIZE_M \ + 0x0000FFFF // SRAM Size Indicates the size of + // the on-chip SRAM. Value + // Description 0x0007 2 KB of SRAM + // 0x000F 4 KB of SRAM 0x0017 6 KB + // of SRAM 0x001F 8 KB of SRAM + // 0x002F 12 KB of SRAM 0x003F 16 KB + // of SRAM 0x004F 20 KB of SRAM + // 0x005F 24 KB of SRAM 0x007F 32 KB + // of SRAM + +#define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0 +#define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key +#define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1 +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read + // Enable 0 +#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read + // Enable 1 +#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read + // Enable 2 +#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read + // Enable 3 +#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read + // Enable 4 +#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read + // Enable 5 +#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read + // Enable 6 +#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read + // Enable 7 +#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read + // Enable 8 +#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read + // Enable 9 +#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read + // Enable 10 +#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read + // Enable 11 +#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read + // Enable 12 +#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read + // Enable 13 +#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read + // Enable 14 +#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read + // Enable 15 + +#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program + // Enable 0 +#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program + // Enable 1 +#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program + // Enable 2 +#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program + // Enable 3 +#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program + // Enable 4 +#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program + // Enable 5 +#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program + // Enable 6 +#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program + // Enable 7 +#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program + // Enable 8 +#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program + // Enable 9 +#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program + // Enable 10 +#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program + // Enable 11 +#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program + // Enable 12 +#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program + // Enable 13 +#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program + // Enable 14 +#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program + // Enable 15 + +#define FLASH_USECRL 0x400FE140 // USec Reload +#define FLASH_CTRL_ERASE_SIZE 0x00000400 + + +#endif // __HW_FLASH_CTRL_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gpio.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gpio.h new file mode 100755 index 00000000000..118e24704d5 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gpio.h @@ -0,0 +1,1347 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets. +// +//***************************************************************************** +#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000 + // 7000 0x4002 4000 GPIO Data + // (GPIODATA)@@ offset 0x000 The + // GPIODATA register is the data + // register. In software control + // mode@@ values written in the + // GPIODATA register are transferred + // onto the GPIO port pins if the + // respective pins have been + // configured as outputs through the + // GPIO Direction (GPIODIR) register + // (see page 653). In order to write + // to GPIODATA@@ the corresponding + // bits in the mask@@ resulting from + // the address bus bits [9:2]@@ must + // be set. Otherwise@@ the bit + // values remain unchanged by the + // write. Similarly@@ the values + // read from this register are + // determined for each bit by the + // mask bit derived from the address + // used to access the data + // register@@ bits [9:2]. Bits that + // are set in the address mask cause + // the corresponding bits in + // GPIODATA to be read@@ and bits + // that are clear in the address + // mask cause the corresponding bits + // in GPIODATA to be read as 0@@ + // regardless of their value. A read + // from GPIODATA returns the last + // bit value written if the + // respective pins are configured as + // outputs@@ or it returns the value + // on the corresponding input pin + // when these are configured as + // inputs. All bits are cleared by a + // reset. +#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000 + // 7400 0x4002 4400 GPIO Direction + // (GPIODIR)@@ offset 0x400 The + // GPIODIR register is the data + // direction register. Setting a bit + // in the GPIODIR register + // configures the corresponding pin + // to be an output@@ while clearing + // a bit configures the + // corresponding pin to be an input. + // All bits are cleared by a reset@@ + // meaning all GPIO pins are inputs + // by default. +#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000 + // 7404 0x4002 4404 GPIO Interrupt + // Sense (GPIOIS)@@ offset 0x404 The + // GPIOIS register is the interrupt + // sense register. Setting a bit in + // the GPIOIS register configures + // the corresponding pin to detect + // levels@@ while clearing a bit + // configures the corresponding pin + // to detect edges. All bits are + // cleared by a reset. +#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000 + // 7408 0x4002 4408 GPIO Interrupt + // Both Edges (GPIOIBE)@@ offset + // 0x408 The GPIOIBE register allows + // both edges to cause interrupts. + // When the corresponding bit in the + // GPIO Interrupt Sense (GPIOIS) + // register is set to detect edges@@ + // setting a bit in the GPIOIBE + // register configures the + // corresponding pin to detect both + // rising and falling edges@@ + // regardless of the corresponding + // bit in the GPIO Interrupt Event + // (GPIOIEV) register . Clearing a + // bit configures the pin to be + // controlled by the GPIOIEV + // register. All bits are cleared by + // a reset. +#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000 + // 740C 0x4002 440C GPIO Interrupt + // Event (GPIOIEV)@@ offset 0x40C + // The GPIOIEV register is the + // interrupt event register. Setting + // a bit in the GPIOIEV register + // configures the corresponding pin + // to detect rising edges or high + // levels@@ depending on the + // corresponding bit value in the + // GPIO Interrupt Sense (GPIOIS) + // register . Clearing a bit + // configures the pin to detect + // falling edges or low levels@@ + // depending on the corresponding + // bit value in the GPIOIS register. + // All bits are cleared by a reset. +#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000 + // 7410 0x4002 4410 GPIO Interrupt + // Mask (GPIOIM)@@ offset 0x410 The + // GPIOIM register is the interrupt + // mask register. Setting a bit in + // the GPIOIM register allows + // interrupts that are generated by + // the corresponding pin to be sent + // to the interrupt controller on + // the combined interrupt signal. + // Clearing a bit prevents an + // interrupt on the corresponding + // pin from being sent to the + // interrupt controller. All bits + // are cleared by a reset. +#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000 + // 7414 0x4002 4414 GPIO Raw + // Interrupt Status (GPIORIS)@@ + // offset 0x414 The GPIORIS register + // is the raw interrupt status + // register. A bit in this register + // is set when an interrupt + // condition occurs on the + // corresponding GPIO pin. If the + // corresponding bit in the GPIO + // Interrupt Mask (GPIOIM) register + // is set@@ the interrupt is sent to + // the interrupt controller. Bits + // read as zero indicate that + // corresponding input pins have not + // initiated an interrupt. A bit in + // this register can be cleared by + // writing a 1 to the corresponding + // bit in the GPIO Interrupt Clear + // (GPIOICR) register. +#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000 + // 7418 0x4002 4418 GPIO Masked + // Interrupt Status (GPIOMIS)@@ + // offset 0x418 The GPIOMIS register + // is the masked interrupt status + // register. If a bit is set in this + // register@@ the corresponding + // interrupt has triggered an + // interrupt to the interrupt + // controller. If a bit is clear@@ + // either no interrupt has been + // generated@@ or the interrupt is + // masked. If no port pin@@ other + // than the one that is being used + // as an ADC trigger@@ is being used + // to generate interrupts@@ the + // appropriate Interrupt Set Enable + // (ENn) register can disable the + // interrupts for the port@@ and the + // ADC interrupt can be used to read + // back the converted data. + // Otherwise@@ the port interrupt + // handler must ignore and clear + // interrupts on the port pin and + // wait for the ADC interrupt@@ or + // the ADC interrupt must be + // disabled in the EN0 register and + // the port interrupt handler must + // poll the ADC registers until the + // conversion is completed. If no + // port pin@@ other than the one + // that is being used as an ADC + // trigger@@ is being used to + // generate interrupts@@ the + // appropriate Interrupt Set Enable + // (ENn) register can disable the + // interrupts for the port@@ and the + // ADC interrupt can be used to read + // back the converted data. + // Otherwise@@ the port interrupt + // handler must ignore and clear + // interrupts on the port pin and + // wait for the ADC interrupt@@ or + // the ADC interrupt must be + // disabled in the EN0 register and + // the port interrupt handler must + // poll the ADC registers until the + // conversion is completed. Note + // that if the Port B GPIOADCCTL + // register is cleared@@ PB4 can + // still be used as an external + // trigger for the ADC. This is a + // legacy mode which allows code + // written for previous Stellaris + // devices to operate on this + // microcontroller. GPIOMIS is the + // state of the interrupt after + // masking. +#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000 + // 741C 0x4002 441C GPIO Interrupt + // Clear (GPIOICR)@@ offset 0x41C + // The GPIOICR register is the + // interrupt clear register. Writing + // a 1 to a bit in this register + // clears the corresponding + // interrupt bit in the GPIORIS and + // GPIOMIS registers. Writing a 0 + // has no effect. +#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000 + // 7420 0x4002 4420 GPIO Alternate + // Function Select (GPIOAFSEL)@@ + // offset 0x420 The GPIOAFSEL + // register is the mode control + // select register. If a bit is + // clear@@ the pin is used as a GPIO + // and is controlled by the GPIO + // registers. Setting a bit in this + // register configures the + // corresponding GPIO line to be + // controlled by an associated + // peripheral. Several possible + // peripheral functions are + // multiplexed on each GPIO. The + // GPIO Port Control (GPIOPCTL) + // register is used to select one of + // the possible functions. +#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000 + // 7500 0x4002 4500 GPIO 2-mA Drive + // Select (GPIODR2R)@@ offset 0x500 + // The GPIODR2R register is the 2-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV2 bit for a GPIO + // signal@@ the corresponding DRV4 + // bit in the GPIODR4R register and + // DRV8 bit in the GPIODR8R register + // are automatically cleared by + // hardware. By default@@ all GPIO + // pins have 2-mA drive. +#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000 + // 7504 0x4002 4504 GPIO 4-mA Drive + // Select (GPIODR4R)@@ offset 0x504 + // The GPIODR4R register is the 4-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV4 bit for a GPIO + // signal@@ the corresponding DRV2 + // bit in the GPIODR2R register and + // DRV8 bit in the GPIODR8R register + // are automatically cleared by + // hardware. +#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000 + // 7508 0x4002 4508 GPIO 8-mA Drive + // Select (GPIODR8R)@@ offset 0x508 + // The GPIODR8R register is the 8-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV8 bit for a GPIO + // signal@@ the corresponding DRV2 + // bit in the GPIODR2R register and + // DRV4 bit in the GPIODR4R register + // are automatically cleared by + // hardware. The 8-mA setting is + // also used for high-current + // operation. Note: There is no + // configuration difference between + // 8-mA and high-current operation. + // The additional current capacity + // results from a shift in the + // VOH/VOL levels. +#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000 + // 750C 0x4002 450C GPIO Open Drain + // Select (GPIOODR)@@ offset 0x50C + // The GPIOODR register is the open + // drain control register. Setting a + // bit in this register enables the + // open-drain configuration of the + // corresponding GPIO pad. When + // open-drain mode is enabled@@ the + // corresponding bit should also be + // set in the GPIO Digital Input + // Enable (GPIODEN) register . + // Corresponding bits in the drive + // strength and slew rate control + // registers (GPIODR2R@@ GPIODR4R@@ + // GPIODR8R@@ and GPIOSLR) can be + // set to achieve the desired rise + // and fall times. The GPIO acts as + // an open-drain input if the + // corresponding bit in the GPIODIR + // register is cleared. If open + // drain is selected while the GPIO + // is configured as an input@@ the + // GPIO will remain an input and the + // open-drain selection has no + // effect until the GPIO is changed + // to an output. When using the I2C + // module@@ in addition to + // configuring the pin to open + // drain@@ the GPIO Alternate + // Function Select (GPIOAFSEL) + // register bits for the I2C clock + // and data pins should be set +#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000 + // 7510 0x4002 4510 GPIO Pull-Up + // Select (GPIOPUR)@@ offset 0x510 + // The GPIOPUR register is the + // pull-up control register. When a + // bit is set@@ a weak pull-up + // resistor on the corresponding + // GPIO signal is enabled. Setting a + // bit in GPIOPUR automatically + // clears the corresponding bit in + // the GPIO Pull-Down Select + // (GPIOPDR) register . Write access + // to this register is protected + // with the GPIOCR register. Bits in + // GPIOCR that are cleared prevent + // writes to the equivalent bit in + // this register. +#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000 + // 7514 0x4002 4514 GPIO Pull-Down + // Select (GPIOPDR)@@ offset 0x514 + // The GPIOPDR register is the + // pull-down control register. When + // a bit is set@@ a weak pull-down + // resistor on the corresponding + // GPIO signal is enabled. Setting a + // bit in GPIOPDR automatically + // clears the corresponding bit in + // the GPIO Pull-Up Select (GPIOPUR) + // register +#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000 + // 7518 0x4002 4518 The GPIOSLR + // register is the slew rate control + // register. Slew rate control is + // only available when using the + // 8-mA drive strength option via + // the GPIO 8-mA Drive Select + // (GPIODR8R) register +#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000 + // 751C 0x4002 451C GPIO Digital + // Enable (GPIODEN)@@ offset 0x51C + // Note: Pins configured as digital + // inputs are Schmitt-triggered. The + // GPIODEN register is the digital + // enable register. By default@@ all + // GPIO signals except those listed + // below are configured out of reset + // to be undriven (tristate). Their + // digital function is disabled; + // they do not drive a logic value + // on the pin and they do not allow + // the pin voltage into the GPIO + // receiver. To use the pin as a + // digital input or output (either + // GPIO or alternate function)@@ the + // corresponding GPIODEN bit must be + // set. +#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000 + // 7520 0x4002 4520 GPIO Lock + // (GPIOLOCK)@@ offset 0x520 The + // GPIOLOCK register enables write + // access to the GPIOCR register . + // Writing 0x4C4F.434B to the + // GPIOLOCK register unlocks the + // GPIOCR register. Writing any + // other value to the GPIOLOCK + // register re-enables the locked + // state. Reading the GPIOLOCK + // register returns the lock status + // rather than the 32-bit value that + // was previously written. + // Therefore@@ when write accesses + // are disabled@@ or locked@@ + // reading the GPIOLOCK register + // returns 0x0000.0001. When write + // accesses are enabled@@ or + // unlocked@@ reading the GPIOLOCK + // register returns 0x0000.0000. +#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000 + // 7524 0x4002 4524 GPIO Commit + // (GPIOCR)@@ offset 0x524 The + // GPIOCR register is the commit + // register. The value of the GPIOCR + // register determines which bits of + // the GPIOAFSEL@@ GPIOPUR@@ + // GPIOPDR@@ and GPIODEN registers + // are committed when a write to + // these registers is performed. If + // a bit in the GPIOCR register is + // cleared@@ the data being written + // to the corresponding bit in the + // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ + // or GPIODEN registers cannot be + // committed and retains its + // previous value. If a bit in the + // GPIOCR register is set@@ the data + // being written to the + // corresponding bit of the + // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ + // or GPIODEN registers is committed + // to the register and reflects the + // new value. The contents of the + // GPIOCR register can only be + // modified if the status in the + // GPIOLOCK register is unlocked. + // Writes to the GPIOCR register are + // ignored if the status in the + // GPIOLOCK register is locked. +#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000 + // 7528 0x4002 4528 The GPIOAMSEL + // register controls isolation + // circuits to the analog side of a + // unified I/O pad. Because the + // GPIOs may be driven by a 5-V + // source and affect analog + // operation@@ analog circuitry + // requires isolation from the pins + // when they are not used in their + // analog function. Each bit of this + // register controls the isolation + // circuitry for the corresponding + // GPIO signal. +#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) 0x4000 552C + // 0x4000 652C 0x4000 752C 0x4002 + // 452C GPIO Port Control + // (GPIOPCTL)@@ offset 0x52C The + // GPIOPCTL register is used in + // conjunction with the GPIOAFSEL + // register and selects the specific + // peripheral signal for each GPIO + // pin when using the alternate + // function mode. Most bits in the + // GPIOAFSEL register are cleared on + // reset@@ therefore most GPIO pins + // are configured as GPIOs by + // default. When a bit is set in the + // GPIOAFSEL register@@ the + // corresponding GPIO signal is + // controlled by an associated + // peripheral. The GPIOPCTL register + // selects one out of a set of + // peripheral functions for each + // GPIO@@ providing additional + // flexibility in signal definition. +#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in + // cc3xx. ADC trigger via GPIO is + // not supported. 0x4000 5530 0x4000 + // 6530 0x4000 7530 0x4002 4530 GPIO + // ADC Control (GPIOADCCTL)@@ offset + // 0x530 This register is used to + // configure a GPIO pin as a source + // for the ADC trigger. Note that if + // the Port B GPIOADCCTL register is + // cleared@@ PB4 can still be used + // as an external trigger for the + // ADC. This is a legacy mode which + // allows code written for previous + // Stellaris devices to operate on + // this microcontroller. +#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000 + // 7534 0x4002 4534 GPIO DMA Control + // (GPIODMACTL)@@ offset 0x534 This + // register is used to configure a + // GPIO pin as a source for the ?DMA + // trigger. +#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000 + // 7538 0x4002 4538 GPIO Select + // Interrupt (GPIOSI)@@ offset 0x538 + // This register is used to enable + // individual interrupts for each + // pin. Note: This register is only + // available on Port P and Port Q. +#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000 + // 7FD0 0x4002 4FD0 GPIO Peripheral + // Identification 4 + // (GPIOPeriphID4)@@ offset 0xFD0 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000 + // 7FD4 0x4002 4FD4 GPIO Peripheral + // Identification 5 + // (GPIOPeriphID5)@@ offset 0xFD4 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000 + // 7FD8 0x4002 4FD8 GPIO Peripheral + // Identification 6 + // (GPIOPeriphID6)@@ offset 0xFD8 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000 + // 7FDC 0x4002 4FDC GPIO Peripheral + // Identification 7 + // (GPIOPeriphID7)@@ offset 0xFDC + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000 + // 7FE0 0x4002 4FE0 GPIO Peripheral + // Identification 0 + // (GPIOPeriphID0)@@ offset 0xFE0 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000 + // 7FE4 0x4002 4FE4 GPIO Peripheral + // Identification 1 + // (GPIOPeriphID1)@@ offset 0xFE4 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000 + // 7FE8 0x4002 4FE8 GPIO Peripheral + // Identification 2 + // (GPIOPeriphID2)@@ offset 0xFE8 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000 + // 7FEC 0x4002 4FEC GPIO Peripheral + // Identification 3 + // (GPIOPeriphID3)@@ offset 0xFEC + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000 + // 7FF0 0x4002 4FF0 GPIO PrimeCell + // Identification 0 (GPIOPCellID0)@@ + // offset 0xFF0 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000 + // 7FF4 0x4002 4FF4 GPIO PrimeCell + // Identification 1 (GPIOPCellID1)@@ + // offset 0xFF4 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000 + // 7FF8 0x4002 4FF8 GPIO PrimeCell + // Identification 2 (GPIOPCellID2)@@ + // offset 0xFF8 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000 + // 7FFC 0x4002 4FFC GPIO PrimeCell + // Identification 3 (GPIOPCellID3)@@ + // offset 0xFFC The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system.0xb1 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register. +// +//****************************************************************************** +#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is + // virtually mapped to 256 locations + // in the address space. To + // facilitate the reading and + // writing of data to these + // registers by independent + // drivers@@ the data read from and + // written to the registers are + // masked by the eight address lines + // [9:2]. Reads from this register + // return its current state. Writes + // to this register only affect bits + // that are not masked by ADDR[9:2] + // and are configured as outputs. +#define GPIO_GPIO_DATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register. +// +//****************************************************************************** +#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value + // Description 0 Corresponding pin + // is an input. 1 Corresponding pins + // is an output. +#define GPIO_GPIO_DIR_DIR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IS register. +// +//****************************************************************************** +#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value + // Description 0 The edge on the + // corresponding pin is detected + // (edge-sensitive). 1 The level on + // the corresponding pin is detected + // (level-sensitive). +#define GPIO_GPIO_IS_IS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register. +// +//****************************************************************************** +#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value + // Description 0 Interrupt + // generation is controlled by the + // GPIO Interrupt Event (GPIOIEV) + // register. 1 Both edges on the + // corresponding pin trigger an + // interrupt. +#define GPIO_GPIO_IBE_IBE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register. +// +//****************************************************************************** +#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value + // Description 1 A falling edge or a + // Low level on the corresponding + // pin triggers an interrupt. 0 A + // rising edge or a High level on + // the corresponding pin triggers an + // interrupt. +#define GPIO_GPIO_IEV_IEV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IM register. +// +//****************************************************************************** +#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value + // Description 0 The interrupt from + // the corresponding pin is masked. + // 1 The interrupt from the + // corresponding pin is sent to the + // interrupt controller. +#define GPIO_GPIO_IM_IME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register. +// +//****************************************************************************** +#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value + // Description 1 An interrupt + // condition has occurred on the + // corresponding pin. 0 interrupt + // condition has not occurred on the + // corresponding pin. A bit is + // cleared by writing a 1 to the + // corresponding bit in the GPIOICR + // register. +#define GPIO_GPIO_RIS_RIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register. +// +//****************************************************************************** +#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status + // Value Description 1 An interrupt + // condition on the corresponding + // pin has triggered an interrupt to + // the interrupt controller. 0 An + // interrupt condition on the + // corresponding pin is masked or + // has not occurred. A bit is + // cleared by writing a 1 to the + // corresponding bit in the GPIOICR + // register. +#define GPIO_GPIO_MIS_MIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register. +// +//****************************************************************************** +#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value + // Description 1 The corresponding + // interrupt is cleared. 0 The + // corresponding interrupt is + // unaffected. +#define GPIO_GPIO_ICR_IC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 2-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 2-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR4R + // or GPIODR8R register. 0 Setting a + // bit in either the GPIODR4 + // register or the GPIODR8 register + // clears the corresponding 2-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR2R_DRV2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 4-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 4-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR2R + // or GPIODR8R register. 0 Setting a + // bit in either the GPIODR2 + // register or the GPIODR8 register + // clears the corresponding 4-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR4R_DRV4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 8-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 8-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR2R + // or GPIODR4R register. 0 Setting a + // bit in either the GPIODR2 + // register or the GPIODR4 register + // clears the corresponding 8-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR8R_DRV8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register. +// +//****************************************************************************** +#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // Open Drain Enable Value + // Description 1 The corresponding + // pin is configured as open drain. + // 0 The corresponding pin is not + // configured as open drain. +#define GPIO_GPIO_ODR_ODE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register. +// +//****************************************************************************** +#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Pad Weak + // Pull-Up Enable Value Description + // 1 The corresponding pin has a + // weak pull-up resistor. 0 The + // corresponding pin is not + // affected. Setting a bit in the + // GPIOPDR register clears the + // corresponding bit in the GPIOPUR + // register. The change is effective + // on the second clock cycle after + // the write if accessing GPIO via + // the APB memory aperture. If using + // AHB access@@ the change is + // effective on the next clock + // cycle. +#define GPIO_GPIO_PUR_PUE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register. +// +//****************************************************************************** +#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Pad Weak + // Pull-Down Enable Value + // Description 1 The corresponding + // pin has a weak pull-down + // resistor. 0 The corresponding pin + // is not affected. Setting a bit in + // the GPIOPUR register clears the + // corresponding bit in the GPIOPDR + // register. The change is effective + // on the second clock cycle after + // the write if accessing GPIO via + // the APB memory aperture. If using + // AHB access@@ the change is + // effective on the next clock + // cycle. +#define GPIO_GPIO_PDR_PDE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register. +// +//****************************************************************************** +#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Slew Rate + // Limit Enable (8-mA drive only) + // Value Description 1 Slew rate + // control is enabled for the + // corresponding pin. 0 Slew rate + // control is disabled for the + // corresponding pin. +#define GPIO_GPIO_SLR_SRL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register. +// +//****************************************************************************** +#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Digital Enable + // Value Description 0 The digital + // functions for the corresponding + // pin are disabled. 1 The digital + // functions for the corresponding + // pin are enabled. +#define GPIO_GPIO_DEN_DEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register. +// +//****************************************************************************** +#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in + // cc3xx. GPIO Lock A write of the + // value 0x4C4F.434B unlocks the + // GPIO Commit (GPIOCR) register for + // write access.A write of any other + // value or a write to the GPIOCR + // register reapplies the lock@@ + // preventing any register updates. + // A read of this register returns + // the following values: Value + // Description 0x1 The GPIOCR + // register is locked and may not be + // modified. 0x0 The GPIOCR register + // is unlocked and may be modified. +#define GPIO_GPIO_LOCK_LOCK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_CR register. +// +//****************************************************************************** +#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) GPIO Commit + // Value Description The + // corresponding GPIOAFSEL@@ + // GPIOPUR@@ GPIOPDR@@ or GPIODEN + // bits can be written. 1 The + // corresponding GPIOAFSEL@@ + // GPIOPUR@@ GPIOPDR@@ or GPIODEN + // bits cannot be written. 0 Note: + // The default register type for the + // GPIOCR register is RO for all + // GPIO pins with the exception of + // the NMI pin and the four JTAG/SWD + // pins (PD7@@ PF0@@ and PC[3:0]). + // These six pins are the only GPIOs + // that are protected by the GPIOCR + // register. Because of this@@ the + // register type for GPIO Port D7@@ + // GPIO Port F0@@ and GPIO Port + // C[3:0] is R/W. The default reset + // value for the GPIOCR register is + // 0x0000.00FF for all GPIO pins@@ + // with the exception of the NMI pin + // and the four JTAG/SWD pins (PD7@@ + // PF0@@ and PC[3:0]). To ensure + // that the JTAG port is not + // accidentally programmed as GPIO + // pins@@ the PC[3:0] pins default + // to non-committable. Similarly@@ + // to ensure that the NMI pin is not + // accidentally programmed as a GPIO + // pin@@ the PD7 and PF0 pins + // default to non-committable. + // Because of this@@ the default + // reset value of GPIOCR for GPIO + // Port C is 0x0000.00F0@@ for GPIO + // Port D is 0x0000.007F@@ and for + // GPIO Port F is 0x0000.00FE. +#define GPIO_GPIO_CR_CR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register. +// +//****************************************************************************** +#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \ + 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) GPIO Analog + // Mode Select Value Description 1 + // The analog function of the pin is + // enabled@@ the isolation is + // disabled@@ and the pin is capable + // of analog functions. 0 The analog + // function of the pin is disabled@@ + // the isolation is enabled@@ and + // the pin is capable of digital + // functions as specified by the + // other GPIO configuration + // registers. Note: This register + // and bits are only valid for GPIO + // signals that share analog + // function through a unified I/O + // pad. The reset state of this + // register is 0 for all signals. + +#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register. +// +//****************************************************************************** +#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 7 This field controls the + // configuration for GPIO pin 7. +#define GPIO_GPIO_PCTL_PMC7_S 28 +#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 6 This field controls the + // configuration for GPIO pin 6. +#define GPIO_GPIO_PCTL_PMC6_S 24 +#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 5 This field controls the + // configuration for GPIO pin 5. +#define GPIO_GPIO_PCTL_PMC5_S 20 +#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 4 This field controls the + // configuration for GPIO pin 4. +#define GPIO_GPIO_PCTL_PMC4_S 16 +#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 43 This field controls + // the configuration for GPIO pin 3. +#define GPIO_GPIO_PCTL_PMC3_S 12 +#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 1 This field controls the + // configuration for GPIO pin 1. +#define GPIO_GPIO_PCTL_PMC1_S 8 +#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 2 This field controls the + // configuration for GPIO pin 2. +#define GPIO_GPIO_PCTL_PMC2_S 4 +#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 0 This field controls the + // configuration for GPIO pin 0. +#define GPIO_GPIO_PCTL_PMC0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_ADCCTL register. +// +//****************************************************************************** +#define GPIO_GPIO_ADCCTL_ADCEN_M \ + 0x000000FF // This register is not used in + // cc3xx. ADC trigger via GPIO is + // not supported. ADC Trigger Enable + // Value Description 1 The + // corresponding pin is used to + // trigger the ADC. 0 The + // corresponding pin is not used to + // trigger the ADC. + +#define GPIO_GPIO_ADCCTL_ADCEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_DMACTL register. +// +//****************************************************************************** +#define GPIO_GPIO_DMACTL_DMAEN_M \ + 0x000000FF // This register is not used in the + // cc3xx. Alternate register to + // support this feature is coded in + // the APPS_NWP_CMN space. refer + // register as offset 0x400F70D8 + // ?DMA Trigger Enable Value + // Description 1 The corresponding + // pin is used to trigger the ?DMA. + // 0 The corresponding pin is not + // used to trigger the ?DMA. + +#define GPIO_GPIO_DMACTL_DMAEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_SI register. +// +//****************************************************************************** +#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value + // Description 1 Each pin has its + // own interrupt vector. 0 All port + // pin interrupts are OR'ed together + // to produce a summary interrupt. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID4 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID4_PID4_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [7:0] + +#define GPIO_GPIO_PERIPHID4_PID4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID5 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID5_PID5_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [15:8] + +#define GPIO_GPIO_PERIPHID5_PID5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID6 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID6_PID6_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [23:16] + +#define GPIO_GPIO_PERIPHID6_PID6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID7 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID7_PID7_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [31:24] + +#define GPIO_GPIO_PERIPHID7_PID7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID0 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID0_PID0_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [7:0] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID0_PID0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID1 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID1_PID1_M \ + 0x000000FF // GPIO Peripheral ID Register + // [15:8] Can be used by software to + // identify the presence of this + // peripheral. + +#define GPIO_GPIO_PERIPHID1_PID1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID2 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID2_PID2_M \ + 0x000000FF // This register is not used in + // CC3XX.v GPIO Peripheral ID + // Register [23:16] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID2_PID2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID3 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID3_PID3_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [31:24] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID3_PID3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID0 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID0_CID0_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [7:0] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID0_CID0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID1 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID1_CID1_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [15:8] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID1_CID1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID2 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID2_CID2_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [23:16] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID2_CID2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID3 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID3_CID3_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [31:24] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID3_CID3_S 0 + + + +#endif // __HW_GPIO_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gprcm.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gprcm.h new file mode 100755 index 00000000000..72b99d6d511 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_gprcm.h @@ -0,0 +1,3320 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_GPRCM_H__ +#define __HW_GPRCM_H__ + +//***************************************************************************** +// +// The following are defines for the GPRCM register offsets. +// +//***************************************************************************** +#define GPRCM_O_APPS_SOFT_RESET 0x00000000 +#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \ + 0x00000004 + +#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \ + 0x00000008 + +#define GPRCM_O_APPS_RESET_CAUSE \ + 0x0000000C + +#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \ + 0x00000010 + +#define GPRCM_O_APPS_SRAM_DSLP_CFG \ + 0x00000018 + +#define GPRCM_O_APPS_SRAM_LPDS_CFG \ + 0x0000001C + +#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \ + 0x00000020 + +#define GPRCM_O_TOP_DIE_ENABLE 0x00000100 +#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \ + 0x00000104 + +#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \ + 0x00000108 + +#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C +#define GPRCM_O_APPS_GPIO_WAKE_CONF \ + 0x00000110 + +#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \ + 0x00000114 + +#define GPRCM_O_MEM_HCLK_DIV_CFG \ + 0x00000118 + +#define GPRCM_O_MEM_SYSCLK_DIV_CFG \ + 0x0000011C + +#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \ + 0x00000120 + +#define GPRCM_O_NWP_SOFT_RESET 0x00000400 +#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \ + 0x00000404 + +#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \ + 0x00000408 + +#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C +#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \ + 0x00000410 + +#define GPRCM_O_NWP_SRAM_DSLP_CFG \ + 0x00000418 + +#define GPRCM_O_NWP_SRAM_LPDS_CFG \ + 0x0000041C + +#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \ + 0x00000420 + +#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \ + 0x00000424 + +#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \ + 0x00000428 + +#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \ + 0x0000042C + +#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \ + 0x00000430 + +#define GPRCM_O_NWP_GPIO_WAKE_CONF \ + 0x00000434 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \ + 0x00000438 + +#define GPRCM_O_GPRCM_DIEID_READ_REG5 \ + 0x00000448 + +#define GPRCM_O_GPRCM_DIEID_READ_REG6 \ + 0x0000044C + +#define GPRCM_O_REF_FSM_CFG0 0x00000800 +#define GPRCM_O_REF_FSM_CFG1 0x00000804 +#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \ + 0x00000808 + +#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \ + 0x0000080C + +#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \ + 0x00000810 + +#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \ + 0x00000814 + +#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \ + 0x00000818 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \ + 0x0000081C + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \ + 0x00000820 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \ + 0x00000824 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \ + 0x00000828 + +#define GPRCM_O_SPARE_RW0 0x0000082C +#define GPRCM_O_SPARE_RW1 0x00000830 +#define GPRCM_O_APLLMCS_MCU_OVERRIDES \ + 0x00000834 + +#define GPRCM_O_SYSCLK_SWITCH_STATUS \ + 0x00000838 + +#define GPRCM_O_REF_LDO_CONTROLS \ + 0x0000083C + +#define GPRCM_O_REF_RTRIM_CONTROL \ + 0x00000840 + +#define GPRCM_O_REF_SLICER_CONTROLS0 \ + 0x00000844 + +#define GPRCM_O_REF_SLICER_CONTROLS1 \ + 0x00000848 + +#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \ + 0x0000084C + +#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \ + 0x00000850 + +#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \ + 0x00000854 + +#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \ + 0x00000858 + +#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \ + 0x0000085C + +#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \ + 0x00000860 + +#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \ + 0x00000864 + +#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868 +#define GPRCM_O_MEMSS_PWR_PS 0x0000086C +#define GPRCM_O_REF_FSM_DEBUG 0x00000870 +#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \ + 0x00000874 + +#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \ + 0x00000878 + +#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \ + 0x0000087C + +#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \ + 0x00000880 + +#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \ + 0x00000884 + +#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \ + 0x00000888 + +#define GPRCM_O_MEM_REF_FSM_CFG2 \ + 0x0000088C + +#define GPRCM_O_TESTCTRL_POWER_CTRL \ + 0x00000C10 + +#define GPRCM_O_SSDIO_POWER_CTRL \ + 0x00000C14 + +#define GPRCM_O_MCSPI_N1_POWER_CTRL \ + 0x00000C18 + +#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C +#define GPRCM_O_WL_SDIO_POWER_CTRL \ + 0x00000C20 + +#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \ + 0x00000C24 + +#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \ + 0x00000C28 + +#define GPRCM_O_APPS_SECURE_INIT_DONE \ + 0x00000C30 + +#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \ + 0x00000C34 + +#define GPRCM_O_EN_APPS_REBOOT 0x00000C38 +#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \ + 0x00000C3C + +#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \ + 0x00000C40 + +#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \ + 0x00000C44 + +#define GPRCM_O_NWP_PWR_STATE 0x00000C48 +#define GPRCM_O_APPS_PWR_STATE 0x00000C4C +#define GPRCM_O_MCU_PWR_STATE 0x00000C50 +#define GPRCM_O_WTOP_PM_PS 0x00000C54 +#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \ + 0x00000C58 + +#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \ + 0x00000C5C + +#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \ + 0x00000C60 + +#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \ + 0x00000C64 + +#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \ + 0x00000C68 + +#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \ + 0x00000C6C + +#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \ + 0x00000C70 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \ + 0x00000C78 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \ + 0x00000C7C + +#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \ + 0x00000C80 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \ + 0x00000C84 + +#define GPRCM_O_WTOP_MEM_RET_CFG \ + 0x00000C88 + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \ + 0x00000C8C + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \ + 0x00000C90 + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \ + 0x00000C94 + +#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \ + 0x00000C98 + +#define GPRCM_O_DCDC_CLK_GEN_CONFIG \ + 0x00000C9C + +#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \ + 0x00000CA0 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \ + 0x00000CA4 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \ + 0x00000CA8 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \ + 0x00000CAC + +#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \ + 0x00000CB0 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \ + 0x00000CB4 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \ + 0x00000CB8 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \ + 0x00000CBC + +#define GPRCM_O_GPRCM_DIEID_READ_REG0 \ + 0x00000CC0 + +#define GPRCM_O_GPRCM_DIEID_READ_REG1 \ + 0x00000CC4 + +#define GPRCM_O_GPRCM_DIEID_READ_REG2 \ + 0x00000CC8 + +#define GPRCM_O_GPRCM_DIEID_READ_REG3 \ + 0x00000CCC + +#define GPRCM_O_GPRCM_DIEID_READ_REG4 \ + 0x00000CD0 + +#define GPRCM_O_APPS_SS_OVERRIDES \ + 0x00000CD4 + +#define GPRCM_O_NWP_SS_OVERRIDES \ + 0x00000CD8 + +#define GPRCM_O_SHARED_SS_OVERRIDES \ + 0x00000CDC + +#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \ + 0x00000CE0 + +#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \ + 0x00000CE4 + +#define GPRCM_O_MCU_PSCON_OVERRIDES \ + 0x00000CE8 + +#define GPRCM_O_WTOP_PSCON_OVERRIDES \ + 0x00000CEC + +#define GPRCM_O_WELP_PSCON_OVERRIDES \ + 0x00000CF0 + +#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \ + 0x00000CF4 + +#define GPRCM_O_MCSPI_PSCON_OVERRIDES \ + 0x00000CF8 + +#define GPRCM_O_SSDIO_PSCON_OVERRIDES \ + 0x00000CFC + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \ + 0x00000002 // Soft-reset1 for APPS : Cortex + // sysrstn is asserted and in + // addition to that the associated + // APPS Peripherals are also reset. + // This is an auto-clear bit. + +#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \ + 0x00000001 // Soft-reset0 for APPS : Only + // sys-resetn for Cortex will be + // asserted. This is an auto-clear + // bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKEUP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \ + 0x000000FF // Mask for LPDS Wakeup interrupt : + // [7] - Host IRQ from NWP [6] - + // NWP_LPDS_Wake_irq (TRUE_LPDS) [5] + // - NWP Wake-request to APPS [4] - + // GPIO [3:1] - Reserved [0] - LPDS + // Wakeup-timer + +#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKEUP_SRC register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \ + 0x000000FF // Indicates the cause for wakeup + // from LPDS : [7] - Host IRQ from + // NWP [6] - NWP_LPDS_Wake_irq + // (TRUE_LPDS) [5] - NWP + // Wake-request to APPS [4] - GPIO + // [3:1] - Reserved [0] - LPDS + // Wakeup-timer + +#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_RESET_CAUSE register. +// +//****************************************************************************** +#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \ + 0x000000FF // Indicates the reset cause for + // APPS : "0000" - Wake from HIB/OFF + // mode; "0001" - Wake from LPDS ; + // "0010" - Reserved ; "0011" - + // Soft-reset0 (Only APPS + // Cortex-sysrstn is asserted); + // "0100" - Soft-reset1 (APPS + // Cortex-sysrstn and APPS + // peripherals are reset); "0101" - + // WDOG0 (APPS Cortex-sysrstn and + // APPS peripherals are reset); + // "0110" - MCU Soft-reset (APPS + + // NWP Cortex-sysrstn + Peripherals + // are reset); "0111" - Secure Init + // done (Indication that reset has + // happened after DevInit); "1000" - + // Dev Mode Patch Init done (During + // development mode, patch + // downloading and Cortex + // re-vectoring is completed) + +#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \ + 0xFFFFFFFF // OPP Request Configuration + // (Number of slow-clk cycles) for + // LPDS Wake-timer : This + // configuration implies the RTC + // time-stamp, which must be few + // slow-clks prior to + // APPS_LPDS_WAKETIME_WAKE_CFG, such + // that by the time actual wakeup is + // given, OPP is already switched to + // ACTIVE (RUN). + +#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SRAM_DSLP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \ + 0x000FFFFF // Configuration of APPS Memories + // during Deep-sleep : 0 - SRAMs are + // OFF ; 1 - SRAMs are Retained. + // APPS SRAM Cluster information : + // [0] - 1st column in MEMSS + // (Applicable only when owned by + // APPS); [1] - 2nd column in MEMSS + // (Applicable only when owned by + // APPS); [2] - 3rd column in MEMSS + // (Applicable only when owned by + // APPS) ; [3] - 4th column in MEMSS + // (Applicable only when owned by + // APPS) ; [16] - MCU-PD - Apps + // cluster 0 (TBD); [19:18] - + // Reserved. + +#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SRAM_LPDS_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \ + 0x000FFFFF // Configuration of APPS Memories + // during LPDS : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. APPS SRAM + // Cluster information : [0] - 1st + // column in MEMSS (Applicable only + // when owned by APPS); [1] - 2nd + // column in MEMSS (Applicable only + // when owned by APPS); [2] - 3rd + // column in MEMSS (Applicable only + // when owned by APPS) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by APPS) ; [16] - + // MCU-PD - Apps cluster 0 (TBD); + // [19:18] - Reserved. + +#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \ + 0xFFFFFFFF // Configuration (in no of + // slow_clks) which says when the + // actual wakeup request for + // removing the PD-reset be given. + +#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_ENABLE register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \ + 0x00001000 + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \ + 0x00000F00 + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8 +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \ + 0x00000002 // 1 - Top-die is enabled ; + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \ + 0x00000001 // 1 - Enable the top-die ; 0 - + // Disable the top-die + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \ + 0xF0000000 // Configuration (in slow_clks) for + // number of clks between + // Flash-3p3-rstn to D2D POR Resetn. + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28 +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \ + 0x00FF0000 // Configuration (in slow_clks) for + // number of clks between Top-die + // Switch-Enable and Top-die Flash + // 3p3 Reset removal + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16 +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \ + 0x000000FF // Configuration (in slow_clks) for + // number of clks between D2D POR + // Reset removal and bottom die FMC + // reset removal + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_GLOBAL_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \ + 0x00000001 // 1 - Assert the global reset for + // MCU (APPS + NWP) ; Asserts both + // Cortex sysrstn and its + // peripherals 0 - Deassert the + // global reset for MCU (APPS + NWP) + // ; Asserts both Cortex sysrstn and + // its peripherals Note : Reset for + // shared peripherals is not + // affected here. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_ADC_CLK_CONFIG register. +// +//****************************************************************************** +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \ + 0x000007C0 // Configuration (in number of 38.4 + // MHz clks) for the OFF-Time in + // generation of ADC_CLK + +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6 +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \ + 0x0000003E // Configuration (in number of 38.4 + // MHz clks) for the ON-Time in + // generation of ADC_CLK + +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1 +#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \ + 0x00000001 // 1 - Enable the ADC_CLK ; 0 - + // Disable the ADC_CLK + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \ + 0x00000003 // "00" - Wake on Level0 on + // selected GPIO pin (GPIO is + // selected inside the HIB3p3 + // module); "01" - Wakeup on + // fall-edge of GPIO pin. + +#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register. +// +//****************************************************************************** +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \ + 0xFFFFFFFE + +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1 +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \ + 0x00000001 // 1 - Override the secure-mode + // done for booting up NWP (Wakeup + // NWP on its event independent of + // CM4 state) ; 0 - Donot override + // the secure-mode done for NWP boot + // (NWP must be enabled by CM4 only) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_HCLK_DIV_CFG register. +// +//****************************************************************************** +#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \ + 0x00000007 // Division configuration for + // HCLKDIVOUT : "000" - Divide by 1 + // ; "001" - Divide by 2 ; "010" - + // Divide by 3 ; "011" - Divide by 4 + // ; "100" - Divide by 5 ; "101" - + // Divide by 6 ; "110" - Divide by 7 + // ; "111" - Divide by 8 + +#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SYSCLK_DIV_CFG register. +// +//****************************************************************************** +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \ + 0x00000038 + +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3 +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \ + 0x00000007 + +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_LOCK_TIME_CONF register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \ + 0x0000FF00 + +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8 +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \ + 0x000000FF + +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \ + 0x00000002 // Soft-reset1 for NWP - Cortex + // sysrstn and NWP associated + // peripherals are - This is an + // auto-clr bit. + +#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \ + 0x00000001 // Soft-reset0 for NWP - Only + // Cortex-sysrstn is asserted - This + // is an auto-clear bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKEUP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \ + 0x000000FF // Mask for LPDS Wakeup interrupt : + // 7 - WLAN Host Interrupt ; 6 - + // WLAN to NWP Wake request ; 5 - + // APPS to NWP Wake request; 4 - + // GPIO Wakeup ; 3 - Autonomous UART + // Wakeup ; 2 - SSDIO Wakeup ; 1 - + // Autonomous SPI Wakeup ; 0 - LPDS + // Wakeup-timer + +#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKEUP_SRC register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \ + 0x000000FF // Indicates the cause for NWP + // LPDS-Wakeup : 7 - WLAN Host + // Interrupt ; 6 - WLAN to NWP Wake + // request ; 5 - APPS to NWP Wake + // request; 4 - GPIO Wakeup ; 3 - + // Autonomous UART Wakeup ; 2 - + // SSDIO Wakeup ; 1 - Autonomous SPI + // Wakeup ; 0 - LPDS Wakeup-timer + +#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_RESET_CAUSE register. +// +//****************************************************************************** +#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \ + 0x000000FF // Indicates the reset cause for + // NWP : "0000" - Wake from HIB/OFF + // mode; "0001" - Wake from LPDS ; + // "0010" - Reserved ; "0011" - + // Soft-reset0 (Only NWP + // Cortex-sysrstn is asserted); + // "0100" - Soft-reset1 (NWP + // Cortex-sysrstn and NWP + // peripherals are reset); "0101" - + // WDOG0 (NWP Cortex-sysrstn and NWP + // peripherals are reset); "0110" - + // MCU Soft-reset (APPS + NWP + // Cortex-sysrstn + Peripherals are + // reset); "0111" - SSDIO Function2 + // reset (Only Cortex-sysrstn is + // asserted) ; "1000" - Reset due to + // WDOG of APPS (NWP Cortex-sysrstn + // and NWP peripherals are reset); + +#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \ + 0xFFFFFFFF // OPP Request Configuration + // (Number of slow-clk cycles) for + // LPDS Wake-timer + +#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SRAM_DSLP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \ + 0x000FFFFF // Configuration of NWP Memories + // during DSLP : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. NWP SRAM + // Cluster information : [2] - 3rd + // column in MEMSS (Applicable only + // when owned by NWP) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by NWP) ; [4] - 5th + // column in MEMSS (Applicable only + // when owned by NWP) ; [5] - 6th + // column in MEMSS (Applicable only + // when owned by NWP) ; [6] - 7th + // column in MEMSS (Applicable only + // when owned by NWP) ; [7] - 8th + // column in MEMSS (Applicable only + // when owned by NWP) ; [8] - 9th + // column in MEMSS (Applicable only + // when owned by NWP) ; [9] - 10th + // column in MEMSS (Applicable only + // when owned by NWP) ; [10] - 11th + // column in MEMSS (Applicable only + // when owned by NWP) ; [11] - 12th + // column in MEMSS (Applicable only + // when owned by NWP) ; [12] - 13th + // column in MEMSS (Applicable only + // when owned by NWP) ; [13] - 14th + // column in MEMSS (Applicable only + // when owned by NWP) ; [14] - 15th + // column in MEMSS (Applicable only + // when owned by NWP) ; [19:18] - + // Reserved. + +#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SRAM_LPDS_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \ + 0x000FFFFF // Configuration of NWP Memories + // during LPDS : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. NWP SRAM + // Cluster information : [2] - 3rd + // column in MEMSS (Applicable only + // when owned by NWP) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by NWP) ; [4] - 5th + // column in MEMSS (Applicable only + // when owned by NWP) ; [5] - 6th + // column in MEMSS (Applicable only + // when owned by NWP) ; [6] - 7th + // column in MEMSS (Applicable only + // when owned by NWP) ; [7] - 8th + // column in MEMSS (Applicable only + // when owned by NWP) ; [8] - 9th + // column in MEMSS (Applicable only + // when owned by NWP) ; [9] - 10th + // column in MEMSS (Applicable only + // when owned by NWP) ; [10] - 11th + // column in MEMSS (Applicable only + // when owned by NWP) ; [11] - 12th + // column in MEMSS (Applicable only + // when owned by NWP) ; [12] - 13th + // column in MEMSS (Applicable only + // when owned by NWP) ; [13] - 14th + // column in MEMSS (Applicable only + // when owned by NWP) ; [14] - 15th + // column in MEMSS (Applicable only + // when owned by NWP) ; [19:18] - + // Reserved. + +#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \ + 0xFFFFFFFF // Wake time configuration (no of + // slow clks) for NWP wake from + // LPDS. + +#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register. +// +//****************************************************************************** +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \ + 0xFFFE0000 + +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17 +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \ + 0x00010000 // 0 - APPS is selected as host for + // Autonms SPI ; 1 - External host + // is selected as host for Autonms + // SPI + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register. +// +//****************************************************************************** +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \ + 0x00010000 + +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \ + 0x00000002 // When 1 => IDLE-mode is + // acknowledged by the SPI-IP. (This + // is for MCSPI_N1) + +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \ + 0x00000001 // When 1 => Request for IDLE-mode + // for autonomous SPI. (This is for + // MCSPI_N1) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register. +// +//****************************************************************************** +#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \ + 0x00000001 // 1 - Request for waking up NWP + // from any of its low-power modes + // (SLP/DSLP/LPDS) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register. +// +//****************************************************************************** +#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \ + 0x00000001 // 1 - Request for wakinp up WLAN + // from its ELP Mode (This gets + // triggered to ELP-logic of WLAN) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \ + 0x00000003 // "00" - Wakeup on level0 of the + // selected GPIO (GPIO gets selected + // inside HIB3P3-module); "01" - + // Wakeup on fall-edge of selected + // GPIO. + +#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG12 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \ + 0x0000FFFF // This corrsponds to ROW_32 + // [31:16] of the FUSEFARM. SPARE + +#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG5 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \ + 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM + // : [5:0] - ADC OFFSET ; [13:6] - + // TEMP_SENSE ; [14:14] - DFT_GSG ; + // [15:15] - FMC_DISABLE ; [31:16] - + // WLAN_MAC ID + +#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG6 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \ + 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM + // : [31:0] : WLAN MAC ID + +#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_CFG0 register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \ + 0x00FF0000 // ANA-BGAP Settling time (In + // number of slow_clks) + +#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16 +#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \ + 0x0000FF00 // Slicer LDO settling time (In + // number of slow clks) + +#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8 +#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \ + 0x000000FF // Dig-buffer settling time (In + // number of slow clks) + +#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_CFG1 register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \ + 0xFF000000 // XTAL settling time (In number of + // slow clks) + +#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24 +#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \ + 0x00FF0000 // LV Slicer settling time + +#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16 +#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \ + 0x0000FF00 // HV Slicer Pull-down settling + // time + +#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8 +#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \ + 0x000000FF // HV Slicer settling time + +#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \ + 0x00007F00 // Configuration for WLAN APLLMCS - + // N[6:0], if the XTAL frequency is + // 40 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8 +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \ + 0x000000FF // Configuration for WLAN APLLMCS - + // M[7:0], if the XTAL frequency is + // 40 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \ + 0x00000010 // Configuration for WLAN APLLMCS - + // if the XTAL frequency if 40 MHz + // (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \ + 0x00000008 // Configuration for WLAN APLLMCS - + // Sel96, if the XTAL frequency is + // 40 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \ + 0x00000007 // Configuration for WLAN APLLMCS - + // Selinpfreq, if the XTAL frequency + // is 40 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \ + 0x00007F00 // Configuration for WLAN APLLMCS - + // N[6:0], if the XTAL frequency is + // 26 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8 +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \ + 0x000000FF // Configuration for WLAN APLLMCS - + // M[7:0], if the XTAL frequency is + // 26 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \ + 0x00000010 // Configuration for WLAN APLLMCS - + // if the XTAL frequency if 26 MHz + // (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \ + 0x00000008 // Configuration for WLAN APLLMCS - + // Sel96, if the XTAL frequency is + // 26 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \ + 0x00000007 // Configuration for WLAN APLLMCS - + // Selinpfreq, if the XTAL frequency + // is 26 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \ + 0x00080000 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \ + 0x00070000 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16 +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \ + 0x00000700 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8 +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \ + 0x00000020 // Override control for + // WLAN_APLLMCS_M[8]. When set to1, + // M[8] will be selected by bit [3]. + // (Else controlled from WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \ + 0x00000010 // Override for WLAN_APLLMCS_M[8]. + // Applicable only when bit [4] is + // set to 1. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \ + 0x00000004 // Override control for + // WLAN_APLLMCS_N[8:7]. When set + // to1, N[8:7] will be selected by + // bits [2:1]. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \ + 0x00000003 // Override value for + // WLAN_APLLMCS_N[8:7] bits. + // Applicable only when bit [1] is + // set to 1. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \ + 0x38000000 + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \ + 0x07000000 + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \ + 0x007F0000 // Configuration for MCU-APLLMCS : + // N during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \ + 0x0000FF00 // Configuration for MCU-APLLMCS : + // M during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // M[8] during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \ + 0x00000003 // Configuration for MCU-APLLMCS : + // N[8:7] during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // HISPEED during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \ + 0x00000008 // Configuration for MCU-APLLMCS : + // SEL96 during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \ + 0x00000007 // Configuration for MCU-APLLMCS : + // SELINPFREQ during RUN mode. + // Selected if the XTAL frequency is + // 38.4 MHz (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \ + 0x007F0000 // Configuration for MCU-APLLMCS : + // N during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \ + 0x0000FF00 // Configuration for MCU-APLLMCS : + // M during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // M[8] during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \ + 0x00000003 // Configuration for MCU-APLLMCS : + // N[8:7] during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // HISPEED during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \ + 0x00000008 // Configuration for MCU-APLLMCS : + // SEL96 during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \ + 0x00000007 // Configuration for MCU-APLLMCS : + // SELINPFREQ during RUN mode. + // Selected if the XTAL frequency is + // 26 MHz (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \ + 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 - + // APLLMCS_MCU is not locked + +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \ + 0x00000200 // Override for APLLMCS_MCU Enable. + // Applicable if bit [8] is set + +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \ + 0x00000100 // 1 - Enable for APLLMCS_MCU comes + // from bit [9]. 0 - Enable for + // APLLMCS_MCU comes from FSM. + +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \ + 0x00000006 // Override for sysclk src + // (applicable only if bit [0] is + // set to 1. "00"- SLOW_CLK "01"- + // XTAL_CLK "10"- PLL_CLK + +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1 +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \ + 0x00000001 // 1 - Sysclk src is selected from + // bits [2:1] of this register. 0 - + // Sysclk src is selected from FSM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SYSCLK_SWITCH_STATUS register. +// +//****************************************************************************** +#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \ + 0x00000001 // 1 - Sysclk switching is + // complete. 0 - Sysclk switching is + // in progress. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_LDO_CONTROLS register. +// +//****************************************************************************** +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \ + 0x00010000 // 1 - Enable for REF_LDO comes + // from bit [0] of this register ; 0 + // - Enable for REF_LDO comes from + // the FSM. Note : Final REF_LDO_EN + // reaches on the port + // TOP_PM_REG2[0] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \ + 0x0000C000 // Spare bits for REF_CTRL_FSM. + // Reaches directly on port + // TOP_PM_REG2[15:14] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14 +#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \ + 0x00003800 // REF TLOAD Enable. Reaches + // directly on port + // TOP_PM_REG2[13:11] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11 +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \ + 0x00000700 // REF_LDO Test-mux control. + // Reaches directly on port + // TOP_PM_REG2[10:8] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8 +#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \ + 0x000000C0 // REF BW Control. Reaches directly + // on port TOP_PM_REG2[7:6] of + // gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6 +#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \ + 0x0000003C // REF VTRIM Control. Reaches + // directly on port TOP_PM_REG2[5:2] + // of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2 +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \ + 0x00000002 // REF LDO Bypass Enable. Reaches + // directly on port TOP_PM_REG2[1] + // of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \ + 0x00000001 // Override for REF_LDO Enable. + // Applicable only if bit [16] of + // this register is set. Note : + // Final REF_LDO_EN reaches on the + // port TOP_PM_REG2[0] of gprcm. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_RTRIM_CONTROL register. +// +//****************************************************************************** +#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \ + 0x18000000 // This is [5:4] bits of + // TOP_PM_REG0 + +#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27 +#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \ + 0x07FF0000 // This is [15:5] bits of + // TOP_CLKM_REG0 + +#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16 +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \ + 0x00000100 // 1 - CLKM_RTRIM comes for + // bits[4:0] of this register. 0 - + // CLKM_RTRIM comes from Efuse + // (after efuse_done = 1). + +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \ + 0x0000001F // CLKM_TRIM Override. Applicable + // when efuse_done = 0 or bit[8] is + // set to 1. + +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_SLICER_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \ + 0x00200000 // 1 - EN_DIG_BUF_TOP comes from + // bit [14] of this register. 0 - + // EN_DIG_BUF_TOP comes from the + // FSM. Note : Final EN_DIG_BUF_WLAN + // reaches on TOP_CLKM_REG1_IN[14] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \ + 0x00100000 // 1 - EN_DIG_BUF_TOP comes from + // bit [15] of this register. 0 - + // EN_DIG_BUF_TOP comes from the + // FSM. Note : Final EN_DIG_BUF_TOP + // reaches on TOP_CLKM_REG1_IN[15] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \ + 0x00080000 // 1 - EN_XTAL comes from bit [3] + // of this register. 0 - EN_XTAL + // comes from FSM. Note : Final + // XTAL_EN reaches on + // TOP_CLKM_REG1_IN[3] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \ + 0x00040000 // 1 - Enable HV Slicer comes from + // bit [2] of this register. 0 - + // Enable HV Slicer comes from FSM. + // Note : Final HV_SLICER_EN reaches + // on port TOP_CLKM_REG1_IN[1] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \ + 0x00020000 // 1 - Enable LV Slicer comes from + // bit[1] of this register. 0 - + // Enable LV Slicer comes from FSM. + // Note : final LV_SLICER_EN reaches + // on port TOP_CLKM_REG1_IN[2] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \ + 0x00010000 // 1 - Enable HV Pull-down comes + // from bit[0] of this register. 0 - + // Enable HV Pull-down comes from + // FSM. Note : Final HV_PULL_DOWN + // reaches on port + // TOP_CLKM_REG1_IN[0] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \ + 0x00008000 // Override for EN_DIG_BUF_TOP. + // Applicable if bit[20] is set to + // 1. Note : Final EN_DIG_BUF_TOP + // reaches on TOP_CLKM_REG1_IN[15] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \ + 0x00004000 // Override for EN_DIG_BUF_WLAN. + // Applicable if bit[19] is set to + // 1. Note : Final EN_DIG_BUF_WLAN + // reaches on TOP_CLKM_REG1_IN[14] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \ + 0x00002000 // CLKOUT Flip Enable. Reaches on + // bit[13] of TOP_CLKM_REG1_IN[13] + // port of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \ + 0x00001000 // Enable divide2 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[12] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \ + 0x00000800 // Enable divide3 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[11] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \ + 0x00000400 // Enable divide4 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[10] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \ + 0x000003C0 // CM Test-mux select. Reaches on + // TOP_CLMM_REG1_IN[9:6] port of + // gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6 +#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \ + 0x00000030 // Slicer spare0 control. Reaches + // on TOP_CLKM_REG1_IN[5:4] port of + // gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4 +#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \ + 0x00000008 // Enable XTAL override. Reaches on + // TOP_CLKM_REG1_IN[3] port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \ + 0x00000004 // Enable HV Slicer override. + // Reaches on TOP_CLKM_REG1_IN[1] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \ + 0x00000002 // Enable LV Slicer override. + // Reaches on TOP_CLKM_REG1_IN[2] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \ + 0x00000001 // Enable HV Pull-down override. + // Reaches on TOP_CLKM_REG1_IN[0] + // port of gprcm + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_SLICER_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \ + 0x0000FC00 // Slicer spare1. Reaches on port + // TOP_CLKM_REG2_IN[15:10] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10 +#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \ + 0x000003F0 // XOSC Trim. Reaches on port + // TOP_CLKM_REG2_IN[9:4] of gprcm + +#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4 +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \ + 0x00000008 // Slicer ITRIM Toggle. Reaches on + // port TOP_CLKM_REG2_IN[3] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \ + 0x00000007 // LV Slicer trim. Reaches on port + // TOP_CLKM_REG2_IN[2:0] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \ + 0xFF800000 + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \ + 0x00400000 // 1 - REF_MAG_TRIM comes from + // bit[4:0] of register + // REF_ANA_BGAP_CONTROLS1 [Addr : + // 0x0850]; 0 - REF_MAG_TRIM comes + // from efuse (After efc_done = 1). + // Note : Final REF_MAG_TRIM reaches + // on port TOP_PM_REG1[4:0] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \ + 0x00200000 // 1 - REF_V2I_TRIM comes from + // bit[9:6] of this register ; 0 - + // REF_V2I_TRIM comes from efuse + // (After efc_done = 1). Note : + // Final REF_V2I_TRIM reaches on + // port TOP_PM_REG0[9:6] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \ + 0x00100000 // 1 - REF_TEMP_TRIM comes from + // bit[15:10] of this register ; 0 - + // REF_TEMP_TRIM comes from efuse + // (After efc_done = 1). Note : + // Final REF_TEMP_TRIM reaches on + // port TOP_PM_REG0[15:10] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \ + 0x00080000 // 1 - REF_STARTUP_EN comes from + // bit [3] of this register ; 0 - + // REF_STARTUP_EN comes from FSM. + // Note : Final REF_STARTUP_EN + // reaches on port TOP_PM_REG0[3] of + // gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \ + 0x00040000 // 1 - REF_V2I_EN comes from bit + // [2] of this register ; 0 - + // REF_V2I_EN comes from FSM. Note : + // Final REF_V2I_EN reaches on port + // TOP_PM_REG0[2] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \ + 0x00020000 // 1 - REF_FC_EN comes from bit [1] + // of this register ; 0 - REF_FC_EN + // comes from FSM. Note : Final + // REF_FC_EN reaches on port + // TOP_PM_REG0[1] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \ + 0x00010000 // 1 - REF_BGAP_EN comes from bit + // [0] of this register ; 0 - + // REF_BGAP_EN comes from FSM. Note + // : Final REF_BGAP_EN reaches on + // port TOP_PM_REG0[0] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \ + 0x0000FC00 // REF_TEMP_TRIM override. + // Applicable when bit [20] of this + // register set to 1. (or efc_done = + // 0) Note : Final REF_TEMP_TRIM + // reaches on port + // TOP_PM_REG0[15:10] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \ + 0x000003C0 // REF_V2I_TRIM Override. + // Applicable when bit [21] of this + // register set to 1 . (of efc_done + // = 0) Note : Final REF_V2I_TRIM + // reaches on port TOP_PM_REG0[9:6] + // of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \ + 0x00000030 + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \ + 0x00000008 // REF_STARTUP_EN override. + // Applicable when bit [19] of this + // register is set to 1. Note : + // Final REF_STARTUP_EN reaches on + // port TOP_PM_REG0[3] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \ + 0x00000004 // REF_V2I_EN override. Applicable + // when bit [21] of this register is + // set to 1. Note : Final REF_V2I_EN + // reaches on port TOP_PM_REG0[2] of + // gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \ + 0x00000002 // REF_FC_EN override. Applicable + // when bit [17] of this register is + // set to 1. Note : Final REF_FC_EN + // reaches on port TOP_PM_REG0[1] of + // gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \ + 0x00000001 // REF_BGAP_EN override. Applicable + // when bit [16] of this register + // set to 1. Note : Final + // REF_BGAP_EN reaches on port + // TOP_PM_REG0[0] of gprcm. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \ + 0xFFFF0000 + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \ + 0x0000C000 // REF_BGAP_SPARE. Reaches on port + // TOP_PM_REG1[15:14] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \ + 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on + // port TOP_PM_REG1[13:9] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \ + 0x000001E0 // REF_FILT_TRIM. Reaches on port + // TOP_PM_REG1[8:5] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \ + 0x0000001F // REF_MAG_TRIM Override. + // Applicable when bit[22] of + // REF_ANA_BGAP_CONTROLS0 [0x084C] + // set to 1 (of efc_done = 0). Note + // : Final REF_MAG_TRIM reaches on + // port TOP_PM_REG1[4:0] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \ + 0xFFFF0000 + +#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16 +#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \ + 0x0000FFFF // Spare control. Reaches on + // TOP_PM_REG3 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \ + 0xFFFF0000 // Spare control. Reaches on + // TOP_CLKM_REG3 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16 +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \ + 0x0000FFFF // Spare control. Reaches on + // TOP_CLKM_REG4 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \ + 0xFFFF0000 + +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16 +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \ + 0x0000FFFF + +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6 +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \ + 0x00000020 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \ + 0x00000010 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \ + 0x00000008 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \ + 0x00000004 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \ + 0x00000002 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_PLL_REF_LOCK_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3 +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \ + 0x00000004 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \ + 0x00000002 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PSCON_DEBUG register. +// +//****************************************************************************** +#define GPRCM_MCU_PSCON_DEBUG_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6 +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \ + 0x00000038 // MCU_PSCON_RTC_ON = "0000"; + // MCU_PSCON_RTC_OFF = "0001"; + // MCU_PSCON_RTC_RET = "0010"; + // MCU_PSCON_RTC_OFF_TO_ON = "0011"; + // MCU_PSCON_RTC_RET_TO_ON = "0100"; + // MCU_PSCON_RTC_ON_TO_RET = "0101"; + // MCU_PSCON_RTC_ON_TO_OFF = "0110"; + // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP + // = "0111"; + // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP + // = "1000"; + +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3 +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \ + 0x00000007 + +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PWR_PS register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PWR_PS_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_MEMSS_PWR_PS_reserved_S 3 +#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \ + 0x00000007 // MEMSS_PM_SLEEP = "000"; + // MEMSS_PM_WAIT_OPP = "010"; + // MEMSS_PM_ACTIVE = "011"; + // MEMSS_PM_SLEEP_TO_ACTIVE = "100"; + // MEMSS_PM_ACTIVE_TO_SLEEP = "101"; + +#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_DEBUG register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_DEBUG_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_REF_FSM_DEBUG_reserved_S 6 +#define GPRCM_REF_FSM_DEBUG_fref_mode_M \ + 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11 + // - XTAL Mode + +#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4 +#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \ + 0x0000000F // constant FREF_CLK_OFF = "00000"; + // constant FREF_EN_BGAP = "00001"; + // constant FREF_EN_LDO = "00010"; + // constant FREF_EN_SLI_HV = + // "00011"; constant + // FREF_EN_SLI_HV_PD = "00100"; + // constant FREF_EN_DIG_BUF = + // "00101"; constant FREF_EN_OSC = + // "00110"; constant FREF_EN_SLI_LV + // = "00111"; constant + // FREF_EN_CLK_REQ = "01000"; + // constant FREF_CLK_VALID = + // "01001"; constant FREF_MODE_DET0 + // = "01010"; constant + // FREF_MODE_DET1 = "01011"; + // constant FREF_MODE_DET2 = + // "10010"; constant FREF_MODE_DET3 + // = "10011"; constant FREF_VALID = + // "01100"; constant FREF_VALID0 = + // "01101"; constant FREF_VALID1 = + // "01110"; constant FREF_VALID2 = + // "01111"; constant + // FREF_WAIT_EXT_TCXO0 = "10000"; + // constant FREF_WAIT_EXT_TCXO1 = + // "10001"; + +#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register. +// +//****************************************************************************** +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \ + 0xFFFFFFE0 + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5 +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \ + 0x00000010 // 1 - Override the sytem-opp + // request to ANATOP using bit0 of + // this register + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \ + 0x0000000F // "0001" - RUN ; "0010" - DSLP ; + // "0100" - LPDS ; Others - NA + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register. +// +//****************************************************************************** +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \ + 0xFFFFFFFE + +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1 +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \ + 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS) + // entry even if Test-Pd is kept ON + // ; 0 - Donot enable sleep-opp + // (DSLP/LPDS) entry with Test-Pd + // ON. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3 +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \ + 0x00000004 // NA + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \ + 0x00000002 // NA + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \ + 0x00000001 // NA + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \ + 0x00000004 // 1 - Override the MCU-PD power + // modes using bits [1] & [0] ; + +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \ + 0x00000002 // 1 - Request for power-down of + // MCU-PD ; + +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \ + 0x00000001 // 1 - Request for retention mode + // of MCU-PD. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \ + 0x00000002 // 1- Override the MCSPI + // (Autonomous SPI) memory state + // using bit [0] + +#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \ + 0x00000001 // 1 - Request for power-down of + // Autonomous SPI 8k memory ; 0 - + // Donot request power-down of + // Autonomous SPI 8k Memory + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \ + 0x00000100 + +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \ + 0x00000002 + +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_REF_FSM_CFG2 register. +// +//****************************************************************************** +#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \ + 0x00380000 // Number of RTC clocks for keeping + // the FC_EN asserted high + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19 +#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \ + 0x00070000 // Number of RTC clocks for keeping + // the STARTUP_EN asserted high + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16 +#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \ + 0x0000FFFF // Number of RTC clocks for waiting + // for clock to settle. + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TESTCTRL_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1 +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \ + 0x00000001 // 0 - Disable the TestCtrl-pd ; 1 + // - Enable the TestCtrl-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \ + 0x00000006 // 1 - SSDIO-PD is ON ; 0 - + // SSDIO-PD is OFF + +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1 +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \ + 0x00000001 // 0 - Disable the SSDIO-pd ; 1 - + // Enable the SSDIO-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_N1_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \ + 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 - + // MCSPI_N1-PD if OFF + +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1 +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \ + 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1 + // - Enable the MCSPI_N1-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \ + 0x00001C00 + +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10 +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \ + 0x00000200 + +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \ + 0x00000100 + +#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1 +#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \ + 0x00000001 // 0 - Disable the WELP-pd ; 1 - + // Enable the WELP-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1 +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \ + 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 - + // Enable the WL_SDIO-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register. +// +//****************************************************************************** +#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \ + 0x00FFFFFF // SRAM (WTOP+DRP) state during + // Active-mode : 1 - SRAMs are ON ; + // 0 - SRAMs are OFF. Cluster + // information : [0] - 1st column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) [1] - 2nd column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [2] - 3rd column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [3] - 4th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [4] - + // 5th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [5] - 6th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [6] - 7th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [7] - 8th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [8] - 9th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [9] - + // 10th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [10] - 11th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [11] - 12th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [12] - 13th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [13] - 14th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [14] - + // 15th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [15] - 16th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [23:16] - Internal to + // WTOP Cluster + +#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register. +// +//****************************************************************************** +#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \ + 0x00FFFFFF // SRAM (WTOP+DRP) state during + // Sleep-mode : 1 - SRAMs are RET ; + // 0 - SRAMs are OFF. Cluster + // information : [0] - 1st column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) [1] - 2nd column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [2] - 3rd column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [3] - 4th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [4] - + // 5th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [5] - 6th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [6] - 7th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [7] - 8th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [8] - 9th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [9] - + // 10th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [10] - 11th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [11] - 12th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [12] - 13th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [13] - 14th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [14] - + // 15th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [15] - 16th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [23:16] - Internal to + // WTOP Cluster + +#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SECURE_INIT_DONE register. +// +//****************************************************************************** +#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \ + 0x00000002 // 1-Secure mode init is done ; + // 0-Secure mode init is not done + +#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \ + 0x00000001 // Must be programmed 1 in order to + // say that secure-mode device init + // is done + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_DEV_MODE_INIT_DONE register. +// +//****************************************************************************** +#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \ + 0x00000001 // 1 - Patch download and other + // initializations are done (before + // removing APPS resetn) for + // development mode (#3) . 0 - + // Development mode (#3) init is not + // done yet + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_EN_APPS_REBOOT register. +// +//****************************************************************************** +#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \ + 0x00000001 // 1 - When 1, disable the reboot + // of APPS after DevInit is + // completed. In this case, APPS + // will permanantly help in reset. 0 + // - When 0, enable the reboot of + // APPS after DevInit is completed. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_APPS_PERIPH_PRESENT register. +// +//****************************************************************************** +#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \ + 0x00010000 // 1 - Enable ; 0 - Disable + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \ + 0x00008000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \ + 0x00004000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \ + 0x00002000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \ + 0x00001000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \ + 0x00000800 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \ + 0x00000400 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \ + 0x00000200 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \ + 0x00000100 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \ + 0x00000080 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \ + 0x00000040 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \ + 0x00000020 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \ + 0x00000010 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \ + 0x00000008 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \ + 0x00000004 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \ + 0x00000002 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_NWP_PERIPH_PRESENT register. +// +//****************************************************************************** +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \ + 0x00000200 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \ + 0x00000100 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \ + 0x00000080 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \ + 0x00000040 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \ + 0x00000020 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \ + 0x00000010 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \ + 0x00000008 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \ + 0x00000004 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \ + 0x00000002 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register. +// +//****************************************************************************** + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \ + 0x00000040 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \ + 0x00000020 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \ + 0x00000010 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \ + 0x00000008 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \ + 0x00000004 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \ + 0x00000002 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \ + 0x00000F00 // "0000"- PORZ :- NWP is yet to be + // enabled by APPS during powerup + // (from HIB/OFF) ; "0011"- ACTIVE + // :- NWP is enabled, clocks and + // resets to NWP-SubSystem are + // enabled ; "0010"- LPDS :- NWP is + // in LPDS-mode ; Clocks and reset + // to NWP-SubSystem are gated ; + // "0101"- WAIT_FOR_OPP :- NWP is in + // transition from LPDS to ACTIVE, + // where it is waiting for OPP to be + // stable ; "1000"- + // WAKE_TIMER_OPP_REQ :- NWP is in + // transition from LPDS, where the + // wakeup cause is LPDS_Wake timer + // OTHERS : NA + +#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8 +#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \ + 0x00000007 // "000" - NWP_RUN : NWP is in RUN + // state (default) - Applicable only + // when NWP_PWR_STATE_PS = ACTIVE ; + // "001" - NWP_SLP : NWP is in SLEEP + // state (default) - Applicable only + // when NWP_PWR_STATE_PS = ACTIVE ; + // "010" - NWP_DSLP : NWP is in + // Deep-Sleep state (default) - + // Applicable only when + // NWP_PWR_STATE_PS = ACTIVE ; "011" + // - WAIT_FOR_ACTIVE : NWP is in + // transition from Deep-sleep to + // Run, where it is waiting for OPP + // to be stable ; "100" - + // WAIT_FOR_DSLP_TIMER_WAKE_REQ : + // NWP is in transition from + // Deep-sleep to Run, where the + // wakeup cause is deep-sleep + // wake-timer + +#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \ + 0x00000F00 // "0000"- PORZ :- APPS is waiting + // for PLL_clock during powerup + // (from HIB/OFF) ; "0011"- ACTIVE + // :- APPS is enabled, clocks and + // resets to APPS-SubSystem are + // enabled ; APPS might be either in + // Secure or Un-secure mode during + // this state. "1001" - + // SECURE_MODE_LPDS :- While in + // ACTIVE (Secure-mode), APPS had to + // program the DevInit_done bit at + // the end, after which it enters + // into this state, where the reset + // to APPS will be asserted. From + // this state APPS might either + // re-boot itself or enter into LPDS + // depending upon whether the device + // is 3200 or 3100. "0010"- LPDS :- + // APPS is in LPDS-mode ; Clocks and + // reset to APPS-SubSystem are gated + // ; "0101"- WAIT_FOR_OPP :- APPS is + // in transition from LPDS to + // ACTIVE, where it is waiting for + // OPP to be stable ; "1000" - + // WAKE_TIMER_OPP_REQ : APPS is in + // transition from LPDS, where the + // wakeup cause is LPDS_Wake timer ; + // "1010" - WAIT_FOR_PATCH_INIT : + // APPS enters into this state + // during development-mode #3 (SOP = + // 3), where it is waiting for patch + // download to complete and 0x4 hack + // is programmed. OTHERS : NA + +#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8 +#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \ + 0x00000007 // "000" - APPS_RUN : APPS is in + // RUN state (default) - Applicable + // only when APPS_PWR_STATE_PS = + // ACTIVE ; "001" - APPS_SLP : APPS + // is in SLEEP state (default) - + // Applicable only when + // APPS_PWR_STATE_PS = ACTIVE ; + // "010" - APPS_DSLP : APPS is in + // Deep-Sleep state (default) - + // Applicable only when + // APPS_PWR_STATE_PS = ACTIVE ; + // "011" - WAIT_FOR_ACTIVE : APPS is + // in transition from Deep-sleep to + // Run, where it is waiting for OPP + // to be stable ; "100" - + // WAIT_FOR_DSLP_TIMER_WAKE_REQ : + // APPS is in transition from + // Deep-sleep to Run, where the + // wakeup cause is deep-sleep + // wake-timer + +#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \ + 0x0000001F // TBD + +#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PM_PS register. +// +//****************************************************************************** +#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \ + 0x00000007 // "011" - WTOP_PM_ACTIVE (Default) + // :- WTOP_Pd is in ACTIVE mode; + // "100" - WTOP_PM_ACTIVE_TO_SLEEP + // :- WTOP_Pd is in transition from + // ACTIVE to SLEEP ; "000" - + // WTOP_PM_SLEEP : WTOP-Pd is in + // Sleep-state ; "100" - + // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd + // is in transition from SLEEP to + // ACTIVE ; "000" - + // WTOP_PM_WAIT_FOR_OPP : Wait for + // OPP to be stable ; + +#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WTOP PD + // Resetz. When set to 1, + // WTOP_Resetz will be controlled by + // bit [0] + +#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WTOP PD Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WELP PD + // Resetz. When set to 1, + // WELP_Resetz will be controlled by + // bit [0] + +#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WELP PD Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WL_SDIO + // Resetz. When set to 1, + // WL_SDIO_Resetz will be controlled + // by bit [0] + +#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WL_SDIO Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for SSDIO + // Resetz. When set to 1, + // SSDIO_Resetz will be controlled + // by bit [0] + +#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for SSDIO Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for MCSPI_N1 + // Resetz. When set to 1, + // MCSPI_N1_Resetz will be + // controlled by bit [0] + +#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for MCSPI_N1 Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for TESTCTRL-PD + // Resetz. When set to 1, + // TESTCTRL_Resetz will be + // controlled by bit [0] + +#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for TESTCTRL Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for MCU-PD + // Resetz. When set to 1, MCU_Resetz + // will be controlled by bit [0] + +#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for MCU Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG0 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \ + 0xFFFFFFFF // This is ROW_14 [31:0] of + // FUSEFARM. [0:0] : XTAL_IS_26MHZ + // [5:1] : TOP_CLKM_RTRIM[4:0] + // [10:6] : ANA_BGAP_MAG_TRIM[4:0] + // [16:11] : ANA_BGAP_TEMP_TRIM[5:0] + // [20:17] : ANA_BGAP_V2I_TRIM[3:0] + // [25:22] : PROCESS INDICATOR + // [26:26] : Reserved [31:27] : + // FUSEROM Version + +#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG1 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \ + 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM + // 1. NWP Peripheral Present bits + // [15:8] NWP_GPT_N0_PP [15:15] + // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP + // [13:13] NWP_UDMA_PP [12:12] + // NWP_UART_N0_PP [11:11] + // NWP_UART_N1_PP [10:10] + // NWP_SSDIO_PP [9:9] + // NWP_MCSPI_N1_PP [8:8] 2. Shared + // Peripheral Present bits [7:0] + // SHARED SPI PP [6:6] + // SHARED I2C PP [5:5] SHARED + // GPIO-A PP [4:4] SHARED GPIO-B PP + // [3:3] SHARED GPIO-C PP [2:2] + // SHARED GPIO-D PP [1:1] SHARED + // GPIO-E PP [0:0] + +#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG2 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \ + 0xFFFFFFFF // This is ROW_16[15:0] & + // ROW_15[31:16] of FUSEFARM. + // [31:21] - Reserved [20:16] - + // CHIP_ID [15:15] - SSBD SOP + // Control [14:14] - SSBD TAP + // Control [13:2] - APPS Peripheral + // Present bits : APPS_CAMERA_PP + // [13:13] APPS_MMCHS_PP [12:12] + // APPS_MCASP_PP [11:11] + // APPS_MCSPI_A1_PP [10:10] + // APPS_MCSPI_A2_PP [9:9] + // APPS_UDMA_PP [8:8] APPS_WDOG_PP + // [7:7] APPS_UART_A0_PP [6:6] + // APPS_UART_A1_PP [5:5] + // APPS_GPT_A0_PP [4:4] + // APPS_GPT_A1_PP [3:3] + // APPS_GPT_A2_PP [2:2] + // APPS_GPT_A3_PP [1:1] [0:0] - NWP + // Peripheral present bits + // NWP_ACSPI_PP [0:0] + +#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG3 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \ + 0xFFFFFFFF // This is ROW_17[15:0] & + // ROW_16[31:16] of FUSEFARM : + // [31:16] - TEST_TAP_KEY(15:0) + // [15:0] - Reserved + +#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_MEM_RET_CFG register. +// +//****************************************************************************** +#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \ + 0x00000001 // 1 - Soft-compile memories in + // WTOP can be turned-off during + // WTOP-sleep mode ; 0 - + // Soft-compile memories in WTOP + // must be kept on during WTOP-sleep + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \ + 0x007FFFFF // TBD + +#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \ + 0x000FFFFF // TBD + +#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \ + 0x00000018 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3 +#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \ + 0x00000004 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \ + 0x00000002 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \ + 0x00000001 // TBD + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \ + 0x00000001 // 1 - Enable switching of sysclk + // to Coex-clk path ; 0 - Disable + // switching of sysclk to Coex-clk + // path. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_DCDC_CLK_GEN_CONFIG register. +// +//****************************************************************************** +#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \ + 0x00000001 // 1 - Enable the clock for DCDC + // (PWM-mode) ; 0 - Disable the + // clock for DCDC (PWM-mode) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG4 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \ + 0x0000FFFF // This corresponds to + // ROW_17[31:16] of the FUSEFARM : + // [15:0] : TEST_TAP_KEY(31:16) + +#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG5 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \ + 0xFFFFFFFF // Corresponds to ROW_18 of + // FUSEFARM. [29:0] - + // MEMSS_COLUMN_SEL_LSW ; [30:30] - + // WLAN GEM DISABLE ; [31:31] - + // SERIAL WIRE JTAG SELECT + +#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG6 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \ + 0x0000FFFF // Corresponds to ROW_19[15:0] of + // FUSEFARM. [15:0] : + // MEMSS_COLUMN_SEL_MSW + +#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG7 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_20[15:0] & + // ROW_19[31:16] of FUSEFARM. + // FLASH_REGION0 + +#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG8 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_21[15:0] & + // ROW_20[31:16] of FUSEFARM. + // FLASH_REGION1 + +#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG9 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_22[15:0] & + // ROW_21[31:16] of FUSEFARM. + // FLASH_REGION2 + +#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG10 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_23[15:0] & + // ROW_22[31:16] of FUSEFARM. + // FLASH_REGION3 + +#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG11 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_24[15:0] & + // ROW_23[31:16] of FUSEFARM. + // FLASH_DESCRIPTOR + +#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG0 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \ + 0xFFFFFFFF // Corresponds to bits [191:160] of + // the FUSEFARM. This is ROW_5 of + // FUSEFARM [191:160] : [31:0] : + // DIE_ID0 [31:0] : DEVX [11:0] DEVY + // [23:12] DEVWAF [29:24] DEV_SPARE + // [31:30] + +#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG1 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \ + 0xFFFFFFFF // Corresponds to bits [223:192] of + // the FUSEFARM. This is ROW_6 of + // FUSEFARM :- DEVLOT [23:0] DEVFAB + // [28:24] DEVFABBE [31:29] + +#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG2 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \ + 0xFFFFFFFF // Corresponds to bits [255:224] of + // the FUSEFARM. This is ROW_7 of + // FUSEFARM:- DEVDESREV[4:0] + // Memrepair[5:5] MakeDefined[16:6] + // CHECKSUM[30:17] Reserved : + // [31:31] + +#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG3 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \ + 0xFFFFFFFF // Corresponds to bits [287:256] of + // the FUSEFARM. This is ROW_8 of + // FUSEFARM :- DIEID0 - DEVREG + // [31:0] + +#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG4 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \ + 0xFFFFFFFF // Corresponds to bits [319:288] of + // the FUSEFARM. This is ROW_9 of + // FUSEFARM :- [7:0] - VBATMON ; + // [13:8] - BUFF_OFFSET ; [15:15] - + // DFT_GXG ; [14:14] - DFT_GLX ; + // [19:16] - PHY ROM Version ; + // [23:20] - MAC ROM Version ; + // [27:24] - NWP ROM Version ; + // [31:28] - APPS ROM Version + +#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APPS_SS_OVERRIDES_reserved_M \ + 0xFFFFFC00 + +#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10 +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \ + 0x00000200 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \ + 0x00000100 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \ + 0x00000080 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \ + 0x00000040 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \ + 0x00000020 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \ + 0x00000010 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \ + 0x00000008 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \ + 0x00000002 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_NWP_SS_OVERRIDES_reserved_M \ + 0xFFFFFC00 + +#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10 +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \ + 0x00000200 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \ + 0x00000100 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \ + 0x00000080 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \ + 0x00000040 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \ + 0x00000020 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \ + 0x00000010 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \ + 0x00000008 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \ + 0x00000002 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SHARED_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8 +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \ + 0x00000080 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \ + 0x00000040 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \ + 0x00000020 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \ + 0x00000010 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \ + 0x00000008 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \ + 0x00000004 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \ + 0x00000002 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8 +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \ + 0x00000080 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \ + 0x00000040 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \ + 0x00000020 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \ + 0x00000010 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \ + 0x00000008 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \ + 0x00000002 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_FSM_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \ + 0xFFFFF000 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12 +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \ + 0x00000800 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \ + 0x00000400 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \ + 0x00000200 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \ + 0x00000100 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \ + 0x00000080 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \ + 0x00000040 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \ + 0x00000020 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \ + 0x00000010 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \ + 0x00000008 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \ + 0x00000002 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \ + 0xFFF00000 + +#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \ + 0x00080000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \ + 0x00040000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \ + 0x00020000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \ + 0x00010000 + +#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \ + 0x0000FC00 + +#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \ + 0x00000200 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \ + 0x00000100 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \ + 0x000000F0 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \ + 0x0000000F + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \ + 0xFFC00000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22 +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \ + 0x00200000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \ + 0x00100000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \ + 0x00080000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \ + 0x00040000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \ + 0x00020000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \ + 0x00010000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \ + 0x0000FF00 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8 +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \ + 0x000000FF + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8 +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \ + 0x00000080 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \ + 0x00000040 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \ + 0x00000020 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \ + 0x00000010 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \ + 0x00000008 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \ + 0x00000004 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \ + 0x00000001 + + + + +#endif // __HW_GPRCM_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib1p2.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib1p2.h new file mode 100755 index 00000000000..06694512f46 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib1p2.h @@ -0,0 +1,1748 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_HIB1P2_H__ +#define __HW_HIB1P2_H__ + +//***************************************************************************** +// +// The following are defines for the HIB1P2 register offsets. +// +//***************************************************************************** +#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \ + 0x00000000 + +#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \ + 0x00000004 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \ + 0x00000008 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \ + 0x0000000C + +#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \ + 0x00000010 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \ + 0x00000014 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \ + 0x00000018 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \ + 0x0000001C + +#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \ + 0x00000020 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \ + 0x00000024 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \ + 0x00000028 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \ + 0x00000064 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \ + 0x00000068 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \ + 0x0000006C + +#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \ + 0x00000070 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \ + 0x00000074 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \ + 0x00000078 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \ + 0x0000007C + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \ + 0x00000080 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \ + 0x00000084 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \ + 0x00000088 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \ + 0x0000008C + +#define HIB1P2_O_PMBIST_PARAMETERS0 \ + 0x00000094 + +#define HIB1P2_O_PMBIST_PARAMETERS1 \ + 0x00000098 + +#define HIB1P2_O_PMBIST_PARAMETERS2 \ + 0x0000009C + +#define HIB1P2_O_PMBIST_PARAMETERS3 \ + 0x000000A0 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \ + 0x000000A4 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \ + 0x000000A8 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \ + 0x000000AC + +#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \ + 0x000000B0 + +#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \ + 0x000000B4 + +#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \ + 0x000000B8 + +#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \ + 0x000000BC + +#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \ + 0x000000C0 + +#define HIB1P2_O_CM_OSC_16M_CONFIG \ + 0x000000C4 + +#define HIB1P2_O_SOP_SENSE_VALUE \ + 0x000000C8 + +#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \ + 0x000000CC + +#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \ + 0x000000D0 + +#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \ + 0x000000D4 + +#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \ + 0x000000D8 + +#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \ + 0x000000DC + +#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \ + 0x000000E0 + +#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \ + 0x000000E4 + +#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \ + 0x000000E8 + +#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \ + 0x000000EC + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \ + 0x000000F0 + +#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \ + 0x000000F4 + +#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \ + 0x000000F8 + +#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \ + 0x000000FC + +#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \ + 0x00000100 + +#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \ + 0x00000104 + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \ + 0x00000108 + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \ + 0x0000010C + +#define HIB1P2_O_CM_SPARE 0x00000110 +#define HIB1P2_O_PORPOL_SPARE 0x00000114 +#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \ + 0x00000118 + +#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \ + 0x0000011C + +#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \ + 0x00000120 + +#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \ + 0x00000124 + +#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \ + 0x00000128 + +#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \ + 0x0000012C + +#define HIB1P2_O_MEM_HIB_FSM_DEBUG \ + 0x00000130 + +#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \ + 0x00000134 + +#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \ + 0x00000138 + +#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \ + 0x0000013C + +#define HIB1P2_O_MEM_CM_TEST_MODE \ + 0x00000140 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \ + 0xC0000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \ + 0x30000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \ + 0x08000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \ + 0x04000000 // FSM Override value for SLDO_EN : + // Applicable only when bit [4] of + // this register is set to 1. + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \ + 0x02000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \ + 0x01000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \ + 0x00FC0000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \ + 0x0003FF00 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \ + 0x00000080 // FSM Override value for + // SKA_LDO_EN : Applicable only when + // bit [3] of this register is set + // to 1. + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \ + 0x00000040 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \ + 0x00000020 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \ + 0x00000010 // When 1, bit[26] of this register + // will be used as SLDO_EN + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \ + 0x00000008 // When 1, bit[26] of this register + // will be used as SKA_LDO_EN + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \ + 0x00000007 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \ + 0xFFC00000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \ + 0x003F0000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \ + 0x00008000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \ + 0x00004000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \ + 0x00002000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \ + 0x00001000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \ + 0x00000800 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \ + 0x000007FF + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \ + 0x80000000 // Override value for DCDC_DIG_EN : + // Applicable only when bit [31] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \ + 0x20000000 // Override value for + // DCDC_DIG_EN_SUBREG_1P8V : + // Applicable only when bit [30] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \ + 0x10000000 // Override value for + // DCDC_DIG_EN_SUBREG_1P2V : + // Applicable only when bit [29] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \ + 0x08000000 // Override value for + // DCDC_DIG_SLP_EN : Applicable only + // when bit [28] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \ + 0x04000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \ + 0x02000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \ + 0x01000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \ + 0x00800000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \ + 0x00400000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \ + 0x003F0000 // Override value for + // DCDC_DIG_VTRIM : Applicable only + // when bit [27] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \ + 0x0000C000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \ + 0x00003000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \ + 0x00000800 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \ + 0x00000780 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \ + 0x00000078 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3 +#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \ + 0x00000007 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \ + 0x20000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \ + 0x10000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \ + 0x08000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \ + 0x04000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \ + 0x02000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \ + 0x01FFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \ + 0x0F000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \ + 0x00C00000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \ + 0x00300000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16 +#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \ + 0x00008000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \ + 0x00007800 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \ + 0x00000400 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \ + 0x000003FC + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \ + 0x00000002 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \ + 0x00000001 // Override value for + // DCDC_DIG_COT_EN : Applicable only + // when bit[26] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \ + 0x7F800000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \ + 0x00400000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \ + 0x00200000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \ + 0x001FE000 // Override value for + // DCDC_DIG_ILIM_TRIM : Applicable + // only when bit [25] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \ + 0x00001800 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \ + 0x00000400 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \ + 0x00000200 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \ + 0x000001F0 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \ + 0x0000000C + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \ + 0x00000002 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS4 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \ + 0x20000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \ + 0x1FFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS5 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS6 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \ + 0x80000000 // Override for ANA DCDC EN + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \ + 0x20000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \ + 0x10000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \ + 0x08000000 // Override for ANA DCDC PWM + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \ + 0x04000000 // Override for ANA DCDC SLP + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \ + 0x02000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \ + 0x01000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \ + 0x00800000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \ + 0x00400000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \ + 0x00200000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \ + 0x001E0000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \ + 0x00018000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \ + 0x00006000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \ + 0x00001000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \ + 0x00000F00 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \ + 0x000000F0 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \ + 0x0000000F + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \ + 0x0C000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \ + 0x03000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \ + 0x00F00000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \ + 0x00008000 // (Earlier SHOOTTHRU CTRL) + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \ + 0x00004000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \ + 0x00003E00 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \ + 0x00000100 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \ + 0x00000080 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \ + 0x00000060 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \ + 0x00000010 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \ + 0x0000000C + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2 +#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \ + 0x00000003 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS16 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \ + 0x00200000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \ + 0x00100000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \ + 0x000FF000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \ + 0x00000C00 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \ + 0x00000200 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \ + 0x00000100 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \ + 0x000000F8 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \ + 0x00000006 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS17 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \ + 0x40000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \ + 0x3FFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS18 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS19 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \ + 0x20000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \ + 0x18000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \ + 0x04000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \ + 0x02000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \ + 0x01000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \ + 0x00800000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \ + 0x00400000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \ + 0x003C0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \ + 0x00020000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \ + 0x00010000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \ + 0x00008000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \ + 0x00004000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \ + 0x00002000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \ + 0x00001000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \ + 0x00000800 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \ + 0x00000400 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \ + 0x00000200 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \ + 0x000001E0 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \ + 0x0000001E + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \ + 0x0F000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \ + 0x00F00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \ + 0x0000F000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \ + 0x00000F00 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \ + 0x000000C0 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \ + 0x00000030 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \ + 0x0000000C + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \ + 0x00000003 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \ + 0xC0000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \ + 0x30000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \ + 0x0C000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \ + 0x03000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \ + 0x00800000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \ + 0x00400000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \ + 0x00200000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \ + 0x001F0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \ + 0x0000F000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \ + 0x00000800 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \ + 0x00000400 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \ + 0x000003FC + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \ + 0x00000003 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \ + 0x20000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \ + 0x1F000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \ + 0x00E00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \ + 0x001C0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \ + 0x0003C000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \ + 0x00003C00 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \ + 0x00000300 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \ + 0x00000080 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \ + 0x00000040 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \ + 0x00000020 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \ + 0x0000001F + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \ + 0x3FFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \ + 0x80000000 + +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \ + 0x7FFFF800 + +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11 +#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \ + 0x000007FF + +#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \ + 0xFFFF0000 + +#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16 +#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \ + 0x00008000 + +#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \ + 0x00007FFF + +#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \ + 0xFFFF0000 + +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16 +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \ + 0x0000E000 + +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13 +#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \ + 0x00001000 + +#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \ + 0x00000FFF + +#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \ + 0x7C000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26 +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \ + 0x03E00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21 +#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \ + 0x001FFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \ + 0xFFFFFFC0 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6 +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \ + 0x00000020 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \ + 0x00000010 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \ + 0x00000008 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \ + 0x00000004 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \ + 0x00000002 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \ + 0xFFFFFFFC + +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \ + 0x00000002 + +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_VTRIM_CFG register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \ + 0xFF000000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \ + 0x00FC0000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \ + 0x0003F000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \ + 0x00000FC0 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \ + 0x0000003F + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \ + 0xFFFF8000 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \ + 0x00007000 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \ + 0x00000E00 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \ + 0x000001C0 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \ + 0x00000038 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \ + 0x00000007 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \ + 0xFFFFFFF8 + +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3 +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \ + 0x00000007 + +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \ + 0xFFFFFFC0 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6 +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \ + 0x00000038 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3 +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \ + 0x00000007 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register. +// +//****************************************************************************** +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \ + 0xFFFFFFF8 + +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3 +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \ + 0x00000007 + +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_CM_OSC_16M_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \ + 0xFFFC0000 + +#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18 +#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \ + 0x00020000 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \ + 0x00010000 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \ + 0x0000FC00 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10 +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \ + 0x000003F0 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4 +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \ + 0x00000008 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \ + 0x00000007 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SOP_SENSE_VALUE register. +// +//****************************************************************************** +#define HIB1P2_SOP_SENSE_VALUE_reserved_M \ + 0xFFFFFF00 + +#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8 +#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \ + 0x000000FF + +#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \ + 0xFF800000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \ + 0x00400000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \ + 0x003FC000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \ + 0x00002000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \ + 0x00001FC0 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \ + 0x00000020 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \ + 0x0000001F + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \ + 0xFFFFFFFF // Corresponds to ROW_12 of + // FUSEFARM. [7:0] : + // DCDC_DIG_ILIM_TRIM_LOWV(7:0) + // [15:8] : + // DCDC_ANA_ILIM_TRIM_LOWV(7:0) + // [23:16] : + // DCDC_FLASH_ILIM_TRIM_LOWV(7:0) + // [24:24] : DTHE SHA DISABLE + // [25:25] : DTHE DES DISABLE + // [26:26] : DTHE AES DISABLE + // [31:27] : HD_BG_RTRIM (4:0) + +#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \ + 0xFFFFFFFF // Corresponds to ROW_13 of the + // FUSEFARM. [7:0] : HD_BG_MAG_TRIM + // (7:0) [14:8] : HD_BG_TEMP_TRIM + // (6:0) [15:15] : GREYOUT ENABLE + // DUTY CYCLING [31:16] : + // Reserved/Checksum + +#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_POR_TEST_CTRL register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \ + 0xFFFFFF00 + +#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8 +#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \ + 0x000000FF + +#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \ + 0x0000FF00 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \ + 0x000000FE + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \ + 0xFFF00000 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \ + 0x000FFFFF + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \ + 0xFFFFFE00 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9 +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \ + 0x00000100 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \ + 0x000000FC + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2 +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \ + 0x00000002 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16 +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16 +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \ + 0xFFFFF000 + +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12 +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \ + 0x00000FFF + +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register. +// +//****************************************************************************** +#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \ + 0xFF000000 + +#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24 +#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \ + 0x00FF0000 + +#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16 +#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \ + 0x0000FFFF + +#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PORPOL_SPARE register. +// +//****************************************************************************** +#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \ + 0xFFFFFFFF + +#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \ + 0x00000002 + +#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \ + 0x00000002 + +#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_HIB_FSM_DEBUG register. +// +//****************************************************************************** +#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \ + 0x00000700 + +#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8 +#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \ + 0x000000F0 + +#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4 +#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \ + 0x0000000F + +#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \ + 0x000FFFFF + +#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register. +// +//****************************************************************************** +#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \ + 0x00000002 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_CM_TEST_MODE register. +// +//****************************************************************************** +#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \ + 0x00000001 + + + + +#endif // __HW_HIB1P2_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib3p3.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib3p3.h new file mode 100755 index 00000000000..93c385e761e --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_hib3p3.h @@ -0,0 +1,1136 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_HIB3P3_H__ +#define __HW_HIB3P3_H__ + +//***************************************************************************** +// +// The following are defines for the HIB3P3 register offsets. +// +//***************************************************************************** +#define HIB3P3_O_MEM_HIB_REQ 0x00000000 +#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \ + 0x00000004 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \ + 0x00000008 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \ + 0x0000000C + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \ + 0x00000010 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \ + 0x00000014 + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \ + 0x00000018 + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \ + 0x0000001C + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \ + 0x00000020 + +#define HIB3P3_O_MEM_INT_OSC_CONF \ + 0x0000002C + +#define HIB3P3_O_MEM_XTAL_OSC_CONF \ + 0x00000034 + +#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \ + 0x00000038 + +#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \ + 0x0000003C + +#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \ + 0x00000040 + +#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \ + 0x00000044 + +#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050 +#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \ + 0x00000054 + +#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \ + 0x00000058 + +#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \ + 0x0000005C + +#define HIB3P3_O_MEM_HIB_UART_CONF \ + 0x00000400 + +#define HIB3P3_O_MEM_GPIO_WAKE_EN \ + 0x00000404 + +#define HIB3P3_O_MEM_GPIO_WAKE_CONF \ + 0x00000408 + +#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \ + 0x0000040C + +#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \ + 0x00000410 + +#define HIB3P3_O_MEM_JTAG_CONF 0x00000414 +#define HIB3P3_O_MEM_HIB_REG0 0x00000418 +#define HIB3P3_O_MEM_HIB_REG1 0x0000041C +#define HIB3P3_O_MEM_HIB_REG2 0x00000420 +#define HIB3P3_O_MEM_HIB_REG3 0x00000424 +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \ + 0x0000045C + +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \ + 0x00000460 + +#define HIB3P3_O_MEM_HIB_MISC_CONFIG \ + 0x00000464 + +#define HIB3P3_O_MEM_HIB_WAKE_STATUS \ + 0x00000468 + +#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \ + 0x0000046C + +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \ + 0x00000470 + +#define HIB3P3_O_HIBANA_SPARE_LOWV \ + 0x00000474 + +#define HIB3P3_O_HIB_TMUX_CTRL 0x00000478 +#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \ + 0x0000047C + +#define HIB3P3_O_HIB_COMP_TRIM 0x00000480 +#define HIB3P3_O_HIB_EN_TS 0x00000484 +#define HIB3P3_O_HIB_1P8V_DET_EN \ + 0x00000488 + +#define HIB3P3_O_HIB_VBAT_MON_EN \ + 0x0000048C + +#define HIB3P3_O_HIB_NHIB_ENABLE \ + 0x00000490 + +#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \ + 0x00000494 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REQ register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REQ_reserved_M \ + 0xFFFFFE00 + +#define HIB3P3_MEM_HIB_REQ_reserved_S 9 +#define HIB3P3_MEM_HIB_REQ_NU1_M \ + 0x000001FC + +#define HIB3P3_MEM_HIB_REQ_NU1_S 2 +#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \ + 0x00000002 // 1 - Specifies that the Hiberante + // mode is without clocks ; 0 - + // Specified that the Hibernate mode + // is with clocks This register will + // be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +#define HIB3P3_MEM_HIB_REQ_mem_hib_req \ + 0x00000001 // 1 - Request for hibernate mode + // (This is an auto-clear bit) ; 0 - + // Donot request for hibernate mode + // This register will be reset + // during Hibernate -WO-Clks mode + // (but not during Hibernate-W-Clks + // mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \ + 0x00000001 // 1 - Enable the RTC timer to + // start running ; 0 - Keep the RTC + // timer disabled This register will + // be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \ + 0x00000001 // 1 - Reset the RTC timer ; 0 - + // Donot reset the RTC timer. This + // is an auto-clear bit. This + // register will be reset during + // Hibernate -WO-Clks mode (but not + // during Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \ + 0x00000001 // 1 - Latch the running RTC timer + // into local registers. After + // programming this bit to 1, the + // F/w can read the latched RTC + // timer values from + // MEM_HIB_RTC_TIMER_LSW and + // MEM_HIB_RTC_TIMER_MSW. Before the + // F/w (APPS or NWP) wants to read + // the RTC-Timer, it has to program + // this bit to 1, then only read the + // MSW and LSW values. This is an + // auto-clear bit. This register + // will be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \ + 0xFFFFFFFF // Lower 32b value of the latched + // RTC-Timer. + +#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16 +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \ + 0x0000FFFF // Upper 32b value of the latched + // RTC-Timer. + +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \ + 0x00000001 // 1 - Enable the RTC timer based + // wakeup during Hibernate mode ; 0 + // - Disable the RTC timer based + // wakeup during Hibernate mode This + // register will be reset during + // Hibernate-WO-Clks mode (but not + // during Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \ + 0xFFFFFFFF // Configuration for RTC-Timer + // Wakeup (Lower 32b word) + +#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16 +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \ + 0x0000FFFF // Configuration for RTC-Timer + // Wakeup (Upper 16b word) + +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_INT_OSC_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16 +#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \ + 0x00008000 // 1 - Internal 32kHz Oscillator is + // valid ; 0 - Internal 32k + // oscillator clk is not valid + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \ + 0x00007E00 + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9 +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \ + 0x00000100 // When 1, the INT_32K_OSC_EN comes + // from bit [0] of this register, + // else comes from the FSM. This + // register will be reset during + // Hibernate-WO-Clks mode (but not + // during Hibernate-W-Clks mode) + +#define HIB3P3_MEM_INT_OSC_CONF_NU1 \ + 0x00000080 + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \ + 0x0000007E + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1 +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \ + 0x00000001 // Override value for INT_OSC_EN. + // Applicable only when bit [3] of + // this register is set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_XTAL_OSC_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \ + 0xFFF00000 + +#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \ + 0x00080000 // When 1, the SLICER_EN comes from + // bit [10] of this register, else + // comes from the FSM. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \ + 0x00040000 // When 1, the XTAL_EN comes from + // bit [0] of this register, else + // comes from the FSM. + +#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \ + 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL + // Clk is yet to be valid. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \ + 0x0001F800 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \ + 0x00000400 // SLICER_EN Override value : + // Applicable only when bit [19] of + // this register is set to 1. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \ + 0x00000380 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \ + 0x00000070 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \ + 0x00000008 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \ + 0x00000006 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \ + 0x00000001 // XTAL_EN Override value : + // Applicable only when bit [18] of + // this register is set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_BGAP_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \ + 0xFFF80000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19 +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \ + 0x00040000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \ + 0x0001C000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14 +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \ + 0x00001000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \ + 0x00000800 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \ + 0x00000400 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \ + 0x000003FF + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_BGAP_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \ + 0xE0000000 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29 +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \ + 0x1F000000 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24 +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \ + 0x00000008 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \ + 0x00000004 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \ + 0x00000002 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_DETECTION_STATUS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \ + 0xFFFFFF80 + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7 +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \ + 0x00000040 // 1 - 1.8 V supply forced mode. + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \ + 0x00000004 // 1 - 3.3 V supply forced mode for + // Flash supply + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \ + 0x00000002 // 1 - Forced clock mode + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \ + 0x00000001 // 1 - XTAL clock mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_MISC_CONTROLS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \ + 0xFFFFF800 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11 +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \ + 0x00000400 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \ + 0x00000200 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \ + 0x000001C0 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6 +#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \ + 0x00000020 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \ + 0x00000010 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_CONFIG register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \ + 0xFF000000 + +#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24 +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \ + 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD + // for digital path (SHARED4) ; 0 - + // Disable VDD_FLASH_INDP_PAD for + // digital path (SHARED4) ; Before + // programming this bit to 1, ensure + // that the device is in FORCED 3.3 + // supply Mode, which can be + // inferred from the register : + // MEM_HIB_DETECTION_STATUS : 0x0040 + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \ + 0x00040000 // 1 - Enable the + // VDD_FB_GPIO_MUX_PAD for digital + // path (SHARED3) ; 0 - Disable the + // VDD_FB_GPIO_MUX_PAD for digital + // path (SHARED3) ; This pin can be + // used only in modes other than + // SOP("111") + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \ + 0x00020000 // 1 - Enable the PM_TEST_PAD for + // digital GPIO path (SHARED2) ; 0 - + // Disable the PM_TEST_PAD for + // digital GPIO path (SHARED2) This + // pin can be used for digital only + // in modes other then SOP-111 + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \ + 0x00010000 // 1 - Enable the XTAL_N pin + // digital GPIO path (SHARED1); 0 - + // Disable the XTAL_N pin digital + // GPIO path (SHARED1). Before + // programming this bit to 1, ensure + // that the device is in FORCED CLK + // Mode, which can inferred from the + // register : + // MEM_HIB_DETECTION_STATUS : + // 0x0040. + +#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \ + 0x00000100 // 1 - Enable the XTAL Clock ; 0 - + // Donot enable the XTAL Clock. This + // bit has to be programmed to 1 (by + // APPS Devinit F/w), during exit + // from OFF or Hib_wo_clks modes, + // after checking if the slow_clk + // mode is XTAL_CLK mode. Once + // enabled the XTAL will be disabled + // only after entering HIB_WO_CLKS + // mode. This register will be reset + // during Hibernate -WO-Clks mode + // (but not during Hibernate-W-Clks + // mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \ + 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0 + // - Disable the HIB RTC - IRQ + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \ + 0xFFFFFFFF // Configuration for LSW of the + // RTC-Timestamp at which interrupt + // need to be generated + +#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \ + 0x0000FFFF // Configuration for MSW of thr + // RTC-Timestamp at which the + // interrupt need to be generated + +#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_UART_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1 +#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \ + 0x00000001 // 1 - Enable the UART-Autonomous + // mode wakeup during Hibernate mode + // ; This is an auto-clear bit, once + // programmed to 1, it will latched + // into an internal register which + // remain asserted until the + // Hib-wakeup is initiated. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_GPIO_WAKE_EN register. +// +//****************************************************************************** +#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \ + 0xFFFFFF00 + +#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8 +#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \ + 0x000000FF // 1 - Enable the GPIO-Autonomous + // mode wakeup during Hibernate mode + // ; This is an auto-clear bit, once + // programmed to 1, it will latched + // into an internal register which + // remain asserted until the + // Hib-wakeup is initiated. + +#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16 +#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \ + 0x0000FFFF // Configuration to say whether the + // GPIO wakeup has to happen on + // Level0 or falling-edge for the + // given group. “00� – Level0 “01� – + // Level1 “10�- Fall-edge “11�- + // Rise-edge [1:0] – Conf for GPIO0 + // [3:2] – Conf for GPIO1 [5:4] – + // Conf for GPIO2 [7:6] – Conf for + // GPIO3 [9:8] – Conf for GPIO4 + // [11:10] – Conf for GPIO5 [13:12] + // – Conf for GPIO6 + +#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \ + 0x00000004 // 1 - Override the OEN33 and RET33 + // controls of GPIOs during + // SOP-Bootdebug mode ; 0 - Donot + // override the OEN33 and RET33 + // controls of GPIOs during + // SOP-Bootdebug mode + +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \ + 0x00000004 // 1 - Override the OEN33 and RET33 + // controls of UART NRTS GPIO during + // SOP-Bootdebug mode ; 0 - Donot + // override the OEN33 and RET33 + // controls of UART NRTS GPIO during + // SOP-Bootdebug mode + +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_JTAG_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \ + 0x00000200 + +#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \ + 0x00000100 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \ + 0x00000008 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \ + 0x00000004 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG2 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG3 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \ + 0xFFFF0000 // Configuration for the number of + // slow-clks between de-assertion of + // EN_BG_3P3V to assertion of + // EN_BG_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \ + 0x00008000 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \ + 0x00006000 // Configuration for the number of + // slow-clks between assertion of + // EN_COMP_3P3V and assertion of + // EN_COMP_LATCH_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \ + 0x00001800 // Configuration for the number of + // slow-clks between assertion of + // (EN_CAP_SW_3P3V,EN_COMP_REF) and + // assertion of (EN_COMP_3P3V) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \ + 0x00000600 // Configuration for the number of + // slow-clks between assertion of + // (EN_BG_3P3V) and assertion of + // (EN_CAP_SW_3P3V, + // EN_COMP_REF_3P3V) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \ + 0x00000100 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \ + 0x00000080 // 1 - EN_VBOK4BG_REF comes from + // bit[10] of the register + // MEM_BGAP_PARAMETERS0 [0x0038]. 0 + // - EN_VBOK4BG_REF comes directly + // from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \ + 0x00000040 // 1 - EN_VBOK4BG comes from + // bit[11] of the register + // MEM_BGAP_PARAMETERS0 [0x0038]. 0 + // - EN_VBOK4BG comes directly from + // the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \ + 0x00000020 // 1 - EN_V2I comes from bit[2] of + // the register MEM_BGAP_PARAMETERS1 + // [0x003C]. 0 - EN_V2I comes + // directly from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \ + 0x00000010 // 1 - EN_POR_COMP_REF comes from + // bit[9] of the register + // MEM_HIB_MISC_CONTROLS [0x0044]. 0 + // - EN_POR_COMP_REF comes directly + // from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \ + 0x00000008 // 1 - EN_POR_COMP comes from + // bit[10] of the register + // MEM_HIB_MISC_CONTROLS [0x044]. 0 + // - EN_POR_COMP comes directly from + // the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \ + 0x00000004 // 1 - EN_CAP_SW comes from bit[1] + // of the register + // MEM_BGAP_PARAMETERS1 [0x003C]. 0 + // - EN_CAP_SW comes directly from + // Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \ + 0x00000002 // 1 - EN_BGAP comes from bit[0] of + // the register MEM_BGAP_PARAMETERS1 + // [0x003C]. 0 - EN_BGAP comes + // directly from Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \ + 0x0000C000 // Configuration for number of + // slow-clks between de-assertion of + // EN_COMP_LATCH and assertion of + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \ + 0x00003000 // Configuration for number of + // slow-clks between assertion of + // EN_COMP_REF to assertion of + // EN_COMP during HIB-Exit + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \ + 0x00000C00 // TBD + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \ + 0x00000300 // Configuration in number of + // slow-clks between assertion of + // (EN_BGAP_3P3V, EN_CAP_SW_3P3V, + // EN_ACT_IREF_3P3V, EN_COMP_REF) to + // assertion of EN_COMP_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \ + 0x000000C0 // Configuration in number of + // slow-clks between de-assertion of + // (EN_COMP_3P3V, EN_COMP_REF_3P3V, + // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V) + // to deassertion of EN_BGAP_3P3V. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \ + 0x0000003F + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_MISC_CONFIG register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_WAKE_STATUS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \ + 0x0000001E // "0100" - GPIO ; "0010" - RTC ; + // "0001" - UART Others - Reserved + +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1 +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \ + 0x00000001 // 1 - Wake from Hibernate ; 0 - + // Wake from OFF + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \ + 0x00000007 + +#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \ + 0xFFFFF800 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \ + 0x00000600 // Deassertion of EN_COMP_LATCH_3P3 + // to deassertion of (EN_COMP_3P3, + // EN_COMP_REF_3P3, EN_ACT_IREF_3P3, + // EN_CAP_SW_3P3) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \ + 0x000001C0 // Assertion of EN_COMP_LATCH_3P3 + // to deassertion of + // EN_COMP_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \ + 0x00000030 // Deassertion of (EN_CAP_SW_3P3, + // EN_COMP_REF_3P3, EN_COMP_3P3, + // EN_COMP_OUT_LATCH_3P3) to + // deassertion of EN_BGAP_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \ + 0x0000000C // Assertion of EN_COMP_3P3 to + // assertion of EN_COMPOUT_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \ + 0x00000003 // Assertion of EN_COMP_3P3 to + // assertion of EN_COMPOUT_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIBANA_SPARE_LOWV register. +// +//****************************************************************************** +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \ + 0xFFC00000 + +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22 +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \ + 0x0001FFFF + +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_TMUX_CTRL register. +// +//****************************************************************************** +#define HIB3P3_HIB_TMUX_CTRL_reserved_M \ + 0xFFFFFC00 + +#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10 +#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \ + 0x000003FF + +#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register. +// +//****************************************************************************** +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \ + 0xFFFFF000 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12 +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \ + 0x00000800 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \ + 0x00000400 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \ + 0x00000200 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \ + 0x00000100 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \ + 0x000000F0 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4 +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \ + 0x0000000F + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_COMP_TRIM register. +// +//****************************************************************************** +#define HIB3P3_HIB_COMP_TRIM_reserved_M \ + 0xFFFFFFF8 + +#define HIB3P3_HIB_COMP_TRIM_reserved_S 3 +#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \ + 0x00000007 + +#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_EN_TS register. +// +//****************************************************************************** +#define HIB3P3_HIB_EN_TS_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_HIB_EN_TS_reserved_S 1 +#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_1P8V_DET_EN register. +// +//****************************************************************************** +#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1 +#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_VBAT_MON_EN register. +// +//****************************************************************************** +#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \ + 0xFFFFFFFC + +#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2 +#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \ + 0x00000002 + +#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_NHIB_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \ + 0x00000001 + + + + +#endif // __HW_HIB3P3_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_i2c.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_i2c.h new file mode 100755 index 00000000000..5a8246a615f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_i2c.h @@ -0,0 +1,501 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 +#define I2C_O_MCS 0x00000004 +#define I2C_O_MDR 0x00000008 +#define I2C_O_MTPR 0x0000000C +#define I2C_O_MIMR 0x00000010 +#define I2C_O_MRIS 0x00000014 +#define I2C_O_MMIS 0x00000018 +#define I2C_O_MICR 0x0000001C +#define I2C_O_MCR 0x00000020 +#define I2C_O_MCLKOCNT 0x00000024 +#define I2C_O_MBMON 0x0000002C +#define I2C_O_MBLEN 0x00000030 +#define I2C_O_MBCNT 0x00000034 +#define I2C_O_SOAR 0x00000800 +#define I2C_O_SCSR 0x00000804 +#define I2C_O_SDR 0x00000808 +#define I2C_O_SIMR 0x0000080C +#define I2C_O_SRIS 0x00000810 +#define I2C_O_SMIS 0x00000814 +#define I2C_O_SICR 0x00000818 +#define I2C_O_SOAR2 0x0000081C +#define I2C_O_SACKCTL 0x00000820 +#define I2C_O_FIFODATA 0x00000F00 +#define I2C_O_FIFOCTL 0x00000F04 +#define I2C_O_FIFOSTATUS 0x00000F08 +#define I2C_O_OBSMUXSEL0 0x00000F80 +#define I2C_O_OBSMUXSEL1 0x00000F84 +#define I2C_O_MUXROUTE 0x00000F88 +#define I2C_O_PV 0x00000FB0 +#define I2C_O_PP 0x00000FC0 +#define I2C_O_PC 0x00000FC4 +#define I2C_O_CC 0x00000FC8 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//****************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_SA_S 1 +#define I2C_MSA_RS 0x00000001 // Receive not send +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//****************************************************************************** +#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_BUSY 0x00000001 // I2C Busy +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//****************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // Data Transferred +#define I2C_MDR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//****************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period +#define I2C_MTPR_TPR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//****************************************************************************** +#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt + // Mask +#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask +#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask +#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//****************************************************************************** +#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt + // Status +#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt + // Status +#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt + // Status +#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt + // Status +#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt + // Status +#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt + // Status +#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt + // Status +#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//****************************************************************************** +#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask +#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask +#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status +#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//****************************************************************************** +#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt + // Clear +#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt + // Clear +#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt + // Clear +#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt + // Clear +#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear +#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear +#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear +#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt + // Clear +#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear +#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//****************************************************************************** +#define I2C_MCR_MMD 0x00000040 // Multi-master Disable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//****************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//****************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBLEN register. +// +//****************************************************************************** +#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length +#define I2C_MBLEN_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBCNT register. +// +//****************************************************************************** +#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count +#define I2C_MBCNT_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//****************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//****************************************************************************** +#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write +#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//****************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//****************************************************************************** +#define I2C_SIMR_IM 0x00000100 // Interrupt Mask +#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask +#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//****************************************************************************** +#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status +#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt + // Status +#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt + // Status +#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//****************************************************************************** +#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt + // Status +#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt + // Status +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//****************************************************************************** +#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask +#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask +#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear +#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//****************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//****************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFODATA register. +// +//****************************************************************************** +#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte +#define I2C_FIFODATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOCTL register. +// +//****************************************************************************** +#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment +#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush +#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable +#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger +#define I2C_FIFOCTL_RXTRIG_S 16 +#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment +#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush +#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable +#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger +#define I2C_FIFOCTL_TXTRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register. +// +//****************************************************************************** +#define I2C_FIFOSTATUS_RXABVTRIG \ + 0x00040000 // RX FIFO Above Trigger Level + +#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full +#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty +#define I2C_FIFOSTATUS_TXBLWTRIG \ + 0x00000004 // TX FIFO Below Trigger Level + +#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full +#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register. +// +//****************************************************************************** +#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3 +#define I2C_OBSMUXSEL0_LN3_S 24 +#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2 +#define I2C_OBSMUXSEL0_LN2_S 16 +#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1 +#define I2C_OBSMUXSEL0_LN1_S 8 +#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0 +#define I2C_OBSMUXSEL0_LN0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register. +// +//****************************************************************************** +#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7 +#define I2C_OBSMUXSEL1_LN7_S 24 +#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6 +#define I2C_OBSMUXSEL1_LN6_S 16 +#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5 +#define I2C_OBSMUXSEL1_LN5_S 8 +#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4 +#define I2C_OBSMUXSEL1_LN4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MUXROUTE register. +// +//****************************************************************************** +#define I2C_MUXROUTE_LN7ROUTE_M \ + 0x70000000 // Lane 7 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN7ROUTE_S 28 +#define I2C_MUXROUTE_LN6ROUTE_M \ + 0x07000000 // Lane 6 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN6ROUTE_S 24 +#define I2C_MUXROUTE_LN5ROUTE_M \ + 0x00700000 // Lane 5 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN5ROUTE_S 20 +#define I2C_MUXROUTE_LN4ROUTE_M \ + 0x00070000 // Lane 4 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN4ROUTE_S 16 +#define I2C_MUXROUTE_LN3ROUTE_M \ + 0x00007000 // Lane 3 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN3ROUTE_S 12 +#define I2C_MUXROUTE_LN2ROUTE_M \ + 0x00000700 // Lane 2 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN2ROUTE_S 8 +#define I2C_MUXROUTE_LN1ROUTE_M \ + 0x00000070 // Lane 1 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN1ROUTE_S 4 +#define I2C_MUXROUTE_LN0ROUTE_M \ + 0x00000007 // Lane 0 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN0ROUTE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PV register. +// +//****************************************************************************** +#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision +#define I2C_PV_MAJOR_S 8 +#define I2C_PV_MINOR_M 0x000000FF // Minor Revision +#define I2C_PV_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//****************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//****************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_CC register. +// +//****************************************************************************** + + + +#endif // __HW_I2C_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ints.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ints.h new file mode 100755 index 00000000000..59da049796a --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ints.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on CC3200. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA0 16 // GPIO Port S0 +#define INT_GPIOA1 17 // GPIO Port S1 +#define INT_GPIOA2 18 // GPIO Port S2 +#define INT_GPIOA3 19 // GPIO Port S3 +#define INT_UARTA0 21 // UART0 Rx and Tx +#define INT_UARTA1 22 // UART1 Rx and Tx +#define INT_I2CA0 24 // I2C controller +#define INT_ADCCH0 30 // ADC Sequence 0 +#define INT_ADCCH1 31 // ADC Sequence 1 +#define INT_ADCCH2 32 // ADC Sequence 2 +#define INT_ADCCH3 33 // ADC Sequence 3 +#define INT_WDT 34 // Watchdog Timer0 +#define INT_TIMERA0A 35 // Timer 0 subtimer A +#define INT_TIMERA0B 36 // Timer 0 subtimer B +#define INT_TIMERA1A 37 // Timer 1 subtimer A +#define INT_TIMERA1B 38 // Timer 1 subtimer B +#define INT_TIMERA2A 39 // Timer 2 subtimer A +#define INT_TIMERA2B 40 // Timer 2 subtimer B +#define INT_FLASH 45 // FLASH Control +#define INT_TIMERA3A 51 // Timer 3 subtimer A +#define INT_TIMERA3B 52 // Timer 3 subtimer B +#define INT_UDMA 62 // uDMA controller +#define INT_UDMAERR 63 // uDMA Error +#define INT_SHA 164 // SHA +#define INT_AES 167 // AES +#define INT_DES 169 // DES +#define INT_MMCHS 175 // SDIO +#define INT_I2S 177 // McAPS +#define INT_CAMERA 179 // Camera +#define INT_NWPIC 187 // Interprocessor communication +#define INT_PRCM 188 // Power, Reset and Clock Module +#define INT_SSPI 191 // Shared SPI +#define INT_GSPI 192 // Generic SPI +#define INT_LSPI 193 // Link SPI + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 195 //The above number plus 2? + + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + + +#endif // __HW_INTS_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcasp.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcasp.h new file mode 100755 index 00000000000..ec6e483dc4c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcasp.h @@ -0,0 +1,1704 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_MCASP_H__ +#define __HW_MCASP_H__ + +//***************************************************************************** +// +// The following are defines for the MCASP register offsets. +// +//***************************************************************************** +#define MCASP_O_PID 0x00000000 +#define MCASP_O_ESYSCONFIG 0x00000004 // Power Idle SYSCONFIG register. +#define MCASP_O_PFUNC 0x00000010 +#define MCASP_O_PDIR 0x00000014 +#define MCASP_O_PDOUT 0x00000018 +#define MCASP_O_PDSET 0x0000001C // The pin data set register + // (PDSET) is an alias of the pin + // data output register (PDOUT) for + // writes only. Writing a 1 to the + // PDSET bit sets the corresponding + // bit in PDOUT and if PFUNC = 1 + // (GPIO function) and PDIR = 1 + // (output) drives a logic high on + // the pin. +#define MCASP_O_PDIN 0x0000001C // The pin data input register + // (PDIN) holds the I/O pin state of + // each of the McASP pins. PDIN + // allows the actual value of the + // pin to be read regardless of the + // state of PFUNC and PDIR. +#define MCASP_O_PDCLR 0x00000020 // The pin data clear register + // (PDCLR) is an alias of the pin + // data output register (PDOUT) for + // writes only. Writing a 1 to the + // PDCLR bit clears the + // corresponding bit in PDOUT and if + // PFUNC = 1 (GPIO function) and + // PDIR = 1 (output) drives a logic + // low on the pin. +#define MCASP_O_TLGC 0x00000030 // for IODFT +#define MCASP_O_TLMR 0x00000034 // for IODFT +#define MCASP_O_TLEC 0x00000038 // for IODFT +#define MCASP_O_GBLCTL 0x00000044 +#define MCASP_O_AMUTE 0x00000048 +#define MCASP_O_LBCTL 0x0000004C +#define MCASP_O_TXDITCTL 0x00000050 +#define MCASP_O_GBLCTLR 0x00000060 +#define MCASP_O_RXMASK 0x00000064 +#define MCASP_O_RXFMT 0x00000068 +#define MCASP_O_RXFMCTL 0x0000006C +#define MCASP_O_ACLKRCTL 0x00000070 +#define MCASP_O_AHCLKRCTL 0x00000074 +#define MCASP_O_RXTDM 0x00000078 +#define MCASP_O_EVTCTLR 0x0000007C +#define MCASP_O_RXSTAT 0x00000080 +#define MCASP_O_RXTDMSLOT 0x00000084 +#define MCASP_O_RXCLKCHK 0x00000088 +#define MCASP_O_REVTCTL 0x0000008C +#define MCASP_O_GBLCTLX 0x000000A0 +#define MCASP_O_TXMASK 0x000000A4 +#define MCASP_O_TXFMT 0x000000A8 +#define MCASP_O_TXFMCTL 0x000000AC +#define MCASP_O_ACLKXCTL 0x000000B0 +#define MCASP_O_AHCLKXCTL 0x000000B4 +#define MCASP_O_TXTDM 0x000000B8 +#define MCASP_O_EVTCTLX 0x000000BC +#define MCASP_O_TXSTAT 0x000000C0 +#define MCASP_O_TXTDMSLOT 0x000000C4 +#define MCASP_O_TXCLKCHK 0x000000C8 +#define MCASP_O_XEVTCTL 0x000000CC +#define MCASP_O_CLKADJEN 0x000000D0 +#define MCASP_O_DITCSRA0 0x00000100 +#define MCASP_O_DITCSRA1 0x00000104 +#define MCASP_O_DITCSRA2 0x00000108 +#define MCASP_O_DITCSRA3 0x0000010C +#define MCASP_O_DITCSRA4 0x00000110 +#define MCASP_O_DITCSRA5 0x00000114 +#define MCASP_O_DITCSRB0 0x00000118 +#define MCASP_O_DITCSRB1 0x0000011C +#define MCASP_O_DITCSRB2 0x00000120 +#define MCASP_O_DITCSRB3 0x00000124 +#define MCASP_O_DITCSRB4 0x00000128 +#define MCASP_O_DITCSRB5 0x0000012C +#define MCASP_O_DITUDRA0 0x00000130 +#define MCASP_O_DITUDRA1 0x00000134 +#define MCASP_O_DITUDRA2 0x00000138 +#define MCASP_O_DITUDRA3 0x0000013C +#define MCASP_O_DITUDRA4 0x00000140 +#define MCASP_O_DITUDRA5 0x00000144 +#define MCASP_O_DITUDRB0 0x00000148 +#define MCASP_O_DITUDRB1 0x0000014C +#define MCASP_O_DITUDRB2 0x00000150 +#define MCASP_O_DITUDRB3 0x00000154 +#define MCASP_O_DITUDRB4 0x00000158 +#define MCASP_O_DITUDRB5 0x0000015C +#define MCASP_O_XRSRCTL0 0x00000180 +#define MCASP_O_XRSRCTL1 0x00000184 +#define MCASP_O_XRSRCTL2 0x00000188 +#define MCASP_O_XRSRCTL3 0x0000018C +#define MCASP_O_XRSRCTL4 0x00000190 +#define MCASP_O_XRSRCTL5 0x00000194 +#define MCASP_O_XRSRCTL6 0x00000198 +#define MCASP_O_XRSRCTL7 0x0000019C +#define MCASP_O_XRSRCTL8 0x000001A0 +#define MCASP_O_XRSRCTL9 0x000001A4 +#define MCASP_O_XRSRCTL10 0x000001A8 +#define MCASP_O_XRSRCTL11 0x000001AC +#define MCASP_O_XRSRCTL12 0x000001B0 +#define MCASP_O_XRSRCTL13 0x000001B4 +#define MCASP_O_XRSRCTL14 0x000001B8 +#define MCASP_O_XRSRCTL15 0x000001BC +#define MCASP_O_TXBUF0 0x00000200 +#define MCASP_O_TXBUF1 0x00000204 +#define MCASP_O_TXBUF2 0x00000208 +#define MCASP_O_TXBUF3 0x0000020C +#define MCASP_O_TXBUF4 0x00000210 +#define MCASP_O_TXBUF5 0x00000214 +#define MCASP_O_TXBUF6 0x00000218 +#define MCASP_O_TXBUF7 0x0000021C +#define MCASP_O_TXBUF8 0x00000220 +#define MCASP_O_TXBUF9 0x00000224 +#define MCASP_O_TXBUF10 0x00000228 +#define MCASP_O_TXBUF11 0x0000022C +#define MCASP_O_TXBUF12 0x00000230 +#define MCASP_O_TXBUF13 0x00000234 +#define MCASP_O_TXBUF14 0x00000238 +#define MCASP_O_TXBUF15 0x0000023C +#define MCASP_O_RXBUF0 0x00000280 +#define MCASP_O_RXBUF1 0x00000284 +#define MCASP_O_RXBUF2 0x00000288 +#define MCASP_O_RXBUF3 0x0000028C +#define MCASP_O_RXBUF4 0x00000290 +#define MCASP_O_RXBUF5 0x00000294 +#define MCASP_O_RXBUF6 0x00000298 +#define MCASP_O_RXBUF7 0x0000029C +#define MCASP_O_RXBUF8 0x000002A0 +#define MCASP_O_RXBUF9 0x000002A4 +#define MCASP_O_RXBUF10 0x000002A8 +#define MCASP_O_RXBUF11 0x000002AC +#define MCASP_O_RXBUF12 0x000002B0 +#define MCASP_O_RXBUF13 0x000002B4 +#define MCASP_O_RXBUF14 0x000002B8 +#define MCASP_O_RXBUF15 0x000002BC +#define MCASP_0_WFIFOCTL 0x00001000 +#define MCASP_0_WFIFOSTS 0x00001004 +#define MCASP_0_RFIFOCTL 0x00001008 +#define MCASP_0_RFIFOSTS 0x0000100C + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PID register. +// +//****************************************************************************** +#define MCASP_PID_SCHEME_M 0xC0000000 +#define MCASP_PID_SCHEME_S 30 +#define MCASP_PID_RESV_M 0x30000000 +#define MCASP_PID_RESV_S 28 +#define MCASP_PID_FUNCTION_M 0x0FFF0000 // McASP +#define MCASP_PID_FUNCTION_S 16 +#define MCASP_PID_RTL_M 0x0000F800 +#define MCASP_PID_RTL_S 11 +#define MCASP_PID_REVMAJOR_M 0x00000700 +#define MCASP_PID_REVMAJOR_S 8 +#define MCASP_PID_CUSTOM_M 0x000000C0 // non-custom +#define MCASP_PID_CUSTOM_S 6 +#define MCASP_PID_REVMINOR_M 0x0000003F +#define MCASP_PID_REVMINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCASP_O_ESYSCONFIG register. +// +//****************************************************************************** +#define MCASP_ESYSCONFIG_RSV_M 0xFFFFFFC0 // Reserved as per PDR 3.5 +#define MCASP_ESYSCONFIG_RSV_S 6 +#define MCASP_ESYSCONFIG_OTHER_M \ + 0x0000003C // Reserved for future expansion + +#define MCASP_ESYSCONFIG_OTHER_S 2 +#define MCASP_ESYSCONFIG_IDLE_MODE_M \ + 0x00000003 // Idle Mode + +#define MCASP_ESYSCONFIG_IDLE_MODE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PFUNC register. +// +//****************************************************************************** +#define MCASP_PFUNC_AFSR 0x80000000 // AFSR PFUNC 31 0 1 +#define MCASP_PFUNC_AHCLKR 0x40000000 // AHCLKR PFUNC 30 0 1 +#define MCASP_PFUNC_ACLKR 0x20000000 // ACLKR PFUNC 29 0 1 +#define MCASP_PFUNC_AFSX 0x10000000 // AFSX PFUNC 28 0 1 +#define MCASP_PFUNC_AHCLKX 0x08000000 // AHCLKX PFUNC 27 0 1 +#define MCASP_PFUNC_ACLKX 0x04000000 // ACLKX PFUNC 26 0 1 +#define MCASP_PFUNC_AMUTE 0x02000000 // AMUTE PFUNC 25 0 1 +#define MCASP_PFUNC_RESV1_M 0x01FF0000 // Reserved +#define MCASP_PFUNC_RESV1_S 16 +#define MCASP_PFUNC_AXR15 0x00008000 // AXR PFUNC BIT 15 0 1 +#define MCASP_PFUNC_AXR14 0x00004000 // AXR PFUNC BIT 14 0 1 +#define MCASP_PFUNC_AXR13 0x00002000 // AXR PFUNC BIT 13 0 1 +#define MCASP_PFUNC_AXR12 0x00001000 // AXR PFUNC BIT 12 0 1 +#define MCASP_PFUNC_AXR11 0x00000800 // AXR PFUNC BIT 11 0 1 +#define MCASP_PFUNC_AXR10 0x00000400 // AXR PFUNC BIT 10 0 1 +#define MCASP_PFUNC_AXR9 0x00000200 // AXR PFUNC BIT 9 0 1 +#define MCASP_PFUNC_AXR8 0x00000100 // AXR PFUNC BIT 8 0 1 +#define MCASP_PFUNC_AXR7 0x00000080 // AXR PFUNC BIT 7 0 1 +#define MCASP_PFUNC_AXR6 0x00000040 // AXR PFUNC BIT 6 0 1 +#define MCASP_PFUNC_AXR5 0x00000020 // AXR PFUNC BIT 5 0 1 +#define MCASP_PFUNC_AXR4 0x00000010 // AXR PFUNC BIT 4 0 1 +#define MCASP_PFUNC_AXR3 0x00000008 // AXR PFUNC BIT 3 0 1 +#define MCASP_PFUNC_AXR2 0x00000004 // AXR PFUNC BIT 2 0 1 +#define MCASP_PFUNC_AXR1 0x00000002 // AXR PFUNC BIT 1 0 1 +#define MCASP_PFUNC_AXR0 0x00000001 // AXR PFUNC BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDIR register. +// +//****************************************************************************** +#define MCASP_PDIR_AFSR 0x80000000 // AFSR PDIR 31 0 1 +#define MCASP_PDIR_AHCLKR 0x40000000 // AHCLKR PDIR 30 0 1 +#define MCASP_PDIR_ACLKR 0x20000000 // ACLKR PDIR 29 0 1 +#define MCASP_PDIR_AFSX 0x10000000 // AFSX PDIR 28 0 1 +#define MCASP_PDIR_AHCLKX 0x08000000 // AHCLKX PDIR 27 0 1 +#define MCASP_PDIR_ACLKX 0x04000000 // ACLKX PDIR 26 0 1 +#define MCASP_PDIR_AMUTE 0x02000000 // AMUTE PDIR 25 0 1 +#define MCASP_PDIR_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDIR_RESV_S 16 +#define MCASP_PDIR_AXR15 0x00008000 // AXR PDIR BIT 15 0 1 +#define MCASP_PDIR_AXR14 0x00004000 // AXR PDIR BIT 14 0 1 +#define MCASP_PDIR_AXR13 0x00002000 // AXR PDIR BIT 13 0 1 +#define MCASP_PDIR_AXR12 0x00001000 // AXR PDIR BIT 12 0 1 +#define MCASP_PDIR_AXR11 0x00000800 // AXR PDIR BIT 11 0 1 +#define MCASP_PDIR_AXR10 0x00000400 // AXR PDIR BIT 10 0 1 +#define MCASP_PDIR_AXR9 0x00000200 // AXR PDIR BIT 9 0 1 +#define MCASP_PDIR_AXR8 0x00000100 // AXR PDIR BIT 8 0 1 +#define MCASP_PDIR_AXR7 0x00000080 // AXR PDIR BIT 7 0 1 +#define MCASP_PDIR_AXR6 0x00000040 // AXR PDIR BIT 6 0 1 +#define MCASP_PDIR_AXR5 0x00000020 // AXR PDIR BIT 5 0 1 +#define MCASP_PDIR_AXR4 0x00000010 // AXR PDIR BIT 4 0 1 +#define MCASP_PDIR_AXR3 0x00000008 // AXR PDIR BIT 3 0 1 +#define MCASP_PDIR_AXR2 0x00000004 // AXR PDIR BIT 2 0 1 +#define MCASP_PDIR_AXR1 0x00000002 // AXR PDIR BIT 1 0 1 +#define MCASP_PDIR_AXR0 0x00000001 // AXR PDIR BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDOUT register. +// +//****************************************************************************** +#define MCASP_PDOUT_AFSR 0x80000000 // AFSR PDOUT 31 0 1 +#define MCASP_PDOUT_AHCLKR 0x40000000 // AHCLKR PDOUT 30 0 1 +#define MCASP_PDOUT_ACLKR 0x20000000 // ACLKR PDOUT 29 0 1 +#define MCASP_PDOUT_AFSX 0x10000000 // AFSX PDOUT 28 0 1 +#define MCASP_PDOUT_AHCLKX 0x08000000 // AHCLKX PDOUT 27 0 1 +#define MCASP_PDOUT_ACLKX 0x04000000 // ACLKX PDOUT 26 0 1 +#define MCASP_PDOUT_AMUTE 0x02000000 // AMUTE PDOUT 25 0 1 +#define MCASP_PDOUT_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDOUT_RESV_S 16 +#define MCASP_PDOUT_AXR15 0x00008000 // AXR PDOUT BIT 15 0 1 +#define MCASP_PDOUT_AXR14 0x00004000 // AXR PDOUT BIT 14 0 1 +#define MCASP_PDOUT_AXR13 0x00002000 // AXR PDOUT BIT 13 0 1 +#define MCASP_PDOUT_AXR12 0x00001000 // AXR PDOUT BIT 12 0 1 +#define MCASP_PDOUT_AXR11 0x00000800 // AXR PDOUT BIT 11 0 1 +#define MCASP_PDOUT_AXR10 0x00000400 // AXR PDOUT BIT 10 0 1 +#define MCASP_PDOUT_AXR9 0x00000200 // AXR PDOUT BIT 9 0 1 +#define MCASP_PDOUT_AXR8 0x00000100 // AXR PDOUT BIT 8 0 1 +#define MCASP_PDOUT_AXR7 0x00000080 // AXR PDOUT BIT 7 0 1 +#define MCASP_PDOUT_AXR6 0x00000040 // AXR PDOUT BIT 6 0 1 +#define MCASP_PDOUT_AXR5 0x00000020 // AXR PDOUT BIT 5 0 1 +#define MCASP_PDOUT_AXR4 0x00000010 // AXR PDOUT BIT 4 0 1 +#define MCASP_PDOUT_AXR3 0x00000008 // AXR PDOUT BIT 3 0 1 +#define MCASP_PDOUT_AXR2 0x00000004 // AXR PDOUT BIT 2 0 1 +#define MCASP_PDOUT_AXR1 0x00000002 // AXR PDOUT BIT 1 0 1 +#define MCASP_PDOUT_AXR0 0x00000001 // AXR PDOUT BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDSET register. +// +//****************************************************************************** +#define MCASP_PDSET_AFSR 0x80000000 +#define MCASP_PDSET_AHCLKR 0x40000000 +#define MCASP_PDSET_ACLKR 0x20000000 +#define MCASP_PDSET_AFSX 0x10000000 +#define MCASP_PDSET_AHCLKX 0x08000000 +#define MCASP_PDSET_ACLKX 0x04000000 +#define MCASP_PDSET_AMUTE 0x02000000 +#define MCASP_PDSET_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDSET_RESV_S 16 +#define MCASP_PDSET_AXR15 0x00008000 +#define MCASP_PDSET_AXR14 0x00004000 +#define MCASP_PDSET_AXR13 0x00002000 +#define MCASP_PDSET_AXR12 0x00001000 +#define MCASP_PDSET_AXR11 0x00000800 +#define MCASP_PDSET_AXR10 0x00000400 +#define MCASP_PDSET_AXR9 0x00000200 +#define MCASP_PDSET_AXR8 0x00000100 +#define MCASP_PDSET_AXR7 0x00000080 +#define MCASP_PDSET_AXR6 0x00000040 +#define MCASP_PDSET_AXR5 0x00000020 +#define MCASP_PDSET_AXR4 0x00000010 +#define MCASP_PDSET_AXR3 0x00000008 +#define MCASP_PDSET_AXR2 0x00000004 +#define MCASP_PDSET_AXR1 0x00000002 +#define MCASP_PDSET_AXR0 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDIN register. +// +//****************************************************************************** +#define MCASP_PDIN_AFSR 0x80000000 +#define MCASP_PDIN_AHCLKR 0x40000000 +#define MCASP_PDIN_ACLKR 0x20000000 +#define MCASP_PDIN_AFSX 0x10000000 +#define MCASP_PDIN_AHCLKX 0x08000000 +#define MCASP_PDIN_ACLKX 0x04000000 +#define MCASP_PDIN_AMUTE 0x02000000 +#define MCASP_PDIN_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDIN_RESV_S 16 +#define MCASP_PDIN_AXR15 0x00008000 +#define MCASP_PDIN_AXR14 0x00004000 +#define MCASP_PDIN_AXR13 0x00002000 +#define MCASP_PDIN_AXR12 0x00001000 +#define MCASP_PDIN_AXR11 0x00000800 +#define MCASP_PDIN_AXR10 0x00000400 +#define MCASP_PDIN_AXR9 0x00000200 +#define MCASP_PDIN_AXR8 0x00000100 +#define MCASP_PDIN_AXR7 0x00000080 +#define MCASP_PDIN_AXR6 0x00000040 +#define MCASP_PDIN_AXR5 0x00000020 +#define MCASP_PDIN_AXR4 0x00000010 +#define MCASP_PDIN_AXR3 0x00000008 +#define MCASP_PDIN_AXR2 0x00000004 +#define MCASP_PDIN_AXR1 0x00000002 +#define MCASP_PDIN_AXR0 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDCLR register. +// +//****************************************************************************** +#define MCASP_PDCLR_AFSR 0x80000000 // AFSR PDCLR 31 0 1 +#define MCASP_PDCLR_AHCLKR 0x40000000 // AHCLKR PDCLR 30 0 1 +#define MCASP_PDCLR_ACLKR 0x20000000 // ACLKR PDCLR 29 0 1 +#define MCASP_PDCLR_AFSX 0x10000000 // AFSX PDCLR 28 0 1 +#define MCASP_PDCLR_AHCLKX 0x08000000 // AHCLKX PDCLR 27 0 1 +#define MCASP_PDCLR_ACLKX 0x04000000 // ACLKX PDCLR 26 0 1 +#define MCASP_PDCLR_AMUTE 0x02000000 // AMUTE PDCLR 25 0 1 +#define MCASP_PDCLR_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDCLR_RESV_S 16 +#define MCASP_PDCLR_AXR15 0x00008000 // AXR PDCLR BIT 15 0 1 +#define MCASP_PDCLR_AXR14 0x00004000 // AXR PDCLR BIT 14 0 1 +#define MCASP_PDCLR_AXR13 0x00002000 // AXR PDCLR BIT 13 0 1 +#define MCASP_PDCLR_AXR12 0x00001000 // AXR PDCLR BIT 12 0 1 +#define MCASP_PDCLR_AXR11 0x00000800 // AXR PDCLR BIT 11 0 1 +#define MCASP_PDCLR_AXR10 0x00000400 // AXR PDCLR BIT 10 0 1 +#define MCASP_PDCLR_AXR9 0x00000200 // AXR PDCLR BIT 9 0 1 +#define MCASP_PDCLR_AXR8 0x00000100 // AXR PDCLR BIT 8 0 1 +#define MCASP_PDCLR_AXR7 0x00000080 // AXR PDCLR BIT 7 0 1 +#define MCASP_PDCLR_AXR6 0x00000040 // AXR PDCLR BIT 6 0 1 +#define MCASP_PDCLR_AXR5 0x00000020 // AXR PDCLR BIT 5 0 1 +#define MCASP_PDCLR_AXR4 0x00000010 // AXR PDCLR BIT 4 0 1 +#define MCASP_PDCLR_AXR3 0x00000008 // AXR PDCLR BIT 3 0 1 +#define MCASP_PDCLR_AXR2 0x00000004 // AXR PDCLR BIT 2 0 1 +#define MCASP_PDCLR_AXR1 0x00000002 // AXR PDCLR BIT 1 0 1 +#define MCASP_PDCLR_AXR0 0x00000001 // AXR PDCLR BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLGC register. +// +//****************************************************************************** +#define MCASP_TLGC_RESV_M 0xFFFF0000 // Reserved +#define MCASP_TLGC_RESV_S 16 +#define MCASP_TLGC_MT_M 0x0000C000 // MISR on/off trigger command 0x0 + // 0x1 0x2 0x3 +#define MCASP_TLGC_MT_S 14 +#define MCASP_TLGC_RESV1_M 0x00003E00 // Reserved +#define MCASP_TLGC_RESV1_S 9 +#define MCASP_TLGC_MMS 0x00000100 // Source of MISR input 0 1 +#define MCASP_TLGC_ESEL 0x00000080 // Output enable select 0 1 +#define MCASP_TLGC_TOEN 0x00000040 // Test output enable control. 0 1 +#define MCASP_TLGC_MC_M 0x00000030 // States of MISR 0x0 0x1 0x2 0x3 +#define MCASP_TLGC_MC_S 4 +#define MCASP_TLGC_PC_M 0x0000000E // Pattern code 0x0 0x1 0x2 0x3 0x4 + // 0x5 0x6 0x7 +#define MCASP_TLGC_PC_S 1 +#define MCASP_TLGC_TM 0x00000001 // Tie high; do not write to this + // bit 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLMR register. +// +//****************************************************************************** +#define MCASP_TLMR_TLMR_M 0xFFFFFFFF // Contains test result signature. +#define MCASP_TLMR_TLMR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLEC register. +// +//****************************************************************************** +#define MCASP_TLEC_TLEC_M 0xFFFFFFFF // Contains number of cycles during + // which MISR sig will be + // accumulated. +#define MCASP_TLEC_TLEC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTL register. +// +//****************************************************************************** +#define MCASP_GBLCTL_XFRST 0x00001000 // Frame sync generator reset 0 1 +#define MCASP_GBLCTL_XSMRST 0x00000800 // XMT state machine reset 0 1 +#define MCASP_GBLCTL_XSRCLR 0x00000400 // XMT serializer clear 0 1 +#define MCASP_GBLCTL_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 +#define MCASP_GBLCTL_XCLKRST 0x00000100 // XMT clock divder reset 0 1 +#define MCASP_GBLCTL_RFRST 0x00000010 // Frame sync generator reset 0 1 +#define MCASP_GBLCTL_RSMRST 0x00000008 // RCV state machine reset 0 1 +#define MCASP_GBLCTL_RSRCLR 0x00000004 // RCV serializer clear 0 1 +#define MCASP_GBLCTL_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 +#define MCASP_GBLCTL_RCLKRST 0x00000001 // RCV clock divder reset 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AMUTE register. +// +//****************************************************************************** +#define MCASP_AMUTE_XDMAERR 0x00001000 // MUTETXDMAERR occur 0 1 +#define MCASP_AMUTE_RDMAERR 0x00000800 // MUTERXDMAERR occur 0 1 +#define MCASP_AMUTE_XCKFAIL 0x00000400 // XMT bad clock 0 1 +#define MCASP_AMUTE_RCKFAIL 0x00000200 // RCV bad clock 0 1 +#define MCASP_AMUTE_XSYNCERR 0x00000100 // XMT unexpected FS 0 1 +#define MCASP_AMUTE_RSYNCERR 0x00000080 // RCV unexpected FS 0 1 +#define MCASP_AMUTE_XUNDRN 0x00000040 // XMT underrun occurs 0 1 +#define MCASP_AMUTE_ROVRN 0x00000020 // RCV overun occurs 0 1 +#define MCASP_AMUTE_INSTAT 0x00000010 +#define MCASP_AMUTE_INEN 0x00000008 // drive AMUTE active on mute in + // active 0 1 +#define MCASP_AMUTE_INPOL 0x00000004 // Mute input polarity 0 1 +#define MCASP_AMUTE_MUTEN_M 0x00000003 // AMUTE pin enable 0x0 0x1 0x2 +#define MCASP_AMUTE_MUTEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_LBCTL register. +// +//****************************************************************************** +#define MCASP_LBCTL_IOLBEN 0x00000010 // IO loopback enable 0 1 +#define MCASP_LBCTL_MODE_M 0x0000000C // Loop back clock source generator + // 0x0 0x1 0x2 0x3 +#define MCASP_LBCTL_MODE_S 2 +#define MCASP_LBCTL_ORD 0x00000002 // Loopback order 0 1 +#define MCASP_LBCTL_DLBEN 0x00000001 // Loop back mode 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXDITCTL register. +// +//****************************************************************************** +#define MCASP_TXDITCTL_VB 0x00000008 // Valib bit for odd TDM 0 1 +#define MCASP_TXDITCTL_VA 0x00000004 // Valib bit for even TDM 0 1 +#define MCASP_TXDITCTL_DITEN 0x00000001 // XMT DIT Mode Enable 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTLR register. +// +//****************************************************************************** +#define MCASP_GBLCTLR_XFRST 0x00001000 +#define MCASP_GBLCTLR_XSMRST 0x00000800 +#define MCASP_GBLCTLR_XSRCLR 0x00000400 +#define MCASP_GBLCTLR_XHCLKRST 0x00000200 +#define MCASP_GBLCTLR_XCLKRST 0x00000100 +#define MCASP_GBLCTLR_RFRST 0x00000010 // Frame sync generator reset 0 1 +#define MCASP_GBLCTLR_RSMRST 0x00000008 // RCV state machine reset 0 1 +#define MCASP_GBLCTLR_RSRCLR 0x00000004 // RCV serializer clear 0 1 +#define MCASP_GBLCTLR_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 +#define MCASP_GBLCTLR_RCLKRST 0x00000001 // RCV clock divder reset 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXMASK register. +// +//****************************************************************************** +#define MCASP_RXMASK_RMASK31 0x80000000 // RMASK BIT 31 0 1 +#define MCASP_RXMASK_RMASK30 0x40000000 // RMASK BIT 30 0 1 +#define MCASP_RXMASK_RMASK29 0x20000000 // RMASK BIT 29 0 1 +#define MCASP_RXMASK_RMASK28 0x10000000 // RMASK BIT 28 0 1 +#define MCASP_RXMASK_RMASK27 0x08000000 // RMASK BIT 27 0 1 +#define MCASP_RXMASK_RMASK26 0x04000000 // RMASK BIT 26 0 1 +#define MCASP_RXMASK_RMASK25 0x02000000 // RMASK BIT 25 0 1 +#define MCASP_RXMASK_RMASK24 0x01000000 // RMASK BIT 24 0 1 +#define MCASP_RXMASK_RMASK23 0x00800000 // RMASK BIT 23 0 1 +#define MCASP_RXMASK_RMASK22 0x00400000 // RMASK BIT 22 0 1 +#define MCASP_RXMASK_RMASK21 0x00200000 // RMASK BIT 21 0 1 +#define MCASP_RXMASK_RMASK20 0x00100000 // RMASK BIT 20 0 1 +#define MCASP_RXMASK_RMASK19 0x00080000 // RMASK BIT 19 0 1 +#define MCASP_RXMASK_RMASK18 0x00040000 // RMASK BIT 18 0 1 +#define MCASP_RXMASK_RMASK17 0x00020000 // RMASK BIT 17 0 1 +#define MCASP_RXMASK_RMASK16 0x00010000 // RMASK BIT 16 0 1 +#define MCASP_RXMASK_RMASK15 0x00008000 // RMASK BIT 15 0 1 +#define MCASP_RXMASK_RMASK14 0x00004000 // RMASK BIT 14 0 1 +#define MCASP_RXMASK_RMASK13 0x00002000 // RMASK BIT 13 0 1 +#define MCASP_RXMASK_RMASK12 0x00001000 // RMASK BIT 12 0 1 +#define MCASP_RXMASK_RMASK11 0x00000800 // RMASK BIT 11 0 1 +#define MCASP_RXMASK_RMASK10 0x00000400 // RMASK BIT 10 0 1 +#define MCASP_RXMASK_RMASK9 0x00000200 // RMASK BIT 9 0 1 +#define MCASP_RXMASK_RMASK8 0x00000100 // RMASK BIT 8 0 1 +#define MCASP_RXMASK_RMASK7 0x00000080 // RMASK BIT 7 0 1 +#define MCASP_RXMASK_RMASK6 0x00000040 // RMASK BIT 6 0 1 +#define MCASP_RXMASK_RMASK5 0x00000020 // RMASK BIT 5 0 1 +#define MCASP_RXMASK_RMASK4 0x00000010 // RMASK BIT 4 0 1 +#define MCASP_RXMASK_RMASK3 0x00000008 // RMASK BIT 3 0 1 +#define MCASP_RXMASK_RMASK2 0x00000004 // RMASK BIT 2 0 1 +#define MCASP_RXMASK_RMASK1 0x00000002 // RMASK BIT 1 0 1 +#define MCASP_RXMASK_RMASK0 0x00000001 // RMASK BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXFMT register. +// +//****************************************************************************** +#define MCASP_RXFMT_RDATDLY_M 0x00030000 // RCV Frame sync delay 0x0 0 Bit + // delay 0x1 1 Bit delay 0x2 2 Bit + // delay +#define MCASP_RXFMT_RDATDLY_S 16 +#define MCASP_RXFMT_RRVRS 0x00008000 // RCV serial stream bit order 0 1 +#define MCASP_RXFMT_RPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 +#define MCASP_RXFMT_RPAD_S 13 +#define MCASP_RXFMT_RPBIT_M 0x00001F00 // Pad bit position +#define MCASP_RXFMT_RPBIT_S 8 +#define MCASP_RXFMT_RSSZ_M 0x000000F0 // RCV slot Size 0x0 0x1 0x2 0x3 + // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB + // 0xC 0xD 0xE 0xF +#define MCASP_RXFMT_RSSZ_S 4 +#define MCASP_RXFMT_RBUSEL 0x00000008 // Write to RBUF using CPU/DMA 0 + // DMA port access 1 CPU port Access +#define MCASP_RXFMT_RROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 + // 0x3 0x4 0x5 0x6 0x7 +#define MCASP_RXFMT_RROT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXFMCTL register. +// +//****************************************************************************** +#define MCASP_RXFMCTL_RMOD_M 0x0000FF80 // RCV Frame sync mode +#define MCASP_RXFMCTL_RMOD_S 7 +#define MCASP_RXFMCTL_FRWID 0x00000010 // RCV Frame sync Duration 0 1 +#define MCASP_RXFMCTL_FSRM 0x00000002 // RCV frame sync External 0 1 +#define MCASP_RXFMCTL_FSRP 0x00000001 // RCV Frame sync Polarity 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_ACLKRCTL register. +// +//****************************************************************************** +#define MCASP_ACLKRCTL_BUSY 0x00100000 +#define MCASP_ACLKRCTL_DIVBUSY 0x00080000 +#define MCASP_ACLKRCTL_ADJBUSY 0x00040000 +#define MCASP_ACLKRCTL_CLKRADJ_M \ + 0x00030000 + +#define MCASP_ACLKRCTL_CLKRADJ_S 16 +#define MCASP_ACLKRCTL_CLKRP 0x00000080 // RCV Clock Polarity 0 1 +#define MCASP_ACLKRCTL_CLKRM 0x00000020 // RCV clock source 0 1 +#define MCASP_ACLKRCTL_CLKRDIV_M \ + 0x0000001F // RCV clock devide ratio + +#define MCASP_ACLKRCTL_CLKRDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register. +// +//****************************************************************************** +#define MCASP_AHCLKRCTL_BUSY 0x00100000 +#define MCASP_AHCLKRCTL_DIVBUSY 0x00080000 +#define MCASP_AHCLKRCTL_ADJBUSY 0x00040000 +#define MCASP_AHCLKRCTL_HCLKRADJ_M \ + 0x00030000 + +#define MCASP_AHCLKRCTL_HCLKRADJ_S 16 +#define MCASP_AHCLKRCTL_HCLKRM 0x00008000 // High Freq. RCV clock Source 0 1 +#define MCASP_AHCLKRCTL_HCLKRP 0x00004000 // High Freq. clock Polarity Before + // diviser 0 1 +#define MCASP_AHCLKRCTL_HCLKRDIV_M \ + 0x00000FFF // RCV clock Divide Ratio + +#define MCASP_AHCLKRCTL_HCLKRDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXTDM register. +// +//****************************************************************************** +#define MCASP_RXTDM_RTDMS31 0x80000000 // RCV mode during TDM time slot 31 + // 0 1 +#define MCASP_RXTDM_RTDMS30 0x40000000 // RCV mode during TDM time slot 30 + // 0 1 +#define MCASP_RXTDM_RTDMS29 0x20000000 // RCV mode during TDM time slot 29 + // 0 1 +#define MCASP_RXTDM_RTDMS28 0x10000000 // RCV mode during TDM time slot 28 + // 0 1 +#define MCASP_RXTDM_RTDMS27 0x08000000 // RCV mode during TDM time slot 27 + // 0 1 +#define MCASP_RXTDM_RTDMS26 0x04000000 // RCV mode during TDM time slot 26 + // 0 1 +#define MCASP_RXTDM_RTDMS25 0x02000000 // RCV mode during TDM time slot 25 + // 0 1 +#define MCASP_RXTDM_RTDMS24 0x01000000 // RCV mode during TDM time slot 24 + // 0 1 +#define MCASP_RXTDM_RTDMS23 0x00800000 // RCV mode during TDM time slot 23 + // 0 1 +#define MCASP_RXTDM_RTDMS22 0x00400000 // RCV mode during TDM time slot 22 + // 0 1 +#define MCASP_RXTDM_RTDMS21 0x00200000 // RCV mode during TDM time slot 21 + // 0 1 +#define MCASP_RXTDM_RTDMS20 0x00100000 // RCV mode during TDM time slot 20 + // 0 1 +#define MCASP_RXTDM_RTDMS19 0x00080000 // RCV mode during TDM time slot 19 + // 0 1 +#define MCASP_RXTDM_RTDMS18 0x00040000 // RCV mode during TDM time slot 18 + // 0 1 +#define MCASP_RXTDM_RTDMS17 0x00020000 // RCV mode during TDM time slot 17 + // 0 1 +#define MCASP_RXTDM_RTDMS16 0x00010000 // RCV mode during TDM time slot 16 + // 0 1 +#define MCASP_RXTDM_RTDMS15 0x00008000 // RCV mode during TDM time slot 15 + // 0 1 +#define MCASP_RXTDM_RTDMS14 0x00004000 // RCV mode during TDM time slot 14 + // 0 1 +#define MCASP_RXTDM_RTDMS13 0x00002000 // RCV mode during TDM time slot 13 + // 0 1 +#define MCASP_RXTDM_RTDMS12 0x00001000 // RCV mode during TDM time slot 12 + // 0 1 +#define MCASP_RXTDM_RTDMS11 0x00000800 // RCV mode during TDM time slot 11 + // 0 1 +#define MCASP_RXTDM_RTDMS10 0x00000400 // RCV mode during TDM time slot 10 + // 0 1 +#define MCASP_RXTDM_RTDMS9 0x00000200 // RCV mode during TDM time slot 9 + // 0 1 +#define MCASP_RXTDM_RTDMS8 0x00000100 // RCV mode during TDM time slot 8 + // 0 1 +#define MCASP_RXTDM_RTDMS7 0x00000080 // RCV mode during TDM time slot 7 + // 0 1 +#define MCASP_RXTDM_RTDMS6 0x00000040 // RCV mode during TDM time slot 6 + // 0 1 +#define MCASP_RXTDM_RTDMS5 0x00000020 // RCV mode during TDM time slot 5 + // 0 1 +#define MCASP_RXTDM_RTDMS4 0x00000010 // RCV mode during TDM time slot 4 + // 0 1 +#define MCASP_RXTDM_RTDMS3 0x00000008 // RCV mode during TDM time slot 3 + // 0 1 +#define MCASP_RXTDM_RTDMS2 0x00000004 // RCV mode during TDM time slot 2 + // 0 1 +#define MCASP_RXTDM_RTDMS1 0x00000002 // RCV mode during TDM time slot 1 + // 0 1 +#define MCASP_RXTDM_RTDMS0 0x00000001 // RCV mode during TDM time slot 0 + // 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_EVTCTLR register. +// +//****************************************************************************** +#define MCASP_EVTCTLR_RSTAFRM 0x00000080 // RCV Start of Frame Interrupt 0 1 +#define MCASP_EVTCTLR_RDATA 0x00000020 // RCV Data Interrupt 0 1 +#define MCASP_EVTCTLR_RLAST 0x00000010 // RCV Last Slot Interrupt 0 1 +#define MCASP_EVTCTLR_RDMAERR 0x00000008 // RCV DMA Bus Error 0 1 +#define MCASP_EVTCTLR_RCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 +#define MCASP_EVTCTLR_RSYNCERR 0x00000002 // RCV Unexpected FSR Interrupt 0 1 +#define MCASP_EVTCTLR_ROVRN 0x00000001 // RCV Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXSTAT register. +// +//****************************************************************************** +#define MCASP_RXSTAT_RERR 0x00000100 // RCV Error 0 1 +#define MCASP_RXSTAT_RDMAERR 0x00000080 // RCV DMA bus error 0 1 +#define MCASP_RXSTAT_RSTAFRM 0x00000040 // Start of Frame-RCV 0 1 +#define MCASP_RXSTAT_RDATA 0x00000020 // Data Ready Flag 0 1 +#define MCASP_RXSTAT_RLAST 0x00000010 // Last Slot Interrupt Flag 0 1 +#define MCASP_RXSTAT_RTDMSLOT 0x00000008 // EvenOdd Slot 0 1 +#define MCASP_RXSTAT_RCKFAIL 0x00000004 // Bad Transmit Flag 0 1 +#define MCASP_RXSTAT_RSYNCERR 0x00000002 // Unexpected RCV Frame sync flag 0 + // 1 +#define MCASP_RXSTAT_ROVRN 0x00000001 // RCV Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register. +// +//****************************************************************************** +#define MCASP_RXTDMSLOT_RSLOTCNT_M \ + 0x000003FF // Current RCV time slot count + +#define MCASP_RXTDMSLOT_RSLOTCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXCLKCHK register. +// +//****************************************************************************** +#define MCASP_RXCLKCHK_RCNT_M 0xFF000000 // RCV clock count value +#define MCASP_RXCLKCHK_RCNT_S 24 +#define MCASP_RXCLKCHK_RMAX_M 0x00FF0000 // RCV clock maximum boundary +#define MCASP_RXCLKCHK_RMAX_S 16 +#define MCASP_RXCLKCHK_RMIN_M 0x0000FF00 // RCV clock minimum boundary +#define MCASP_RXCLKCHK_RMIN_S 8 +#define MCASP_RXCLKCHK_RPS_M 0x0000000F // RCV clock check prescaler 0x0 + // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 +#define MCASP_RXCLKCHK_RPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_REVTCTL register. +// +//****************************************************************************** +#define MCASP_REVTCTL_RDATDMA 0x00000001 // RCV data DMA request 0 Enable + // DMA Transfer 1 Disable DMA + // Transfer +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTLX register. +// +//****************************************************************************** +#define MCASP_GBLCTLX_XFRST 0x00001000 // Frame sync generator reset 0 1 +#define MCASP_GBLCTLX_XSMRST 0x00000800 // XMT state machine reset 0 1 +#define MCASP_GBLCTLX_XSRCLR 0x00000400 // XMT serializer clear 0 1 +#define MCASP_GBLCTLX_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 +#define MCASP_GBLCTLX_XCLKRST 0x00000100 // XMT clock divder reset 0 1 +#define MCASP_GBLCTLX_RFRST 0x00000010 +#define MCASP_GBLCTLX_RSMRST 0x00000008 +#define MCASP_GBLCTLX_RSRCLKR 0x00000004 +#define MCASP_GBLCTLX_RHCLKRST 0x00000002 +#define MCASP_GBLCTLX_RCLKRST 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXMASK register. +// +//****************************************************************************** +#define MCASP_TXMASK_XMASK31 0x80000000 // XMASK BIT 31 0 1 +#define MCASP_TXMASK_XMASK30 0x40000000 // XMASK BIT 30 0 1 +#define MCASP_TXMASK_XMASK29 0x20000000 // XMASK BIT 29 0 1 +#define MCASP_TXMASK_XMASK28 0x10000000 // XMASK BIT 28 0 1 +#define MCASP_TXMASK_XMASK27 0x08000000 // XMASK BIT 27 0 1 +#define MCASP_TXMASK_XMASK26 0x04000000 // XMASK BIT 26 0 1 +#define MCASP_TXMASK_XMASK25 0x02000000 // XMASK BIT 25 0 1 +#define MCASP_TXMASK_XMASK24 0x01000000 // XMASK BIT 24 0 1 +#define MCASP_TXMASK_XMASK23 0x00800000 // XMASK BIT 23 0 1 +#define MCASP_TXMASK_XMASK22 0x00400000 // XMASK BIT 22 0 1 +#define MCASP_TXMASK_XMASK21 0x00200000 // XMASK BIT 21 0 1 +#define MCASP_TXMASK_XMASK20 0x00100000 // XMASK BIT 20 0 1 +#define MCASP_TXMASK_XMASK19 0x00080000 // XMASK BIT 19 0 1 +#define MCASP_TXMASK_XMASK18 0x00040000 // XMASK BIT 18 0 1 +#define MCASP_TXMASK_XMASK17 0x00020000 // XMASK BIT 17 0 1 +#define MCASP_TXMASK_XMASK16 0x00010000 // XMASK BIT 16 0 1 +#define MCASP_TXMASK_XMASK15 0x00008000 // XMASK BIT 15 0 1 +#define MCASP_TXMASK_XMASK14 0x00004000 // XMASK BIT 14 0 1 +#define MCASP_TXMASK_XMASK13 0x00002000 // XMASK BIT 13 0 1 +#define MCASP_TXMASK_XMASK12 0x00001000 // XMASK BIT 12 0 1 +#define MCASP_TXMASK_XMASK11 0x00000800 // XMASK BIT 11 0 1 +#define MCASP_TXMASK_XMASK10 0x00000400 // XMASK BIT 10 0 1 +#define MCASP_TXMASK_XMASK9 0x00000200 // XMASK BIT 9 0 1 +#define MCASP_TXMASK_XMASK8 0x00000100 // XMASK BIT 8 0 1 +#define MCASP_TXMASK_XMASK7 0x00000080 // XMASK BIT 7 0 1 +#define MCASP_TXMASK_XMASK6 0x00000040 // XMASK BIT 6 0 1 +#define MCASP_TXMASK_XMASK5 0x00000020 // XMASK BIT 5 0 1 +#define MCASP_TXMASK_XMASK4 0x00000010 // XMASK BIT 4 0 1 +#define MCASP_TXMASK_XMASK3 0x00000008 // XMASK BIT 3 0 1 +#define MCASP_TXMASK_XMASK2 0x00000004 // XMASK BIT 2 0 1 +#define MCASP_TXMASK_XMASK1 0x00000002 // XMASK BIT 1 0 1 +#define MCASP_TXMASK_XMASK0 0x00000001 // XMASK BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXFMT register. +// +//****************************************************************************** +#define MCASP_TXFMT_XDATDLY_M 0x00030000 // XMT Frame sync delay 0x0 0 Bit + // delay 0x1 1 Bit delay 0x2 2 Bit + // delay +#define MCASP_TXFMT_XDATDLY_S 16 +#define MCASP_TXFMT_XRVRS 0x00008000 // XMT serial stream bit order 0 1 +#define MCASP_TXFMT_XPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 +#define MCASP_TXFMT_XPAD_S 13 +#define MCASP_TXFMT_XPBIT_M 0x00001F00 // Pad bit position +#define MCASP_TXFMT_XPBIT_S 8 +#define MCASP_TXFMT_XSSZ_M 0x000000F0 // XMT slot Size 0x0 0x1 0x2 0x3 + // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB + // 0xC 0xD 0xE 0xF +#define MCASP_TXFMT_XSSZ_S 4 +#define MCASP_TXFMT_XBUSEL 0x00000008 // Write to XBUF using CPU/DMA 0 + // DMA port access 1 CPU port Access +#define MCASP_TXFMT_XROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 + // 0x3 0x4 0x5 0x6 0x7 +#define MCASP_TXFMT_XROT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXFMCTL register. +// +//****************************************************************************** +#define MCASP_TXFMCTL_XMOD_M 0x0000FF80 // XMT Frame sync mode +#define MCASP_TXFMCTL_XMOD_S 7 +#define MCASP_TXFMCTL_FXWID 0x00000010 // XMT Frame sync Duration 0 1 +#define MCASP_TXFMCTL_FSXM 0x00000002 // XMT frame sync External 0 1 +#define MCASP_TXFMCTL_FSXP 0x00000001 // XMT Frame sync Polarity 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_ACLKXCTL register. +// +//****************************************************************************** +#define MCASP_ACLKXCTL_BUSY 0x00100000 +#define MCASP_ACLKXCTL_DIVBUSY 0x00080000 +#define MCASP_ACLKXCTL_ADJBUSY 0x00040000 +#define MCASP_ACLKXCTL_CLKXADJ_M \ + 0x00030000 + +#define MCASP_ACLKXCTL_CLKXADJ_S 16 +#define MCASP_ACLKXCTL_CLKXP 0x00000080 // XMT Clock Polarity 0 1 +#define MCASP_ACLKXCTL_ASYNC 0x00000040 // XMT/RCV operation sync /Async 0 + // 1 +#define MCASP_ACLKXCTL_CLKXM 0x00000020 // XMT clock source 0 1 +#define MCASP_ACLKXCTL_CLKXDIV_M \ + 0x0000001F // XMT clock devide ratio + +#define MCASP_ACLKXCTL_CLKXDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register. +// +//****************************************************************************** +#define MCASP_AHCLKXCTL_BUSY 0x00100000 +#define MCASP_AHCLKXCTL_DIVBUSY 0x00080000 +#define MCASP_AHCLKXCTL_ADJBUSY 0x00040000 +#define MCASP_AHCLKXCTL_HCLKXADJ_M \ + 0x00030000 + +#define MCASP_AHCLKXCTL_HCLKXADJ_S 16 +#define MCASP_AHCLKXCTL_HCLKXM 0x00008000 // High Freq. XMT clock Source 0 1 +#define MCASP_AHCLKXCTL_HCLKXP 0x00004000 // High Freq. clock Polarity Before + // diviser 0 1 +#define MCASP_AHCLKXCTL_HCLKXDIV_M \ + 0x00000FFF // XMT clock Divide Ratio + +#define MCASP_AHCLKXCTL_HCLKXDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXTDM register. +// +//****************************************************************************** +#define MCASP_TXTDM_XTDMS31 0x80000000 // XMT mode during TDM time slot 31 + // 0 1 +#define MCASP_TXTDM_XTDMS30 0x40000000 // XMT mode during TDM time slot 30 + // 0 1 +#define MCASP_TXTDM_XTDMS29 0x20000000 // XMT mode during TDM time slot 29 + // 0 1 +#define MCASP_TXTDM_XTDMS28 0x10000000 // XMT mode during TDM time slot 28 + // 0 1 +#define MCASP_TXTDM_XTDMS27 0x08000000 // XMT mode during TDM time slot 27 + // 0 1 +#define MCASP_TXTDM_XTDMS26 0x04000000 // XMT mode during TDM time slot 26 + // 0 1 +#define MCASP_TXTDM_XTDMS25 0x02000000 // XMT mode during TDM time slot 25 + // 0 1 +#define MCASP_TXTDM_XTDMS24 0x01000000 // XMT mode during TDM time slot 24 + // 0 1 +#define MCASP_TXTDM_XTDMS23 0x00800000 // XMT mode during TDM time slot 23 + // 0 1 +#define MCASP_TXTDM_XTDMS22 0x00400000 // XMT mode during TDM time slot 22 + // 0 1 +#define MCASP_TXTDM_XTDMS21 0x00200000 // XMT mode during TDM time slot 21 + // 0 1 +#define MCASP_TXTDM_XTDMS20 0x00100000 // XMT mode during TDM time slot 20 + // 0 1 +#define MCASP_TXTDM_XTDMS19 0x00080000 // XMT mode during TDM time slot 19 + // 0 1 +#define MCASP_TXTDM_XTDMS18 0x00040000 // XMT mode during TDM time slot 18 + // 0 1 +#define MCASP_TXTDM_XTDMS17 0x00020000 // XMT mode during TDM time slot 17 + // 0 1 +#define MCASP_TXTDM_XTDMS16 0x00010000 // XMT mode during TDM time slot 16 + // 0 1 +#define MCASP_TXTDM_XTDMS15 0x00008000 // XMT mode during TDM time slot 15 + // 0 1 +#define MCASP_TXTDM_XTDMS14 0x00004000 // XMT mode during TDM time slot 14 + // 0 1 +#define MCASP_TXTDM_XTDMS13 0x00002000 // XMT mode during TDM time slot 13 + // 0 1 +#define MCASP_TXTDM_XTDMS12 0x00001000 // XMT mode during TDM time slot 12 + // 0 1 +#define MCASP_TXTDM_XTDMS11 0x00000800 // XMT mode during TDM time slot 11 + // 0 1 +#define MCASP_TXTDM_XTDMS10 0x00000400 // XMT mode during TDM time slot 10 + // 0 1 +#define MCASP_TXTDM_XTDMS9 0x00000200 // XMT mode during TDM time slot 9 + // 0 1 +#define MCASP_TXTDM_XTDMS8 0x00000100 // XMT mode during TDM time slot 8 + // 0 1 +#define MCASP_TXTDM_XTDMS7 0x00000080 // XMT mode during TDM time slot 7 + // 0 1 +#define MCASP_TXTDM_XTDMS6 0x00000040 // XMT mode during TDM time slot 6 + // 0 1 +#define MCASP_TXTDM_XTDMS5 0x00000020 // XMT mode during TDM time slot 5 + // 0 1 +#define MCASP_TXTDM_XTDMS4 0x00000010 // XMT mode during TDM time slot 4 + // 0 1 +#define MCASP_TXTDM_XTDMS3 0x00000008 // XMT mode during TDM time slot 3 + // 0 1 +#define MCASP_TXTDM_XTDMS2 0x00000004 // XMT mode during TDM time slot 2 + // 0 1 +#define MCASP_TXTDM_XTDMS1 0x00000002 // XMT mode during TDM time slot 1 + // 0 1 +#define MCASP_TXTDM_XTDMS0 0x00000001 // XMT mode during TDM time slot 0 + // 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_EVTCTLX register. +// +//****************************************************************************** +#define MCASP_EVTCTLX_XSTAFRM 0x00000080 // XMT Start of Frame Interrupt 0 1 +#define MCASP_EVTCTLX_XDATA 0x00000020 // XMT Data Interrupt 0 1 +#define MCASP_EVTCTLX_XLAST 0x00000010 // XMT Last Slot Interrupt 0 1 +#define MCASP_EVTCTLX_XDMAERR 0x00000008 // XMT DMA Bus Error 0 1 +#define MCASP_EVTCTLX_XCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 +#define MCASP_EVTCTLX_XSYNCERR 0x00000002 // XMT Unexpected FSR Interrupt 0 1 +#define MCASP_EVTCTLX_XUNDRN 0x00000001 // XMT Underrun Interrupt 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXSTAT register. +// +//****************************************************************************** +#define MCASP_TXSTAT_XERR 0x00000100 // XMT Error 0 1 +#define MCASP_TXSTAT_XDMAERR 0x00000080 // XMT DMA bus error 0 1 +#define MCASP_TXSTAT_XSTAFRM 0x00000040 // Start of Frame-XMT 0 1 +#define MCASP_TXSTAT_XDATA 0x00000020 // Data Ready Flag 0 1 +#define MCASP_TXSTAT_XLAST 0x00000010 // Last Slot Interrupt Flag 0 1 +#define MCASP_TXSTAT_XTDMSLOT 0x00000008 // EvenOdd Slot 0 1 +#define MCASP_TXSTAT_XCKFAIL 0x00000004 // Bad Transmit Flag 0 1 +#define MCASP_TXSTAT_XSYNCERR 0x00000002 // Unexpected XMT Frame sync flag 0 + // 1 +#define MCASP_TXSTAT_XUNDRN 0x00000001 // XMT Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register. +// +//****************************************************************************** +#define MCASP_TXTDMSLOT_XSLOTCNT_M \ + 0x000003FF // Current XMT time slot count + // during reset the value of this + // register is 0b0101111111 (0x17f) + // and after reset 0 + +#define MCASP_TXTDMSLOT_XSLOTCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXCLKCHK register. +// +//****************************************************************************** +#define MCASP_TXCLKCHK_XCNT_M 0xFF000000 // XMT clock count value +#define MCASP_TXCLKCHK_XCNT_S 24 +#define MCASP_TXCLKCHK_XMAX_M 0x00FF0000 // XMT clock maximum boundary +#define MCASP_TXCLKCHK_XMAX_S 16 +#define MCASP_TXCLKCHK_XMIN_M 0x0000FF00 // XMT clock minimum boundary +#define MCASP_TXCLKCHK_XMIN_S 8 +#define MCASP_TXCLKCHK_RESV 0x00000080 // Reserved +#define MCASP_TXCLKCHK_XPS_M 0x0000000F // XMT clock check prescaler 0x0 + // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 +#define MCASP_TXCLKCHK_XPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XEVTCTL register. +// +//****************************************************************************** +#define MCASP_XEVTCTL_XDATDMA 0x00000001 // XMT data DMA request 0 Enable + // DMA Transfer 1 Disable DMA + // Transfer +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_CLKADJEN register. +// +//****************************************************************************** +#define MCASP_CLKADJEN_ENABLE 0x00000001 // One-shot clock adjust enable 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA0 register. +// +//****************************************************************************** +#define MCASP_DITCSRA0_DITCSRA0_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA0_DITCSRA0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA1 register. +// +//****************************************************************************** +#define MCASP_DITCSRA1_DITCSRA1_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA1_DITCSRA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA2 register. +// +//****************************************************************************** +#define MCASP_DITCSRA2_DITCSRA2_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status Register + +#define MCASP_DITCSRA2_DITCSRA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA3 register. +// +//****************************************************************************** +#define MCASP_DITCSRA3_DITCSRA3_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status Register + +#define MCASP_DITCSRA3_DITCSRA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA4 register. +// +//****************************************************************************** +#define MCASP_DITCSRA4_DITCSRA4_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA4_DITCSRA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA5 register. +// +//****************************************************************************** +#define MCASP_DITCSRA5_DITCSRA5_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA5_DITCSRA5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB0 register. +// +//****************************************************************************** +#define MCASP_DITCSRB0_DITCSRB0_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB0_DITCSRB0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB1 register. +// +//****************************************************************************** +#define MCASP_DITCSRB1_DITCSRB1_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB1_DITCSRB1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB2 register. +// +//****************************************************************************** +#define MCASP_DITCSRB2_DITCSRB2_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB2_DITCSRB2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB3 register. +// +//****************************************************************************** +#define MCASP_DITCSRB3_DITCSRB3_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB3_DITCSRB3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB4 register. +// +//****************************************************************************** +#define MCASP_DITCSRB4_DITCSRB4_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB4_DITCSRB4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB5 register. +// +//****************************************************************************** +#define MCASP_DITCSRB5_DITCSRB5_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB5_DITCSRB5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA0 register. +// +//****************************************************************************** +#define MCASP_DITUDRA0_DITUDRA0_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA0_DITUDRA0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA1 register. +// +//****************************************************************************** +#define MCASP_DITUDRA1_DITUDRA1_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA1_DITUDRA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA2 register. +// +//****************************************************************************** +#define MCASP_DITUDRA2_DITUDRA2_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA2_DITUDRA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA3 register. +// +//****************************************************************************** +#define MCASP_DITUDRA3_DITUDRA3_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA3_DITUDRA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA4 register. +// +//****************************************************************************** +#define MCASP_DITUDRA4_DITUDRA4_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA4_DITUDRA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA5 register. +// +//****************************************************************************** +#define MCASP_DITUDRA5_DITUDRA5_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA5_DITUDRA5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB0 register. +// +//****************************************************************************** +#define MCASP_DITUDRB0_DITUDRB0_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB0_DITUDRB0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB1 register. +// +//****************************************************************************** +#define MCASP_DITUDRB1_DITUDRB1_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB1_DITUDRB1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB2 register. +// +//****************************************************************************** +#define MCASP_DITUDRB2_DITUDRB2_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB2_DITUDRB2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB3 register. +// +//****************************************************************************** +#define MCASP_DITUDRB3_DITUDRB3_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB3_DITUDRB3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB4 register. +// +//****************************************************************************** +#define MCASP_DITUDRB4_DITUDRB4_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB4_DITUDRB4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB5 register. +// +//****************************************************************************** +#define MCASP_DITUDRB5_DITUDRB5_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB5_DITUDRB5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL0_RRDY 0x00000020 +#define MCASP_XRSRCTL0_XRDY 0x00000010 +#define MCASP_XRSRCTL0_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL0_DISMOD_S 2 +#define MCASP_XRSRCTL0_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL0_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL1_RRDY 0x00000020 +#define MCASP_XRSRCTL1_XRDY 0x00000010 +#define MCASP_XRSRCTL1_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL1_DISMOD_S 2 +#define MCASP_XRSRCTL1_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL1_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL2_RRDY 0x00000020 +#define MCASP_XRSRCTL2_XRDY 0x00000010 +#define MCASP_XRSRCTL2_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL2_DISMOD_S 2 +#define MCASP_XRSRCTL2_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL2_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL3_RRDY 0x00000020 +#define MCASP_XRSRCTL3_XRDY 0x00000010 +#define MCASP_XRSRCTL3_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL3_DISMOD_S 2 +#define MCASP_XRSRCTL3_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL3_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL4_RRDY 0x00000020 +#define MCASP_XRSRCTL4_XRDY 0x00000010 +#define MCASP_XRSRCTL4_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL4_DISMOD_S 2 +#define MCASP_XRSRCTL4_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL4_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL5_RRDY 0x00000020 +#define MCASP_XRSRCTL5_XRDY 0x00000010 +#define MCASP_XRSRCTL5_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL5_DISMOD_S 2 +#define MCASP_XRSRCTL5_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL5_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL6_RRDY 0x00000020 +#define MCASP_XRSRCTL6_XRDY 0x00000010 +#define MCASP_XRSRCTL6_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL6_DISMOD_S 2 +#define MCASP_XRSRCTL6_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL6_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL7_RRDY 0x00000020 +#define MCASP_XRSRCTL7_XRDY 0x00000010 +#define MCASP_XRSRCTL7_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL7_DISMOD_S 2 +#define MCASP_XRSRCTL7_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL7_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL8_RRDY 0x00000020 +#define MCASP_XRSRCTL8_XRDY 0x00000010 +#define MCASP_XRSRCTL8_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL8_DISMOD_S 2 +#define MCASP_XRSRCTL8_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL8_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL9_RRDY 0x00000020 +#define MCASP_XRSRCTL9_XRDY 0x00000010 +#define MCASP_XRSRCTL9_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL9_DISMOD_S 2 +#define MCASP_XRSRCTL9_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL9_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL10_RRDY 0x00000020 +#define MCASP_XRSRCTL10_XRDY 0x00000010 +#define MCASP_XRSRCTL10_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL10_DISMOD_S 2 +#define MCASP_XRSRCTL10_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL10_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL11_RRDY 0x00000020 +#define MCASP_XRSRCTL11_XRDY 0x00000010 +#define MCASP_XRSRCTL11_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL11_DISMOD_S 2 +#define MCASP_XRSRCTL11_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL11_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL12_RRDY 0x00000020 +#define MCASP_XRSRCTL12_XRDY 0x00000010 +#define MCASP_XRSRCTL12_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL12_DISMOD_S 2 +#define MCASP_XRSRCTL12_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL12_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL13_RRDY 0x00000020 +#define MCASP_XRSRCTL13_XRDY 0x00000010 +#define MCASP_XRSRCTL13_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL13_DISMOD_S 2 +#define MCASP_XRSRCTL13_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL13_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL14_RRDY 0x00000020 +#define MCASP_XRSRCTL14_XRDY 0x00000010 +#define MCASP_XRSRCTL14_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL14_DISMOD_S 2 +#define MCASP_XRSRCTL14_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL14_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL15_RRDY 0x00000020 +#define MCASP_XRSRCTL15_XRDY 0x00000010 +#define MCASP_XRSRCTL15_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL15_DISMOD_S 2 +#define MCASP_XRSRCTL15_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL15_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF0 register. +// +//****************************************************************************** +#define MCASP_TXBUF0_XBUF0_M 0xFFFFFFFF // Transmit Buffer 0 +#define MCASP_TXBUF0_XBUF0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF1 register. +// +//****************************************************************************** +#define MCASP_TXBUF1_XBUF1_M 0xFFFFFFFF // Transmit Buffer 1 +#define MCASP_TXBUF1_XBUF1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF2 register. +// +//****************************************************************************** +#define MCASP_TXBUF2_XBUF2_M 0xFFFFFFFF // Transmit Buffer 2 +#define MCASP_TXBUF2_XBUF2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF3 register. +// +//****************************************************************************** +#define MCASP_TXBUF3_XBUF3_M 0xFFFFFFFF // Transmit Buffer 3 +#define MCASP_TXBUF3_XBUF3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF4 register. +// +//****************************************************************************** +#define MCASP_TXBUF4_XBUF4_M 0xFFFFFFFF // Transmit Buffer 4 +#define MCASP_TXBUF4_XBUF4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF5 register. +// +//****************************************************************************** +#define MCASP_TXBUF5_XBUF5_M 0xFFFFFFFF // Transmit Buffer 5 +#define MCASP_TXBUF5_XBUF5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF6 register. +// +//****************************************************************************** +#define MCASP_TXBUF6_XBUF6_M 0xFFFFFFFF // Transmit Buffer 6 +#define MCASP_TXBUF6_XBUF6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF7 register. +// +//****************************************************************************** +#define MCASP_TXBUF7_XBUF7_M 0xFFFFFFFF // Transmit Buffer 7 +#define MCASP_TXBUF7_XBUF7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF8 register. +// +//****************************************************************************** +#define MCASP_TXBUF8_XBUF8_M 0xFFFFFFFF // Transmit Buffer 8 +#define MCASP_TXBUF8_XBUF8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF9 register. +// +//****************************************************************************** +#define MCASP_TXBUF9_XBUF9_M 0xFFFFFFFF // Transmit Buffer 9 +#define MCASP_TXBUF9_XBUF9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF10 register. +// +//****************************************************************************** +#define MCASP_TXBUF10_XBUF10_M 0xFFFFFFFF // Transmit Buffer 10 +#define MCASP_TXBUF10_XBUF10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF11 register. +// +//****************************************************************************** +#define MCASP_TXBUF11_XBUF11_M 0xFFFFFFFF // Transmit Buffer 11 +#define MCASP_TXBUF11_XBUF11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF12 register. +// +//****************************************************************************** +#define MCASP_TXBUF12_XBUF12_M 0xFFFFFFFF // Transmit Buffer 12 +#define MCASP_TXBUF12_XBUF12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF13 register. +// +//****************************************************************************** +#define MCASP_TXBUF13_XBUF13_M 0xFFFFFFFF // Transmit Buffer 13 +#define MCASP_TXBUF13_XBUF13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF14 register. +// +//****************************************************************************** +#define MCASP_TXBUF14_XBUF14_M 0xFFFFFFFF // Transmit Buffer 14 +#define MCASP_TXBUF14_XBUF14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF15 register. +// +//****************************************************************************** +#define MCASP_TXBUF15_XBUF15_M 0xFFFFFFFF // Transmit Buffer 15 +#define MCASP_TXBUF15_XBUF15_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF0 register. +// +//****************************************************************************** +#define MCASP_RXBUF0_RBUF0_M 0xFFFFFFFF // Receive Buffer 0 +#define MCASP_RXBUF0_RBUF0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF1 register. +// +//****************************************************************************** +#define MCASP_RXBUF1_RBUF1_M 0xFFFFFFFF // Receive Buffer 1 +#define MCASP_RXBUF1_RBUF1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF2 register. +// +//****************************************************************************** +#define MCASP_RXBUF2_RBUF2_M 0xFFFFFFFF // Receive Buffer 2 +#define MCASP_RXBUF2_RBUF2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF3 register. +// +//****************************************************************************** +#define MCASP_RXBUF3_RBUF3_M 0xFFFFFFFF // Receive Buffer 3 +#define MCASP_RXBUF3_RBUF3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF4 register. +// +//****************************************************************************** +#define MCASP_RXBUF4_RBUF4_M 0xFFFFFFFF // Receive Buffer 4 +#define MCASP_RXBUF4_RBUF4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF5 register. +// +//****************************************************************************** +#define MCASP_RXBUF5_RBUF5_M 0xFFFFFFFF // Receive Buffer 5 +#define MCASP_RXBUF5_RBUF5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF6 register. +// +//****************************************************************************** +#define MCASP_RXBUF6_RBUF6_M 0xFFFFFFFF // Receive Buffer 6 +#define MCASP_RXBUF6_RBUF6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF7 register. +// +//****************************************************************************** +#define MCASP_RXBUF7_RBUF7_M 0xFFFFFFFF // Receive Buffer 7 +#define MCASP_RXBUF7_RBUF7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF8 register. +// +//****************************************************************************** +#define MCASP_RXBUF8_RBUF8_M 0xFFFFFFFF // Receive Buffer 8 +#define MCASP_RXBUF8_RBUF8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF9 register. +// +//****************************************************************************** +#define MCASP_RXBUF9_RBUF9_M 0xFFFFFFFF // Receive Buffer 9 +#define MCASP_RXBUF9_RBUF9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF10 register. +// +//****************************************************************************** +#define MCASP_RXBUF10_RBUF10_M 0xFFFFFFFF // Receive Buffer 10 +#define MCASP_RXBUF10_RBUF10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF11 register. +// +//****************************************************************************** +#define MCASP_RXBUF11_RBUF11_M 0xFFFFFFFF // Receive Buffer 11 +#define MCASP_RXBUF11_RBUF11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF12 register. +// +//****************************************************************************** +#define MCASP_RXBUF12_RBUF12_M 0xFFFFFFFF // Receive Buffer 12 +#define MCASP_RXBUF12_RBUF12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF13 register. +// +//****************************************************************************** +#define MCASP_RXBUF13_RBUF13_M 0xFFFFFFFF // Receive Buffer 13 +#define MCASP_RXBUF13_RBUF13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF14 register. +// +//****************************************************************************** +#define MCASP_RXBUF14_RBUF14_M 0xFFFFFFFF // Receive Buffer 14 +#define MCASP_RXBUF14_RBUF14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF15 register. +// +//****************************************************************************** +#define MCASP_RXBUF15_RBUF15_M 0xFFFFFFFF // Receive Buffer 15 +#define MCASP_RXBUF15_RBUF15_S 0 + + + +#endif // __HW_MCASP_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcspi.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcspi.h new file mode 100755 index 00000000000..aeddbc2e740 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mcspi.h @@ -0,0 +1,1743 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_MCSPI_H__ +#define __HW_MCSPI_H__ + +//***************************************************************************** +// +// The following are defines for the MCSPI register offsets. +// +//***************************************************************************** +#define MCSPI_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) + // Used by software to track + // features bugs and compatibility +#define MCSPI_O_HL_HWINFO 0x00000004 // Information about the IP + // module's hardware configuration + // i.e. typically the module's HDL + // generics (if any). Actual field + // format and encoding is up to the + // module's designer to decide. +#define MCSPI_O_HL_SYSCONFIG 0x00000010 // 0x4402 1010 0x4402 2010 Clock + // management configuration +#define MCSPI_O_REVISION 0x00000100 // 0x4402 1100 0x4402 2100 This + // register contains the hard coded + // RTL revision number. +#define MCSPI_O_SYSCONFIG 0x00000110 // 0x4402 1110 0x4402 2110 This + // register allows controlling + // various parameters of the OCP + // interface. +#define MCSPI_O_SYSSTATUS 0x00000114 // 0x4402 1114 0x4402 2114 This + // register provides status + // information about the module + // excluding the interrupt status + // information +#define MCSPI_O_IRQSTATUS 0x00000118 // 0x4402 1118 0x4402 2118 The + // interrupt status regroups all the + // status of the module internal + // events that can generate an + // interrupt +#define MCSPI_O_IRQENABLE 0x0000011C // 0x4402 111C 0x4402 211C This + // register allows to enable/disable + // the module internal sources of + // interrupt on an event-by-event + // basis. +#define MCSPI_O_WAKEUPENABLE 0x00000120 // 0x4402 1120 0x4402 2120 The + // wakeup enable register allows to + // enable/disable the module + // internal sources of wakeup on + // event-by-event basis. +#define MCSPI_O_SYST 0x00000124 // 0x4402 1124 0x4402 2124 This + // register is used to check the + // correctness of the system + // interconnect either internally to + // peripheral bus or externally to + // device IO pads when the module is + // configured in system test + // (SYSTEST) mode. +#define MCSPI_O_MODULCTRL 0x00000128 // 0x4402 1128 0x4402 2128 This + // register is dedicated to the + // configuration of the serial port + // interface. +#define MCSPI_O_CH0CONF 0x0000012C // 0x4402 112C 0x4402 212C This + // register is dedicated to the + // configuration of the channel 0 +#define MCSPI_O_CH0STAT 0x00000130 // 0x4402 1130 0x4402 2130 This + // register provides status + // information about transmitter and + // receiver registers of channel 0 +#define MCSPI_O_CH0CTRL 0x00000134 // 0x4402 1134 0x4402 2134 This + // register is dedicated to enable + // the channel 0 +#define MCSPI_O_TX0 0x00000138 // 0x4402 1138 0x4402 2138 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX0 0x0000013C // 0x4402 113C 0x4402 213C This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH1CONF 0x00000140 // 0x4402 1140 0x4402 2140 This + // register is dedicated to the + // configuration of the channel. +#define MCSPI_O_CH1STAT 0x00000144 // 0x4402 1144 0x4402 2144 This + // register provides status + // information about transmitter and + // receiver registers of channel 1 +#define MCSPI_O_CH1CTRL 0x00000148 // 0x4402 1148 0x4402 2148 This + // register is dedicated to enable + // the channel 1 +#define MCSPI_O_TX1 0x0000014C // 0x4402 114C 0x4402 214C This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX1 0x00000150 // 0x4402 1150 0x4402 2150 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH2CONF 0x00000154 // 0x4402 1154 0x4402 2154 This + // register is dedicated to the + // configuration of the channel 2 +#define MCSPI_O_CH2STAT 0x00000158 // 0x4402 1158 0x4402 2158 This + // register provides status + // information about transmitter and + // receiver registers of channel 2 +#define MCSPI_O_CH2CTRL 0x0000015C // 0x4402 115C 0x4402 215C This + // register is dedicated to enable + // the channel 2 +#define MCSPI_O_TX2 0x00000160 // 0x4402 1160 0x4402 2160 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX2 0x00000164 // 0x4402 1164 0x4402 2164 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH3CONF 0x00000168 // 0x4402 1168 0x4402 2168 This + // register is dedicated to the + // configuration of the channel 3 +#define MCSPI_O_CH3STAT 0x0000016C // 0x4402 116C 0x4402 216C This + // register provides status + // information about transmitter and + // receiver registers of channel 3 +#define MCSPI_O_CH3CTRL 0x00000170 // 0x4402 1170 0x4402 2170 This + // register is dedicated to enable + // the channel 3 +#define MCSPI_O_TX3 0x00000174 // 0x4402 1174 0x4402 2174 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX3 0x00000178 // 0x4402 1178 0x4402 2178 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_XFERLEVEL 0x0000017C // 0x4402 117C 0x4402 217C This + // register provides transfer levels + // needed while using FIFO buffer + // during transfer. +#define MCSPI_O_DAFTX 0x00000180 // 0x4402 1180 0x4402 2180 This + // register contains the SPI words + // to transmit on the serial link + // when FIFO used and DMA address is + // aligned on 256 bit.This register + // is an image of one of MCSPI_TX(i) + // register corresponding to the + // channel which have its FIFO + // enabled. +#define MCSPI_O_DAFRX 0x000001A0 // 0x4402 11A0 0x4402 21A0 This + // register contains the SPI words + // to received on the serial link + // when FIFO used and DMA address is + // aligned on 256 bit.This register + // is an image of one of MCSPI_RX(i) + // register corresponding to the + // channel which have its FIFO + // enabled. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_HL_REV register. +// +//****************************************************************************** +#define MCSPI_HL_REV_SCHEME_M 0xC0000000 +#define MCSPI_HL_REV_SCHEME_S 30 +#define MCSPI_HL_REV_RSVD_M 0x30000000 // Reserved These bits are + // initialized to zero and writes to + // them are ignored. +#define MCSPI_HL_REV_RSVD_S 28 +#define MCSPI_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define MCSPI_HL_REV_FUNC_S 16 +#define MCSPI_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define MCSPI_HL_REV_R_RTL_S 11 +#define MCSPI_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. +#define MCSPI_HL_REV_X_MAJOR_S 8 +#define MCSPI_HL_REV_CUSTOM_M 0x000000C0 +#define MCSPI_HL_REV_CUSTOM_S 6 +#define MCSPI_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. +#define MCSPI_HL_REV_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register. +// +//****************************************************************************** +#define MCSPI_HL_HWINFO_RETMODE 0x00000040 +#define MCSPI_HL_HWINFO_FFNBYTE_M \ + 0x0000003E + +#define MCSPI_HL_HWINFO_FFNBYTE_S 1 +#define MCSPI_HL_HWINFO_USEFIFO 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCSPI_O_HL_SYSCONFIG register. +// +//****************************************************************************** +#define MCSPI_HL_SYSCONFIG_IDLEMODE_M \ + 0x0000000C // Configuration of the local + // target state management mode. By + // definition target can handle + // read/write transaction as long as + // it is out of IDLE state. 0x0 + // Force-idle mode: local target's + // idle state follows (acknowledges) + // the system's idle requests + // unconditionally i.e. regardless + // of the IP module's internal + // requirements.Backup mode for + // debug only. 0x1 No-idle mode: + // local target never enters idle + // state.Backup mode for debug only. + // 0x2 Smart-idle mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module shall not + // generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 "Smart-idle + // wakeup-capable mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2 +#define MCSPI_HL_SYSCONFIG_FREEEMU \ + 0x00000002 // Sensitivity to emulation (debug) + // suspend input signal. 0 IP module + // is sensitive to emulation suspend + // 1 IP module is not sensitive to + // emulation suspend + +#define MCSPI_HL_SYSCONFIG_SOFTRESET \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_REVISION register. +// +//****************************************************************************** +#define MCSPI_REVISION_REV_M 0x000000FF // IP revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 +#define MCSPI_REVISION_REV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register. +// +//****************************************************************************** +#define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \ + 0x00000300 // Clocks activity during wake up + // mode period 0x0 OCP and + // Functional clocks may be switched + // off. 0x1 OCP clock is maintained. + // Functional clock may be + // switched-off. 0x2 Functional + // clock is maintained. OCP clock + // may be switched-off. 0x3 OCP and + // Functional clocks are maintained. + +#define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8 +#define MCSPI_SYSCONFIG_SIDLEMODE_M \ + 0x00000018 // Power management 0x0 If an idle + // request is detected the McSPI + // acknowledges it unconditionally + // and goes in Inactive mode. + // Interrupt DMA requests and wake + // up lines are unconditionally + // de-asserted and the module wakeup + // capability is deactivated even if + // the bit + // MCSPI_SYSCONFIG[EnaWakeUp] is + // set. 0x1 If an idle request is + // detected the request is ignored + // and the module does not switch to + // wake up mode and keeps on + // behaving normally. 0x2 If an idle + // request is detected the module + // will switch to idle mode based on + // its internal activity. The wake + // up capability cannot be used. 0x3 + // If an idle request is detected + // the module will switch to idle + // mode based on its internal + // activity and the wake up + // capability can be used if the bit + // MCSPI_SYSCONFIG[EnaWakeUp] is + // set. + +#define MCSPI_SYSCONFIG_SIDLEMODE_S 3 +#define MCSPI_SYSCONFIG_ENAWAKEUP \ + 0x00000004 // WakeUp feature control 0 WakeUp + // capability is disabled 1 WakeUp + // capability is enabled + +#define MCSPI_SYSCONFIG_SOFTRESET \ + 0x00000002 // Software reset. During reads it + // always returns 0. 0 (write) + // Normal mode 1 (write) Set this + // bit to 1 to trigger a module + // reset.The bit is automatically + // reset by the hardware. + +#define MCSPI_SYSCONFIG_AUTOIDLE \ + 0x00000001 // Internal OCP Clock gating + // strategy 0 OCP clock is + // free-running 1 Automatic OCP + // clock gating strategy is applied + // based on the OCP interface + // activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register. +// +//****************************************************************************** +#define MCSPI_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register. +// +//****************************************************************************** +#define MCSPI_IRQSTATUS_EOW 0x00020000 +#define MCSPI_IRQSTATUS_WKS 0x00010000 +#define MCSPI_IRQSTATUS_RX3_FULL \ + 0x00004000 + +#define MCSPI_IRQSTATUS_TX3_UNDERFLOW \ + 0x00002000 + +#define MCSPI_IRQSTATUS_TX3_EMPTY \ + 0x00001000 + +#define MCSPI_IRQSTATUS_RX2_FULL \ + 0x00000400 + +#define MCSPI_IRQSTATUS_TX2_UNDERFLOW \ + 0x00000200 + +#define MCSPI_IRQSTATUS_TX2_EMPTY \ + 0x00000100 + +#define MCSPI_IRQSTATUS_RX1_FULL \ + 0x00000040 + +#define MCSPI_IRQSTATUS_TX1_UNDERFLOW \ + 0x00000020 + +#define MCSPI_IRQSTATUS_TX1_EMPTY \ + 0x00000010 + +#define MCSPI_IRQSTATUS_RX0_OVERFLOW \ + 0x00000008 + +#define MCSPI_IRQSTATUS_RX0_FULL \ + 0x00000004 + +#define MCSPI_IRQSTATUS_TX0_UNDERFLOW \ + 0x00000002 + +#define MCSPI_IRQSTATUS_TX0_EMPTY \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_IRQENABLE register. +// +//****************************************************************************** +#define MCSPI_IRQENABLE_EOW_ENABLE \ + 0x00020000 // End of Word count Interrupt + // Enable. 0 Interrupt disabled 1 + // Interrupt enabled + +#define MCSPI_IRQENABLE_WKE 0x00010000 // Wake Up event interrupt Enable + // in slave mode when an active + // control signal is detected on the + // SPIEN line programmed in the + // field MCSPI_CH0CONF[SPIENSLV] 0 + // Interrupt disabled 1 Interrupt + // enabled +#define MCSPI_IRQENABLE_RX3_FULL_ENABLE \ + 0x00004000 // Receiver register Full Interrupt + // Enable. Ch 3 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \ + 0x00002000 // Transmitter register Underflow + // Interrupt Enable. Ch 3 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \ + 0x00001000 // Transmitter register Empty + // Interrupt Enable. Ch3 0 Interrupt + // disabled 1 Interrupt enabled + +#define MCSPI_IRQENABLE_RX2_FULL_ENABLE \ + 0x00000400 // Receiver register Full Interrupt + // Enable. Ch 2 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \ + 0x00000200 // Transmitter register Underflow + // Interrupt Enable. Ch 2 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \ + 0x00000100 // Transmitter register Empty + // Interrupt Enable. Ch 2 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX1_FULL_ENABLE \ + 0x00000040 // Receiver register Full Interrupt + // Enable. Ch 1 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \ + 0x00000020 // Transmitter register Underflow + // Interrupt Enable. Ch 1 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \ + 0x00000010 // Transmitter register Empty + // Interrupt Enable. Ch 1 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \ + 0x00000008 // Receiver register Overflow + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX0_FULL_ENABLE \ + 0x00000004 // Receiver register Full Interrupt + // Enable. Ch 0 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \ + 0x00000002 // Transmitter register Underflow + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \ + 0x00000001 // Transmitter register Empty + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCSPI_O_WAKEUPENABLE register. +// +//****************************************************************************** +#define MCSPI_WAKEUPENABLE_WKEN 0x00000001 // WakeUp functionality in slave + // mode when an active control + // signal is detected on the SPIEN + // line programmed in the field + // MCSPI_CH0CONF[SPIENSLV] 0 The + // event is not allowed to wakeup + // the system even if the global + // control bit + // MCSPI_SYSCONF[EnaWakeUp] is set. + // 1 The event is allowed to wakeup + // the system if the global control + // bit MCSPI_SYSCONF[EnaWakeUp] is + // set. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYST register. +// +//****************************************************************************** +#define MCSPI_SYST_SSB 0x00000800 // Set status bit 0 No action. + // Writing 0 does not clear already + // set status bits; This bit must be + // cleared prior attempting to clear + // a status bit of the + // register. 1 + // Force to 1 all status bits of + // MCSPI_IRQSTATUS register. Writing + // 1 into this bit sets to 1 all + // status bits contained in the + // register. +#define MCSPI_SYST_SPIENDIR 0x00000400 // Set the direction of the + // SPIEN[3:0] lines and SPICLK line + // 0 output (as in master mode) 1 + // input (as in slave mode) +#define MCSPI_SYST_SPIDATDIR1 0x00000200 // Set the direction of the + // SPIDAT[1] 0 output 1 input +#define MCSPI_SYST_SPIDATDIR0 0x00000100 // Set the direction of the + // SPIDAT[0] 0 output 1 input +#define MCSPI_SYST_WAKD 0x00000080 // SWAKEUP output (signal data + // value of internal signal to + // system). The signal is driven + // high or low according to the + // value written into this register + // bit. 0 The pin is driven low. 1 + // The pin is driven high. +#define MCSPI_SYST_SPICLK 0x00000040 // SPICLK line (signal data value) + // If MCSPI_SYST[SPIENDIR] = 1 + // (input mode direction) this bit + // returns the value on the CLKSPI + // line (high or low) and a write + // into this bit has no effect. If + // MCSPI_SYST[SPIENDIR] = 0 (output + // mode direction) the CLKSPI line + // is driven high or low according + // to the value written into this + // register. +#define MCSPI_SYST_SPIDAT_1 0x00000020 // SPIDAT[1] line (signal data + // value) If MCSPI_SYST[SPIDATDIR1] + // = 0 (output mode direction) the + // SPIDAT[1] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIDATDIR1] = 1 (input + // mode direction) this bit returns + // the value on the SPIDAT[1] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIDAT_0 0x00000010 // SPIDAT[0] line (signal data + // value) If MCSPI_SYST[SPIDATDIR0] + // = 0 (output mode direction) the + // SPIDAT[0] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIDATDIR0] = 1 (input + // mode direction) this bit returns + // the value on the SPIDAT[0] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_3 0x00000008 // SPIEN[3] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[3] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[3] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_2 0x00000004 // SPIEN[2] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[2] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[2] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_1 0x00000002 // SPIEN[1] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[1] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[1] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_0 0x00000001 // SPIEN[0] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[0] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[0] line + // (high or low) and a write into + // this bit has no effect. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_MODULCTRL register. +// +//****************************************************************************** +#define MCSPI_MODULCTRL_FDAA 0x00000100 // FIFO DMA Address 256-bit aligned + // This register is used when a FIFO + // is managed by the module and DMA + // connected to the controller + // provides only 256 bit aligned + // address. If this bit is set the + // enabled channel which uses the + // FIFO has its datas managed + // through MCSPI_DAFTX and + // MCSPI_DAFRX registers instead of + // MCSPI_TX(i) and MCSPI_RX(i) + // registers. 0 FIFO data managed by + // MCSPI_TX(i) and MCSPI_RX(i) + // registers. 1 FIFO data managed by + // MCSPI_DAFTX and MCSPI_DAFRX + // registers. +#define MCSPI_MODULCTRL_MOA 0x00000080 // Multiple word ocp access: This + // register can only be used when a + // channel is enabled using a FIFO. + // It allows the system to perform + // multiple SPI word access for a + // single 32-bit OCP word access. + // This is possible for WL < 16. 0 + // Multiple word access disabled 1 + // Multiple word access enabled with + // FIFO +#define MCSPI_MODULCTRL_INITDLY_M \ + 0x00000070 // Initial spi delay for first + // transfer: This register is an + // option only available in SINGLE + // master mode The controller waits + // for a delay to transmit the first + // spi word after channel enabled + // and corresponding TX register + // filled. This Delay is based on + // SPI output frequency clock No + // clock output provided to the + // boundary and chip select is not + // active in 4 pin mode within this + // period. 0x0 No delay for first + // spi transfer. 0x1 The controller + // wait 4 spi bus clock 0x2 The + // controller wait 8 spi bus clock + // 0x3 The controller wait 16 spi + // bus clock 0x4 The controller wait + // 32 spi bus clock + +#define MCSPI_MODULCTRL_INITDLY_S 4 +#define MCSPI_MODULCTRL_SYSTEM_TEST \ + 0x00000008 // Enables the system test mode 0 + // Functional mode 1 System test + // mode (SYSTEST) + +#define MCSPI_MODULCTRL_MS 0x00000004 // Master/ Slave 0 Master - The + // module generates the SPICLK and + // SPIEN[3:0] 1 Slave - The module + // receives the SPICLK and + // SPIEN[3:0] +#define MCSPI_MODULCTRL_PIN34 0x00000002 // Pin mode selection: This + // register is used to configure the + // SPI pin mode in master or slave + // mode. If asserted the controller + // only use SIMOSOMI and SPICLK + // clock pin for spi transfers. 0 + // SPIEN is used as a chip select. 1 + // SPIEN is not used.In this mode + // all related option to chip select + // have no meaning. +#define MCSPI_MODULCTRL_SINGLE 0x00000001 // Single channel / Multi Channel + // (master mode only) 0 More than + // one channel will be used in + // master mode. 1 Only one channel + // will be used in master mode. This + // bit must be set in Force SPIEN + // mode. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0CONF register. +// +//****************************************************************************** +#define MCSPI_CH0CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH0CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH0CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH0CONF_TCS0_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH0CONF_TCS0_S 25 +#define MCSPI_CH0CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH0CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH0CONF[SBPOL] +#define MCSPI_CH0CONF_SPIENSLV_M \ + 0x00600000 // Channel 0 only and slave mode + // only: SPI slave select signal + // detection. Reserved bits for + // other cases. 0x0 Detection + // enabled only on SPIEN[0] 0x1 + // Detection enabled only on + // SPIEN[1] 0x2 Detection enabled + // only on SPIEN[2] 0x3 Detection + // enabled only on SPIEN[3] + +#define MCSPI_CH0CONF_SPIENSLV_S 21 +#define MCSPI_CH0CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH0CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH0CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH0CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH0CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH0CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH0CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH0CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH0CONF_TRM_S 12 +#define MCSPI_CH0CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH0CONF_WL_S 7 +#define MCSPI_CH0CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH0CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH0CONF_CLKD_S 2 +#define MCSPI_CH0CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH0CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0STAT register. +// +//****************************************************************************** +#define MCSPI_CH0STAT_RXFFF 0x00000040 +#define MCSPI_CH0STAT_RXFFE 0x00000020 +#define MCSPI_CH0STAT_TXFFF 0x00000010 +#define MCSPI_CH0STAT_TXFFE 0x00000008 +#define MCSPI_CH0STAT_EOT 0x00000004 +#define MCSPI_CH0STAT_TXS 0x00000002 +#define MCSPI_CH0STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0CTRL register. +// +//****************************************************************************** +#define MCSPI_CH0CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH0CTRL_EXTCLK_S 8 +#define MCSPI_CH0CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX0 register. +// +//****************************************************************************** +#define MCSPI_TX0_TDATA_M 0xFFFFFFFF // Channel 0 Data to transmit +#define MCSPI_TX0_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX0 register. +// +//****************************************************************************** +#define MCSPI_RX0_RDATA_M 0xFFFFFFFF // Channel 0 Received Data +#define MCSPI_RX0_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1CONF register. +// +//****************************************************************************** +#define MCSPI_CH1CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH1CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH1CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH1CONF_TCS1_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH1CONF_TCS1_S 25 +#define MCSPI_CH1CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH1CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH1CONF[SBPOL] +#define MCSPI_CH1CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH1CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH1CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH1CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH1CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH1CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH1CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH1CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH1CONF_TRM_S 12 +#define MCSPI_CH1CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH1CONF_WL_S 7 +#define MCSPI_CH1CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH1CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH1CONF_CLKD_S 2 +#define MCSPI_CH1CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH1CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1STAT register. +// +//****************************************************************************** +#define MCSPI_CH1STAT_RXFFF 0x00000040 +#define MCSPI_CH1STAT_RXFFE 0x00000020 +#define MCSPI_CH1STAT_TXFFF 0x00000010 +#define MCSPI_CH1STAT_TXFFE 0x00000008 +#define MCSPI_CH1STAT_EOT 0x00000004 +#define MCSPI_CH1STAT_TXS 0x00000002 +#define MCSPI_CH1STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1CTRL register. +// +//****************************************************************************** +#define MCSPI_CH1CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH1CTRL_EXTCLK_S 8 +#define MCSPI_CH1CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX1 register. +// +//****************************************************************************** +#define MCSPI_TX1_TDATA_M 0xFFFFFFFF // Channel 1 Data to transmit +#define MCSPI_TX1_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX1 register. +// +//****************************************************************************** +#define MCSPI_RX1_RDATA_M 0xFFFFFFFF // Channel 1 Received Data +#define MCSPI_RX1_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2CONF register. +// +//****************************************************************************** +#define MCSPI_CH2CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH2CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH2CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH2CONF_TCS2_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH2CONF_TCS2_S 25 +#define MCSPI_CH2CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH2CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH2CONF[SBPOL] +#define MCSPI_CH2CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH2CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH2CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH2CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH2CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH2CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH2CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH2CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH2CONF_TRM_S 12 +#define MCSPI_CH2CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH2CONF_WL_S 7 +#define MCSPI_CH2CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH2CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH2CONF_CLKD_S 2 +#define MCSPI_CH2CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH2CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2STAT register. +// +//****************************************************************************** +#define MCSPI_CH2STAT_RXFFF 0x00000040 +#define MCSPI_CH2STAT_RXFFE 0x00000020 +#define MCSPI_CH2STAT_TXFFF 0x00000010 +#define MCSPI_CH2STAT_TXFFE 0x00000008 +#define MCSPI_CH2STAT_EOT 0x00000004 +#define MCSPI_CH2STAT_TXS 0x00000002 +#define MCSPI_CH2STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2CTRL register. +// +//****************************************************************************** +#define MCSPI_CH2CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH2CTRL_EXTCLK_S 8 +#define MCSPI_CH2CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX2 register. +// +//****************************************************************************** +#define MCSPI_TX2_TDATA_M 0xFFFFFFFF // Channel 2 Data to transmit +#define MCSPI_TX2_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX2 register. +// +//****************************************************************************** +#define MCSPI_RX2_RDATA_M 0xFFFFFFFF // Channel 2 Received Data +#define MCSPI_RX2_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3CONF register. +// +//****************************************************************************** +#define MCSPI_CH3CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH3CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH3CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH3CONF_TCS3_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH3CONF_TCS3_S 25 +#define MCSPI_CH3CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH3CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH3CONF[SBPOL] +#define MCSPI_CH3CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH3CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH3CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH3CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH3CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH3CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH3CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH3CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH3CONF_TRM_S 12 +#define MCSPI_CH3CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH3CONF_WL_S 7 +#define MCSPI_CH3CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH3CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH3CONF_CLKD_S 2 +#define MCSPI_CH3CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH3CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3STAT register. +// +//****************************************************************************** +#define MCSPI_CH3STAT_RXFFF 0x00000040 +#define MCSPI_CH3STAT_RXFFE 0x00000020 +#define MCSPI_CH3STAT_TXFFF 0x00000010 +#define MCSPI_CH3STAT_TXFFE 0x00000008 +#define MCSPI_CH3STAT_EOT 0x00000004 +#define MCSPI_CH3STAT_TXS 0x00000002 +#define MCSPI_CH3STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3CTRL register. +// +//****************************************************************************** +#define MCSPI_CH3CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH3CTRL_EXTCLK_S 8 +#define MCSPI_CH3CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX3 register. +// +//****************************************************************************** +#define MCSPI_TX3_TDATA_M 0xFFFFFFFF // Channel 3 Data to transmit +#define MCSPI_TX3_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX3 register. +// +//****************************************************************************** +#define MCSPI_RX3_RDATA_M 0xFFFFFFFF // Channel 3 Received Data +#define MCSPI_RX3_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register. +// +//****************************************************************************** +#define MCSPI_XFERLEVEL_WCNT_M 0xFFFF0000 // Spi word counterThis register + // holds the programmable value of + // number of SPI word to be + // transferred on channel which is + // using the FIFO buffer.When + // transfer had started a read back + // in this register returns the + // current SPI word transfer index. + // 0x0000 Counter not used 0x0001 + // one word 0xFFFE 65534 spi word + // 0xFFFF 65535 spi word +#define MCSPI_XFERLEVEL_WCNT_S 16 +#define MCSPI_XFERLEVEL_AFL_M 0x0000FF00 // Buffer Almost Full This register + // holds the programmable almost + // full level value used to + // determine almost full buffer + // condition. If the user wants an + // interrupt or a DMA read request + // to be issued during a receive + // operation when the data buffer + // holds at least n bytes then the + // buffer MCSPI_MODULCTRL[AFL] must + // be set with n-1.The size of this + // register is defined by the + // generic parameter FFNBYTE. 0x00 + // one byte 0x01 2 bytes 0xFE + // 255bytes 0xFF 256bytes +#define MCSPI_XFERLEVEL_AFL_S 8 +#define MCSPI_XFERLEVEL_AEL_M 0x000000FF // Buffer Almost EmptyThis register + // holds the programmable almost + // empty level value used to + // determine almost empty buffer + // condition. If the user wants an + // interrupt or a DMA write request + // to be issued during a transmit + // operation when the data buffer is + // able to receive n bytes then the + // buffer MCSPI_MODULCTRL[AEL] must + // be set with n-1. 0x00 one byte + // 0x01 2 bytes 0xFE 255 bytes 0xFF + // 256bytes +#define MCSPI_XFERLEVEL_AEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_DAFTX register. +// +//****************************************************************************** +#define MCSPI_DAFTX_DAFTDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA + // 256 bit aligned address. "This + // Register is only is used when + // MCSPI_MODULCTRL[FDAA] is set to + // ""1"" and only one of the + // MCSPI_CH(i)CONF[FFEW] of enabled + // channels is set. If these + // conditions are not respected any + // access to this register return a + // null value." +#define MCSPI_DAFTX_DAFTDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_DAFRX register. +// +//****************************************************************************** +#define MCSPI_DAFRX_DAFRDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA + // 256 bit aligned address. "This + // Register is only is used when + // MCSPI_MODULCTRL[FDAA] is set to + // ""1"" and only one of the + // MCSPI_CH(i)CONF[FFEW] of enabled + // channels is set. If these + // conditions are not respected any + // access to this register return a + // null value." +#define MCSPI_DAFRX_DAFRDATA_S 0 + + + +#endif // __HW_MCSPI_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_memmap.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_memmap.h new file mode 100755 index 00000000000..0919ee8c1d2 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_memmap.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the slave_1 interface. +// +//***************************************************************************** +#define FLASH_BASE 0x01000000 +#define SRAM_BASE 0x20000000 +#define WDT_BASE 0x40000000 +#define GPIOA0_BASE 0x40004000 +#define GPIOA1_BASE 0x40005000 +#define GPIOA2_BASE 0x40006000 +#define GPIOA3_BASE 0x40007000 +#define GPIOA4_BASE 0x40024000 +#define UARTA0_BASE 0x4000C000 +#define UARTA1_BASE 0x4000D000 +#define I2CA0_BASE 0x40020000 +#define TIMERA0_BASE 0x40030000 +#define TIMERA1_BASE 0x40031000 +#define TIMERA2_BASE 0x40032000 +#define TIMERA3_BASE 0x40033000 +#define STACKDIE_CTRL_BASE 0x400F5000 +#define COMMON_REG_BASE 0x400F7000 +#define FLASH_CONTROL_BASE 0x400FD000 +#define SYSTEM_CONTROL_BASE 0x400FE000 +#define UDMA_BASE 0x400FF000 +#define SDHOST_BASE 0x44010000 +#define CAMERA_BASE 0x44018000 +#define I2S_BASE 0x4401C000 +#define SSPI_BASE 0x44020000 +#define GSPI_BASE 0x44021000 +#define LSPI_BASE 0x44022000 +#define ARCM_BASE 0x44025000 +#define APPS_CONFIG_BASE 0x44026000 +#define GPRCM_BASE 0x4402D000 +#define OCP_SHARED_BASE 0x4402E000 +#define ADC_BASE 0x4402E800 +#define HIB1P2_BASE 0x4402F000 +#define HIB3P3_BASE 0x4402F800 +#define DTHE_BASE 0x44030000 +#define SHAMD5_BASE 0x44035000 +#define AES_BASE 0x44037000 +#define DES_BASE 0x44039000 + + +#endif // __HW_MEMMAP_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mmchs.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mmchs.h new file mode 100755 index 00000000000..88b8e755853 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_mmchs.h @@ -0,0 +1,1917 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_MMCHS_H__ +#define __HW_MMCHS_H__ + +//***************************************************************************** +// +// The following are defines for the MMCHS register offsets. +// +//***************************************************************************** +#define MMCHS_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) + // Used by software to track + // features bugs and compatibility +#define MMCHS_O_HL_HWINFO 0x00000004 // Information about the IP + // module's hardware configuration + // i.e. typically the module's HDL + // generics (if any). Actual field + // format and encoding is up to the + // module's designer to decide. +#define MMCHS_O_HL_SYSCONFIG 0x00000010 // Clock management configuration +#define MMCHS_O_SYSCONFIG 0x00000110 // System Configuration Register + // This register allows controlling + // various parameters of the OCP + // interface. +#define MMCHS_O_SYSSTATUS 0x00000114 // System Status Register This + // register provides status + // information about the module + // excluding the interrupt status + // information +#define MMCHS_O_CSRE 0x00000124 // Card status response error This + // register enables the host + // controller to detect card status + // errors of response type R1 R1b + // for all cards and of R5 R5b and + // R6 response for cards types SD or + // SDIO. When a bit MMCHS_CSRE[i] is + // set to 1 if the corresponding bit + // at the same position in the + // response MMCHS_RSP0[i] is set to + // 1 the host controller indicates a + // card error (MMCHS_STAT[CERR]) + // interrupt status to avoid the + // host driver reading the response + // register (MMCHS_RSP0). Note: No + // automatic card error detection + // for autoCMD12 is implemented; the + // host system has to check + // autoCMD12 response register + // (MMCHS_RESP76) for possible card + // errors. +#define MMCHS_O_SYSTEST 0x00000128 // System Test register This + // register is used to control the + // signals that connect to I/O pins + // when the module is configured in + // system test (SYSTEST) mode for + // boundary connectivity + // verification. Note: In SYSTEST + // mode a write into MMCHS_CMD + // register will not start a + // transfer. The buffer behaves as a + // stack accessible only by the + // local host (push and pop + // operations). In this mode the + // Transfer Block Size + // (MMCHS_BLK[BLEN]) and the Blocks + // count for current transfer + // (MMCHS_BLK[NBLK]) are needed to + // generate a Buffer write ready + // interrupt (MMCHS_STAT[BWR]) or a + // Buffer read ready interrupt + // (MMCHS_STAT[BRR]) and DMA + // requests if enabled. +#define MMCHS_O_CON 0x0000012C // Configuration register This + // register is used: - to select the + // functional mode or the SYSTEST + // mode for any card. - to send an + // initialization sequence to any + // card. - to enable the detection + // on DAT[1] of a card interrupt for + // SDIO cards only. and also to + // configure : - specific data and + // command transfers for MMC cards + // only. - the parameters related to + // the card detect and write protect + // input signals. +#define MMCHS_O_PWCNT 0x00000130 // Power counter register This + // register is used to program a mmc + // counter to delay command + // transfers after activating the + // PAD power this value depends on + // PAD characteristics and voltage. +#define MMCHS_O_BLK 0x00000204 // Transfer Length Configuration + // register MMCHS_BLK[BLEN] is the + // block size register. + // MMCHS_BLK[NBLK] is the block + // count register. This register + // shall be used for any card. +#define MMCHS_O_ARG 0x00000208 // Command argument Register This + // register contains command + // argument specified as bit 39-8 of + // Command-Format These registers + // must be initialized prior to + // sending the command itself to the + // card (write action into the + // register MMCHS_CMD register). + // Only exception is for a command + // index specifying stuff bits in + // arguments making a write + // unnecessary. +#define MMCHS_O_CMD 0x0000020C // Command and transfer mode + // register MMCHS_CMD[31:16] = the + // command register MMCHS_CMD[15:0] + // = the transfer mode. This + // register configures the data and + // command transfers. A write into + // the most significant byte send + // the command. A write into + // MMCHS_CMD[15:0] registers during + // data transfer has no effect. This + // register shall be used for any + // card. Note: In SYSTEST mode a + // write into MMCHS_CMD register + // will not start a transfer. +#define MMCHS_O_RSP10 0x00000210 // Command response[31:0] Register + // This 32-bit register holds bits + // positions [31:0] of command + // response type + // R1/R1b/R2/R3/R4/R5/R5b/R6 +#define MMCHS_O_RSP32 0x00000214 // Command response[63:32] Register + // This 32-bit register holds bits + // positions [63:32] of command + // response type R2 +#define MMCHS_O_RSP54 0x00000218 // Command response[95:64] Register + // This 32-bit register holds bits + // positions [95:64] of command + // response type R2 +#define MMCHS_O_RSP76 0x0000021C // Command response[127:96] + // Register This 32-bit register + // holds bits positions [127:96] of + // command response type R2 +#define MMCHS_O_DATA 0x00000220 // Data Register This register is + // the 32-bit entry point of the + // buffer for read or write data + // transfers. The buffer size is + // 32bits x256(1024 bytes). Bytes + // within a word are stored and read + // in little endian format. This + // buffer can be used as two 512 + // byte buffers to transfer data + // efficiently without reducing the + // throughput. Sequential and + // contiguous access is necessary to + // increment the pointer correctly. + // Random or skipped access is not + // allowed. In little endian if the + // local host accesses this register + // byte-wise or 16bit-wise the least + // significant byte (bits [7:0]) + // must always be written/read + // first. The update of the buffer + // address is done on the most + // significant byte write for full + // 32-bit DATA register or on the + // most significant byte of the last + // word of block transfer. Example + // 1: Byte or 16-bit access + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=1100 (2-bytes) OK + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=0100 (1-byte) OK + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=1000 (1-byte) Bad +#define MMCHS_O_PSTATE 0x00000224 // Present state register The Host + // can get status of the Host + // Controller from this 32-bit read + // only register. +#define MMCHS_O_HCTL 0x00000228 // Control register This register + // defines the host controls to set + // power wakeup and transfer + // parameters. MMCHS_HCTL[31:24] = + // Wakeup control MMCHS_HCTL[23:16] + // = Block gap control + // MMCHS_HCTL[15:8] = Power control + // MMCHS_HCTL[7:0] = Host control +#define MMCHS_O_SYSCTL 0x0000022C // SD system control register This + // register defines the system + // controls to set software resets + // clock frequency management and + // data timeout. MMCHS_SYSCTL[31:24] + // = Software resets + // MMCHS_SYSCTL[23:16] = Timeout + // control MMCHS_SYSCTL[15:0] = + // Clock control +#define MMCHS_O_STAT 0x00000230 // Interrupt status register The + // interrupt status regroups all the + // status of the module internal + // events that can generate an + // interrupt. MMCHS_STAT[31:16] = + // Error Interrupt Status + // MMCHS_STAT[15:0] = Normal + // Interrupt Status +#define MMCHS_O_IE 0x00000234 // Interrupt SD enable register + // This register allows to + // enable/disable the module to set + // status bits on an event-by-event + // basis. MMCHS_IE[31:16] = Error + // Interrupt Status Enable + // MMCHS_IE[15:0] = Normal Interrupt + // Status Enable +#define MMCHS_O_ISE 0x00000238 // Interrupt signal enable register + // This register allows to + // enable/disable the module + // internal sources of status on an + // event-by-event basis. + // MMCHS_ISE[31:16] = Error + // Interrupt Signal Enable + // MMCHS_ISE[15:0] = Normal + // Interrupt Signal Enable +#define MMCHS_O_AC12 0x0000023C // Auto CMD12 Error Status Register + // The host driver may determine + // which of the errors cases related + // to Auto CMD12 has occurred by + // checking this MMCHS_AC12 register + // when an Auto CMD12 Error + // interrupt occurs. This register + // is valid only when Auto CMD12 is + // enabled (MMCHS_CMD[ACEN]) and + // Auto CMD12Error (MMCHS_STAT[ACE]) + // is set to 1. Note: These bits are + // automatically reset when starting + // a new adtc command with data. +#define MMCHS_O_CAPA 0x00000240 // Capabilities register This + // register lists the capabilities + // of the MMC/SD/SDIO host + // controller. +#define MMCHS_O_CUR_CAPA 0x00000248 // Maximum current capabilities + // Register This register indicates + // the maximum current capability + // for each voltage. The value is + // meaningful if the voltage support + // is set in the capabilities + // register (MMCHS_CAPA). + // Initialization of this register + // (via a write access to this + // register) depends on the system + // capabilities. The host driver + // shall not modify this register + // after the initilaization. This + // register is only reinitialized by + // a hard reset (via RESETN signal) +#define MMCHS_O_FE 0x00000250 // Force Event Register for Error + // Interrupt status The force Event + // Register is not a physically + // implemented register. Rather it + // is an address at which the Error + // Interrupt Status register can be + // written. The effect of a write to + // this address will be reflected in + // the Error Interrupt Status + // Register if corresponding bit of + // the Error Interrupt Status Enable + // Register is set. +#define MMCHS_O_ADMAES 0x00000254 // ADMA Error Status Register When + // ADMA Error Interrupt is occurred + // the ADMA Error States field in + // this register holds the ADMA + // state and the ADMA System Address + // Register holds the address around + // the error descriptor. For + // recovering the error the Host + // Driver requires the ADMA state to + // identify the error descriptor + // address as follows: ST_STOP: + // Previous location set in the ADMA + // System Address register is the + // error descriptor address ST_FDS: + // Current location set in the ADMA + // System Address register is the + // error descriptor address ST_CADR: + // This sate is never set because do + // not generate ADMA error in this + // state. ST_TFR: Previous location + // set in the ADMA System Address + // register is the error descriptor + // address In case of write + // operation the Host Driver should + // use ACMD22 to get the number of + // written block rather than using + // this information since unwritten + // data may exist in the Host + // Controller. The Host Controller + // generates the ADMA Error + // Interrupt when it detects invalid + // descriptor data (Valid=0) at the + // ST_FDS state. In this case ADMA + // Error State indicates that an + // error occurs at ST_FDS state. The + // Host Driver may find that the + // Valid bit is not set in the error + // descriptor. +#define MMCHS_O_ADMASAL 0x00000258 // ADMA System address Low bits +#define MMCHS_O_REV 0x000002FC // Versions Register This register + // contains the hard coded RTL + // vendor revision number the + // version number of SD + // specification compliancy and a + // slot status bit. MMCHS_REV[31:16] + // = Host controller version + // MMCHS_REV[15:0] = Slot Interrupt + // Status + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HL_REV register. +// +//****************************************************************************** +#define MMCHS_HL_REV_SCHEME_M 0xC0000000 +#define MMCHS_HL_REV_SCHEME_S 30 +#define MMCHS_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define MMCHS_HL_REV_FUNC_S 16 +#define MMCHS_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define MMCHS_HL_REV_R_RTL_S 11 +#define MMCHS_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. +#define MMCHS_HL_REV_X_MAJOR_S 8 +#define MMCHS_HL_REV_CUSTOM_M 0x000000C0 +#define MMCHS_HL_REV_CUSTOM_S 6 +#define MMCHS_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. +#define MMCHS_HL_REV_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register. +// +//****************************************************************************** +#define MMCHS_HL_HWINFO_RETMODE 0x00000040 +#define MMCHS_HL_HWINFO_MEM_SIZE_M \ + 0x0000003C + +#define MMCHS_HL_HWINFO_MEM_SIZE_S 2 +#define MMCHS_HL_HWINFO_MERGE_MEM \ + 0x00000002 + +#define MMCHS_HL_HWINFO_MADMA_EN \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MMCHS_O_HL_SYSCONFIG register. +// +//****************************************************************************** +#define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \ + 0x00000030 // Configuration of the local + // initiator state management mode. + // By definition initiator may + // generate read/write transaction + // as long as it is out of STANDBY + // state. 0x0 Force-standby mode: + // local initiator is + // unconditionally placed in standby + // state.Backup mode for debug only. + // 0x1 No-standby mode: local + // initiator is unconditionally + // placed out of standby + // state.Backup mode for debug only. + // 0x2 Smart-standby mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator.IP module + // shall not generate + // (initiator-related) wakeup + // events. 0x3 "Smart-Standby + // wakeup-capable mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator. IP module may + // generate (master-related) wakeup + // events when in standby state.Mode + // is only relevant if the + // appropriate IP module ""mwakeup"" + // output is implemented." + +#define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4 +#define MMCHS_HL_SYSCONFIG_IDLEMODE_M \ + 0x0000000C // Configuration of the local + // target state management mode. By + // definition target can handle + // read/write transaction as long as + // it is out of IDLE state. 0x0 + // Force-idle mode: local target's + // idle state follows (acknowledges) + // the system's idle requests + // unconditionally i.e. regardless + // of the IP module's internal + // requirements.Backup mode for + // debug only. 0x1 No-idle mode: + // local target never enters idle + // state.Backup mode for debug only. + // 0x2 Smart-idle mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module shall not + // generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 "Smart-idle + // wakeup-capable mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2 +#define MMCHS_HL_SYSCONFIG_FREEEMU \ + 0x00000002 // Sensitivity to emulation (debug) + // suspend input signal. + // Functionality NOT implemented in + // MMCHS. 0 IP module is sensitive + // to emulation suspend 1 IP module + // is not sensitive to emulation + // suspend + +#define MMCHS_HL_SYSCONFIG_SOFTRESET \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register. +// +//****************************************************************************** +#define MMCHS_SYSCONFIG_STANDBYMODE_M \ + 0x00003000 // Master interface power + // Management standby/wait control. + // The bit field is only useful when + // generic parameter MADMA_EN + // (Master ADMA enable) is set as + // active otherwise it is a read + // only register read a '0'. 0x0 + // Force-standby. Mstandby is forced + // unconditionnaly. 0x1 No-standby. + // Mstandby is never asserted. 0x2 + // Smart-standby mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator.IP module + // shall not generate + // (initiator-related) wakeup + // events. 0x3 Smart-Standby + // wakeup-capable mode: "local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator. IP module may + // generate (master-related) wakeup + // events when in standby state.Mode + // is only relevant if the + // appropriate IP module ""mwakeup"" + // output is implemented." + +#define MMCHS_SYSCONFIG_STANDBYMODE_S 12 +#define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \ + 0x00000300 // Clocks activity during wake up + // mode period. Bit8: OCP interface + // clock Bit9: Functional clock 0x0 + // OCP and Functional clock may be + // switched off. 0x1 OCP clock is + // maintained. Functional clock may + // be switched-off. 0x2 Functional + // clock is maintained. OCP clock + // may be switched-off. 0x3 OCP and + // Functional clocks are maintained. + +#define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8 +#define MMCHS_SYSCONFIG_SIDLEMODE_M \ + 0x00000018 // Power management 0x0 If an idle + // request is detected the MMCHS + // acknowledges it unconditionally + // and goes in Inactive mode. + // Interrupt and DMA requests are + // unconditionally de-asserted. 0x1 + // If an idle request is detected + // the request is ignored and the + // module keeps on behaving + // normally. 0x2 Smart-idle mode: + // local target's idle state + // eventually follows (acknowledges) + // the system's idle requests + // depending on the IP module's + // internal requirements.IP module + // shall not generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 Smart-idle + // wakeup-capable mode: "local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MMCHS_SYSCONFIG_SIDLEMODE_S 3 +#define MMCHS_SYSCONFIG_ENAWAKEUP \ + 0x00000004 // Wakeup feature control 0 Wakeup + // capability is disabled 1 Wakeup + // capability is enabled + +#define MMCHS_SYSCONFIG_SOFTRESET \ + 0x00000002 + +#define MMCHS_SYSCONFIG_AUTOIDLE \ + 0x00000001 // Internal Clock gating strategy 0 + // Clocks are free-running 1 + // Automatic clock gating strategy + // is applied based on the OCP and + // MMC interface activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register. +// +//****************************************************************************** +#define MMCHS_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CSRE register. +// +//****************************************************************************** +#define MMCHS_CSRE_CSRE_M 0xFFFFFFFF // Card status response error +#define MMCHS_CSRE_CSRE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSTEST register. +// +//****************************************************************************** +#define MMCHS_SYSTEST_OBI 0x00010000 +#define MMCHS_SYSTEST_SDCD 0x00008000 +#define MMCHS_SYSTEST_SDWP 0x00004000 +#define MMCHS_SYSTEST_WAKD 0x00002000 +#define MMCHS_SYSTEST_SSB 0x00001000 +#define MMCHS_SYSTEST_D7D 0x00000800 +#define MMCHS_SYSTEST_D6D 0x00000400 +#define MMCHS_SYSTEST_D5D 0x00000200 +#define MMCHS_SYSTEST_D4D 0x00000100 +#define MMCHS_SYSTEST_D3D 0x00000080 +#define MMCHS_SYSTEST_D2D 0x00000040 +#define MMCHS_SYSTEST_D1D 0x00000020 +#define MMCHS_SYSTEST_D0D 0x00000010 +#define MMCHS_SYSTEST_DDIR 0x00000008 +#define MMCHS_SYSTEST_CDAT 0x00000004 +#define MMCHS_SYSTEST_CDIR 0x00000002 +#define MMCHS_SYSTEST_MCKD 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CON register. +// +//****************************************************************************** +#define MMCHS_CON_SDMA_LNE 0x00200000 // Slave DMA Level/Edge Request: + // The waveform of the DMA request + // can be configured either edge + // sensitive with early de-assertion + // on first access to MMCHS_DATA + // register or late de-assertion + // request remains active until last + // allowed data written into + // MMCHS_DATA. 0 Slave DMA edge + // sensitive Early DMA de-assertion + // 1 Slave DMA level sensitive Late + // DMA de-assertion +#define MMCHS_CON_DMA_MNS 0x00100000 // DMA Master or Slave selection: + // When this bit is set and the + // controller is configured to use + // the DMA Ocp master interface is + // used to get datas from system + // using ADMA2 procedure (direct + // access to the memory).This option + // is only available if generic + // parameter MADMA_EN is asserted to + // '1'. 0 The controller is slave on + // data transfers with system. 1 The + // controller is master on data + // exchange with system controller + // must be configured as using DMA. +#define MMCHS_CON_DDR 0x00080000 // Dual Data Rate mode: When this + // register is set the controller + // uses both clock edge to emit or + // receive data. Odd bytes are + // transmitted on falling edges and + // even bytes are transmitted on + // rise edges. It only applies on + // Data bytes and CRC Start end bits + // and CRC status are kept full + // cycle. This bit field is only + // meaningful and active for even + // clock divider ratio of + // MMCHS_SYSCTL[CLKD] it is + // insensitive to MMCHS_HCTL[HSPE] + // setting. 0 Standard mode : data + // are transmitted on a single edge + // depending on MMCHS_HCTRL[HSPE]. 1 + // Data Bytes and CRC are + // transmitted on both edge. +#define MMCHS_CON_BOOT_CF0 0x00040000 +#define MMCHS_CON_BOOT_ACK 0x00020000 // Book acknowledge received: When + // this bit is set the controller + // should receive a boot status on + // DAT0 line after next command + // issued. If no status is received + // a data timeout will be generated. + // 0 No acknowledge to be received 1 + // A boot status will be received on + // DAT0 line after issuing a + // command. +#define MMCHS_CON_CLKEXTFREE 0x00010000 // External clock free running: + // This register is used to maintain + // card clock out of transfer + // transaction to enable slave + // module for example to generate a + // synchronous interrupt on DAT[1]. + // The Clock will be maintain only + // if MMCHS_SYSCTL[CEN] is set. 0 + // External card clock is cut off + // outside active transaction + // period. 1 External card clock is + // maintain even out of active + // transaction period only if + // MMCHS_SYSCTL[CEN] is set. +#define MMCHS_CON_PADEN 0x00008000 // Control Power for MMC Lines: + // This register is only useful when + // MMC PADs contain power saving + // mechanism to minimize its leakage + // power. It works as a GPIO that + // directly control the ACTIVE pin + // of PADs. Excepted for DAT[1] the + // signal is also combine outside + // the module with the dedicated + // power control MMCHS_CON[CTPL] + // bit. 0 ADPIDLE module pin is not + // forced it is automatically + // generated by the MMC fsms. 1 + // ADPIDLE module pin is forced to + // active state. +#define MMCHS_CON_OBIE 0x00004000 // Out-of-Band Interrupt Enable MMC + // cards only: This bit enables the + // detection of Out-of-Band + // Interrupt on MMCOBI input pin. + // The usage of the Out-of-Band + // signal (OBI) is optional and + // depends on the system + // integration. 0 Out-of-Band + // interrupt detection disabled 1 + // Out-of-Band interrupt detection + // enabled +#define MMCHS_CON_OBIP 0x00002000 // Out-of-Band Interrupt Polarity + // MMC cards only: This bit selects + // the active level of the + // out-of-band interrupt coming from + // MMC cards. The usage of the + // Out-of-Band signal (OBI) is + // optional and depends on the + // system integration. 0 active high + // level 1 active low level +#define MMCHS_CON_CEATA 0x00001000 // CE-ATA control mode MMC cards + // compliant with CE-ATA:By default + // this bit is set to 0. It is use + // to indicate that next commands + // are considered as specific CE-ATA + // commands that potentially use + // 'command completion' features. 0 + // Standard MMC/SD/SDIO mode. 1 + // CE-ATA mode next commands are + // considered as CE-ATA commands. +#define MMCHS_CON_CTPL 0x00000800 // Control Power for DAT[1] line + // MMC and SD cards: By default this + // bit is set to 0 and the host + // controller automatically disables + // all the input buffers outside of + // a transaction to minimize the + // leakage current. SDIO cards: When + // this bit is set to 1 the host + // controller automatically disables + // all the input buffers except the + // buffer of DAT[1] outside of a + // transaction in order to detect + // asynchronous card interrupt on + // DAT[1] line and minimize the + // leakage current of the buffers. 0 + // Disable all the input buffers + // outside of a transaction. 1 + // Disable all the input buffers + // except the buffer of DAT[1] + // outside of a transaction. +#define MMCHS_CON_DVAL_M 0x00000600 // Debounce filter value All cards + // This register is used to define a + // debounce period to filter the + // card detect input signal (SDCD). + // The usage of the card detect + // input signal (SDCD) is optional + // and depends on the system + // integration and the type of the + // connector housing that + // accommodates the card. 0x0 33 us + // debounce period 0x1 231 us + // debounce period 0x2 1 ms debounce + // period 0x3 84 ms debounce period +#define MMCHS_CON_DVAL_S 9 +#define MMCHS_CON_WPP 0x00000100 // Write protect polarity For SD + // and SDIO cards only This bit + // selects the active level of the + // write protect input signal + // (SDWP). The usage of the write + // protect input signal (SDWP) is + // optional and depends on the + // system integration and the type + // of the connector housing that + // accommodates the card. 0 active + // high level 1 active low level +#define MMCHS_CON_CDP 0x00000080 // Card detect polarity All cards + // This bit selects the active level + // of the card detect input signal + // (SDCD). The usage of the card + // detect input signal (SDCD) is + // optional and depends on the + // system integration and the type + // of the connector housing that + // accommodates the card. 0 active + // high level 1 active low level +#define MMCHS_CON_MIT 0x00000040 // MMC interrupt command Only for + // MMC cards. This bit must be set + // to 1 when the next write access + // to the command register + // (MMCHS_CMD) is for writing a MMC + // interrupt command (CMD40) + // requiring the command timeout + // detection to be disabled for the + // command response. 0 Command + // timeout enabled 1 Command timeout + // disabled +#define MMCHS_CON_DW8 0x00000020 // 8-bit mode MMC select For + // SD/SDIO cards this bit must be + // set to 0. For MMC card this bit + // must be set following a valid + // SWITCH command (CMD6) with the + // correct value and extend CSD + // index written in the argument. + // Prior to this command the MMC + // card configuration register (CSD + // and EXT_CSD) must be verified for + // compliancy with MMC standard + // specification 4.x (see section + // 3.6). 0 1-bit or 4-bit Data width + // (DAT[0] used MMC SD cards) 1 + // 8-bit Data width (DAT[7:0] used + // MMC cards) +#define MMCHS_CON_MODE 0x00000010 // Mode select All cards These bits + // select between Functional mode + // and SYSTEST mode. 0 Functional + // mode. Transfers to the + // MMC/SD/SDIO cards follow the card + // protocol. MMC clock is enabled. + // MMC/SD transfers are operated + // under the control of the CMD + // register. 1 SYSTEST mode The + // signal pins are configured as + // general-purpose input/output and + // the 1024-byte buffer is + // configured as a stack memory + // accessible only by the local host + // or system DMA. The pins retain + // their default type (input output + // or in-out). SYSTEST mode is + // operated under the control of the + // SYSTEST register. +#define MMCHS_CON_STR 0x00000008 // Stream command Only for MMC + // cards. This bit must be set to 1 + // only for the stream data + // transfers (read or write) of the + // adtc commands. Stream read is a + // class 1 command (CMD11: + // READ_DAT_UNTIL_STOP). Stream + // write is a class 3 command + // (CMD20: WRITE_DAT_UNTIL_STOP). 0 + // Block oriented data transfer 1 + // Stream oriented data transfer +#define MMCHS_CON_HR 0x00000004 // Broadcast host response Only for + // MMC cards. This register is used + // to force the host to generate a + // 48-bit response for bc command + // type. "It can be used to + // terminate the interrupt mode by + // generating a CMD40 response by + // the core (see section 4.3 + // ""Interrupt Mode"" in the MMC [1] + // specification). In order to have + // the host response to be generated + // in open drain mode the register + // MMCHS_CON[OD] must be set to 1." + // When MMCHS_CON[CEATA] is set to 1 + // and MMCHS_ARG set to 0x00000000 + // when writing 0x00000000 into + // MMCHS_CMD register the host + // controller performs a 'command + // completion signal disable' token + // i.e. CMD line held to '0' during + // 47 cycles followed by a 1. 0 The + // host does not generate a 48-bit + // response instead of a command. 1 + // The host generates a 48-bit + // response instead of a command or + // a command completion signal + // disable token. +#define MMCHS_CON_INIT 0x00000002 // Send initialization stream All + // cards. When this bit is set to 1 + // and the card is idle an + // initialization sequence is sent + // to the card. "An initialization + // sequence consists of setting the + // CMD line to 1 during 80 clock + // cycles. The initialisation + // sequence is mandatory - but it is + // not required to do it through + // this bit - this bit makes it + // easier. Clock divider + // (MMCHS_SYSCTL[CLKD]) should be + // set to ensure that 80 clock + // periods are greater than 1ms. + // (see section 9.3 ""Power-Up"" in + // the MMC card specification [1] or + // section 6.4 in the SD card + // specification [2])." Note: in + // this mode there is no command + // sent to the card and no response + // is expected 0 The host does not + // send an initialization sequence. + // 1 The host sends an + // initialization sequence. +#define MMCHS_CON_OD 0x00000001 // Card open drain mode. Only for + // MMC cards. This bit must be set + // to 1 for MMC card commands 1 2 3 + // and 40 and if the MMC card bus is + // operating in open-drain mode + // during the response phase to the + // command sent. Typically during + // card identification mode when the + // card is either in idle ready or + // ident state. It is also necessary + // to set this bit to 1 for a + // broadcast host response (see + // Broadcast host response register + // MMCHS_CON[HR]) 0 No Open Drain 1 + // Open Drain or Broadcast host + // response +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_PWCNT register. +// +//****************************************************************************** +#define MMCHS_PWCNT_PWRCNT_M 0x0000FFFF // Power counter register. This + // register is used to introduce a + // delay between the PAD ACTIVE pin + // assertion and the command issued. + // 0x0000 No additional delay added + // 0x0001 TCF delay (card clock + // period) 0x0002 TCF x 2 delay + // (card clock period) 0xFFFE TCF x + // 65534 delay (card clock period) + // 0xFFFF TCF x 65535 delay (card + // clock period) +#define MMCHS_PWCNT_PWRCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_BLK register. +// +//****************************************************************************** +#define MMCHS_BLK_NBLK_M 0xFFFF0000 // Blocks count for current + // transfer This register is enabled + // when Block count Enable + // (MMCHS_CMD[BCE]) is set to 1 and + // is valid only for multiple block + // transfers. Setting the block + // count to 0 results no data blocks + // being transferred. Note: The host + // controller decrements the block + // count after each block transfer + // and stops when the count reaches + // zero. This register can be + // accessed only if no transaction + // is executing (i.e after a + // transaction has stopped). Read + // operations during transfers may + // return an invalid value and write + // operation will be ignored. In + // suspend context the number of + // blocks yet to be transferred can + // be determined by reading this + // register. When restoring transfer + // context prior to issuing a Resume + // command The local host shall + // restore the previously saved + // block count. 0x0000 Stop count + // 0x0001 1 block 0x0002 2 blocks + // 0xFFFF 65535 blocks +#define MMCHS_BLK_NBLK_S 16 +#define MMCHS_BLK_BLEN_M 0x00000FFF // Transfer Block Size. This + // register specifies the block size + // for block data transfers. Read + // operations during transfers may + // return an invalid value and write + // operations are ignored. When a + // CMD12 command is issued to stop + // the transfer a read of the BLEN + // field after transfer completion + // (MMCHS_STAT[TC] set to 1) will + // not return the true byte number + // of data length while the stop + // occurs but the value written in + // this register before transfer is + // launched. 0x000 No data transfer + // 0x001 1 byte block length 0x002 2 + // bytes block length 0x003 3 bytes + // block length 0x1FF 511 bytes + // block length 0x200 512 bytes + // block length 0x7FF 2047 bytes + // block length 0x800 2048 bytes + // block length +#define MMCHS_BLK_BLEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ARG register. +// +//****************************************************************************** +#define MMCHS_ARG_ARG_M 0xFFFFFFFF // Command argument bits [31:0] +#define MMCHS_ARG_ARG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CMD register. +// +//****************************************************************************** +#define MMCHS_CMD_INDX_M 0x3F000000 // Command index Binary encoded + // value from 0 to 63 specifying the + // command number send to card 0x00 + // CMD0 or ACMD0 0x01 CMD1 or ACMD1 + // 0x02 CMD2 or ACMD2 0x03 CMD3 or + // ACMD3 0x04 CMD4 or ACMD4 0x05 + // CMD5 or ACMD5 0x06 CMD6 or ACMD6 + // 0x07 CMD7 or ACMD7 0x08 CMD8 or + // ACMD8 0x09 CMD9 or ACMD9 0x0A + // CMD10 or ACMD10 0x0B CMD11 or + // ACMD11 0x0C CMD12 or ACMD12 0x0D + // CMD13 or ACMD13 0x0E CMD14 or + // ACMD14 0x0F CMD15 or ACMD15 0x10 + // CMD16 or ACMD16 0x11 CMD17 or + // ACMD17 0x12 CMD18 or ACMD18 0x13 + // CMD19 or ACMD19 0x14 CMD20 or + // ACMD20 0x15 CMD21 or ACMD21 0x16 + // CMD22 or ACMD22 0x17 CMD23 or + // ACMD23 0x18 CMD24 or ACMD24 0x19 + // CMD25 or ACMD25 0x1A CMD26 or + // ACMD26 0x1B CMD27 or ACMD27 0x1C + // CMD28 or ACMD28 0x1D CMD29 or + // ACMD29 0x1E CMD30 or ACMD30 0x1F + // CMD31 or ACMD31 0x20 CMD32 or + // ACMD32 0x21 CMD33 or ACMD33 0x22 + // CMD34 or ACMD34 0x23 CMD35 or + // ACMD35 0x24 CMD36 or ACMD36 0x25 + // CMD37 or ACMD37 0x26 CMD38 or + // ACMD38 0x27 CMD39 or ACMD39 0x28 + // CMD40 or ACMD40 0x29 CMD41 or + // ACMD41 0x2A CMD42 or ACMD42 0x2B + // CMD43 or ACMD43 0x2C CMD44 or + // ACMD44 0x2D CMD45 or ACMD45 0x2E + // CMD46 or ACMD46 0x2F CMD47 or + // ACMD47 0x30 CMD48 or ACMD48 0x31 + // CMD49 or ACMD49 0x32 CMD50 or + // ACMD50 0x33 CMD51 or ACMD51 0x34 + // CMD52 or ACMD52 0x35 CMD53 or + // ACMD53 0x36 CMD54 or ACMD54 0x37 + // CMD55 or ACMD55 0x38 CMD56 or + // ACMD56 0x39 CMD57 or ACMD57 0x3A + // CMD58 or ACMD58 0x3B CMD59 or + // ACMD59 0x3C CMD60 or ACMD60 0x3D + // CMD61 or ACMD61 0x3E CMD62 or + // ACMD62 0x3F CMD63 or ACMD63 +#define MMCHS_CMD_INDX_S 24 +#define MMCHS_CMD_CMD_TYPE_M 0x00C00000 // Command type This register + // specifies three types of special + // command: Suspend Resume and + // Abort. These bits shall be set to + // 00b for all other commands. 0x0 + // Others Commands 0x1 "CMD52 for + // writing ""Bus Suspend"" in CCCR" + // 0x2 "CMD52 for writing ""Function + // Select"" in CCCR" 0x3 "Abort + // command CMD12 CMD52 for writing + // "" I/O Abort"" in CCCR" +#define MMCHS_CMD_CMD_TYPE_S 22 +#define MMCHS_CMD_DP 0x00200000 // Data present select This + // register indicates that data is + // present and DAT line shall be + // used. It must be set to 0 in the + // following conditions: - command + // using only CMD line - command + // with no data transfer but using + // busy signal on DAT[0] - Resume + // command 0 Command with no data + // transfer 1 Command with data + // transfer +#define MMCHS_CMD_CICE 0x00100000 // Command Index check enable This + // bit must be set to 1 to enable + // index check on command response + // to compare the index field in the + // response against the index of the + // command. If the index is not the + // same in the response as in the + // command it is reported as a + // command index error + // (MMCHS_STAT[CIE] set to1) Note: + // The register CICE cannot be + // configured for an Auto CMD12 then + // index check is automatically + // checked when this command is + // issued. 0 Index check disable 1 + // Index check enable +#define MMCHS_CMD_CCCE 0x00080000 // Command CRC check enable This + // bit must be set to 1 to enable + // CRC7 check on command response to + // protect the response against + // transmission errors on the bus. + // If an error is detected it is + // reported as a command CRC error + // (MMCHS_STAT[CCRC] set to 1). + // Note: The register CCCE cannot be + // configured for an Auto CMD12 and + // then CRC check is automatically + // checked when this command is + // issued. 0 CRC7 check disable 1 + // CRC7 check enable +#define MMCHS_CMD_RSP_TYPE_M 0x00030000 // Response type This bits defines + // the response type of the command + // 0x0 No response 0x1 Response + // Length 136 bits 0x2 Response + // Length 48 bits 0x3 Response + // Length 48 bits with busy after + // response +#define MMCHS_CMD_RSP_TYPE_S 16 +#define MMCHS_CMD_MSBS 0x00000020 // Multi/Single block select This + // bit must be set to 1 for data + // transfer in case of multi block + // command. For any others command + // this bit shall be set to 0. 0 + // Single block. If this bit is 0 it + // is not necessary to set the + // register MMCHS_BLK[NBLK]. 1 Multi + // block. When Block Count is + // disabled (MMCHS_CMD[BCE] is set + // to 0) in Multiple block transfers + // (MMCHS_CMD[MSBS] is set to 1) the + // module can perform infinite + // transfer. +#define MMCHS_CMD_DDIR 0x00000010 // Data transfer Direction Select + // This bit defines either data + // transfer will be a read or a + // write. 0 Data Write (host to + // card) 1 Data Read (card to host) +#define MMCHS_CMD_ACEN 0x00000004 // Auto CMD12 Enable SD card only. + // When this bit is set to 1 the + // host controller issues a CMD12 + // automatically after the transfer + // completion of the last block. The + // Host Driver shall not set this + // bit to issue commands that do not + // require CMD12 to stop data + // transfer. In particular secure + // commands do not require CMD12. 0 + // Auto CMD12 disable 1 Auto CMD12 + // enable or CCS detection enabled. +#define MMCHS_CMD_BCE 0x00000002 // Block Count Enable Multiple + // block transfers only. This bit is + // used to enable the block count + // register (MMCHS_BLK[NBLK]). When + // Block Count is disabled + // (MMCHS_CMD[BCE] is set to 0) in + // Multiple block transfers + // (MMCHS_CMD[MSBS] is set to 1) the + // module can perform infinite + // transfer. 0 Block count disabled + // for infinite transfer. 1 Block + // count enabled for multiple block + // transfer with known number of + // blocks +#define MMCHS_CMD_DE 0x00000001 // DMA Enable This bit is used to + // enable DMA mode for host data + // access. 0 DMA mode disable 1 DMA + // mode enable +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP10 register. +// +//****************************************************************************** +#define MMCHS_RSP10_RSP1_M 0xFFFF0000 // Command Response [31:16] +#define MMCHS_RSP10_RSP1_S 16 +#define MMCHS_RSP10_RSP0_M 0x0000FFFF // Command Response [15:0] +#define MMCHS_RSP10_RSP0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP32 register. +// +//****************************************************************************** +#define MMCHS_RSP32_RSP3_M 0xFFFF0000 // Command Response [63:48] +#define MMCHS_RSP32_RSP3_S 16 +#define MMCHS_RSP32_RSP2_M 0x0000FFFF // Command Response [47:32] +#define MMCHS_RSP32_RSP2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP54 register. +// +//****************************************************************************** +#define MMCHS_RSP54_RSP5_M 0xFFFF0000 // Command Response [95:80] +#define MMCHS_RSP54_RSP5_S 16 +#define MMCHS_RSP54_RSP4_M 0x0000FFFF // Command Response [79:64] +#define MMCHS_RSP54_RSP4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP76 register. +// +//****************************************************************************** +#define MMCHS_RSP76_RSP7_M 0xFFFF0000 // Command Response [127:112] +#define MMCHS_RSP76_RSP7_S 16 +#define MMCHS_RSP76_RSP6_M 0x0000FFFF // Command Response [111:96] +#define MMCHS_RSP76_RSP6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_DATA register. +// +//****************************************************************************** +#define MMCHS_DATA_DATA_M 0xFFFFFFFF // Data Register [31:0] In + // functional mode (MMCHS_CON[MODE] + // set to the default value 0) A + // read access to this register is + // allowed only when the buffer read + // enable status is set to 1 + // (MMCHS_PSTATE[BRE]) otherwise a + // bad access (MMCHS_STAT[BADA]) is + // signaled. A write access to this + // register is allowed only when the + // buffer write enable status is set + // to 1(MMCHS_STATE[BWE]) otherwise + // a bad access (MMCHS_STAT[BADA]) + // is signaled and the data is not + // written. +#define MMCHS_DATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_PSTATE register. +// +//****************************************************************************** +#define MMCHS_PSTATE_CLEV 0x01000000 +#define MMCHS_PSTATE_DLEV_M 0x00F00000 // DAT[3:0] line signal level + // DAT[3] => bit 23 DAT[2] => bit 22 + // DAT[1] => bit 21 DAT[0] => bit 20 + // This status is used to check DAT + // line level to recover from errors + // and for debugging. This is + // especially useful in detecting + // the busy signal level from + // DAT[0]. The value of these + // registers after reset depends on + // the DAT lines level at that time. +#define MMCHS_PSTATE_DLEV_S 20 +#define MMCHS_PSTATE_WP 0x00080000 +#define MMCHS_PSTATE_CDPL 0x00040000 +#define MMCHS_PSTATE_CSS 0x00020000 +#define MMCHS_PSTATE_CINS 0x00010000 +#define MMCHS_PSTATE_BRE 0x00000800 +#define MMCHS_PSTATE_BWE 0x00000400 +#define MMCHS_PSTATE_RTA 0x00000200 +#define MMCHS_PSTATE_WTA 0x00000100 +#define MMCHS_PSTATE_DLA 0x00000004 +#define MMCHS_PSTATE_DATI 0x00000002 +#define MMCHS_PSTATE_CMDI 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HCTL register. +// +//****************************************************************************** +#define MMCHS_HCTL_OBWE 0x08000000 // Wakeup event enable for + // 'Out-of-Band' Interrupt. This bit + // enables wakeup events for + // 'Out-of-Band' assertion. Wakeup + // is generated if the wakeup + // feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). The + // write to this register is ignored + // when MMCHS_CON[OBIE] is not set. + // 0 Disable wakeup on 'Out-of-Band' + // Interrupt 1 Enable wakeup on + // 'Out-of-Band' Interrupt +#define MMCHS_HCTL_REM 0x04000000 // Wakeup event enable on SD card + // removal This bit enables wakeup + // events for card removal + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card removal 1 + // Enable wakeup on card removal +#define MMCHS_HCTL_INS 0x02000000 // Wakeup event enable on SD card + // insertion This bit enables wakeup + // events for card insertion + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card insertion + // 1 Enable wakeup on card insertion +#define MMCHS_HCTL_IWE 0x01000000 // Wakeup event enable on SD card + // interrupt This bit enables wakeup + // events for card interrupt + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card interrupt + // 1 Enable wakeup on card interrupt +#define MMCHS_HCTL_IBG 0x00080000 // Interrupt block at gap This bit + // is valid only in 4-bit mode of + // SDIO card to enable interrupt + // detection in the interrupt cycle + // at block gap for a multiple block + // transfer. For MMC cards and for + // SD card this bit should be set to + // 0. 0 Disable interrupt detection + // at the block gap in 4-bit mode 1 + // Enable interrupt detection at the + // block gap in 4-bit mode +#define MMCHS_HCTL_RWC 0x00040000 // Read wait control The read wait + // function is optional only for + // SDIO cards. If the card supports + // read wait this bit must be + // enabled then requesting a stop at + // block gap (MMCHS_HCTL[SBGR]) + // generates a read wait period + // after the current end of block. + // Be careful if read wait is not + // supported it may cause a conflict + // on DAT line. 0 Disable Read Wait + // Control. Suspend/Resume cannot be + // supported. 1 Enable Read Wait + // Control +#define MMCHS_HCTL_CR 0x00020000 // Continue request This bit is + // used to restart a transaction + // that was stopped by requesting a + // stop at block gap + // (MMCHS_HCTL[SBGR]). Set this bit + // to 1 restarts the transfer. The + // bit is automatically set to 0 by + // the host controller when transfer + // has restarted i.e DAT line is + // active (MMCHS_PSTATE[DLA]) or + // transferring data + // (MMCHS_PSTATE[WTA]). The Stop at + // block gap request must be + // disabled (MMCHS_HCTL[SBGR]=0) + // before setting this bit. 0 No + // affect 1 transfer restart +#define MMCHS_HCTL_SBGR 0x00010000 // Stop at block gap request This + // bit is used to stop executing a + // transaction at the next block + // gap. The transfer can restart + // with a continue request + // (MMHS_HCTL[CR]) or during a + // suspend/resume sequence. In case + // of read transfer the card must + // support read wait control. In + // case of write transfer the host + // driver shall set this bit after + // all block data written. Until the + // transfer completion + // (MMCHS_STAT[TC] set to 1) the + // host driver shall leave this bit + // set to 1. If this bit is set the + // local host shall not write to the + // data register (MMCHS_DATA). 0 + // Transfer mode 1 Stop at block gap +#define MMCHS_HCTL_SDVS_M 0x00000E00 // SD bus voltage select All cards. + // The host driver should set to + // these bits to select the voltage + // level for the card according to + // the voltage supported by the + // system (MMCHS_CAPA[VS18VS30VS33]) + // before starting a transfer. 0x5 + // 1.8V (Typical) 0x6 3.0V (Typical) + // 0x7 3.3V (Typical) +#define MMCHS_HCTL_SDVS_S 9 +#define MMCHS_HCTL_SDBP 0x00000100 // SD bus power Before setting this + // bit the host driver shall select + // the SD bus voltage + // (MMCHS_HCTL[SDVS]). If the host + // controller detects the No card + // state this bit is automatically + // set to 0. If the module is power + // off a write in the command + // register (MMCHS_CMD) will not + // start the transfer. A write to + // this bit has no effect if the + // selected SD bus voltage + // MMCHS_HCTL[SDVS] is not supported + // according to capability register + // (MMCHS_CAPA[VS*]). 0 Power off 1 + // Power on +#define MMCHS_HCTL_CDSS 0x00000080 // Card Detect Signal Selection + // This bit selects source for the + // card detection.When the source + // for the card detection is + // switched the interrupt should be + // disabled during the switching + // period by clearing the Interrupt + // Status/Signal Enable register in + // order to mask unexpected + // interrupt being caused by the + // glitch. The Interrupt + // Status/Signal Enable should be + // disabled during over the period + // of debouncing. 0 SDCD# is + // selected (for normal use) 1 The + // Card Detect Test Level is + // selected (for test purpose) +#define MMCHS_HCTL_CDTL 0x00000040 // Card Detect Test Level: This bit + // is enabled while the Card Detect + // Signal Selection is set to 1 and + // it indicates card inserted or + // not. 0 No Card 1 Card Inserted +#define MMCHS_HCTL_DMAS_M 0x00000018 // DMA Select Mode: One of + // supported DMA modes can be + // selected. The host driver shall + // check support of DMA modes by + // referring the Capabilities + // register. Use of selected DMA is + // determined by DMA Enable of the + // Transfer Mode register. This + // register is only meaningful when + // MADMA_EN is set to 1. When + // MADMA_EN is set to 0 the bit + // field is read only and returned + // value is 0. 0x0 Reserved 0x1 + // Reserved 0x2 32-bit Address ADMA2 + // is selected 0x3 Reserved +#define MMCHS_HCTL_DMAS_S 3 +#define MMCHS_HCTL_HSPE 0x00000004 // High Speed Enable: Before + // setting this bit the Host Driver + // shall check the High Speed + // Support in the Capabilities + // register. If this bit is set to 0 + // (default) the Host Controller + // outputs CMD line and DAT lines at + // the falling edge of the SD Clock. + // If this bit is set to 1 the Host + // Controller outputs CMD line and + // DAT lines at the rising edge of + // the SD Clock.This bit shall not + // be set when dual data rate mode + // is activated in MMCHS_CON[DDR]. 0 + // Normal speed mode 1 High speed + // mode +#define MMCHS_HCTL_DTW 0x00000002 // Data transfer width For MMC card + // this bit must be set following a + // valid SWITCH command (CMD6) with + // the correct value and extend CSD + // index written in the argument. + // Prior to this command the MMC + // card configuration register (CSD + // and EXT_CSD) must be verified for + // compliance with MMC standard + // specification 4.x (see section + // 3.6). This register has no effect + // when the MMC 8-bit mode is + // selected (register MMCHS_CON[DW8] + // set to1 ) For SD/SDIO cards this + // bit must be set following a valid + // SET_BUS_WIDTH command (ACMD6) + // with the value written in bit 1 + // of the argument. Prior to this + // command the SD card configuration + // register (SCR) must be verified + // for the supported bus width by + // the SD card. 0 1-bit Data width + // (DAT[0] used) 1 4-bit Data width + // (DAT[3:0] used) +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSCTL register. +// +//****************************************************************************** +#define MMCHS_SYSCTL_SRD 0x04000000 // Software reset for DAT line This + // bit is set to 1 for reset and + // released to 0 when completed. DAT + // finite state machine in both + // clock domain are also reset. Here + // below are the registers cleared + // by MMCHS_SYSCTL[SRD]: #VALUE! - + // MMCHS_PSTATE: BRE BWE RTA WTA DLA + // and DATI - MMCHS_HCTL: SBGR and + // CR - MMCHS_STAT: BRR BWR BGE and + // TC OCP and MMC buffer data + // management is reinitialized. 0 + // Reset completed 1 Software reset + // for DAT line +#define MMCHS_SYSCTL_SRC 0x02000000 // Software reset for CMD line This + // bit is set to 1 for reset and + // released to 0 when completed. CMD + // finite state machine in both + // clock domain are also reset. Here + // below the registers cleared by + // MMCHS_SYSCTL[SRC]: - + // MMCHS_PSTATE: CMDI - MMCHS_STAT: + // CC OCP and MMC command status + // management is reinitialized. 0 + // Reset completed 1 Software reset + // for CMD line +#define MMCHS_SYSCTL_SRA 0x01000000 // Software reset for all This bit + // is set to 1 for reset and + // released to 0 when completed. + // This reset affects the entire + // host controller except for the + // card detection circuit and + // capabilities registers. 0 Reset + // completed 1 Software reset for + // all the design +#define MMCHS_SYSCTL_DTO_M 0x000F0000 // Data timeout counter value and + // busy timeout. This value + // determines the interval by which + // DAT lines timeouts are detected. + // The host driver needs to set this + // bitfield based on - the maximum + // read access time (NAC) (Refer to + // the SD Specification Part1 + // Physical Layer) - the data read + // access time values (TAAC and + // NSAC) in the card specific data + // register (CSD) of the card - the + // timeout clock base frequency + // (MMCHS_CAPA[TCF]). If the card + // does not respond within the + // specified number of cycles a data + // timeout error occurs + // (MMCHS_STA[DTO]). The + // MMCHS_SYSCTL[DTO] register is + // also used to check busy duration + // to generate busy timeout for + // commands with busy response or + // for busy programming during a + // write command. Timeout on CRC + // status is generated if no CRC + // token is present after a block + // write. 0x0 TCF x 2^13 0x1 TCF x + // 2^14 0xE TCF x 2^27 0xF Reserved +#define MMCHS_SYSCTL_DTO_S 16 +#define MMCHS_SYSCTL_CLKD_M 0x0000FFC0 // Clock frequency select These + // bits define the ratio between a + // reference clock frequency (system + // dependant) and the output clock + // frequency on the CLK pin of + // either the memory card (MMC SD or + // SDIO). 0x000 Clock Ref bypass + // 0x001 Clock Ref bypass 0x002 + // Clock Ref / 2 0x003 Clock Ref / 3 + // 0x3FF Clock Ref / 1023 +#define MMCHS_SYSCTL_CLKD_S 6 +#define MMCHS_SYSCTL_CEN 0x00000004 // Clock enable This bit controls + // if the clock is provided to the + // card or not. 0 The clock is not + // provided to the card . Clock + // frequency can be changed . 1 The + // clock is provided to the card and + // can be automatically gated when + // MMCHS_SYSCONFIG[AUTOIDLE] is set + // to 1 (default value) . The host + // driver shall wait to set this bit + // to 1 until the Internal clock is + // stable (MMCHS_SYSCTL[ICS]). +#define MMCHS_SYSCTL_ICS 0x00000002 +#define MMCHS_SYSCTL_ICE 0x00000001 // Internal clock enable This + // register controls the internal + // clock activity. In very low power + // state the internal clock is + // stopped. Note: The activity of + // the debounce clock (used for + // wakeup events) and the OCP clock + // (used for reads and writes to the + // module register map) are not + // affected by this register. 0 The + // internal clock is stopped (very + // low power state). 1 The internal + // clock oscillates and can be + // automatically gated when + // MMCHS_SYSCONFIG[AUTOIDLE] is set + // to 1 (default value) . +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_STAT register. +// +//****************************************************************************** +#define MMCHS_STAT_BADA 0x20000000 +#define MMCHS_STAT_CERR 0x10000000 +#define MMCHS_STAT_ADMAE 0x02000000 +#define MMCHS_STAT_ACE 0x01000000 +#define MMCHS_STAT_DEB 0x00400000 +#define MMCHS_STAT_DCRC 0x00200000 +#define MMCHS_STAT_DTO 0x00100000 +#define MMCHS_STAT_CIE 0x00080000 +#define MMCHS_STAT_CEB 0x00040000 +#define MMCHS_STAT_CCRC 0x00020000 +#define MMCHS_STAT_CTO 0x00010000 +#define MMCHS_STAT_ERRI 0x00008000 +#define MMCHS_STAT_BSR 0x00000400 +#define MMCHS_STAT_OBI 0x00000200 +#define MMCHS_STAT_CIRQ 0x00000100 +#define MMCHS_STAT_CREM 0x00000080 +#define MMCHS_STAT_CINS 0x00000040 +#define MMCHS_STAT_BRR 0x00000020 +#define MMCHS_STAT_BWR 0x00000010 +#define MMCHS_STAT_DMA 0x00000008 +#define MMCHS_STAT_BGE 0x00000004 +#define MMCHS_STAT_TC 0x00000002 +#define MMCHS_STAT_CC 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_IE register. +// +//****************************************************************************** +#define MMCHS_IE_BADA_ENABLE 0x20000000 // Bad access to data space + // Interrupt Enable 0 Masked 1 + // Enabled +#define MMCHS_IE_CERR_ENABLE 0x10000000 // Card error interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_ADMAE_ENABLE 0x02000000 // ADMA error Interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_ACE_ENABLE 0x01000000 // Auto CMD12 error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DEB_ENABLE 0x00400000 // Data end bit error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DCRC_ENABLE 0x00200000 // Data CRC error Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_DTO_ENABLE 0x00100000 // Data timeout error Interrupt + // Enable 0 The data timeout + // detection is deactivated. The + // host controller provides the + // clock to the card until the card + // sends the data or the transfer is + // aborted. 1 The data timeout + // detection is enabled. +#define MMCHS_IE_CIE_ENABLE 0x00080000 // Command index error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CEB_ENABLE 0x00040000 // Command end bit error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CCRC_ENABLE 0x00020000 // Command CRC error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CTO_ENABLE 0x00010000 // Command timeout error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_NULL 0x00008000 // Fixed to 0 The host driver shall + // control error interrupts using + // the Error Interrupt Signal Enable + // register. Writes to this bit are + // ignored +#define MMCHS_IE_BSR_ENABLE 0x00000400 // Boot status interrupt Enable A + // write to this register when + // MMCHS_CON[BOOT_ACK] is set to 0x0 + // is ignored. 0 Masked 1 Enabled +#define MMCHS_IE_OBI_ENABLE 0x00000200 // Out-of-Band interrupt Enable A + // write to this register when + // MMCHS_CON[OBIE] is set to '0' is + // ignored. 0 Masked 1 Enabled +#define MMCHS_IE_CIRQ_ENABLE 0x00000100 // Card interrupt Enable A clear of + // this bit also clears the + // corresponding status bit. During + // 1-bit mode if the interrupt + // routine doesn't remove the source + // of a card interrupt in the SDIO + // card the status bit is reasserted + // when this bit is set to 1. 0 + // Masked 1 Enabled +#define MMCHS_IE_CREM_ENABLE 0x00000080 // Card removal Interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_CINS_ENABLE 0x00000040 // Card insertion Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_BRR_ENABLE 0x00000020 // Buffer Read Ready Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_BWR_ENABLE 0x00000010 // Buffer Write Ready Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DMA_ENABLE 0x00000008 // DMA interrupt Enable 0 Masked 1 + // Enabled +#define MMCHS_IE_BGE_ENABLE 0x00000004 // Block Gap Event Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_TC_ENABLE 0x00000002 // Transfer completed Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CC_ENABLE 0x00000001 // Command completed Interrupt + // Enable 0 Masked 1 Enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ISE register. +// +//****************************************************************************** +#define MMCHS_ISE_BADA_SIGEN 0x20000000 // Bad access to data space signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CERR_SIGEN 0x10000000 // Card error interrupt signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_ADMAE_SIGEN 0x02000000 // ADMA error signal status Enable + // 0 Masked 1 Enabled +#define MMCHS_ISE_ACE_SIGEN 0x01000000 // Auto CMD12 error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DEB_SIGEN 0x00400000 // Data end bit error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DCRC_SIGEN 0x00200000 // Data CRC error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DTO_SIGEN 0x00100000 // Data timeout error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CIE_SIGEN 0x00080000 // Command index error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CEB_SIGEN 0x00040000 // Command end bit error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CCRC_SIGEN 0x00020000 // Command CRC error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CTO_SIGEN 0x00010000 // Command timeout error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_NULL 0x00008000 // Fixed to 0 The host driver shall + // control error interrupts using + // the Error Interrupt Signal Enable + // register. Writes to this bit are + // ignored +#define MMCHS_ISE_BSR_SIGEN 0x00000400 // Boot status signal status + // EnableA write to this register + // when MMCHS_CON[BOOT_ACK] is set + // to 0x0 is ignored. 0 Masked 1 + // Enabled +#define MMCHS_ISE_OBI_SIGEN 0x00000200 // Out-Of-Band Interrupt signal + // status Enable A write to this + // register when MMCHS_CON[OBIE] is + // set to '0' is ignored. 0 Masked 1 + // Enabled +#define MMCHS_ISE_CIRQ_SIGEN 0x00000100 // Card interrupt signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CREM_SIGEN 0x00000080 // Card removal signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CINS_SIGEN 0x00000040 // Card insertion signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_BRR_SIGEN 0x00000020 // Buffer Read Ready signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_BWR_SIGEN 0x00000010 // Buffer Write Ready signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DMA_SIGEN 0x00000008 // DMA interrupt Signal status + // enable 0 Masked 1 Enabled +#define MMCHS_ISE_BGE_SIGEN 0x00000004 // Black Gap Event signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_TC_SIGEN 0x00000002 // Transfer completed signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CC_SIGEN 0x00000001 // Command completed signal status + // Enable 0 Masked 1 Enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_AC12 register. +// +//****************************************************************************** +#define MMCHS_AC12_CNI 0x00000080 +#define MMCHS_AC12_ACIE 0x00000010 +#define MMCHS_AC12_ACEB 0x00000008 +#define MMCHS_AC12_ACCE 0x00000004 +#define MMCHS_AC12_ACTO 0x00000002 +#define MMCHS_AC12_ACNE 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CAPA register. +// +//****************************************************************************** +#define MMCHS_CAPA_BIT64 0x10000000 +#define MMCHS_CAPA_VS18 0x04000000 +#define MMCHS_CAPA_VS30 0x02000000 +#define MMCHS_CAPA_VS33 0x01000000 +#define MMCHS_CAPA_SRS 0x00800000 +#define MMCHS_CAPA_DS 0x00400000 +#define MMCHS_CAPA_HSS 0x00200000 +#define MMCHS_CAPA_AD2S 0x00080000 +#define MMCHS_CAPA_MBL_M 0x00030000 +#define MMCHS_CAPA_MBL_S 16 +#define MMCHS_CAPA_BCF_M 0x00003F00 +#define MMCHS_CAPA_BCF_S 8 +#define MMCHS_CAPA_TCU 0x00000080 +#define MMCHS_CAPA_TCF_M 0x0000003F +#define MMCHS_CAPA_TCF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register. +// +//****************************************************************************** +#define MMCHS_CUR_CAPA_CUR_1V8_M \ + 0x00FF0000 + +#define MMCHS_CUR_CAPA_CUR_1V8_S 16 +#define MMCHS_CUR_CAPA_CUR_3V0_M \ + 0x0000FF00 + +#define MMCHS_CUR_CAPA_CUR_3V0_S 8 +#define MMCHS_CUR_CAPA_CUR_3V3_M \ + 0x000000FF + +#define MMCHS_CUR_CAPA_CUR_3V3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_FE register. +// +//****************************************************************************** +#define MMCHS_FE_FE_BADA 0x20000000 +#define MMCHS_FE_FE_CERR 0x10000000 +#define MMCHS_FE_FE_ADMAE 0x02000000 +#define MMCHS_FE_FE_ACE 0x01000000 +#define MMCHS_FE_FE_DEB 0x00400000 +#define MMCHS_FE_FE_DCRC 0x00200000 +#define MMCHS_FE_FE_DTO 0x00100000 +#define MMCHS_FE_FE_CIE 0x00080000 +#define MMCHS_FE_FE_CEB 0x00040000 +#define MMCHS_FE_FE_CCRC 0x00020000 +#define MMCHS_FE_FE_CTO 0x00010000 +#define MMCHS_FE_FE_CNI 0x00000080 +#define MMCHS_FE_FE_ACIE 0x00000010 +#define MMCHS_FE_FE_ACEB 0x00000008 +#define MMCHS_FE_FE_ACCE 0x00000004 +#define MMCHS_FE_FE_ACTO 0x00000002 +#define MMCHS_FE_FE_ACNE 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ADMAES register. +// +//****************************************************************************** +#define MMCHS_ADMAES_LME 0x00000004 // ADMA Length Mismatch Error: (1) + // While Block Count Enable being + // set the total data length + // specified by the Descriptor table + // is different from that specified + // by the Block Count and Block + // Length. (2) Total data length can + // not be divided by the block + // length. 0 No Error 1 Error +#define MMCHS_ADMAES_AES_M 0x00000003 // ADMA Error State his field + // indicates the state of ADMA when + // error is occurred during ADMA + // data transfer. "This field never + // indicates ""10"" because ADMA + // never stops in this state." 0x0 + // ST_STOP (Stop DMA)Contents of + // SYS_SDR register 0x1 ST_STOP + // (Stop DMA)Points the error + // descriptor 0x2 Never set this + // state(Not used) 0x3 ST_TFR + // (Transfer Data)Points the next of + // the error descriptor +#define MMCHS_ADMAES_AES_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ADMASAL register. +// +//****************************************************************************** +#define MMCHS_ADMASAL_ADMA_A32B_M \ + 0xFFFFFFFF // ADMA System address 32 bits.This + // register holds byte address of + // executing command of the + // Descriptor table. 32-bit Address + // Descriptor uses lower 32-bit of + // this register. At the start of + // ADMA the Host Driver shall set + // start address of the Descriptor + // table. The ADMA increments this + // register address which points to + // next line when every fetching a + // Descriptor line. When the ADMA + // Error Interrupt is generated this + // register shall hold valid + // Descriptor address depending on + // the ADMA state. The Host Driver + // shall program Descriptor Table on + // 32-bit boundary and set 32-bit + // boundary address to this + // register. ADMA2 ignores lower + // 2-bit of this register and + // assumes it to be 00b. + +#define MMCHS_ADMASAL_ADMA_A32B_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_REV register. +// +//****************************************************************************** +#define MMCHS_REV_VREV_M 0xFF000000 // Vendor Version Number: IP + // revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 +#define MMCHS_REV_VREV_S 24 +#define MMCHS_REV_SREV_M 0x00FF0000 +#define MMCHS_REV_SREV_S 16 +#define MMCHS_REV_SIS 0x00000001 // Slot Interrupt Status This + // status bit indicates the inverted + // state of interrupt signal for the + // module. By a power on reset or by + // setting a software reset for all + // (MMCHS_HCTL[SRA]) the interrupt + // signal shall be de-asserted and + // this status shall read 0. + + + +#endif // __HW_MMCHS_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_nvic.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_nvic.h new file mode 100755 index 00000000000..c8c0c88fa34 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_nvic.h @@ -0,0 +1,1708 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg + +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable +#define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable + +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable + +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable +#define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable + +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending + +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending +#define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending + +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending + +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending +#define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending + +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit + +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit +#define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit + +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority + +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority +#define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority +#define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority +#define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority +#define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority +#define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority +#define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority +#define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority +#define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority +#define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority +#define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority +#define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority +#define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority +#define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority +#define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority + + + +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable + +#undef NVIC_EN1_INT_M +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable + +#undef NVIC_DIS1_INT_M +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending + +#undef NVIC_PEND1_INT_M +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending + +#undef NVIC_UNPEND1_INT_M +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active + +#undef NVIC_ACTIVE1_INT_M +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor + +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor + +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number + +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number + +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number + +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number + +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset + +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset + +#define NVIC_VTABLE_OFFSET_S 9 + +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid + +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation + +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid + +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation + +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID + +#undef NVIC_SW_TRIG_INTID_M +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID + +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ocp_shared.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ocp_shared.h new file mode 100755 index 00000000000..670cad67103 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_ocp_shared.h @@ -0,0 +1,3443 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_OCP_SHARED_H__ +#define __HW_OCP_SHARED_H__ + +//***************************************************************************** +// +// The following are defines for the OCP_SHARED register offsets. +// +//***************************************************************************** +#define OCP_SHARED_O_SEMAPHORE1 0x00000000 +#define OCP_SHARED_O_SEMAPHORE2 0x00000004 +#define OCP_SHARED_O_SEMAPHORE3 0x00000008 +#define OCP_SHARED_O_SEMAPHORE4 0x0000000C +#define OCP_SHARED_O_SEMAPHORE5 0x00000010 +#define OCP_SHARED_O_SEMAPHORE6 0x00000014 +#define OCP_SHARED_O_SEMAPHORE7 0x00000018 +#define OCP_SHARED_O_SEMAPHORE8 0x0000001C +#define OCP_SHARED_O_SEMAPHORE9 0x00000020 +#define OCP_SHARED_O_SEMAPHORE10 \ + 0x00000024 + +#define OCP_SHARED_O_SEMAPHORE11 \ + 0x00000028 + +#define OCP_SHARED_O_SEMAPHORE12 \ + 0x0000002C + +#define OCP_SHARED_O_IC_LOCKER_ID \ + 0x00000030 + +#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \ + 0x00000034 + +#define OCP_SHARED_O_WL_SEMAPHORE_PEND \ + 0x00000038 + +#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \ + 0x0000003C + +#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \ + 0x00000040 + +#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \ + 0x00000044 + +#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \ + 0x00000048 + +#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \ + 0x0000004C + +#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \ + 0x00000050 + +#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \ + 0x00000054 + +#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \ + 0x00000058 + +#define OCP_SHARED_O_SSBD_SEED 0x0000005C +#define OCP_SHARED_O_SSBD_CHK 0x00000060 +#define OCP_SHARED_O_SSBD_POLY_SEL \ + 0x00000064 + +#define OCP_SHARED_O_SPARE_REG_0 \ + 0x00000068 + +#define OCP_SHARED_O_SPARE_REG_1 \ + 0x0000006C + +#define OCP_SHARED_O_SPARE_REG_2 \ + 0x00000070 + +#define OCP_SHARED_O_SPARE_REG_3 \ + 0x00000074 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \ + 0x000000A0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \ + 0x000000A4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \ + 0x000000A8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \ + 0x000000AC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \ + 0x000000B0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \ + 0x000000B4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \ + 0x000000B8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \ + 0x000000BC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \ + 0x000000C0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \ + 0x000000C4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \ + 0x000000C8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \ + 0x000000CC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \ + 0x000000D0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \ + 0x000000D4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \ + 0x000000D8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \ + 0x000000DC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \ + 0x000000E0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \ + 0x000000E4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \ + 0x000000E8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \ + 0x000000EC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \ + 0x000000F0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \ + 0x000000F4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \ + 0x000000F8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \ + 0x000000FC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \ + 0x00000100 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \ + 0x00000104 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \ + 0x00000108 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \ + 0x0000010C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \ + 0x00000110 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \ + 0x00000114 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \ + 0x00000118 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \ + 0x0000011C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \ + 0x00000120 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \ + 0x00000124 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \ + 0x00000128 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \ + 0x0000012C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \ + 0x00000130 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \ + 0x00000134 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \ + 0x00000138 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \ + 0x0000013C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \ + 0x00000140 + +#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \ + 0x00000144 // This register provide control to + // GPIO_CC3XXV1 IO PAD. Common + // control signals to all bottom Die + // IO's are controlled via this. + +#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \ + 0x00000148 + +#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \ + 0x0000014C + +#define OCP_SHARED_O_D2D_MISC_PAD_CONF \ + 0x00000150 + +#define OCP_SHARED_O_SOP_CONF_OVERRIDE \ + 0x00000154 + +#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \ + 0x00000158 + +#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \ + 0x0000015C + +#define OCP_SHARED_O_ALT_PC_VAL_NW \ + 0x00000160 + +#define OCP_SHARED_O_ALT_PC_VAL_APPS \ + 0x00000164 + +#define OCP_SHARED_O_SPARE_REG_4 \ + 0x00000168 + +#define OCP_SHARED_O_SPARE_REG_5 \ + 0x0000016C + +#define OCP_SHARED_O_SH_SPI_CS_MASK \ + 0x00000170 + +#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \ + 0x00000174 + +#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \ + 0x00000178 + +#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \ + 0x0000017C + +#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \ + 0x00000180 + +#define OCP_SHARED_O_CC3XX_DEV_PADCONF \ + 0x00000184 + +#define OCP_SHARED_O_SPARE_REG_8 \ + 0x00000188 + +#define OCP_SHARED_O_SPARE_REG_6 \ + 0x0000018C + +#define OCP_SHARED_O_SPARE_REG_7 \ + 0x00000190 + +#define OCP_SHARED_O_APPS_WLAN_ORBIT \ + 0x00000194 + +#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \ + 0x00000198 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE1 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE2 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE3 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE4 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE5 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE6 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE7 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE8 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE9 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE10 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE11 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE12 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_IC_LOCKER_ID register. +// +//****************************************************************************** +#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \ + 0x00000007 // This register is used for + // allowing only one master OCP to + // perform write transactions to the + // OCP slaves. Each bit represents + // an IP in the following format: { + // JTAG,WLAN, NWP mcu}. As any of + // the bits is set to one, the + // correlating IP is preventing the + // other IP's from performing write + // transactions to the slaves. As + // the Inter Connect is locked, the + // only the locking IP can write to + // the register and by that + // releasing the lock. 3'b000 => IC + // is not locked. 3'b001 => IC is + // locked by NWP mcu. 3'b010 => IC + // is locked by WLAN. 3'b100 => IC + // is locked by JTAG. + +#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_MCU_SEMAPHORE_PEND register. +// +//****************************************************************************** +#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \ + 0x0000FFFF // This register specifies the + // semaphore for which the NWP mcu + // is waiting to be released. It is + // set to the serial number of a + // given locked semaphore after it + // was read by the NWP mcu. Only + // [11:0] is used. + +#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_WL_SEMAPHORE_PEND register. +// +//****************************************************************************** +#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \ + 0x0000FFFF // This register specifies the + // semaphore for which the WLAN is + // waiting to be released. It is set + // to the serial number of a given + // locked semaphore after it was + // read by the WLAN. Only [11:0] is + // used. + +#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register. +// +//****************************************************************************** +#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \ + 0x0000FFFF // This information serves the IPs + // for knowing in which platform are + // they integrated at: 0 = CC31XX. + +#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \ + 0x00000FFF // Captured/released semaphores + // status for the 12 semaphores. + // Each bit of the 12 bits + // represents a semaphore. 0 => + // Semaphore Free. 1 => Semaphore + // Captured. + +#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_CONFIG_CTRL register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \ + 0x00000010 // This bit is used to enable + // timeout mechanism for top_ocp_ic + // (for debug puropse). When 1 value + // , in case any ocp slave doesn't + // give sresponse within 16 cylcles + // top_ic will give error response + // itself to avoid bus hange. + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \ + 0x00000008 // 1 bit should be accessible only + // in devinit. This will enable 0x4 + // hack for apps processor + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \ + 0x00000004 // 1 bit, should be accessible only + // in devinit. This will enable 0x4 + // hack for nw processor + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \ + 0x00000002 // When set NW can take over apps + // rom and flash via IDCODE bus. + // Apps will able to access this + // register only during devinit and + // reset value should be 0. + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \ + 0x00000001 // When this bit is set to 0 WPSI + // host interface wil be selected, + // when this bit is set to 1 , WLAN + // host async bridge will be + // selected. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \ + 0x3FFFFFFF // This register provides memss RAM + // column configuration for column 0 + // to 9. 3 bits are allocated per + // column. This register is required + // to be configured before starting + // RAM access. Changing register + // setting while code is running + // will result into unpredictable + // memory behaviour. Register is + // supported to configured ones + // after core is booted up. 3 bit + // encoding per column is as + // follows: when 000 : WLAN, 001: + // NWP, 010: APPS, 011: PHY, 100: + // OCLA column 0 select: bit [2:0] + // :when 000 -> WLAN,001 -> NWP,010 + // -> APPS, 011 -> PHY, 100 -> OCLA + // column 1 select: bit [5:3] + // :column 2 select: bit [8 : 6]: + // column 3 select : bit [11: 9] + // column 4 select : bit [14:12] + // column 5 select : bit [17:15] + // column 6 select : bit [20:18] + // column 7 select : bit [23:21] + // column 8 select : bit [26:24] + // column 9 select : bit [29:27] + // column 10 select + +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \ + 0x00000FFF // This register provides memss RAM + // column configuration for column + // 10 to 15. 3 bits are allocated + // per column. This register is + // required to be configured before + // starting RAM access. Changing + // register setting while code is + // running will result into + // unpredictable memory behaviour. + // Register is supported to + // configured ones after core is + // booted up. 3 bit encoding per + // column is as follows: when 000 : + // WLAN, 001: NWP, 010: APPS, 011: + // PHY, 100: OCLA column 11 select : + // bit [2:0] column 12 select : bit + // [5:3] column 13 select : bit [8 : + // 6] column 14 select : + +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_WLAN_ELP_WAKE_EN register. +// +//****************************************************************************** +#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \ + 0x00000001 // when '1' : signal will enabled + // ELP power doamin when '0': ELP is + // not powered up. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register. +// +//****************************************************************************** +#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. This register is not used + // , similar register availble in + // GPRCM space. + +#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register. +// +//****************************************************************************** +#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_SEED register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_CHK register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_POLY_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \ + 0x00000003 // 2 bit, Writable only during + // devinit, and whole 2 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_0 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \ + 0xFFFFFFFF // Devinit code should look for + // whether corresponding fuse is + // blown and if blown write to the + // 11th bit of this register to + // disable flshtst interface + +#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_1 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_2 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_3 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \ + 0xFFFFFFFF // APPS Software register + +#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." "For example in + // case of I2C Value gets latched at + // rising edge of RET33.""" """ 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \ + 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." "For example in + // case of I2C Value gets latched at + // rising edge of RET33.""" """ 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \ + 0x00000080 // when '1' enable ISO A control to + // D2D Pads else ISO is disabled. + // For these PADS to be functional + // this signals should be set 0. + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \ + 0x00000040 // when '1' enable ISO Y control to + // D2D Pads else ISO is disabled. + // For these PADS to be functional + // this signals should be set 0. + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \ + 0x00000020 // If level ‘1’ enables the PAD to + // ODI path for JTAG PADS [PAD 23, + // 24, 28, 29]. Else ODI is pulled + // ‘Low’ regardless of PAD level." + // "Value gets latched at rising + // edge of RET33.""" """ + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \ + 0x00000018 // 00’: hysteriris = 10% of VDDS + // (difference between upper and + // lower threshold of the schmit + // trigger) ‘01’: hysteriris = 20% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger) ‘10’: hysteriris = 30% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger) ‘11’: hysteriris = 40% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger)" """ + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3 +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \ + 0x00000004 // If logic ‘0’ there is no + // hysteresis. Set to ‘1’ to enable + // hysteresis. Leave the choice to + // customers""" + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \ + 0x00000002 // Normal functional operation set + // this to logic ‘1’ to increase the + // speed of the o/p buffer at the + // cost of 0.2uA static current + // consumption per IO. During IDDQ + // test and during Hibernate this + // would be forced to logic ‘0’. + // Value is not latched at rising + // edge of RET33."" + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \ + 0x00000001 // If level ‘1’ enables the PAD to + // ODI path. Else ODI is pulled + // ‘Low’ regardless of PAD level." + // "Value gets latched at rising + // edge of RET33.""" """ + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \ + 0x0000003F // this register implements common + // IO control to all devement mode + // PADs; these PADs are DEV_PAD33 to + // DEV_PAD39. Bit [1:0] : Drive + // strength control. These 2 bits + // are connected to DEV PAD drive + // strength control. possible drive + // stregnths are 2MA, 4MA and 6 MA + // for the these IO's. bit 0: when + // set to logic value '1' enable 2MA + // drive strength for DEVPAD01 to 07 + // bit 1: when set to logic value + // '1' enable 4MA drive strength for + // DEVPAD01 to 07. bit[3:2] : WK + // PULL UP and PULL down control. + // These 2 bits provide IWKPUEN and + // IWKPDEN control for all DEV IO's. + // bit 2: when set to logic value + // '1' enable WKPU to DEVPAD01 to 07 + // bit 3: when set to logic value + // '1' enable WKPD to DEVPAD01 to + // 07. bit 4: WK PULL control for + // DEV_PKG_DETECT pin. when '1' + // pullup enabled else it is + // disable. bit 5: when set to logic + // value '1' enable 8MA drive + // strength for DEVPAD01 to 07. + +#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \ + 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + // this register control OEN2X pin + // of D2D TOSTACK PAD: OEN1X and + // OEN2X decoding is as follows: + // "when ""00"" :" "when ""01"" : + // dirve strength is '1' and output + // buffer enabled." "when ""10"" : + // drive strength is 2 and output + // buffer is disabled." "when ""11"" + // : dirve strength is '3' and + // output buffer enabled." + +#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_MISC_PAD_CONF register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \ + 0x00000200 // This register provide OEN2X + // control to D2D PADS OEN/OEN2X + // control. When 0 : Act as input + // buffer else output buffer with + // drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \ + 0x00000100 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \ + 0x00000080 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \ + 0x00000040 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \ + 0x00000020 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \ + 0x00000010 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \ + 0x00000008 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \ + 0x00000007 // D2D SPARE PAD OEN/OEN2X control. + // When 0: Act as input buffer else + // output buffer with drive strength + // 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SOP_CONF_OVERRIDE register. +// +//****************************************************************************** +#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \ + 0x00000001 // when '1' : signal will ovberride + // SoP setting of JTAG PADS. when + // '0': SoP setting will control + // JTAG PADs [ TDI, TDO, TMS, TCK] + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \ + 0x00000020 // This register contains debug + // subsystem status bits From APPS + // MCU status bit to indicates + // whether serial wire or 4 pins + // jtag select. + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \ + 0x00000010 // cjtag bypass bit select + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \ + 0x00000008 // serial wire interface bit select + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \ + 0x00000004 // apps tap enable status + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \ + 0x00000002 // tap enable status + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \ + 0x00000001 // ssbd unlock status + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \ + 0x0000FFFF // debug mux select register. Upper + // 8 bits are used for debug module + // selection. Lower 8 bit [7:0] used + // inside debug module for selecting + // module specific signals. + // Bits[15:8: when set x"00" : GPRCM + // debug bus. When "o1" : SDIO debug + // debug bus when x"02" : + // autonoumous SPI when x"03" : + // TOPIC when x"04": memss when + // x"25": mcu debug bus : APPS debug + // when x"45": mcu debug bus : NWP + // debug when x"65": mcu debug bus : + // AHB2VBUS debug when x"85": mcu + // debug bus : VBUS2HAB debug when + // x"95": mcu debug bus : RCM debug + // when x"A5": mcu debug bus : + // crypto debug when x"06": WLAN + // debug bus when x"07": debugss bus + // when x"08": ADC debug when x"09": + // SDIO PHY debug bus then "others" + // : no debug is selected + +#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_ALT_PC_VAL_NW register. +// +//****************************************************************************** +#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \ + 0xFFFFFFFF // 32 bit. Program counter value + // for 0x4 address when Alt_pc_en_nw + // is set. + +#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_ALT_PC_VAL_APPS register. +// +//****************************************************************************** +#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \ + 0xFFFFFFFF // 32 bit. Program counter value + // for 0x4 address when + // Alt_pc_en_apps is set + +#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_4 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \ + 0xFFFFFFFE // HW register + +#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1 +#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \ + 0x00000001 // Data to the top die launched at + // negative edge instead of positive + // edge. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_5 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \ + 0xFFFFFFFF // HW register + +#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SH_SPI_CS_MASK register. +// +//****************************************************************************** +#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \ + 0x0000000F // ( chip select 0 is unmasked + // after reset. When ‘1’ : CS is + // unmasked or else masked. Valid + // configurations are 1000, 0100, + // 0010 or 0001. Any other setting + // can lead to unpredictable + // behavior. + +#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEVICE_TYPE register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \ + 0x00000060 // reserved bits tied off "00". + +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5 +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \ + 0x0000001F // CC3XX Device type information. + +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register. +// +//****************************************************************************** +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \ + 0x000000F0 // [4] 1: switch between + // WLAN_I2C_SCL and + // TOP_GPIO_PORT4_I2C closes 0: + // switch opens [5] 1: switch + // between WLAN_I2C_SCL and + // TOP_VSENSE_PORT closes 0: switch + // opens [6] 1: switch between + // WLAN_I2C_SCL and WLAN_ANA_TP4 + // closes 0: switch opens [7] + // Reserved + +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4 +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \ + 0x0000000F // [0] 1: switch between + // WLAN_I2C_SDA and + // TOP_GPIO_PORT3_I2C closes 0: + // switch opens [1] 1: switch + // between WLAN_I2C_SDA and + // TOP_IFORCE_PORT closes 0: switch + // opens [2] 1: switch between + // WLAN_I2C_SDA and WLAN_ANA_TP3 + // closes 0: switch opens [3] + // Reserved + +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \ + 0x00000001 // when '0' indicates package type + // is development. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_AUTONMS_SPICLK_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \ + 0x00000002 // This bit is used to bypass MCPSI + // autonomous mode .if this bit is 1 + // autonomous MCSPI logic will be + // bypassed and it will act as link + // SPI + +#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \ + 0x00000001 // This bit is used in SPI + // Autonomous mode to switch clock + // from system clock to SPI clk that + // is coming from PAD. When value 1 + // PAD SPI clk is used as system + // clock in LPDS mode by SPI as well + // as autonomous wrapper logic. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEV_PADCONF register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \ + 0x0000FFFF + +#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_IDMEM_TIM_UPDATE register. +// +//****************************************************************************** +#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \ + 0xFFFFFFFF + +#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_6 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_7 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_APPS_WLAN_ORBIT register. +// +//****************************************************************************** +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \ + 0xFFFFFC00 // Spare bit + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10 +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \ + 0x00000200 // A rising edge on this bit + // indicates that the test case + // passes. This bit would be brought + // out on the pin interface during + // ORBIT. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \ + 0x00000100 // This register bit is writable by + // the FW and when set to 1 it + // indicates the start of a test + // execution. A failing edge on this + // bit indicates that the test + // execution is complete. This bit + // would be brought out on the pin + // interface during ORBIT. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \ + 0x000000FC // Implies the test case ID that + // needs to run. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2 +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \ + 0x00000002 // This bit is used to trigger the + // execution of test cases within + // the (ROM based) IP. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \ + 0x00000001 // When this bit is 1 it implies + // ORBIT mode of operation and the + // (ROM based) IP start the + // execution from a test case + // perspective + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register. +// +//****************************************************************************** +#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \ + 0xFFFFFFFF // scratch pad register. + +#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0 + + + +#endif // __HW_OCP_SHARED_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_shamd5.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_shamd5.h new file mode 100755 index 00000000000..aaee0ef4bde --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_shamd5.h @@ -0,0 +1,1240 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_SHAMD5_H__ +#define __HW_SHAMD5_H__ + +//***************************************************************************** +// +// The following are defines for the SHAMD5_P register offsets. +// +//***************************************************************************** +#define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for + // MD5 [159:128] for SHA-1 [255:224] + // for SHA-2 / HMAC Key [31:0] for + // HMAC key proc READ: Outer Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 +#define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for + // MD5 [127:96] for SHA-1 [223:192] + // for SHA-2 / HMAC Key [63:32] for + // HMAC key proc READ: Outer Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 +#define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for + // MD5 [95:64] for SHA-1 [191:160] + // for SHA-2 / HMAC Key [95:64] for + // HMAC key proc READ: Outer Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA-2 +#define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for + // MD5 [63:31] for SHA-1 [159:128] + // for SHA-2 / HMAC Key [127:96] for + // HMAC key proc READ: Outer Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 +#define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for + // SHA-1 [127:96] for SHA-2 / HMAC + // Key [159:128] for HMAC key proc + // READ: Outer Digest [31:0] for + // SHA-1 [127:96] for SHA-2 +#define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for + // SHA-2 / HMAC Key [191:160] for + // HMAC key proc READ: Outer Digest + // [95:64] for SHA-2 +#define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for + // SHA-2 / HMAC Key [223:192] for + // HMAC key proc READ: Outer Digest + // [63:32] for SHA-2 +#define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for + // SHA-2 / HMAC Key [255:224] for + // HMAC key proc READ: Outer Digest + // [31:0] for SHA-2 +#define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 / HMAC + // Key [287:256] for HMAC key proc + // READ: Intermediate / Inner Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 / + // Result Digest/MAC [127:96] for + // MD5 [159:128] for SHA-1 [223:192] + // for SHA-2 224 [255:224] for SHA-2 + // 256 +#define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 / HMAC + // Key [319:288] for HMAC key proc + // READ: Intermediate / Inner Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 / + // Result Digest/MAC [95:64] for MD5 + // [127:96] for SHA-1 [191:160] for + // SHA-2 224 [223:192] for SHA-2 256 +#define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA- 2 / HMAC Key + // [351:320] for HMAC key proc READ: + // Intermediate / Inner Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA-2 / Result + // Digest/MAC [63:32] for MD5 + // [95:64] for SHA-1 [159:128] for + // SHA-2 224 [191:160] for SHA-2 256 +#define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 / HMAC Key + // [383:352] for HMAC key proc READ: + // Intermediate / Inner Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 / Result + // Digest/MAC [31:0] for MD5 [63:32] + // for SHA-1 [127:96] for SHA-2 224 + // [159:128] for SHA-2 256 +#define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest + // [31:0] for SHA-1 [127:96] for + // SHA-2 / HMAC Key [415:384] for + // HMAC key proc READ: Intermediate + // / Inner Digest [31:0] for SHA-1 + // [127:96] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-1 + // [95:64] for SHA-2 224 [127:96] + // for SHA-2 256 +#define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest + // [95:64] for SHA-2 / HMAC Key + // [447:416] for HMAC key proc READ: + // Intermediate / Inner Digest + // [95:64] for SHA-2 / Result + // Digest/MAC [63:32] for SHA-2 224 + // [95:64] for SHA-2 256 +#define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest + // [63:32] for SHA-2 / HMAC Key + // [479:448] for HMAC key proc READ: + // Intermediate / Inner Digest + // [63:32] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-2 224 + // [63:32] for SHA-2 256 +#define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest + // [31:0] for SHA-2 / HMAC Key + // [511:480] for HMAC key proc READ: + // Intermediate / Inner Digest + // [31:0] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-2 256 +#define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count + // ([31:6] only [5:0] assumed 0) + // READ: Result / IntermediateDigest + // Count The initial digest byte + // count for hash/HMAC continue + // operations (HMAC Key Processing = + // 0 and Use Algorithm Constants = + // 0) on the Secure World must be + // written to this register prior to + // starting the operation by writing + // to S_HASH_MODE. When either HMAC + // Key Processing is 1 or Use + // Algorithm Constants is 1 this + // register does not need to be + // written it will be overwritten + // with 64 (1 hash block of key XOR + // ipad) or 0 respectively + // automatically. When starting a + // HMAC operation from pre-computes + // (HMAC Key Processing is 0) then + // the value 64 must be written here + // to compensate for the appended + // key XOR ipad block. Note that the + // value written should always be a + // 64 byte multiple the lower 6 bits + // written are ignored. The updated + // digest byte count (initial digest + // byte count + bytes processed) can + // be read from this register when + // the status register indicates + // that the operation is done or + // suspended due to a context switch + // request or when a Secure World + // context out DMA is requested. In + // Advanced DMA mode when not + // suspended with a partial result + // reading the SHAMD5_DIGEST_COUNT + // register triggers the Hash/HMAC + // Engine to start the next context + // input DMA. Therefore reading the + // SHAMD5_DIGEST_COUNT register + // should always be the last + // context-read action if not + // suspended with a partial result + // (i.e. PartHashReady interrupt not + // pending). +#define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE +#define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining + // Byte Count (bytes) READ: + // Remaining Byte Count. The value + // programmed MUST be a 64-byte + // multiple if Close Hash is set to + // 0. This register is also the + // trigger to start processing: once + // this register is written the core + // will commence requesting input + // data via DMA or IRQ (if + // programmed length > 0) and start + // processing. The remaining byte + // count for the active operation + // can be read from this register + // when the interrupt status + // register indicates that the + // operation is suspended due to a + // context switch request. +#define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0 +#define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1 +#define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2 +#define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3 +#define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4 +#define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5 +#define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6 +#define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7 +#define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8 +#define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9 +#define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10 +#define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11 +#define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12 +#define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13 +#define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14 +#define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15 +#define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV +#define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG +#define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS +#define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS +#define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The + // SHAMD5_IRQENABLE register contains + // an enable bit for each unique + // interrupt for the public side. An + // interrupt is enabled when both + // the global enable in + // SHAMD5_SYSCONFIG (PIT_en) and the + // bit in this register are both set + // to 1. An interrupt that is + // enabled is propagated to the + // SINTREQUEST_P output. Please note + // that the dedicated partial hash + // output (SINTREQUEST_PART_P) is + // not affected by this register it + // is only affected by the global + // enable SHAMD5_SYSCONFIG (PIT_en). +#define SHAMD5_O_HASH512_ODIGEST_A \ + 0x00000200 + +#define SHAMD5_O_HASH512_ODIGEST_B \ + 0x00000204 + +#define SHAMD5_O_HASH512_ODIGEST_C \ + 0x00000208 + +#define SHAMD5_O_HASH512_ODIGEST_D \ + 0x0000020C + +#define SHAMD5_O_HASH512_ODIGEST_E \ + 0x00000210 + +#define SHAMD5_O_HASH512_ODIGEST_F \ + 0x00000214 + +#define SHAMD5_O_HASH512_ODIGEST_G \ + 0x00000218 + +#define SHAMD5_O_HASH512_ODIGEST_H \ + 0x0000021C + +#define SHAMD5_O_HASH512_ODIGEST_I \ + 0x00000220 + +#define SHAMD5_O_HASH512_ODIGEST_J \ + 0x00000224 + +#define SHAMD5_O_HASH512_ODIGEST_K \ + 0x00000228 + +#define SHAMD5_O_HASH512_ODIGEST_L \ + 0x0000022C + +#define SHAMD5_O_HASH512_ODIGEST_M \ + 0x00000230 + +#define SHAMD5_O_HASH512_ODIGEST_N \ + 0x00000234 + +#define SHAMD5_O_HASH512_ODIGEST_O \ + 0x00000238 + +#define SHAMD5_O_HASH512_ODIGEST_P \ + 0x0000023C + +#define SHAMD5_O_HASH512_IDIGEST_A \ + 0x00000240 + +#define SHAMD5_O_HASH512_IDIGEST_B \ + 0x00000244 + +#define SHAMD5_O_HASH512_IDIGEST_C \ + 0x00000248 + +#define SHAMD5_O_HASH512_IDIGEST_D \ + 0x0000024C + +#define SHAMD5_O_HASH512_IDIGEST_E \ + 0x00000250 + +#define SHAMD5_O_HASH512_IDIGEST_F \ + 0x00000254 + +#define SHAMD5_O_HASH512_IDIGEST_G \ + 0x00000258 + +#define SHAMD5_O_HASH512_IDIGEST_H \ + 0x0000025C + +#define SHAMD5_O_HASH512_IDIGEST_I \ + 0x00000260 + +#define SHAMD5_O_HASH512_IDIGEST_J \ + 0x00000264 + +#define SHAMD5_O_HASH512_IDIGEST_K \ + 0x00000268 + +#define SHAMD5_O_HASH512_IDIGEST_L \ + 0x0000026C + +#define SHAMD5_O_HASH512_IDIGEST_M \ + 0x00000270 + +#define SHAMD5_O_HASH512_IDIGEST_N \ + 0x00000274 + +#define SHAMD5_O_HASH512_IDIGEST_O \ + 0x00000278 + +#define SHAMD5_O_HASH512_IDIGEST_P \ + 0x0000027C + +#define SHAMD5_O_HASH512_DIGEST_COUNT \ + 0x00000280 + +#define SHAMD5_O_HASH512_MODE 0x00000284 +#define SHAMD5_O_HASH512_LENGTH 0x00000288 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_DIGEST_COUNT register. +// +//****************************************************************************** +#define SHAMD5_DIGEST_COUNT_DATA_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DIGEST_COUNT_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_MODE register. +// +//****************************************************************************** +#define SHAMD5_MODE_HMAC_OUTER_HASH \ + 0x00000080 // The HMAC Outer Hash is performed + // on the hash digest when the inner + // hash hash finished (block length + // exhausted and final hash + // performed if close_hash is 1). + // This bit should normally be set + // together with close_hash to + // finish the inner hash first or + // Block Length should be zero (HMAC + // continue with the just outer hash + // to be done). Auto cleared + // internally when outer hash + // performed. 0 No operation 1 hmac + // processing + +#define SHAMD5_MODE_HMAC_KEY_PROC \ + 0x00000020 // Performs HMAC key processing on + // the 512 bit HMAC key loaded into + // the SHAMD5_IDIGEST_{A to H} and + // SHAMD5_ODIGEST_{A to H} register + // block. Once HMAC key processing + // is finished this bit is + // automatically cleared and the + // resulting Inner and Outer digest + // is available from + // SHAMD5_IDIGEST_{A to H} and + // SHAMD5_ODIGEST_{A to H} + // respectively after which regular + // hash processing (using + // SHAMD5_IDIGEST_{A to H} as initial + // digest) will commence until the + // Block Length is exhausted. 0 No + // operation. 1 Hmac processing. + +#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the + // hash/HMAC will be 'closed' at the + // end of the block as per + // MD5/SHA-1/SHA-2 specification + // (i.e. appropriate padding is + // added) or no padding is done + // allowing the hash to be continued + // later. However if the hash/HMAC + // is not closed then the Block + // Length MUST be a multiple of 64 + // bytes to ensure correct + // operation. Auto cleared + // internally when hash closed. 0 No + // padding hash computation can be + // contimued. 1 Last packet will be + // padded. +#define SHAMD5_MODE_ALGO_CONSTANT \ + 0x00000008 // The initial digest register will + // be overwritten with the algorithm + // constants for the selected + // algorithm when hashing and the + // initial digest count register + // will be reset to 0. This will + // start a normal hash operation. + // When continuing an existing hash + // or when performing an HMAC + // operation this register must be + // set to 0 and the + // intermediate/inner digest or HMAC + // key and digest count need to be + // written to the context input + // registers prior to writing + // SHAMD5_MODE. Auto cleared + // internally after first block + // processed. 0 Use pre-calculated + // digest (from an other operation) + // 1 Use constants of the selected + // algo. + +#define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash + // algorithm to be used for + // processing: 0x0 md5_128 algorithm + // 0x1 sha1_160 algorithm 0x2 + // sha2_224 algorithm 0x3 sha2_256 + // algorithm +#define SHAMD5_MODE_ALGO_S 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_LENGTH register. +// +//****************************************************************************** +#define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data +#define SHAMD5_LENGTH_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA0_IN_DATA0_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA0_IN_DATA0_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA1_IN_DATA1_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA1_IN_DATA1_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA2_IN_DATA2_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA2_IN_DATA2_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA3_IN_DATA3_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA3_IN_DATA3_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA4_IN_DATA4_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA4_IN_DATA4_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA5_IN_DATA5_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA5_IN_DATA5_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA6_IN_DATA6_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA6_IN_DATA6_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA7_IN_DATA7_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA7_IN_DATA7_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA8_IN_DATA8_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA8_IN_DATA8_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA9_IN_DATA9_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA9_IN_DATA9_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA10_IN_DATA10_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA10_IN_DATA10_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA11_IN_DATA11_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA11_IN_DATA11_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA12_IN_DATA12_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA12_IN_DATA12_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA13_IN_DATA13_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA13_IN_DATA13_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA14_IN_DATA14_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA14_IN_DATA14_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA15_IN_DATA15_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA15_IN_DATA15_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_REVISION register. +// +//****************************************************************************** +#define SHAMD5_REVISION_SCHEME_M 0xC0000000 +#define SHAMD5_REVISION_SCHEME_S 30 +#define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define SHAMD5_REVISION_FUNC_S 16 +#define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define SHAMD5_REVISION_R_RTL_S 11 +#define SHAMD5_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. + +#define SHAMD5_REVISION_X_MAJOR_S 8 +#define SHAMD5_REVISION_CUSTOM_M 0x000000C0 +#define SHAMD5_REVISION_CUSTOM_S 6 +#define SHAMD5_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. + +#define SHAMD5_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register. +// +//****************************************************************************** +#define SHAMD5_SYSCONFIG_PADVANCED \ + 0x00000080 // If set to 1 Advanced mode is + // enabled for the Secure World. If + // set to 0 Legacy mode is enabled + // for the Secure World. + +#define SHAMD5_SYSCONFIG_PCONT_SWT \ + 0x00000040 // Finish all pending data and + // context DMA input requests (but + // will not assert any new requests) + // finish processing all data in the + // module and provide a saved + // context (partial hash result + // updated digest count remaining + // length updated mode information + // where applicable) for the last + // operation that was interrupted so + // that it can be resumed later. + +#define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008 +#define SHAMD5_SYSCONFIG_PIT_EN 0x00000004 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register. +// +//****************************************************************************** +#define SHAMD5_SYSSTATUS_RESETDONE \ + 0x00000001 // data + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register. +// +//****************************************************************************** +#define SHAMD5_IRQSTATUS_CONTEXT_READY \ + 0x00000008 // indicates that the secure side + // context input registers are + // available for a new context for + // the next packet to be processed. + +#define SHAMD5_IRQSTATUS_PARTHASH_READY \ + 0x00000004 // After a secure side context + // switch request this bit will read + // as 1 indicating that the saved + // context is available from the + // secure side context output + // registers. Note that if the + // context switch request coincides + // with a final hash (when hashing) + // or an outer hash (when doing + // HMAC) that PartHashReady will not + // become active but a regular + // Output Ready will occur instead + // (indicating that the result is + // final and therefore no + // continuation is required). + +#define SHAMD5_IRQSTATUS_INPUT_READY \ + 0x00000002 // indicates that the secure side + // data FIFO is ready to receive the + // next 64 byte data block. + +#define SHAMD5_IRQSTATUS_OUTPUT_READY \ + 0x00000001 // Indicates that a (partial) + // result or saved context is + // available from the secure side + // context output registers. + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register. +// +//****************************************************************************** +#define SHAMD5_IRQENABLE_M_CONTEXT_READY \ + 0x00000008 // mask for context ready + +#define SHAMD5_IRQENABLE_M_PARTHASH_READY \ + 0x00000004 // mask for partial hash + +#define SHAMD5_IRQENABLE_M_INPUT_READY \ + 0x00000002 // mask for input_ready + +#define SHAMD5_IRQENABLE_M_OUTPUT_READY \ + 0x00000001 // mask for output_ready + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_A_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_B_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_C_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_D_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_E_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_F_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_G_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_H_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_I register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_I_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_I_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_J register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_J_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_J_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_K register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_K_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_K_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_L register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_L_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_L_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_M register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_M_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_M_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_N register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_N_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_N_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_O register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_O_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_O_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_P register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_A_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_B_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_C_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_D_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_E_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_F_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_G_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_H_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_I register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_I_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_I_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_J register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_J_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_J_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_K register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_K_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_K_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_L register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_L_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_L_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_M register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_M_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_M_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_N register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_N_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_N_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_O register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_O_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_O_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_P register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_DIGEST_COUNT register. +// +//****************************************************************************** +#define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_MODE register. +// +//****************************************************************************** +#define SHAMD5_HASH512_MODE_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_MODE_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_LENGTH register. +// +//****************************************************************************** +#define SHAMD5_HASH512_LENGTH_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_LENGTH_DATA_S 0 + + + +#endif // __HW_SHAMD5_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h new file mode 100755 index 00000000000..d406163277c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h @@ -0,0 +1,762 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __HW_STACK_DIE_CTRL_H__ +#define __HW_STACK_DIE_CTRL_H__ + +//***************************************************************************** +// +// The following are defines for the STACK_DIE_CTRL register offsets. +// +//***************************************************************************** +#define STACK_DIE_CTRL_O_STK_UP_RESET \ + 0x00000000 // Can be written only by Base + // Processor. Writing to this + // register will reset the stack + // processor reset will be + // de-asserted upon clearing this + // register. + +#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \ + 0x00000004 // This register defines who among + // base processor and stack + // processor have highest priority + // for Sram Access. Can be written + // only by Base Processor. + +#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \ + 0x00000008 // In Spinlock mode this Register + // defines who among base processor + // and stack processor have access + // to Sram Bank2 right now. In + // Handshake mode this Register + // defines who among base processor + // and stack processor have access + // to Sram Bank2 and Bank3 right + // now. Its Clear only register and + // is set by hardware. Lower bit can + // be cleared only by Base Processor + // and Upper bit Cleared only by the + // Stack processor. + +#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \ + 0x0000000C // In Spinlock mode whenever Base + // processor wants the access to + // Sram Bank2 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by Stack + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \ + 0x00000010 // In Spinlock mode Whenever Stack + // processor wants the access to + // Sram Bank2 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by the Base + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \ + 0x00000014 // Register defines who among base + // processor and stack processor + // have access to Sram Bank3 right + // now. Its Clear only register and + // is set by hardware. Lower bit can + // be cleared only by Base Processor + // and Upper bit Cleared only by the + // Stack processor. + +#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \ + 0x00000018 // In Spinlock mode whenever Base + // processor wants the access to + // Sram Bank3 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by Stack + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \ + 0x0000001C // In Spinlock mode Whenever Stack + // processor wants the access to + // Sram Bank3 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by the Base + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \ + 0x00000020 // Read State Machine timing + // configuration register. Generally + // Bit 4 and 3 will be identical. + // For stacked die always 43 are 0 + // and 6:5 == 1 for 120Mhz. + +#define STACK_DIE_CTRL_O_RDSM_CFG_EE \ + 0x00000024 // Read State Machine timing + // configuration register. Generally + // Bit 4 and 3 will be identical. + // For stacked die always 43 are 0 + // and 6:5 == 1 for 120Mhz. + +#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \ + 0x00000028 // Reading this register Base + // procesor will able to know the + // reason for the interrupt. This is + // clear only register - set by HW + // upon an interrupt to Base + // processor and can be cleared only + // by BASE processor. + +#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \ + 0x0000002C // Reading this register Stack + // procesor will able to know the + // reason for the interrupt. This is + // clear only register - set by HW + // upon an interrupt to Stack + // processor and can be cleared only + // by Stack processor. + +#define STACK_DIE_CTRL_O_STK_CLK_EN \ + 0x00000030 // Can be written only by base + // processor. Controls the enable + // pin of the cgcs for the clocks + // going to CM3 dft ctrl block and + // Sram. + +#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \ + 0x00000034 // Can be written only by the base + // processor. Decides the ram + // sharing mode :: handshake or + // Spinlock mode. + +#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \ + 0x00000038 // Stores the last bus fault + // address. + +#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \ + 0x0000003C // write only registers on read + // returns 0.W Write 1 to clear the + // bust fault to store the new bus + // fault address + +#define STACK_DIE_CTRL_O_RESET_CAUSE \ + 0x00000040 // Reset cause value captured from + // the ICR_CLKRST block. + +#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \ + 0x00000044 // Watchdog timer event value + // captured from the ICR_CLKRST + // block + +#define STACK_DIE_CTRL_O_DMA_REQ \ + 0x00000048 // To send Dma Request to bottom + // die. + +#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \ + 0x0000004C // Address offset within SRAM to + // which CM3 should jump after + // reset. + +#define STACK_DIE_CTRL_O_SW_REG1 \ + 0x00000050 // These are sw registers for + // topdie processor and bottom die + // processor to communicate. Both + // can set and read these registers. + // In case of write clash bottom + // die's processor wins and top die + // processor access is ignored. + +#define STACK_DIE_CTRL_O_SW_REG2 \ + 0x00000054 // These are sw registers for + // topdie processor and bottom die + // processor to communicate. Both + // can set and read these registers. + // In case of write clash bottom + // die's processor wins and top die + // processor access is ignored. + +#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \ + 0x00000058 // By posting the request Flash can + // be put into low-power mode + // (Sleep) without powering down the + // Flash. Earlier (in Garnet) this + // was fully h/w controlled and the + // control for this was coming from + // SysCtl while entering into Cortex + // Deep-sleep mode. But for our + // device the D2D i/f doesnt support + // this. The Firmware has to program + // the register in the top-die for + // entering into this mode and wait + // for an interrupt. + +#define STACK_DIE_CTRL_O_MISC_CTL \ + 0x0000005C // Miscellanious control register. + +#define STACK_DIE_CTRL_O_SW_DFT_CTL \ + 0x000000FC // DFT control and status bits + +#define STACK_DIE_CTRL_O_PADN_CTL_0 \ + 0x00000100 // Mainly for For controlling the + // pads OEN pins. There are total 60 + // pads and hence 60 control registe + // i.e n value varies from 0 to 59. + // Here is the mapping for the + // pad_ctl register number and the + // functionality : 0 D2DPAD_DMAREQ1 + // 1 D2DPAD_DMAREQ0 2 + // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 + // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 + // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 + // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS + // 10 D2DPAD_JTAG_TDI 11-27 + // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE + // -1:0] 28-56 D2DPAD_TOSTACK + // [D2D_TOSTACK_SIZE -1:0] 57-59 + // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE + // -1:0] 0:00 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_RESET register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \ + 0x00000001 // 1 :Assert Reset 0 : Deassert the + // Reset + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \ + 0x00000003 // 00 : Equal Priority 01 : Stack + // Processor have priority 10 : Base + // Processor have priority 11 : + // Unused + +#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \ + 0x00000002 // Stack Processor should clear it + // when it is done with the sram + // bank usage. Set by HW It is set + // when Stack Processor is granted + // the access to this bank + +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \ + 0x00000001 // Base Processor should clear it + // when it is done wth the sram + // usage. Set by HW It is set when + // Base Processor is granted the + // access to this bank + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \ + 0x00000001 // Base Processor will set when + // Sram access is needed in Spin + // Lock mode. In Handshake mode + // Stack Processor will set to + // inform Base Processor that it is + // done with the processing of data + // in SRAM and is now ready to use + // by the base processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \ + 0x00000001 // Stack Processor will set when + // Sram access is needed in Spin + // Lock mode. In Handshake mode Base + // Processor will set to inform + // Stack Processor to start + // processing the data in the Ram. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \ + 0x00000002 // Stack Processor should clear it + // when it is done with the sram + // bank usage. Set by HW It is set + // when Stack Processor is granted + // the access to this bank. + +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \ + 0x00000001 // Base Processor should clear it + // when it is done wth the sram + // usage. Set by HW it is set when + // Base Processor is granted the + // access to this bank. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \ + 0x00000001 // Base Processor will set when + // Sram access is needed in Spin + // Lock mode. Not used in handshake + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \ + 0x00000001 // Stack Processor will set when + // Sram access is needed in Spin + // Lock mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RDSM_CFG_CPU register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \ + 0x000000C0 // Bank Clock Hi Time 00 : HCLK + // pulse 01 : 1 cycle of HCLK 10 : + // 1.5 cycles of HCLK 11 : 2 cycles + // of HCLK + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6 +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \ + 0x00000020 // FLCLK 0 : indicates flash clock + // rise aligns on HCLK rise 1 : + // indicates flash clock rise aligns + // on HCLK fall + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \ + 0x00000010 // 0 : Always register flash rdata + // before sending to CPU 1 : Drive + // Flash rdata directly out on MISS + // (Both ICODE / DCODE) + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \ + 0x0000000F // Number of wait states inserted + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RDSM_CFG_EE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \ + 0x000000C0 // Bank Clock Hi Time 00 : HCLK + // pulse 01 : 1 cycle of HCLK 10 : + // 1.5 cycles of HCLK 11 : 2 cycles + // of HCLK + +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6 +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \ + 0x00000020 // FLCLK 0 : indicates flash clock + // rise aligns on HCLK rise 1 : + // indicates flash clock rise aligns + // on HCLK fall + +#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \ + 0x00000010 // 0 : Always register flash rdata + // before sending to CPU 1 : Drive + // Flash rdata directly out on MISS + // (Both ICODE / DCODE) + +#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \ + 0x0000000F // Number of wait states inserted + +#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \ + 0x00000010 // Set when Relinquish Interrupt + // sent to Base processor for Bank3. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \ + 0x00000008 // Set when Relinquish Interrupt + // sent to Base processor for Bank2. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \ + 0x00000004 // Set when Bank3 is granted to + // Base processor. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \ + 0x00000002 // Set when Bank2 is granted to + // BAse processor. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \ + 0x00000001 // Set when there Base processor do + // an Invalid access to Sram. Ex : + // Accessing the bank which is not + // granted for BAse processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \ + 0x00000008 // Set when Relinquish Interrupt + // sent to Stack processor for + // Bank3. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \ + 0x00000004 // Set when Relinquish Interrupt + // sent to Stack processor for + // Bank2. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \ + 0x00000002 // Set when Bank3 is granted to + // Stack processor. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \ + 0x00000001 // Set when Bank2 is granted to + // Stack processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_CLK_EN register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \ + 0x00000004 // Enable the clock going to sram. + +#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \ + 0x00000002 // Enable the clock going to dft + // control block + +#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \ + 0x00000001 // Enable the clock going to Cm3 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \ + 0x00000001 // 0 : Handshake Mode 1 : Spinlock + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \ + 0xFFFFFFFF // Fault Address + +#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BUS_FAULT_CLR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \ + 0x00000001 // When set it'll clear the bust + // fault address register to store + // the new bus fault address + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RESET_CAUSE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_DMA_REQ register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \ + 0x00000002 // Generate DMAREQ1 on setting this + // bit. + +#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \ + 0x00000001 // Generate DMAREQ0 on setting this + // bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_REG1 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_REG2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \ + 0x00000002 // captures the status of of + // fmc_lpm_ack + +#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \ + 0x00000001 // When set assert + // iflpe2fmc_lpm_req to FMC. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_MISC_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \ + 0x00000080 // 1 : will reset the async wdog + // timer runing on piosc clock + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \ + 0x00000020 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \ + 0x00000010 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \ + 0x00000008 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \ + 0x00000004 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 3 goes to Bank3 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank2 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \ + 0x00000002 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 2 goes to Bank2 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank2 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \ + 0x00000001 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 1 goes to Bank1 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_DFT_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \ + 0x20000000 // when set to '1' all flash + // control signals switch over to + // CM3 control when '0' it is under + // the D2D interface control + +#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \ + 0x10000000 // 1 indicates in SWIF mode the + // control signals to flash are from + // FMC CPU read controls the clock + // and address. that is one can give + // address via FMC and read through + // IDMEM. + +#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \ + 0x00800000 // 'CPU Done' bit for PBIST. Write + // '1' to indicate test done. + +#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \ + 0x00400000 // 'CPU Fail' bit for PBIST. Write + // '1' to indicate test failed. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \ + 0x00001000 // when set to '1' flash bank 4 + // (EEPROM) is owned by the CM3for + // reads over DCODE bus. When '0' + // access control given to D2D + // interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \ + 0x00000800 // when set to '1' flash bank 3 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \ + 0x00000400 // when set to '1' flash bank 2 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \ + 0x00000200 // when set to '1' flash bank 1 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \ + 0x00000100 // when set to '1' flash bank 0 is + // owned by the CM3 for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_PADN_CTL_0 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \ + 0x00000008 // This bit is valid for only the + // spare pads ie for n=57 to 59. + // value to drive at the output of + // the pad + +#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \ + 0x00000004 // This bit is valid for only the + // spare pads ie for n=57 to 59. + // captures the 'Y' pin of the pad + // which is the data being driven + // into the die + +#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \ + 0x00000002 // OEN2X control when '1' enables + // the output with 1x. Total drive + // strength is decided bu oen1x + // setting + oen2x setting. + +#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \ + 0x00000001 // OEN1X control when '1' enables + // the output with 1x . Total drive + // strength is decided bu oen1x + // setting + oen2x setting. + + + + +#endif // __HW_STACK_DIE_CTRL_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_timer.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_timer.h new file mode 100755 index 00000000000..af36c3fff3f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_timer.h @@ -0,0 +1,776 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +//***************************************************************************** + +//##### INTERNAL BEGIN ##### +// +// This is an auto-generated file. Do not edit by hand. +// Created by version 6779 of DriverLib. +// +//##### INTERNAL END ##### + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the Timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // GPTM Configuration +#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode +#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode +#define TIMER_O_CTL 0x0000000C // GPTM Control +//##### GARNET BEGIN ##### +#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize +//##### GARNET END ##### +#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask +#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status +#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status +#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear +#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load +#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load +#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match +#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match +#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale +#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale +#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match +#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match +#define TIMER_O_TAR 0x00000048 // GPTM Timer A +#define TIMER_O_TBR 0x0000004C // GPTM Timer B +#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value +#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value +#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide +#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot +#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot +#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value +#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value +#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event +#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties + + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) + // counter configuration +#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The + // function is controlled by bits + // 1:0 of GPTMTAMR and GPTMTBMR + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +//##### GARNET END ##### +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +//##### GARNET END ##### +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable +//##### GARNET BEGIN ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11 +#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of + // GPTM11 is triggered +#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of + // GPTM11 is triggered +#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM11 is + // triggered +#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10 +#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of + // GPTM10 is triggered +#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of + // GPTM10 is triggered +#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM10 is + // triggered +#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9 +#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of + // GPTM9 is triggered +#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of + // GPTM9 is triggered +#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM9 is + // triggered +#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8 +#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of + // GPTM8 is triggered +#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of + // GPTM8 is triggered +#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM8 is + // triggered +#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7 +#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of + // GPTM7 is triggered +#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of + // GPTM7 is triggered +#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM7 is + // triggered +#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6 +#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of + // GPTM6 is triggered +#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of + // GPTM6 is triggered +#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM6 is + // triggered +#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Mask +//##### GARNET END ##### +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match + // Interrupt Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt + // Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt + // Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match + // Interrupt Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt + // Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt + // Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Raw Interrupt Status +//##### GARNET END ##### +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw + // Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw + // Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw + // Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw + // Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw + // Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw + // Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Masked Interrupt Status +//##### GARNET END ##### +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked + // Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked + // Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked + // Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked + // Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Clear +//##### GARNET END ##### +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match + // Interrupt Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt + // Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt + // Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match + // Interrupt Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt + // Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt + // Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +//##### GARNET END ##### +#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load + // Register High +#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load + // Register Low +#define TIMER_TAILR_TAILRH_S 16 +#define TIMER_TAILR_TAILRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAILR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +//##### GARNET END ##### +#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_TBILRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBILR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +//##### GARNET END ##### +#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High +#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low +#define TIMER_TAMATCHR_TAMRH_S 16 +#define TIMER_TAMATCHR_TAMRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAMATCHR_TAMR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +//##### GARNET END ##### +#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low +//##### GARNET BEGIN ##### +#define TIMER_TBMATCHR_TBMR_S 0 +//##### GARNET END ##### +#define TIMER_TBMATCHR_TBMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +//##### GARNET END ##### +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +//##### GARNET BEGIN ##### +#define TIMER_TAPR_TAPSRH_S 8 +//##### GARNET END ##### +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +//##### GARNET END ##### +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +//##### GARNET BEGIN ##### +#define TIMER_TBPR_TBPSRH_S 8 +//##### GARNET END ##### +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +//##### GARNET END ##### +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +//##### GARNET BEGIN ##### +#define TIMER_TAPMR_TAPSMRH_S 8 +//##### GARNET END ##### +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +//##### GARNET END ##### +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +//##### GARNET BEGIN ##### +#define TIMER_TBPMR_TBPSMRH_S 8 +//##### GARNET END ##### +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +//##### GARNET END ##### +#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High +#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAR_TARH_S 16 +#define TIMER_TAR_TARL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +//##### GARNET END ##### +#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B +#define TIMER_TBR_TBRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +//##### GARNET END ##### +#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High +#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAV_TAVH_S 16 +#define TIMER_TAV_TAVL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAV_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +//##### GARNET END ##### +#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register +#define TIMER_TBV_TBVL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start +#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are + // 32 bits each with an 16-bit + // prescale counter +//##### GARNET END ##### + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CFG +// register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CTL +// register. +// +//***************************************************************************** +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_RIS +// register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAILR +// register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBILR +// register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAR +// register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBR +// register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the timer +// registers. +// +//***************************************************************************** +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnMR +// register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPR +// register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPMR +// register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +#endif + +#endif // __HW_TIMER_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_types.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_types.h new file mode 100755 index 00000000000..30f4270dd9c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_types.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif // __HW_TYPES_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_uart.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_uart.h new file mode 100755 index 00000000000..9c2604ccbea --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_uart.h @@ -0,0 +1,415 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 +#define UART_O_RSR 0x00000004 +#define UART_O_ECR 0x00000004 +#define UART_O_FR 0x00000018 +#define UART_O_ILPR 0x00000020 +#define UART_O_IBRD 0x00000024 +#define UART_O_FBRD 0x00000028 +#define UART_O_LCRH 0x0000002C +#define UART_O_CTL 0x00000030 +#define UART_O_IFLS 0x00000034 +#define UART_O_IM 0x00000038 +#define UART_O_RIS 0x0000003C +#define UART_O_MIS 0x00000040 +#define UART_O_ICR 0x00000044 +#define UART_O_DMACTL 0x00000048 +#define UART_O_LCTL 0x00000090 +#define UART_O_LSS 0x00000094 +#define UART_O_LTIM 0x00000098 +#define UART_O_9BITADDR 0x000000A4 +#define UART_O_9BITAMASK 0x000000A8 +#define UART_O_PP 0x00000FC0 +#define UART_O_CC 0x00000FC8 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//****************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//****************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//****************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//****************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect +#define UART_FR_DSR 0x00000002 // Data Set Ready +#define UART_FR_CTS 0x00000001 // Clear To Send +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//****************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//****************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//****************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//****************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 : + // UART_LCRH_WLEN_5 : 5 bits + // (default) 0x00000020 : + // UART_LCRH_WLEN_6 : 6 bits + // 0x00000040 : UART_LCRH_WLEN_7 : 7 + // bits 0x00000060 : + // UART_LCRH_WLEN_8 : 8 bits +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//****************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RI 0x00002000 // Ring Indicator +#define UART_CTL_DCD 0x00001000 // Data Carrier Detect +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_LIN 0x00000040 // LIN Mode Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//****************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX_S 3 +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//****************************************************************************** +#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask +#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask +#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask +#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask +#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt + // Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt + // Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//****************************************************************************** +#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt + // Status +#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status +#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt + // Status +#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt + // Status +#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw + // Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw + // Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem + // Raw Interrupt Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//****************************************************************************** +#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt + // Status +#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt + // Status +#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt + // Status +#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt + // Status +#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked + // Interrupt Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked + // Interrupt Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem + // Masked Interrupt Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//****************************************************************************** +#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear +#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear +#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt + // Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//****************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCTL register. +// +//****************************************************************************** +#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 : + // UART_LCTL_BLEN_13T : Sync break + // length is 13T bits (default) + // 0x00000010 : UART_LCTL_BLEN_14T : + // Sync break length is 14T bits + // 0x00000020 : UART_LCTL_BLEN_15T : + // Sync break length is 15T bits + // 0x00000030 : UART_LCTL_BLEN_16T : + // Sync break length is 16T bits +#define UART_LCTL_BLEN_S 4 +#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LSS register. +// +//****************************************************************************** +#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot +#define UART_LSS_TSS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LTIM register. +// +//****************************************************************************** +#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value +#define UART_LTIM_TIMER_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UART_O_9BITADDR register. +// +//****************************************************************************** +#define UART_9BITADDR_9BITEN \ + 0x00008000 // Enable 9-Bit Mode + +#define UART_9BITADDR_ADDR_M \ + 0x000000FF // Self Address for 9-Bit Mode + +#define UART_9BITADDR_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UART_O_9BITAMASK register. +// +//****************************************************************************** +#define UART_9BITAMASK_RANGE_M \ + 0x0000FF00 // Self Address Range for 9-Bit + // Mode + +#define UART_9BITAMASK_RANGE_S 8 +#define UART_9BITAMASK_MASK_M \ + 0x000000FF // Self Address Mask for 9-Bit Mode + +#define UART_9BITAMASK_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//****************************************************************************** +#define UART_PP_MSE 0x00000008 // Modem Support Extended +#define UART_PP_MS 0x00000004 // Modem Support +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//****************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source + // 0x00000005 : UART_CC_CS_PIOSC : + // PIOSC 0x00000000 : + // UART_CC_CS_SYSCLK : The system + // clock (default) +#define UART_CC_CS_S 0 + + + +#endif // __HW_UART_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_udma.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_udma.h new file mode 100755 index 00000000000..8f01306ccbd --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_udma.h @@ -0,0 +1,334 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// The following are defines for the UDMA register offsets. +// +//***************************************************************************** +#define UDMA_O_STAT 0x00000000 +#define UDMA_O_CFG 0x00000004 +#define UDMA_O_CTLBASE 0x00000008 +#define UDMA_O_ALTBASE 0x0000000C +#define UDMA_O_WAITSTAT 0x00000010 +#define UDMA_O_SWREQ 0x00000014 +#define UDMA_O_USEBURSTSET 0x00000018 +#define UDMA_O_USEBURSTCLR 0x0000001C +#define UDMA_O_REQMASKSET 0x00000020 +#define UDMA_O_REQMASKCLR 0x00000024 +#define UDMA_O_ENASET 0x00000028 +#define UDMA_O_ENACLR 0x0000002C +#define UDMA_O_ALTSET 0x00000030 +#define UDMA_O_ALTCLR 0x00000034 +#define UDMA_O_PRIOSET 0x00000038 +#define UDMA_O_PRIOCLR 0x0000003C +#define UDMA_O_ERRCLR 0x0000004C +#define UDMA_O_CHASGN 0x00000500 +#define UDMA_O_CHIS 0x00000504 +#define UDMA_O_CHMAP0 0x00000510 +#define UDMA_O_CHMAP1 0x00000514 +#define UDMA_O_CHMAP2 0x00000518 +#define UDMA_O_CHMAP3 0x0000051C +#define UDMA_O_PV 0x00000FB0 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_STAT register. +// +//****************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_DMACHANS_S 16 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status + // 0x00000090 : UDMA_STAT_STATE_DONE + // : Done 0x00000000 : + // UDMA_STAT_STATE_IDLE : Idle + // 0x00000010 : + // UDMA_STAT_STATE_RD_CTRL : Reading + // channel controller data + // 0x00000030 : + // UDMA_STAT_STATE_RD_DSTENDP : + // Reading destination end pointer + // 0x00000040 : + // UDMA_STAT_STATE_RD_SRCDAT : + // Reading source data 0x00000020 : + // UDMA_STAT_STATE_RD_SRCENDP : + // Reading source end pointer + // 0x00000080 : + // UDMA_STAT_STATE_STALL : Stalled + // 0x000000A0 : + // UDMA_STAT_STATE_UNDEF : Undefined + // 0x00000060 : UDMA_STAT_STATE_WAIT + // : Waiting for uDMA request to + // clear 0x00000070 : + // UDMA_STAT_STATE_WR_CTRL : Writing + // channel controller data + // 0x00000050 : + // UDMA_STAT_STATE_WR_DSTDAT : + // Writing destination data +#define UDMA_STAT_STATE_S 4 +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CFG register. +// +//****************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CTLBASE register. +// +//****************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTBASE register. +// +//****************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_WAITSTAT register. +// +//****************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M \ + 0xFFFFFFFF // Channel [n] Wait Status + +#define UDMA_WAITSTAT_WAITREQ_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SWREQ register. +// +//****************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request +#define UDMA_SWREQ_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UDMA_O_USEBURSTSET register. +// +//****************************************************************************** +#define UDMA_USEBURSTSET_SET_M \ + 0xFFFFFFFF // Channel [n] Useburst Set + +#define UDMA_USEBURSTSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UDMA_O_USEBURSTCLR register. +// +//****************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M \ + 0xFFFFFFFF // Channel [n] Useburst Clear + +#define UDMA_USEBURSTCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_REQMASKSET register. +// +//****************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set +#define UDMA_REQMASKSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register. +// +//****************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear +#define UDMA_REQMASKCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ENASET register. +// +//****************************************************************************** +#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set +#define UDMA_ENASET_CHENSET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ENACLR register. +// +//****************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear +#define UDMA_ENACLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTSET register. +// +//****************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set +#define UDMA_ALTSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTCLR register. +// +//****************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear +#define UDMA_ALTCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PRIOSET register. +// +//****************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set +#define UDMA_PRIOSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PRIOCLR register. +// +//****************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear +#define UDMA_PRIOCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ERRCLR register. +// +//****************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHASGN register. +// +//****************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHIS register. +// +//****************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status +#define UDMA_CHIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP0 register. +// +//****************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH0SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP1 register. +// +//****************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH8SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP2 register. +// +//****************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH16SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP3 register. +// +//****************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH24SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PV register. +// +//****************************************************************************** +#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision +#define UDMA_PV_MAJOR_S 8 +#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision +#define UDMA_PV_MINOR_S 0 + + + +#endif // __HW_UDMA_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_wdt.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_wdt.h new file mode 100755 index 00000000000..75d5591afe3 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_wdt.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// The following are defines for the WDT register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 +#define WDT_O_VALUE 0x00000004 +#define WDT_O_CTL 0x00000008 +#define WDT_O_ICR 0x0000000C +#define WDT_O_RIS 0x00000010 +#define WDT_O_MIS 0x00000014 +#define WDT_O_TEST 0x00000418 +#define WDT_O_LOCK 0x00000C00 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//****************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//****************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//****************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit + // is not used in cc3xx, WDOG shall + // always generate RESET to system + // irrespective of this bit setting. +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//****************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//****************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//****************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//****************************************************************************** +#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable +#define WDT_TEST_STALL_EN_S 10 +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//****************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_S 0 +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + + + + + +#endif // __HW_WDT_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Power.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Power.h new file mode 100755 index 00000000000..38b96bcdaa9 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Power.h @@ -0,0 +1,607 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file Power.h + * + * @brief Power Manager interface + * + * The Power header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Operation # + * The Power Manager facilitates the transition of the MCU from active states + * to sleep states and vice versa. It provides other drivers the + * ability to set and release dependencies on hardware resources, and keeps + * reference counts on each resource to know when to enable or disable the + * resource. It provides drivers the ability to register callback functions + * to be invoked upon specific power events. In addition, drivers and + * applications can set or release constraints to prevent the MCU from + * transitioning into specific active or sleep states. + * + * The Power Manager APIs and configuration parameters are described here. + * For a detailed description of terms and concepts, and usage by different + * types of software components (peripheral drivers, power policies, + * and applications) please see the + * SimpleLink SDK Power Management User's Guide. + * + * ============================================================================ + */ + +#ifndef ti_drivers_Power__include +#define ti_drivers_Power__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Power latency types */ +#define Power_TOTAL (1U) /*!< total latency */ +#define Power_RESUME (2U) /*!< resume latency */ + +/* Power notify responses */ +#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ +#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ + +/* Power status */ +#define Power_SOK (0) /*!< OK, operation succeeded */ +#define Power_EFAIL (-1) /*!< general failure */ +#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ +#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ +#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ +#define Power_EBUSY (-5) /*!< busy with another transition */ + +/* Power transition states */ +#define Power_ACTIVE (1U) /*!< normal active state */ +#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ +#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ +#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ +#define Power_CHANGING_PERF_LEVEL (5U) /*!< moving to new performance level */ + + +/*! + * @brief Power policy initialization function pointer + */ +typedef void (*Power_PolicyInitFxn)(void); + +/*! + * @brief Power policy function pointer + */ +typedef void (*Power_PolicyFxn)(void); + +/*! + * @brief Power notify function pointer + */ +typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType, + uintptr_t eventArg, uintptr_t clientArg); + +/*! + * @brief Power notify object structure. + * + * This struct specification is for internal use. Notification clients must + * pre-allocate a notify object when registering for a notification; + * Power_registerNotify() will take care initializing the internal elements + * appropriately. + */ +typedef struct Power_NotifyObj_ { + List_Elem link; /*!< for placing on the notify list */ + uint_fast16_t eventTypes; /*!< the event type */ + Power_NotifyFxn notifyFxn; /*!< notification function */ + uintptr_t clientArg; /*!< argument provided by client */ +} Power_NotifyObj; + +/*! + * @brief Disable the configured power policy from running when the CPU is + * idle + * + * Calling this function clears the flag that controls whether the configured + * power policy function is invoked on each pass through the Idle loop. + * This function call will override both a 'true' setting of the + * "enablePolicy" setting in the Power Manager configuration object, as well + * as a previous runtime call to the Power_enablePolicy() function. + * + * @return The old value of "enablePolicy". + * + * @sa Power_enablePolicy + */ +bool Power_disablePolicy(void); + +/*! + * @brief Enable the configured power policy to run when the CPU is idle + * + * Calling this function sets a flag that will cause the configured power + * policy function to be invoked on each pass through the Idle loop. This + * function call will override both a 'false' setting of the "enablePolicy" + * setting in the Power Manager configuration object, as well as a previous + * runtime call to the Power_disablePolicy() function. + * + * For some processor families, automatic power transitions can make initial + * application development more difficult, as well as being at odds with + * basic debugger operation. This convenience function allows an application + * to be initially configured, built, and debugged, without automatic power + * transitions during idle time. When the application is found to be working, + * this function can be called (typically in main()) to enable the policy + * to run, without having to change the application configuration. + * + * @sa Power_disablePolicy + */ +void Power_enablePolicy(void); + +/*! + * @brief Get the constraints that have been declared with Power + * + * This function returns a bitmask indicating the constraints that are + * currently declared to the Power Manager (via previous calls to + * Power_setConstraint()). For each constraint that is currently declared, + * the corresponding bit in the bitmask will be set. For example, if two + * clients have independently declared two different constraints, the returned + * bitmask will have two bits set. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. The corresponding bit in the + * bitmask returned by this function can be derived by a left-shift using + * the constraint identifier. For example, for MSP432, for the corresponding + * bit for the PowerMSP432_DISALLOW_SLEEP constraint, the bit position is + * determined by the operation: (1 << PowerMSP432_DISALLOW_SLEEP) + * + * @return A bitmask of the currently declared constraints. + * + * @sa Power_setConstraint + */ +uint_fast32_t Power_getConstraintMask(void); + +/*! + * @brief Get the current dependency count for a resource + * + * This function returns the number of dependencies that are currently + * declared upon a resource. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param resourceId resource id + * + * @return The number of dependencies declared for the resource. + * Power_EINVALIDINPUT if the resourceId is invalid. + * + * @sa Power_setDependency + */ +int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId); + +/*! + * @brief Get the current performance level + * + * This function returns the current device performance level in effect. + * + * If performance scaling is not supported for the device, this function + * will always indicate a performance level of zero. + * + * @return The current performance level. + * + * @sa Power_setPerformanceLevel + */ +uint_fast16_t Power_getPerformanceLevel(void); + +/*! + * @brief Get the hardware transition latency for a sleep state + * + * This function reports the minimal hardware transition latency for a specific + * sleep state. The reported latency is that for a direct transition, and does + * not include any additional latency that might occur due to software-based + * notifications. + * + * Sleep states are device specific, and defined in the device-specific Power + * include file. For example, the sleep states for CC32XX are defined in + * PowerCC32XX.h. + * + * This function is typically called by the power policy function. The latency + * is reported in units of microseconds. + * + * @param sleepState the sleep state + * + * @param type the latency type (Power_TOTAL or Power_RESUME) + * + * @return The latency value, in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, + uint_fast16_t type); + +/*! + * @brief Get the current transition state of the Power Manager + * + * This function returns the current transition state for the Power Manager. + * For example, when no transitions are in progress, a status of Power_ACTIVE + * is returned. Power_ENTERING_SLEEP is returned during the transition to + * sleep, before sleep has occurred. Power_EXITING_SLEEP is returned + * after wakeup, as the device is being transitioned back to Power_ACTIVE. + * And Power_CHANGING_PERF_LEVEL is returned when a change is being made + * to the performance level. + * + * @return The current Power Manager transition state. + */ +uint_fast16_t Power_getTransitionState(void); + +/*! + * @brief Power function to be added to the application idle loop + * + * This function should be added to the application idle loop. (The method to + * do this depends upon the operating system being used.) This function + * will invoke the configured power policy function when appropriate. The + * specific policy function to be invoked is configured as the 'policyFxn' + * in the application-defined Power configuration object. + * + */ +void Power_idleFunc(void); + +/*! + * @brief Power initialization function + * + * This function initializes Power Manager internal state. It must be called + * prior to any other Power API. This function is normally called as part + * of TI-RTOS board initialization, for example, from within the + * \_initGeneral() function. + * + * @return Power_SOK + */ +int_fast16_t Power_init(void); + +/*! + * @brief Register a function to be called upon a specific power event + * + * This function registers a function to be called when a Power event occurs. + * Registrations and the corresponding notifications are processed in + * first-in-first-out (FIFO) order. The function registered must behave as + * described later, below. + * + * The pNotifyObj parameter is a pointer to a pre-allocated, opaque object + * that will be used by Power to support the notification. This object could + * be dynamically allocated, or declared as a global object. This function + * will properly initialized the object's fields as appropriate; the caller + * just needs to provide a pointer to this pre-existing object. + * + * The eventTypes parameter identifies the type of power event(s) for which + * the notify function being registered is to be called. (Event identifiers are + * device specific, and defined in the device-specific Power include file. + * For example, the events for MSP432 are defined in PowerMSP432.h.) The + * eventTypes parameter for this function call is treated as a bitmask, so + * multiple event types can be registered at once, using a common callback + * function. For example, to call the specified notifyFxn when both + * the entering deepsleep and awake from deepsleep events occur, eventTypes + * should be specified as: PowerMSP432_ENTERING_DEEPSLEEP | + * PowerMSP432_AWAKE_DEEPSLEEP + * + * The notifyFxn parameter specifies a callback function to be called when the + * specified Power event occurs. The notifyFxn must implement the following + * signature: + * status = notifyFxn(eventType, eventArg, clientArg); + * + * Where: eventType identifies the event being signalled, eventArg is an + * optional event-specific argument, and clientArg is an abitrary argument + * specified by the client at registration. Note that multipe types of events + * can be specified when registering the notification callback function, + * but when the callback function is actually called by Power, only a + * single eventType will be specified for the callback (i.e., the current + * event). The status returned by the client notification function must + * be one of the following constants: Power_NOTIFYDONE if the client processed + * the notification successfully, or Power_NOTIFYERROR if an error occurred + * during notification. + * + * The clientArg parameter is an arbitrary, client-defined argument to be + * passed back to the client upon notification. This argument may allow one + * notify function to be used by multiple instances of a driver (that is, the + * clientArg can be used to identify the instance of the driver that is being + * notified). + * + * @param pNotifyObj notification object (preallocated by caller) + * + * @param eventTypes event type or types + * + * @param notifyFxn client's callback function + * + * @param clientArg client-specified argument to pass with notification + * + * @return Power_SOK on success. + * Power_EINVALIDPOINTER if either pNotifyObj or notifyFxn are NULL. + * + * @sa Power_unregisterNotify + */ +int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, + uint_fast16_t eventTypes, + Power_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Release a previously declared constraint + * + * This function releases a constraint that was previously declared with + * Power_setConstraint(). For example, if a device driver is starting an I/O + * transaction and wants to prohibit activation of a sleep state during the + * transaction, it uses Power_setConstraint() to declare the constraint, + * before starting the transaction. When the transaction completes, the + * driver calls this function to release the constraint, to allow the Power + * manager to once again allow transitions to sleep. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. + * + * Only one constraint can be specified with each call to this function; to + * release multiple constraints this function must be called multiple times. + * + * It is critical that clients call Power_releaseConstraint() when operational + * constraints no longer exists. Otherwise, Power may be left unnecessarily + * restricted from activating power savings. + * + * @param constraintId constraint id + * + * @return CC26XX/CC13XX only: Power_SOK. To minimize code size + * asserts are used internally to check that the constraintId is valid, + * and that the constraint count is not already zero; + * the function always returns Power_SOK. + * + * @return All other devices: Power_SOK on success, + * Power_EINVALIDINPUT if the constraintId is invalid, and Power_EFAIL + * if the constraint count is already zero. + * + * @sa Power_setConstraint + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId); + +/*! + * @brief Release a previously declared dependency + * + * This function releases a dependency that had been previously declared upon + * a resource (by a call to Power_setDependency()). + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param resourceId resource id + * + * @return CC26XX/CC13XX only: Power_SOK. To minimize code size + * asserts are used internally to check that the resourceId is valid, + * and that the resource reference count is not already zero; + * the function always returns Power_SOK. + * + * @return All other devices: Power_SOK on success, + * Power_EINVALIDINPUT if the resourceId is invalid, and Power_EFAIL + * if the resource reference count is already zero. + * + * @sa Power_setDependency + */ +int_fast16_t Power_releaseDependency(uint_fast16_t resourceId); + +/*! + * @brief Declare an operational constraint + * + * Before taking certain actions, the Power Manager checks to see if the + * requested action would conflict with a client-declared constraint. If the + * action does conflict, Power will not proceed with the request. This is the + * function that allows clients to declare their constraints with Power. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. + * + * Only one constraint can be specified with each call to this function; to + * declare multiple constraints this function must be called multiple times. + * + * @param constraintId constraint id + * + * @return CC26XX/CC13XX only: Power_SOK. To minimize code size an + * assert is used internally to check that the constraintId is valid; + * the function always returns Power_SOK. + * + * @return All other devices: Power_SOK on success, + * Power_EINVALIDINPUT if the constraintId is invalid. + * + * @sa Power_releaseConstraint + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId); + +/*! + * @brief Declare a dependency upon a resource + * + * This function declares a dependency upon a resource. For example, if a + * UART driver needs a specific UART peripheral, it uses this function to + * declare this to the Power Manager. If the resource had been inactive, + * then Power will activate the peripheral during this function call. + * + * What is needed to make a peripheral resource 'active' will vary by device + * family. For some devices this may be a simple enable of a clock to the + * specified peripheral. For others it may also require a power on of a + * power domain. In either case, the Power Manager will take care of these + * details, and will also implement reference counting for resources and their + * interdependencies. For example, if multiple UART peripherals reside in + * a shared serial power domain, the Power Manager will power up the serial + * domain when it is first needed, and then automatically power the domain off + * later, when all related dependencies for the relevant peripherals are + * released. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param resourceId resource id + * + * @return CC26XX/CC13XX only: Power_SOK. To minimize code size an + * assert is used internally to check that the resourceId is valid; + * the function always returns Power_SOK. + * + * @return All other devices: Power_SOK on success, + * Power_EINVALIDINPUT if the reseourceId is invalid. + * + * @sa Power_releaseDependency + */ +int_fast16_t Power_setDependency(uint_fast16_t resourceId); + +/*! + * @brief Set the MCU performance level + * + * This function manages a transition to a new device performance level. + * Before the actual transition is initiated, notifications will be sent to + * any clients who've registered (with Power_registerNotify()) for a + * 'start change performance level' notification. The event name is device + * specific, and defined in the device-specific Power include file. For + * example, for MSP432, the event is "PowerMSP432_START_CHANGE_PERF_LEVEL", + * which is defined in PowerMSP432.h. Once notifications have been completed, + * the change to the performance level is initiated. After the level change + * is completed, there is a comparable event that can be used to signal a + * client that the change has completed. For example, on MSP432 the + * "PowerMSP432_DONE_CHANGE_PERF_LEVEL" event can be used to signal + * completion. + * + * This function will not return until the new performance level is in effect. + * If performance scaling is not supported for the device, or is prohibited + * by an active constraint, or if the specified level is invalid, then an + * error status will be returned. + * + * @param level the new performance level + * + * @return Power_SOK on success. + * Power_EINVALIDINPUT if the specified performance level is out of + * range of valid levels. + * Power_EBUSY if another transition is already in progress, or if + * a single constraint is set to prohibit any change to the + * performance level. + * Power_ECHANGE_NOT_ALLOWED if a level-specific constraint prohibits + * a change to the requested level. + * Power_EFAIL if performance scaling is not supported, if an + * error occurred during initialization, or if an error occurred + * during client notifications. + * + * @sa Power_getPerformanceLevel + */ +int_fast16_t Power_setPerformanceLevel(uint_fast16_t level); + +/*! + * @brief Set a new Power policy + * + * This function allows a new Power policy function to be selected at runtime. + * + * @param policy the new Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy); + +/*! + * @brief Put the device into a shutdown state + * + * This function will transition the device into a shutdown state. + * Before the actual transition is initiated, notifications will be sent to + * any clients who've registered (with Power_registerNotify()) for an + * 'entering shutdown' event. The event name is device specific, and defined + * in the device-specific Power include file. For example, for CC32XX, the + * event is "PowerCC32XX_ENTERING_SHUTDOWN", which is defined in + * PowerCC32XX.h. Once notifications have been completed, the device shutdown + * will commence. + * + * If the device is successfully transitioned to shutdown, this function + * call will never return. Upon wakeup, the device and application will + * be rebooted (through a device reset). If the transition is not + * successful, one of the error codes listed below will be returned. + * + * On some devices a timed wakeup from shutdown can be specified, using + * the shutdownTime parameter. This enables an autonomous application reboot + * at a future time. For example, an application can go to shutdown, and then + * automatically reboot at a future time to do some work. And once that work + * is done, the application can shutdown again, for another timed interval. + * The time interval is specified via the shutdownTime parameter. (On devices + * that do not support this feature, any value specified for shutdownTime will + * be ignored.) If the specified shutdownTime is less than the total + * shutdown latency for the device, then shutdownTime will be ignored. The + * shutdown latency for the device can be found in the device-specific Power + * include file. For example, for the CC32XX, this latency is defined in + * PowerCC32XX.h, as "PowerCC32XX_TOTALTIMESHUTDOWN".) + * + * @param shutdownState the device-specific shutdown state + * + * @param shutdownTime the amount of time (in milliseconds) to keep the + * the device in the shutdown state; this parameter + * is not supported on all device families + * + * @return Power_ECHANGE_NOT_ALLOWED if a constraint is prohibiting shutdown. + * Power_EFAIL if an error occurred during client notifications. + * Power_EINVALIDINPUT if the shutdownState is invalid. + * Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, + uint_fast32_t shutdownTime); + +/*! + * @brief Transition the device into a sleep state + * + * This function is called from the power policy when it has made a decision + * to put the device in a specific sleep state. This function returns to the + * caller (the policy function) once the device has awoken from sleep. + * + * This function must be called with interrupts disabled, and should not be + * called directly by the application, or by any drivers. + * This function does not check declared constraints; the policy function + * must check constraints before calling this function to initiate sleep. + * + * @param sleepState the sleep state + * + * @return Power_SOK on success, the device has slept and is awake again. + * Power_EFAIL if an error occurred during client notifications, or + * if a general failure occurred. + * Power_EINVALIDINPUT if the sleepState is invalid. + * Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState); + +/*! + * @brief Unregister previously registered notifications + * + * This function unregisters for event notifications that were previously + * registered with Power_registerNotify(). The caller must specify a pointer + * to the same notification object used during registration. + * + * @param pNotifyObj notify object + * + * @sa Power_registerNotify + */ +void Power_unregisterNotify(Power_NotifyObj *pNotifyObj); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Power__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.c new file mode 100755 index 00000000000..66f5cd82a0c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.c @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +extern const UDMACC32XX_Config UDMACC32XX_config[]; + +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg); + +static bool dmaInitialized = false; +static Power_NotifyObj postNotifyObj; /* LPDS wake-up notify object */ + +/* Reference count for open calls */ +static uint32_t refCount = 0; + +/* + * ======== UDMACC32XX_close ======== + */ +void UDMACC32XX_close(UDMACC32XX_Handle handle) +{ + UDMACC32XX_Object *object = handle->object; + uintptr_t key; + + Power_releaseDependency(PowerCC32XX_PERIPH_UDMA); + + key = HwiP_disable(); + + refCount--; + + if (refCount == 0) { + Power_unregisterNotify(&postNotifyObj); + object->isOpen = false; + } + + HwiP_restore(key); +} + +/* + * ======== UDMACC32XX_init ======== + */ +void UDMACC32XX_init() +{ + HwiP_Params hwiParams; + UDMACC32XX_Handle handle = (UDMACC32XX_Handle)&(UDMACC32XX_config[0]); + UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + UDMACC32XX_Object *object = handle->object; + + if (!dmaInitialized) { + object->isOpen = false; + + HwiP_Params_init(&hwiParams); + hwiParams.priority = hwAttrs->intPriority; + + /* Will check in UDMACC32XX_open() if this failed */ + object->hwiHandle = HwiP_create(hwAttrs->intNum, hwAttrs->dmaErrorFxn, + &hwiParams); + if (object->hwiHandle == NULL) { + DebugP_log0("Failed to create uDMA error Hwi!!\n"); + } + else { + dmaInitialized = true; + } + } +} + +/* + * ======== UDMACC32XX_open ======== + */ +UDMACC32XX_Handle UDMACC32XX_open() +{ + UDMACC32XX_Handle handle = (UDMACC32XX_Handle)&(UDMACC32XX_config); + UDMACC32XX_Object *object = handle->object; + UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + if (!dmaInitialized) { + return (NULL); + } + + Power_setDependency(PowerCC32XX_PERIPH_UDMA); + + key = HwiP_disable(); + + /* + * If the UDMA has not been opened yet, create the error Hwi + * and initialize the control table base address. + */ + if (object->isOpen == false) { + MAP_PRCMPeripheralReset(PRCM_UDMA); + + MAP_uDMAEnable(); + MAP_uDMAControlBaseSet(hwAttrs->controlBaseAddr); + + Power_registerNotify(&postNotifyObj, PowerCC32XX_AWAKE_LPDS, + postNotifyFxn, (uintptr_t)handle); + + object->isOpen = true; + } + + refCount++; + + HwiP_restore(key); + + return (handle); +} + +/* + * ======== postNotifyFxn ======== + * Called by Power module when waking up from LPDS. + */ +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg) +{ + UDMACC32XX_Handle handle = (UDMACC32XX_Handle)clientArg; + UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + MAP_uDMAEnable(); + MAP_uDMAControlBaseSet(hwAttrs->controlBaseAddr); + + return (Power_NOTIFYDONE); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.h new file mode 100755 index 00000000000..d57f9b28cfd --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dma/UDMACC32XX.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UDMACC32XX.h + * + * @brief uDMA driver implementation for CC32XX. + * + * This driver is intended for use only by TI-RTOS drivers that use the uDMA + * peripheral (e.g., SPI and I2S). This driver is mainly used for Power + * management of the UDMA peripheral. + * + * The application should only define the memory for the control table and + * set up the UDMACC32XX_HWAttrs and UDMACC32XX_Config structures. + * + * The UDMACC32XX header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_dma_UDMACC32XX__include +#define ti_drivers_dma_UDMACC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief UDMA error function pointer + */ +typedef void (*UDMACC32XX_ErrorFxn)(uintptr_t arg); + +/*! + * @brief UDMACC32XX Hardware attributes + * + * This structure contains the base address of the uDMA control + * table, and uDMA error interrupt attributes. + * + * The control table is used by the uDMA controller to store channel + * control structures. The control table can be located anywhere in + * system memory, but must be contiguous and aligned on a 1024-byte boundary. + * + * dmaErrorFxn is the uDMA peripheral's error interrupt handler. + * + * intPriority is priority of the uDMA peripheral's error interrupt, as + * defined by the underlying OS. It is passed unmodified to the + * underlying OS's interrupt handler creation code, so you need to + * refer to the OS documentation for usage. If the + * driver uses the ti.dpl interface instead of making OS + * calls directly, then the HwiP port handles the interrupt priority + * in an OS specific way. In the case of the SYS/BIOS port, + * intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * + * #include + * + * #if defined(__TI_COMPILER_VERSION__) + * #pragma DATA_ALIGN(dmaControlTable, 1024) + * #elif defined(__IAR_SYSTEMS_ICC__) + * #pragma data_alignment=1024 + * #elif defined(__GNUC__) + * __attribute__ ((aligned (1024))) + * #endif + * + * static tDMAControlTable dmaControlTable[64]; + * + * #include + * + * UDMACC32XX_Object udmaCC32XXObject; + * + * const UDMACC32XX_HWAttrs udmaCC32XXHWAttrs = { + * .controlBaseAddr = (void *)dmaControlTable, + * .dmaErrorFxn = UDMACC32XX_errorFxn, + * .intNum = INT_UDMAERR, + * .intPriority = (~0) + * }; + * @endcode + * + */ +typedef struct UDMACC32XX_HWAttrs { + void *controlBaseAddr; /*!< uDMA control registers base address */ + UDMACC32XX_ErrorFxn dmaErrorFxn; /*!< uDMA error interrupt handler */ + uint8_t intNum; /*!< uDMA error interrupt number */ + uint8_t intPriority; /*!< uDMA error interrupt priority. */ +} UDMACC32XX_HWAttrs; + +/*! + * @brief UDMACC32XX Global configuration + * + * The UDMACC32XX_Config structure contains pointers used by the UDMACC32XX + * driver. + * + * This structure needs to be defined before calling UDMACC32XX_init() and + * it must not be changed thereafter. + */ +typedef struct UDMACC32XX_Config { + void *object; /*!< Pointer to UDMACC32XX object */ + void const *hwAttrs; /*!< Pointer to hardware attributes */ +} UDMACC32XX_Config; + +/*! + * @brief A handle that is returned from a UDMACC32XX_open() call. + */ +typedef struct UDMACC32XX_Config *UDMACC32XX_Handle; + +/*! + * @brief UDMACC32XX object + * + * The application must not access any member variables of this structure! + */ +typedef struct UDMACC32XX_Object { + bool isOpen; /* Flag for open/close status */ + HwiP_Handle hwiHandle; /* DMA error Hwi */ +} UDMACC32XX_Object; + +/*! + * @brief Function to close the DMA driver. + * + * This function releases Power dependency on UDMA that was previously + * set with a call to UDMACC32XX_open(). If there is only one outstanding + * UDMACC32XX_open() call (i.e. all but one UDMACC32XX_open() calls have + * been matched by a corresponding call to UDMACC32XX_close()), this + * function will disable the UDMA. + * + * @pre UDMACC32XX_open() has to be called first. + * Calling context: Task + * + * @param handle A UDMACC32XX_Handle returned from UDMACC32XX_open() + * + * @return none + * + * @sa UDMACC32XX_open + */ +extern void UDMACC32XX_close(UDMACC32XX_Handle handle); + +/*! + * @brief Function to initialize the CC32XX DMA driver + * + * The function will set the isOpen flag to false, and should be called prior + * to opening the DMA driver. + * + * @return none + * + * @sa UDMACC32XX_open() + */ +extern void UDMACC32XX_init(); + +/*! + * @brief Function to initialize the CC32XX DMA peripheral + * + * UDMACC32XX_open() can be called multiple times. Each time the + * function is called, it will set a dependency on the peripheral and + * enable the clock. The Power dependency count on the UDMA will be + * equal to the number of outstanding calls to UDMACC32XX_open(). + * Calling UDMACC32XX_close() will decrement the Power dependency count, + * and the last call to UDMACC32XX_close() will disable the UDMA. + * + * @pre UDMACC32XX_init() has to be called first. + * Calling context: Task + * + * @return UDMACC32XX_Handle on success or NULL if an error has occurred. + * + * @sa UDMACC32XX_close() + */ +extern UDMACC32XX_Handle UDMACC32XX_open(); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_dma_UDMACC32XX__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/ClockP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/ClockP.h new file mode 100755 index 00000000000..76a0bd810b8 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/ClockP.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ClockP.h + * + * @brief Clock interface for the RTOS Porting Interface + * + * The ClockP module can be used to schedule functions that run at intervals + * specified in the underlying kernel's system ticks. ClockP instances are + * one-shot. The one-shot function will be run once + * after the specified period has elapsed since calling ClockP_start(). + * + * The ClockP module can also be used to obtain the period of the kernel's + * system tick in microseconds. This is useful for determining the number of + * ticks needed for setting a Clock object's period. + * + * When using the TI-RTOS kernel, ClockP functions are run at software + * interrupt level. With FreeRTOS, the ClockP functions are run by a timer + * service task with priority configured by the application. + * + * A common use case is to post a semaphore in the clock function. There is a + * specific API for this: Semaphore_postFromClock(). This must be used in a + * clock function (instead of Semaphore_post). + * + * ============================================================================ + */ + +#ifndef ti_dpl_ClockP__include +#define ti_dpl_ClockP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * ClockP object. + * + * nortos: 32 (biggest of the HW-specific ClockP instance structs) + * SysBIOS: 36 + */ +#define ClockP_STRUCT_SIZE (36) + +/*! + * @brief ClockP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific ClockP objects. + */ +typedef union ClockP_Struct { + uint32_t dummy; /*!< Align object */ + char data[ClockP_STRUCT_SIZE]; +} ClockP_Struct; + +/*! + * @brief Frequency-in-hertz struct + */ +typedef struct ClockP_FreqHz { + uint32_t hi; /*!< most significant 32-bits of frequency */ + uint32_t lo; /*!< least significant 32-bits of frequency */ +} ClockP_FreqHz; + +/*! + * @brief Status codes for ClockP APIs + */ +typedef enum ClockP_Status { + ClockP_OK = 0, + ClockP_FAILURE = -1 +} ClockP_Status; + +/*! + * @brief Opaque client reference to an instance of a ClockP + * + * A ClockP_Handle returned from the ::ClockP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::ClockP_start, + * ::ClockP_stop, etc.). + */ +typedef void *ClockP_Handle; + +#define ClockP_handle(x) ((ClockP_Handle)(x)) + +extern uint32_t ClockP_tickPeriod; + +/*! + * @brief Prototype for a ClockP function. + */ +typedef void (*ClockP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic ClockP Parameters + * + * Structure that contains the parameters passed into ::ClockP_create + * when creating a ClockP instance. The ::ClockP_Params_init function should + * be used to initialize the fields to default values before the application + * sets the fields manually. The ClockP default parameters are noted in + * ClockP_Params_init. + * The default startFlag is false, meaning the user will have to call + * ClockP_start(). If startFlag is true, the clock instance will be + * started automatically when it is created. + * + * The default value of period is 0, indicating a one-shot clock object. + * A non-zero period indicates the clock function will be called + * periodically at the period rate (in system clock ticks), after the + * clock is initially started and set to expire with the 'timeout' + * argument. + */ +typedef struct ClockP_Params { + bool startFlag; /*!< Start immediately after instance is created. */ + uint32_t period; /*!< Period of clock object. */ + uintptr_t arg; /*!< Argument passed into the clock function. */ +} ClockP_Params; + + +/*! + * @brief Function to construct a clock object. + * + * @param clockP Pointer to ClockP_Struct object. + * @param timeout The startup timeout, if supported by the RTOS. + * @param clockFxn Function called when timeout or period expires. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A ClockP_Handle on success or a NULL on an error + */ +extern ClockP_Handle ClockP_construct(ClockP_Struct *clockP, + ClockP_Fxn clockFxn, + uint32_t timeout, + ClockP_Params *params); + +/*! + * @brief Function to destruct a clock object + * + * @param clockP Pointer to a ClockP_Struct object that was passed to + * ClockP_construct(). + * + * @return + */ +extern void ClockP_destruct(ClockP_Struct *clockP); + +/*! + * @brief Function to create a clock object. + * + * @param clockFxn Function called when timeout or period expires. + * @param timeout The startup timeout, if supported by the RTOS. + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in ::ClockP_Params_init. + * + * @return A ClockP_Handle on success or a NULL on an error. This handle can + * be passed to ClockP_start() + */ +extern ClockP_Handle ClockP_create(ClockP_Fxn clockFxn, + uint32_t timeout, + ClockP_Params *params); + +/*! + * @brief Function to delete a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + */ +extern void ClockP_delete(ClockP_Handle handle); + +/*! + * @brief Get CPU frequency in Hz + * + * @param freq Pointer to the FreqHz structure + */ +extern void ClockP_getCpuFreq(ClockP_FreqHz *freq); + +/*! + * @brief Get the system tick period in microseconds. + * + * @return The kernel's system tick period in microseconds. + */ +extern uint32_t ClockP_getSystemTickPeriod(); + +/*! + * @brief Get the current tick value + * + * The value returned will wrap back to zero after it reaches the max + * value that can be stored in 32 bits. + * + * @return Time in system clock ticks + */ +extern uint32_t ClockP_getSystemTicks(); + +/*! + * @brief Get number of ClockP tick periods expected to expire between + * now and the next interrupt from the timer peripheral + * + * Returns the number of ClockP tick periods that are expected to expore + * between now and the next interrupt from the timer peripheral. + * + * Used internally by PowerCC26XX module + * + * @return count in ticks + */ +extern uint32_t ClockP_getTicksUntilInterrupt(); + +/*! + * @brief Get timeout of clock instance. + * + * Returns the remaining time in clock ticks if the instance has + * been started. If the clock is not active, the initial timeout value + * is returned. + * + * @return remaining timeout in clock ticks. + * + * Cannot change the initial timeout if the clock has been started. + */ +extern uint32_t ClockP_getTimeout(ClockP_Handle handle); + +/*! + * @brief Determine if a clock object is currently active (i.e., running) + * + * Returns true if the clock object is currently active, otherwise + * returns false. + * + * @return active state + */ +extern bool ClockP_isActive(ClockP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * - arg: 0 + * + * @param params Pointer to the instance configuration parameters. + */ +extern void ClockP_Params_init(ClockP_Params *params); + +/*! + * @brief Set the initial timeout + * + * @param timeout Initial timeout in ClockP ticks + * + * Cannot change the initial timeout if the clock has been started. + */ +extern void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout); + +/*! + * @brief Function to start a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + */ +extern void ClockP_start(ClockP_Handle handle); + +/*! + * @brief Function to stop a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + * + * It is ok to call ClockP_stop() for a clock that has not been started. + * + * @return Status of the functions + * - ClockP_OK: Stopped the clock function successfully + * - ClockP_FAILURE: The API failed. + */ +extern void ClockP_stop(ClockP_Handle handle); + +extern void ClockP_timestamp(ClockP_Handle handle); + +/*! + * @brief Set delay in microseconds + * + * @param usec A duration in micro seconds + * + * @return ClockP_OK + */ +extern void ClockP_usleep(uint32_t usec); + +/*! + * @brief Set delay in seconds + * + * @param sec A duration in seconds + * + * @return ClockP_OK + */ +extern void ClockP_sleep(uint32_t sec); + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_ClockP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/DebugP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/DebugP.h new file mode 100755 index 00000000000..51faa02c346 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/DebugP.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DebugP.h + * + * @brief Debug support + * + * The DebugP module allows application to do logging and assert checking. + * + * DebugP_assert calls can be added into code. If the code + * is compiled with the compiler define DebugP_ASSERT_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_ASSERT_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + * + * This module sits on top of the assert checking of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * Similarly, DebugP_logN calls can be added into code. If the code + * is compiled with the compiler define DebugP_LOG_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_LOG_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + + * This module sits on top of the logging of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * ============================================================================ + */ + +#ifndef ti_dpl_DebugP__include +#define ti_dpl_DebugP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif + +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#if DebugP_ASSERT_ENABLED +extern void _DebugP_assert(int expression, const char *file, int line); +/*! + * @brief Assert checking function + * + * If the expression is evaluated to true, the API does nothing. + * If it is evaluated to false, the underlying RTOS port implementation + * handles the assert via its mechanisms. + * + * @param expression Expression to evaluate + */ +#define DebugP_assert(expression) (_DebugP_assert(expression, \ + __FILE__, __LINE__)) +#else +#define DebugP_assert(expression) +#endif + +#if DebugP_LOG_ENABLED +/*! + * @brief Debug log function with 0 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + */ +extern void DebugP_log0(const char *format); + +/*! + * @brief Debug log function with 1 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + */ +extern void DebugP_log1(const char *format, uintptr_t p1); + +/*! + * @brief Debug log function with 2 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + */ +extern void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2); + +/*! + * @brief Debug log function with 3 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + */ +extern void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3); + +/*! + * @brief Debug log function with 4 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + * @param p4 fourth parameter to format string + */ +extern void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4); +#else +#define DebugP_log0(format) +#define DebugP_log1(format, p1) +#define DebugP_log2(format, p1, p2) +#define DebugP_log3(format, p1, p2, p3) +#define DebugP_log4(format, p1, p2, p3, p4) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_DebugP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiP.h new file mode 100755 index 00000000000..fa6f1260490 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiP.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file HwiP.h + * + * @brief Hardware Interrupt module for the RTOS Porting Interface + * + * The ::HwiP_disable/::HwiP_restore APIs can be called recursively. The order + * of the HwiP_restore calls, must be in reversed order. For example: + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_HwiP__include +#define ti_dpl_HwiP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * HwiP object. + * + * nortos: 12 + * SysBIOS: 28 + */ +#define HwiP_STRUCT_SIZE (28) + +/*! + * @brief HwiP structure. + * + * Opaque structure that should be large enough to hold any of the RTOS + * specific HwiP objects. + */ +typedef union HwiP_Struct { + uint32_t dummy; /*!< Align object */ + char data[HwiP_STRUCT_SIZE]; +} HwiP_Struct; + +/*! + * @brief Opaque client reference to an instance of a HwiP + * + * A HwiP_Handle returned from the ::HwiP_create represents that instance. + */ +typedef void *HwiP_Handle; + +/*! + * @brief Status codes for HwiP APIs + */ +typedef enum HwiP_Status { + HwiP_OK = 0, + HwiP_FAILURE = -1 +} HwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*HwiP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic HwiP Parameters + * + * Structure that contains the parameters passed into ::HwiP_create + * when creating a HwiP instance. The ::HwiP_Params_init function should + * be used to initialize the fields to default values before the application sets + * the fields manually. The HwiP default parameters are noted in + * HwiP_Params_init. + * + * Parameter enableInt specifies if the interrupt should be enabled + * upon creation of the HwiP object. The default is true. + */ +typedef struct HwiP_Params { + uintptr_t arg; /*!< Argument passed into the Hwi function. */ + uint32_t priority; /*!< Device specific priority. */ + bool enableInt; /*!< Enable interrupt on creation. */ +} HwiP_Params; + +/*! + * @brief Interrupt number posted by SwiP + * + * The SwiP module needs its scheduler to run at key points in SwiP + * processing. This is accomplished via an interrupt that is configured + * at the lowest possible interrupt priority level and is plugged with + * the SwiP scheduler. This interrupt must be the *only* interrupt at + * that lowest priority. SwiP will post this interrupt whenever its + * scheduler needs to run. + * + * The default value for your device should suffice, but if a different + * interrupt is needed to be used for SwiP scheduling then HwiP_swiPIntNum + * can be assigned with this interrupt (early on, before HwiPs are created + * and before any SwiP gets posted). + */ +extern int HwiP_swiPIntNum; + +/*! + * @brief Function to construct a hardware interrupt object. + * + * @param hwiP Pointer to HwiP_Struct object. + * @param interruptNum Interrupt Vector Id + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in ::HwiP_Params_init. + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_construct(HwiP_Struct *hwiP, int interruptNum, + HwiP_Fxn hwiFxn, HwiP_Params *params); + +/*! + * @brief Function to destruct a hardware interrupt object + * + * @param hwiP Pointer to a HwiP_Struct object that was passed to + * HwiP_construct(). + * + * @return + */ +extern void HwiP_destruct(HwiP_Struct *hwiP); + +/*! + * @brief Function to clear a single interrupt + * + * @param interruptNum interrupt number to clear + */ +extern void HwiP_clearInterrupt(int interruptNum); + +/*! + * @brief Function to create an interrupt on CortexM devices + * + * @param interruptNum Interrupt Vector Id + * + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in ::HwiP_Params_init. + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, + HwiP_Params *params); + +/*! + * @brief Function to delete an interrupt on CortexM devices + * + * @param handle returned from the HwiP_create call + * + * @return + */ +extern void HwiP_delete(HwiP_Handle handle); + +/*! + * @brief Function to disable interrupts to enter a critical region + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to HwiP_restore to re-enable interrupts. + */ +extern uintptr_t HwiP_disable(void); + +/*! + * @brief Function to enable interrupts + */ +extern void HwiP_enable(void); + +/*! + * @brief Function to disable a single interrupt + * + * @param interruptNum interrupt number to disable + */ +extern void HwiP_disableInterrupt(int interruptNum); + +/*! + * @brief Function to enable a single interrupt + * + * @param interruptNum interrupt number to enable + */ +extern void HwiP_enableInterrupt(int interruptNum); + +/*! + * @brief Function to return a status based on whether it is in an interrupt + * context. + * + * @return A status: indicating whether the function was called in an + * ISR (true) or at thread level (false). + */ +extern bool HwiP_inISR(void); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - arg: 0 + * - priority: ~0 + * - enableInt: true + * + * @param params Pointer to the instance configuration parameters. + */ +extern void HwiP_Params_init(HwiP_Params *params); + +/*! + * @brief Function to plug an interrupt vector + * + * @param interruptNum ID of interrupt to plug + * @param fxn ISR that services plugged interrupt + */ +extern void HwiP_plug(int interruptNum, void *fxn); + +/*! + * @brief Function to generate an interrupt + * + * @param interruptNum ID of interrupt to generate + */ +extern void HwiP_post(int interruptNum); + +/*! + * @brief Function to restore interrupts to exit a critical region + * + * @param key return from HwiP_disable + */ +extern void HwiP_restore(uintptr_t key); + +/*! + * @brief Function to overwrite HwiP function and arg + * + * @param hwiP handle returned from the HwiP_create or construct call + * @param fxn pointer to ISR function + * @param arg argument to ISR function + */ +extern void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg); + +/*! + * @brief Function to set the priority of a hardware interrupt + * + * @param interruptNum id of the interrupt to change + * @param priority new priority + */ +extern void HwiP_setPriority(int interruptNum, uint32_t priority); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_HwiP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiPCC32XX.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiPCC32XX.cpp new file mode 100755 index 00000000000..d9cac222573 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/HwiPCC32XX.cpp @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== HwiPCC32XX_nortos.c ======== + */ + +#include +#include + +#include +#include + +/* Driver lib includes */ +#include +#include +#include +#include +#include + +#define MAX_INTERRUPTS 195 + +typedef struct _HwiP_Obj { + uint32_t intNum; + HwiP_Fxn fxn; + uintptr_t arg; +} HwiP_Obj; + +typedef struct Hwi_NVIC { + uint32_t RES_00; + uint32_t ICTR; + uint32_t RES_08; + uint32_t RES_0C; + uint32_t STCSR; + uint32_t STRVR; + uint32_t STCVR; + uint32_t STCALIB; + uint32_t RES_20[56]; + uint32_t ISER[8]; + uint32_t RES_120[24]; + uint32_t ICER[8]; + uint32_t RES_1A0[24]; + uint32_t ISPR[8]; + uint32_t RES_220[24]; + uint32_t ICPR[8]; + uint32_t RES_2A0[24]; + uint32_t IABR[8]; + uint32_t RES_320[56]; + uint8_t IPR[240]; + uint32_t RES_4F0[516]; + uint32_t CPUIDBR; + uint32_t ICSR; + uint32_t VTOR; + uint32_t AIRCR; + uint32_t SCR; + uint32_t CCR; + uint8_t SHPR[12]; + uint32_t SHCSR; + uint8_t MMFSR; + uint8_t BFSR; + uint16_t UFSR; + uint32_t HFSR; + uint32_t DFSR; + uint32_t MMAR; + uint32_t BFAR; + uint32_t AFSR; + uint32_t PFR0; + uint32_t PFR1; + uint32_t DFR0; + uint32_t AFR0; + uint32_t MMFR0; + uint32_t MMFR1; + uint32_t MMFR2; + uint32_t MMFR3; + uint32_t ISAR0; + uint32_t ISAR1; + uint32_t ISAR2; + uint32_t ISAR3; + uint32_t ISAR4; + uint32_t RES_D74[5]; + uint32_t CPACR; + uint32_t RES_D8C[93]; + uint32_t STI; + uint32_t RES_F04[12]; + uint32_t FPCCR; + uint32_t FPCAR; + uint32_t FPDSCR; + uint32_t MVFR0; + uint32_t MVFR1; + uint32_t RES_F48[34]; + uint32_t PID4; + uint32_t PID5; + uint32_t PID6; + uint32_t PID7; + uint32_t PID0; + uint32_t PID1; + uint32_t PID2; + uint32_t PID3; + uint32_t CID0; + uint32_t CID1; + uint32_t CID2; + uint32_t CID3; +} Hwi_NVIC; + +static Hwi_NVIC *Hwi_nvic = (Hwi_NVIC *)0xE000E000; + +static HwiP_Obj* HwiP_dispatchTable[MAX_INTERRUPTS] = { + 0 +}; +uintptr_t HwiP_key = 0; + +int HwiP_swiPIntNum = FAULT_PENDSV; + + +/* + * ======== HwiP_enable ======== + */ +void HwiP_enable(void) +{ + MAP_IntMasterEnable(); +} + +/* + * ======== HwiP_disable ======== + */ +uintptr_t HwiP_disable(void) +{ + return (MAP_IntMasterDisable()); +} + +/* + * ======== HwiP_restore ======== + */ +void HwiP_restore(uintptr_t alreadyDisabled) +{ + if (!alreadyDisabled) { + MAP_IntMasterEnable(); + } +} + +/* + * ======== HwiP_clearInterrupt ======== + */ +void HwiP_clearInterrupt(int interruptNum) +{ + MAP_IntPendClear((unsigned long)interruptNum); +} + +/* + * ======== HwiP_destruct ======== + */ +void HwiP_destruct(HwiP_Struct *handle) +{ + HwiP_Obj *obj = (HwiP_Obj *)handle; + + MAP_IntDisable((unsigned long)obj->intNum); + MAP_IntUnregister((unsigned long)obj->intNum); +} + +/* + * ======== HwiP_delete ======== + */ +void HwiP_delete(HwiP_Handle handle) +{ + HwiP_destruct((HwiP_Struct *)handle); + + free(handle); +} + +/* + * ======== HwiP_disableInterrupt ======== + */ +void HwiP_disableInterrupt(int interruptNum) +{ + MAP_IntDisable((unsigned long)interruptNum); +} + +/* + * ======== HwiP_dispatch ======== + */ +void HwiP_dispatch(void) +{ + Hwi_NVIC *Hwi_nvic = (Hwi_NVIC *)0xE000E000; + + /* Determine which interrupt has fired */ + uint32_t intNum = (Hwi_nvic->ICSR & 0x000000ff); + HwiP_Obj* obj = HwiP_dispatchTable[intNum]; + if (obj) { + (obj->fxn)(obj->arg); + } +} + +/* + * ======== HwiP_enableInterrupt ======== + */ +void HwiP_enableInterrupt(int interruptNum) +{ + MAP_IntEnable((unsigned long)interruptNum); +} + +/* + * ======== HwiP_construct ======== + */ +HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, + HwiP_Fxn hwiFxn, HwiP_Params *params) +{ + HwiP_Params defaultParams; + HwiP_Obj *obj = (HwiP_Obj *)handle; + + if (handle != NULL) { + if (params == NULL) { + params = &defaultParams; + HwiP_Params_init(&defaultParams); + } + + if ((params->priority & 0xFF) == 0xFF) { + /* SwiP_nortos.c uses INT_PRIORITY_LVL_7 as its scheduler */ + params->priority = INT_PRIORITY_LVL_6; + } + + if (interruptNum != HwiP_swiPIntNum && + params->priority == INT_PRIORITY_LVL_7) { + DebugP_log0("HwiP_construct: can't use reserved INT_PRIORITY_LVL_7"); + + handle = NULL; + } + else { + HwiP_dispatchTable[interruptNum] = obj; + obj->fxn = hwiFxn; + obj->arg = params->arg; + obj->intNum = (uint32_t)interruptNum; + + MAP_IntRegister((unsigned long)interruptNum, + (void(*)(void))HwiP_dispatch); + MAP_IntPrioritySet((unsigned long)interruptNum, params->priority); + + if (params->enableInt) { + MAP_IntEnable((unsigned long)interruptNum); + } + } + } + + return ((HwiP_Handle)handle); +} + +/* + * ======== HwiP_create ======== + */ +HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params) +{ + HwiP_Handle handle; + HwiP_Handle retHandle; + + handle = (HwiP_Handle)malloc(sizeof(HwiP_Obj)); + + /* + * Even though HwiP_construct will check handle for NULL and not do + * anything, we should check it here so that we can know afterwards + * that construct failed with non-NULL pointer and that we need to + * free the handle. + */ + if (handle != NULL) { + retHandle = HwiP_construct((HwiP_Struct *)handle, interruptNum, hwiFxn, + params); + if (retHandle == NULL) { + free(handle); + handle = NULL; + } + } + + return (handle); +} + +/* + * ======== HwiP_Params_init ======== + */ +void HwiP_Params_init(HwiP_Params *params) +{ + if (params != NULL) { + params->arg = 0; + params->priority = ~0; + params->enableInt = true; + } +} + +/* + * ======== HwiP_plug ======== + */ +void HwiP_plug(int interruptNum, void *fxn) +{ + MAP_IntRegister((unsigned long)interruptNum, (void(*)(void))fxn); +} + +/* + * ======== HwiP_setFunc ======== + */ +void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg) +{ + HwiP_Obj *obj = (HwiP_Obj *)hwiP; + + uintptr_t key = HwiP_disable(); + + obj->fxn = fxn; + obj->arg = arg; + + HwiP_restore(key); +} + +/* + * ======== HwiP_post ======== + */ +void HwiP_post(int interruptNum) +{ + IntPendSet((unsigned long)interruptNum); +} + +/* + * ======== HwiP_inISR ======== + */ +bool HwiP_inISR(void) +{ + bool stat; + + if ((Hwi_nvic->ICSR & 0x000000ff) == 0) { + stat = false; + } + else { + stat = true; + } + + return (stat); +} + +/* + * ======== HwiP_inSwi ======== + */ +bool HwiP_inSwi(void) +{ + uint32_t intNum = Hwi_nvic->ICSR & 0x000000ff; + if (intNum == (uint32_t)HwiP_swiPIntNum) { + /* Currently in a Swi */ + return (true); + } + + return (false); +} + +/* + * ======== HwiP_setPriority ======== + */ +void HwiP_setPriority(int interruptNum, uint32_t priority) +{ + MAP_IntPrioritySet((unsigned long)interruptNum, (unsigned char)priority); +} + +/* + * ======== HwiP_staticObjectSize ======== + */ +size_t HwiP_staticObjectSize(void) +{ + return (sizeof(HwiP_Obj)); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.cpp new file mode 100755 index 00000000000..b8457bbf911 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.cpp @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== MutexP_freertos.c ======== + */ + +#include +#include + + +/* + * ======== MutexP_create ======== + */ +MutexP_Handle MutexP_create(MutexP_Params *params) +{ + Mutex * p_mutex; + + p_mutex = new Mutex; + + return ((MutexP_Handle)p_mutex); +} + +/* + * ======== MutexP_delete ======== + */ +void MutexP_delete(MutexP_Handle handle) +{ + delete ((Mutex *)handle); +} + +/* + * ======== MutexP_lock ======== + */ +uintptr_t MutexP_lock(MutexP_Handle handle) +{ + Mutex * p_mutex = ( Mutex *)handle; + + /* Try 1 millisecond */ + while(p_mutex->trylock_for(1) == false); + return (0); +} + +/* + * ======== MutexP_Params_init ======== + */ +void MutexP_Params_init(MutexP_Params *params) +{ + params->callback = NULL; +} + +#if (configSUPPORT_STATIC_ALLOCATION == 1) +/* + * ======== MutexP_staticObjectSize ======== + */ +size_t MutexP_staticObjectSize(void) +{ + return (sizeof(StaticSemaphore_t)); +} +#endif + +/* + * ======== MutexP_unlock ======== + */ +void MutexP_unlock(MutexP_Handle handle, uintptr_t key) +{ + Mutex * p_mutex = (Mutex *)handle; + p_mutex->unlock(); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.h new file mode 100755 index 00000000000..037bb553327 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/MutexP.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file MutexP.h + * + * @brief Mutex module for the RTOS Porting Interface + * + * The MutexP module allows task to maintain critical region segments. The + * MutexP module has two main functions: ::MutexP_lock and ::MutexP_unlock. + * + * The MutexP module supports recursive calls to the MutexP_lock API by a + * single task. The same number of MutexP_unlock calls must be done for the + * mutex to be release. Note: the returned key must be provided in the LIFO + * order. For example: + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_lock(key2); + * MutexP_lock(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_MutexP__include +#define ti_dpl_MutexP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * MutexP object. + * + * nortos: 12 + * SysBIOS: 40 + */ +#define MutexP_STRUCT_SIZE (40) + +/*! + * @brief MutexP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific MutexP objects. + */ +typedef union MutexP_Struct { + uint32_t dummy; /*!< Align object */ + char data[MutexP_STRUCT_SIZE]; +} MutexP_Struct; + +/*! + * @brief Status codes for MutexP APIs + */ +typedef enum MutexP_Status { + /*! API completed successfully */ + MutexP_OK = 0, + /*! API failed */ + MutexP_FAILURE = -1 +} MutexP_Status; + +/*! + * @brief Opaque client reference to an instance of a MutexP + * + * A MutexP_Handle returned from the ::MutexP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::MutexP_lock, + * ::MutexP_unlock, etc.). + */ +typedef void *MutexP_Handle; + +/*! + * @brief Basic MutexP Parameters + * + * Structure that contains the parameters are passed into ::MutexP_create + * when creating a MutexP instance. The ::MutexP_Params_init function should + * be used to initialize the fields to default values before the application + * sets the fields manually. The MutexP default parameters are noted in + * ::MutexP_Params_init. + */ +typedef struct MutexP_Params { + void (*callback)(void); /*!< Callback while waiting for mutex unlock */ +} MutexP_Params; + + +/*! + * @brief Function to construct a mutex. + * + * @param handle Pointer to a MutexP_Struct object + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (MutexP default + * parameters as noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_construct(MutexP_Struct *handle, + MutexP_Params *params); + +/*! + * @brief Function to destruct a mutex object + * + * @param mutexP Pointer to a MutexP_Struct object that was passed to + * MutexP_construct(). + * + * @return + */ +extern void MutexP_destruct(MutexP_Struct *mutexP); + +/*! + * @brief Function to create a mutex. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The MutexP default + * parameters are noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_create(MutexP_Params *params); + +/*! + * @brief Function to delete a mutex. + * + * @param handle A MutexP_Handle returned from MutexP_create + */ +extern void MutexP_delete(MutexP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * callback - NULL. + * + * @param params Pointer to the instance configuration parameters. + */ +extern void MutexP_Params_init(MutexP_Params *params); + +/*! + * @brief Function to lock a mutex. + * + * This function can only be called from a Task. It cannot be called from + * an interrupt. The lock will block until the mutex is available. + * + * Users of a mutex should make every attempt to minimize the duration that + * that they have it locked. This is to minimize latency. It is recommended + * that the users of the mutex do not block while they have the mutex locked. + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @return A key is returned. This key must be passed into ::MutexP_unlock. + */ +extern uintptr_t MutexP_lock(MutexP_Handle handle); + +/*! + * @brief Function to unlock a mutex + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. The order of + * the keys must be reversed. For example + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_lock(key2); + * MutexP_lock(key1); + * @endcode + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @param key Return from ::MutexP_lock. + */ +extern void MutexP_unlock(MutexP_Handle handle, uintptr_t key); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_MutexP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/PowerCC32XX_mbed.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/PowerCC32XX_mbed.cpp new file mode 100755 index 00000000000..4356822bf38 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/PowerCC32XX_mbed.cpp @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== PowerCC32XX.cpp ======== + */ + +#include +#include + +/* driverlib header files */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +/* bitmask of constraints that disallow LPDS */ +#define LPDS_DISALLOWED (1 << PowerCC32XX_DISALLOW_LPDS) + +/* macro to pick two matching count values */ +#define COUNT_WITHIN_TRESHOLD(a, b, c, th) \ + ((((b) - (a)) <= (th)) ? (b) : (c)) + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + + +static volatile uint32_t idleTime = 0; + +void PowerCC32XX_sleepPolicy() +{ +#if (configUSE_TICKLESS_IDLE != 0) + int i = 0; + bool returnFromSleep = FALSE; + unsigned long constraintMask; + unsigned long long ullLowPowerTimeBeforeSleep, ullLowPowerTimeAfterSleep; + unsigned long long count[3]; + unsigned long long ullSleepTime; + unsigned long long time; + unsigned long long remain; + eSleepModeStatus eSleepStatus; + + /* + * Enter a critical section that will not effect interrupts + * bringing the MCU out of sleep mode. + */ + vPortEnterCritical(); + + /* query the declared constraints */ + constraintMask = Power_getConstraintMask(); + + /* check if we are allowed to go to LPDS */ + if ((constraintMask & LPDS_DISALLOWED) == 0) { + /* + * Read the current time from a time source that will remain + * operational while the microcontroller is in a low power state. + */ + /* + * Get the current RTC count, using the fast interface; to use the + * fast interface the count must be read three times, and then + * the value that matches on at least two of the reads is chosen + */ + for (i = 0; i < 3; i++) { + count[i] = MAP_PRCMSlowClkCtrFastGet(); + } + ullLowPowerTimeBeforeSleep = + COUNT_WITHIN_TRESHOLD(count[0], count[1], count[2], 1); + + /* Stop the timer that is generating the tick interrupt. */ + MAP_SysTickDisable(); + + /* Ensure it is still ok to enter the sleep mode. */ + eSleepStatus = eTaskConfirmSleepModeStatus(); + + if (eSleepStatus == eAbortSleep ) { + /* + * A task has been moved out of the Blocked state since this + * macro was executed, or a context siwth is being held pending. + * Do not enter a sleep state. Restart the tick and exit the + * critical section. + */ + MAP_SysTickEnable(); + vPortExitCritical(); + + returnFromSleep = FALSE; + } + else { + /* convert ticks to microseconds */ + time = idleTime * ClockP_getSystemTickPeriod(); + + /* check if can go to LPDS */ + if (time > Power_getTransitionLatency(PowerCC32XX_LPDS, + Power_TOTAL)) { + remain = ((time - PowerCC32XX_TOTALTIMELPDS) * 32768) / 1000000; + + /* set the LPDS wakeup time interval */ + MAP_PRCMLPDSIntervalSet(remain); + + /* enable the wake source to be timer */ + MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_TIMER); + + /* go to LPDS mode */ + Power_sleep(PowerCC32XX_LPDS); + + /* set 'returnFromSleep' to TRUE*/ + returnFromSleep = TRUE; + } + else { + MAP_SysTickEnable(); + vPortExitCritical(); + + returnFromSleep = FALSE; + } + } + } + else { + /* A constraint was set */ + vPortExitCritical(); + } + + if (returnFromSleep) { + /* + * Determine how long the microcontroller was actually in a low + * power state for, which will be less than xExpectedIdleTime if the + * microcontroller was brought out of low power mode by an interrupt + * other than that configured by the vSetWakeTimeInterrupt() call. + * Note that the scheduler is suspended before + * portSUPPRESS_TICKS_AND_SLEEP() is called, and resumed when + * portSUPPRESS_TICKS_AND_SLEEP() returns. Therefore no other + * tasks will execute until this function completes. + */ + for (i = 0; i < 3; i++) { + count[i] = MAP_PRCMSlowClkCtrFastGet(); + } + ullLowPowerTimeAfterSleep = + COUNT_WITHIN_TRESHOLD(count[0], count[1], count[2], 1); + + ullSleepTime = ullLowPowerTimeAfterSleep - ullLowPowerTimeBeforeSleep; + + ullSleepTime = ullSleepTime*1000; + ullSleepTime = ullSleepTime/32768; + + /* + * Correct the kernels tick count to account for the time the + * microcontroller spent in its low power state. + */ + vTaskStepTick((unsigned long)ullSleepTime); + + /* Restart the timer that is generating the tick interrupt. */ + MAP_SysTickEnable(); + + /* + * Exit the critical section - it might be possible to do this + * immediately after the prvSleep() calls. + */ + vPortExitCritical(); + } + else { + MAP_PRCMSleepEnter(); + } +#endif +} + +/* + * ======== PowerCC32XX_initPolicy ======== + */ +void PowerCC32XX_initPolicy() +{ +} +#if 0 +/* Tickless Hook */ +void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) +{ +#if (configUSE_TICKLESS_IDLE != 0) + idleTime = xExpectedIdleTime; + Power_idleFunc(); +#endif +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.cpp new file mode 100755 index 00000000000..85c2336af9a --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.cpp @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== SemaphoreP.c ======== + */ +#include +//#include +#include "mbed.h" + +/* + * Maximum count for a semaphore. + */ +#define MAXCOUNT 0xffff + +/* + * ======== SemaphoreP_create ======== + */ +SemaphoreP_Handle SemaphoreP_create(unsigned int count, + SemaphoreP_Params *params) +{ + SemaphoreP_Handle sem = NULL; + SemaphoreP_Params semParams; + + if (params == NULL) { + params = &semParams; + SemaphoreP_Params_init(params); + } + + if (params->mode == SemaphoreP_Mode_COUNTING) { +#if (configUSE_COUNTING_SEMAPHORES == 1) + Semaphore * p_sem = new Semaphore(0, count); + sem = (void*)p_sem; +#endif + } + else { + Semaphore * p_sem = new Semaphore(0, count); + sem = (void*)p_sem; + if ((sem != NULL) && (count != 0)) { + p_sem->release(); + } + } + return ((SemaphoreP_Handle)sem); +} + +/* + * ======== SemaphoreP_createBinary ======== + */ +SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count) +{ + SemaphoreP_Handle sem = NULL; + + Semaphore * p_sem = new Semaphore(count, 1); + + sem = (void*)p_sem; + if ((sem != NULL) && (count != 0)) { + p_sem->release(); + } + return ((SemaphoreP_Handle)sem); +} + +/* + * ======== SemaphoreP_delete ======== + */ +void SemaphoreP_delete(SemaphoreP_Handle handle) +{ + delete ((Semaphore *)handle); +} + +/* + * ======== SemaphoreP_Params_init ======== + */ +void SemaphoreP_Params_init(SemaphoreP_Params *params) +{ + params->mode = SemaphoreP_Mode_COUNTING; + params->callback = NULL; +} + +/* + * ======== SemaphoreP_pend ======== + */ +SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout) +{ + if (((Semaphore *)handle)->try_acquire_for(timeout)) + { + return (SemaphoreP_OK); + } + + return (SemaphoreP_TIMEOUT); +} + +/* + * ======== SemaphoreP_post ======== + */ +void SemaphoreP_post(SemaphoreP_Handle handle) +{ + ((Semaphore *)handle)->release(); +} + +#if (configSUPPORT_STATIC_ALLOCATION == 1) +/* + * ======== SemaphoreP_staticObjectSize ======== + */ +size_t SemaphoreP_staticObjectSize(void) +{ + return (sizeof(StaticSemaphore_t)); +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.h new file mode 100755 index 00000000000..7753e2d75f2 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SemaphoreP.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SemaphoreP.h + * + * @brief Semaphore module for the RTOS Porting Interface + * + * Semaphores can be counting semaphores or binary semaphores. Counting + * semaphores keep track of the number of times the semaphore has been posted + * with post functions. This is useful, for example, if you have a group of + * resources that are shared between tasks. Such tasks might call pend() to see + * if a resource is available before using one. A count of zero for a counting + * semaphore denotes that it is not available. A positive count denotes + * how many times a SemaphoreP_pend can be called before it is blocked (or + * returns SemaphoreP_TIMEOUT). + * + * Binary semaphores can have only two states: available (count = 1) and + * unavailable (count = 0). They can be used to share a single resource + * between tasks. They can also be used for a basic signalling mechanism, where + * the semaphore can be posted multiple times. Binary semaphores do not keep + * track of the count; they simply track whether the semaphore has been posted + * or not. + * + * ============================================================================ + */ + +#ifndef ti_dpl_SemaphoreP__include +#define ti_dpl_SemaphoreP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * SemaphoreP object. + * + * nortos: 16 + * SysBIOS: 28 + */ +#define SemaphoreP_STRUCT_SIZE (28) + +/*! + * @brief SemaphoreP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific SemaphoreP objects. + */ +typedef union SemaphoreP_Struct { + uint32_t dummy; /*!< Align object */ + char data[SemaphoreP_STRUCT_SIZE]; +} SemaphoreP_Struct; + +/*! + * @brief Wait forever define + */ +#define SemaphoreP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define SemaphoreP_NO_WAIT (0) + +/*! + * @brief Status codes for SemaphoreP APIs (for backwards compatibility) + */ +typedef enum SemaphoreP_Status { + /*! API completed successfully */ + SemaphoreP_OK = 0, + /*! API failed because of a timeout */ + SemaphoreP_TIMEOUT = -1 +} SemaphoreP_Status; + +/*! + * @brief Opaque client reference to an instance of a SemaphoreP + * + * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that + * instance and is used in the other instance based functions (e.g. + * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). + */ +typedef void *SemaphoreP_Handle; + +/*! + * @brief Mode of the semaphore + */ +typedef enum SemaphoreP_Mode { + SemaphoreP_Mode_COUNTING = 0x0, + SemaphoreP_Mode_BINARY = 0x1 +} SemaphoreP_Mode; + +/*! + * @brief Basic SemaphoreP Parameters + * + * Structure that contains the parameters are passed into ::SemaphoreP_create + * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function + * should be used to initialize the fields to default values before the + * application sets the fields manually. The SemaphoreP default parameters are + * noted in SemaphoreP_Params_init. + */ +typedef struct SemaphoreP_Params { + SemaphoreP_Mode mode; /*!< Mode for the semaphore */ + void (*callback)(void); /*!< Callback while pending for semaphore post */ +} SemaphoreP_Params; + +/*! + * @brief Default SemaphoreP instance parameters + * + * SemaphoreP_defaultParams represents the default parameters that are + * used when creating or constructing a SemaphoreP instance. + * SemaphoreP_Params_init() will use the contents of this structure for + * initializing the SemaphoreP_Params instance. + * + * SemaphoreP_defaultParams is exposed to the application for the purpose + * of allowing the application to change the default parameters for all + * SemaphoreP instances created thereafter. The main intent for allowing + * the default parameters to be changed is for setting a semaphore's + * callback function to Power_idleFunc(), so that the SOC can enter low + * power mode when pending on a semaphore. + */ +extern SemaphoreP_Params SemaphoreP_defaultParams; + + +/* + * SemaphoreP construct APIs can only be used if one of the OS's + * is defined. For FreeRTOS, configSUPPORT_STATIC_ALLOCATION also + * has to be set to 1 in FreeRTOSConfig.h. + */ +extern SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, + unsigned int count, SemaphoreP_Params *params); + +extern SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, + unsigned int count); + +extern void SemaphoreP_destruct(SemaphoreP_Struct *semP); + +/*! + * @brief Function to create a semaphore. + * + * @param count Initial count of the semaphore. For binary semaphores, + * only values of 0 or 1 are valid. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (SemaphoreP default + * parameters as noted in ::SemaphoreP_Params_init. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_create(unsigned int count, + SemaphoreP_Params *params); + +/*! + * @brief Function to create a binary semaphore. + * + * This can be used instead of SemaphoreP_create() to create a binary + * semaphore. + * + * @param count Initial count of the binary semaphore. Only values + * of 0 or 1 are valid. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count); + +/*! + * @brief Function to create a binary semaphore. + * + * This can be used instead of SemaphoreP_create() to create a binary + * semaphore. + * + * @param count Initial count of the binary semaphore. Only values + * of 0 or 1 are valid. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_createBinaryCallback(unsigned int count, + void (*callback)(void)); + +/*! + * @brief Function to delete a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + */ +extern void SemaphoreP_delete(SemaphoreP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - mode: SemaphoreP_Mode_COUNTING + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SemaphoreP_Params_init(SemaphoreP_Params *params); + +/*! + * @brief Function to pend (wait) on a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + * + * @param timeout Timeout (in ClockP ticks) to wait for the semaphore to + * be posted (signalled). + * + * @return Status of the functions + * - SemaphoreP_OK: Obtained the semaphore + * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. + */ +extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, + uint32_t timeout); + +/*! + * @brief Function to post (signal) a semaphore from task of ISR context. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + */ +extern void SemaphoreP_post(SemaphoreP_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SemaphoreP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SwiP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SwiP.h new file mode 100755 index 00000000000..4f2b3f11d4d --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SwiP.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SwiP.h + * + * @brief Software Interrupt module for the RTOS Porting Interface + * + * ============================================================================ + */ + +#ifndef ti_dpl_SwiP__include +#define ti_dpl_SwiP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * SwiP object. + * + * nortos: 40 + * SysBIOS: 52 + */ +#define SwiP_STRUCT_SIZE (52) + +/*! + * @brief SemaphoreP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific SwiP objects. + */ +typedef union SwiP_Struct { + uint32_t dummy; /*!< Align object */ + char data[SwiP_STRUCT_SIZE]; +} SwiP_Struct; + +#include +#include +#include + +/*! + * @brief Opaque client reference to an instance of a SwiP + * + * A SwiP_Handle returned from the ::SwiP_create represents that instance. + */ +typedef void *SwiP_Handle; + +/*! + * @brief Status codes for SwiP APIs + * TODO: See if we need more error codes. + */ +typedef enum SwiP_Status { + SwiP_OK = 0, + SwiP_FAILURE = -1 +} SwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*SwiP_Fxn)(uintptr_t arg0, uintptr_t arg1); + +/*! + * @brief Basic SwiP Parameters + * + * Structure that contains the parameters passed into ::SwiP_create + * and ::SwiP_construct when creating or constructing a SwiP instance. + * The ::SwiP_Params_init function should be used to initialize the + * fields to default values before the application sets the fields + * manually. The SwiP default parameters are noted in ::SwiP_Params_init. + * + * Each SwiP object has a "trigger" used either to determine whether to + * post the SwiP or as a value that can be evaluated within the SwiP's + * function. + * + * The SwiP_andn and SwiP_dec functions post the SwiP + * if the trigger value transitions to 0. The SwiP_or and + * SwiP_inc functions also modify the trigger value. SwiP_or + * sets bits, and SwiP_andn clears bits. + */ +typedef struct SwiP_Params { + uintptr_t arg0; /*!< Argument passed into the SwiP function. */ + uintptr_t arg1; /*!< Argument passed into the SwiP function. */ + uint32_t priority; /*!< priority, 0 is min, 1, 2, ..., ~0 for max */ + uint32_t trigger; /*!< Initial SwiP trigger value. */ +} SwiP_Params; + +/*! + * @brief Function to construct a software interrupt object. + * + * @param swiP Pointer to SwiP_Struct object. + * @param swiFxn entry function of the software interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The SwiP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A SwiP_Handle on success or a NULL on an error + */ +extern SwiP_Handle SwiP_construct(SwiP_Struct *swiP, SwiP_Fxn swiFxn, + SwiP_Params *params); + +/*! + * @brief Function to destruct a software interrupt object + * + * @param swiP Pointer to a SwiP_Struct object that was passed to + * SwiP_construct(). + * + * @return + */ +extern void SwiP_destruct(SwiP_Struct *swiP); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SwiP_Params_init(SwiP_Params *params); + +/*! + * @brief Function to create a software interrupt object. + * + * @param swiFxn entry function of the software interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The SwiP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A SwiP_Handle on success or a NULL on an error + */ +extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, + SwiP_Params *params); + +/*! + * @brief Function to delete a software interrupt object + * + * @param handle returned from the SwiP_create call + * + */ +extern void SwiP_delete(SwiP_Handle handle); + +/*! + * @brief Function to disable software interrupts + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = SwiP_disable(); + * key2 = SwiP_disable(); + * SwiP_restore(key2); + * SwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to SwiP_restore to re-enable interrupts. + */ +extern uintptr_t SwiP_disable(void); + +/*! + * @brief Function to get the trigger value of the currently running SwiP. + * + */ +extern uint32_t SwiP_getTrigger(); + +/*! + * @brief Clear bits in SwiP's trigger. Post SwiP if trigger becomes 0. + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param mask inverse value to be ANDed + */ +extern void SwiP_andn(SwiP_Handle handle, uint32_t mask); + +/*! + * @brief Decrement SwiP's trigger value. Post SwiP if trigger becomes 0. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_dec(SwiP_Handle handle); + +/*! + * @brief Increment the SwiP's trigger value and post the SwiP. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_inc(SwiP_Handle handle); + +/*! + * @brief Function to return a status based on whether it is in a + * software interrupt context. + * + * @return A status: indicating whether the function was called in a + * software interrupt routine (true) or not (false). + */ +extern bool SwiP_inISR(void); + +/*! + * @brief Or the mask with the SwiP's trigger value and post the SwiP. + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param mask value to be ORed + */ +extern void SwiP_or(SwiP_Handle handle, uint32_t mask); + +/*! + * @brief Unconditionally post a software interrupt. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_post(SwiP_Handle handle); + +/*! + * @brief Function to restore software interrupts + * + * @param key return from SwiP_disable + */ +extern void SwiP_restore(uintptr_t key); + +/*! + * @brief Function to set the priority of a software interrupt + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param priority new priority + */ +extern void SwiP_setPriority(SwiP_Handle handle, uint32_t priority); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SwiP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SystemP.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SystemP.h new file mode 100755 index 00000000000..b5aa4c1aea0 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/dpl/SystemP.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** =========================================================================== + * @file SystemP.h + * + * @brief System module for the RTOS Porting Interface + * + * Basic system services for supporting printf-like output. + * + * =========================================================================== + */ + +#ifndef ti_dpl_SystemP__include +#define ti_dpl_SystemP__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern int SystemP_snprintf(char *buf, size_t n, const char *format,...); +extern int SystemP_vsnprintf(char *buf, size_t n, const char *format, va_list va); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SemaphoreP__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/device.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/device.h new file mode 100755 index 00000000000..d897e6e7d29 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/device.h @@ -0,0 +1,731 @@ +/* + * device.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include + +#ifndef __DEVICE_H__ +#define __DEVICE_H__ + + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup Device + \short Controls the behaviour of the CC31xx/CC32xx device (start/stop, events masking and obtaining specific device status) + +*/ + +/*! + + \addtogroup Device + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ +/* Convert event id to event mask to be used in sl_DeviceEventMaskSet and sl_DeviceEventMaskGet */ +#define SL_DEVICE_EVENT_BIT(EventId) (SL_WLAN_VAL_2_MASK(EventId,1) ) + + + +typedef enum +{ + SL_DEVICE_EVENT_FATAL_DEVICE_ABORT = 1, + SL_DEVICE_EVENT_FATAL_DRIVER_ABORT, + SL_DEVICE_EVENT_FATAL_SYNC_LOSS, + SL_DEVICE_EVENT_FATAL_NO_CMD_ACK, + SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, + SL_DEVICE_EVENT_RESET_REQUEST, + SL_DEVICE_EVENT_ERROR, + SL_DEVICE_EVENT_MAX + +} SlDeviceEventId_e; + +typedef struct +{ + _i16 Status; + _u16 Caller; +}SlDeviceEventResetRequest_t; + +typedef enum +{ + SL_DEVICE_SOURCE_OTHER, + SL_DEVICE_SOURCE_WLAN, + SL_DEVICE_SOURCE_NETCFG, + SL_DEVICE_SOURCE_NETAPP, + SL_DEVICE_SOURCE_SECURITY, + + SL_DEVICE_SOURCE_LAST = 0xFF /* last one */ +}SlDeviceSource_e; + +typedef struct +{ + SlDeviceSource_e Source; + _i16 Code; +}SlDeviceEventError_t; + +typedef union +{ + SlDeviceEventResetRequest_t ResetRequest; + SlDeviceEventError_t Error; +}SlDeviceEventData_u; + + + +typedef enum +{ + SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING, + SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING_EXTERNAL_CONFIGURATION, + SL_DEVICE_RESET_REQUEST_NUM_OF_CALLERS +}SlDeviceResetRequestCaller_e; + +typedef struct +{ + _u32 Id; + SlDeviceEventData_u Data; +}SlDeviceEvent_t; + +/*! + \cond DOXYGEN_REMOVE +*/ +void slcb_DeviceEvtHdlr(SlDeviceEvent_t* pEvent); +/*! + \endcond +*/ + +typedef struct +{ + _u32 Code; + _u32 Value; +} SlDeviceFatalDeviceAssert_t; + + +typedef struct +{ + _u32 Code; +} SlDeviceFatalNoCmdAck_t, SlDeviceFatalCmdTimeout_t; + + +typedef union +{ + SlDeviceFatalDeviceAssert_t DeviceAssert; + SlDeviceFatalNoCmdAck_t NoCmdAck; + SlDeviceFatalCmdTimeout_t CmdTimeout; +}SlDeviceFatalData_u; + + +typedef struct +{ + _u32 Id; + SlDeviceFatalData_u Data; +}SlDeviceFatal_t; + + + +/* + Declare the different IDs for sl_DeviceGet and sl_DeviceSet + */ +#define SL_DEVICE_GENERAL (1) +#define SL_DEVICE_IOT (4) +#define SL_DEVICE_STATUS (2) + +/* + Declare the different Options for SL_DEVICE_GENERAL in sl_DeviceGet and sl_DeviceSet + */ +#define SL_DEVICE_GENERAL_DATE_TIME (11) +#define SL_DEVICE_GENERAL_PERSISTENT (5) +#define SL_DEVICE_GENERAL_VERSION (12) +/* + Declare the different Options for SL_DEVICE_IOT in sl_DeviceGet and sl_DeviceSet +*/ +#define SL_DEVICE_IOT_UDID (41) + +/* Events list to mask/unmask*/ +#define SL_DEVICE_EVENT_CLASS_DEVICE (1) +#define SL_DEVICE_EVENT_CLASS_WLAN (2) +#define SL_DEVICE_EVENT_CLASS_BSD (3) +#define SL_DEVICE_EVENT_CLASS_NETAPP (4) +#define SL_DEVICE_EVENT_CLASS_NETCFG (5) +#define SL_DEVICE_EVENT_CLASS_FS (6) +#define SL_DEVICE_EVENT_CLASS_NETUTIL (7) + + +/****************** DEVICE CLASS status ****************/ +#define SL_DEVICE_EVENT_DROPPED_DEVICE_ASYNC_GENERAL_ERROR (0x00000001L) +#define SL_DEVICE_STATUS_DEVICE_SMART_CONFIG_ACTIVE (0x80000000L) + +/****************** WLAN CLASS status ****************/ +#define SL_DEVICE_EVENT_DROPPED_WLAN_WLANASYNCONNECTEDRESPONSE (0x00000001L) +#define SL_DEVICE_EVENT_DROPPED_WLAN_WLANASYNCDISCONNECTEDRESPONSE (0x00000002L) +#define SL_DEVICE_EVENT_DROPPED_WLAN_STA_CONNECTED (0x00000004L) +#define SL_DEVICE_EVENT_DROPPED_WLAN_STA_DISCONNECTED (0x00000008L) +#define SL_DEVICE_EVENT_DROPPED_WLAN_P2P_DEV_FOUND (0x00000010L) +#define SL_DEVICE_EVENT_DROPPED_WLAN_CONNECTION_FAILED (0x00000020L) +#define SL_DEVICE_EVENT_DROPPED_WLAN_P2P_NEG_REQ_RECEIVED (0x00000040L) +#define SL_DEVICE_EVENT_DROPPED_WLAN_RX_FILTERS (0x00000080L) +#define SL_DEVICE_STATUS_WLAN_STA_CONNECTED (0x80000000L) + +/****************** NETAPP CLASS status ****************/ +#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPACQUIRED (0x00000001L) +#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPACQUIRED_V6 (0x00000002L) +#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_LEASED (0x00000004L) +#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_RELEASED (0x00000008L) +#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPV4_LOST (0x00000010L) +#define SL_DEVICE_EVENT_DROPPED_NETAPP_DHCP_ACQUIRE_TIMEOUT (0x00000020L) +#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_COLLISION (0x00000040L) +#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPV6_LOST (0x00000080L) + +/****************** BSD CLASS status ****************/ +#define SL_DEVICE_EVENT_DROPPED_SOCKET_TXFAILEDASYNCRESPONSE (0x00000001L) + +/****************** FS CLASS ****************/ + + + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +#ifdef SL_IF_TYPE_UART +typedef struct +{ + _u32 BaudRate; + _u8 FlowControlEnable; + _u8 CommPort; +} SlDeviceUartIfParams_t; +#endif + +#ifdef SL_IF_TYPE_UART + +#define SL_DEVICE_BAUD_9600 (9600L) +#define SL_DEVICE_BAUD_14400 (14400L) +#define SL_DEVICE_BAUD_19200 (19200L) +#define SL_DEVICE_BAUD_38400 (38400L) +#define SL_DEVICE_BAUD_57600 (57600L) +#define SL_DEVICE_BAUD_115200 (115200L) +#define SL_DEVICE_BAUD_230400 (230400L) +#define SL_DEVICE_BAUD_460800 (460800L) +#define SL_DEVICE_BAUD_921600 (921600L) + +#endif + +typedef struct +{ + _u32 ChipId; + _u8 FwVersion[4]; + _u8 PhyVersion[4]; + _u8 NwpVersion[4]; + _u16 RomVersion; + _u16 Padding; +}SlDeviceVersion_t; + + +typedef struct +{ + /* time */ + _u32 tm_sec; + _u32 tm_min; + _u32 tm_hour; + /* date */ + _u32 tm_day; /* 1-31 */ + _u32 tm_mon; /* 1-12 */ + _u32 tm_year; /* YYYY 4 digits */ + _u32 tm_week_day; /* not required */ + _u32 tm_year_day; /* not required */ + _u32 reserved[3]; +}SlDateTime_t; + + +/******************************************************************************/ +/* Type declarations */ +/******************************************************************************/ +typedef struct +{ + _u32 ChipId; + _u32 MoreData; +}SlDeviceInitInfo_t; + +typedef void (*P_INIT_CALLBACK)(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo); + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +/*! + \brief Start the SimpleLink device + + This function initialize the communication interface, set the enable pin + of the device, and call to the init complete callback. + + \param[in] pIfHdl Opened Interface Object. In case the interface + must be opened outside the SimpleLink Driver, the + user might give the handler to be used in \n + any access of the communication interface with the + device (UART/SPI). \n + The SimpleLink driver will open an interface port + only if this parameter is null! \n + \param[in] pDevName The name of the device to open. Could be used when + the pIfHdl is null, to transfer information to the + open interface function \n + This pointer could be used to pass additional information to + sl_IfOpen in case it is required (e.g. UART com port name) + \param[in] pInitCallBack Pointer to function that would be called + on completion of the initialization process.\n + If this parameter is NULL the function is + blocked until the device initialization + is completed, otherwise the function returns + immediately. + + \return Returns the current active role (STA/AP/P2P) or an error code: + - ROLE_STA, ROLE_AP, ROLE_P2P in case of success, + otherwise in failure one of the following is return: + - SL_ERROR_ROLE_STA_ERR (Failure to load MAC/PHY in STA role) + - SL_ERROR_ROLE_AP_ERR (Failure to load MAC/PHY in AP role) + - SL_ERROR_ROLE_P2P_ERR (Failure to load MAC/PHY in P2P role) + - SL_ERROR_CALIB_FAIL (Failure of calibration) + - SL_ERROR_FS_CORRUPTED_ERR (FS is corrupted, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram)) + - SL_ERROR_FS_ALERT_ERR (Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram)) + - SL_ERROR_RESTORE_IMAGE_COMPLETE (Return to factory image completed, perform reset) + - SL_ERROR_GENERAL_ERR (General error during init) + + \sa sl_Stop + + \note Belongs to \ref basic_api + + \warning This function must be called before any other SimpleLink API is used, or after sl_Stop is called for reinit the device + \par Example: + + - Open interface without callback routine. The interface name and handler are + handled by the sl_IfOpen routine: + \code + if( sl_Start(NULL, NULL, NULL) < 0 ) + { + LOG("Error opening interface to device\n"); + } + \endcode +
+ + - Open interface with a callback routine: + \code + void SimpleLinkInitCallback(_u32 status) + { + LOG("Handle SimpleLink Interface acording to ststus %d\n", status); + } + + void main(void) + { + if (sl_Start(NULL, NULL, SimpleLinkInitCallback) < 0) + { + LOG("Error opening interface to device\n"); + } + } + \endcode + +*/ +#if _SL_INCLUDE_FUNC(sl_Start) +_i16 sl_Start(const void* pIfHdl, _i8* pDevName, const P_INIT_CALLBACK pInitCallBack); +#endif + +/*! + \brief Stop the SimpleLink device + + This function clears the enable pin of the device, closes the communication \n + interface and invokes the stop complete callback + + \param[in] Timeout Stop timeout in msec. Should be used to give the device time to finish \n + any transmission/reception that is not completed when the function was called. \n + Additional options: + - 0 Enter to hibernate immediately \n + - 0xFFFF Host waits for device's response before \n + hibernating, without timeout protection \n + - 0 < Timeout[msec] < 0xFFFF Host waits for device's response before \n + hibernating, with a defined timeout protection \n + This timeout defines the max time to wait. The NWP \n + response can be sent earlier than this timeout. + + \return Zero on success, or a negative value if an error occurred + + \sa sl_Start + + \note This API will shutdown the device and invoke the "i/f close" function regardless \n + if it was opened implicitly or explicitly. \n + It is up to the platform interface library to properly handle interface close \n + routine \n + Belongs to \ref basic_api \n + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Stop) +_i16 sl_Stop(const _u16 Timeout); +#endif + + +/*! + \brief Setting device configurations + + \param[in] DeviceSetId configuration id: + - SL_DEVICE_GENERAL + + \param[in] Option configurations option: + - SL_DEVICE_GENERAL_DATE_TIME + - SL_DEVICE_GENERAL_PERSISTENT + \param[in] ConfigLen configurations len + \param[in] pValues configurations values + + \return Zero on success, or a negative value if an error occurred + \par Persistent + SL_DEVICE_GENERAL_DATE_TIME - System Persistent (kept during hibernate only, See Note for details) \n + SL_DEVICE_GENERAL_PERSISTENT - Persistent + \sa + \note Persistency for SL_DEVICE_GENERAL_DATE_TIME - The original setted value will be kept as System Persistence.\n + The updated date and time though, will be kept during hibernate only. + \warning + \par Examples: + + - Setting device time and date example: + \code + SlDateTime_t dateTime= {0}; + dateTime.tm_day = (_u32)23; // Day of month (DD format) range 1-31 + dateTime.tm_mon = (_u32)6; // Month (MM format) in the range of 1-12 + dateTime.tm_year = (_u32)2014; // Year (YYYY format) + dateTime.tm_hour = (_u32)17; // Hours in the range of 0-23 + dateTime.tm_min = (_u32)55; // Minutes in the range of 0-59 + dateTime.tm_sec = (_u32)22; // Seconds in the range of 0-59 + sl_DeviceSet(SL_DEVICE_GENERAL, + SL_DEVICE_GENERAL_DATE_TIME, + sizeof(SlDateTime_t), + (_u8 *)(&dateTime)); + \endcode +
+ + - Setting system persistent configuration:
+ Sets the default system-wide configuration persistence mode. + In case true, all APIs that follow 'system configured' persistence (see persistence attribute noted per API) shall maintain the configured settings. + In case false, all calls to APIs that follow 'system configured' persistence shall be volatile. Configuration should revert to default after reset or power recycle + \code + _u8 persistent = 1; + sl_DeviceSet(SL_DEVICE_GENERAL, + SL_DEVICE_GENERAL_PERSISTENT, + sizeof(_u8), + (_u8 *)(&persistent)); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_DeviceSet) +_i16 sl_DeviceSet(const _u8 DeviceSetId ,const _u8 Option,const _u16 ConfigLen,const _u8 *pValues); +#endif + +/*! + \brief Internal function for getting device configurations + \param[in] DeviceGetId configuration id: + - SL_DEVICE_STATUS + - SL_DEVICE_GENERAL + - SL_DEVICE_IOT + + \param[out] pOption Get configurations option: + - SL_DEVICE_STATUS: + - SL_DEVICE_EVENT_CLASS_DEVICE + - SL_DEVICE_EVENT_CLASS_WLAN + - SL_DEVICE_EVENT_CLASS_BSD + - SL_DEVICE_EVENT_CLASS_NETAPP + - SL_DEVICE_EVENT_CLASS_NETCFG + - SL_DEVICE_EVENT_CLASS_FS + - SL_DEVICE_GENERAL: + - SL_DEVICE_GENERAL_VERSION + - SL_DEVICE_GENERAL_DATE_TIME + - SL_DEVICE_GENERAL_PERSISTENT + - SL_DEVICE_IOT: + - SL_DEVICE_IOT_UDID + + \param[out] pConfigLen The length of the allocated memory as input, when the + function complete, the value of this parameter would be + the len that actually read from the device.\n + If the device return length that is longer from the input + value, the function will cut the end of the returned structure + and will return SL_ESMALLBUF + \param[out] pValues Get requested configurations values + \return Zero on success, or a negative value if an error occurred + \sa + \note + \warning + \par Examples + + - Getting WLAN class status (status is always cleared on read): + \code + _u32 statusWlan; + _u8 pConfigOpt; + _u16 pConfigLen; + pConfigOpt = SL_DEVICE_EVENT_CLASS_WLAN; + pConfigLen = sizeof(_u32); + sl_DeviceGet(SL_DEVICE_STATUS,&pConfigOpt,&pConfigLen,(_u8 *)(&statusWlan)); + if (SL_DEVICE_STATUS_WLAN_STA_CONNECTED & statusWlan ) + { + printf("Device is connected\n"); + } + if (SL_DEVICE_EVENT_DROPPED_WLAN_RX_FILTERS & statusWlan ) + { + printf("RX filer event dropped\n"); + } + + \endcode +
+ + - Getting version: + \code + SlDeviceVersion_t ver; + pConfigLen = sizeof(ver); + pConfigOpt = SL_DEVICE_GENERAL_VERSION; + sl_DeviceGet(SL_DEVICE_GENERAL,&pConfigOpt,&pConfigLen,(_u8 *)(&ver)); + printf("CHIP %d\nMAC 31.%d.%d.%d.%d\nPHY %d.%d.%d.%d\nNWP %d.%d.%d.%d\nROM %d\nHOST %d.%d.%d.%d\n", + ver.ChipId, + ver.FwVersion[0],ver.FwVersion[1], + ver.FwVersion[2],ver.FwVersion[3], + ver.PhyVersion[0],ver.PhyVersion[1], + ver.PhyVersion[2],ver.PhyVersion[3], + ver.NwpVersion[0],ver.NwpVersion[1],ver.NwpVersion[2],ver.NwpVersion[3], + ver.RomVersion, + SL_MAJOR_VERSION_NUM,SL_MINOR_VERSION_NUM,SL_VERSION_NUM,SL_SUB_VERSION_NUM); + + \endcode +
+ + - Getting Device time and date: + \code + SlDateTime_t dateTime = {0}; + _i16 configLen = sizeof(SlDateTime_t); + _i8 configOpt = SL_DEVICE_GENERAL_DATE_TIME; + sl_DeviceGet(SL_DEVICE_GENERAL,&configOpt, &configLen,(_u8 *)(&dateTime)); + + printf("Day %d,Mon %d,Year %d,Hour %,Min %d,Sec %d\n",dateTime.tm_day,dateTime.tm_mon,dateTime.tm_year, + dateTime.tm_hour,dateTime.tm_min,dateTime.tm_sec); + \endcode + + - Getting persistency system configuration: + \code + _i16 configLen = sizeof(_u8); + _i8 configOpt = SL_DEVICE_GENERAL_PERSISTENT; + sl_DeviceGet(SL_DEVICE_GENERAL,&configOpt, &configLen,&persistent); + \endcode + +*/ +#if _SL_INCLUDE_FUNC(sl_DeviceGet) +_i16 sl_DeviceGet(const _u8 DeviceGetId, _u8 *pOption,_u16 *pConfigLen, _u8 *pValues); +#endif + + +/*! + \brief Set asynchronous event mask + + Mask asynchronous events from the device.\n + Masked events do not generate asynchronous messages from the device.\n + By default - all events are active + + + + \param[in] EventClass The classification groups that the + mask is referred to. Need to be one of + the following: + - SL_DEVICE_EVENT_CLASS_DEVICE + - SL_DEVICE_EVENT_CLASS_WLAN + - SL_DEVICE_EVENT_CLASS_BSD + - SL_DEVICE_EVENT_CLASS_NETAPP + - SL_DEVICE_EVENT_CLASS_NETCFG + - SL_DEVICE_EVENT_CLASS_FS + + + \param[in] Mask Event Mask bitmap. Valid mask are (per group): + - SL_DEVICE_EVENT_CLASS_WLAN user events + - SL_WLAN_EVENT_CONNECT + - SL_WLAN_EVENT_P2P_CONNECT + - SL_WLAN_EVENT_DISCONNECT + - SL_WLAN_EVENT_P2P_DISCONNECT + - SL_WLAN_EVENT_STA_ADDED + - SL_WLAN_EVENT_STA_REMOVED + - SL_WLAN_EVENT_P2P_CLIENT_ADDED + - SL_WLAN_EVENT_P2P_CLIENT_REMOVED + - SL_WLAN_EVENT_P2P_DEVFOUND + - SL_WLAN_EVENT_P2P_REQUEST + - SL_WLAN_EVENT_P2P_CONNECTFAIL + - SL_WLAN_EVENT_PROVISIONING_STATUS + - SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED + - SL_WLAN_EVENT_RXFILTER + + - SL_DEVICE_EVENT_CLASS_DEVICE user events + - SL_DEVICE_EVENT_ERROR + + - SL_DEVICE_EVENT_CLASS_BSD user events + - SL_SOCKET_TX_FAILED_EVENT + - SL_SOCKET_ASYNC_EVENT + + - SL_DEVICE_EVENT_CLASS_NETAPP user events + - SL_NETAPP_EVENT_IPV4_ACQUIRED + - SL_NETAPP_EVENT_IPV6_ACQUIRED + - SL_NETAPP_EVENT_DHCPV4_LEASED + - SL_NETAPP_EVENT_DHCPV4_RELEASED + - SL_NETAPP_EVENT_IP_COLLISION + - SL_NETAPP_EVENT_IPV4_LOST + - SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT + - SL_NETAPP_EVENT_IPV6_LOST + + + \return Zero on success, or a negative value if an error occurred + \par Persistent System Persistent + \sa sl_DeviceEventMaskGet + + \note Belongs to \ref ext_api \n + \warning + \par Example + + - Masking connection/disconnection async events from WLAN class: + \code + sl_DeviceEventMaskSet(SL_DEVICE_EVENT_CLASS_WLAN, (SL_DEVICE_EVENT_BIT(SL_WLAN_EVENT_CONNECT) | SL_DEVICE_EVENT_BIT(SL_WLAN_EVENT_DISCONNECT) ) ); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskSet) +_i16 sl_DeviceEventMaskSet(const _u8 EventClass ,const _u32 Mask); +#endif + +/*! + \brief Get current event mask of the device + + Return the events bit mask from the device. In case event is + masked, the device will not send that event. + + \param[in] EventClass The classification groups that the + mask is referred to. Need to be one of + the following: + - SL_DEVICE_EVENT_CLASS_GLOBAL + - SL_DEVICE_EVENT_CLASS_DEVICE + - SL_DEVICE_EVENT_CLASS_WLAN + - SL_DEVICE_EVENT_CLASS_BSD + - SL_DEVICE_EVENT_CLASS_NETAPP + - SL_DEVICE_EVENT_CLASS_NETCFG + - SL_DEVICE_EVENT_CLASS_FS + + \param[out] pMask Pointer to mask bitmap where the + value should be stored. Bitmasks are the same as in \ref sl_DeviceEventMaskSet + + \return Zero on success, or a negative value if an error occurred + + \sa sl_DeviceEventMaskSet + + \note Belongs to \ref ext_api + + \warning + \par Example + + - Getting an event mask for WLAN class: + \code + _u32 maskWlan; + sl_DeviceEventMaskGet(SL_DEVICE_EVENT_CLASS_WLAN,&maskWlan); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskGet) +_i16 sl_DeviceEventMaskGet(const _u8 EventClass,_u32 *pMask); +#endif + + +/*! + \brief The SimpleLink task entry + + This function must be called from the main loop or from dedicated thread in + the following cases: + - Non-Os Platform - should be called from the mail loop + - Multi Threaded Platform when the user does not implement the external spawn functions - + should be called from dedicated thread allocated to the SimpleLink driver. + In this mode the function never return. + + \par parameters + None + + \return None + \sa + \note Belongs to \ref basic_api + + \warning This function must be called from a thread that is start running before + any call to other SimpleLink API +*/ +#if _SL_INCLUDE_FUNC(sl_Task) +void* sl_Task(void* pEntry); +#endif + + + + +/*! + \brief Setting the internal uart mode + + \param[in] pUartParams Pointer to the uart configuration parameter set: + - baudrate - up to 711 Kbps + - flow control - enable/disable + - comm port - the comm port number + + \return On success zero is returned, otherwise - Failed. + \par Persistent Non- Persistent + \sa + \note Belongs to \ref basic_api + + \warning This function must consider the host uart capability +*/ +#ifdef SL_IF_TYPE_UART +#if _SL_INCLUDE_FUNC(sl_DeviceUartSetMode) +_i16 sl_DeviceUartSetMode(const SlDeviceUartIfParams_t* pUartParams); +#endif +#endif + +/*! + + Close the Doxygen group. + @} + + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __DEVICE_H__ */ + + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/errors.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/errors.h new file mode 100755 index 00000000000..a9ab823a168 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/errors.h @@ -0,0 +1,736 @@ +/* + * errors.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +#ifndef __ERROR_H__ +#define __ERROR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + + +#define SL_RET_CODE_OK (0L) /* Success */ + +#define SL_ERROR_GENERAL_DEVICE (-6L) /* General device error */ + +/* BSD SOCKET ERRORS CODES */ + +#define SL_ERROR_BSD_SOC_ERROR (-1L) /* Failure */ +#define SL_ERROR_BSD_EINTR (-4L) /* Interrupted system call */ +#define SL_ERROR_BSD_E2BIG (-7L) /* length too big */ +#define SL_ERROR_BSD_INEXE (-8L) /* socket command in execution */ +#define SL_ERROR_BSD_EBADF (-9L) /* Bad file number */ +#define SL_ERROR_BSD_ENSOCK (-10L) /* The system limit on the total number of open socket, has been reached */ +#define SL_ERROR_BSD_EAGAIN (-11L) /* Try again */ +#define SL_ERROR_BSD_EWOULDBLOCK SL_ERROR_BSD_EAGAIN +#define SL_ERROR_BSD_ENOMEM (-12L) /* Out of memory */ +#define SL_ERROR_BSD_EACCES (-13L) /* Permission denied */ +#define SL_ERROR_BSD_EFAULT (-14L) /* Bad address */ +#define SL_ERROR_BSD_ECLOSE (-15L) /* close socket operation failed to transmit all queued packets */ +#define SL_ERROR_BSD_EALREADY_ENABLED (-21L) /* Transceiver - Transceiver already ON. there could be only one */ +#define SL_ERROR_BSD_EINVAL (-22L) /* Invalid argument */ +#define SL_ERROR_BSD_EAUTO_CONNECT_OR_CONNECTING (-69L) /* Transceiver - During connection, connected or auto mode started */ +#define SL_ERROR_BSD_CONNECTION_PENDING (-72L) /* Transceiver - Device is connected, disconnect first to open transceiver */ +#define SL_ERROR_BSD_EUNSUPPORTED_ROLE (-86L) /* Transceiver - Trying to start when WLAN role is AP or P2P GO */ +#define SL_ERROR_BSD_EDESTADDRREQ (-89L) /* Destination address required */ +#define SL_ERROR_BSD_EPROTOTYPE (-91L) /* Protocol wrong type for socket */ +#define SL_ERROR_BSD_ENOPROTOOPT (-92L) /* Protocol not available */ +#define SL_ERROR_BSD_EPROTONOSUPPORT (-93L) /* Protocol not supported */ +#define SL_ERROR_BSD_ESOCKTNOSUPPORT (-94L) /* Socket type not supported */ +#define SL_ERROR_BSD_EOPNOTSUPP (-95L) /* Operation not supported on transport endpoint */ +#define SL_ERROR_BSD_EAFNOSUPPORT (-97L) /* Address family not supported by protocol */ +#define SL_ERROR_BSD_EADDRINUSE (-98L) /* Address already in use */ +#define SL_ERROR_BSD_EADDRNOTAVAIL (-99L) /* Cannot assign requested address */ +#define SL_ERROR_BSD_ENETUNREACH (-101L) /* Network is unreachable */ +#define SL_ERROR_BSD_ENOBUFS (-105L) /* No buffer space available */ +#define SL_ERROR_BSD_EOBUFF SL_ENOBUFS +#define SL_ERROR_BSD_EISCONN (-106L) /* Transport endpoint is already connected */ +#define SL_ERROR_BSD_ENOTCONN (-107L) /* Transport endpoint is not connected */ +#define SL_ERROR_BSD_ETIMEDOUT (-110L) /* Connection timed out */ +#define SL_ERROR_BSD_ECONNREFUSED (-111L) /* Connection refused */ +#define SL_ERROR_BSD_EALREADY (-114L) /* Non blocking connect in progress, try again */ + +/* ssl tls security start with -300 offset */ +#define SL_ERROR_BSD_ESEC_CLOSE_NOTIFY (-300L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_UNEXPECTED_MESSAGE (-310L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_BAD_RECORD_MAC (-320L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_DECRYPTION_FAILED (-321L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_RECORD_OVERFLOW (-322L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_DECOMPRESSION_FAILURE (-330L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_HANDSHAKE_FAILURE (-340L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_NO_CERTIFICATE (-341L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE (-342L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_UNSUPPORTED_CERTIFICATE (-343L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_CERTIFICATE_REVOKED (-344L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_CERTIFICATE_EXPIRED (-345L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_CERTIFICATE_UNKNOWN (-346L) /* ssl/tls alerts */ + +#define SL_ERROR_BSD_ESEC_ILLEGAL_PARAMETER (-347L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_ACCESS_DENIED (-349L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_DECODE_ERROR (-350L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_DECRYPT_ERROR1 (-351L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_EXPORT_RESTRICTION (-360L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_PROTOCOL_VERSION (-370L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_INSUFFICIENT_SECURITY (-371L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_INTERNAL_ERROR (-380L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_USER_CANCELLED (-390L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_NO_RENEGOTIATION (-400L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_UNSUPPORTED_EXTENSION (-410L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_CERTIFICATE_UNOBTAINABLE (-411L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_UNRECOGNIZED_NAME (-412L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE_STATUS_RESPONSE (-413L) /* ssl/tls alerts */ +#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE_HASH_VALUE (-414L) /* ssl/tls alerts */ +/* propriety secure */ +#define SL_ERROR_BSD_ESECGENERAL (-450L) /* error secure level general error */ +#define SL_ERROR_BSD_ESECDECRYPT (-451L) /* error secure level, decrypt recv packet fail */ +#define SL_ERROR_BSD_ESECCLOSED (-452L) /* secure layrer is closed by other size , tcp is still connected */ +#define SL_ERROR_BSD_ESECSNOVERIFY (-453L) /* Connected without server verification */ +#define SL_ERROR_BSD_ESECNOCAFILE (-454L) /* error secure level CA file not found*/ +#define SL_ERROR_BSD_ESECMEMORY (-455L) /* error secure level No memory space available */ +#define SL_ERROR_BSD_ESECBADCAFILE (-456L) /* error secure level bad CA file */ +#define SL_ERROR_BSD_ESECBADCERTFILE (-457L) /* error secure level bad Certificate file */ +#define SL_ERROR_BSD_ESECBADPRIVATEFILE (-458L) /* error secure level bad private file */ +#define SL_ERROR_BSD_ESECBADDHFILE (-459L) /* error secure level bad DH file */ +#define SL_ERROR_BSD_ESECT00MANYSSLOPENED (-460L) /* MAX SSL Sockets are opened */ +#define SL_ERROR_BSD_ESECDATEERROR (-461L) /* connected with certificate date verification error */ +#define SL_ERROR_BSD_ESECHANDSHAKETIMEDOUT (-462L) /* connection timed out due to handshake time */ +#define SL_ERROR_BSD_ESECTXBUFFERNOTEMPTY (-463L) /* cannot start ssl connection while send buffer is full */ +#define SL_ERROR_BSD_ESECRXBUFFERNOTEMPTY (-464L) /* cannot start ssl connection while recv buffer is full */ +#define SL_ERROR_BSD_ESECSSLDURINGHANDSHAKE (-465L) /* cannot use while in hanshaking */ +#define SL_ERROR_BSD_ESECNOTALLOWEDWHENLISTENING (-466L) /* the operation is not allowed when listening, do before listen*/ +#define SL_ERROR_BSD_ESECCERTIFICATEREVOKED (-467L) /* connected but on of the certificates in the chain is revoked */ +#define SL_ERROR_BSD_ESECUNKNOWNROOTCA (-468L) /* connected but the root CA used to validate the peer is unknown */ +#define SL_ERROR_BSD_ESECWRONGPEERCERT (-469L) /* wrong peer cert (server cert) was received while trying to connect to server */ +#define SL_ERROR_BSD_ESECTCPDISCONNECTEDUNCOMPLETERECORD (-470L) /* the other side disconnected the TCP layer and didn't send the whole ssl record */ + +#define SL_ERROR_BSD_ESEC_BUFFER_E (-632L) /* output buffer too small or input too large */ +#define SL_ERROR_BSD_ESEC_ALGO_ID_E (-633L) /* setting algo id error */ +#define SL_ERROR_BSD_ESEC_PUBLIC_KEY_E (-634L) /* setting public key error */ +#define SL_ERROR_BSD_ESEC_DATE_E (-635L) /* setting date validity error */ +#define SL_ERROR_BSD_ESEC_SUBJECT_E (-636L) /* setting subject name error */ +#define SL_ERROR_BSD_ESEC_ISSUER_E (-637L) /* setting issuer name error */ +#define SL_ERROR_BSD_ESEC_CA_TRUE_E (-638L) /* setting CA basic constraint true error */ +#define SL_ERROR_BSD_ESEC_EXTENSIONS_E (-639L) /* setting extensions error */ +#define SL_ERROR_BSD_ESEC_ASN_PARSE_E (-640L) /* ASN parsing error, invalid input */ +#define SL_ERROR_BSD_ESEC_ASN_VERSION_E (-641L) /* ASN version error, invalid number */ +#define SL_ERROR_BSD_ESEC_ASN_GETINT_E (-642L) /* ASN get big int error, invalid data */ +#define SL_ERROR_BSD_ESEC_ASN_RSA_KEY_E (-643L) /* ASN key init error, invalid input */ +#define SL_ERROR_BSD_ESEC_ASN_OBJECT_ID_E (-644L) /* ASN object id error, invalid id */ +#define SL_ERROR_BSD_ESEC_ASN_TAG_NULL_E (-645L) /* ASN tag error, not null */ +#define SL_ERROR_BSD_ESEC_ASN_EXPECT_0_E (-646L) /* ASN expect error, not zero */ +#define SL_ERROR_BSD_ESEC_ASN_BITSTR_E (-647L) /* ASN bit string error, wrong id */ +#define SL_ERROR_BSD_ESEC_ASN_UNKNOWN_OID_E (-648L) /* ASN oid error, unknown sum id */ +#define SL_ERROR_BSD_ESEC_ASN_DATE_SZ_E (-649L) /* ASN date error, bad size */ +#define SL_ERROR_BSD_ESEC_ASN_BEFORE_DATE_E (-650L) /* ASN date error, current date before */ +#define SL_ERROR_BSD_ESEC_ASN_AFTER_DATE_E (-651L) /* ASN date error, current date after */ +#define SL_ERROR_BSD_ESEC_ASN_SIG_OID_E (-652L) /* ASN signature error, mismatched oid */ +#define SL_ERROR_BSD_ESEC_ASN_TIME_E (-653L) /* ASN time error, unknown time type */ +#define SL_ERROR_BSD_ESEC_ASN_INPUT_E (-654L) /* ASN input error, not enough data */ +#define SL_ERROR_BSD_ESEC_ASN_SIG_CONFIRM_E (-655L) /* ASN sig error, confirm failure */ +#define SL_ERROR_BSD_ESEC_ASN_SIG_HASH_E (-656L) /* ASN sig error, unsupported hash type */ +#define SL_ERROR_BSD_ESEC_ASN_SIG_KEY_E (-657L) /* ASN sig error, unsupported key type */ +#define SL_ERROR_BSD_ESEC_ASN_DH_KEY_E (-658L) /* ASN key init error, invalid input */ +#define SL_ERROR_BSD_ESEC_ASN_NTRU_KEY_E (-659L) /* ASN ntru key decode error, invalid input */ +#define SL_ERROR_BSD_ESEC_ASN_CRIT_EXT_E (-660L) /* ASN unsupported critical extension */ +#define SL_ERROR_BSD_ESEC_ECC_BAD_ARG_E (-670L) /* ECC input argument of wrong type */ +#define SL_ERROR_BSD_ESEC_ASN_ECC_KEY_E (-671L) /* ASN ECC bad input */ +#define SL_ERROR_BSD_ESEC_ECC_CURVE_OID_E (-672L) /* Unsupported ECC OID curve type */ +#define SL_ERROR_BSD_ESEC_BAD_FUNC_ARG (-673L) /* Bad function argument provided */ +#define SL_ERROR_BSD_ESEC_NOT_COMPILED_IN (-674L) /* Feature not compiled in */ +#define SL_ERROR_BSD_ESEC_UNICODE_SIZE_E (-675L) /* Unicode password too big */ +#define SL_ERROR_BSD_ESEC_NO_PASSWORD (-676L) /* no password provided by user */ +#define SL_ERROR_BSD_ESEC_ALT_NAME_E (-677L) /* alt name size problem, too big */ +#define SL_ERROR_BSD_ESEC_ASN_NO_SIGNER_E (-688L) /* ASN no signer to confirm failure */ +#define SL_ERROR_BSD_ESEC_ASN_CRL_CONFIRM_E (-689L) /* ASN CRL signature confirm failure */ +#define SL_ERROR_BSD_ESEC_ASN_CRL_NO_SIGNER_E (-690L) /* ASN CRL no signer to confirm failure */ +#define SL_ERROR_BSD_ESEC_ASN_OCSP_CONFIRM_E (-691L) /* ASN OCSP signature confirm failure */ +#define SL_ERROR_BSD_ESEC_VERIFY_FINISHED_ERROR (-704L) /* verify problem on finished */ +#define SL_ERROR_BSD_ESEC_VERIFY_MAC_ERROR (-705L) /* verify mac problem */ +#define SL_ERROR_BSD_ESEC_PARSE_ERROR (-706L) /* parse error on header */ +#define SL_ERROR_BSD_ESEC_UNKNOWN_HANDSHAKE_TYPE (-707L) /* weird handshake type */ +#define SL_ERROR_BSD_ESEC_SOCKET_ERROR_E (-708L) /* error state on socket */ +#define SL_ERROR_BSD_ESEC_SOCKET_NODATA (-709L) /* expected data, not there */ +#define SL_ERROR_BSD_ESEC_INCOMPLETE_DATA (-710L) /* don't have enough data to complete task */ +#define SL_ERROR_BSD_ESEC_UNKNOWN_RECORD_TYPE (-711L) /* unknown type in record hdr */ +#define SL_ERROR_BSD_ESEC_INNER_DECRYPT_ERROR (-712L) /* error during decryption */ +#define SL_ERROR_BSD_ESEC_FATAL_ERROR (-713L) /* recvd alert fatal error */ +#define SL_ERROR_BSD_ESEC_ENCRYPT_ERROR (-714L) /* error during encryption */ +#define SL_ERROR_BSD_ESEC_FREAD_ERROR (-715L) /* fread problem */ +#define SL_ERROR_BSD_ESEC_NO_PEER_KEY (-716L) /* need peer's key */ +#define SL_ERROR_BSD_ESEC_NO_PRIVATE_KEY (-717L) /* need the private key */ +#define SL_ERROR_BSD_ESEC_RSA_PRIVATE_ERROR (-718L) /* error during rsa priv op */ +#define SL_ERROR_BSD_ESEC_NO_DH_PARAMS (-719L) /* server missing DH params */ +#define SL_ERROR_BSD_ESEC_BUILD_MSG_ERROR (-720L) /* build message failure */ +#define SL_ERROR_BSD_ESEC_BAD_HELLO (-721L) /* client hello malformed */ +#define SL_ERROR_BSD_ESEC_DOMAIN_NAME_MISMATCH (-722L) /* peer subject name mismatch */ +#define SL_ERROR_BSD_ESEC_WANT_READ (-723L) /* want read, call again */ +#define SL_ERROR_BSD_ESEC_NOT_READY_ERROR (-724L) /* handshake layer not ready */ +#define SL_ERROR_BSD_ESEC_PMS_VERSION_ERROR (-725L) /* pre m secret version error */ +#define SL_ERROR_BSD_ESEC_WANT_WRITE (-727L) /* want write, call again */ +#define SL_ERROR_BSD_ESEC_BUFFER_ERROR (-728L) /* malformed buffer input */ +#define SL_ERROR_BSD_ESEC_VERIFY_CERT_ERROR (-729L) /* verify cert error */ +#define SL_ERROR_BSD_ESEC_VERIFY_SIGN_ERROR (-730L) /* verify sign error */ +#define SL_ERROR_BSD_ESEC_LENGTH_ERROR (-741L) /* record layer length error */ +#define SL_ERROR_BSD_ESEC_PEER_KEY_ERROR (-742L) /* can't decode peer key */ +#define SL_ERROR_BSD_ESEC_ZERO_RETURN (-743L) /* peer sent close notify */ +#define SL_ERROR_BSD_ESEC_SIDE_ERROR (-744L) /* wrong client/server type */ +#define SL_ERROR_BSD_ESEC_NO_PEER_CERT (-745L) /* peer didn't send key */ +#define SL_ERROR_BSD_ESEC_ECC_CURVETYPE_ERROR (-750L) /* Bad ECC Curve Type */ +#define SL_ERROR_BSD_ESEC_ECC_CURVE_ERROR (-751L) /* Bad ECC Curve */ +#define SL_ERROR_BSD_ESEC_ECC_PEERKEY_ERROR (-752L) /* Bad Peer ECC Key */ +#define SL_ERROR_BSD_ESEC_ECC_MAKEKEY_ERROR (-753L) /* Bad Make ECC Key */ +#define SL_ERROR_BSD_ESEC_ECC_EXPORT_ERROR (-754L) /* Bad ECC Export Key */ +#define SL_ERROR_BSD_ESEC_ECC_SHARED_ERROR (-755L) /* Bad ECC Shared Secret */ +#define SL_ERROR_BSD_ESEC_NOT_CA_ERROR (-757L) /* Not a CA cert error */ +#define SL_ERROR_BSD_ESEC_BAD_PATH_ERROR (-758L) /* Bad path for opendir */ +#define SL_ERROR_BSD_ESEC_BAD_CERT_MANAGER_ERROR (-759L) /* Bad Cert Manager */ +#define SL_ERROR_BSD_ESEC_OCSP_CERT_REVOKED (-760L) /* OCSP Certificate revoked */ +#define SL_ERROR_BSD_ESEC_CRL_CERT_REVOKED (-761L) /* CRL Certificate revoked */ +#define SL_ERROR_BSD_ESEC_CRL_MISSING (-762L) /* CRL Not loaded */ +#define SL_ERROR_BSD_ESEC_MONITOR_RUNNING_E (-763L) /* CRL Monitor already running */ +#define SL_ERROR_BSD_ESEC_THREAD_CREATE_E (-764L) /* Thread Create Error */ +#define SL_ERROR_BSD_ESEC_OCSP_NEED_URL (-765L) /* OCSP need an URL for lookup */ +#define SL_ERROR_BSD_ESEC_OCSP_CERT_UNKNOWN (-766L) /* OCSP responder doesn't know */ +#define SL_ERROR_BSD_ESEC_OCSP_LOOKUP_FAIL (-767L) /* OCSP lookup not successful */ +#define SL_ERROR_BSD_ESEC_MAX_CHAIN_ERROR (-768L) /* max chain depth exceeded */ +#define SL_ERROR_BSD_ESEC_NO_PEER_VERIFY (-778L) /* Need peer cert verify Error */ +#define SL_ERROR_BSD_ESEC_UNSUPPORTED_SUITE (-790L) /* unsupported cipher suite */ +#define SL_ERROR_BSD_ESEC_MATCH_SUITE_ERROR (-791L) /* can't match cipher suite */ + + +/* WLAN ERRORS CODES*/ +#define SL_ERROR_WLAN_KEY_ERROR (-2049L) +#define SL_ERROR_WLAN_INVALID_ROLE (-2050L) +#define SL_ERROR_WLAN_PREFERRED_NETWORKS_FILE_LOAD_FAILED (-2051L) +#define SL_ERROR_WLAN_CANNOT_CONFIG_SCAN_DURING_PROVISIONING (-2052L) +#define SL_ERROR_WLAN_INVALID_SECURITY_TYPE (-2054L) +#define SL_ERROR_WLAN_PASSPHRASE_TOO_LONG (-2055L) +#define SL_ERROR_WLAN_EAP_WRONG_METHOD (-2057L) +#define SL_ERROR_WLAN_PASSWORD_ERROR (-2058L) +#define SL_ERROR_WLAN_EAP_ANONYMOUS_LEN_ERROR (-2059L) +#define SL_ERROR_WLAN_SSID_LEN_ERROR (-2060L) +#define SL_ERROR_WLAN_USER_ID_LEN_ERROR (-2061L) +#define SL_ERROR_WLAN_PREFERRED_NETWORK_LIST_FULL (-2062L) +#define SL_ERROR_WLAN_PREFERRED_NETWORKS_FILE_WRITE_FAILED (-2063L) +#define SL_ERROR_WLAN_ILLEGAL_WEP_KEY_INDEX (-2064L) +#define SL_ERROR_WLAN_INVALID_DWELL_TIME_VALUES (-2065L) +#define SL_ERROR_WLAN_INVALID_POLICY_TYPE (-2066L) +#define SL_ERROR_WLAN_PM_POLICY_INVALID_OPTION (-2067L) +#define SL_ERROR_WLAN_PM_POLICY_INVALID_PARAMS (-2068L) +#define SL_ERROR_WLAN_WIFI_NOT_CONNECTED (-2069L) +#define SL_ERROR_WLAN_ILLEGAL_CHANNEL (-2070L) +#define SL_ERROR_WLAN_WIFI_ALREADY_DISCONNECTED (-2071L) +#define SL_ERROR_WLAN_TRANSCEIVER_ENABLED (-2072L) +#define SL_ERROR_WLAN_GET_NETWORK_LIST_EAGAIN (-2073L) +#define SL_ERROR_WLAN_GET_PROFILE_INVALID_INDEX (-2074L) +#define SL_ERROR_WLAN_FAST_CONN_DATA_INVALID (-2075L) +#define SL_ERROR_WLAN_NO_FREE_PROFILE (-2076L) +#define SL_ERROR_WLAN_AP_SCAN_INTERVAL_TOO_LOW (-2077L) +#define SL_ERROR_WLAN_SCAN_POLICY_INVALID_PARAMS (-2078L) + +#define SL_RXFL_OK (0L) /* O.K */ +#define SL_ERROR_RXFL_RANGE_COMPARE_PARAMS_ARE_INVALID (-2079L) +#define SL_ERROR_RXFL_RXFL_INVALID_PATTERN_LENGTH (-2080L) /* requested length for L1/L4 payload matching must not exceed 16 bytes */ +#define SL_ERROR_RXFL_ACTION_USER_EVENT_ID_TOO_BIG (-2081L) /* user action id for host event must not exceed SL_WLAN_RX_FILTER_MAX_USER_EVENT_ID */ +#define SL_ERROR_RXFL_OFFSET_TOO_BIG (-2082L) /* requested offset for L1/L4 payload matching must not exceed 1535 bytes */ +#define SL_ERROR_RXFL_STAT_UNSUPPORTED (-2083L) /* get rx filters statistics not supported */ +#define SL_ERROR_RXFL_INVALID_FILTER_ARG_UPDATE (-2084L) /* invalid filter args request */ +#define SL_ERROR_RXFL_INVALID_SYSTEM_STATE_TRIGGER_FOR_FILTER_TYPE (-2085L) /* system state not supported for this filter type */ +#define SL_ERROR_RXFL_INVALID_FUNC_ID_FOR_FILTER_TYPE (-2086L) /* function id not supported for this filter type */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_3 (-2087L) /* filter parent doesn't exist */ +#define SL_ERROR_RXFL_OUTPUT_OR_INPUT_BUFFER_LENGTH_TOO_SMALL (-2088L) /* ! The output buffer length is smaller than required for that operation */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_SOFTWARE_FILTER_NOT_FIT (-2089L) /* Node filter can't be child of software filter and vice_versa */ +#define SL_ERROR_RXFL_DEPENDENCY_IS_NOT_PERSISTENT (-2090L) /* Dependency filter is not persistent */ +#define SL_ERROR_RXFL_RXFL_ALLOCATION_PROBLEM (-2091L) +#define SL_ERROR_RXFL_SYSTEM_STATE_NOT_SUPPORTED_FOR_THIS_FILTER (-2092L) /* System state is not supported */ +#define SL_ERROR_RXFL_TRIGGER_USE_REG5_TO_REG8 (-2093L) /* Only counters 5 - 8 are allowed, for Tigger */ +#define SL_ERROR_RXFL_TRIGGER_USE_REG1_TO_REG4 (-2094L) /* Only counters 1 - 4 are allowed, for trigger */ +#define SL_ERROR_RXFL_ACTION_USE_REG5_TO_REG8 (-2095L) /* Only counters 5 - 8 are allowed, for action */ +#define SL_ERROR_RXFL_ACTION_USE_REG1_TO_REG4 (-2096L) /* Only counters 1 - 4 are allowed, for action */ +#define SL_ERROR_RXFL_FIELD_SUPPORT_ONLY_EQUAL_AND_NOTEQUAL (-2097L) /* Rule compare function Id is out of range */ +#define SL_ERROR_RXFL_WRONG_MULTICAST_BROADCAST_ADDRESS (-2098L) /* The address should be of type mutlicast or broadcast */ +#define SL_ERROR_RXFL_THE_FILTER_IS_NOT_OF_HEADER_TYPE (-2099L) /* The filter should be of header type */ +#define SL_ERROR_RXFL_WRONG_COMPARE_FUNC_FOR_BROADCAST_ADDRESS (-2100L) /* The compare funcion is not suitable for broadcast address */ +#define SL_ERROR_RXFL_WRONG_MULTICAST_ADDRESS (-2101L) /* The address should be of muticast type */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_IS_NOT_PERSISTENT (-2102L) /* The dependency filter is not persistent */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_IS_NOT_ENABLED (-2103L) /* The dependency filter is not enabled */ +#define SL_ERROR_RXFL_FILTER_HAS_CHILDS (-2104L) /* The filter has childs and can't be removed */ +#define SL_ERROR_RXFL_CHILD_IS_ENABLED (-2105L) /* Can't disable filter while the child is enabled */ +#define SL_ERROR_RXFL_DEPENDENCY_IS_DISABLED (-2106L) /* Can't enable filetr in case its depndency filter is disabled */ +#define SL_ERROR_RXFL_MAC_SEND_MATCHDB_FAILED (-2107L) +#define SL_ERROR_RXFL_MAC_SEND_ARG_DB_FAILED (-2108L) +#define SL_ERROR_RXFL_MAC_SEND_NODEDB_FAILED (-2109L) +#define SL_ERROR_RXFL_MAC_OPERTATION_RESUME_FAILED (-2110L) +#define SL_ERROR_RXFL_MAC_OPERTATION_HALT_FAILED (-2111L) +#define SL_ERROR_RXFL_NUMBER_OF_CONNECTION_POINTS_EXCEEDED (-2112L) /* Number of connection points exceeded */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_DEPENDENCY_ACTION_IS_DROP (-2113L) /* The dependent filter has Drop action, thus the filter can't be created */ +#define SL_ERROR_RXFL_FILTER_DO_NOT_EXISTS (-2114L) /* The filter doesn't exists */ +#define SL_ERROR_RXFL_DEPEDENCY_NOT_ON_THE_SAME_LAYER (-2115L) /* The filter and its dependency must be on the same layer */ +#define SL_ERROR_RXFL_NUMBER_OF_ARGS_EXCEEDED (-2116L) /* Number of arguments excceded */ +#define SL_ERROR_RXFL_ACTION_NO_REG_NUMBER (-2117L) /* Action require counter number */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_LAYER_DO_NOT_FIT (-2118L) /* the filter and its dependency should be from the same layer */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_SYSTEM_STATE_DO_NOT_FIT (-2119L) /* The filter and its dependency system state don't fit */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_2 (-2120L) /* The parent filter don't exist */ +#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_1 (-2121L) /* The parent filter is null */ +#define SL_ERROR_RXFL_RULE_HEADER_ACTION_TYPE_NOT_SUPPORTED (-2122L) /* The action type is not supported */ +#define SL_ERROR_RXFL_RULE_HEADER_TRIGGER_COMPARE_FUNC_OUT_OF_RANGE (-2123L) /* The Trigger comparision function is out of range */ +#define SL_ERROR_RXFL_RULE_HEADER_TRIGGER_OUT_OF_RANGE (-2124L) /* The Trigger is out of range */ +#define SL_ERROR_RXFL_RULE_HEADER_COMPARE_FUNC_OUT_OF_RANGE (-2125L) /* The rule compare function is out of range */ +#define SL_ERROR_RXFL_FRAME_TYPE_NOT_SUPPORTED (-2126L) /* ASCII frame type string is illegal */ +#define SL_ERROR_RXFL_RULE_FIELD_ID_NOT_SUPPORTED (-2127L) /* Rule field ID is out of range */ +#define SL_ERROR_RXFL_RULE_HEADER_FIELD_ID_ASCII_NOT_SUPPORTED (-2128L) /* This ASCII field ID is not supported */ +#define SL_ERROR_RXFL_RULE_HEADER_NOT_SUPPORTED (-2129L) /* The header rule is not supported on current release */ +#define SL_ERROR_RXFL_RULE_HEADER_OUT_OF_RANGE (-2130L) /* The header rule is out of range */ +#define SL_ERROR_RXFL_RULE_HEADER_COMBINATION_OPERATOR_OUT_OF_RANGE (-2131L) /* Combination function Id is out of ramge */ +#define SL_ERROR_RXFL_RULE_HEADER_FIELD_ID_OUT_OF_RANGE (-2132L) /* rule field Id is out of range */ +#define SL_ERROR_RXFL_UPDATE_NOT_SUPPORTED (-2133L) /* Update not supported */ +#define SL_ERROR_RXFL_NO_FILTER_DATABASE_ALLOCATE (-2134L) +#define SL_ERROR_RXFL_ALLOCATION_FOR_GLOBALS_STRUCTURE_FAILED (-2135L) +#define SL_ERROR_RXFL_ALLOCATION_FOR_DB_NODE_FAILED (-2136L) +#define SL_ERROR_RXFL_READ_FILE_FILTER_ID_ILLEGAL (-2137L) +#define SL_ERROR_RXFL_READ_FILE_NUMBER_OF_FILTER_FAILED (-2138L) +#define SL_ERROR_RXFL_READ_FILE_FAILED (-2139L) +#define SL_ERROR_RXFL_NO_FILTERS_ARE_DEFINED (-2140L) /* No filters are defined in the system */ +#define SL_ERROR_RXFL_NUMBER_OF_FILTER_EXCEEDED (-2141L) /* Number of max filters excceded */ +#define SL_ERROR_RXFL_BAD_FILE_MODE (-2142L) +#define SL_ERROR_RXFL_FAILED_READ_NVFILE (-2143L) +#define SL_ERROR_RXFL_FAILED_INIT_STORAGE (-2144L) +#define SL_ERROR_RXFL_CONTINUE_WRITE_MUST_BE_MOD_4 (-2145L) +#define SL_ERROR_RXFL_FAILED_LOAD_FILE (-2146L) +#define SL_ERROR_RXFL_INVALID_HANDLE (-2147L) +#define SL_ERROR_RXFL_FAILED_TO_WRITE (-2148L) +#define SL_ERROR_RXFL_OFFSET_OUT_OF_RANGE (-2149L) +#define SL_ERROR_RXFL_ALLOC (-2150L) +#define SL_ERROR_RXFL_READ_DATA_LENGTH (-2151L) +#define SL_ERROR_RXFL_INVALID_FILE_ID (-2152L) +#define SL_ERROR_RXFL_FILE_FILTERS_NOT_EXISTS (-2153L) +#define SL_ERROR_RXFL_FILE_ALREADY_IN_USE (-2154L) +#define SL_ERROR_RXFL_INVALID_ARGS (-2155L) +#define SL_ERROR_RXFL_FAILED_TO_CREATE_FILE (-2156L) +#define SL_ERROR_RXFL_FS_ALREADY_LOADED (-2157L) +#define SL_ERROR_RXFL_UNKNOWN (-2158L) +#define SL_ERROR_RXFL_FAILED_TO_CREATE_LOCK_OBJ (-2159L) +#define SL_ERROR_RXFL_DEVICE_NOT_LOADED (-2160L) +#define SL_ERROR_RXFL_INVALID_MAGIC_NUM (-2161L) +#define SL_ERROR_RXFL_FAILED_TO_READ (-2162L) +#define SL_ERROR_RXFL_NOT_SUPPORTED (-2163L) +#define SL_ERROR_WLAN_INVALID_COUNTRY_CODE (-2164L) +#define SL_ERROR_WLAN_NVMEM_ACCESS_FAILED (-2165L) +#define SL_ERROR_WLAN_OLD_FILE_VERSION (-2166L) +#define SL_ERROR_WLAN_TX_POWER_OUT_OF_RANGE (-2167L) +#define SL_ERROR_WLAN_INVALID_AP_PASSWORD_LENGTH (-2168L) +#define SL_ERROR_WLAN_PROVISIONING_ABORT_PROVISIONING_ALREADY_STARTED (-2169L) +#define SL_ERROR_WLAN_PROVISIONING_ABORT_HTTP_SERVER_DISABLED (-2170L) +#define SL_ERROR_WLAN_PROVISIONING_ABORT_PROFILE_LIST_FULL (-2171L) +#define SL_ERROR_WLAN_PROVISIONING_ABORT_INVALID_PARAM (-2172L) +#define SL_ERROR_WLAN_PROVISIONING_ABORT_GENERAL_ERROR (-2173L) +#define SL_ERROR_WLAN_MULTICAST_EXCEED_MAX_ADDR (-2174L) +#define SL_ERROR_WLAN_MULTICAST_INVAL_ADDR (-2175L) +#define SL_ERROR_WLAN_AP_SCAN_INTERVAL_TOO_SHORT (-2176L) +#define SL_ERROR_WLAN_PROVISIONING_CMD_NOT_EXPECTED (-2177L) + + +#define SL_ERROR_WLAN_AP_ACCESS_LIST_NO_ADDRESS_TO_DELETE (-2178L) /* List is empty, no address to delete */ +#define SL_ERROR_WLAN_AP_ACCESS_LIST_FULL (-2179L) /* access list is full */ +#define SL_ERROR_WLAN_AP_ACCESS_LIST_DISABLED (-2180L) /* access list is disabled */ +#define SL_ERROR_WLAN_AP_ACCESS_LIST_MODE_NOT_SUPPORTED (-2181L) /* Trying to switch to unsupported mode */ +#define SL_ERROR_WLAN_AP_STA_NOT_FOUND (-2182L) /* trying to disconnect station which is not connected */ + + +/* DEVICE ERRORS CODES*/ +#define SL_ERROR_SUPPLICANT_ERROR (-4097L) +#define SL_ERROR_HOSTAPD_INIT_FAIL (-4098L) +#define SL_ERROR_HOSTAPD_INIT_IF_FAIL (-4099L) +#define SL_ERROR_WLAN_DRV_INIT_FAIL (-4100L) +#define SL_ERROR_FS_FILE_TABLE_LOAD_FAILED (-4102L) /* init file system failed */ +#define SL_ERROR_MDNS_ENABLE_FAIL (-4103L) /* mDNS enable failed */ +#define SL_ERROR_ROLE_STA_ERR (-4107L) /* Failure to load MAC/PHY in STA role */ +#define SL_ERROR_ROLE_AP_ERR (-4108L) /* Failure to load MAC/PHY in AP role */ +#define SL_ERROR_ROLE_P2P_ERR (-4109L) /* Failure to load MAC/PHY in P2P role */ +#define SL_ERROR_CALIB_FAIL (-4110L) /* Failure of calibration */ +#define SL_ERROR_FS_CORRUPTED_ERR (-4111L) /* FS is corrupted, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ +#define SL_ERROR_FS_ALERT_ERR (-4112L) /* Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ +#define SL_ERROR_RESTORE_IMAGE_COMPLETE (-4113L) /* Return to factory image completed, perform reset */ +#define SL_ERROR_UNKNOWN_ERR (-4114L) +#define SL_ERROR_GENERAL_ERR (-4115L) /* General error during init */ +#define SL_ERROR_WRONG_ROLE (-4116L) +#define SL_ERROR_INCOMPLETE_PROGRAMMING (-4117L) /* Error during programming, Program new image should be invoked (see sl_FsProgram) */ + + +#define SL_ERROR_PENDING_TXRX_STOP_TIMEOUT_EXP (-4118L) /* Timeout expired before completing all TX\RX */ +#define SL_ERROR_PENDING_TXRX_NO_TIMEOUT (-4119L) /* No Timeout , still have pending TX\RX */ +#define SL_ERROR_INVALID_PERSISTENT_CONFIGURATION (-4120L) /* persistency configuration can only be set to 0 (disabled) or 1 (enabled) */ + +/* NETAPP ERRORS CODES*/ +#define SL_ERROR_MDNS_CREATE_FAIL (-6145L) /* mDNS create failed */ +#define SL_ERROR_DEVICE_NAME_LEN_ERR (-6146L) /* Set Dev name error codes */ +#define SL_ERROR_DEVICE_NAME_INVALID (-6147L) /* Set Dev name error codes */ +#define SL_ERROR_DOMAIN_NAME_LEN_ERR (-6148L) /* Set domain name error codes */ +#define SL_ERROR_DOMAIN_NAME_INVALID (-6149L) /* Set domain name error codes */ +#define SL_ERROR_NET_APP_DNS_QUERY_NO_RESPONSE (-6150L) /* DNS query failed, no response */ +#define SL_ERROR_NET_APP_DNS_ERROR (-6151L) /* DNS internal error */ +#define SL_ERROR_NET_APP_DNS_NO_SERVER (-6152L) /* No DNS server was specified */ +#define SL_ERROR_NET_APP_DNS_TIMEOUTR (-6153L) /* mDNS parameters error */ +#define SL_ERROR_NET_APP_DNS_QUERY_FAILED (-6154L) /* DNS query failed; no DNS server sent an 'answer' */ +#define SL_ERROR_NET_APP_DNS_BAD_ADDRESS_ERROR (-6155L) /* Improperly formatted IPv4 or IPv6 address */ +#define SL_ERROR_NET_APP_DNS_SIZE_ERROR (-6156L) /* DNS destination size is too small */ +#define SL_ERROR_NET_APP_DNS_MALFORMED_PACKET (-6157L) /* Improperly formed or corrupted DNS packet received */ +#define SL_ERROR_NET_APP_DNS_BAD_ID_ERROR (-6158L) /* DNS packet from server does not match query ID */ +#define SL_ERROR_NET_APP_DNS_PARAM_ERROR (-6159L) /* Invalid params */ +#define SL_ERROR_NET_APP_DNS_SERVER_NOT_FOUND (-6160L) /* Server not found in Client list of DNS servers */ +#define SL_ERROR_NET_APP_DNS_PACKET_CREATE_ERROR (-6161L) /* Error creating DNS packet */ +#define SL_ERROR_NET_APP_DNS_EMPTY_DNS_SERVER_LIST (-6162L) /* DNS Client's list of DNS servers is empty */ +#define SL_ERROR_NET_APP_DNS_SERVER_AUTH_ERROR (-6163L) /* Server not able to authenticate answer/authority data */ +#define SL_ERROR_NET_APP_DNS_ZERO_GATEWAY_IP_ADDRESS (-6164L) /* DNS Client IP instance has a zero gateway IP address */ +#define SL_ERROR_NET_APP_DNS_MISMATCHED_RESPONSE (-6165L) /* Server response type does not match the query request */ +#define SL_ERROR_NET_APP_DNS_DUPLICATE_ENTRY (-6166L) /* Duplicate entry exists in DNS server table */ +#define SL_ERROR_NET_APP_DNS_RETRY_A_QUERY (-6167L) /* SOA status returned; web site only exists as IPv4 */ +#define SL_ERROR_NET_APP_DNS_INVALID_ADDRESS_TYPE (-6168L) /* IP address type (e.g. IPv6L) not supported */ +#define SL_ERROR_NET_APP_DNS_IPV6_NOT_SUPPORTED (-6169L) /* IPv6 disabled */ +#define SL_ERROR_NET_APP_DNS_NEED_MORE_RECORD_BUFFER (-6170L) /* The buffer size is not enough. */ +#define SL_ERROR_NET_APP_MDNS_ERROR (-6171L) /* MDNS internal error. */ +#define SL_ERROR_NET_APP_MDNS_PARAM_ERROR (-6172L) /* MDNS parameters error. */ +#define SL_ERROR_NET_APP_MDNS_CACHE_ERROR (-6173L) /* The Cache size is not enough. */ +#define SL_ERROR_NET_APP_MDNS_UNSUPPORTED_TYPE (-6174L) /* The unsupported resource record type. */ +#define SL_ERROR_NET_APP_MDNS_DATA_SIZE_ERROR (-6175L) /* The data size is too big. */ +#define SL_ERROR_NET_APP_MDNS_AUTH_ERROR (-6176L) /* Attempting to parse too large a data. */ +#define SL_ERROR_NET_APP_MDNS_PACKET_ERROR (-6177L) /* The packet can not add the resource record. */ +#define SL_ERROR_NET_APP_MDNS_DEST_ADDRESS_ERROR (-6178L) /* The destination address error. */ +#define SL_ERROR_NET_APP_MDNS_UDP_PORT_ERROR (-6179L) /* The udp port error. */ +#define SL_ERROR_NET_APP_MDNS_NOT_LOCAL_LINK (-6180L) /* The message that not originate from the local link. */ +#define SL_ERROR_NET_APP_MDNS_EXCEED_MAX_LABEL (-6181L) /* The data exceed the max laber size. */ +#define SL_ERROR_NET_APP_MDNS_EXIST_UNIQUE_RR (-6182L) /* At least one Unqiue record in the cache. */ +#define SL_ERROR_NET_APP_MDNS_EXIST_ANSWER (-6183L) /* At least one answer record in the cache. */ +#define SL_ERROR_NET_APP_MDNS_EXIST_SAME_QUERY (-6184L) /* Exist the same query. */ +#define SL_ERROR_NET_APP_MDNS_DUPLICATE_SERVICE (-6185L) /* Duplicate service. */ +#define SL_ERROR_NET_APP_MDNS_NO_ANSWER (-6186L) /* No response for one-shot query. */ +#define SL_ERROR_NET_APP_MDNS_NO_KNOWN_ANSWER (-6187L) /* No known answer for query. */ +#define SL_ERROR_NET_APP_MDNS_NAME_MISMATCH (-6188L) /* The name mismatch. */ +#define SL_ERROR_NET_APP_MDNS_NOT_STARTED (-6189L) /* MDNS does not start. */ +#define SL_ERROR_NET_APP_MDNS_HOST_NAME_ERROR (-6190L) /* MDNS host name error. */ +#define SL_ERROR_NET_APP_MDNS_NO_MORE_ENTRIES (-6191L) /* No more entries be found. */ +#define SL_ERROR_NET_APP_MDNS_SERVICE_TYPE_MISMATCH (-6192L) /* The service type mismatch */ +#define SL_ERROR_NET_APP_MDNS_LOOKUP_INDEX_ERROR (-6193L) /* Index is bigger than number of services. */ +#define SL_ERROR_NET_APP_MDNS_MAX_SERVICES_ERROR (-6194L) +#define SL_ERROR_NET_APP_MDNS_IDENTICAL_SERVICES_ERROR (-6195L) +#define SL_ERROR_NET_APP_MDNS_EXISTED_SERVICE_ERROR (-6196L) +#define SL_ERROR_NET_APP_MDNS_ERROR_SERVICE_NAME_ERROR (-6197L) +#define SL_ERROR_NET_APP_MDNS_RX_PACKET_ALLOCATION_ERROR (-6198L) +#define SL_ERROR_NET_APP_MDNS_BUFFER_SIZE_ERROR (-6199L) +#define SL_ERROR_NET_APP_MDNS_NET_APP_SET_ERROR (-6200L) +#define SL_ERROR_NET_APP_MDNS_GET_SERVICE_LIST_FLAG_ERROR (-6201L) +#define SL_ERROR_NET_APP_MDNS_MDNS_NO_CONFIGURATION_ERROR (-6202L) +#define SL_ERROR_NET_APP_MDNS_STATUS_ERROR (-6203L) +#define SL_ERROR_NET_APP_ENOBUFS (-6204L) +#define SL_ERROR_NET_APP_DNS_IPV6_REQ_BUT_IPV6_DISABLED (-6205L) /* trying to issue ipv6 DNS request but ipv6 is disabled */ +#define SL_ERROR_NET_APP_DNS_INVALID_FAMILY_TYPE (-6206L) /* Family type is not ipv4 and not ipv6 */ +#define SL_ERROR_NET_APP_DNS_REQ_TOO_BIG (-6207L) /* DNS request size is too big */ +#define SL_ERROR_NET_APP_DNS_ALLOC_ERROR (-6208L) /* Allocation error */ +#define SL_ERROR_NET_APP_DNS_EXECUTION_ERROR (-6209L) /* Execution error */ +#define SL_ERROR_NET_APP_P2P_ROLE_IS_NOT_CONFIGURED (-6210L) /* role p2p is not configured yet, should be CL or GO in order to execute command */ +#define SL_ERROR_NET_APP_INCORECT_ROLE_FOR_APP (-6211L) /* incorrect role for specific application */ +#define SL_ERROR_NET_APP_INCORECT_APP_MASK (-6212L) /* mask does not match any app */ +#define SL_ERROR_NET_APP_MDNS_ALREADY_STARTED (-6213L) /* mdns application already started */ +#define SL_ERROR_NET_APP_HTTP_SERVER_ALREADY_STARTED (-6214L) /* http server application already started */ + +#define SL_ERROR_NET_APP_HTTP_GENERAL_ERROR (-6216L) /* New error - Http handle request failed */ +#define SL_ERROR_NET_APP_HTTP_INVALID_TIMEOUT (-6217L) /* New error - Http timeout invalid argument */ +#define SL_ERROR_NET_APP_INVALID_URN_LENGTH (-6218L) /* invalid URN length */ +#define SL_ERROR_NET_APP_RX_BUFFER_LENGTH (-6219L) /* size of the requested services is smaller than size of the user buffer */ + +/* NETCFG ERRORS CODES*/ +#define SL_ERROR_STATIC_ADDR_SUBNET_ERROR (-8193L) +#define SL_ERROR_INCORRECT_IPV6_STATIC_LOCAL_ADDR (-8194L) /* Ipv6 Local address perfix is wrong */ +#define SL_ERROR_INCORRECT_IPV6_STATIC_GLOBAL_ADDR (-8195L) /* Ipv6 Global address perfix is wrong */ +#define SL_ERROR_IPV6_LOCAL_ADDR_SHOULD_BE_SET_FIRST (-8196L) /* Attempt to set ipv6 global address before ipv6 local address is set */ + + +/* FS ERRORS CODES*/ +#define SL_FS_OK (0L) +#define SL_ERROR_FS_EXTRACTION_WILL_START_AFTER_RESET (-10241L) +#define SL_ERROR_FS_NO_CERTIFICATE_STORE (-10242L) +#define SL_ERROR_FS_IMAGE_SHOULD_BE_AUTHENTICATE (-10243L) +#define SL_ERROR_FS_IMAGE_SHOULD_BE_ENCRYPTED (-10244L) +#define SL_ERROR_FS_IMAGE_CANT_BE_ENCRYPTED (-10245L) +#define SL_ERROR_FS_DEVELOPMENT_BOARD_WRONG_MAC (-10246L) +#define SL_ERROR_FS_DEVICE_NOT_SECURED (-10247L) +#define SL_ERROR_FS_SYSTEM_FILE_ACCESS_DENIED (-10248L) +#define SL_ERROR_FS_IMAGE_EXTRACT_EXPECTING_USER_KEY (-10249L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_CLOSE_FILE (-10250L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_WRITE_FILE (-10251L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_OPEN_FILE (-10252L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_IMAGE_HEADER (-10253L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_IMAGE_INFO (-10254L) +#define SL_ERROR_FS_IMAGE_EXTRACT_SET_ID_NOT_EXIST (-10255L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_DELETE_FILE (-10256L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_FORMAT_FS (-10257L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_LOAD_FS (-10258L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_DEV_INFO (-10259L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_DELETE_STORAGE (-10260L) +#define SL_ERROR_FS_IMAGE_EXTRACT_INCORRECT_IMAGE_LOCATION (-10261L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_CREATE_IMAGE_FILE (-10262L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_INIT (-10263L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_LOAD_FILE_TABLE (-10264L) +#define SL_ERROR_FS_IMAGE_EXTRACT_ILLEGAL_COMMAND (-10266L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_WRITE_FAT (-10267L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_RET_FACTORY_DEFAULT (-10268L) +#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_READ_NV (-10269L) +#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_EXISTS (-10270L) +#define SL_ERROR_FS_PROGRAMMING_IN_PROCESS (-10271L) +#define SL_ERROR_FS_PROGRAMMING_ALREADY_STARTED (-10272L) +#define SL_ERROR_FS_CERT_IN_THE_CHAIN_REVOKED_SECURITY_ALERT (-10273L) +#define SL_ERROR_FS_INIT_CERTIFICATE_STORE (-10274L) +#define SL_ERROR_FS_PROGRAMMING_ILLEGAL_FILE (-10275L) +#define SL_ERROR_FS_PROGRAMMING_NOT_STARTED (-10276L) +#define SL_ERROR_FS_IMAGE_EXTRACT_NO_FILE_SYSTEM (-10277L) +#define SL_ERROR_FS_WRONG_INPUT_SIZE (-10278L) +#define SL_ERROR_FS_BUNDLE_FILE_SHOULD_BE_CREATED_WITH_FAILSAFE (-10279L) +#define SL_ERROR_FS_BUNDLE_NOT_CONTAIN_FILES (-10280L) +#define SL_ERROR_FS_BUNDLE_ALREADY_IN_STATE (-10281L) +#define SL_ERROR_FS_BUNDLE_NOT_IN_CORRECT_STATE (-10282L) +#define SL_ERROR_FS_BUNDLE_FILES_ARE_OPENED (-10283L) +#define SL_ERROR_FS_INCORRECT_FILE_STATE_FOR_OPERATION (-10284L) +#define SL_ERROR_FS_EMPTY_SFLASH (-10285L) +#define SL_ERROR_FS_FILE_IS_NOT_SECURE_AND_SIGN (-10286L) +#define SL_ERROR_FS_ROOT_CA_IS_UNKOWN (-10287L) +#define SL_ERROR_FS_FILE_HAS_NOT_BEEN_CLOSE_CORRECTLY (-10288L) +#define SL_ERROR_FS_WRONG_SIGNATURE_SECURITY_ALERT (-10289L) +#define SL_ERROR_FS_WRONG_SIGNATURE_OR_CERTIFIC_NAME_LENGTH (-10290L) +#define SL_ERROR_FS_NOT_16_ALIGNED (-10291L) +#define SL_ERROR_FS_CERT_CHAIN_ERROR_SECURITY_ALERT (-10292L) +#define SL_ERROR_FS_FILE_NAME_EXIST (-10293L) +#define SL_ERROR_FS_EXTENDED_BUF_ALREADY_ALLOC (-10294L) +#define SL_ERROR_FS_FILE_SYSTEM_NOT_SECURED (-10295L) +#define SL_ERROR_FS_OFFSET_NOT_16_BYTE_ALIGN (-10296L) +#define SL_ERROR_FS_FAILED_READ_NVMEM (-10297L) +#define SL_ERROR_FS_WRONG_FILE_NAME (-10298L) +#define SL_ERROR_FS_FILE_SYSTEM_IS_LOCKED (-10299L) +#define SL_ERROR_FS_SECURITY_ALERT (-10300L) +#define SL_ERROR_FS_FILE_INVALID_FILE_SIZE (-10301L) +#define SL_ERROR_FS_INVALID_TOKEN (-10302L) +#define SL_ERROR_FS_NO_DEVICE_IS_LOADED (-10303L) +#define SL_ERROR_FS_SECURE_CONTENT_INTEGRITY_FAILURE (-10304L) +#define SL_ERROR_FS_SECURE_CONTENT_RETRIVE_ASYMETRIC_KEY_ERROR (-10305L) +#define SL_ERROR_FS_OVERLAP_DETECTION_THRESHHOLD (-10306L) +#define SL_ERROR_FS_FILE_HAS_RESERVED_NV_INDEX (-10307L) +#define SL_ERROR_FS_FILE_MAX_SIZE_EXCEEDED (-10310L) +#define SL_ERROR_FS_INVALID_READ_BUFFER (-10311L) +#define SL_ERROR_FS_INVALID_WRITE_BUFFER (-10312L) +#define SL_ERROR_FS_FILE_IMAGE_IS_CORRUPTED (-10313L) +#define SL_ERROR_FS_SIZE_OF_FILE_EXT_EXCEEDED (-10314L) +#define SL_ERROR_FS_WARNING_FILE_NAME_NOT_KEPT (-10315L) +#define SL_ERROR_FS_MAX_OPENED_FILE_EXCEEDED (-10316L) +#define SL_ERROR_FS_FAILED_WRITE_NVMEM_HEADER (-10317L) +#define SL_ERROR_FS_NO_AVAILABLE_NV_INDEX (-10318L) +#define SL_ERROR_FS_FAILED_TO_ALLOCATE_MEM (-10319L) +#define SL_ERROR_FS_OPERATION_BLOCKED_BY_VENDOR (-10320L) +#define SL_ERROR_FS_FAILED_TO_READ_NVMEM_FILE_SYSTEM (-10321L) +#define SL_ERROR_FS_NOT_ENOUGH_STORAGE_SPACE (-10322L) +#define SL_ERROR_FS_INIT_WAS_NOT_CALLED (-10323L) +#define SL_ERROR_FS_FILE_SYSTEM_IS_BUSY (-10324L) +#define SL_ERROR_FS_INVALID_ACCESS_TYPE (-10325L) +#define SL_ERROR_FS_FILE_ALREADY_EXISTS (-10326L) +#define SL_ERROR_FS_PROGRAM_FAILURE (-10327L) +#define SL_ERROR_FS_NO_ENTRIES_AVAILABLE (-10328L) +#define SL_ERROR_FS_FILE_ACCESS_IS_DIFFERENT (-10329L) +#define SL_ERROR_FS_INVALID_FILE_MODE (-10330L) +#define SL_ERROR_FS_FAILED_READ_NVFILE (-10331L) +#define SL_ERROR_FS_FAILED_INIT_STORAGE (-10332L) +#define SL_ERROR_FS_FILE_HAS_NO_FAILSAFE (-10333L) +#define SL_ERROR_FS_NO_VALID_COPY_EXISTS (-10334L) +#define SL_ERROR_FS_INVALID_HANDLE (-10335L) +#define SL_ERROR_FS_FAILED_TO_WRITE (-10336L) +#define SL_ERROR_FS_OFFSET_OUT_OF_RANGE (-10337L) +#define SL_ERROR_FS_NO_MEMORY (-10338L) +#define SL_ERROR_FS_INVALID_LENGTH_FOR_READ (-10339L) +#define SL_ERROR_FS_WRONG_FILE_OPEN_FLAGS (-10340L) +#define SL_ERROR_FS_FILE_NOT_EXISTS (-10341L) +#define SL_ERROR_FS_IGNORE_COMMIT_ROLLBAC_FLAG (-10342L) /* commit rollback flag is not supported upon creation */ +#define SL_ERROR_FS_INVALID_ARGS (-10343L) +#define SL_ERROR_FS_FILE_IS_PENDING_COMMIT (-10344L) +#define SL_ERROR_FS_SECURE_CONTENT_SESSION_ALREADY_EXIST (-10345L) +#define SL_ERROR_FS_UNKNOWN (-10346L) +#define SL_ERROR_FS_FILE_NAME_RESERVED (-10347L) +#define SL_ERROR_FS_NO_FILE_SYSTEM (-10348L) +#define SL_ERROR_FS_INVALID_MAGIC_NUM (-10349L) +#define SL_ERROR_FS_FAILED_TO_READ_NVMEM (-10350L) +#define SL_ERROR_FS_NOT_SUPPORTED (-10351L) +#define SL_ERROR_FS_JTAG_IS_OPENED_NO_FORMAT_TO_PRDUCTION (-10352L) +#define SL_ERROR_FS_CONFIG_FILE_RET_READ_FAILED (-10353L) +#define SL_ERROR_FS_CONFIG_FILE_CHECSUM_ERROR_SECURITY_ALERT (-10354L) +#define SL_ERROR_FS_CONFIG_FILE_NO_SUCH_FILE (-10355L) +#define SL_ERROR_FS_CONFIG_FILE_MEMORY_ALLOCATION_FAILED (-10356L) +#define SL_ERROR_FS_IMAGE_HEADER_READ_FAILED (-10357L) +#define SL_ERROR_FS_CERT_STORE_DOWNGRADE (-10358L) +#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_VALID (-10359L) +#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_VERIFIED (-10360L) +#define SL_ERROR_FS_RESERVE_SIZE_IS_SMALLER (-10361L) +#define SL_ERROR_FS_WRONG_ALLOCATION_TABLE (-10362L) +#define SL_ERROR_FS_ILLEGAL_SIGNATURE (-10363L) +#define SL_ERROR_FS_FILE_ALREADY_OPENED_IN_PENDING_STATE (-10364L) +#define SL_ERROR_FS_INVALID_TOKEN_SECURITY_ALERT (-10365L) +#define SL_ERROR_FS_NOT_SECURE (-10366L) +#define SL_ERROR_FS_RESET_DURING_PROGRAMMING (-10367L) +#define SL_ERROR_FS_CONFIG_FILE_RET_WRITE_FAILED (-10368L) +#define SL_ERROR_FS_FILE_IS_ALREADY_OPENED (-10369L) +#define SL_ERROR_FS_FILE_IS_OPEN_FOR_WRITE (-10370L) +#define SL_ERROR_FS_ALERT_CANT_BE_SET_ON_NON_SECURE_DEVICE (-10371L) /* Alerts can be configured on non-secure device. */ +#define SL_ERROR_FS_WRONG_CERTIFICATE_FILE_NAME (-10372L) + + +/* NETUTIL ERRORS CODES */ +#define SL_ERROR_NETUTIL_CRYPTO_GENERAL (-12289L) +#define SL_ERROR_NETUTIL_CRYPTO_INVALID_INDEX (-12290L) +#define SL_ERROR_NETUTIL_CRYPTO_INVALID_PARAM (-12291L) +#define SL_ERROR_NETUTIL_CRYPTO_MEM_ALLOC (-12292L) +#define SL_ERROR_NETUTIL_CRYPTO_INVALID_DB_VER (-12293L) +#define SL_ERROR_NETUTIL_CRYPTO_UNSUPPORTED_OPTION (-12294L) +#define SL_ERROR_NETUTIL_CRYPTO_BUFFER_TOO_SMALL (-12295L) +#define SL_ERROR_NETUTIL_CRYPTO_EMPTY_DB_ENTRY (-12296L) +#define SL_ERROR_NETUTIL_CRYPTO_NON_TEMPORARY_KEY (-12297L) +#define SL_ERROR_NETUTIL_CRYPTO_DB_ENTRY_NOT_FREE (-12298L) +#define SL_ERROR_NETUTIL_CRYPTO_CORRUPTED_DB_FILE (-12299L) + + +/* GENERAL ERRORS CODES*/ +#define SL_ERROR_INVALID_OPCODE (-14337L) +#define SL_ERROR_INVALID_PARAM (-14338L) +#define SL_ERROR_STATUS_ERROR (-14341L) +#define SL_ERROR_NVMEM_ACCESS_FAILED (-14342L) +#define SL_ERROR_NOT_ALLOWED_NWP_LOCKED (-14343L) /* Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ + + +/* SECURITY ERRORS CODE */ +#define SL_ERROR_LOADING_CERTIFICATE_STORE (-28673L) + +/* Device is Locked! Return to Factory Image or Program new + image should be invoked (see sl_FsCtl, sl_FsProgram) */ +#define SL_ERROR_DEVICE_LOCKED_SECURITY_ALERT (-28674L) + +#define SL_ERROR_LENGTH_ERROR_PREFIX (-30734L) +#define SL_ERROR_WAKELOCK_ERROR_PREFIX (-30735L) +#define SL_ERROR_DRV_START_FAIL (-30736L) +#define SL_ERROR_VALIDATION_ERROR (-30737L) +#define SL_ERROR_SETUP_FAILURE (-30738L) +#define SL_ERROR_HTTP_SERVER_ENABLE_FAILED (-30739L) +#define SL_ERROR_DHCP_SERVER_ENABLE_FAILED (-30740L) +#define SL_ERROR_WPS_NO_PIN_OR_WRONG_PIN_LEN (-30741L) + + +/* INTERNAL HOST ERRORS CODES*/ + +/* Receive this error in case there are no resources to issue the command + If possible, increase the number of MAX_CONCURRENT_ACTIONS (result in memory increaseL) + If not, try again later */ +#define SL_POOL_IS_EMPTY (-2000L) + +/* Receive this error in case a given length for RX buffer was too small. + Receive payload was bigger than the given buffer size. Therefore, payload is cut according to receive size + Recommend to increase buffer size */ +#define SL_ESMALLBUF (-2001L) + +/* Receive this error in case zero length is supplied to a "get" API + Recommend to supply length according to requested information (view options defines for helpL) */ +#define SL_EZEROLEN (-2002L) + +/* User supplied invalid parameter */ +#define SL_INVALPARAM (-2003L) + +/* Failed to open interface */ +#define SL_BAD_INTERFACE (-2004L) + +/* API has been aborted due to an error detected by host driver */ +#define SL_API_ABORTED (-2005L) + +/* Parameters are invalid */ +#define SL_RET_CODE_INVALID_INPUT (-2006L) + +/* Driver internal error */ +#define SL_RET_CODE_SELF_ERROR (-2007L) + +/* NWP internal error */ +#define SL_RET_CODE_NWP_IF_ERROR (-2008L) + +/* malloc error */ +#define SL_RET_CODE_MALLOC_ERROR (-2009L) + +/* protocol error */ +#define SL_RET_CODE_PROTOCOL_ERROR (-2010L) + +/* API has been aborted, command is not allowed in device lock state */ +#define SL_RET_CODE_DEV_LOCKED (-2011L) + +/* sl_Start cannot be invoked twice */ +#define SL_RET_CODE_DEV_ALREADY_STARTED (-2012L) + +/* SL API is in progress */ +#define SL_RET_CODE_API_COMMAND_IN_PROGRESS (-2013L) + +/* Provisioning is in progress - */ +#define SL_RET_CODE_PROVISIONING_IN_PROGRESS (-2014L) + +/* Wrong ping parameters - ping cannot be called with the following parameters: +1. infinite ping packet +2. report only when finished +3. no callback supplied */ +#define SL_RET_CODE_NET_APP_PING_INVALID_PARAMS (-2015L) + +/* SL select already in progress. + this error will be returned if app will try to call + sl_select blocking when there is already select trigger in progress */ +#define SL_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR (-2016L) + +#define SL_RET_CODE_STOP_IN_PROGRESS (-2017L) + +/* The device has not been started yet */ +#define SL_RET_CODE_DEV_NOT_STARTED (-2018L) + +/* The event link was not found in the list */ +#define SL_RET_CODE_EVENT_LINK_NOT_FOUND (-2019L) + +/* In case there are no free buffers for async event which arrived + during command context. In this case user needs to increase + MAX_CONCURRENT_ACTIONS at user.h */ +#define SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR (-2020L) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ERROR_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.c new file mode 100755 index 00000000000..740aef035dd --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.c @@ -0,0 +1,381 @@ +/* + * eventreg.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include + + +typedef void (*_pSlDeviceFatalErrorEvtHdlr_t)(SlDeviceFatal_t *pSlFatalErrorEvent); +typedef void (*_pSlDeviceGeneralEvtHdlr_t)(SlDeviceEvent_t *pSlDeviceEvent); +typedef void (*_pSlWlanEvtHdlr)(SlWlanEvent_t* pSlWlanEvent); +typedef void (*_pSlNetAppEvtHdlr)(SlNetAppEvent_t* pSlNetAppEvent); +typedef void (*_pSlSockEvtHdlr)(SlSockEvent_t* pSlSockEvent); +typedef void (*_pSlNetAppHttpServerHdlr)(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); +typedef void (*_pSlNetAppRequestHdlr)(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); +typedef void (*_pSlNetAppRequestMemFree)(_u8 *buffer); +typedef void (*_pSlSocketTriggerEventHandler)(SlSockTriggerEvent_t* pSlSockTriggerEvent); + + +typedef _i32 (*_pSlPropogationDeviceFatalErrorEvtHdlr_t)(SlDeviceFatal_t *pSlFatalErrorEvent); +typedef _i32 (*_pSlPropogationDeviceGeneralEvtHdlr_t)(SlDeviceEvent_t *pSlDeviceEvent); +typedef _i32 (*_pSlPropogationWlanEvtHdlr)(SlWlanEvent_t* pSlWlanEvent); +typedef _i32 (*_pSlPropogationNetAppEvtHdlr)(SlNetAppEvent_t* pSlNetAppEvent); +typedef _i32 (*_pSlPropogationSockEvtHdlr)(SlSockEvent_t* pSlSockEvent); +typedef _i32 (*_pSlPropogationNetAppHttpServerHdlr)(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); +typedef _i32 (*_pSlPropogationNetAppRequestHdlr)(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); +typedef _i32 (*_pSlPropogationNetAppRequestMemFree)(_u8 *buffer); +typedef _i32 (*_pSlPropogationSocketTriggerEventHandler)(SlSockTriggerEvent_t* pSlSockTriggerEvent); + +#ifdef SL_RUNTIME_EVENT_REGISTERATION + +void* g_UserEvents[SL_NUM_OF_EVENT_TYPES] = {0}; +SlEventsListNode_t* g_LibsEvents[SL_NUM_OF_EVENT_TYPES] = {0}; + +#endif + + +_i32 _SlIsEventRegistered(SlEventHandler_e EventHandlerType) +{ +#ifdef SL_RUNTIME_EVENT_REGISTERATION + if( (NULL != g_LibsEvents[EventHandlerType]) || (NULL != g_UserEvents[EventHandlerType]) ) + { + return 1; + } +#endif + if(SL_EVENT_HDL_MEM_FREE == EventHandlerType) + { +#ifdef slcb_NetAppRequestMemFree + return 1; +#endif + } + if(SL_EVENT_HDL_SOCKET_TRIGGER == EventHandlerType) + { +#ifdef slcb_SocketTriggerEventHandler + return 1; +#endif + } + + return 0; +} + +#ifdef SL_RUNTIME_EVENT_REGISTERATION + +_i32 sl_RegisterEventHandler(SlEventHandler_e EventHandlerType , void* EventHandler) +{ + g_UserEvents[EventHandlerType] = EventHandler; + return 0; +} + +_i32 sl_RegisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode) +{ + EventHandlerNode->next = NULL; + + if(g_LibsEvents[EventHandlerType] == NULL) + { + g_LibsEvents[EventHandlerType] = EventHandlerNode; + } + else + { + SlEventsListNode_t* currentNode = g_LibsEvents[EventHandlerType]; + while(currentNode->next != NULL) + { + currentNode = currentNode->next; + } + + currentNode->next = EventHandlerNode; + } + return 0; +} + +_i32 sl_UnregisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[EventHandlerType]; + SlEventsListNode_t* lastNode = g_LibsEvents[EventHandlerType]; + int count = 0; + while(currentNode != NULL) + { + if(EventHandlerNode == currentNode) + { + if(count == 0) + { + g_LibsEvents[EventHandlerType] = g_LibsEvents[EventHandlerType]->next; + } + else + { + lastNode->next = currentNode->next; + } + return 0; + } + + if(count != 0) + { + lastNode = lastNode->next; + } + count++; + currentNode = currentNode->next; + } + + return SL_RET_CODE_EVENT_LINK_NOT_FOUND; +} + + +/* Event handlers section */ +void _SlDeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_FATAL_ERROR]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationDeviceFatalErrorEvtHdlr_t)(currentNode->event))(pSlFatalErrorEvent)) + { + return; + } + currentNode = currentNode->next; + } + + if (NULL != g_UserEvents[SL_EVENT_HDL_FATAL_ERROR]) + { + ((_pSlDeviceFatalErrorEvtHdlr_t)g_UserEvents[SL_EVENT_HDL_FATAL_ERROR])(pSlFatalErrorEvent); + } + +#ifdef slcb_DeviceFatalErrorEvtHdlr + else + { + slcb_DeviceFatalErrorEvtHdlr(pSlFatalErrorEvent); + } +#endif +} + + +void _SlDeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_DEVICE_GENERAL]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationDeviceGeneralEvtHdlr_t)(currentNode->event))(pSlDeviceEvent)) + { + return; + } + currentNode = currentNode->next; + } + + if (NULL != g_UserEvents[SL_EVENT_HDL_DEVICE_GENERAL]) + { + ((_pSlDeviceGeneralEvtHdlr_t)g_UserEvents[SL_EVENT_HDL_DEVICE_GENERAL])(pSlDeviceEvent); + } +#ifdef slcb_DeviceGeneralEvtHdlr + else + { + slcb_DeviceGeneralEvtHdlr(pSlDeviceEvent); + } +#endif +} + + +void _SlWlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_WLAN]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationWlanEvtHdlr)(currentNode->event))(pSlWlanEvent)) + { + return; + } + currentNode = currentNode->next; + } + + if (NULL != g_UserEvents[SL_EVENT_HDL_WLAN]) + { + ((_pSlWlanEvtHdlr)g_UserEvents[SL_EVENT_HDL_WLAN])(pSlWlanEvent); + } +#ifdef slcb_WlanEvtHdlr + else + { + slcb_WlanEvtHdlr(pSlWlanEvent); + } +#endif +} + + +void _SlNetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_NETAPP]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppEvtHdlr)(currentNode->event))(pSlNetAppEvent)) + { + return; + } + currentNode = currentNode->next; + } + if (NULL != g_UserEvents[SL_EVENT_HDL_NETAPP]) + { + ((_pSlNetAppEvtHdlr)g_UserEvents[SL_EVENT_HDL_NETAPP])(pSlNetAppEvent); + } +#ifdef slcb_NetAppEvtHdlr + else + { + slcb_NetAppEvtHdlr(pSlNetAppEvent); + } +#endif +} + + +void _SlSockEvtHdlr(SlSockEvent_t* pSlSockEvent) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_SOCKET]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationSockEvtHdlr)(currentNode->event))(pSlSockEvent)) + { + return; + } + currentNode = currentNode->next; + } + if (NULL != g_UserEvents[SL_EVENT_HDL_SOCKET]) + { + ((_pSlSockEvtHdlr)g_UserEvents[SL_EVENT_HDL_SOCKET])(pSlSockEvent); + } + +#ifdef slcb_SockEvtHdlr + else + { + slcb_SockEvtHdlr(pSlSockEvent); + } +#endif +} + + +void _SlNetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_HTTP_SERVER]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppHttpServerHdlr)(currentNode->event))(pSlHttpServerEvent,pSlHttpServerResponse)) + { + return; + } + currentNode = currentNode->next; + } + if (NULL != g_UserEvents[SL_EVENT_HDL_HTTP_SERVER]) + { + ((_pSlNetAppHttpServerHdlr)g_UserEvents[SL_EVENT_HDL_HTTP_SERVER])(pSlHttpServerEvent,pSlHttpServerResponse); + } +#ifdef slcb_NetAppHttpServerHdlr + else + { + slcb_NetAppHttpServerHdlr(pSlHttpServerEvent,pSlHttpServerResponse); + } +#endif +} + + + +void _SlNetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_NETAPP_REQUEST]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppRequestHdlr)(currentNode->event))(pNetAppRequest,pNetAppResponse)) + { + return; + } + currentNode = currentNode->next; + } + if (NULL != g_UserEvents[SL_EVENT_HDL_NETAPP_REQUEST]) + { + ((_pSlNetAppRequestHdlr)g_UserEvents[SL_EVENT_HDL_NETAPP_REQUEST])(pNetAppRequest,pNetAppResponse); + } +#ifdef slcb_NetAppRequestHdlr + else + { + slcb_NetAppRequestHdlr(pNetAppRequest,pNetAppResponse); + } +#endif +} + + + +void _SlNetAppRequestMemFree (_u8 *buffer) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_MEM_FREE]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppRequestMemFree)(currentNode->event))(buffer)) + { + return; + } + currentNode = currentNode->next; + } + if (NULL != g_UserEvents[SL_EVENT_HDL_MEM_FREE]) + { + ((_pSlNetAppRequestMemFree)g_UserEvents[SL_EVENT_HDL_MEM_FREE])(buffer); + } +#ifdef slcb_NetAppRequestMemFree + else + { + slcb_NetAppRequestMemFree(buffer); + } +#endif +} + + +void _SlSocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent) +{ + SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_SOCKET_TRIGGER]; + while(currentNode != NULL) + { + if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationSocketTriggerEventHandler)(currentNode->event))(pSlSockTriggerEvent)) + { + return; + } + currentNode = currentNode->next; + } + if (NULL != g_UserEvents[SL_EVENT_HDL_SOCKET_TRIGGER]) + { + ((_pSlSocketTriggerEventHandler)g_UserEvents[SL_EVENT_HDL_SOCKET_TRIGGER])(pSlSockTriggerEvent); + } +#ifdef slcb_SocketTriggerEventHandler + else + { + slcb_SocketTriggerEventHandler(pSlSockTriggerEvent); + } +#endif +} + +#endif /* SL_RUNTIME_EVENT_REGISTERATION */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.h new file mode 100755 index 00000000000..4f2a66be7cc --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/eventreg.h @@ -0,0 +1,153 @@ +/* + * eventreg.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef EVENTREG_H_ +#define EVENTREG_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + \defgroup event_registration + \short Allows user to register event handlers dynamically. + +*/ +/*! + + \addtogroup event_registration + @{ + +*/ + +typedef enum +{ + SL_EVENT_HDL_FATAL_ERROR, + SL_EVENT_HDL_DEVICE_GENERAL, + SL_EVENT_HDL_WLAN, + SL_EVENT_HDL_NETAPP, + SL_EVENT_HDL_SOCKET, + SL_EVENT_HDL_HTTP_SERVER, + SL_EVENT_HDL_NETAPP_REQUEST, + SL_EVENT_HDL_MEM_FREE, + SL_EVENT_HDL_SOCKET_TRIGGER, + SL_NUM_OF_EVENT_TYPES +}SlEventHandler_e; + +typedef struct SlEventsListNode_s +{ + void *event; + struct SlEventsListNode_s *next; +}SlEventsListNode_t; + +#ifdef SL_RUNTIME_EVENT_REGISTERATION + +/*! + \brief register events in runtime + + this api enables registration of the SimpleLink host driver in runtime. + + \param[in] EventHandlerType event type - SlEventHandler_e - to register + + \param[in] EventHandler pointer to the event handler + + \return 0 on success, error otherwise + + \sa sl_RegisterEventHandler + + \note registration of event with NULL, clears any registered event. +*/ +_i32 sl_RegisterEventHandler(SlEventHandler_e EventHandlerType , void* EventHandler); + + + +_i32 _SlIsEventRegistered(SlEventHandler_e EventHandlerType); + +/****************************************************************************** + sl_RegisterLibsEventHandler + + \brief this function registers event handlers from external libraries in runtime. + + the allocation and memory maintenance of the SlEventsListNode_t is on the library + Responsibility. + + RETURNS: success or error code. +******************************************************************************/ + +_i32 sl_RegisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode); + +/****************************************************************************** + sl_UnregisterLibsEventHandler + + DESCRIPTION: + this function unregisters event handlers from external libraries in runtime. + the SlEventsListNode_t that was used for registration, must be used to unregister that event handler. + + the allocation and memory maintenance of the SlEventsListNode_t is on the library + Responsibility. + + RETURNS: success or error code. +******************************************************************************/ +_i32 sl_UnregisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode); + +/*! + + Close the Doxygen group. + @} + + */ + + +void _SlDeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent); +void _SlDeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent); +void _SlWlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent); +void _SlNetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent); +void _SlSockEvtHdlr(SlSockEvent_t* pSlSockEvent); +void _SlNetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); +void _SlNetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); +void _SlNetAppRequestMemFree (_u8 *buffer); +void _SlSocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent); + +#endif /* SL_RUNTIME_EVENT_REGISTERATION */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* EVENTREG_H_ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/fs.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/fs.h new file mode 100755 index 00000000000..6b95dc7f72a --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/fs.h @@ -0,0 +1,850 @@ +/* + * fs.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include + +#ifndef __FS_H__ +#define __FS_H__ + + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup FileSystem + \short Provides file system capabilities to TI's CC31XX that can be used by both the CC31XX device and the user + +*/ + +/*! + + \addtogroup FileSystem + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +/* Create file max size mode */ +#define SL_FS_OPEN_MODE_BIT_MASK (0xF8000000) +#define SL_NUM_OF_MODE_BIT (5) + +#define SL_FS_OPEN_FLAGS_BIT_MASK (0x07FE0000) +#define SL_NUM_OF_FLAGS_BIT (10) + +#define SL_FS_OPEN_MAXSIZE_BIT_MASK (0x1FFFF) +#define SL_NUM_OF_MAXSIZE_BIT (17) + + +/* + sl_FsGetInfo and sl_FsGetFileList flags + ------------------ +*/ + +#define SL_FS_INFO_OPEN_WRITE 0x1000 /* File is opened for write */ +#define SL_FS_INFO_OPEN_READ 0x800 /* File is opened for read */ + +#define SL_FS_INFO_MUST_COMMIT 0x1 /* File is currently open with SL_FS_WRITE_MUST_COMMIT */ +#define SL_FS_INFO_BUNDLE_FILE 0x2 /* File is currently open with SL_FS_WRITE_BUNDLE_FILE */ + +#define SL_FS_INFO_PENDING_COMMIT 0x4 /* File that was open with SL_FS_WRITE_MUST_COMMIT is closed */ +#define SL_FS_INFO_PENDING_BUNDLE_COMMIT 0x8 /* File that was open with SL_FS_WRITE_BUNDLE_FILE is closed */ + +#define SL_FS_INFO_NOT_FAILSAFE 0x20 /* File was not created with SL_FS_CREATE_FAILSAFE */ +#define SL_FS_INFO_NOT_VALID 0x100 /* No valid image exists for the file */ +#define SL_FS_INFO_SYS_FILE 0x40 /* File is system file */ +#define SL_FS_INFO_SECURE 0x10 /* File is secured */ +#define SL_FS_INFO_NOSIGNATURE 0x2000 /* File is unsigned, the flag is returns only for sl_FsGetInfo function and not for sl_FsGetFileList */ +#define SL_FS_INFO_PUBLIC_WRITE 0x200 /* File is open for public write */ +#define SL_FS_INFO_PUBLIC_READ 0x400 /* File is open for public read */ + + +/* + fs_Open flags + -------------- +*/ + +/* mode */ +#define SL_FS_CREATE ((_u32)0x1<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) +#define SL_FS_WRITE ((_u32)0x2<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) +#define SL_FS_OVERWRITE ((_u32)0x4<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) +#define SL_FS_READ ((_u32)0x8<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) +/* creation flags */ +#define SL_FS_CREATE_FAILSAFE ((_u32)0x1< + + - Create a non secure file if not already exists and open it for write + \code + DeviceFileHandle = sl_FsOpen((unsigned char *)DeviceFileName, + SL_FS_CREATE|SL_FS_OVERWRITE| SL_FS_CREATE_MAX_SIZE( MaxSize ), + NULL); + \endcode + + \note Some of the flags are creation flags and can only be set when the file is created. When opening the file for write the creation flags are ignored. For more information, refer to chapter 8 in the user manual. + +*/ + +#if _SL_INCLUDE_FUNC(sl_FsOpen) +_i32 sl_FsOpen(const _u8 *pFileName,const _u32 AccessModeAndMaxSize,_u32 *pToken); +#endif + +/*! + \brief Close file in storage device + + \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) + \param[in] pCeritificateFileName Certificate file, or NULL if irrelevant. + \param[in] pSignature The signature is SHA-1, the certificate chain may include SHA-256 + \param[in] SignatureLen The signature actual length + + \return Zero on success, or a negative value if an error occurred + \sa sl_FsRead sl_FsWrite sl_FsOpen + \note Call the fs_Close with signature = 'A' signature len = 1 for activating an abort action\n + Creating signature : OpenSSL> dgst -binary -sha1 -sign \.pem -out \.sig \.txt + \warning + \par Examples + + - Closing file: + \code + _i16 RetVal; + RetVal = sl_FsClose(FileHandle,0,0,0); + \endcode +
+ + - Aborting file: + \code + _u8 Signature; + Signature = 'A'; + sl_FsClose(FileHandle,0,&Signature, 1); + \endcode + + \note In case the file was opened as not secure file or as secure-not signed, any certificate or signature provided are ignored, those fields should be set to NULL. +*/ +#if _SL_INCLUDE_FUNC(sl_FsClose) +_i16 sl_FsClose(const _i32 FileHdl,const _u8* pCeritificateFileName,const _u8* pSignature,const _u32 SignatureLen); +#endif + +/*! + \brief Read block of data from a file in storage device + + \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) + \param[in] Offset Offset to specific read block + \param[out] pData Pointer for the received data + \param[in] Len Length of the received data + + \return Number of read bytes on success, negative error code on failure + + \sa sl_FsClose sl_FsWrite sl_FsOpen + \note belongs to \ref basic_api + \warning + \par Example + + - Reading File: + \code + Status = sl_FsRead(FileHandle, 0, &readBuff[0], readSize); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_FsRead) +_i32 sl_FsRead(const _i32 FileHdl,_u32 Offset ,_u8* pData,_u32 Len); +#endif + +/*! + \brief Write block of data to a file in storage device + + \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) + \param[in] Offset Offset to specific block to be written + \param[in] pData Pointer the transmitted data to the storage device + \param[in] Len Length of the transmitted data + + \return Number of wireted bytes on success, negative error code on failure + + \sa + \note belongs to \ref basic_api + \warning + \par Example + + - Writing file: + \code + Status = sl_FsWrite(FileHandle, 0, &buff[0], readSize); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_FsWrite) +_i32 sl_FsWrite(const _i32 FileHdl,_u32 Offset,_u8* pData,_u32 Len); +#endif + +/*! + \brief Get information of a file + + \param[in] pFileName File name + \param[in] Token File token. if irrelevant set to 0. + \param[out] pFsFileInfo Returns the File's Information (SlFsFileInfo_t) + - Flags + - File size + - Allocated size + - Tokens + + \return Zero on success, negative error code on failure \n + When file not exists : SL_ERROR_FS_FILE_NOT_EXISTS + \note + - If the return value is SL_ERROR_FS_FILE_HAS_NOT_BEEN_CLOSE_CORRECTLY or SL_ERROR_FS_FILE_IS_ALREADY_OPENED information about the file is valid. + - Belongs to \ref basic_api + + \sa sl_FsOpen + \warning + \par Example + + - Getting file info: + \code + Status = sl_FsGetInfo("FileName.html",Token,&FsFileInfo); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_FsGetInfo) +_i16 sl_FsGetInfo(const _u8 *pFileName,const _u32 Token,SlFsFileInfo_t* pFsFileInfo); +#endif + +/*! + \brief Delete specific file from a storage or all files from a storage (format) + + \param[in] pFileName File Name + \param[in] Token File token. if irrelevant set to 0 + \return Zero on success, or a negative value if an error occurred + + \sa + \note belongs to \ref basic_api + \warning + \par Example + + - Deleting file: + \code + Status = sl_FsDel("FileName.html",Token); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_FsDel) +_i16 sl_FsDel(const _u8 *pFileName,const _u32 Token); +#endif + + + +/*! + \brief Controls various file system operations + + \param[in] Command , the command to execute, \see SlFsCtl_e + SL_FS_CTL_RESTORE , Return to factory default, return to factory image , see fs programming + SL_FS_CTL_ROLLBACK , Roll-back file which was created with 'SL_FS_WRITE_MUST_COMMIT' + SL_FS_CTL_COMMIT,Commit file which was created with 'SL_FS_WRITE_MUST_COMMIT' + SL_FS_CTL_RENAME, Rename file + SL_FS_CTL_GET_STORAGE_INFO, Total size of storage , available size of storage + SL_FS_CTL_BUNDLE_ROLLBACK, Rollback bundle files + SL_FS_CTL_BUNDLE_COMMIT, Commit Bundle files + \param[in] Token Set to NULL if not relevant to the command + \param[in] pFileName Set to NULL if not relevant to the command + \param[in] pData The data according the command. + \param[in] DataLen Length of data buffer + \param[out] pOutputData Buffer for the output data + \param[out] OutputDataLen Length of the output data buffer + \param[out] pNewToken The new valid file token, if irrelevant can be set to NULL. + \return + - Zero on success, or a negative value if an error occurred + - For SL_FS_CTL_BUNDLE_ROLLBACK, On success bundle the new bundle state is returned (see SlFsBundleState_e) else negative error number + - For SL_FS_CTL_BUNDLE_COMMIT, On success the new bundle state is returned (see SlFsBundleState_e) else negative error number + + \sa + \note belongs to \ref ext_api + \warning + \par Examples + + - SL_FS_CTL_ROLLBACK: + \code + FsControl.IncludeFilters = 0; + slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_FILE_ROLLBACK, Token, NWPfileName ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , pNewToken); + \endcode +
+ + - SL_FS_CTL_COMMIT: + \code + FsControl.IncludeFilters = 0; + slRetVal = sl_FsCtl(SL_FS_CTL_COMMIT, Token, NWPfileName ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0, pNewToken ); + \endcode +
+ + - SL_FS_CTL_RENAME: + \code + slRetVal = sl_FsCtl(SL_FS_CTL_RENAME, Token, NWPfileName, NewFileName, 0, NULL, 0, NULL ); + \endcode +
+ + - SL_FS_CTL_GET_STORAGE_INFO: + \code + _i32 GetStorageInfo( SlFsControlGetStorageInfoResponse_t* pSlFsControlGetStorageInfoResponse ) + { + _i32 slRetVal; + + slRetVal = sl_FsCtl( ( SlFsCtl_e)SL_FS_CTL_GET_STORAGE_INFO, 0, NULL , NULL , 0, (_u8 *)pSlFsControlGetStorageInfoResponse, sizeof(SlFsControlGetStorageInfoResponse_t), NULL ); + return slRetVal; + } + \endcode +
+ + - SL_FS_CTL_RESTORE: + \code + //Return 0 for OK, else Error + _i32 ProgramRetToImage( ) + { + _i32 slRetVal; + SlFsRetToFactoryCommand_t RetToFactoryCommand; + _i32 RetVal, ExtendedError; + + RetToFactoryCommand.Operation = SL_FS_FACTORY_RET_TO_IMAGE; + slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_RESTORE, 0, NULL , (_u8 *)&RetToFactoryCommand , sizeof(SlFsRetToFactoryCommand_t), NULL, 0 , NULL ); + if ((_i32)slRetVal < 0) + { + //Pay attention, for this function the slRetVal is composed from Signed RetVal & extended error + RetVal = (_i16)slRetVal>> 16; + ExtendedError = (_u16)slRetVal& 0xFFFF; + printf("\tError SL_FS_FACTORY_RET_TO_IMAGE, 5d, %d\n", RetVal, ExtendedError); + return slRetVal; + } + //Reset + sl_Stop(0); + Sleep(1000); + sl_Start(NULL, NULL, NULL); + + return slRetVal; + } + \endcode +
+ + - SL_FS_CTL_BUNDLE_ROLLBACK: + \code + //return 0 for O.K else negative + _i32 BundleRollback() + { + _i32 slRetVal = 0; + SlFsControl_t FsControl; + FsControl.IncludeFilters = 0; //Use default behaviour + slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_BUNDLE_ROLLBACK, 0, NULL ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , NULL); + return slRetVal; + } + \endcode +
+ + - SL_FS_CTL_BUNDLE_COMMIT: + \code + //return 0 for O.K else negative + _i32 BundleCommit() + { + _i32 slRetVal = 0; + SlFsControl_t FsControl; + FsControl.IncludeFilters = 0; //Use default behaviour + slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_BUNDLE_COMMIT, 0, NULL ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , NULL); + return slRetVal; + } + \endcode + */ +#if _SL_INCLUDE_FUNC(sl_FsCtl) +_i32 sl_FsCtl( SlFsCtl_e Command, _u32 Token, _u8 *pFileName, const _u8 *pData, _u16 DataLen, _u8 *pOutputData, _u16 OutputDataLen,_u32 *pNewToken ); +#endif +/*! + \brief Enables to format and configure the device with pre-prepared configuration + + \param[in] Flags For future use + \param[in] pKey In case the ucf is encrypted the encryption key, otherwise NULL + \param[in] pData The file is download in data chunks, the chunk size should be aligned to 16 bytes, if no data Set to NULL + \param[in] Len The length of pData in bytes + \return The return value is: + - On error < 0 , contains the error number and extended error number + - On success > 0, represent the number of bytes received + - On successful end == 0 , when all file chunks are download + \sa + \note belongs to \ref ext_api + \warning + \par Example + + - FS programming: + \code + + //Return 0 for OK, else Error + _i32 ProgramImage( char* UcfFileName, char * KeyFileName ) + { + #define PROGRAMMING_CHUNK_SIZE 4096 + _i32 slRetVal = 0; + SlFsKey_t Key; + FILE *hostFileHandle = NULL; + _u16 bytesRead; + _u8 DataBuf[PROGRAMMING_CHUNK_SIZE]; + FILE *KeyFileHandle = NULL; + short ErrorNum; + unsigned short ExtendedErrorNum; + time_t start,end; + double dif; + _u8* pKey = NULL; + errno_t err; + + if (KeyFileName != "") + { + //Read key + err = fopen_s( &KeyFileHandle, KeyFileName, "rb"); + if (err != 0) + { + return __LINE__;//error + } + fread((_u8*)&Key, 1, sizeof(SlFsKey_t), KeyFileHandle); + fclose(KeyFileHandle); + pKey = (_u8*)&Key; + } + + // Downlaoding the Data with the key, the key can be set only in the first chunk,no need to download it with each chunk + if (UcfFileName != "") + { + //Read data + err = fopen_s( &hostFileHandle, UcfFileName, "rb"); + if (err != 0) + { + return __LINE__;//error + } + + time (&start); + + bytesRead = fread(DataBuf, 1, PROGRAMMING_CHUNK_SIZE, hostFileHandle); + + while ( bytesRead ) + { + slRetVal = sl_FsProgram( DataBuf , bytesRead , (_u8*)pKey, 0 ); + if(slRetVal == SL_API_ABORTED)//timeout + { + return( slRetVal ); + } + else if (slRetVal < 0 )//error + { + ErrorNum = (long)slRetVal >> 16; + ExtendedErrorNum = (_u16)(slRetVal & 0xFFFF); + printf("\tError sl_FsProgram = %d , %d \n", ErrorNum, ExtendedErrorNum); + fclose(hostFileHandle); + return( ErrorNum ); + } + if(slRetVal == 0)//finished succesfully + break; + pKey = NULL;//no need to download the key with each chunk; + bytesRead = fread(DataBuf, 1, PROGRAMMING_CHUNK_SIZE, hostFileHandle); + } + + + time (&end); + dif = difftime (end,start); + #ifdef PRINT + printf ("\tProgramming took %.2lf seconds to run.\n", dif ); + #endif + //The file was downloaded but it was not detected by the programming as the EOF. + if((bytesRead == 0 ) && (slRetVal > 0 )) + { + return __LINE__;//error + } + + + fclose(hostFileHandle); + }//if (UcfFileName != "") + + //this scenario is in case the image was already "burned" to the SFLASH by external tool and only the key is downloaded + else if (KeyFileName != "") + { + slRetVal = sl_FsProgram(NULL , 0 , (_u8*)pKey, 0 ); + if (slRetVal < 0)//error + { + ErrorNum = (long)slRetVal >> 16; + ExtendedErrorNum = (_u16)slRetVal && 0xFF;; + printf("\tError sl_FsProgram = %d , %d \n", ErrorNum, ExtendedErrorNum); + fclose(hostFileHandle); + return( ErrorNum ); + } + } + + if( slRetVal == 0 ) + { + //Reset the nWP + sl_Stop(100); + Sleep(1000); + sl_Start(NULL, NULL, NULL); + Sleep(2000); + } + + return slRetVal; + + } + + \endcode +*/ + +#if _SL_INCLUDE_FUNC(sl_FsProgram) +_i32 sl_FsProgram(const _u8* pData , _u16 Len , const _u8 * pKey , _u32 Flags ); +#endif +/*! + \brief The list of file names, the files are retrieve in chunks + + \param[in, out] pIndex The first chunk should start with value of -1, afterwards the Index from the previous call should be set as input\n + Returns current chunk intex, start the next chunk from that number + \param[in] Count Number of entries to retrieve + \param[in] MaxEntryLen The total size of the buffer is Count * MaxEntryLen + \param[out] pBuff The buffer contains list of SlFileAttributes_t + file name + \param[in] Flags Is to retrieve file attributes see SlFileAttributes_t. + \return The actual number of entries which are contained in the buffer. On error negative number which contains the error number. + \sa + \note belongs to \ref ext_api + \warning + \par Example + + - Getting file list + \code + typedef struct + { + SlFileAttributes_t attribute; + char fileName[SL_FS_MAX_FILE_NAME_LENGTH]; + }slGetfileList_t; + + #define COUNT 5 + + void PrintFileListProperty(_u16 prop); + + INT32 GetFileList() + { + _i32 NumOfEntriesOrError = 1; + _i32 Index = -1; + slGetfileList_t File[COUNT]; + _i32 i; + _i32 RetVal = 0; + + printf("%\n"); + while( NumOfEntriesOrError > 0 ) + { + NumOfEntriesOrError = sl_FsGetFileList( &Index, COUNT, (_u8)(SL_FS_MAX_FILE_NAME_LENGTH + sizeof(SlFileAttributes_t)), (unsigned char*)File, SL_FS_GET_FILE_ATTRIBUTES); + if (NumOfEntriesOrError < 0) + { + RetVal = NumOfEntriesOrError;//error + break; + } + for (i = 0; i < NumOfEntriesOrError; i++) + { + printf("Name: %s\n", File[i].fileName); + printf("AllocatedBlocks: %5d ",File[i].attribute.FileAllocatedBlocks); + printf("MaxSize(byte): %5d \n", File[i].attribute.FileMaxSize); + PrintFileListProperty((_u16)File[i].attribute.Properties); + printf("%\n\n"); + } + } + printf("%\n"); + return RetVal;//0 means O.K + } + + void PrintFileListProperty(_u16 prop) + { + printf("Flags : "); + if (prop & SL_FS_INFO_MUST_COMMIT) + printf("Open file commit,"); + if (prop & SL_FS_INFO_BUNDLE_FILE) + printf("Open bundle commit,"); + if (prop & SL_FS_INFO_PENDING_COMMIT) + printf("Pending file commit,"); + if (prop & SL_FS_INFO_PENDING_BUNDLE_COMMIT) + printf("Pending bundle commit,"); + if (prop & SL_FS_INFO_SECURE) + printf("Secure,"); + if (prop & SL_FS_INFO_NOT_FAILSAFE) + printf("File safe,"); + if (prop & SL_FS_INFO_SYS_FILE) + printf("System,"); + if (prop & SL_FS_INFO_NOT_VALID) + printf("No valid copy,"); + if (prop & SL_FS_INFO_PUBLIC_WRITE) + printf("Public write,"); + if (prop & SL_FS_INFO_PUBLIC_READ) + printf("Public read,"); + } + + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_FsGetFileList) +_i32 sl_FsGetFileList(_i32* pIndex, _u8 Count, _u8 MaxEntryLen , _u8* pBuff, SlFileListFlags_t Flags ); +#endif + +/*! + + Close the Doxygen group. + @} + + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __FS_H__ */ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netapp.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netapp.h new file mode 100755 index 00000000000..e10526907d1 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netapp.h @@ -0,0 +1,1334 @@ +/* + * netapp.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include + +#ifndef __NETAPP_H__ +#define __NETAPP_H__ + + + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup NetApp + \short Activates networking applications, such as: HTTP Server, DHCP Server, Ping, DNS and mDNS + +*/ + +/*! + + \addtogroup NetApp + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +/* NetApp user events */ +typedef enum +{ + SL_NETAPP_EVENT_IPV4_ACQUIRED = 1, + SL_NETAPP_EVENT_IPV6_ACQUIRED, + SL_NETAPP_EVENT_IP_COLLISION, + SL_NETAPP_EVENT_DHCPV4_LEASED, + SL_NETAPP_EVENT_DHCPV4_RELEASED, + SL_NETAPP_EVENT_HTTP_TOKEN_GET, + SL_NETAPP_EVENT_HTTP_TOKEN_POST, + SL_NETAPP_EVENT_IPV4_LOST, + SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT, + SL_NETAPP_EVENT_IPV6_LOST, + SL_NETAPP_EVENT_RESERVED1, + SL_NETAPP_EVENT_RESERVED2, + SL_NETAPP_EVENT_RESERVED3, + SL_NETAPP_EVENT_MAX +} SlNetAppEventId_e; + + +#define SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT 0x1 +#define SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT ((_u32)0x1 << 31) +#define SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT ((_u32)0x1 << 30) +#define SL_NETAPP_MDNS_OPTION_UPDATE_TEXT ((_u32)0x1 << 29) +#define SL_NETAPP_MDNS_IPV4_ONLY_SERVICE (_u32)(0) /* default mode:zero bits 27,28*/ +#define SL_NETAPP_MDNS_IPV6_ONLY_SERVICE ((_u32)0x1 << 28) +#define SL_NETAPP_MDNS_IPV6_IPV4_SERVICE ((_u32)0x1 << 27) + + +/*ERROR code*/ +#define SL_NETAPP_RX_BUFFER_LENGTH_ERROR (-230) + +/* Http Server interface */ +#define SL_NETAPP_MAX_INPUT_STRING (64) /* because of WPA */ + +#define SL_NETAPP_MAX_AUTH_NAME_LEN (20) +#define SL_NETAPP_MAX_AUTH_PASSWORD_LEN (20) +#define SL_NETAPP_MAX_AUTH_REALM_LEN (20) + +#define SL_NETAPP_MAX_DEVICE_URN_LEN (32+1) +#define SL_NETAPP_MAX_DOMAIN_NAME_LEN (24+1) + +#define SL_NETAPP_MAX_ACTION_LEN (30) +#define SL_NETAPP_MAX_TOKEN_NAME_LEN (20) + + +#define SL_NETAPP_MAX_TOKEN_VALUE_LEN SL_NETAPP_MAX_INPUT_STRING + +#define SL_NETAPP_MAX_SERVICE_TEXT_SIZE (256) +#define SL_NETAPP_MAX_SERVICE_NAME_SIZE (60) +#define SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE (64) + + +/* Server Responses */ +#define SL_NETAPP_HTTPRESPONSE_NONE (0) +#define SL_NETAPP_HTTPSETTOKENVALUE (1) + +#define SL_NETAPP_FAMILY_MASK (0x80) + +/* mDNS types */ +#define SL_NETAPP_MASK_IPP_TYPE_OF_SERVICE (0x00000001) +#define SL_NETAPP_MASK_DEVICE_INFO_TYPE_OF_SERVICE (0x00000002) +#define SL_NETAPP_MASK_HTTP_TYPE_OF_SERVICE (0x00000004) +#define SL_NETAPP_MASK_HTTPS_TYPE_OF_SERVICE (0x00000008) +#define SL_NETAPP_MASK_WORKSATION_TYPE_OF_SERVICE (0x00000010) +#define SL_NETAPP_MASK_GUID_TYPE_OF_SERVICE (0x00000020) +#define SL_NETAPP_MASK_H323_TYPE_OF_SERVICE (0x00000040) +#define SL_NETAPP_MASK_NTP_TYPE_OF_SERVICE (0x00000080) +#define SL_NETAPP_MASK_OBJECITVE_TYPE_OF_SERVICE (0x00000100) +#define SL_NETAPP_MASK_RDP_TYPE_OF_SERVICE (0x00000200) +#define SL_NETAPP_MASK_REMOTE_TYPE_OF_SERVICE (0x00000400) +#define SL_NETAPP_MASK_RTSP_TYPE_OF_SERVICE (0x00000800) +#define SL_NETAPP_MASK_SIP_TYPE_OF_SERVICE (0x00001000) +#define SL_NETAPP_MASK_SMB_TYPE_OF_SERVICE (0x00002000) +#define SL_NETAPP_MASK_SOAP_TYPE_OF_SERVICE (0x00004000) +#define SL_NETAPP_MASK_SSH_TYPE_OF_SERVICE (0x00008000) +#define SL_NETAPP_MASK_TELNET_TYPE_OF_SERVICE (0x00010000) +#define SL_NETAPP_MASK_TFTP_TYPE_OF_SERVICE (0x00020000) +#define SL_NETAPP_MASK_XMPP_CLIENT_TYPE_OF_SERVICE (0x00040000) +#define SL_NETAPP_MASK_RAOP_TYPE_OF_SERVICE (0x00080000) +#define SL_NETAPP_MASK_ALL_TYPE_OF_SERVICE (0xFFFFFFFF) + +/********************************************************************************************************/ + +/* NetApp application IDs */ +#define SL_NETAPP_HTTP_SERVER_ID (0x01) +#define SL_NETAPP_DHCP_SERVER_ID (0x02) +#define SL_NETAPP_MDNS_ID (0x04) +#define SL_NETAPP_DNS_SERVER_ID (0x08) + +#define SL_NETAPP_DEVICE_ID (0x10) +#define SL_NETAPP_DNS_CLIENT_ID (0x20) +#define SL_NETAPP_STATUS (0x40) + +/* NetApp application set/get options */ +#define SL_NETAPP_DHCP_SRV_BASIC_OPT (0) + +/* HTTP server set/get options */ +#define SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER (0) +#define SL_NETAPP_HTTP_AUTH_CHECK (1) +#define SL_NETAPP_HTTP_AUTH_NAME (2) +#define SL_NETAPP_HTTP_AUTH_PASSWORD (3) +#define SL_NETAPP_HTTP_AUTH_REALM (4) +#define SL_NETAPP_HTTP_ROM_PAGES_ACCESS (5) +#define SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER (6) +#define SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE (7) /*Enable / disable of secondary port */ +#define SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE (8) +#define SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME (9) +#define SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME (10) +#define SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME (11) +#define SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME (12) +#define SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME (13) +#define SL_NETAPP_HTTP_TIMEOUT (14) + + +#define SL_NETAPP_MDNS_CONT_QUERY_OPT (1) +#define SL_NETAPP_MDNS_QEVETN_MASK_OPT (2) +#define SL_NETAPP_MDNS_TIMING_PARAMS_OPT (3) + +/* DNS server set/get options */ +#define SL_NETAPP_DNS_OPT_DOMAIN_NAME (0) + +/* Device Config set/get options */ +#define SL_NETAPP_DEVICE_URN (0) +#define SL_NETAPP_DEVICE_DOMAIN (1) + +/* DNS client set/get options */ +#define SL_NETAPP_DNS_CLIENT_TIME (0) + +/* Get active application bimap */ +#define SL_NETAPP_STATUS_ACTIVE_APP (0) + +#ifdef SL_TINY +#define SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH (63) +#else +#define SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH (255) +#endif + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +typedef struct +{ + _u32 Ip; + _u32 Gateway; + _u32 Dns; +}SlIpV4AcquiredAsync_t; + +typedef enum +{ + SL_BSD_IPV6_ACQUIRED_TYPE_LOCAL = 1, + SL_BSD_IPV6_ACQUIRED_TYPE_GLOBAL = 2 +}SlIpV6AcquiredAsyncType_e; + +typedef struct +{ + _u32 Ip[4]; + _u32 Dns[4]; +}SlIpV6AcquiredAsync_t; + +typedef struct +{ + _u32 IpAddress; + _u32 LeaseTime; + _u8 Mac[6]; + _u16 Padding; +}SlIpLeasedAsync_t; + +typedef struct +{ + _u32 IpAddress; + _u8 Mac[6]; + _u16 Reason; +}SlIpReleasedAsync_t; + +typedef struct +{ + _u32 IpAddress; + _u8 DhcpMac[6]; + _u8 ConflictMac[6]; +}SlIpCollisionAsync_t; + +typedef struct +{ + _i16 Status; + _u16 Padding; +}SlIpV4Lost_t; + +typedef struct +{ + _u32 IpLost[4]; +}SlIpV6Lost_t; + +typedef struct +{ + _i16 Status; + _u16 Padding; +}SlDhcpIpAcquireTimeout_t; + +typedef union +{ + SlIpV4AcquiredAsync_t IpAcquiredV4; /* SL_NETAPP_EVENT_IPV4_ACQUIRED */ + SlIpV6AcquiredAsync_t IpAcquiredV6; /* SL_NETAPP_EVENT_IPV6_ACQUIRED */ + _u32 Sd; /* SL_SOCKET_TX_FAILED_EVENT */ + SlIpLeasedAsync_t IpLeased; /* SL_NETAPP_EVENT_DHCPV4_LEASED */ + SlIpReleasedAsync_t IpReleased; /* SL_NETAPP_EVENT_DHCPV4_RELEASED */ + SlIpV4Lost_t IpV4Lost; /* SL_NETAPP_EVENT_IPV4_LOST */ + SlDhcpIpAcquireTimeout_t DhcpIpAcquireTimeout; /* SL_NETAPP_DHCP_ACQUIRE_IPV4_TIMEOUT_EVENT */ + SlIpCollisionAsync_t IpCollision; /* SL_NETAPP_EVENT_IP_COLLISION */ + SlIpV6Lost_t IpV6Lost; /* SL_NETAPP_EVENT_IPV6_LOST */ +} SlNetAppEventData_u; + +typedef struct +{ + _u32 Id; + SlNetAppEventData_u Data; +}SlNetAppEvent_t; + +typedef struct +{ + _u32 PacketsSent; + _u32 PacketsReceived; + _u16 MinRoundTime; + _u16 MaxRoundTime; + _u16 AvgRoundTime; + _u32 TestTime; +}SlNetAppPingReport_t; + +typedef struct +{ + _u32 PingIntervalTime; /* delay between pings, in milliseconds */ + _u16 PingSize; /* ping packet size in bytes */ + _u16 PingRequestTimeout; /* timeout time for every ping in milliseconds */ + _u32 TotalNumberOfAttempts; /* max number of ping requests. 0 - forever */ + _u32 Flags; /* flag - 0 report only when finished, 1 - return response for every ping, 2 - stop after 1 successful ping. 4 - ipv4 header flag - don`t fragment packet */ + _u32 Ip; /* IPv4 address or IPv6 first 4 bytes */ + _u32 Ip1OrPadding; + _u32 Ip2OrPadding; + _u32 Ip3OrPadding; +}SlNetAppPingCommand_t; + +typedef struct +{ + _u8 Len; + _u8 *pData; +} SlNetAppHttpServerString_t; + +typedef struct +{ + _u8 ValueLen; + _u8 NameLen; + _u8 *pTokenValue; + _u8 *pTokenName; +} SlNetAppHttpServerData_t; + +typedef struct +{ + SlNetAppHttpServerString_t Action; + SlNetAppHttpServerString_t TokenName; + SlNetAppHttpServerString_t TokenValue; +}SlNetAppHttpServerPostData_t; + +typedef union +{ + SlNetAppHttpServerString_t HttpTokenName; /* SL_NETAPP_HTTPGETTOKENVALUE */ + SlNetAppHttpServerPostData_t HttpPostData; /* SL_NETAPP_HTTPPOSTTOKENVALUE */ +} SlNetAppHttpServerEventData_u; + +typedef union +{ + SlNetAppHttpServerString_t TokenValue; +} SlNetAppHttpServerResponsedata_u; + +typedef struct +{ + _u32 Event; + SlNetAppHttpServerEventData_u EventData; +}SlNetAppHttpServerEvent_t; + +typedef struct +{ + _u32 Response; + SlNetAppHttpServerResponsedata_u ResponseData; +}SlNetAppHttpServerResponse_t; + +/***************************************************************************************** +* NETAPP Request/Response/Send/Receive +******************************************************************************************/ +/* TODO: check what definitions are eventually needed */ +/* NETAPP http request types */ +#define SL_NETAPP_REQUEST_HTTP_GET 1 +#define SL_NETAPP_REQUEST_HTTP_POST 2 +#define SL_NETAPP_REQUEST_HTTP_PUT 3 +#define SL_NETAPP_REQUEST_HTTP_DELETE 4 + +#define SL_NETAPP_REQUEST_MAX_METADATA_LEN 1024 +#define SL_NETAPP_REQUEST_MAX_DATA_LEN 1364 /* Metadata + Payload */ + + +typedef enum +{ + SL_NETAPP_REQUEST_METADATA_TYPE_STATUS = 0, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_VERSION, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REQUEST_URI, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_QUERY_STRING, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_TYPE, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_LOCATION, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SERVER, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_USER_AGENT, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_COOKIE, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SET_COOKIE, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_UPGRADE, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REFERER, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ACCEPT, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_ENCODING, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_DISPOSITION, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONNECTION, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ETAG, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_DATE, + SL_NETAPP_REQUEST_METADATA_TYPE_HEADER_HOST, + SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_ENCODING, + SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_LANGUAGE, + SL_NETAPP_REQUEST_METADATA_TYPE_CONTENT_LANGUAGE, + SL_NETAPP_REQUEST_METADATA_TYPE_ORIGIN, + SL_NETAPP_REQUEST_METADATA_TYPE_ORIGIN_CONTROL_ACCESS, + SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_NONE +} SlNetAppMetadataHTTPTypes_e; + +typedef enum +{ + SL_NETAPP_RESPONSE_NONE = 0, /* No response */ + SL_NETAPP_RESPONSE_PENDING = 1, /* status will arrive in future NetApp Send call (in metadata) */ + + SL_NETAPP_HTTP_RESPONSE_101_SWITCHING_PROTOCOLS = 101, /* 101 Switching Protocol*/ + SL_NETAPP_HTTP_RESPONSE_200_OK = 200, /* 200 OK */ + SL_NETAPP_HTTP_RESPONSE_201_CREATED = 201, /* "HTTP/1.0 201 Created" */ + SL_NETAPP_HTTP_RESPONSE_202_ACCEPTED = 202, /* "HTTP/1.0 202 Accepted" */ + SL_NETAPP_HTTP_RESPONSE_204_OK_NO_CONTENT = 204, /* 204 No Content */ + SL_NETAPP_HTTP_RESPONSE_301_MOVED_PERMANENTLY = 301, /* "HTTP/1.0 301 Moved Permanently" */ + SL_NETAPP_HTTP_RESPONSE_302_MOVED_TEMPORARILY = 302, /* 302 Moved Temporarily (http 1.0) */ + SL_NETAPP_HTTP_RESPONSE_303_SEE_OTHER = 303, /* "HTTP/1.1 303 See Other" */ + SL_NETAPP_HTTP_RESPONSE_304_NOT_MODIFIED = 304, /* "HTTP/1.0 304 Not Modified" */ + SL_NETAPP_HTTP_RESPONSE_400_BAD_REQUEST = 400, /* "HTTP/1.0 400 Bad Request" */ + SL_NETAPP_HTTP_RESPONSE_403_FORBIDDEN = 403, /* "HTTP/1.0 403 Forbidden" */ + SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND = 404, /* 404 Not Found */ + SL_NETAPP_HTTP_RESPONSE_405_METHOD_NOT_ALLOWED = 405, /* "HTTP/1.0 405 Method Not Allowed" */ + SL_NETAPP_HTTP_RESPONSE_500_INTERNAL_SERVER_ERROR = 500, /* 500 Internal Server Error */ + SL_NETAPP_HTTP_RESPONSE_503_SERVICE_UNAVAILABLE = 503, /* "HTTP/1.0 503 Service Unavailable" */ + SL_NETAPP_HTTP_RESPONSE_504_GATEWAY_TIMEOUT = 504 /* "HTTP/1.0 504 Gateway Timeout" */ +} SlNetAppResponseCode_e; + + +#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION 0x00000001 +#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA 0x00000002 /* 0 - data is payload, 1 - data is metadata */ +#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_ACCUMULATION 0x00000004 +#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_ERROR 0x80000000 /* in that case the last two bytes represents the error code */ + +typedef struct +{ + _u16 MetadataLen; + _u8 *pMetadata; + _u16 PayloadLen; + _u8 *pPayload; + _u32 Flags; +} SlNetAppData_t; + +typedef struct +{ + _u8 AppId; + _u8 Type; + _u16 Handle; + SlNetAppData_t requestData; +} SlNetAppRequest_t; + +typedef struct +{ + _u16 Status; + SlNetAppData_t ResponseData; +} SlNetAppResponse_t; + +typedef struct +{ + _u32 lease_time; + _u32 ipv4_addr_start; + _u32 ipv4_addr_last; +}SlNetAppDhcpServerBasicOpt_t; + +/* mDNS parameters */ +typedef enum +{ + SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE = 1, + SL_NETAPP_FULL_SERVICE_IPV4_TYPE, + SL_NETAPP_SHORT_SERVICE_IPV4_TYPE, + SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE , + SL_NETAPP_FULL_SERVICE_IPV6_TYPE, + SL_NETAPP_SHORT_SERVICE_IPV6_TYPE +} SlNetAppGetServiceListType_e; + +typedef struct +{ + _u32 service_ipv4; + _u16 service_port; + _u16 Reserved; +}SlNetAppGetShortServiceIpv4List_t; + +typedef struct +{ + _u32 service_ipv4; + _u16 service_port; + _u16 Reserved; + _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; + _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; +}SlNetAppGetFullServiceIpv4List_t; + +typedef struct +{ + _u32 service_ipv4; + _u16 service_port; + _u16 Reserved; + _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; + _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; + _u8 service_text[SL_NETAPP_MAX_SERVICE_TEXT_SIZE]; +}SlNetAppGetFullServiceWithTextIpv4List_t; + +/* IPv6 entries */ +typedef struct +{ + _u32 service_ipv6[4]; + _u16 service_port; + _u16 Reserved; +}SlNetAppGetShortServiceIpv6List_t; + +typedef struct +{ + _u32 service_ipv6[4]; + _u16 service_port; + _u16 Reserved; + _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; + _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; +}SlNetAppGetFullServiceIpv6List_t; + +typedef struct +{ + _u32 service_ipv6[4]; + _u16 service_port; + _u16 Reserved; + _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; + _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; + _u8 service_text[SL_NETAPP_MAX_SERVICE_TEXT_SIZE]; +}SlNetAppGetFullServiceWithTextIpv6List_t; + +typedef struct +{ + /*The below parameters are used to configure the advertise times and interval + For example: + If: + Period is set to T + Repetitions are set to P + Telescopic factor is K=2 + The transmission shall be: + advertise P times + wait T + advertise P times + wait 4 * T + advertise P time + wait 16 * T ... (till max time reached / configuration changed / query issued) + */ + _u32 t; /* Number of ticks for the initial period. Default is 100 ticks for 1 second. */ + _u32 p; /* Number of repetitions. Default value is 1 */ + _u32 k; /* Telescopic factor. Default value is 2. */ + _u32 RetransInterval; /* Announcing retransmission interval */ + _u32 Maxinterval; /* Announcing max period interval */ + _u32 max_time; /* Announcing max time */ +}SlNetAppServiceAdvertiseTimingParameters_t; + +typedef struct +{ + _u16 MaxResponseTime; + _u16 NumOfRetries; +}SlNetAppDnsClientTime_t; + +/*****************************************************************************/ +/* Types declarations */ +/*****************************************************************************/ +typedef void (*P_SL_DEV_PING_CALLBACK)(SlNetAppPingReport_t*); + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + + +/*! + \brief Starts a network application + + Gets and starts network application for the current WLAN mode + + \param[in] AppBitMap Application bitmap, could be one or combination of the following: + - SL_NETAPP_HTTP_SERVER_ID + - SL_NETAPP_DHCP_SERVER_ID + - SL_NETAPP_MDNS_ID + - SL_NETAPP_DNS_SERVER_ID + + \par Persistent - System Persistent + \return Zero on success, or negative error code on failure + + \sa sl_NetAppStop + \note This command activates the application for the current WLAN mode (AP or STA) + \warning + \par Example + + - Starting internal HTTP server + DHCP server: + \code + sl_NetAppStart(SL_NETAPP_HTTP_SERVER_ID | SL_NETAPP_DHCP_SERVER_ID) + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppStart) +_i16 sl_NetAppStart(const _u32 AppBitMap); +#endif +/*! + \brief Stops a network application + + Gets and stops network application for the current WLAN mode + + \param[in] AppBitMap Application id, could be one of the following: \n + - SL_NETAPP_HTTP_SERVER_ID + - SL_NETAPP_DHCP_SERVER_ID + - SL_NETAPP_MDNS_ID + - SL_NETAPP_DNS_SERVER_ID + + \par Persistent - System Persistent + + \return Zero on success, or nagative error code on failure + + \sa sl_NetAppStart + \note This command disables the application for the current active WLAN mode (AP or STA) + \warning + \par Example + + - Stopping internal HTTP server: + \code + sl_NetAppStop(SL_NETAPP_HTTP_SERVER_ID); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppStop) +_i16 sl_NetAppStop(const _u32 AppBitMap); +#endif + +/*! + \brief Get host IP by name\n + Obtain the IP Address of machine on network, by machine name. + + \param[in] pHostName Host name + \param[in] NameLen Name length + \param[out] OutIpAddr This parameter is filled in with + host IP address. In case that host name is not + resolved, out_ip_addr is zero. + \param[in] Family Protocol family + + \return Zero on success, or negative on failure.\n + SL_POOL_IS_EMPTY may be return in case there are no resources in the system\n + In this case try again later or increase MAX_CONCURRENT_ACTIONS + Possible DNS error codes: + - SL_NETAPP_DNS_QUERY_NO_RESPONSE + - SL_NETAPP_DNS_NO_SERVER + - SL_NETAPP_DNS_QUERY_FAILED + - SL_NETAPP_DNS_MALFORMED_PACKET + - SL_NETAPP_DNS_MISMATCHED_RESPONSE + + \sa + \note Only one sl_NetAppDnsGetHostByName can be handled at a time.\n + Calling this API while the same command is called from another thread, may result + in one of the two scenarios: + 1. The command will wait (internal) until the previous command finish, and then be executed. + 2. There are not enough resources and POOL_IS_EMPTY error will return.\n + In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try + again later to issue the command. + \warning + In case an IP address in a string format is set as input, without any prefix (e.g. "1.2.3.4") the device will not + try to access the DNS and it will return the input address on the 'out_ip_addr' field + \par Example + + - Getting host by name: + \code + _u32 DestinationIP; + _u32 AddrSize; + _i16 SockId; + SlSockAddrIn_t Addr; + + sl_NetAppDnsGetHostByName("www.google.com", strlen("www.google.com"), &DestinationIP,SL_AF_INET); + + Addr.sin_family = SL_AF_INET; + Addr.sin_port = sl_Htons(80); + Addr.sin_addr.s_addr = sl_Htonl(DestinationIP); + AddrSize = sizeof(SlSockAddrIn_t); + SockId = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByName) +_i16 sl_NetAppDnsGetHostByName(_i8 * pHostName,const _u16 NameLen, _u32* OutIpAddr,const _u8 Family ); +#endif + +/*! + \brief Return service attributes like IP address, port and text according to service name\n + The user sets a service name Full/Part (see example below), and should get: + - IP of service + - The port of service + - The text of service + Hence it can make a connection to the specific service and use it. + It is similar to sl_NetAppDnsGetHostByName method.\n + It is done by a single shot ipv4 & ipv6 (if enabled) query with PTR type on the service name. + The command that is sent is from constant parameters and variables parameters. + + \param[in] pServiceName Service name can be full or partial. \n + Example for full service name: + 1. PC1._ipp._tcp.local + 2. PC2_server._ftp._tcp.local \n + . + Example for partial service name: + 1. _ipp._tcp.local + 2. _ftp._tcp.local + + \param[in] ServiceLen The length of the service name (in_pService). + \param[in] Family IPv4 or IPv6 (SL_AF_INET , SL_AF_INET6). + \param[out] pAddr Contains the IP address of the service. + \param[out] pPort Contains the port of the service. + \param[out] pTextLen Has 2 options. One as Input field and the other one as output: + - Input: \n + Contains the max length of the text that the user wants to get.\n + It means that if the text len of service is bigger that its value than + the text is cut to inout_TextLen value. + - Output: \n + Contain the length of the text that is returned. Can be full text or part of the text (see above). + + \param[out] pText Contains the text of the service full or partial + + \return Zero on success,\n + SL_POOL_IS_EMPTY may be return in case there are no resources in the system, + In this case try again later or increase MAX_CONCURRENT_ACTIONS\n + In case No service is found error SL_NETAPP_DNS_NO_ANSWER will be returned + \sa sl_NetAppDnsGetHostByName + \note The returns attributes belongs to the first service found. + There may be other services with the same service name that will response to the query. + The results of these responses are saved in the peer cache of the Device and should be read by another API.\n + + Only one sl_NetAppDnsGetHostByService can be handled at a time.\n + Calling this API while the same command is called from another thread, may result + in one of the two scenarios: + 1. The command will wait (internal) until the previous command finish, and then be executed. + 2. There are not enough resources and SL_POOL_IS_EMPTY error will return. + In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try + again later to issue the command. + + \warning Text length can be 120 bytes only +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByService) +_i16 sl_NetAppDnsGetHostByService(_i8 *pServiceName, /* string containing all (or only part): name + subtype + service */ + const _u8 ServiceLen, + const _u8 Family, /* 4-IPv4 , 16-IPv6 */ + _u32 pAddr[], + _u32 *pPort, + _u16 *pTextLen, /* in: max len , out: actual len */ + _i8 *pText + ); + +#endif + +/*! + \brief Get service list\n + Insert into out pBuffer a list of peer's services that are in the NWP without issuing any queries (relying on pervious collected data).\n + The list is in a form of service struct. The user should chose the type + of the service struct like: + - Full service parameters with text. + - Full service parameters. + - Short service parameters (port and IP only) especially for tiny hosts. + + The different types of struct are made to give the + possibility to save memory in the host.\n + + The user can also chose how many max services to get and start point index + NWP peer cache.\n + For example: + 1. Get max of 3 full services from index 0. + - Up to 3 full services from index 0 are inserted into pBuffer (services that are in indexes 0,1,2). + 2. Get max of 4 full services from index 3. + - Up to 4 full services from index 3 are inserted into pBuffer (services that are in indexes 3,4,5,6). + 3. Get max of 2 int services from index 6. + - Up to 2 int services from index 6 are inserted into pBuffer (services that are in indexes 6,7). + See below - command parameters. + + \param[in] IndexOffset - The start index in the peer cache that from it the first service is returned. + \param[in] MaxServiceCount - The Max services that can be returned if existed or if not exceed the max index + in the peer cache + \param[in] Flags - an ENUM number that means which service struct to use (means which types of service to fill) + - use SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE for SlNetAppGetFullServiceWithTextIpv4List_t + - use SL_NETAPP_FULL_SERVICE_IPV4_TYPE for SlNetAppGetFullServiceIpv4List_t + - use SL_NETAPP_SHORT_SERVICE_IPV4_TYP SlNetAppGetShortServiceIpv4List_t + - use SL_NETAPP_FULL_SERVICE_IPV6_TYPE, SlNetAppGetFullServiceIpv6List_t + - use SL_NETAPP_SHORT_SERVICE_IPV6_TYPE SlNetAppGetShortServiceIpv6List_t + - use SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE SlNetAppGetFullServiceWithTextIpv6List_t + + \param[out] pBuffer - The Services are inserted into this buffer. In the struct form according to the bit that is set in the Flags + input parameter. + + \param[in] BufferLength - The allocated buffer length (pointed by pBuffer). + + \return ServiceFoundCount - The number of the services that were inserted into the buffer.\n + Zero means no service is found negative number means an error + \sa sl_NetAppMDNSRegisterService + \note + \warning + If the out pBuffer size is bigger than an RX packet(1480), than + an error is returned because there is no place in the RX packet.\n + The size is a multiply of MaxServiceCount and size of service struct(that is set + according to flag value). +*/ + +#if _SL_INCLUDE_FUNC(sl_NetAppGetServiceList) +_i16 sl_NetAppGetServiceList(const _u8 IndexOffset, + const _u8 MaxServiceCount, + const _u8 Flags, + _i8 *pBuffer, + const _u32 BufferLength + ); + +#endif + +/*! + \brief Unregister mDNS service\n + This function deletes the mDNS service from the mDNS package and the database. + + The mDNS service that is to be unregistered is a service that the application no longer wishes to provide. \n + The service name should be the full service name according to RFC + of the DNS-SD - meaning the value in name field in the SRV answer. + + Examples for service names: + 1. PC1._ipp._tcp.local + 2. PC2_server._ftp._tcp.local + + \param[in] pServiceName Full service name. \n + \param[in] ServiceNameLen The length of the service. + \param[in] Options bitwise parameters: \n + - SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT bit 0 - service is unique per interface (means that the service needs to be unique) + - SL_NETAPP_MDNS_IPV6_IPV4_SERVICE bit 27 - add this service to IPv6 interface, if exist (default is IPv4 service only) + - SL_NETAPP_MDNS_IPV6_ONLY_SERVICE bit 28 - add this service to IPv6 interface, but remove it from IPv4 (only IPv6 is available) + - SL_NETAPP_MDNS_OPTION_UPDATE_TEXT bit 29 - for update text fields (without reregister the service) + - SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT bit 30 - for setting a non persistent service + - SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT bit 31 - for internal use if the service should be added or deleted (set means ADD). + + \return Zero on success, or negative error code on failure + \par Persistent - Optionally persistent + \sa sl_NetAppMDNSRegisterService + \note + \warning + The size of the service length should be smaller than 255. +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppMDNSUnRegisterService) +_i16 sl_NetAppMDNSUnRegisterService(const _i8 *pServiceName,const _u8 ServiceNameLen,_u32 Options); +#endif + +/*! + \brief Register a new mDNS service\n + This function registers a new mDNS service to the mDNS package and the DB. \n + This registered service is a service offered by the application. + The service name should be full service name according to RFC + of the DNS-SD - meaning the value in name field in the SRV answer.\n + Example for service name: + 1. PC1._ipp._tcp.local + 2. PC2_server._ftp._tcp.local + + If the option is_unique is set, mDNS probes the service name to make sure + it is unique before starting to announce the service on the network. + Instance is the instance portion of the service name. + + \param[in] ServiceNameLen The length of the service. + \param[in] TextLen The length of the service should be smaller than 64. + \param[in] Port The port on this target host port. + \param[in] TTL The TTL of the service + \param[in] Options bitwise parameters: \n + - SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT bit 0 - service is unique per interface (means that the service needs to be unique) + - SL_NETAPP_MDNS_IPV6_IPV4_SERVICE bit 27 - add this service to IPv6 interface, if exist (default is IPv4 service only) + - SL_NETAPP_MDNS_IPV6_ONLY_SERVICE bit 28 - add this service to IPv6 interface, but remove it from IPv4 (only IPv6 is available) + - SL_NETAPP_MDNS_OPTION_UPDATE_TEXT bit 29 - for update text fields (without reregister the service) + - SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT bit 30 - for setting a non persistent service + - SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT bit 31 - for internal use if the service should be added or deleted (set means ADD). + + \param[in] pServiceName The service name. + \param[in] pText The description of the service. + should be as mentioned in the RFC + (according to type of the service IPP,FTP...) + + \return Zero on success, or negative error code on failure + + \par Persistent - Optionally persistent + + \sa sl_NetAppMDNSUnRegisterService + + \warning 1) Temporary - there is an allocation on stack of internal buffer. + Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. \n + It means that the sum of the text length and service name length cannot be bigger than + SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.\n + If it is - An error is returned. \n + 2) According to now from certain constraints the variables parameters are set in the + attribute part (contain constant parameters) + + \par Examples: + + - Register a new service: + \code + const signed char AddService[40] = "PC1._ipp._tcp.local"; + _u32 Options; + + Options = SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT | SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT; + sl_NetAppMDNSRegisterService(AddService,sizeof(AddService),"Service 1;payper=A3;size=5",strlen("Service 1;payper=A3;size=5"),1000,120,Options); + \endcode +
+ + - Update text for existing service: + \code + Please Note! Update is for text only! Important to apply the same persistent flag options as original service registration.\n + + Options = SL_NETAPP_MDNS_OPTION_UPDATE_TEXT | SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT; + sl_NetAppMDNSRegisterService(AddService,sizeof(AddService),"Service 5;payper=A4;size=10",strlen("Service 5;payper=A4;size=10"),1000,120,Options); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) +_i16 sl_NetAppMDNSRegisterService( const _i8* pServiceName, + const _u8 ServiceNameLen, + const _i8* pText, + const _u8 TextLen, + const _u16 Port, + const _u32 TTL, + _u32 Options); +#endif + +/*! + \brief send ICMP ECHO_REQUEST to network hosts + + Ping uses the ICMP protocol's mandatory ECHO_REQUEST + + \param[in] pPingParams Pointer to the ping request structure: + - If flags parameter is set to 0, ping will report back once all requested pings are done (as defined by TotalNumberOfAttempts). + - If flags parameter is set to 1, ping will report back after every ping, for TotalNumberOfAttempts. + - If flags parameter is set to 2, ping will stop after the first successful ping, and report back for the successful ping, as well as any preceding failed ones. \n + - If flags parameter is set to 4, for ipv4 - don`t fragment the ping packet. This flag can be set with other flags. + For stopping an ongoing ping activity, set parameters IP address to 0 + \param[in] Family SL_AF_INET or SL_AF_INET6 + \param[out] pReport Ping pReport + \param[out] pPingCallback Callback function upon completion.\n + If callback is NULL, the API is blocked until data arrives + + \return Zero on success, or negative error code on failure.\n + SL_POOL_IS_EMPTY may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa + \note Only one sl_NetAppPing can be handled at a time. + Calling this API while the same command is called from another thread, may result + in one of the two scenarios: + 1. The command will wait (internal) until the previous command finish, and then be executed. + 2. There are not enough resources and SL_POOL_IS_EMPTY error will return. + In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try + again later to issue the command. + \warning + \par Example: + + - Sending 20 ping requests and reporting results to a callback routine when + all requests are sent: + \code + // callback routine + void pingRes(SlNetAppPingReport_t* pReport) + { + // handle ping results + } + + // ping activation + void PingTest() + { + SlNetAppPingReport_t report; + SlNetAppPingCommand_t pingCommand; + + pingCommand.Ip = SL_IPV4_VAL(10,1,1,200); // destination IP address is 10.1.1.200 + pingCommand.PingSize = 150; // size of ping, in bytes + pingCommand.PingIntervalTime = 100; // delay between pings, in milliseconds + pingCommand.PingRequestTimeout = 1000; // timeout for every ping in milliseconds + pingCommand.TotalNumberOfAttempts = 20; // max number of ping requests. 0 - forever + pingCommand.Flags = 0; // report only when finished + + sl_NetAppPing( &pingCommand, SL_AF_INET, &report, pingRes ); + } + \endcode +
+ + - Stopping Ping command: + \code + Status = sl_NetAppPing(0, 0, 0, 0 ); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppPing) +_i16 sl_NetAppPing(const SlNetAppPingCommand_t* pPingParams,const _u8 Family, SlNetAppPingReport_t *pReport, const P_SL_DEV_PING_CALLBACK pPingCallback); +#endif + +/*! + \brief Setting network application configurations + + \param[in] AppId Application id, could be one of the following: + - SL_NETAPP_HTTP_SERVER_ID + - SL_NETAPP_DHCP_SERVER_ID (AP Role only) + - SL_NETAPP_MDNS_ID + - SL_NETAPP_DNS_SERVER_ID + - SL_NETAPP_DEVICE_ID + - SL_NETAPP_DNS_CLIENT_ID + + \param[in] Option Set option, could be one of the following: + - For SL_NETAPP_HTTP_SERVER_ID + - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER + - SL_NETAPP_HTTP_AUTH_CHECK + - SL_NETAPP_HTTP_AUTH_NAME + - SL_NETAPP_HTTP_AUTH_PASSWORD + - SL_NETAPP_HTTP_AUTH_REALM + - SL_NETAPP_HTTP_ROM_PAGES_ACCESS + - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER + - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE + - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE + - SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME + - SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME + - SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME + - SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME + - SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME + - SL_NETAPP_HTTP_TIMEOUT + - For SL_NETAPP_DHCP_SERVER_ID: + - SL_NETAPP_DHCP_SRV_BASIC_OPT + - For SL_NETAPP_MDNS_ID: + - SL_NETAPP_MDNS_CONT_QUERY_OPT + - SL_NETAPP_MDNS_QEVETN_MASK_OPT + - SL_NETAPP_MDNS_TIMING_PARAMS_OPT + - For SL_NETAPP_DEVICE_ID: + - SL_NETAPP_DEVICE_URN + - SL_NETAPP_DEVICE_DOMAIN + - For SL_NETAPP_DNS_CLIENT_ID: + - SL_NETAPP_DNS_CLIENT_TIME + \param[in] OptionLen Option structure length + + \param[in] pOptionValue Pointer to the option structure + + \par Persistent + \par + Reset: + - SL_NETAPP_DEVICE_DOMAIN + - SL_NETAPP_DHCP_SRV_BASIC_OPT \n + \par + Non- Persistent: + - SL_NETAPP_HTTP_TIMEOUT + - SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME + - SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME \n + \par + System Persistent: + - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER + - SL_NETAPP_HTTP_AUTH_CHECK + - SL_NETAPP_HTTP_AUTH_NAME + - SL_NETAPP_HTTP_AUTH_PASSWORD + - SL_NETAPP_HTTP_AUTH_REALM + - SL_NETAPP_HTTP_ROM_PAGES_ACCESS + - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER + - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE + - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE + - SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME + - SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME + - SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME + - SL_NETAPP_MDNS_CONT_QUERY_OPT + - SL_NETAPP_MDNS_QEVETN_MASK_OPT + - SL_NETAPP_MDNS_TIMING_PARAMS_OPT + - SL_NETAPP_DEVICE_URN + - SL_NETAPP_DEVICE_ID + - SL_NETAPP_DNS_CLIENT_ID + + \return Zero on success, or negative value if an error occurred. + \sa sl_NetAppGet + \note + \warning + \par Example + + - Setting DHCP Server (AP mode) parameters example: + \code + SlNetAppDhcpServerBasicOpt_t dhcpParams; + _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t); + dhcpParams.lease_time = 4096; // lease time (in seconds) of the IP Address + dhcpParams.ipv4_addr_start = SL_IPV4_VAL(192,168,1,10); // first IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1) + dhcpParams.ipv4_addr_last = SL_IPV4_VAL(192,168,1,16); // last IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1) + sl_NetAppStop(SL_NETAPP_DHCP_SERVER_ID); // Stop DHCP server before settings + sl_NetAppSet(SL_NETAPP_DHCP_SERVER_ID, SL_NETAPP_DHCP_SRV_BASIC_OPT, outLen, (_u8* )&dhcpParams); // set parameters + sl_NetAppStart(SL_NETAPP_DHCP_SERVER_ID); // Start DHCP server with new settings + \endcode +
+ + - Setting Device URN name:
+ Device name, maximum length of 32 characters + Device name affects URN name, and WPS file "device name" in WPS I.E (STA-WPS / P2P) + In case no device URN name set, the default name is "mysimplelink" + In case of setting the device name with length 0, device will return to default name "mysimplelink" + Allowed characters in device name are: 'a - z' , 'A - Z' , '0-9' and '-' + \code + _u8 *my_device = "MY-SIMPLELINK-DEV"; + sl_NetAppSet (SL_NETAPP_DEVICE_ID, SL_NETAPP_DEVICE_URN, strlen(my_device), (_u8 *) my_device); + \endcode +
+ + - Register new temporary HTTP service name for MDNS (not persistent): + \code + _u8 *my_http_temp_name = "New - Bonjour Service Name"; + sl_NetAppSet (SL_NETAPP_HTTP_SERVER_ID, SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME, strlen(my_http_temp_name), (_u8 *) my_http_temp_name); + \endcode +
+ + - Remove registration of current HTTP internal MDNS service (not persistent) : + \code + _u8 *old_http_name = "0800285A7891@mysimplelink-022"; + sl_NetAppSet (SL_NETAPP_HTTP_SERVER_ID, SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME, strlen(old_http_name), (_u8 *) old_http_name); + \endcode +
+ + - Set DNS client time example:
+ Set DNS client (sl_NetAppDnsGetHostByName) timeout, two parameters max_response_time and number_retries. + number_retries: Max number of DNS request before sl_NetAppDnsGetHostByName failed, (up to 100 retries). + max_response_time: DNS request timeout changed every retry, it`s start with 100 millisecond and increased every retry up to max_response_time milliseconds, (up to 2 seconds) + \code + SlNetAppDnsClientTime_t time; + time.MaxResponseTime = 2000; + time.NumOfRetries = 30; + sl_NetAppSet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, sizeof(time), (_u8 *)&time); + + \endcode +
+ + + - Start MDNS continuous querys:
+ In a continuous mDNS query mode, the device keeps sending queries to the network according to a specific service name. + The query will be sent in IPv4 and IPv6 (if enabled) format. To see the completed list of responding services sl_NetAppGetServiceList() need to be called + \code + const signed char AddService[40] = "Printer._ipp._tcp.local"; + _i16 Status; + + Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_CONT_QUERY_OPT,strlen(AddService) , &AddService); + \endcode +
+ + - Stop MDNS: + \code + Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_CONT_QUERY_OPT,0 , 0); + \endcode +
+ + - Set MDNS timing parameters for service advertisement:
+ This option allows to control and reconfigures the timing parameters for service advertisement + \code + SlNetAppServiceAdvertiseTimingParameters_t Timing; + _i16 Status; + + Timing.t = 200; // 2 seconds + Timing.p = 2; // 2 repetitions + Timing.k = 2; // Telescopic factor 2 + Timing.RetransInterval = 0; + Timing.Maxinterval = 0xFFFFFFFF; + Timing.max_time = 5; + + Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_TIMING_PARAMS_OPT,sizeof(Timing),&Timing); + + \endcode +
+ + - User-defined service types to monitor:
+ In cases that the user decides not to get responses from certain + types of services it should set the adapt bit in the event mask that is related to: + \code + // bit 0: _ipp + // bit 1: _device-info + // bit 2: _http + // bit 3: _https + // bit 4: _workstation + // bit 5: _guid + // bit 6: _h323 + // bit 7: _ntp + // bit 8: _objective + // bit 9: _rdp + // bit 10: _remote + // bit 11: _rtsp + // bit 12: _sip + // bit 13: _smb + // bit 14: _soap + // bit 15: _ssh + // bit 16: _telnet + // bit 17: _tftp + // bit 18: _xmpp-client + // bit 19: _raop + + _u32 EventMask; + _i16 Status; + + EventMask = BIT0 | BIT1 | BIT18; + Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_QEVETN_MASK_OPT,sizeof(EventMask),&EventMask); + \endcode +
+*/ +#if _SL_INCLUDE_FUNC(sl_NetAppSet) +_i16 sl_NetAppSet(const _u8 AppId ,const _u8 Option,const _u8 OptionLen,const _u8 *pOptionValue); +#endif + +/*! + \brief Getting network applications configurations + + \param[in] AppId Application id, could be one of the following: \n + - SL_NETAPP_HTTP_SERVER_ID + - SL_NETAPP_DHCP_SERVER_ID + - SL_NETAPP_DNS_SERVER_ID + - SL_NETAPP_DEVICE_ID + - SL_NETAPP_DNS_CLIENT_ID + + \param[in] Option Get option, could be one of the following: \n + - SL_NETAPP_DHCP_SERVER_ID: + - SL_NETAPP_DHCP_SRV_BASIC_OPT + - SL_NETAPP_HTTP_SERVER_ID: + - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER + - SL_NETAPP_HTTP_AUTH_CHECK + - SL_NETAPP_HTTP_AUTH_NAME + - SL_NETAPP_HTTP_AUTH_PASSWORD + - SL_NETAPP_HTTP_AUTH_REALM + - SL_NETAPP_HTTP_ROM_PAGES_ACCESS + - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER + - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE + - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE + - SL_NETAPP_MDNS_ID: + - SL_NETAPP_MDNS_CONT_QUERY_OPT + - SL_NETAPP_MDNS_QEVETN_MASK_OPT + - SL_NETAPP_MDNS_TIMING_PARAMS_OPT + - SL_NETAPP_DEVICE_ID: + - SL_NETAPP_DEVICE_URN + - SL_NETAPP_DEVICE_DOMAIN + - SL_NETAPP_DNS_CLIENT_ID: + - SL_NETAPP_DNS_CLIENT_TIME + + \param[in] pOptionLen The length of the allocated memory as input, when the + function complete, the value of this parameter would be + the len that actually read from the device.\n + If the device return length that is longer from the input + value, the function will cut the end of the returned structure + and will return ESMALLBUF + + \param[out] pOptionValue pointer to the option structure which will be filled with the response from the device + + \return Zero on success, or negative value if an error occurred. + + \sa sl_NetAppSet + \note + \warning + \par Example + + - Getting DHCP Server parameters example: + \code + SlNetAppDhcpServerBasicOpt_t dhcpParams; + _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t); + sl_NetAppGet(SL_NETAPP_DHCP_SERVER_ID, SL_NETAPP_SET_DHCP_SRV_BASIC_OPT, &outLen, (_u8* )&dhcpParams); + + printf("DHCP Start IP %d.%d.%d.%d End IP %d.%d.%d.%d Lease time seconds %d\n", + SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,3),SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,2), + SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,1),SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,0), + SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,3),SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,2), + SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,1),SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,0), + dhcpParams.lease_time); + \endcode +
+ + - Getting device URN name:
+ Maximum length of 32 characters of device name. + Device name affects URN name, own SSID name in AP mode, and WPS file "device name" in WPS I.E (STA-WPS / P2P) + in case no device URN name set, the default name is "mysimplelink" + \code + _u8 my_device_name[SL_NETAPP_MAX_DEVICE_URN_LEN]; + sl_NetAppGet (SL_NETAPP_DEVICE_ID, SL_NETAPP_DEVICE_URN, strlen(my_device_name), (_u8 *)my_device_name); + \endcode +
+ + - Getting DNS client time:
+ Get DNS client (sl_NetAppDnsGetHostByName) timeout, two parameters max_response_time and number_retries. + number_retries: Max number of DNS request before sl_NetAppDnsGetHostByName failed. + max_response_time: DNS request timeout changed every retry, it`s start with 100 millisecond and increased every retry up to max_response_time milliseconds + \code + SlNetAppDnsClientTime_t time; + _u8 pOptionLen = sizeof(time); + sl_NetAppGet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, &pOptionLen, (_u8 *)&time); + \endcode +
+ + + - Getting active applications:
+ Get active applications for active role. return value is mask of the active application (similar defines as sl_NetAppStart\sl_NetAppStop): + \code + _u32 AppBitMap; + _u8 pOptionLen = sizeof(AppBitMap); + sl_NetAppGet (SL_NETAPP_STATUS, SL_NETAPP_STATUS_ACTIVE_APP, &pOptionLen, (_u8 *)&AppBitMap); + + \endcode + +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppGet) +_i16 sl_NetAppGet(const _u8 AppId, const _u8 Option,_u8 *pOptionLen, _u8 *pOptionValue); +#endif + +/*! + \brief Function for sending Netapp response or data following a Netapp request event (i.e. HTTP GET request) + + + \param[in] Handle Handle to send the data to. Should match the handle received in the Netapp request event + \param[in] DataLen Data Length + \param[in] pData Data to send. Can be just data payload or metadata (depends on flags) + \param[out] Flags Can have the following values: + - SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION - More data will arrive in subsequent calls to NetAppSend + - SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA - 0 - data is payload, 1 - data is metadata + - SL_NETAPP_REQUEST_RESPONSE_FLAGS_ACCUMULATION - The network processor should accumulate the data chunks and will process it when it is completelly received + + \return Zero on success, or negative error code on failure + + \sa sl_NetAppRecv + \note + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppSend) +_u16 sl_NetAppSend( _u16 Handle, _u16 DataLen, _u8 *pData, _u32 Flags); +#endif + +/*! + \brief Function for retrieving data from the network processor following a Netapp request event (i.e. HTTP POST request) + + \param[in] Handle Handle to receive data from. Should match the handle received in the Netapp request event + \param[in,out] *DataLen Max buffer size (in) / Actual data received (out) + \param[out] *pData Data received + \param[in,out] *Flags Can have the following values: + - SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION (out) + - More data is pending in the network processor. Application should continue reading the data by calling sl_NetAppRecv again + + \return Zero on success, or negative error code on failure + + \sa sl_NetAppSend + \note + \warning handle is received in the sl_NetAppRequestHandler callback. Handle is valid until all data is receive from the network processor. +*/ +#if _SL_INCLUDE_FUNC(sl_NetAppRecv) +_SlReturnVal_t sl_NetAppRecv( _u16 Handle, _u16 *DataLen, _u8 *pData, _u32 *Flags); +#endif + +/*! + + Close the Doxygen group. + @} + + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NETAPP_H__ */ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netcfg.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netcfg.h new file mode 100755 index 00000000000..26c9ef8ba1e --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netcfg.h @@ -0,0 +1,663 @@ +/* + * netcfg.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include + + +#ifndef __NETCFG_H__ +#define __NETCFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup NetCfg + \short Controls the configuration of the device addresses (i.e. IP and MAC addresses) + +*/ + +/*! + + \addtogroup NetCfg + @{ + +*/ + + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +#define SL_MAC_ADDR_LEN (6) +#define SL_IPV6_ADDR_LEN (16) +#define SL_IPV4_VAL(add_3,add_2,add_1,add_0) ((((_u32)add_3 << 24) & 0xFF000000) | (((_u32)add_2 << 16) & 0xFF0000) | (((_u32)add_1 << 8) & 0xFF00) | ((_u32)add_0 & 0xFF) ) +#define SL_IPV6_VAL(add_1,add_2) ((((_u32)add_1 << 16) & 0xFFFF0000) | (((_u32)add_2 ) & 0x0000FFFF) ) +#define SL_IPV4_BYTE(val,index) ( (val >> (index*8)) & 0xFF ) + + +#define SL_NETCFG_IF_IPV6_STA_LOCAL (0x4) /* disable ipv6 local */ +#define SL_NETCFG_IF_IPV6_STA_GLOBAL (0x8) /* disable ipv6 global */ +#define SL_NETCFG_IF_DISABLE_IPV4_DHCP (0x40) /* disable ipv4 dhcp */ +#define SL_NETCFG_IF_IPV6_LOCAL_STATIC (0x80) /* enable ipv6 local static */ +#define SL_NETCFG_IF_IPV6_LOCAL_STATELESS (0x100) /* enable ipv6 local stateless */ +#define SL_NETCFG_IF_IPV6_LOCAL_STATEFUL (0x200) /* enable ipv6 local statefull */ +#define SL_NETCFG_IF_IPV6_GLOBAL_STATIC (0x400) /* enable ipv6 global static */ +#define SL_NETCFG_IF_IPV6_GLOBAL_STATEFUL (0x800) /* enable ipv6 global statefull */ +#define SL_NETCFG_IF_DISABLE_IPV4_LLA (0x1000) /* disable LLA feature. Relevant only in IPV4 */ +#define SL_NETCFG_IF_ENABLE_DHCP_RELEASE (0x2000) /* Enables DHCP release when WLAN disconnect command is issued */ +#define SL_NETCFG_IF_IPV6_GLOBAL_STATELESS (0x4000) /* enable ipv6 global stateless */ +#define SL_NETCFG_IF_DISABLE_FAST_RENEW (0x8000) /* fast renew disabled */ + + +#define SL_NETCFG_IF_STATE (0) +#define SL_NETCFG_ADDR_DHCP (1) +#define SL_NETCFG_ADDR_DHCP_LLA (2) +#define SL_NETCFG_ADDR_STATIC (4) +#define SL_NETCFG_ADDR_STATELESS (5) +#define SL_NETCFG_ADDR_STATEFUL (6) +#define SL_NETCFG_ADDR_RELEASE_IP_SET (7) +#define SL_NETCFG_ADDR_RELEASE_IP_OFF (8) +#define SL_NETCFG_ADDR_ENABLE_FAST_RENEW (9) +#define SL_NETCFG_ADDR_DISABLE_FAST_RENEW (10) +#define SL_NETCFG_ADDR_FAST_RENEW_MODE_NO_WAIT_ACK (11) +#define SL_NETCFG_ADDR_FAST_RENEW_MODE_WAIT_ACK (12) + + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ +typedef enum +{ + SL_NETCFG_MAC_ADDRESS_SET = 1, + SL_NETCFG_MAC_ADDRESS_GET = 2, + SL_NETCFG_AP_STATIONS_NUM_CONNECTED = 3, + SL_NETCFG_AP_STATIONS_INFO_LIST = 4, + SL_NETCFG_AP_STATION_DISCONNECT = 5, + SL_NETCFG_IF = 6, + SL_NETCFG_IPV4_STA_ADDR_MODE = 7, + SL_NETCFG_IPV4_AP_ADDR_MODE = 8, + SL_NETCFG_IPV6_ADDR_LOCAL = 9, + SL_NETCFG_IPV6_ADDR_GLOBAL = 10, + SL_NETCFG_IPV4_DHCP_CLIENT = 11, + SL_NETCFG_IPV4_DNS_CLIENT = 12, + SL_NETCFG_RESERVED = 13, + MAX_SETTINGS = 0xFF +}SlNetCfg_e; + +typedef struct +{ + _u32 DnsSecondServerAddr; +}SlNetCfgIpV4DnsClientArgs_t; + + +typedef struct +{ + _u32 Ip; + _u32 Gateway; + _u32 Mask; + _u32 Dns[2]; + _u32 DhcpServer; + _u32 LeaseTime; + _u32 TimeToRenew; + _u8 DhcpState; + _u8 Reserved[3]; +} SlNetCfgIpv4DhcpClient_t; + +typedef enum +{ + SL_NETCFG_DHCP_CLIENT_UNKNOWN = 0, + SL_NETCFG_DHCP_CLIENT_DISABLED, + SL_NETCFG_DHCP_CLIENT_ENABLED, + SL_NETCFG_DHCP_CLIENT_BOUND, + SL_NETCFG_DHCP_CLIENT_RENEW, + SL_NETCFG_DHCP_CLIENT_REBIND +}SlNetCfgIpv4DhcpClientState_e; + + +typedef enum +{ + SL_NETCFG_DHCP_OPT_DISABLE_LLA = 0x2, /* 1=LLA disabled, 0=LLA enabled. */ + SL_NETCFG_DHCP_OPT_RELEASE_IP_BEFORE_DISCONNECT = 0x4, /* 1=DHCP release enabled, 0=DHCP release disabled */ + MAX_SL_NETCFG_DHCP_OPT = 0xFF +} SlNetCfgDhcpOption_e; + +typedef struct +{ + _u32 Ip; + _u32 IpMask; + _u32 IpGateway; + _u32 IpDnsServer; +}SlNetCfgIpV4Args_t; + +typedef struct +{ + _u32 Ip[4]; + _u32 IpDnsServer[4]; + _u32 IpV6Flags; /* bit 0: Indicate if the address is valid for use in the network (IPv6 DAD completed) . If not, try again later or set a different address. 1=Valid. Relevant for sl_NetCfgGet only. */ +}SlNetCfgIpV6Args_t; + +#define _SL_NETCFG_IPV6_ADDR_BIT_STATUS 0x01 +#define SL_IS_IPV6_ADDR_VALID(IpV6Flags) (IpV6Flags & _SL_NETCFG_IPV6_ADDR_BIT_STATUS) + +#define NET_CFG_STA_INFO_STATUS_DHCP_ADDR 1 + +typedef struct +{ + _u32 Ip; + _u8 MacAddr[6]; + _u16 Status; + _u8 Name[32]; +} SlNetCfgStaInfo_t; + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +/*! + \brief Setting network configurations + + \param[in] ConfigId Configuration id: + - SL_NETCFG_IF + - SL_NETCFG_IPV4_STA_ADDR_MODE + - SL_NETCFG_IPV6_ADDR_LOCAL + - SL_NETCFG_IPV6_ADDR_GLOBAL + - SL_NETCFG_IPV4_AP_ADDR_MODE + - SL_NETCFG_MAC_ADDRESS_SET + - SL_NETCFG_AP_STATION_DISCONNECT + \param[in] ConfigOpt Configurations option: + - SL_NETCFG_IF_STATE + - SL_NETCFG_ADDR_DHCP + - SL_NETCFG_ADDR_DHCP_LLA + - SL_NETCFG_ADDR_STATIC + - SL_NETCFG_ADDR_STATELESS + - SL_NETCFG_ADDR_STATEFUL + - SL_NETCFG_ADDR_RELEASE_IP_SET + - SL_NETCFG_ADDR_RELEASE_IP_OFF + \param[in] ConfigLen Configurations len + \param[in] pValues Configurations values + \par Persistent + \par + Reset: + - SL_NETCFG_MAC_ADDRESS_SET + - SL_NETCFG_IPV4_AP_ADDR_MODE + \par + Non- Persistent: + - SL_NETCFG_AP_STATION_DISCONNECT + \par + System Persistent: + - SL_NETCFG_IPV4_STA_ADDR_MODE + - SL_NETCFG_IF + - SL_NETCFG_IPV6_ADDR_LOCAL + - SL_NETCFG_IPV6_ADDR_GLOBAL + + \return Non-negative value on success, or -1 for failure + \sa sl_NetCfgGet + \note + \warning + + \par Examples + + - SL_NETCFG_MAC_ADDRESS_SET:
+ Setting MAC address to the Device. + The new MAC address will override the default MAC address and it be saved in the FileSystem. + Requires restarting the device for updating this setting. + \code + _u8 MAC_Address[6]; + MAC_Address[0] = 0x8; + MAC_Address[1] = 0x0; + MAC_Address[2] = 0x28; + MAC_Address[3] = 0x22; + MAC_Address[4] = 0x69; + MAC_Address[5] = 0x31; + sl_NetCfgSet(SL_NETCFG_MAC_ADDRESS_SET,1,SL_MAC_ADDR_LEN,(_u8 *)MAC_Address); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_IPV4_STA_ADDR_MODE
: + Setting/Releasing a DHCP/DHCP LLA /STATIC STA IP address + + - SL_NETCFG_ADDR_STATIC:
+ Setting a static IP address to the device working in STA mode or P2P client. + The IP address will be stored in the FileSystem. + \code + SlNetCfgIpV4Args_t ipV4; + ipV4.Ip = (_u32)SL_IPV4_VAL(10,1,1,201); // _u32 IP address + ipV4.IpMask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this STA/P2P + ipV4.IpGateway = (_u32)SL_IPV4_VAL(10,1,1,1); // _u32 Default gateway address + ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(8,16,32,64); // _u32 DNS server address + + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV4Args_t),(_u8 *)&ipV4); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_ADDR_DHCP:
+ Setting IP address by DHCP to FileSystem using WLAN sta mode or P2P client. + This should be done once if using Serial Flash. + This is the system's default mode for acquiring an IP address after WLAN connection. + \code + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_DHCP,0,0); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_ADDR_DHCP_LLA:
+ Setting DHCP LLA will runs LLA mechanism in case DHCP fails to acquire an address + SL_NETCFG_DHCP_OPT_RELEASE_IP_BEFORE_DISCONNECT - If set, enables sending a DHCP release frame to the server if user issues a WLAN disconnect command. + \code + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_DHCP_LLA,0,0); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_ADDR_RELEASE_IP_SET:
+ Setting release ip before disconnect enables sending a DHCP release frame to the server if user issues a WLAN disconnect command. + \code + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_RELEASE_IP_SET,0,0); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_ADDR_RELEASE_IP_OFF:
+ Setting release ip before disconnect disables sending a DHCP release frame to the server if user issues a WLAN disconnect command. + \code + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_RELEASE_IP_OFF,0,0); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_IPV4_AP_ADDR_MODE:
+ Setting a static IP address to the device working in AP mode or P2P go. + The IP address will be stored in the FileSystem. Requires restart. + \code + SlNetCfgIpV4Args_t ipV4; + ipV4.Ip = (_u32)SL_IPV4_VAL(10,1,1,201); // _u32 IP address + ipV4.IpMask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this AP/P2P + ipV4.IpGateway = (_u32)SL_IPV4_VAL(10,1,1,1); // _u32 Default gateway address + ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(8,16,32,64); // _u32 DNS server address + + sl_NetCfgSet(SL_NETCFG_IPV4_AP_ADDR_MODE,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV4Args_t),(_u8 *)&ipV4); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_IF:
+ Enable\Disable IPV6 interface - Local or/and Global address (Global could not be enabled without Local) + \code + _u32 IfBitmap = 0; + + IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL | SL_NETCFG_IF_IPV6_STA_GLOBAL; + sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_IPV6_ADDR_LOCAL:
+ Setting a IPv6 Local static address to the device working in STA mode. + The IP address will be stored in the FileSystem. Requires restart. + \code + SlNetCfgIpV6Args_t ipV6; + _u32 IfBitmap = 0; + + IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; + sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); + + ipV6.Ip[0] = 0xfe800000; + ipV6.Ip[1] = 0x00000000; + ipV6.Ip[2] = 0x00004040; + ipV6.Ip[3] = 0x0000ce65; + + sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV6Args_t),(_u8 *)&ipV6); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_IPV6_ADDR_LOCAL:
+ Setting a IPv6 Local stateless address to the device working in STA mode. + The IP address will be stored in the FileSystem. Requires restart. + \code + _u32 IfBitmap = 0; + IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; + sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); + sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATELESS,0,0); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_IPV6_ADDR_LOCAL:
+ Setting a IPv6 Local statefull address to the device working in STA mode. + The IP address will be stored in the FileSystem. Requires restart. + \code + _u32 IfBitmap = 0; + + IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; + sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); + sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATEFUL,0,0); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_IPV6_ADDR_GLOBAL:
+ Setting a IPv6 Global static address to the device working in STA mode. + The IP address will be stored in the FileSystem. Requires restart. + \code + SlNetCfgIpV6Args_t ipV6; + _u32 IfBitmap = 0; + + ipV6.Ip[0] = 0xfe80; + ipV6.Ip[1] = 0x03a; + ipV6.Ip[2] = 0x4040; + ipV6.Ip[3] = 0xce65; + + ipV6.IpDnsServer[0] = 0xa780; + ipV6.IpDnsServer[1] = 0x65e; + ipV6.IpDnsServer[2] = 0x8; + ipV6.IpDnsServer[3] = 0xce00; + + IfBitmap = SL_NETCFG_IF_IPV6_STA_GLOBAL; + sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); + sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_GLOBAL,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV6Args_t),(_u8 *)&ipV6); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_IPV6_ADDR_GLOBAL:
+ Setting a IPv6 Global statefull address to the device working in STA mode. + The IP address will be stored in the FileSystem. Requires restart. + \code + _u32 IfBitmap = 0; + IfBitmap = SL_NETCFG_IF_IPV6_STA_GLOBAL; + sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); + sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_GLOBAL,SL_NETCFG_ADDR_STATEFUL,0,0); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode +
+ + - SL_NETCFG_AP_STATION_DISCONNECT:
+ Disconnect AP station by mac address. + The AP connected stations list can be read by sl_NetCfgGet with options: SL_AP_STATIONS_NUM_CONNECTED, SL_AP_STATIONS_INFO_LIST + \code + _u8 ap_sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; + sl_NetCfgSet(SL_NETCFG_AP_STATION_DISCONNECT,1,SL_MAC_ADDR_LEN,(_u8 *)ap_sta_mac); + \endcode +
+ + - SL_NETCFG_IPV4_DNS_CLIENT:
+ Set additional IPv4 DNS address + \code + _i32 Status; + SlNetCfgIpV4DnsClientArgs_t DnsOpt; + DnsOpt.DnsSecondServerAddr = SL_IPV4_VAL(8,8,8,8); ; + Status = sl_NetCfgSet(SL_NETCFG_IPV4_DNS_CLIENT,0,sizeof(SlNetCfgIpV4DnsClientArgs_t),(unsigned char *)&DnsOpt); + if( Status ) + { + // error + } + \endcode +
+ +*/ +#if _SL_INCLUDE_FUNC(sl_NetCfgSet) +_i16 sl_NetCfgSet(const _u16 ConfigId,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues); +#endif + + +/*! + \brief Getting network configurations + + \param[in] ConfigId Configuration id + + \param[out] pConfigOpt Get configurations option + + \param[out] pConfigLen The length of the allocated memory as input, when the + function complete, the value of this parameter would be + the len that actually read from the device.\n + If the device return length that is longer from the input + value, the function will cut the end of the returned structure + and will return ESMALLBUF + + \param[out] pValues - get configurations values + \return Zero on success, or -1 on failure + \sa sl_NetCfgSet + \note + \warning + \par Examples + + - SL_NETCFG_MAC_ADDRESS_GET:
+ Get the device MAC address. + The returned MAC address is taken from FileSystem first. If the MAC address was not set by SL_MAC_ADDRESS_SET, the default MAC address + is retrieved from HW. + \code + _u8 macAddressVal[SL_MAC_ADDR_LEN]; + _u16 macAddressLen = SL_MAC_ADDR_LEN; + _u16 ConfigOpt = 0; + sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,&ConfigOpt,&macAddressLen,(_u8 *)macAddressVal); + \endcode +
+ + - SL_NETCFG_IPV4_STA_ADDR_MODE:
+ Get IP address from WLAN station or P2P client. A DHCP flag is returned to indicate if the IP address is static or from DHCP. + \code + _u16 len = sizeof(SlNetCfgIpV4Args_t); + _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC + SlNetCfgIpV4Args_t ipV4 = {0}; + sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&len,(_u8 *)&ipV4); + + printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", + (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", + SL_IPV4_BYTE(ipV4.Ip,3),SL_IPV4_BYTE(ipV4.Ip,2),SL_IPV4_BYTE(ipV4.Ip,1),SL_IPV4_BYTE(ipV4.Ip,0), + SL_IPV4_BYTE(ipV4.IpMask,3),SL_IPV4_BYTE(ipV4.IpMask,2),SL_IPV4_BYTE(ipV4.IpMask,1),SL_IPV4_BYTE(ipV4.IpMask,0), + SL_IPV4_BYTE(ipV4.IpGateway,3),SL_IPV4_BYTE(ipV4.IpGateway,2),SL_IPV4_BYTE(ipV4.IpGateway,1),SL_IPV4_BYTE(ipV4.IpGateway,0), + SL_IPV4_BYTE(ipV4.IpDnsServer,3),SL_IPV4_BYTE(ipV4.IpDnsServer,2),SL_IPV4_BYTE(ipV4.IpDnsServer,1),SL_IPV4_BYTE(ipV4.IpDnsServer,0)); + \endcode +
+ + - SL_NETCFG_IPV4_AP_ADDR_MODE:
+ Get static IP address for AP or P2P go. + \code + _u16 len = sizeof(SlNetCfgIpV4Args_t); + _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC + SlNetCfgIpV4Args_t ipV4 = {0}; + sl_NetCfgGet(SL_NETCFG_IPV4_AP_ADDR_MODE,&ConfigOpt,&len,(_u8 *)&ipV4); + + printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", + (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", + SL_IPV4_BYTE(ipV4.Ip,3),SL_IPV4_BYTE(ipV4.Ip,2),SL_IPV4_BYTE(ipV4.Ip,1),SL_IPV4_BYTE(ipV4.Ip,0), + SL_IPV4_BYTE(ipV4.IpMask,3),SL_IPV4_BYTE(ipV4.IpMask,2),SL_IPV4_BYTE(ipV4.IpMask,1),SL_IPV4_BYTE(ipV4.IpMask,0), + SL_IPV4_BYTE(ipV4.IpGateway,3),SL_IPV4_BYTE(ipV4.IpGateway,2),SL_IPV4_BYTE(ipV4.IpGateway,1),SL_IPV4_BYTE(ipV4.IpGateway,0), + SL_IPV4_BYTE(ipV4.IpDnsServer,3),SL_IPV4_BYTE(ipV4.IpDnsServer,2),SL_IPV4_BYTE(ipV4.IpDnsServer,1),SL_IPV4_BYTE(ipV4.IpDnsServer,0)); + \endcode +
+ + - SL_NETCFG_IF:
+ Get interface bitmap + \code + _u16 len; + _u32 IfBitmap; + len = sizeof(IfBitmap); + sl_NetCfgGet(SL_NETCFG_IF,NULL,&len,(_u8 *)&IfBitmap); + \endcode +
+ + - SL_NETCFG_IPV6_ADDR_LOCAL:
+ Get IPV6 Local address (ipV6.ipV6IsValid holds the address status. 1=Valid, ipv6 DAD completed and address is valid for use) + \code + SlNetCfgIpV6Args_t ipV6; + _u16 len = sizeof(SlNetCfgIpV6Args_t); + _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_STATIC / SL_NETCFG_ADDR_STATELESS / SL_NETCFG_ADDR_STATEFUL + + sl_NetCfgGet(SL_NETCFG_IPV6_ADDR_LOCAL,&ConfigOpt,&len,(_u8 *)&ipV6); + if (SL_IS_IPV6_ADDR_VALID(ipV6.IpV6Flags)) + { + printf("Ipv6 Local Address is valid: %8x:%8x:%8x:%8x\n", ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0]); + } + else + { + printf("Ipv6 Local Address is not valid, wait for DAD to complete or configure a different address"); + } + + \endcode +
+ + - SL_NETCFG_IPV6_ADDR_GLOBAL:
+ Get IPV6 Global address (ipV6.ipV6IsValid holds the address status. 1=Valid, ipv6 DAD completed and address is valid for use) + \code + SlNetCfgIpV6Args_t ipV6; + _u16 len = sizeof(SlNetCfgIpV6Args_t); + _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_STATIC / SL_NETCFG_ADDR_STATEFUL + + if (SL_IS_IPV6_ADDR_VALID(ipV6.IpV6Flags)) + { + printf("Ipv6 Global Address is valid: %8x:%8x:%8x:%8x\n", ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0]); + } + else + { + printf("Ipv6 Global Address is not valid, wait for DAD to complete or configure a different address"); + } + + \endcode +
+ + - SL_NETCFG_AP_STATIONS_NUM_CONNECTED:
+ Get AP number of connected stations. + \code + _u8 num_ap_connected_sta; + _u16 len = sizeof(num_ap_connected_sta); + sl_NetCfgGet(SL_NETCFG_AP_STATIONS_NUM_CONNECTED, NULL, &len, &num_ap_connected_sta); + printf("AP number of connected stations = %d\n", num_ap_connected_sta); + + \endcode +
+ + - SL_NETCFG_AP_STATIONS_INFO_LIST:
+ Get AP full list of connected stationss. + \code + SlNetCfgStaInfo_t ApStaList[4]; + _u16 sta_info_len; + _u16 start_sta_index = 0; + int actual_num_sta; + int i; + + start_sta_index = 0; + sta_info_len = sizeof(ApStaList); + sl_NetCfgGet(SL_NETCFG_AP_STATIONS_INFO_LIST, &start_sta_index, &sta_info_len, (_u8 *)ApStaList); + + actual_num_sta = sta_info_len / sizeof(SlNetCfgStaInfo_t); + printf("-Print SL_NETCFG_AP_STATIONS_INFO_LIST actual num_stations = %d (upon sta_info_len = %d)\n", actual_num_sta, sta_info_len); + + for (i=0; iName); + printf(" MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", staInfo->MacAddr[0], staInfo->MacAddr[1], staInfo->MacAddr[2], staInfo->MacAddr[3], staInfo->MacAddr[4], staInfo->MacAddr[5]); + printf(" IP: %d.%d.%d.%d\n", SL_IPV4_BYTE(staInfo->Ip,3), SL_IPV4_BYTE(staInfo->Ip,2), SL_IPV4_BYTE(staInfo->Ip,1), SL_IPV4_BYTE(staInfo->Ip,0)); + } + + \endcode +
+ + - SL_NETCFG_IPV4_DNS_CLIENT:
+ Get secondary DNS address (DHCP and static configuration) + \code + _u16 ConfigOpt = 0; + _i32 Status; + _u16 pConfigLen = sizeof(SlNetCfgIpV4DnsClientArgs_t); + SlNetCfgIpV4DnsClientArgs_t DnsOpt; + Status = sl_NetCfgGet(SL_NETCFG_IPV4_DNS_CLIENT,&ConfigOpt,&pConfigLen,&DnsOpt); + if( Status ) + { + // error + } + \endcode +
+ + + - SL_NETCFG_IPV4_DHCP_CLIENT:
+ Get DHCP Client info + \code + _u16 ConfigOpt = 0; + _u16 pConfigLen = sizeof(SlNetCfgIpv4DhcpClient_t); + SlNetCfgIpv4DhcpClient_t dhcpCl; + SlNetCfgIpV4Args_t ipV4 = {0}; + + ret = sl_NetCfgGet(SL_NETCFG_IPV4_DHCP_CLIENT, &ConfigOpt, &pConfigLen, (_u8 *)&dhcpCl); + if(ret < 0) + { + printf("Error = %d\n", ret); + } + \endcode + +*/ +#if _SL_INCLUDE_FUNC(sl_NetCfgGet) +_i16 sl_NetCfgGet(const _u16 ConfigId ,_u16 *pConfigOpt, _u16 *pConfigLen, _u8 *pValues); +#endif + +/*! + + Close the Doxygen group. + @} + + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NETCFG_H__ */ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netutil.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netutil.h new file mode 100755 index 00000000000..f5b31b6ba0e --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/netutil.h @@ -0,0 +1,519 @@ +/* + * netutil.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef __NETUTIL_H__ +#define __NETUTIL_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup NetUtil + \short Networking related commands and configuration + +*/ + +/*! + + \addtogroup NetUtil + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +/* Set/get options */ +#define SL_NETUTIL_CRYPTO_PUBLIC_KEY (1) +#define SL_NETUTIL_CRYPTO_PUBLIC_KEY_INFO (2) +#define SL_NETUTIL_TRUE_RANDOM (3) + +/* Commands */ +#define SL_NETUTIL_CRYPTO_CMD_CREATE_CERT (1) +#define SL_NETUTIL_CRYPTO_CMD_SIGN_MSG (2) +#define SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG (3) +#define SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS (4) +#define SL_NETUTIL_CRYPTO_CMD_INSTALL_OP (5) +#define SL_NETUTIL_CMD_ARP_LOOKUP (6) + +/*****************************************************************************/ +/* Errors returned from the general error async event */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +typedef struct +{ + _u8 *pOutputValues; + _u16 *pOutputLen; + _i16 Status; +}_SlNetUtilCmdData_t; + +/* Defines the size of the buffer that will be allocated */ +/* (on the stack) by the sl_UtilsCmd API. */ +#define SL_NETUTIL_CMD_BUFFER_SIZE (256) + +/* Enumeration of Signature types */ +#define SL_NETUTIL_CRYPTO_SIG_SHAwDSA (0) +#define SL_NETUTIL_CRYPTO_SIG_MD2wRSA (1) +#define SL_NETUTIL_CRYPTO_SIG_MD5wRSA (2) +#define SL_NETUTIL_CRYPTO_SIG_SHAwRSA (3) +#define SL_NETUTIL_CRYPTO_SIG_SHAwECDSA (4) +#define SL_NETUTIL_CRYPTO_SIG_SHA256wRSA (5) +#define SL_NETUTIL_CRYPTO_SIG_SHA256wECDSA (6) +#define SL_NETUTIL_CRYPTO_SIG_SHA384wRSA (7) +#define SL_NETUTIL_CRYPTO_SIG_SHA384wECDSA (8) +#define SL_NETUTIL_CRYPTO_SIG_SHA512wRSA (9) +#define SL_NETUTIL_CRYPTO_SIG_SHA512wECDSA (10) +#define SL_NETUTIL_CRYPTO_SIG_DIGESTwECDSA (11) +/* Add more signature-Types here */ + +/* Digest length definitions */ +#define SL_NETUTIL_CRYPTO_DGST_MD2_LEN_BYTES (16) +#define SL_NETUTIL_CRYPTO_DGST_MD5_LEN_BYTES (16) +#define SL_NETUTIL_CRYPTO_DGST_SHA_LEN_BYTES (20) +#define SL_NETUTIL_CRYPTO_DGST_SHA256_LEN_BYTES (32) +#define SL_NETUTIL_CRYPTO_DGST_SHA384_LEN_BYTES (48) +#define SL_NETUTIL_CRYPTO_DGST_SHA512_LEN_BYTES (64) + + +/* Enumeration of Create-Certificate sub-commands */ +#define SL_NETUTIL_CRYPTO_CERT_INIT (1) +#define SL_NETUTIL_CRYPTO_CERT_SIGN_AND_SAVE (2) +#define SL_NETUTIL_CRYPTO_CERT_VER (3) +#define SL_NETUTIL_CRYPTO_CERT_SERIAL (4) +#define SL_NETUTIL_CRYPTO_CERT_SIG_TYPE (5) +#define SL_NETUTIL_CRYPTO_CSR_SIGN_AND_SAVE (6) +#if 0 /* reserved for Issuer information - currently not supported */ +#define SL_NETUTIL_CRYPTO_CERT_ISSUER_COUNTRY (6) +#define SL_NETUTIL_CRYPTO_CERT_ISSUER_STATE (7) +#define SL_NETUTIL_CRYPTO_CERT_ISSUER_LOCALITY (8) +#define SL_NETUTIL_CRYPTO_CERT_ISSUER_SUR (9) +#define SL_NETUTIL_CRYPTO_CERT_ISSUER_ORG (10) +#define SL_NETUTIL_CRYPTO_CERT_ISSUER_ORG_UNIT (11) +#define SL_NETUTIL_CRYPTO_CERT_ISSUER_COMMON_NAME (12) +#define SL_NETUTIL_CRYPTO_CERT_ISSUER_EMAIL (13) +#endif /* End - issuer information */ +#define SL_NETUTIL_CRYPTO_CERT_DAYS_VALID (14) +#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_COUNTRY (15) +#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_STATE (16) +#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_LOCALITY (17) +#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_SUR (18) +#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_ORG (19) +#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_ORG_UNIT (20) +#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_COMMON_NAME (21) +#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_EMAIL (22) +#define SL_NETUTIL_CRYPTO_CERT_IS_CA (23) + + +/* Enumeration of "Temp-Keys" commands */ +#define SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE (1) +#define SL_NETUTIL_CRYPTO_TEMP_KEYS_REMOVE (2) + +/* Enumeration of "Install/Uninstall" sub-commands */ +#define SL_NETUTIL_CRYPTO_INSTALL_SUB_CMD (1) +#define SL_NETUTIL_CRYPTO_UNINSTALL_SUB_CMD (2) + + +/* The reserved key for IOT Usage */ +#define SL_NETUTIL_CRYPTO_SERVICES_IOT_RESERVED_INDEX (0) + +/* The Temporary key for FS Usage */ +#define SL_NETUTIL_CRYPTO_FS_TEMP_KEYS_OBJ_ID (1) + + +/**********************************************/ +/* Public Key Info Structures and Definitions */ +/**********************************************/ + +/* Enumeration of Elliptic Curve "named" curves */ +#define SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_NONE (0) +#define SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_SECP256R1 (1) + +/* PLACE HOLDER for future definitions of custom-curve parameters */ +typedef struct +{ + _u8 Padding[4]; +} SlNetUtilCryptoEcCustomCurveParam_t; + + +/* Union holding the Elliptic Curve parameters. */ +typedef union +{ + _u8 NamedCurveParams; /* parameters for named-curve (the curve identifier) */ + SlNetUtilCryptoEcCustomCurveParam_t CustomCurveParams; /* parameters for custom curves */ +} SlNetUtilCryptoEcCurveParams_u; + + +/* ?curve-type? definitions */ +#define SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_NAMED (1) /* ECC Named Curve type */ +#define SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_CUSTOM (2) /* ECC Custom curve type */ + + +/* Enumeration of the supported public-key algorithms */ +#define SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_NONE (0) +#define SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_EC (1) + + +/* Structure for holding the Elliptic Curve Key parameters */ +typedef struct +{ + _u8 CurveType; /* defines curve type - custom or named */ + SlNetUtilCryptoEcCurveParams_u CurveParams; /* specific parameters of the curve (depends on curve_type) */ +} SlNetUtilCryptoEcKeyParams_t; + +/* Union for holding the Public Key parameters, depends on key algorithm */ +typedef union +{ + + SlNetUtilCryptoEcKeyParams_t EcParams; /* parameters for Elliptic Curve key */ + + /* add containers for other key types and algos here*/ +} SlNetUtilCryptoPubKeyParams_u; + +/* structure for holding all the meta-data about a key-pair */ +typedef struct +{ + _u8 KeyAlgo; + SlNetUtilCryptoPubKeyParams_u KeyParams; + _u8 KeyFileNameLen; + _u8 CertFileNameLen; +}SlNetUtilCryptoPubKeyInfo_t; + +/********************************************/ +/* NetUtil-Crypto Cmd "Attributes" structures */ +/********************************************/ +/* structure for holding all the attributes for a "Sign" Command */ +typedef struct +{ + _u32 ObjId; + _u32 SigType; + _u32 Flags; +} SlNetUtilCryptoCmdSignAttrib_t; + + +/* structure for holding all the attributes for a "Verify" Command */ +typedef struct +{ + _u32 ObjId; + _u32 SigType; + _u32 Flags; + _u16 MsgLen; + _u16 SigLen; +} SlNetUtilCryptoCmdVerifyAttrib_t; + +/* structure for holding all the attributes for a "Create Certificate" Command */ +typedef struct +{ + _u32 ObjId; + _u32 Flags; + _u16 SubCmd; +} SlNetUtilCryptoCmdCreateCertAttrib_t; + +/* structure for holding all the attributes for "Key management" Commands: */ +/* Temp-Key (create and delete), Install and un-Install. */ +typedef struct +{ + _u32 ObjId; + _u32 Flags; + _u16 SubCmd; +} SlNetUtilCryptoCmdKeyMgnt_t; + +/* structure for holding all the attributes for a "SL_NETUTIL_CMD_ARP_LOOKUP" Command */ +typedef struct +{ + _u16 NumOfRetries; /* number of retires for ARP request, range 1-20 */ + _u16 Timeout; /* timeout between ARP requests, range 10-500 mSec , 10 mSec resolution*/ +}NetUtilCmdArpLookupAttrib_t; + + +/******************************************************************************/ +/* Type declarations */ +/******************************************************************************/ + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +/*! + \brief Function for setting configurations of utilities + + \param[in] Option Identifier of the specific "set" operation to perform + \param[in] ObjID ID of the relevant object that this set operation will be performed on + \param[in] ValueLen Length of the value parameter + \param[in] pValues Pointer to the buffer holding the configurations values + + \return Zero on success, or negative error code on failure + \sa sl_NetUtilGet sl_NetUtilCmd + \note + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_NetUtilSet) +_i32 sl_NetUtilSet(const _u16 Option, const _u32 ObjID, const _u8 *pValues, const _u16 ValueLen); +#endif + +/*! + \brief Function for getting configurations of utilities + \param[in] Option Identifier of the specific "get" operation to perform + - SL_NETUTIL_CRYPTO_PUBLIC_KEY \n + Used to retrieve the public key from an installed key-pair. \n + Saved in a certain index. + - SL_NETUTIL_TRUE_RANDOM \n + Generates a random number using the internal TRNG of the NWP. \n + \param[in] ObjID ID of the relevant object that this set operation will be performed on + \param[in,out] pValueLen Pointer to the length of the value parameter\n + On input - provides the length of the buffer that the application allocates, and + will hold the output\n + On output - provides the actual length of the received data + \param[out] pValues Pointer to the buffer that the application allocates, and will hold + the received data. + \return Zero on success, or negative error code on failure. + \sa sl_NetUtilSet sl_NetUtilCmd + \note + \warning + \par Examples + - SL_NETUTIL_CRYPTO_PUBLIC_KEY: + \code + int16_t Status; + uint8_t configOpt = 0; + uint32_t objId = 0; + uint16_t configLen = 0; + uint8_t key_buf[256]; + + configOpt = SL_NETUTIL_CRYPTO_PUBLIC_KEY; + + objId = 1; + configLen = 255; + //get the Public key + Status = sl_NetUtilGet(configOpt, objId, key_buf, &configLen); + \endcode + + - SL_NETUTIL_TRUE_RANDOM: + \code + uint32_t randNum; + int32_t len = sizeof(uint32_t); + + sl_NetUtilGet(SL_NETUTIL_TRUE_RANDOM, 0, (uint8_t *)&randNum, &len); + \endcode +
+*/ +#if _SL_INCLUDE_FUNC(sl_NetUtilGet) +_i16 sl_NetUtilGet(const _u16 Option, const _u32 ObjID, _u8 *pValues, _u16 *pValueLen); +#endif + +/*! + \brief Function for performing utilities-related commands + \param[in] Cmd Identifier of the specific Command to perform + - SL_NETUTIL_CRYPTO_CMD_INSTALL_OP \n + Install / Uninstall key pairs in one or more of the crypto utils + key-pair management mechanism. \n + Key Must be an ECC key-pair using SECP256R1 curve and already programmed to file system, + in DER format.\n + Key installation is persistent. + - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS \n + Creates or removes a temporary key pair. \n + Key pair is created internally by the NWP. + Key pair is not persistent over power cycle. + - SL_NETUTIL_CRYPTO_CMD_SIGN_MSG \n + Signs with a digital signature a data buffer using ECDSA algorithm. \n + - SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG \n + Verify a digital signature given with a data buffer using ECDSA algorithm. \n + \param[in] pAttrib Pointer to the buffer holding the Attribute values + \param[in] AttribLen Length of the Attribute-values + \param[in] pInputValues Pointer to the buffer holding the input-value + \param[in] InputLen Length of the input-value + \param[out] pOutputValues Pointer to the buffer that the application allocates, and will hold the received data. + \param[in,out] pOutputLen Length of the output-value \n + On input - provides the length of the buffer that the application allocates, and + will hold the output\n + On output - provides the actual length of the received output-values + \return Zero on success, or negative error code on failure + \sa sl_NetUtilGet sl_NetUtilSet + \note The host driver API sl_NetUtilCmd is not valid for use with the CC3220R device. + \warning + \par Examples + + - SL_NETUTIL_CRYPTO_CMD_INSTALL_OP (install / uninstall crypto keys): + \code + // Install a key + SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; + SlNetUtilCryptoPubKeyInfo_t *pInfoKey; + uint8_t name[FILE_NAME_SIZE]; + int32_t Status; + int16_t resultLen; + + keyAttrib.ObjId = 5; // Key would be stored at index 5 + keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_INSTALL_SUB_CMD; + pInfoKey->KeyAlgo = SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_EC; + pInfoKey->KeyParams.EcParams.CurveType = SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_NAMED; //ECC curve + pInfoKey->KeyParams.EcParams.CurveParams.NamedCurveParams = SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_SECP256R1; // SECP256R1 curve only. + + pInfoKey->CertFileNameLen = 0; + name = ((uint8_t *)pInfoKey) + sizeof(SlNetUtilCryptoPubKeyInfo_t); + name += pInfoKey->CertFileNameLen; + strcpy((char *)name, "extkey.der"); // Private key name in file system. + pInfoKey->KeyFileNameLen = strlen("extkey.der")+1; + + Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_INSTALL_OP, + (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), + (uint8_t *)pInfo, + sizeof(SlNetUtilCryptoPubKeyInfo_t) + pInfoKey->KeyFileNameLen, + NULL, &resultLen); + + // Uninstall the Key: + resultLen = 0; + keyAttrib.ObjId = 5; + keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_UNINSTALL_SUB_CMD; + + Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_INSTALL_OP, (uint8_t *)&keyAttrib, + sizeof(SlNetUtilCryptoCmdKeyMgnt_t), NULL, 0 , NULL, &resultLen); + \endcode + + - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, (Create a temporary key ): + \code + + SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; + int32_t Status; + uint16_t resultLen; + keyAttrib.ObjId = 1; // key index is 1 + keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE; + + Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, + (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), + NULL, 0 , NULL, &resultLen); + \endcode + + - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, (Create a temporary key ): + \code + + SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; + int32_t Status; + uint16_t resultLen; + keyAttrib.ObjId = 1; // key index is 1 + keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE; + + Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, + (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), + NULL, 0 , NULL, &resultLen); + \endcode + + - SL_NETUTIL_CRYPTO_CMD_SIGN_MSG, (Sign a data buffer): + \code + int32_t Status; + int32_t configLen; + uint8_t messageBuff[1500]; + uint8_t sig_buf[256]; // This buffer shall contain the digital signature. + SlNetUtilCryptoCmdSignAttrib_t signAttrib; + + signAttrib.Flags = 0; + signAttrib.ObjId = 3; + signAttrib.SigType = SL_NETUTIL_CRYPTO_SIG_SHAwECDSA; // this is the only type supported + configLen = 255; + + Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_SIGN_MSG, (uint8_t *)&signAttrib, + sizeof(SlNetUtilCryptoCmdSignAttrib_t), + messageBuff, sizeof(messageBuf), sig_buf, &configLen); + \endcode + + - SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG, (Verify a data buffer): + \code + + int32_t Status; + int32_t configLen; + uint8_t verifyBuf[2048]; + uint8_t messageBuff[1500]; + uint8_t sig_buf[256]; // This buffer contains the digital signature. + int32_t verifyResult; + SlNetUtilCryptoCmdVerifyAttrib_t verAttrib; + + memcpy(verifyBuf, messageBuf, sizeof(messageBuf)); // copy the message to verify buffer. + memcpy(verifyBuf + sizeof(messageBuff), sig_buf, configLen); // Append the signature to message buffer. + + verAttrib.Flags = 0; + verAttrib.ObjId = 3; + verAttrib.SigType = SL_NETUTIL_CRYPTO_SIG_SHAwECDSA; // this is the only type supported, if other hash algorithm + // is wanted, SL_NETUTIL_CRYPTO_SIG_DIGESTwECDSA is used and + // the verifyBuf should be the digest and MsgLen should be + // the digest size + verAttrib.MsgLen = sizeof(messageBuff); + verAttrib.SigLen = configLen; + configLen = 255; + resultLen = 4; + + Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG, (uint8_t *)&verAttrib, + sizeof(SlNetUtilCryptoCmdVerifyAttrib_t), + verifyBuf, sizeof(messageBuf) + configLen, + (uint8_t *)&verifyResult , &resultLen); + \endcode +
+ + \endcode + + + + +*/ +#if _SL_INCLUDE_FUNC(sl_NetUtilCmd) +_i16 sl_NetUtilCmd(const _u16 Cmd, const _u8 *pAttrib, const _u16 AttribLen, + const _u8 *pInputValues, const _u16 InputLen, + _u8 *pOutputValues,_u16 *pOutputLen ); +#endif + +/*! + + Close the Doxygen group. + @} + + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NETUTIL_H__ */ + + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.cpp new file mode 100755 index 00000000000..1c3b3e4f6c9 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.cpp @@ -0,0 +1,496 @@ +/* + * cc_pal.c - CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ +/****************************************************************************** +* cc_pal.cpp +* +* SimpleLink Wi-Fi abstraction file for CC32xx +******************************************************************************/ + +/* Board includes */ +#include "mbed.h" +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ti/devices/cc32xx/driverlib/rom.h" +#include "ti/devices/cc32xx/driverlib/rom_map.h" +#include +#include +#include +#include + +/* NWP_SPARE_REG_5 - (OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5) + - Bits 31:02 - Reserved + - Bits 01 - SLSTOP1 - NWP in Reset, Power Domain Down + - Bits 00 - Reserved +*/ +#define NWP_SPARE_REG_5 (OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5) +#define NWP_SPARE_REG_5_SLSTOP (0x00000002) + +/* ANA_DCDC_PARAMS0 - (HIB1P2_BASE + HIB1P2_O_ANA_DCDC_PARAMETERS0) + - Bits 31:28 - Reserved + - Bits 27 - Override PWM mode (==> PFM) + - Bits 26:00 - Reserved +*/ +#define ANA_DCDC_PARAMS0 (HIB1P2_BASE + HIB1P2_O_ANA_DCDC_PARAMETERS0) +#define ANA_DCDC_PARAMS0_PWMOVERRIDE (0x08000000) + +/* WAKENWP - (ARCM_BASE + APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST) + - Bits 31:01 - Reserved + - Bits 00 - Wake Request to NWP +*/ +#define WAKENWP (ARCM_BASE + APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST) +#define WAKENWP_WAKEREQ (APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST) + +/* NWP_PWR_STATE - (GPRCM_BASE + GPRCM_O_NWP_PWR_STATE) + - Bits 31:12 - Reserved + - Bits 11:08 - Active (0x3) + - Bits 07:00 - Reserved +*/ +#define NWP_PWR_STATE (GPRCM_BASE + GPRCM_O_NWP_PWR_STATE) +#define NWP_PWR_STATE_PWRMASK (0x00000F00) +#define NWP_PWR_STATE_PWRACTIVE (0x00000300) + +/* NWP_LPDS_WAKEUPCFG - (GPRCM_BASE + GPRCM_O_NWP_LPDS_WAKEUP_CFG) + - Bits 31:08 - Reserved + - Bits 07:00 - WakeUp Config AppsToNwp Wake (0x20) - reset condition +*/ +#define NWP_LPDS_WAKEUPCFG (GPRCM_BASE + GPRCM_O_NWP_LPDS_WAKEUP_CFG) +#define NWP_LPDS_WAKEUPCFG_APPS2NWP (0x00000020) +#define NWP_LPDS_WAKEUPCFG_TIMEOUT_MSEC (600) + +/* N2A_INT_MASK_SET - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_SET) */ +#define N2A_INT_MASK_SET (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_SET) +/* N2A_INT_MASK_CLR - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_CLR) */ +#define N2A_INT_MASK_CLR (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_CLR) +/* N2A_INT_ACK - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_ACK) */ +#define N2A_INT_ACK (COMMON_REG_BASE + COMMON_REG_O_NW_INT_ACK) +#define NWP_N2A_INT_ACK_TIMEOUT_MSEC (3000) + +/* A2N_INT_STS_CLR - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_CLR) */ +#define A2N_INT_STS_CLR (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_CLR) +/* A2N_INT_TRIG - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_TRIG) */ +#define A2N_INT_TRIG (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_TRIG) +/* A2N_INT_STS_RAW - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_RAW) */ +#define A2N_INT_STS_RAW (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_RAW) + +#define uSEC_DELAY(x) (ROM_UtilsDelayDirect(x*80/3)) +#define MAX_DMA_RECV_TRANSACTION_SIZE (4096) +#define SPI_RATE_20M (20000000) +#define SPI_RATE_30M (30000000) + +HwiP_Handle g_intHandle = 0; + +//**************************************************************************** +// LOCAL FUNCTIONS +//**************************************************************************** + +Fd_t spi_Open(char *ifName, unsigned long flags) +{ + void *lspi_hndl; + unsigned int lspi_index; + SPI_Params SPI_Config; + SPI_Params_init(&SPI_Config); + + /* configure the SPI settings */ + SPI_Config.transferMode = SPI_MODE_BLOCKING; + SPI_Config.mode = SPI_MASTER; + /* Check NWP generation */ + if((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_DIEID_READ_REG4) >> 24) & 0x02) + { + SPI_Config.bitRate = SPI_RATE_30M; + } + else + { + SPI_Config.bitRate = SPI_RATE_20M; + } + SPI_Config.dataSize = 32; + SPI_Config.frameFormat = SPI_POL0_PHA0; + + /* index of the link SPI initialization configuration in the SPI_Config table */ + lspi_index = 0; + lspi_hndl = SPI_open(lspi_index, &SPI_Config); + if(NULL == lspi_hndl) + { + return -1; + } + else + { + return (Fd_t)lspi_hndl; + } +} + + +int spi_Close(Fd_t fd) +{ + SPI_close((SPI_Handle)fd); + return 0; +} + + +int spi_Read(Fd_t fd, unsigned char *pBuff, int len) +{ + SPI_Transaction transact_details; + int read_size = 0; + + /* check if the link SPI has been initialized successfully */ + if(fd < 0) + { + return -1; + } + + transact_details.txBuf = NULL; + transact_details.arg = NULL; + while(len > 0) + { + /* DMA can transfer upto a maximum of 1024 words in one go. So, if + the data to be read is more than 1024 words, it will be done in + parts */ + /* length is received in bytes, should be specified in words for the + * SPI driver. + */ + if(len > MAX_DMA_RECV_TRANSACTION_SIZE) + { + transact_details.count = (MAX_DMA_RECV_TRANSACTION_SIZE +3)>>2; + transact_details.rxBuf = (void*)(pBuff + read_size); + if(SPI_transfer((SPI_Handle)fd, &transact_details)) + { + read_size += MAX_DMA_RECV_TRANSACTION_SIZE; + len = len - MAX_DMA_RECV_TRANSACTION_SIZE; + } + else + { + return -1; + } + + } + else + { + transact_details.count = (len+3)>>2; + transact_details.rxBuf = (void*)(pBuff + read_size); + if(SPI_transfer((SPI_Handle)fd, &transact_details)) + { + read_size += len; + len = 0; + return read_size; + } + else + { + return -1; + } + } + } + + return(read_size); +} + + +int spi_Write(Fd_t fd, unsigned char *pBuff, int len) +{ + SPI_Transaction transact_details; + int write_size = 0; + + /* check if the link SPI has been initialized successfully */ + if(fd < 0) + { + return -1; + } + + transact_details.rxBuf = NULL; + transact_details.arg = NULL; + while(len > 0) + { + /* configure the transaction details. + * length is received in bytes, should be specified in words for the SPI + * driver. + */ + if(len > MAX_DMA_RECV_TRANSACTION_SIZE) + { + transact_details.count = (MAX_DMA_RECV_TRANSACTION_SIZE +3)>>2; + transact_details.txBuf = (void*)(pBuff + write_size); + if(SPI_transfer((SPI_Handle)fd, &transact_details)) + { + write_size += MAX_DMA_RECV_TRANSACTION_SIZE; + len = len - MAX_DMA_RECV_TRANSACTION_SIZE; + } + else + { + return -1; + } + } + else + { + transact_details.count = (len+3)>>2; + transact_details.txBuf = (void*)(pBuff + write_size); + if(SPI_transfer((SPI_Handle)fd, &transact_details)) + { + write_size += len; + len = 0; + return write_size; + } + else + { + return -1; + } + } + } + + return(write_size); +} + + +int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) +{ + NVIC_ClearPendingIRQ(INT_NWPIC_IRQn); + NVIC_SetVector(INT_NWPIC_IRQn, (uint32_t)InterruptHdl); + NVIC_EnableIRQ(INT_NWPIC_IRQn); + return OS_OK; +} + + +void NwpMaskInterrupt() +{ + (*(unsigned long *)N2A_INT_MASK_SET) = 0x1; +} + + +void NwpUnMaskInterrupt() +{ + (*(unsigned long *)N2A_INT_MASK_CLR) = 0x1; +} + + +void NwpPowerOn(void) +{ + /* bring the 1.32 eco out of reset */ + HWREG(NWP_SPARE_REG_5) &= ~NWP_SPARE_REG_5_SLSTOP; + + /* Clear host IRQ indication */ + HWREG(N2A_INT_ACK) = 1; + + /* NWP Wake-up */ + HWREG(WAKENWP) = WAKENWP_WAKEREQ; + + //UnMask Host Interrupt + NwpUnMaskInterrupt(); +} + + +void NwpPowerOff(void) +{ + + volatile unsigned long apps_int_sts_raw; + volatile unsigned long sl_stop_ind = HWREG(NWP_SPARE_REG_5); + volatile unsigned long nwp_lpds_wake_cfg = HWREG(NWP_LPDS_WAKEUPCFG); + _SlTimeoutParams_t SlTimeoutInfo = {0}; + + if((nwp_lpds_wake_cfg != NWP_LPDS_WAKEUPCFG_APPS2NWP) && /* Check for NWP POR condition - APPS2NWP is reset condition */ + !(sl_stop_ind & NWP_SPARE_REG_5_SLSTOP)) /* Check if sl_stop was executed */ + { + HWREG(0xE000E104) = 0x200; /* Enable the out of band interrupt, this is not a wake-up source*/ + HWREG(A2N_INT_TRIG) = 0x1; /* Trigger out of band interrupt */ + HWREG(WAKENWP) = WAKENWP_WAKEREQ; /* Wake-up the NWP */ + + _SlDrvStartMeasureTimeout(&SlTimeoutInfo, NWP_N2A_INT_ACK_TIMEOUT_MSEC); + + /* Wait for the A2N_INT_TRIG to be cleared by the NWP to indicate it's awake and ready for shutdown. + * poll until APPs->NWP interrupt is cleared or timeout : + * for service pack 3.1.99.1 or higher, this condition is fulfilled in less than 1 mSec. + * Otherwise, in some cases it may require up to 3000 mSec of waiting. */ + + apps_int_sts_raw = HWREG(A2N_INT_STS_RAW); + while(!(apps_int_sts_raw & 0x1)) + { + if(_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) + { + break; + } + apps_int_sts_raw = HWREG(A2N_INT_STS_RAW); + } + + WAIT_NWP_SHUTDOWN_READY; + } + + /* Clear Out of band interrupt, Acked by the NWP */ + HWREG(A2N_INT_STS_CLR) = 0x1; + + /* Mask Host Interrupt */ + NwpMaskInterrupt(); + + /* Switch to PFM Mode */ + HWREG(ANA_DCDC_PARAMS0) &= ~ANA_DCDC_PARAMS0_PWMOVERRIDE; + + /* sl_stop ECO for PG1.32 devices */ + HWREG(NWP_SPARE_REG_5) |= NWP_SPARE_REG_5_SLSTOP; + + /* Wait for 20 uSec, which is the minimal time between on-off cycle */ + uSEC_DELAY(20); +} + + +int Semaphore_create_handle(SemaphoreP_Handle* pSemHandle) +{ + SemaphoreP_Params params; + + SemaphoreP_Params_init(¶ms); + + params.mode = SemaphoreP_Mode_BINARY; + +#ifndef SL_PLATFORM_MULTI_THREADED + params.callback = tiDriverSpawnCallback; +#endif + (*(pSemHandle)) = SemaphoreP_create(1, ¶ms); + + if(!(*(pSemHandle))) + { + return Semaphore_FAILURE ; + } + + return Semaphore_OK; +} + +int SemaphoreP_delete_handle(SemaphoreP_Handle* pSemHandle) +{ + if (pSemHandle) + { + SemaphoreP_delete(*(pSemHandle)); + return Semaphore_OK; + } + else + { + return Semaphore_FAILURE; + } +} + +int SemaphoreP_post_handle(SemaphoreP_Handle* pSemHandle) +{ + if (pSemHandle) + { + SemaphoreP_post(*(pSemHandle)); + return Semaphore_OK; + } + else + { + return Semaphore_FAILURE; + } +} + + +int Mutex_create_handle(MutexP_Handle* pMutexHandle) +{ + MutexP_Params params; + + MutexP_Params_init(¶ms); + +#ifndef SL_PLATFORM_MULTI_THREADED + params.callback = tiDriverSpawnCallback; +#endif + + if (pMutexHandle) + { + (*(pMutexHandle)) = MutexP_create(¶ms); + + if(*(pMutexHandle)) + { + return Mutex_OK; + } + } + return Mutex_FAILURE; +} + +int MutexP_delete_handle(MutexP_Handle* pMutexHandle) +{ + MutexP_delete(*(pMutexHandle)); + return(Mutex_OK); +} + +int Mutex_unlock(MutexP_Handle pMutexHandle) +{ + MutexP_unlock(pMutexHandle, 0); + return(Mutex_OK); +} + + +int Mutex_lock(MutexP_Handle pMutexHandle) +{ + MutexP_lock(pMutexHandle); + return(Mutex_OK); +} + + +unsigned long TimerGetCurrentTimestamp() +{ + // TODO: add the header file containing osKernelGetTickCount + //return (ClockP_getSystemTicks()); + return osKernelGetTickCount(); +} + + +void NwpWaitForShutDownInd() +{ + volatile unsigned long nwp_wakup_ind = HWREG(NWP_LPDS_WAKEUPCFG); + _SlTimeoutParams_t SlTimeoutInfo = {0}; + + _SlDrvStartMeasureTimeout(&SlTimeoutInfo, NWP_LPDS_WAKEUPCFG_TIMEOUT_MSEC); + + while(nwp_wakup_ind != NWP_LPDS_WAKEUPCFG_APPS2NWP) + { + if(_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) + { + return; + } + nwp_wakup_ind = HWREG(NWP_LPDS_WAKEUPCFG); + } + + return ; +} + +void* pthread_self(void) +{ + return ThisThread::get_id(); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.h new file mode 100755 index 00000000000..cf757cdbb8f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/cc_pal.h @@ -0,0 +1,419 @@ +/* + * cc_pal.h - CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ +/****************************************************************************** +* cc_pal.h +* +* SimpleLink Wi-Fi abstraction file for CC32xx +******************************************************************************/ + +#ifndef __CC31xx_PAL_H__ +#define __CC31xx_PAL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + + +#define MAX_QUEUE_SIZE (4) +#define OS_WAIT_FOREVER (0xFFFFFFFF) +#define OS_NO_WAIT (0) +#define OS_OK (0) + +#define Semaphore_OK (0) +#define Semaphore_FAILURE (-1) + +#define Mutex_OK (0) +#define Mutex_FAILURE (-1) + + +/*! + \brief type definition for the SPI channel file descriptor + + \note On each porting or platform the type could be whatever is needed - integer, pointer to structure etc. +*/ +typedef int Fd_t; + + +/*! + \brief type definition for the host interrupt handler + + \param pValue - pointer to any memory strcuture. The value of this pointer is given on + registration of a new interrupt handler + + \note +*/ + +typedef void (*SL_P_EVENT_HANDLER)(void); + +#define P_EVENT_HANDLER SL_P_EVENT_HANDLER + +/*! + \brief type definition for the host spawn function + + \param pValue - pointer to any memory strcuture. The value of this pointer is given on + invoking the spawn function. + + \note +*/ + +typedef signed short (*P_OS_SPAWN_ENTRY)(void* pValue); + +typedef struct +{ + P_OS_SPAWN_ENTRY pEntry; + void* pValue; +}tSimpleLinkSpawnMsg; + +/*! + \brief open spi communication port to be used for communicating with a SimpleLink device + + Given an interface name and option flags, this function opens the spi communication port + and creates a file descriptor. This file descriptor can be used afterwards to read and + write data from and to this specific spi channel. + The SPI speed, clock polarity, clock phase, chip select and all other attributes are all + set to hardcoded values in this function. + + \param ifName - points to the interface name/path. The interface name is an + optional attributes that the SimpleLink driver receives + on opening the device. in systems that the spi channel is + not implemented as part of the os device drivers, this + parameter could be NULL. + \param flags - option flags + + \return upon successful completion, the function shall open the spi channel and return + a non-negative integer representing the file descriptor. + Otherwise, -1 shall be returned + + \sa spi_Close , spi_Read , spi_Write + \note + \warning +*/ +Fd_t spi_Open(char *ifName, unsigned long flags); + +/*! + \brief closes an opened SPI communication port + + \param fd - file descriptor of an opened SPI channel + + \return upon successful completion, the function shall return 0. + Otherwise, -1 shall be returned + + \sa spi_Open + \note + \warning +*/ +int spi_Close(Fd_t fd); + +/*! + \brief attempts to read up to len bytes from SPI channel into a buffer starting at pBuff. + + \param fd - file descriptor of an opened SPI channel + + \param pBuff - points to first location to start writing the data + + \param len - number of bytes to read from the SPI channel + + \return upon successful completion, the function shall return 0. + Otherwise, -1 shall be returned + + \sa spi_Open , spi_Write + \note + \warning +*/ +int spi_Read(Fd_t fd, unsigned char *pBuff, int len); + +/*! + \brief attempts to write up to len bytes to the SPI channel + + \param fd - file descriptor of an opened SPI channel + + \param pBuff - points to first location to start getting the data from + + \param len - number of bytes to write to the SPI channel + + \return upon successful completion, the function shall return 0. + Otherwise, -1 shall be returned + + \sa spi_Open , spi_Read + \note This function could be implemented as zero copy and return only upon successful completion + of writing the whole buffer, but in cases that memory allocation is not too tight, the + function could copy the data to internal buffer, return back and complete the write in + parallel to other activities as long as the other SPI activities would be blocked untill + the entire buffer write would be completed + \warning +*/ +int spi_Write(Fd_t fd, unsigned char *pBuff, int len); + +/*! + \brief register an interrupt handler for the host IRQ + + \param InterruptHdl - pointer to interrupt handler function + + \param pValue - pointer to a memory strcuture that is passed to the interrupt handler. + + \return upon successful registration, the function shall return 0. + Otherwise, -1 shall be returned + + \sa + \note If there is already registered interrupt handler, the function should overwrite the old handler + with the new one + \warning +*/ +int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue); + + +/*! + \brief Masks host IRQ + + + \sa NwpUnMaskInterrupt + + \warning +*/ +void NwpMaskInterrupt(); + + +/*! + \brief Unmasks host IRQ + + + \sa NwpMaskInterrupt + + \warning +*/ +void NwpUnMaskInterrupt(); + + +/*! + \brief Preamble to the enabling the Network Processor. + Placeholder to implement any pre-process operations + before enabling networking operations. + + \sa sl_DeviceEnable + + \note belongs to \ref ported_sec + +*/ + +void NwpPowerOnPreamble(void); + + + +/*! + \brief Disable the Network Processor + + \sa sl_DeviceEnable + + \note belongs to \ref ported_sec +*/ +void NwpPowerOff(void); + + +/*! + \brief Enable the Network Processor + + \sa sl_DeviceDisable + + \note belongs to \ref ported_sec + +*/ +void NwpPowerOn(void); + + +/*! + \brief Creates a semaphore handle, using the driver porting layer of the core SDK. + + \param pSemHandle - pointer to a memory structure that would contain the handle. + + \return upon successful creation, the function shall return 0. + Otherwise, -1 shall be returned + + \note belongs to \ref ported_sec +*/ +int Semaphore_create_handle(SemaphoreP_Handle* pSemHandle); + + +/*! + \brief Deletes a semaphore handle, using the driver porting layer of the core SDK. + + \param pSemHandle - pointer to a memory structure that would contain the handle. + + \return The function shall return 0. + + \note belongs to \ref ported_sec +*/ +int SemaphoreP_delete_handle(SemaphoreP_Handle* pSemHandle); + + +/*! + \brief Post (signal) a semaphore handle, using the driver porting layer of the core SDK. + + \param pSemHandle - pointer to a memory structure that would contain the handle. + + \return The function shall return 0. + + \note belongs to \ref ported_sec +*/ +int SemaphoreP_post_handle(SemaphoreP_Handle* pSemHandle); + + +/*! + \brief Creates a mutex object handle, using the driver porting layer of the core SDK. + + \param pMutexHandle - pointer to a memory structure that would contain the handle. + + \return upon successful creation, the function shall return 0. + Otherwise, -1 shall be returned + + \note belongs to \ref ported_sec +*/ +int Mutex_create_handle(MutexP_Handle* pMutexHandle); + + +/*! + \brief Deletes a mutex object handle, using the driver porting layer of the core SDK. + + \param pMutexHandle - pointer to a memory structure that would contain the handle. + + \return the function shall return 0. + + \note belongs to \ref ported_sec +*/ +int MutexP_delete_handle(MutexP_Handle* pMutexHandle); + +/*! + \brief Unlocks a mutex object. + + \param pMutexHandle - pointer to a memory structure that contains the object. + + \return upon successful unlocking, the function shall return 0. + + \note belongs to \ref ported_sec +*/ +int Mutex_unlock(MutexP_Handle pMutexHandle); + + +/*! + \brief Locks a mutex object. + + \param pMutexHandle - pointer to a memory structure that contains the object. + + \return upon successful locking, the function shall return 0. + + \note belongs to \ref ported_sec + + \warning The lock will block until the mutex is available. +*/ +/*! + \brief Creates a mutex object handle, using the driver porting layer of the core SDK. + + \param pMutexHandle - pointer to a memory structure that would contain the handle. + + \return upon successful creation, the function shall return 0. + Otherwise, -1 shall be returned + + \note belongs to \ref ported_sec +*/ + + +/*! + \brief Deletes a mutex object handle, using the driver porting layer of the core SDK. + + \param pMutexHandle - pointer to a memory structure that would contain the handle. + + \return the function shall return 0. + + \note belongs to \ref ported_sec +*/ + +/*! + \brief Unlocks a mutex object. + + \param pMutexHandle - pointer to a memory structure that contains the object. + + \return upon successful unlocking, the function shall return 0. + + \note belongs to \ref ported_sec +*/ + + +/*! + \brief Locks a mutex object. + + \param pMutexHandle - pointer to a memory structure that contains the object. + + \return upon successful locking, the function shall return 0. + + \note belongs to \ref ported_sec + + \warning The lock will block until the mutex is available. +*/ +int Mutex_lock(MutexP_Handle pMutexHandle); + + +/*! + \brief Take a time stamp value. + + \return 32-bit value of the systick counter. + + \sa + + \warning +*/ +unsigned long TimerGetCurrentTimestamp(); + +/*! + \brief + + \return + + \sa + + \warning +*/ +void NwpWaitForShutDownInd(); + + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/user.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/user.h new file mode 100755 index 00000000000..017b5a475d5 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/porting/user.h @@ -0,0 +1,1332 @@ +/* + * user.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/****************************************************************************** +* user.h - CC31xx/CC32xx Host Driver Implementation +******************************************************************************/ + +#ifndef __USER_H__ +#define __USER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include + +typedef signed int _SlFd_t; + +#define SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS (_u32)(10) +#define SL_TIMESTAMP_MAX_VALUE (_u32)(0xFFFFFFFF) + +/*! + ****************************************************************************** + + \defgroup configuration_mem_mgm Configuration - Memory Management + + This section declare in which memory management model the SimpleLink driver + will run: + -# Static + -# Dynamic + + This section IS NOT REQUIRED in case Static model is selected. + + The default memory model is Static + + + @{ + + ***************************************************************************** +*/ + +/*! + \brief Defines whether the SimpleLink driver is working in dynamic + memory model or not + + When defined, the SimpleLink driver use dynamic allocations + if dynamic allocation is selected malloc and free functions + must be retrieved + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ + +#define SL_MEMORY_MGMT_DYNAMIC + +#ifdef SL_MEMORY_MGMT_DYNAMIC + + +#include +/*! + \brief + \sa + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_Malloc(Size) malloc(Size) + +/*! + \brief + \sa + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_Free(pMem) free(pMem) +#endif + + +/*! + + Close the Doxygen group. + @} + +*/ + +/*! + + \def MAX_CONCURRENT_ACTIONS + + \brief Defines the maximum number of concurrent action in the system + Min:1 , Max: 32 + + Actions which has async events as return, will be blocked until the event arrive + + \sa + + \note In case there are not enough resources for the actions needed in the system, + error is received: SL_POOL_IS_EMPTY + one option is to increase MAX_CONCURRENT_ACTIONS + (improves performance but results in memory consumption) + Other option is to call the API later (decrease performance) + + Async events which arrive during command context will be dynamically or static + allocated and handled in spawn context. If MAX_CONCURRENT_ACTIONS + is high, there will be more events which might arrive during this period. + Due to memory constrains MAX_CONCURRENT_ACTIONS is lower in static allocation mode. + + + \warning In case of setting to one, recommend to use non-blocking recv\recvfrom to allow + multiple socket recv +*/ +#ifndef SL_TINY_EXT +#ifdef SL_MEMORY_MGMT_DYNAMIC +#define MAX_CONCURRENT_ACTIONS 18 +#else +#define MAX_CONCURRENT_ACTIONS 5 +#endif +#else +#define MAX_CONCURRENT_ACTIONS 1 +#endif + /*! + \def SL_MAX_ASYNC_BUFFERS + + + + \brief Defines the maximum static buffers to store asycn events which + arrives during command context. The event is stored in a buffer (if free) + and handle in spwan cotext. value must be set to MAX_CONCURRENT_ACTIONS which + is the maximum simultaniuos async event which could arrive in command context. + value: MAX_CONCURRENT_ACTIONS + + \sa + + \note Events which arrive when there is no free buffer will be dropped. + If there is a command which is waiting on this event, it will be released + with error SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR. + In this case need to increase MAX_CONCURRENT_ACTIONS + (improves performance but results in memory consumption) + + + */ + +#define SL_MAX_ASYNC_BUFFERS MAX_CONCURRENT_ACTIONS +/*! + \def CPU_FREQ_IN_MHZ + \brief Defines CPU frequency for Host side, for better accuracy of busy loops, if any + \sa + \note + + \warning If not set the default CPU frequency is set to 200MHz + This option will be deprecated in future release +*/ + +/* #define CPU_FREQ_IN_MHZ 80 */ + + +/*! + ****************************************************************************** + + \defgroup configuration_capabilities Configuration - Capabilities Set + + This section IS NOT REQUIRED in case one of the following pre defined + capabilities set is in use: + - SL_TINY + - SL_SMALL + - SL_FULL + + PORTING ACTION: + - Define one of the pre-defined capabilities set or uncomment the + relevant definitions below to select the required capabilities + + @{ + + ******************************************************************************* +*/ +/*! + \def SL_RUNTIME_EVENT_REGISTERATION + + \brief Defines whether the SimpleLink driver uses dynamic event registration + or static precompiled event mechanism + \sa + + \note belongs to \ref configuration_sec + +*/ +#define SL_RUNTIME_EVENT_REGISTERATION + + +/*! + \def SL_INC_ARG_CHECK + + \brief Defines whether the SimpleLink driver perform argument check + or not + + When defined, the SimpleLink driver perform argument check on + function call. Removing this define could reduce some code + size and improve slightly the performances but may impact in + unpredictable behavior in case of invalid arguments + + \sa + + \note belongs to \ref configuration_sec + + \warning Removing argument check may cause unpredictable behavior in + case of invalid arguments. + In this case the user is responsible to argument validity + (for example all handlers must not be NULL) +*/ +#define SL_INC_ARG_CHECK + + +/*! + \brief Defines whether to include extended API in SimpleLink driver + or not + + When defined, the SimpleLink driver will include also all + exteded API of the included packages + + \sa ext_api + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_EXT_API + + +/*! + \brief Defines whether to include WLAN package in SimpleLink driver + or not + + When defined, the SimpleLink driver will include also + the WLAN package + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_WLAN_PKG + + +/*! + \brief Defines whether to include SOCKET package in SimpleLink + driver or not + + When defined, the SimpleLink driver will include also + the SOCKET package + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_SOCKET_PKG + + +/*! + \brief Defines whether to include NET_APP package in SimpleLink + driver or not + + When defined, the SimpleLink driver will include also the + NET_APP package + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_NET_APP_PKG + + +/*! + \brief Defines whether to include NET_CFG package in SimpleLink + driver or not + + When defined, the SimpleLink driver will include also + the NET_CFG package + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_NET_CFG_PKG + + +/*! + \brief Defines whether to include NVMEM package in SimpleLink + driver or not + + When defined, the SimpleLink driver will include also the + NVMEM package + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_NVMEM_PKG + + +/*! + \brief Defines whether to include NVMEM extended package in SimpleLink + driver or not + + When defined, the SimpleLink driver will include also the + NVMEM extended package + + \sa + + \note belongs to \ref nvmem_ext + + \warning +*/ +#define SL_INC_NVMEM_EXT_PKG + + +/*! + \brief Defines whether to include socket server side APIs + in SimpleLink driver or not + + When defined, the SimpleLink driver will include also socket + server side APIs + + \sa server_side + + \note + + \warning +*/ +#define SL_INC_SOCK_SERVER_SIDE_API + + +/*! + \brief Defines whether to include socket client side APIs in SimpleLink + driver or not + + When defined, the SimpleLink driver will include also socket + client side APIs + + \sa client_side + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_SOCK_CLIENT_SIDE_API + + +/*! + \brief Defines whether to include socket receive APIs in SimpleLink + driver or not + + When defined, the SimpleLink driver will include also socket + receive side APIs + + \sa recv_api + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_SOCK_RECV_API + + +/*! + \brief Defines whether to include socket send APIs in SimpleLink + driver or not + + When defined, the SimpleLink driver will include also socket + send side APIs + + \sa send_api + + \note belongs to \ref configuration_sec + + \warning +*/ +#define SL_INC_SOCK_SEND_API + + +/*! + + Close the Doxygen group. + @} + + */ + + +/*! + ****************************************************************************** + + \defgroup configuration_enable_device Configuration - Device Enable/Disable + + The enable/disable API provide mechanism to enable/disable the network processor + + + porting ACTION: + - None + @{ + + ****************************************************************************** + */ + +/*! + \brief Preamble to the enabling the Network Processor. + Placeholder to implement any pre-process operations + before enabling networking operations. + + \sa sl_DeviceEnable + + \note belongs to \ref configuration_sec + +*/ +#define sl_DeviceEnablePreamble() + + + +/*! + \brief Enable the Network Processor + + \sa sl_DeviceDisable + + \note belongs to \ref configuration_sec + +*/ +#define sl_DeviceEnable() NwpPowerOn() + + +/*! + \brief Disable the Network Processor + + \sa sl_DeviceEnable + + \note belongs to \ref configuration_sec +*/ +#define sl_DeviceDisable() NwpPowerOff() + + +/*! + + Close the Doxygen group. + @} + + */ + +/*! + ****************************************************************************** + + \defgroup configuration_interface Configuration - Communication Interface + + The SimpleLink device supports several standard communication protocol among SPI and + UART. CC32XX Host Driver implements SPI Communication Interface + + + \note In CC32XX, SPI implementation uses DMA in order to increase the utilization + of the communication channel. If user prefers to user UART, these interfaces + need to be redefined + + + porting ACTION: + - None + + @{ + + ****************************************************************************** +*/ + +#define _SlFd_t Fd_t + + +/*! + \brief Opens an interface communication port to be used for communicating + with a SimpleLink device + + Given an interface name and option flags, this function opens + the communication port and creates a file descriptor. + This file descriptor is used afterwards to read and write + data from and to this specific communication channel. + The speed, clock polarity, clock phase, chip select and all other + specific attributes of the channel are all should be set to hardcoded + in this function. + + \param ifName - points to the interface name/path. The interface name is an + optional attributes that the SimpleLink driver receives + on opening the driver (sl_Start). + In systems that the spi channel is not implemented as + part of the os device drivers, this parameter could be NULL. + + \param flags - optional flags parameters for future use + + \return upon successful completion, the function shall open the channel + and return a non-negative integer representing the file descriptor. + Otherwise, -1 shall be returned + + \sa sl_IfClose , sl_IfRead , sl_IfWrite + + \note The prototype of the function is as follow: + Fd_t xxx_IfOpen(char* pIfName , unsigned long flags); + + \note belongs to \ref configuration_sec + + \warning +*/ +#define sl_IfOpen spi_Open + + +/*! + \brief Closes an opened interface communication port + + \param fd - file descriptor of opened communication channel + + \return upon successful completion, the function shall return 0. + Otherwise, -1 shall be returned + + \sa sl_IfOpen , sl_IfRead , sl_IfWrite + + \note The prototype of the function is as follow: + int xxx_IfClose(Fd_t Fd); + + \note belongs to \ref configuration_sec + + \warning +*/ +#define sl_IfClose spi_Close + + +/*! + \brief Attempts to read up to len bytes from an opened communication channel + into a buffer starting at pBuff. + + \param fd - file descriptor of an opened communication channel + + \param pBuff - pointer to the first location of a buffer that contains enough + space for all expected data + + \param len - number of bytes to read from the communication channel + + \return upon successful completion, the function shall return the number of read bytes. + Otherwise, 0 shall be returned + + \sa sl_IfClose , sl_IfOpen , sl_IfWrite + + + \note The prototype of the function is as follow: + int xxx_IfRead(Fd_t Fd , char* pBuff , int Len); + + \note belongs to \ref configuration_sec + + \warning +*/ +#define sl_IfRead spi_Read + + +/*! + \brief attempts to write up to len bytes to the SPI channel + + \param fd - file descriptor of an opened communication channel + + \param pBuff - pointer to the first location of a buffer that contains + the data to send over the communication channel + + \param len - number of bytes to write to the communication channel + + \return upon successful completion, the function shall return the number of sent bytes. + therwise, 0 shall be returned + + \sa sl_IfClose , sl_IfOpen , sl_IfRead + + \note This function could be implemented as zero copy and return only upon successful completion + of writing the whole buffer, but in cases that memory allocation is not too tight, the + function could copy the data to internal buffer, return back and complete the write in + parallel to other activities as long as the other SPI activities would be blocked until + the entire buffer write would be completed + + The prototype of the function is as follow: + int xxx_IfWrite(Fd_t Fd , char* pBuff , int Len); + + \note belongs to \ref configuration_sec + + \warning +*/ +#define sl_IfWrite spi_Write + + +/*! + \brief register an interrupt handler routine for the host IRQ + + \param InterruptHdl - pointer to interrupt handler routine + + \param pValue - pointer to a memory structure that is passed + to the interrupt handler. + + \return upon successful registration, the function shall return 0. + Otherwise, -1 shall be returned + + \sa + + \note If there is already registered interrupt handler, the function + should overwrite the old handler with the new one + + \note If the handler is a null pointer, the function should un-register the + interrupt handler, and the interrupts can be disabled. + + \note belongs to \ref configuration_sec + + \warning +*/ +#define sl_IfRegIntHdlr(InterruptHdl , pValue) NwpRegisterInterruptHandler(InterruptHdl , pValue) + + +/*! + \brief Masks the Host IRQ + + \sa sl_IfUnMaskIntHdlr + + + + \note belongs to \ref configuration_sec + + \warning +*/ +#define sl_IfMaskIntHdlr() NwpMaskInterrupt() + + +/*! + \brief Unmasks the Host IRQ + + \sa sl_IfMaskIntHdlr + + + + \note belongs to \ref configuration_sec + + \warning +*/ +#define sl_IfUnMaskIntHdlr() NwpUnMaskInterrupt() + + +/*! + \brief Write Handers for statistics debug on write + + \param interface handler - pointer to interrupt handler routine + + + \return no return value + + \sa + + \note An optional hooks for monitoring before and after write info + + \note belongs to \ref configuration_sec + + \warning +*/ +/* #define SL_START_WRITE_STAT */ + +#ifdef SL_START_WRITE_STAT +#define sl_IfStartWriteSequence +#define sl_IfEndWriteSequence +#endif + + +/*! + \brief Get the timer counter value (timestamp). + The timer must count from zero to its MAX value. + + \param None. + + + \return Returns 32-bit timer counter value (ticks unit) + + \sa + + \note + + \note belongs to \ref porting_sec + + \warning +*/ +#ifndef SL_TINY_EXT +#undef slcb_GetTimestamp +/* A timer must be started before using this function */ +#define slcb_GetTimestamp TimerGetCurrentTimestamp +#endif + + +/*! + \brief This macro wait for the NWP to raise a ready for shutdown indication. + + \param None. + + \note This function is unique for the CC32XX family + + \warning +*/ + +#define WAIT_NWP_SHUTDOWN_READY NwpWaitForShutDownInd() + + +/*! + Close the Doxygen group. + @} + +*/ + +/*! + ****************************************************************************** + + \defgroup configuration_os Configuration - Operating System + + The SimpleLink driver could run on two kind of platforms: + -# Non-Os / Single Threaded (default) + -# Multi-Threaded + + CC32XX SimpleLink Host Driver is ported on both Non-Os and Multi Threaded OS enviroment. + The Host driver is made OS independent by implementing an OS Abstraction layer. + Reference implementation for OS Abstraction is available for FreeRTOS and TI-RTOS. + + + If you choose to work in multi-threaded environment under different operating system you + will have to provide some basic adaptation routines to allow the driver to protect access to + resources for different threads (locking object) and to allow synchronization between threads + (sync objects). In additional the driver support running without dedicated thread allocated solely + to the SimpleLink driver. If you choose to work in this mode, you should also supply a spawn + method that will enable to run function on a temporary context. + + \note - This Macro is defined in the IDE to generate Driver for both OS and Non-OS + + porting ACTION: + - None + + @{ + + ****************************************************************************** +*/ + +#define SL_PLATFORM_MULTI_THREADED + +#ifdef SL_PLATFORM_MULTI_THREADED + +/*! + \brief + \sa + \note belongs to \ref configuration_sec + \warning +*/ +#define SL_OS_RET_CODE_OK ((int)OS_OK) + +/*! + \brief + \sa + \note belongs to \ref configuration_sec + \warning +*/ +#define SL_OS_WAIT_FOREVER ((uint32_t)OS_WAIT_FOREVER) + +/*! + \brief + \sa + \note belongs to \ref configuration_sec + \warning +*/ +#define SL_OS_NO_WAIT ((uint32_t)OS_NO_WAIT) + +/*! + \brief type definition for a time value + + \note On each configuration or platform the type could be whatever is needed - integer, pointer to structure etc. + + \note belongs to \ref configuration_sec +*/ +#define _SlTime_t uint32_t + + +#endif //SL_PLATFORM_MULTI_THREADED + +/*! + \brief type definition for a sync object container + + Sync object is object used to synchronize between two threads or thread and interrupt handler. + One thread is waiting on the object and the other thread send a signal, which then + release the waiting thread. + The signal must be able to be sent from interrupt context. + This object is generally implemented by binary semaphore or events. + + \note On each configuration or platform the type could be whatever is needed - integer, structure etc. + + \note belongs to \ref configuration_sec +*/ +#define _SlSyncObj_t SemaphoreP_Handle + + +/*! + \brief This function creates a sync object + + The sync object is used for synchronization between diffrent thread or ISR and + a thread. + + \param pSyncObj - pointer to the sync object control block + + \return upon successful creation the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_SyncObjCreate(pSyncObj,pName) Semaphore_create_handle(pSyncObj) + + +/*! + \brief This function deletes a sync object + + \param pSyncObj - pointer to the sync object control block + + \return upon successful deletion the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_SyncObjDelete(pSyncObj) SemaphoreP_delete_handle(pSyncObj) + + +/*! + \brief This function generates a sync signal for the object. + + All suspended threads waiting on this sync object are resumed + + \param pSyncObj - pointer to the sync object control block + + \return upon successful signaling the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note the function could be called from ISR context + \warning +*/ +#define sl_SyncObjSignal(pSyncObj) SemaphoreP_post_handle(pSyncObj) + + +/*! + \brief This function generates a sync signal for the object from Interrupt + + This is for RTOS that should signal from IRQ using a dedicated API + + \param pSyncObj - pointer to the sync object control block + + \return upon successful signaling the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note the function could be called from ISR context + \warning +*/ +#define sl_SyncObjSignalFromIRQ(pSyncObj) SemaphoreP_post_handle(pSyncObj) + + +/*! + \brief This function waits for a sync signal of the specific sync object + + \param pSyncObj - pointer to the sync object control block + \param Timeout - numeric value specifies the maximum number of mSec to + stay suspended while waiting for the sync signal + Currently, the SimpleLink driver uses only two values: + - OSI_WAIT_FOREVER + - OSI_NO_WAIT + + \return upon successful reception of the signal within the timeout window return 0 + Otherwise, a negative value indicating the error code shall be returned + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_SyncObjWait(pSyncObj,Timeout) SemaphoreP_pend((*(pSyncObj)),Timeout) + +/*! + \brief type definition for a locking object container + + Locking object are used to protect a resource from mutual accesses of two or more threads. + The locking object should suppurt reentrant locks by a signal thread. + This object is generally implemented by mutex semaphore + + \note On each configuration or platform the type could be whatever is needed - integer, structure etc. + \note belongs to \ref configuration_sec +*/ +#define _SlLockObj_t MutexP_Handle + +/*! + \brief This function creates a locking object. + + The locking object is used for protecting a shared resources between different + threads. + + \param pLockObj - pointer to the locking object control block + + \return upon successful creation the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_LockObjCreate(pLockObj, pName) Mutex_create_handle(pLockObj) + + +/*! + \brief This function deletes a locking object. + + \param pLockObj - pointer to the locking object control block + + \return upon successful deletion the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_LockObjDelete(pLockObj) MutexP_delete_handle(pLockObj) + + +/*! + \brief This function locks a locking object. + + All other threads that call this function before this thread calls + the osi_LockObjUnlock would be suspended + + \param pLockObj - pointer to the locking object control block + \param Timeout - numeric value specifies the maximum number of mSec to + stay suspended while waiting for the locking object + Currently, the SimpleLink driver uses only two values: + - OSI_WAIT_FOREVER + - OSI_NO_WAIT + + + \return upon successful reception of the locking object the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_LockObjLock(pLockObj,Timeout) Mutex_lock(*(pLockObj)) + + +/*! + \brief This function unlock a locking object. + + \param pLockObj - pointer to the locking object control block + + \return upon successful unlocking the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note belongs to \ref configuration_sec + \warning +*/ +#define sl_LockObjUnlock(pLockObj) Mutex_unlock(*(pLockObj)) + + +/*! + \brief This function call the pEntry callback from a different context + + \param pEntry - pointer to the entry callback function + + \param pValue - pointer to any type of memory structure that would be + passed to pEntry callback from the execution thread. + + \param flags - execution flags - reserved for future usage + + \return upon successful registration of the spawn the function should return 0 + (the function is not blocked till the end of the execution of the function + and could be returned before the execution is actually completed) + Otherwise, a negative value indicating the error code shall be returned + \note belongs to \ref configuration_sec + + \warning User must implement it's own 'os_Spawn' function. +*/ +//#define SL_PLATFORM_EXTERNAL_SPAWN + +#ifdef SL_PLATFORM_EXTERNAL_SPAWN +#define sl_Spawn(pEntry,pValue,flags) os_Spawn(pEntry,pValue,flags) +#endif + +/*! + * + Close the Doxygen group. + @} + + */ + +/*! + ****************************************************************************** + + \defgroup configuration_events Configuration - Event Handlers + + This section includes the asynchronous event handlers routines + + porting ACTION: + -define your routine as the value of this handler + + @{ + + ****************************************************************************** + */ + + + +/*! + \brief Fatal Error async event for inspecting fatal error events. + This event handles events/errors reported from the device/host driver + + \param[out] pSlFatalErrorEvent + + \par + Parameters: + + - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_DEVICE_ABORT , + + - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_DRIVER_ABORT , + + - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_NO_CMD_ACK , + + - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_SYNC_LOSS , + + - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT , + + + \note belongs to \ref configuration_sec + + \warning +*/ + +#define slcb_DeviceFatalErrorEvtHdlr SimpleLinkFatalErrorEventHandler + +/*! + \brief General async event for inspecting general events. + This event handles events/errors reported from the device/host driver + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ + +#define slcb_DeviceGeneralEvtHdlr SimpleLinkGeneralEventHandler + +/*! + \brief WLAN Async event handler + + \param[out] pSlWlanEvent pointer to SlWlanEvent_t data + + \par + Parameters: + + - pSlWlanEvent->Event = SL_WLAN_CONNECT_EVENT , STA or P2P client connection indication event + - pSlWlanEvent->EventData.STAandP2PModeWlanConnected main fields: + - ssid_name + - ssid_len + - bssid + - go_peer_device_name + - go_peer_device_name_len + + - pSlWlanEvent->Event = SL_WLAN_DISCONNECT_EVENT , STA or P2P client disconnection event + - pSlWlanEvent->EventData.STAandP2PModeDisconnected main fields: + - ssid_name + - ssid_len + - reason_code + + - pSlWlanEvent->Event = SL_WLAN_STA_CONNECTED_EVENT , AP/P2P(Go) connected STA/P2P(Client) + - pSlWlanEvent->EventData.APModeStaConnected fields: + - go_peer_device_name + - mac + - go_peer_device_name_len + - wps_dev_password_id + - own_ssid: relevant for event sta-connected only + - own_ssid_len: relevant for event sta-connected only + + - pSlWlanEvent->Event = SL_WLAN_STA_DISCONNECTED_EVENT , AP/P2P(Go) disconnected STA/P2P(Client) + - pSlWlanEvent->EventData.APModestaDisconnected fields: + - go_peer_device_name + - mac + - go_peer_device_name_len + - wps_dev_password_id + - own_ssid: relevant for event sta-connected only + - own_ssid_len: relevant for event sta-connected only + + - pSlWlanEvent->Event = SL_WLAN_SMART_CONFIG_COMPLETE_EVENT + - pSlWlanEvent->EventData.smartConfigStartResponse fields: + - status + - ssid_len + - ssid + - private_token_len + - private_token + + - pSlWlanEvent->Event = SL_WLAN_SMART_CONFIG_STOP_EVENT + - pSlWlanEvent->EventData.smartConfigStopResponse fields: + - status + + - pSlWlanEvent->Event = SL_WLAN_P2P_DEV_FOUND_EVENT + - pSlWlanEvent->EventData.P2PModeDevFound fields: + - go_peer_device_name + - mac + - go_peer_device_name_len + - wps_dev_password_id + - own_ssid: relevant for event sta-connected only + - own_ssid_len: relevant for event sta-connected only + + - pSlWlanEvent->Event = SL_WLAN_P2P_NEG_REQ_RECEIVED_EVENT + - pSlWlanEvent->EventData.P2PModeNegReqReceived fields + - go_peer_device_name + - mac + - go_peer_device_name_len + - wps_dev_password_id + - own_ssid: relevant for event sta-connected only + + - pSlWlanEvent->Event = SL_WLAN_CONNECTION_FAILED_EVENT , P2P only + - pSlWlanEvent->EventData.P2PModewlanConnectionFailure fields: + - status + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ + +#define slcb_WlanEvtHdlr SimpleLinkWlanEventHandler + + +/*! + \brief NETAPP Async event handler + + \param[out] pSlNetApp pointer to SlNetAppEvent_t data + + \par + Parameters: + - pSlWlanEvent->Event = SL_NETAPP_IPV4_IPACQUIRED_EVENT, IPV4 acquired event + - pSlWlanEvent->EventData.ipAcquiredV4 fields: + - ip + - gateway + - dns + + - pSlWlanEvent->Event = SL_NETAPP_IP_LEASED_EVENT, AP or P2P go dhcp lease event + - pSlWlanEvent->EventData.ipLeased fields: + - ip_address + - lease_time + - mac + + - pSlWlanEvent->Event = SL_NETAPP_IP_RELEASED_EVENT, AP or P2P go dhcp ip release event + - pSlWlanEvent->EventData.ipReleased fields + - ip_address + - mac + - reason + + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ + +#define slcb_NetAppEvtHdlr SimpleLinkNetAppEventHandler + +/*! + \brief HTTP server async event + + \param[out] pSlHttpServerEvent pointer to SlHttpServerEvent_t + \param[in] pSlHttpServerResponse pointer to SlHttpServerResponse_t + + \par + Parameters: \n + + - pSlHttpServerEvent->Event = SL_NETAPP_HTTPGETTOKENVALUE_EVENT + - pSlHttpServerEvent->EventData fields: + - httpTokenName + - data + - len + - pSlHttpServerResponse->ResponseData fields: + - data + - len + + - pSlHttpServerEvent->Event = SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT + - pSlHttpServerEvent->EventData.httpPostData fields: + - action + - token_name + - token_value + - pSlHttpServerResponse->ResponseData fields: + - data + - len + + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ + +#define slcb_NetAppHttpServerHdlr SimpleLinkHttpServerEventHandler + + + +/*! + \brief A handler for handling Netapp requests. + Netapp request types: + For HTTP server: GET / POST (future: PUT / DELETE) + + \param + + \param + + \sa + + \note belongs to \ref porting_sec + + \warning +*/ + +#define slcb_NetAppRequestHdlr SimpleLinkNetAppRequestEventHandler + + + +/*! + \brief A handler for freeing the memory of the NetApp response. + + \param + + \param + + \sa + + \note belongs to \ref porting_sec + + \warning +*/ + +#define slcb_NetAppRequestMemFree SimpleLinkNetAppRequestMemFreeEventHandler + + + +/*! + \brief Socket Async event handler + + \param[out] pSlSockEvent pointer to SlSockEvent_t data + + \par + Parameters:\n + - pSlSockEvent->Event = SL_SOCKET_TX_FAILED_EVENT + - pSlSockEvent->EventData fields: + - sd + - status + - pSlSockEvent->Event = SL_SOCKET_ASYNC_EVENT + - pSlSockEvent->EventData fields: + - sd + - type: SSL_ACCEPT or RX_FRAGMENTATION_TOO_BIG or OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED + - val + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ + +#define slcb_SockEvtHdlr SimpleLinkSockEventHandler + + +/*! + \brief Trigger Async event handler. If define, sl_Select operates only in trigger mode. + To disable trigger mode, handler should not be defined. + + \param[out] pSlTriggerEvent pointer to SlSockTriggerEvent_t data + + \par + Parameters:\n + - pSlTriggerEvent->Event = SL_SOCKET_TRIGGER_EVENT_SELECT + - pSlTriggerEvent->EventData: Not in use + + + \sa + + \note belongs to \ref configuration_sec + + \warning +*/ +#ifndef SL_PLATFORM_MULTI_THREADED +#define slcb_SocketTriggerEventHandler SimpleLinkSocketTriggerEventHandler +#endif +/*! + + Close the Doxygen group. + @} + + */ + + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __USER_H__ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/simplelink.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/simplelink.h new file mode 100755 index 00000000000..9037e56e334 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/simplelink.h @@ -0,0 +1,1253 @@ +/* + * simplelink.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*! + \mainpage SimpleLink Driver + + \section intro_sec Introduction + + The SimpleLink(tm) CC31xx/CC32xx family allows to add Wi-Fi and networking capabilities + to low-cost embedded products without having prior Wi-Fi, RF or networking expertise.\n + The CC31xx/CC32xx is an ideal solution for microcontroller-based sensor and control + applications such as home appliances, home automation and smart metering.\n + The CC31xx/CC32xx has integrated a comprehensive TCP/IP network stack, Wi-Fi driver and + security supplicant leading to easier portability to microcontrollers, to an + ultra-low memory footprint, all without compromising the capabilities and robustness + of the final application. + + + + \section modules_sec Module Names + To make it simple, TI's SimpleLink CC31xx/CC32xx platform capabilities were divided into modules by topic (Silo).\n + These capabilities range from basic device management through wireless + network configuration, standard BSD socket and much more.\n + Listed below are the various modules in the SimpleLink CC31xx/CC32xx driver: + -# \ref Device - Controls the behaviour of the CC31xx/CC32xx device (start/stop, events masking and obtaining specific device status) + -# \ref FileSystem - Provides file system capabilities to TI's CC31XX that can be used by both the CC31XX device and the user. + -# \ref NetApp - Activates networking applications, such as: HTTP Server, DHCP Server, Ping, DNS and mDNS. + -# \ref NetCfg - Controls the configuration of the device addresses (i.e. IP and MAC addresses) + -# \ref NetUtil - Networking related commands and configuration + -# \ref Socket - Controls standard client/server sockets programming options and capabilities + -# \ref Wlan - Controls the use of the WiFi WLAN module including: + - Connection features, such as: profiles, policies, SmartConfig(tm) + - Advanced WLAN features, such as: scans, rx filters and rx statistics collection + -# \ref UserEvents - Function prototypes for event callback handlers + + \section persistency_sec Persistency + The SimpleLink(tm) device support few different persistency types for settings and configurations:\n + - Temporary - Effective immediately but returned to default after reset\n + - System Persistent - Effective immediately and kept after reset according\n + to system persistent mode\n + - Persistent - Effective immediately and kept after reset regardless the system persistent mode\n + - Optionally Persistent - Effective immediately and kept after reset according to a parameter in the API call\n + - Reset - Persistent but effective only after reset\n + \n + For all Set/Get function in this guide, the type of persistency per relevant parameters will be + described as part of the function description\n + + \section proting_sec Porting Guide + + The porting of the SimpleLink host driver to any new platform is based on few simple steps.\n + This guide takes you through this process step by step. Please follow the instructions + carefully to avoid any problems during this process and to enable efficient and proper + work with the device.\n + Please notice that all modifications and porting adjustments of the driver should be + made in the user.h header file only. Keeping this method ensure smoothly +transaction to new versions of the driver in the future!\n + +The porting process consists of few simple steps: +-# Create user.h for the target platform +-# Select the capabilities set +-# Bind the device enable/disable line +-# Writing your interface communication driver +-# Choose your memory management model +-# OS adaptation +-# Set your asynchronous event handlers +-# Testing + +For host interface details please refer to: +http://processors.wiki.ti.com/index.php/CC31xx_Host_Interface + +Please see the rest of the page for more details about the different steps. + + \subsection porting_step1 Step 1 - Create your own user.h file + + The first step is to create a user.h file that will include your configurations and + adjustments. \n + The file should be located in the porting directory (the porting directory is in the same level as the source directory)\n + It is recommended to use the empty template provided as part of this driver or + file of other platform such as MSP432 or CC32xx, from one of the wide range + of example applications provided by Texas Instruments. + + \subsection porting_step2 Step 2 - Select the capabilities set required for your application + + Texas Instruments built 3 different predefined sets of capabilities that would fit most of + the target applications.\n + It is recommended to try and choose one of this predefined capabilities set before going to + build your own customized set. If you find compatible set you can skip the rest of this step. + + The available sets are: + -# SL_TINY - Compatible to be used on platforms with very limited resources. Provides + the best in class low foot print in terms of Code and Data consumption. + -# SL_SMALL - Compatible to most common networking applications. Provide the most + common APIs with decent balance between code size, data size, functionality + and performances + -# SL_FULL - Provide access to all SimpleLink functionalities + + \subsection porting_step3 Step 3 - Bind the device enable/disable output line + + The CC31xx has two external hardware lines that can be used to enable/disable the device. + - nReset + - nHib - provides mechanism to enter the device into the least current consumption mode. In + this mode the RTC value is kept. + + The driver manipulates the enable/disable line automatically during sl_Start / sl_Stop.\n + Not connecting one these lines means that the driver could start only once (sl_Stop will not + work correctly and might lead to failure latter on) and the internal provisioning mechanism + could not be used.\n + + To bind these lines the following defines should be defined correctly: + - sl_DeviceEnable + - sl_DeviceDisable + + If some initializations required before the enable/disable macros are called the user can use also the following optional define + - sl_DeviceEnablePreamble + + \subsection porting_step4 Step 4 - Writing your interface communication driver + + The SimpleLink CC31xx has two standard communication interfaces + - SPI + - UART + + The device detects automatically the active interface during initialization. After the detection, the second interface could not be used.\n + + To wrap the driver for the communication channel the following functions should be implemented: + -# sl_IfOpen + -# sl_IfClose + -# sl_IfRead + -# sl_IfWrite + -# sl_IfRegIntHdlr + + The way these functions are implemented has direct effect on the performances of the SimpleLink + device on this target platform. DMA and Jitter Buffer should be considered.\n + + In some platforms the user need to mask the IRQ line when this interrupt could be masked. \n + The driver can call the mask/unmask whenever is needed. To allow this functionality the + user should implement also the following defines: + - sl_IfMaskIntHdlr + - sl_IfUnMaskIntHdlr + + By default the driver is writing the command in few transactions to allow zero-copy mechanism. \n + To enable a Jitter buffer for improving the communication line utilization, the can implement + also the following defines: + - sl_IfStartWriteSequence + - sl_IfEndWriteSequence + + \subsection porting_step5 Step 5 - Choose your memory management model + + The SimpleLink driver support two memory models: + - Static (default) + - Dynamic + + To enable the dynamic memory, the following pre-processor define should be set: \n + #define SL_MEMORY_MGMT_DYNAMIC + + And the following macros should be defined and supplied: + - sl_Malloc + - sl_Free + + Using the dynamic mode will allocate the required resources on sl_Start and release these resource on sl_Stop. + + \subsection porting_step6 Step 6 - OS adaptation + + The SimpleLink driver could run on two kind of platforms: + -# Non-Os / Single Threaded (default) + -# Multi-Threaded + + When building a multi-threaded application. the following pre-processor define must be set: \n + #define SL_PLATFORM_MULTI_THREADED + + If you choose to work in multi-threaded environment under operating system you will have to + provide some basic adaptation routines to allow the driver to protect access to resources + for different threads (locking object) and to allow synchronization between threads (sync objects). + In additional the driver support running without dedicated thread allocated solely to the + SimpleLink driver. If you choose to work in this mode, you should also supply a spawn method that + will enable to run function on a temporary context. + + + \subsection porting_step7 Step 7 - Set your asynchronous event handlers routines + + The SimpleLink device generate asynchronous events in several situations. + These asynchronous events could be masked. + In order to catch these events you have to provide handler routines. + Please notice that if you not provide a handler routine and the event is received, + the driver will drop this event without any indication of this drop. + + + \subsection porting_step8 Step 8 - Run diagnostic tools to validate the correctness of your porting + + The driver is delivered with some porting diagnostic tools to simplify the porting validation process + and to reduce issues latter. It is very important to follow carefully this process. + + The diagnostic process include: + -# Validating interface communication driver + -# Validating basic work with the device + + + \section annex_step Annex Persistency + The SimpleLink(tm) device support few different persistency types for settings and configurations:\n + - Temporary - Effective immediately but returned to default after reset\n + - System Persistent - Effective immediately and kept after reset according\n + - to system persistent mode\n + - Persistent - Effective immediately and kept after reset regardless the system persistent mode\n + - Optionally Persistent - Effective immediately and kept after reset according to a parameter in the API call\n + - Reset - Persistent but effective only after reset\n + +*/ + +#ifndef __SIMPLELINK_H__ +#define __SIMPLELINK_H__ + +/* define the default types + * If user wants to overwrite it, + * he need to undef and define again */ +#define _u8 unsigned char +#define _i8 signed char +#define _u16 unsigned short +#define _i16 signed short +#define _u32 unsigned long +#define _i32 signed long + +#define _volatile volatile +#define _const const + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + \defgroup UserEvents + \short Function prototypes for event callback handlers + +*/ + +/*! \attention Async event activation notes\n + Function prototypes for event callback handlers\n + Event handler function names should be defined in the user.h file\n + e.g.\n + "#define slcb_WlanEvtHdlr SLWlanEventHandler"\n + Indicates all WLAN events are handled by User func "SLWlanEventHandler"\n + Important notes:\n + 1. Event handlers cannot activate another SimpleLink API from the event's context + 2. Event's data is valid during event's context. Any application data + which is required for the user application should be copied or marked + into user's variables + 3. It is not recommended to delay the execution of the event callback handler + +*/ + +/*! + + \addtogroup UserEvents + @{ + +*/ + + +/*****************************************************************************/ +/* Macro declarations for Host Driver version */ +/*****************************************************************************/ +#define SL_DRIVER_VERSION "3.0.1.39" +#define SL_MAJOR_VERSION_NUM 3L +#define SL_MINOR_VERSION_NUM 0L +#define SL_VERSION_NUM 1L +#define SL_SUB_VERSION_NUM 39L + +/*****************************************************************************/ +/* Macro declarations for predefined configurations */ +/*****************************************************************************/ + +#ifdef SL_TINY +#undef SL_INC_ARG_CHECK +#undef SL_INC_EXT_API +#undef SL_INC_SOCK_SERVER_SIDE_API +#undef SL_INC_WLAN_PKG +#undef SL_INC_NET_CFG_PKG +#undef SL_INC_FS_PKG +#undef SL_INC_SET_UART_MODE +#undef SL_INC_NVMEM_PKG +#define SL_INC_SOCK_CLIENT_SIDE_API +#define SL_INC_SOCK_RECV_API +#define SL_INC_SOCK_SEND_API +#define SL_INC_SOCKET_PKG +#define SL_INC_NET_APP_PKG +#endif + +#ifdef SL_SMALL +#undef SL_INC_EXT_API +#undef SL_INC_NET_APP_PKG +#undef SL_INC_NET_CFG_PKG +#undef SL_INC_FS_PKG +#define SL_INC_ARG_CHECK +#define SL_INC_WLAN_PKG +#define SL_INC_SOCKET_PKG +#define SL_INC_SOCK_CLIENT_SIDE_API +#define SL_INC_SOCK_SERVER_SIDE_API +#define SL_INC_SOCK_RECV_API +#define SL_INC_SOCK_SEND_API +#define SL_INC_SET_UART_MODE +#endif + +#ifdef SL_FULL +#define SL_INC_EXT_API +#define SL_INC_NET_APP_PKG +#define SL_INC_NET_CFG_PKG +#define SL_INC_FS_PKG +#define SL_INC_ARG_CHECK +#define SL_INC_WLAN_PKG +#define SL_INC_SOCKET_PKG +#define SL_INC_SOCK_CLIENT_SIDE_API +#define SL_INC_SOCK_SERVER_SIDE_API +#define SL_INC_SOCK_RECV_API +#define SL_INC_SOCK_SEND_API +#define SL_INC_SET_UART_MODE +#endif + +/* #define sl_Memcpy memcpy */ +#define sl_Memset(addr, val, len) memset(addr, val, (size_t)len) +#define sl_Memcpy(dest, src, len) memcpy(dest, src, (size_t)len) +#define sl_Memmove(dest, src, len) memmove(dest, src, (size_t)len) + +#ifndef SL_TINY +#define SL_MAX_SOCKETS (_u8)(16) +#else +#define SL_MAX_SOCKETS (_u8)(2) +#endif + +/*****************************************************************************/ +/* Types definitions */ +/*****************************************************************************/ + +#ifndef NULL +#define NULL (0) +#endif + +#ifndef FALSE +#define FALSE (0) +#endif + +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +typedef _u16 _SlOpcode_t; +typedef _u8 _SlArgSize_t; +typedef _i16 _SlDataSize_t; +typedef _i16 _SlReturnVal_t; + +/* + * This event status used to block or continue the event propagation + * through all the registered external libs/user application + * + */ + + typedef enum { + EVENT_PROPAGATION_BLOCK = 0, + EVENT_PROPAGATION_CONTINUE + } _SlEventPropogationStatus_e; + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + + +/* + objInclusion.h and user.h must be included before all api header files + objInclusion.h must be the last arrangement just before including the API header files + since it based on the other configurations to decide which object should be included +*/ +#include "source/objInclusion.h" +#include "trace.h" +#include "fs.h" +#include "sl_socket.h" +#include "netapp.h" +#include "wlan.h" +#include "device.h" +#include "netcfg.h" +#include "netutil.h" +#include "errors.h" +#include "eventreg.h" + +/*! + \cond DOXYGEN_IGNORE +*/ + /* In case of use dynamic event registration + * redirect the event to the internal mechanism */ +#if (defined(SL_RUNTIME_EVENT_REGISTERATION)) + +#define _SlDrvHandleFatalErrorEvents _SlDeviceFatalErrorEvtHdlr +#define _SlDrvHandleGeneralEvents _SlDeviceGeneralEvtHdlr +#define _SlDrvHandleWlanEvents _SlWlanEvtHdlr +#define _SlDrvHandleNetAppEvents _SlNetAppEvtHdlr +#define _SlDrvHandleSockEvents _SlSockEvtHdlr +#define _SlDrvHandleHttpServerEvents _SlNetAppHttpServerHdlr +#define _SlDrvHandleNetAppRequestEvents _SlNetAppRequestHdlr +#define _SlDrvHandleNetAppRequestMemFreeEvents _SlNetAppRequestMemFree +#define _SlDrvHandleSocketTriggerEvents _SlSocketTriggerEventHandler + +#else + + /* The fatal error events dispatcher which is + * initialized to the user handler */ +#ifdef slcb_DeviceFatalErrorEvtHdlr +#define _SlDrvHandleFatalErrorEvents slcb_DeviceFatalErrorEvtHdlr +#endif + + /* The general events dispatcher which is + * initialized to the user handler */ +#ifdef slcb_DeviceGeneralEvtHdlr +#define _SlDrvHandleGeneralEvents slcb_DeviceGeneralEvtHdlr +#endif + + /* The wlan events dispatcher which is + * initialized to the user handler */ +#ifdef slcb_WlanEvtHdlr +#define _SlDrvHandleWlanEvents slcb_WlanEvtHdlr +#endif + + /* The NetApp events dispatcher which is + * initialized to the user handler */ +#ifdef slcb_NetAppEvtHdlr +#define _SlDrvHandleNetAppEvents slcb_NetAppEvtHdlr +#endif + + /* The http server events dispatcher which is + * initialized to the user handler if exists */ +#ifdef slcb_NetAppHttpServerHdlr +#define _SlDrvHandleHttpServerEvents slcb_NetAppHttpServerHdlr +#endif + + /* The socket events dispatcher which is + * initialized to the user handler */ +#ifdef slcb_SockEvtHdlr +#define _SlDrvHandleSockEvents slcb_SockEvtHdlr +#endif + + +/* The netapp requests dispatcher which is + * initialized to the user handler if exists */ +#ifdef slcb_NetAppRequestHdlr +#define _SlDrvHandleNetAppRequestEvents slcb_NetAppRequestHdlr +#endif + +/* The netapp request mem free requests dispatcher which is +* initialized to the user handler if exists */ +#ifdef slcb_NetAppRequestMemFree +#define _SlDrvHandleNetAppRequestMemFreeEvents slcb_NetAppRequestMemFree +#endif + +/* The netapp requests dispatcher which is +* initialized to the user handler if exists */ +#ifdef slcb_SocketTriggerEventHandler +#define _SlDrvHandleSocketTriggerEvents slcb_SocketTriggerEventHandler +#endif + + +#endif + +#define SL_CONCAT(x,y) x ## y +#define SL_CONCAT2(x,y) SL_CONCAT(x,y) + + +#if (!defined(SL_RUNTIME_EVENT_REGISTERATION)) + +/* + * The section below handles the external lib event registration + * according to the desired events it specified in its API header file. + * The external lib should be first installed by the user (see user.h) + */ +#ifdef SL_EXT_LIB_1 + +/* General Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_GENERAL_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _GeneralEventHdl) (SlDeviceEvent_t *); + #define SlExtLib1GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_1, _GeneralEventHdl) + + #undef EXT_LIB_REGISTERED_GENERAL_EVENTS + #define EXT_LIB_REGISTERED_GENERAL_EVENTS + #endif + + /* Wlan Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_WLAN_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _WlanEventHdl) (SlWlanEvent_t *); + #define SlExtLib1WlanEventHandler SL_CONCAT2(SL_EXT_LIB_1, _WlanEventHdl) + + #undef EXT_LIB_REGISTERED_WLAN_EVENTS + #define EXT_LIB_REGISTERED_WLAN_EVENTS + #endif + + /* NetApp Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_NETAPP_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _NetAppEventHdl) (SlNetAppEvent_t *); + #define SlExtLib1NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_1, _NetAppEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_EVENTS + #endif + + /* Http Server Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_HTTP_SERVER_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); + #define SlExtLib1HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_1, _HttpServerEventHdl) + + #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #endif + + /* Socket Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_SOCK_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _SockEventHdl) (SlSockEvent_t *); + #define SlExtLib1SockEventHandler SL_CONCAT2(SL_EXT_LIB_1, _SockEventHdl) + + #undef EXT_LIB_REGISTERED_SOCK_EVENTS + #define EXT_LIB_REGISTERED_SOCK_EVENTS + #endif + + /* Fatal Error Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_FATAL_ERROR_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _FatalErrorEventHdl) (SlDeviceEvent_t *); + #define SlExtLib1FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_1, _FatalErrorEventHdl) + + #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #endif + + /* NetApp requests events registration */ + #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_NETAPP_REQUEST_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); + #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_1, _NetAppRequestEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #endif + +#endif + + +#ifdef SL_EXT_LIB_2 + + /* General Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_GENERAL_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _GeneralEventHdl) (SlDeviceEvent_t *); + #define SlExtLib2GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_2, _GeneralEventHdl) + + #undef EXT_LIB_REGISTERED_GENERAL_EVENTS + #define EXT_LIB_REGISTERED_GENERAL_EVENTS + #endif + + /* Wlan Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_WLAN_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _WlanEventHdl) (SlWlanEvent_t *); + #define SlExtLib2WlanEventHandler SL_CONCAT2(SL_EXT_LIB_2, _WlanEventHdl) + + #undef EXT_LIB_REGISTERED_WLAN_EVENTS + #define EXT_LIB_REGISTERED_WLAN_EVENTS + #endif + + /* NetApp Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_NETAPP_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _NetAppEventHdl) (SlNetAppEvent_t *); + #define SlExtLib2NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_2, _NetAppEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_EVENTS + #endif + + /* Http Server Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_HTTP_SERVER_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); + #define SlExtLib2HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_2, _HttpServerEventHdl) + + #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #endif + + /* Socket Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_SOCK_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _SockEventHdl) (SlSockEvent_t *); + #define SlExtLib2SockEventHandler SL_CONCAT2(SL_EXT_LIB_2, _SockEventHdl) + + #undef EXT_LIB_REGISTERED_SOCK_EVENTS + #define EXT_LIB_REGISTERED_SOCK_EVENTS + #endif + + /* Fatal Error Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_FATAL_ERROR_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _FatalErrorEventHdl) (SlDeviceEvent_t *); + #define SlExtLib2FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_2, _FatalErrorEventHdl) + + #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #endif + + /* NetApp requests events registration */ + #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_NETAPP_REQUEST_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); + #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_2, _NetAppRequestEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #endif + +#endif + +#ifdef SL_EXT_LIB_3 + + /* General Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_GENERAL_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _GeneralEventHdl) (SlDeviceEvent_t *); + #define SlExtLib3GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_3, _GeneralEventHdl) + + #undef EXT_LIB_REGISTERED_GENERAL_EVENTS + #define EXT_LIB_REGISTERED_GENERAL_EVENTS + #endif + + /* Wlan Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_WLAN_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _WlanEventHdl) (SlWlanEvent_t *); + #define SlExtLib3WlanEventHandler SL_CONCAT2(SL_EXT_LIB_3, _WlanEventHdl) + + #undef EXT_LIB_REGISTERED_WLAN_EVENTS + #define EXT_LIB_REGISTERED_WLAN_EVENTS + #endif + + /* NetApp Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_NETAPP_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _NetAppEventHdl) (SlNetAppEvent_t *); + #define SlExtLib3NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_3, _NetAppEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_EVENTS + #endif + + /* Http Server Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_HTTP_SERVER_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); + #define SlExtLib3HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_3, _HttpServerEventHdl) + + #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #endif + + /* Socket Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_SOCK_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _SockEventHdl) (SlSockEvent_t *); + #define SlExtLib3SockEventHandler SL_CONCAT2(SL_EXT_LIB_3, _SockEventHdl) + + #undef EXT_LIB_REGISTERED_SOCK_EVENTS + #define EXT_LIB_REGISTERED_SOCK_EVENTS + #endif + + + /* Fatal Error Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_FATAL_ERROR_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _FatalErrorEventHdl) (SlDeviceEvent_t *); + #define SlExtLib3FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_3, _FatalErrorEventHdl) + + #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #endif + + /* NetApp requests events registration */ + #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_NETAPP_REQUEST_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); + #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_3, _NetAppRequestEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #endif + +#endif + +#ifdef SL_EXT_LIB_4 + + /* General Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_GENERAL_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _GeneralEventHdl) (SlDeviceEvent_t *); + #define SlExtLib4GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_4, _GeneralEventHdl) + + #undef EXT_LIB_REGISTERED_GENERAL_EVENTS + #define EXT_LIB_REGISTERED_GENERAL_EVENTS + #endif + + /* Wlan Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_WLAN_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _WlanEventHdl) (SlWlanEvent_t *); + #define SlExtLib4WlanEventHandler SL_CONCAT2(SL_EXT_LIB_4, _WlanEventHdl) + + #undef EXT_LIB_REGISTERED_WLAN_EVENTS + #define EXT_LIB_REGISTERED_WLAN_EVENTS + #endif + + /* NetApp Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_NETAPP_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _NetAppEventHdl) (SlNetAppEvent_t *); + #define SlExtLib4NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_4, _NetAppEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_EVENTS + #endif + + /* Http Server Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_HTTP_SERVER_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); + #define SlExtLib4HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_4, _HttpServerEventHdl) + + #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #endif + + /* Socket Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_SOCK_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _SockEventHdl) (SlSockEvent_t *); + #define SlExtLib4SockEventHandler SL_CONCAT2(SL_EXT_LIB_4, _SockEventHdl) + + #undef EXT_LIB_REGISTERED_SOCK_EVENTS + #define EXT_LIB_REGISTERED_SOCK_EVENTS + #endif + + /* Fatal Error Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_FATAL_ERROR_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _FatalErrorEventHdl) (SlDeviceEvent_t *); + #define SlExtLib4FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_4, _FatalErrorEventHdl) + + #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #endif + + /* NetApp requests events registration */ + #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_NETAPP_REQUEST_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); + #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_4, _NetAppRequestEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #endif + +#endif + +#ifdef SL_EXT_LIB_5 + + /* General Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_GENERAL_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _GeneralEventHdl) (SlDeviceEvent_t *); + #define SlExtLib5GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_5, _GeneralEventHdl) + + #undef EXT_LIB_REGISTERED_GENERAL_EVENTS + #define EXT_LIB_REGISTERED_GENERAL_EVENTS + #endif + + /* Wlan Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_WLAN_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _WlanEventHdl) (SlWlanEvent_t *); + #define SlExtLib5WlanEventHandler SL_CONCAT2(SL_EXT_LIB_5, _WlanEventHdl) + + #undef EXT_LIB_REGISTERED_WLAN_EVENTS + #define EXT_LIB_REGISTERED_WLAN_EVENTS + #endif + + /* NetApp Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_NETAPP_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _NetAppEventHdl) (SlNetAppEvent_t *); + #define SlExtLib5NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_5, _NetAppEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_EVENTS + #endif + + /* Http Server Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_HTTP_SERVER_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); + #define SlExtLib5HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_5, _HttpServerEventHdl) + + #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS + #endif + + /* Socket Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_SOCK_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _SockEventHdl) (SlSockEvent_t *); + #define SlExtLib5SockEventHandler SL_CONCAT2(SL_EXT_LIB_5, _SockEventHdl) + + #undef EXT_LIB_REGISTERED_SOCK_EVENTS + #define EXT_LIB_REGISTERED_SOCK_EVENTS + #endif + + /* Fatal Error Event Registration */ + #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_FATAL_ERROR_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _FatalErrorEventHdl) (SlDeviceEvent_t *); + #define SlExtLib5FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_5, _FatalErrorEventHdl) + + #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS + #endif + + /* NetApp requests events registration */ + #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_NETAPP_REQUEST_EVENT) + extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); + #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_5, _NetAppRequestEventHdl) + + #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS + #endif + +#endif + +#if defined(EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) +extern void _SlDrvHandleFatalErrorEvents(SlDeviceEvent_t *slFatalErrorEvent); +#endif + +#if defined(EXT_LIB_REGISTERED_GENERAL_EVENTS) +extern void _SlDrvHandleGeneralEvents(SlDeviceEvent_t *slGeneralEvent); +#endif + +#if defined(EXT_LIB_REGISTERED_WLAN_EVENTS) +extern void _SlDrvHandleWlanEvents(SlWlanEvent_t *slWlanEvent); +#endif + +#if defined (EXT_LIB_REGISTERED_NETAPP_EVENTS) +extern void _SlDrvHandleNetAppEvents(SlNetAppEvent_t *slNetAppEvent); +#endif + +#if defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) +extern void _SlDrvHandleHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse); +#endif + +#if defined(EXT_LIB_REGISTERED_SOCK_EVENTS) +extern void _SlDrvHandleSockEvents(SlSockEvent_t *slSockEvent); +#endif + +#if defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) +extern void _SlDrvHandleNetAppRequestEvents(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); +#endif + +#endif //#if (defined(SL_RUNTIME_EVENT_REGISTERATION)) + +typedef _SlReturnVal_t (*_SlSpawnEntryFunc_t)(void* pValue); + +#define SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER (0x1) +#define SL_SPAWN_FLAG_FROM_CMD_CTX (0x2) +#define SL_SPAWN_FLAG_FROM_CMD_PROCESS (0x3) + +#ifdef SL_PLATFORM_MULTI_THREADED + #include "source/spawn.h" +#else + #include "source/nonos.h" +#endif + +/*! + \endcond +*/ + + +/* Async functions description*/ + + +/*! + \brief Fatal Error event for inspecting fatal error + + \param[out] pSlFatalErrorEvent pointer to SlDeviceFatal_t + \return None + \sa + \note + \warning + \par Example + \code + For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_DEVICE_ABORT + Indicates a severe error occured and the device stopped + Use pSlDeviceFatal->Data.DeviceAssert fields + - Code: An idication of the abort type + - Value: The abort data + + + For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_NO_CMD_ACK + Indicates that the command sent to the device had no ack + Use pSlDeviceFatal->Data.NoCmdAck fields + - Code: An idication of the cmd opcode + + For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT + Indicates that the command got a timeout while waiting for its async response + Use pSlDeviceFatal->Data.CmdTimeout fields + - Code: An idication of the asyncevent opcode + + + For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_DRIVER_ABORT + Indicates a severe error occured in the driver + Use pSlDeviceFatal->Data.DeviceAssert fields + - None. + + For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_SYNC_LOSS + Indicates a sync loss with the device + Use pSlDeviceFatal->Data.DeviceAssert fields + - None. + \endcode + \code + Example for fatal error + printf(Abort type =%d Abort Data=0x%x\n\n", + pSlDeviceFatal->Data.deviceReport.AbortType, + pSlDeviceFatal->Data.deviceReport.AbortData); + \endcode +*/ +#if (defined(slcb_DeviceFatalErrorEvtHdlr)) +extern void slcb_DeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent); +#endif + + +/*! + \brief General async event for inspecting general events + + \param[out] pSlDeviceEvent pointer to SlDeviceEvent_t + \return None + \sa + \note + \warning + \par Example + \code + For pSlDeviceEvent->Id = SL_DEVICE_EVENT_RESET_REQUEST + Use pSlDeviceEvent->Data.ResetRequest fields + - Status: An error code indication from the device + - Source: The sender originator which is based on SlDeviceSource_e enum + + For pSlDeviceEvent->Id = SL_DEVICE_EVENT_ERROR + Use pSlDeviceEvent->Data.Error fields + - Code: An error code indication from the device + - Source: The sender originator which is based on SlErrorSender_e enum + \endcode + \code + Example for error event: + printf(General Event Handler - ID=%d Sender=%d\n\n", + pSlDeviceEvent->Data.Error.Code, // the error code + pSlDeviceEvent->Data.Error.Source); // the error source + \endcode + +*/ +#if (defined(slcb_DeviceGeneralEvtHdlr)) +extern void slcb_DeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent); +#endif + +/*! + \brief WLAN Async event handler + + \param[out] pSlWlanEvent pointer to SlWlanEvent_t data + \return None + \sa + \note + \warning + \par Example + \code + For pSlWlanEvent->Id = SL_WLAN_EVENT_CONNECT, STA connection indication event + Use pSlWlanEvent->Data.Connect main fields + - SsidLen + - SsidName + - Bssid + + For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CONNECT, P2P client connection indication event + Use pSlWlanEvent->Data.P2PConnect main fields + - SsidLen + - SsidName + - Bssid + - GoDeviceNameLen + - GoDeviceName + + For pSlWlanEvent->Id = SL_WLAN_EVENT_DISCONNECT, STA client disconnection event + Use pSlWlanEvent->Data.Disconnect main fields: + - SsidLen + - SsidName + - Bssid + - ReasonCode + + For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_DISCONNECT, P2P client disconnection event + Use pSlWlanEvent->Data.P2PDisconnect main fields: + - SsidLen + - SsidName + - Bssid + - ReasonCode + - GoDeviceNameLen + - GoDeviceName + + For pSlWlanEvent->Id = SL_WLAN_EVENT_STA_ADDED, AP connected STA + Use pSlWlanEvent->Data.STAAdded fields: + - Mac + + For pSlWlanEvent->Id = SL_WLAN_EVENT_STA_REMOVED, AP disconnected STA + Use pSlWlanEvent->Data.STARemoved fields: + - Mac + + For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CLIENT_ADDED, P2P(Go) connected P2P(Client) + Use pSlWlanEvent->Data.P2PClientAdded fields: + - Mac + - GoDeviceNameLen + - GoDeviceName + - OwnSsidLen + - OwnSsid + + For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CLIENT_REMOVED, P2P(Go) disconnected P2P(Client) + Use pSlWlanEvent->Data.P2PClientRemoved fields: + - Mac + - GoDeviceNameLen + - GoDeviceName + - OwnSsidLen + - OwnSsid + + For pSlWlanEvent->Id = SL_WLAN_P2P_DEV_FOUND_EVENT + Use pSlWlanEvent->Data.P2PDevFound fields: + - GoDeviceNameLen + - GoDeviceName + - Mac + - WpsMethod + + For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_REQUEST + Use pSlWlanEvent->Data.P2PRequest fields + - GoDeviceNameLen + - GoDeviceName + - Mac + - WpsMethod + + For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CONNECTFAIL, P2P only + Use pSlWlanEvent->Data.P2PConnectFail fields: + - Status + + For pSlWlanEvent->Id = SL_WLAN_EVENT_PROVISIONING_STATUS + Use pSlWlanEvent->Data.ProvisioningStatus fields + - Status + + For pSlWlanEvent->Id = SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED + Use pSlWlanEvent->Data.ProvisioningProfileAdded fields: + - Status + - SsidLen + - Ssid + - Reserved + \endcode +*/ +#if (defined(slcb_WlanEvtHdlr)) +extern void slcb_WlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent); +#endif + + +/*! + \brief NETAPP Async event handler + + \param[out] pSlNetAppEvent pointer to SlNetAppEvent_t data + \return None + \sa + \note + \warning + \par Example + \code + For pSlNetAppEvent->Id = SL_NETAPP_EVENT_IPV4_ACQUIRED/SL_NETAPP_EVENT_IPV6_ACQUIRED + Use pSlNetAppEvent->Data.ipAcquiredV4 (V6) fields + - ip + - gateway + - dns + + For pSlNetAppEvent->Id = SL_NETAPP_IP_LEASED_EVENT, AP or P2P go dhcp lease event + Use pSlNetAppEvent->Data.ipLeased fields + - ip_address + - lease_time + - mac + + For pSlNetApp->Id = SL_NETAPP_IP_RELEASED_EVENT, AP or P2P go dhcp ip release event + Use pSlNetAppEvent->Data.ipReleased fields + - ip_address + - mac + - reason + \endcode +*/ +#if (defined(slcb_NetAppEvtHdlr)) +extern void slcb_NetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent); +#endif + +/*! + \brief Socket Async event handler + + \param[out] pSlSockEvent pointer to SlSockEvent_t data + \return None + \sa + \note + \warning + \par Example + \code + For pSlSockEvent->Event = SL_SOCKET_TX_FAILED_EVENT + Use pSlSockEvent->SockTxFailData fields + - sd + - status + For pSlSockEvent->Event = SL_SOCKET_ASYNC_EVENT + Use pSlSockEvent->SockAsyncData fields + - sd + - type + - SL_SSL_ACCEPT + - SL_WLAN_RX_FRAGMENTATION_TOO_BIG + - SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED + - val + \endcode + +*/ +#if (defined(slcb_SockEvtHdlr)) +extern void slcb_SockEvtHdlr(SlSockEvent_t* pSlSockEvent); +#endif + +/*! + \brief HTTP server async event + + \param[out] pSlHttpServerEvent Pointer to SlNetAppHttpServerEvent_t + \param[in] pSlHttpServerResponse Pointer to SlNetAppHttpServerResponse_t + + \return None + \sa slcb_NetAppRequestHdlr + \note + \warning + \par Example + \code + For pSlHttpServerResponse->Event = SL_NETAPP_HTTPGETTOKENVALUE_EVENT + Use pSlHttpServerEvent->EventData fields + - httpTokenName + - data + - len + And pSlHttpServerResponse->ResponseData fields + - data + - len + + For pSlHttpServerEvent->Event = SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT + Use pSlHttpServerEvent->EventData.httpPostData fields + - action + - token_name + - token_value + And pSlHttpServerResponse->ResponseData fields: + - data + - len + \endcode +*/ +#if (defined(slcb_NetAppHttpServerHdlr)) +extern void slcb_NetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); +#endif + +/*! + \brief General netapp async event + + \param[out] pNetAppRequest Pointer to SlNetAppRequest_t + \param[in] pNetAppResponse Pointer to SlNetAppResponse_t + + \return None + \sa slcb_NetAppHttpServerHdlr + \note + \warning + \par Example + \code + TBD + \endcode +*/ +#if (defined(slcb_NetAppRequestHdlr)) +extern void slcb_NetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); +#endif + +/*! + \brief A handler for freeing the memory of the NetApp response. + + \param[in,out] buffer Pointer to the buffer to free + + \return None + \sa + \note + \warning + \par Example + \code + TBD + \endcode +*/ +#if (defined(slcb_NetAppRequestMemFree)) +extern void slcb_NetAppRequestMemFree (_u8 *buffer); +#endif + +/*! + \brief Get the timer counter value (timestamp).\n + The timer must count from zero to its MAX value. + For non-os application, this routine must be implemented. + \param None + \return Returns 32-bit timer counter value (ticks unit) + \sa + \note + \note belongs to \ref porting_sec + \warning +*/ +#if defined (slcb_GetTimestamp) +extern _u32 slcb_GetTimestamp(void); +#endif + + +/*! + \brief Socket trigger routine. + This routine will notify the application that a netwrok activity has + been completed on the required socket/s. + + \param[out] pSlSockTriggerEvent pointer to SlSockTriggerEvent_t data + \return None. + \sa + \note + \note belongs to \ref porting_sec + \warning +*/ +#if (defined(slcb_SocketTriggerEventHandler)) +extern void slcb_SocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent); +#endif + + +/*! + Close the Doxygen group. + @} + + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __SIMPLELINK_H__ */ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/sl_socket.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/sl_socket.h new file mode 100755 index 00000000000..e70c6f2ee85 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/sl_socket.h @@ -0,0 +1,1550 @@ +/* + * sl_socket.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include + +#ifndef __SL_SOCKET_H__ +#define __SL_SOCKET_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup Socket + \short Controls standard client/server sockets programming options and capabilities + +*/ +/*! + + \addtogroup Socket + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ +#undef SL_FD_SETSIZE +#define SL_FD_SETSIZE SL_MAX_SOCKETS /* Number of sockets to select on - same is max sockets! */ +#define SL_BSD_SOCKET_ID_MASK (0x1F) /* Index using the LBS 4 bits for socket id 0-7 */ + +/* Define some BSD protocol constants. */ +#define SL_SOCK_STREAM (1) /* TCP Socket */ +#define SL_SOCK_DGRAM (2) /* UDP Socket */ +#define SL_SOCK_RAW (3) /* Raw socket */ +#define SL_IPPROTO_TCP (6) /* TCP Raw Socket */ +#define SL_IPPROTO_UDP (17) /* UDP Raw Socket */ +#define SL_IPPROTO_RAW (255) /* Raw Socket */ +#define SL_SEC_SOCKET (100) /* Secured Socket Layer (SSL,TLS) */ + +/* Address families. */ +#define SL_AF_INET (2) /* IPv4 socket (UDP, TCP, etc) */ +#define SL_AF_INET6 (3) /* IPv6 socket (UDP, TCP, etc) */ +#define SL_AF_RF (6) /* data include RF parameter, All layer by user (Wifi could be disconnected) */ +#define SL_AF_PACKET (17) +/* Protocol families, same as address families. */ +#define SL_PF_INET AF_INET +#define SL_PF_INET6 AF_INET6 +#define SL_INADDR_ANY (0) /* bind any address */ +#define SL_IN6ADDR_ANY (0) + + +/* Max payload size by protocol */ +#define SL_SOCKET_PAYLOAD_TYPE_MASK (0xF0) /*4 bits type, 4 bits sockets id */ +#define SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER (0x80) /* 1536 bytes */ + +/* SL_SOCKET_EVENT_CLASS_BSD user events */ +#define SL_SOCKET_TX_FAILED_EVENT (1) +#define SL_SOCKET_ASYNC_EVENT (2) + + +/* SL_SOCKET_EVENT_CLASS_BSD user trigger events */ +#define SL_SOCKET_TRIGGER_EVENT_SELECT (1) + +#define SL_SOL_SOCKET (1) /* Define the socket option category. */ +#define SL_IPPROTO_IP (2) /* Define the IP option category. */ +#define SL_SOL_PHY_OPT (3) /* Define the PHY option category. */ + +#define SL_SO_RCVBUF (8) /* Setting TCP receive buffer size */ +#define SL_SO_KEEPALIVE (9) /* Connections are kept alive with periodic messages */ +#define SL_SO_LINGER (13) /* Socket lingers on close pending remaining send/receive packets. */ +#define SL_SO_RCVTIMEO (20) /* Enable receive timeout */ +#define SL_SO_NONBLOCKING (24) /* Enable . disable nonblocking mode */ +#define SL_SO_SECMETHOD (25) /* security metohd */ +#define SL_SO_SECURE_MASK (26) /* security mask */ +#define SL_SO_SECURE_FILES (27) /* security files */ +#define SL_SO_CHANGE_CHANNEL (28) /* This option is available only when transceiver started */ +#define SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME (30) /* This option used to configue secure file */ +#define SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME (31) /* This option used to configue secure file */ +#define SL_SO_SECURE_FILES_CA_FILE_NAME (32) /* This option used to configue secure file */ +#define SL_SO_SECURE_FILES_PEER_CERT_OR_DH_KEY_FILE_NAME (33) /* This option used to configue secure file - in server mode DH params file, and in client mode peer cert for domain verification */ +#define SL_SO_STARTTLS (35) /* initiate STARTTLS on non secure socket */ +#define SL_SO_SSL_CONNECTION_PARAMS (36) /* retrieve by getsockopt the connection params of the current SSL connection in to SlSockSSLConnectionParams_t*/ +#define SL_SO_KEEPALIVETIME (37) /* keepalive time out */ +#define SL_SO_SECURE_DISABLE_CERTIFICATE_STORE (38) /* disable certificate store */ +#define SL_SO_RX_NO_IP_BOUNDARY (39) /* connectionless socket disable rx boundary */ +#define SL_SO_SECURE_ALPN (40) /* set the ALPN bitmap list */ +#define SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP (41) /*set external challange for client certificate */ +#define SL_SO_SECURE_DOMAIN_NAME_VERIFICATION (42) /* set a domain name for verification */ + +#define SL_IP_MULTICAST_IF (60) /* Specify outgoing multicast interface */ +#define SL_IP_MULTICAST_TTL (61) /* Specify the TTL value to use for outgoing multicast packet. */ +#define SL_IP_ADD_MEMBERSHIP (65) /* Join IPv4 multicast membership */ +#define SL_IP_DROP_MEMBERSHIP (66) /* Leave IPv4 multicast membership */ +#define SL_IP_HDRINCL (67) /* Raw socket IPv4 header included. */ +#define SL_IP_RAW_RX_NO_HEADER (68) /* Proprietary socket option that does not includeIPv4/IPv6 header (and extension headers) on received raw sockets*/ +#define SL_IP_RAW_IPV6_HDRINCL (69) /* Transmitted buffer over IPv6 socket contains IPv6 header. */ +#define SL_IPV6_ADD_MEMBERSHIP (70) /* Join IPv6 multicast membership */ +#define SL_IPV6_DROP_MEMBERSHIP (71) /* Leave IPv6 multicast membership */ +#define SL_IPV6_MULTICAST_HOPS (72) /* Specify the hops value to use for outgoing multicast packet. */ + +#define SL_SO_PHY_RATE (100) /* WLAN Transmit rate */ +#define SL_SO_PHY_TX_POWER (101) /* TX Power level */ +#define SL_SO_PHY_NUM_FRAMES_TO_TX (102) /* Number of frames to transmit */ +#define SL_SO_PHY_PREAMBLE (103) /* Preamble for transmission */ +#define SL_SO_PHY_TX_INHIBIT_THRESHOLD (104) /* TX Inhibit Threshold (CCA) */ +#define SL_SO_PHY_TX_TIMEOUT (105) /* TX timeout for Transceiver frames (lifetime) in miliseconds (max value is 100ms) */ +#define SL_SO_PHY_ALLOW_ACKS (106) /* Enable sending ACKs in transceiver mode */ + +typedef enum +{ + SL_TX_INHIBIT_THRESHOLD_MIN = 1, + SL_TX_INHIBIT_THRESHOLD_LOW = 2, + SL_TX_INHIBIT_THRESHOLD_DEFAULT = 3, + SL_TX_INHIBIT_THRESHOLD_MED = 4, + SL_TX_INHIBIT_THRESHOLD_HIGH = 5, + SL_TX_INHIBIT_THRESHOLD_MAX = 6 +} SlTxInhibitThreshold_e; + +#define SL_SO_SEC_METHOD_SSLV3 (0) /* security metohd SSL v3*/ +#define SL_SO_SEC_METHOD_TLSV1 (1) /* security metohd TLS v1*/ +#define SL_SO_SEC_METHOD_TLSV1_1 (2) /* security metohd TLS v1_1*/ +#define SL_SO_SEC_METHOD_TLSV1_2 (3) /* security metohd TLS v1_2*/ +#define SL_SO_SEC_METHOD_SSLv3_TLSV1_2 (4) /* use highest possible version from SSLv3 - TLS 1.2*/ +#define SL_SO_SEC_METHOD_DLSV1 (5) /* security metohd DTL v1 */ + +#define SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA (1 << 0) +#define SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5 (1 << 1) +#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA (1 << 2) +#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA (1 << 3) +#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA (1 << 4) +#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA (1 << 5) +#define SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256 (1 << 6) +#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256 (1 << 7) +#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (1 << 8) +#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (1 << 9) +#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA (1 << 10) +#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA (1 << 11) +#define SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256 (1 << 12) +#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384 (1 << 13) +#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 14) +#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 15) +#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 16) +#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 17) +#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (1 << 18) +#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 (1 << 19) +#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 20) +#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 21) +#define SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 22) + +#define SL_SEC_MASK_SECURE_DEFAULT ((SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 << 1) - 1) + +#define SL_SECURE_ALPN_H1 (1 << 0) +#define SL_SECURE_ALPN_H2 (1 << 1) +#define SL_SECURE_ALPN_H2C (1 << 2) +#define SL_SECURE_ALPN_H2_14 (1 << 3) +#define SL_SECURE_ALPN_H2_16 (1 << 4) +#define SL_SECURE_ALPN_FULL_LIST ((SL_SECURE_ALPN_H2_16 << 1 ) - 1) + +#define SL_MSG_DONTWAIT (0x00000008) /* Nonblocking IO */ + +/* AP DHCP Server - IP Release reason code */ +#define SL_IP_LEASE_PEER_RELEASE (0) +#define SL_IP_LEASE_PEER_DECLINE (1) +#define SL_IP_LEASE_EXPIRED (2) + +/* possible types when receiving SL_SOCKET_ASYNC_EVENT*/ +#define SL_SSL_ACCEPT (0) /* accept failed due to ssl issue ( tcp pass) */ +#define SL_RX_FRAGMENTATION_TOO_BIG (1) /* connection less mode, rx packet fragmentation > 16K, packet is being released */ +#define SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED (2) /* remote side down from secure to unsecure */ +#define SL_SSL_NOTIFICATION_CONNECTED_SECURED (3) /* STARTTLS success */ +#define SL_SSL_NOTIFICATION_HANDSHAKE_FAILED (4) /* STARTTLS handshake faild */ +#define SL_SSL_NOTIFICATION_WRONG_ROOT_CA (5) /* Root CA configured is wrong, the name is in SocketAsyncEvent.EventData.extraInfo */ +#define SL_SOCKET_ASYNC_EVENT_SSL_NOTIFICATION_WRONG_ROOT_CA (5) +#define SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN (16) + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +/* Internet address */ +typedef struct SlInAddr_t +{ +#ifndef s_addr + _u32 s_addr; /* Internet address 32 bits */ +#else + union S_un { + struct { _u8 s_b1,s_b2,s_b3,s_b4; } S_un_b; + struct { _u16 s_w1,s_w2; } S_un_w; + _u32 S_addr; + } S_un; +#endif +}SlInAddr_t; + +/* IpV6 or Ipv6 EUI64 */ +typedef struct SlIn6Addr_t +{ + union + { + _u8 _S6_u8[16]; + _u32 _S6_u32[4]; + } _S6_un; +}SlIn6Addr_t; + + +/* sockopt */ +typedef struct +{ + _u32 KeepaliveEnabled; /* 0 = disabled;1 = enabled; default = 1*/ +}SlSockKeepalive_t; + +typedef struct +{ + _u32 ReuseaddrEnabled; /* 0 = disabled; 1 = enabled; default = 1*/ +}SlSockReuseaddr_t; + +typedef struct +{ + _i32 RxIpNoBoundaryEnabled; /* 0 = keep IP boundary; 1 = don`t keep ip boundary; default = 0; */ +} SlSockRxNoIpBoundary_t; + +typedef struct +{ + _u32 WinSize; /* receive window size for tcp sockets */ +}SlSockWinsize_t; + +typedef struct +{ + _u32 NonBlockingEnabled;/* 0 = disabled;1 = enabled;default = 1*/ +}SlSockNonblocking_t; + +typedef struct +{ + _u8 Sd; + _u8 Type; + _i16 Val; + _i8 pExtraInfo[128]; +} SlSocketAsyncEvent_t; + +typedef struct +{ + _i16 Status; + _u8 Sd; + _u8 Padding; +} SlSockTxFailEventData_t; + + +typedef union +{ + SlSockTxFailEventData_t SockTxFailData; + SlSocketAsyncEvent_t SockAsyncData; +} SlSockEventData_u; + + +typedef struct +{ + _u32 Event; + SlSockEventData_u SocketAsyncEvent; +} SlSockEvent_t; + +typedef struct +{ + _u32 Event; + _u32 EventData; +} SlSockTriggerEvent_t; + + +typedef struct +{ + _u32 SecureALPN; +} SlSockSecureALPN_t; + +typedef struct +{ + _u32 SecureMask; +} SlSockSecureMask_t; + +typedef struct +{ + _u8 SecureMethod; +} SlSockSecureMethod_t; + +typedef struct +{ + _u16 SubjectNameXoredSha1; + _u16 IssuerNameXoredSha1; + _i8 FromDate[8]; + _i8 ToDate[8]; + _i8 SubjectName[SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN]; + _i8 IssuerName[SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN]; + _i8 SubjectNameLen; + _i8 IssuerNameLen; + _i8 Padding[2]; +} SlSockSSLCertInfo_t; + + +typedef struct +{ + _u32 SecureVersion; /* what version of SSL decided in the handshake */ + _u32 SecureCipherSuit; /* what Cipher Index was decided in the handshake */ + _u32 SecureIsPeerValidated; /* was the other peer verified */ + _u32 SecureALPNChosenProtocol; /* bit indicate one of the protocol defined above + SL_SECURE_ALPN_H1 + SL_SECURE_ALPN_H2 + SL_SECURE_ALPN_H2C + SL_SECURE_ALPN_H2_14 + SL_SECURE_ALPN_H2_16 + */ + SlSockSSLCertInfo_t SecurePeerCertinfo; +} SlSockSSLConnectionParams_t; + + + + +typedef enum +{ + SL_SOCK_TX_RATE_1M = 1, + SL_SOCK_TX_RATE_2M = 2, + SL_SOCK_TX_RATE_5_5M = 3, + SL_SOCK_TX_RATE_11M = 4, + SL_SOCK_TX_RATE_6M = 6, + SL_SOCK_TX_RATE_9M = 7, + SL_SOCK_TX_RATE_12M = 8, + SL_SOCK_TX_RATE_18M = 9, + SL_SOCK_TX_RATE_24M = 10, + SL_SOCK_TX_RATE_36M = 11, + SL_SOCK_TX_RATE_48M = 12, + SL_SOCK_TX_RATE_54M = 13, + SL_SOCK_TX_RATE_MCS_0 = 14, + SL_SOCK_TX_RATE_MCS_1 = 15, + SL_SOCK_TX_RATE_MCS_2 = 16, + SL_SOCK_TX_RATE_MCS_3 = 17, + SL_SOCK_TX_RATE_MCS_4 = 18, + SL_SOCK_TX_RATE_MCS_5 = 19, + SL_SOCK_TX_RATE_MCS_6 = 20, + SL_SOCK_TX_RATE_MCS_7 = 21, + SL_SOCK_TX_MAX_NUM_RATES = 0xFF +}slSockTransceiverTXRateTable_e; + + +typedef enum +{ + SL_SOCK_RX_RATE_1M = 0, + SL_SOCK_RX_RATE_2M = 1, + SL_SOCK_RX_RATE_5_5M = 2, + SL_SOCK_RX_RATE_11M = 3, + SL_SOCK_RX_RATE_6M = 4, + SL_SOCK_RX_RATE_9M = 5, + SL_SOCK_RX_RATE_12M = 6, + SL_SOCK_RX_RATE_18M = 7, + SL_SOCK_RX_RATE_24M = 8, + SL_SOCK_RX_RATE_36M = 9, + SL_SOCK_RX_RATE_48M = 10, + SL_SOCK_RX_RATE_54M = 11, + SL_SOCK_RX_RATE_MCS0 = 12, /* 6.5Mbps */ + SL_SOCK_RX_RATE_MCS1 = 13, /* 13Mbps */ + SL_SOCK_RX_RATE_MCS2 = 14, /* 19.5Mbps */ + SL_SOCK_RX_RATE_MCS3 = 15, /* 26Mbps */ + SL_SOCK_RX_RATE_MCS4 = 16, /* 39Mbps */ + SL_SOCK_RX_RATE_MCS5 = 17, /* 52Mbps */ + SL_SOCK_RX_RATE_MCS6 = 18, /* 58.5Mbps */ + SL_SOCK_RX_RATE_MCS7 = 19, /* 65Mbps */ + SL_SOCK_RX_RATE_MCS7_SGI = 20, /* 65Mbps+10% */ + +}SlSockTransceiverRXRates_e; + +typedef enum +{ + SL_BSD_SECURED_PRIVATE_KEY_IDX = 0, + SL_BSD_SECURED_CERTIFICATE_IDX, + SL_BSD_SECURED_CA_IDX, + SL_BSD_SECURED_DH_IDX +}SlSockSecureSocketFilesIndex_e; + +typedef struct +{ + SlInAddr_t imr_multiaddr; /* The IPv4 multicast address to join */ + SlInAddr_t imr_interface; /* The interface to use for this group */ +}SlSockIpMreq_t; + +typedef struct{ + SlIn6Addr_t ipv6mr_multiaddr; /* IPv6 multicast address of group */ + _u32 ipv6mr_interface; /*should be 0 to choose the default multicast interface*/ +}SlSockIpV6Mreq_t; + +typedef struct +{ + _u32 l_onoff; /* 0 = disabled; 1 = enabled; default = 0;*/ + _u32 l_linger; /* linger time in seconds; default = 0;*/ +}SlSocklinger_t; + +/* sockopt */ +typedef _i32 SlTime_t; +typedef _i32 SlSuseconds_t; + +typedef struct SlTimeval_t +{ + SlTime_t tv_sec; /* Seconds */ + SlSuseconds_t tv_usec; /* Microseconds */ +}SlTimeval_t; + +typedef _u16 SlSocklen_t; + +/* IpV4 socket address */ +typedef struct SlSockAddr_t +{ + _u16 sa_family; /* Address family (e.g. , AF_INET) */ + _u8 sa_data[14]; /* Protocol- specific address information*/ +}SlSockAddr_t; + +typedef struct SlSockAddrIn6_t +{ + _u16 sin6_family; /* AF_INET6 || AF_INET6_EUI_48*/ + _u16 sin6_port; /* Transport layer port. */ + _u32 sin6_flowinfo; /* IPv6 flow information. */ + SlIn6Addr_t sin6_addr; /* IPv6 address. */ + _u32 sin6_scope_id; /* set of interfaces for a scope. */ +}SlSockAddrIn6_t; + +/* Socket address, Internet style. */ + +typedef struct SlSockAddrIn_t +{ + _u16 sin_family; /* Internet Protocol (AF_INET). */ + _u16 sin_port; /* Address port (16 bits). */ + SlInAddr_t sin_addr; /* Internet address (32 bits). */ + _i8 sin_zero[8]; /* Not used. */ +}SlSockAddrIn_t; + +typedef struct +{ + _u8 SecureFiles[4]; +}SlSockSecureFiles_t; + +typedef struct SlFdSet_t /* The select socket array manager */ +{ + _u32 fd_array[(SL_FD_SETSIZE + (_u8)31)/(_u8)32]; /* Bit map of SOCKET Descriptors */ +} SlFdSet_t; + +typedef struct +{ + _u8 Rate; /* Received Rate, refer to slSockTransceiverRXRateTable_e */ + _u8 Channel; /* The received channel*/ + _i8 Rssi; /* The computed RSSI value in db of current frame */ + _u8 Padding; /* pad to align to 32 bits */ + _u32 Timestamp; /* Timestamp in microseconds */ +}SlTransceiverRxOverHead_t; + + + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +/*! + + \brief Create an endpoint for communication + + The socket function creates a new socket of a certain socket type, identified + by an integer number, and allocates system resources to it.\n + This function is called by the application layer to obtain a socket handle. + + \param[in] Domain Specifies the protocol family of the created socket. + For example: + - SL_AF_INET for network protocol IPv4 + - SL_AF_INET6 for network protocol IPv6 + - SL_AF_RF for starting transceiver mode. Notes: + - sending and receiving any packet overriding 802.11 header + - for optimized power consumption the socket will be started in TX + only mode until receive command is activated + + \param[in] Type specifies the communication semantic, one of: + - SL_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) + - SL_SOCK_DGRAM (datagram service or Datagram Sockets) + - SL_SOCK_RAW (raw protocols atop the network layer) + - when used with AF_RF: + - SL_SOCK_DGRAM - L2 socket + - SL_SOCK_RAW - L1 socket - bypass WLAN CCA (Clear Channel Assessment) + The Protocol parameter is used to set the channel number. + \param[in] Protocol specifies a particular transport to be used with + the socket. \n + The most common are + - SL_IPPROTO_TCP + - SL_IPPROTO_UDP + The value 0 may be used to select a default + protocol from the selected domain and type + + \return On success, socket handle that is used for consequent socket operations. \n + A successful return code should be a positive number (int16)\n + On error, a negative (int16) value will be returned specifying the error code. + - SL_EAFNOSUPPORT - illegal domain parameter + - SL_EPROTOTYPE - illegal type parameter + - SL_EACCES - permission denied + - SL_ENSOCK - exceeded maximal number of socket + - SL_ENOMEM - memory allocation error + - SL_EINVAL - error in socket configuration + - SL_EPROTONOSUPPORT - illegal protocol parameter + - SL_EOPNOTSUPP - illegal combination of protocol and type parameters + + \sa sl_Close + \note belongs to \ref basic_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Socket) +_i16 sl_Socket(_i16 Domain, _i16 Type, _i16 Protocol); +#endif + +/*! + \brief Gracefully close socket + + This function causes the system to release resources allocated to a socket. \n + In case of TCP, the connection is terminated. + + \param[in] sd Socket handle (received in sl_Socket) + + \return Zero on success, or negative error code on failure + + \sa sl_Socket + \note belongs to \ref ext_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Close) +_i16 sl_Close(_i16 sd); +#endif + +/*! + \brief Accept a connection on a socket + + This function is used with connection-based socket types (SOCK_STREAM).\n + It extracts the first connection request on the queue of pending + connections, creates a new connected socket, and returns a new file + descriptor referring to that socket.\n + The newly created socket is not in the listening state. The + original socket sd is unaffected by this call. \n + The argument sd is a socket that has been created with + sl_Socket(), bound to a local address with sl_Bind(), and is + listening for connections after a sl_Listen(). The argument \b + \e addr is a pointer to a sockaddr structure. This structure + is filled in with the address of the peer socket, as known to + the communications layer. The exact format of the address + returned addr is determined by the socket's address family. \n + The \b \e addrlen argument is a value-result argument: it + should initially contain the size of the structure pointed to + by addr, on return it will contain the actual length (in + bytes) of the address returned. + + \param[in] sd Socket descriptor (handle) + \param[out] addr The argument addr is a pointer + to a sockaddr structure. This + structure is filled in with the + address of the peer socket, as + known to the communications + layer. The exact format of the + address returned addr is + determined by the socket's + address\n + sockaddr:\n - code for the + address format. On this version + only AF_INET is supported.\n - + socket address, the length + depends on the code format + \param[out] addrlen The addrlen argument is a value-result + argument: it should initially contain the + size of the structure pointed to by addr + + \return On success, a socket handle.\n + On a non-blocking accept a possible negative value is SL_EAGAIN.\n + On failure, negative error code.\n + SL_POOL_IS_EMPTY may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa sl_Socket sl_Bind sl_Listen + \note Belongs to \ref server_side + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Accept) +_i16 sl_Accept(_i16 sd, SlSockAddr_t *addr, SlSocklen_t *addrlen); +#endif + +/*! + \brief Assign a name to a socket + + This function gives the socket the local address addr. + addr is addrlen bytes long. Traditionally, this is called + When a socket is created with socket, it exists in a name + space (address family) but has no name assigned. + It is necessary to assign a local address before a SOCK_STREAM + socket may receive connections. + + \param[in] sd Socket descriptor (handle) + \param[in] addr Specifies the destination + addrs\n sockaddr:\n - code for + the address format. On this + version only SL_AF_INET is + supported.\n - socket address, + the length depends on the code + format + \param[in] addrlen Contains the size of the structure pointed to by addr + + \return Zero on success, or negative error code on failure + + \sa sl_Socket sl_Accept sl_Listen + \note belongs to \ref basic_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Bind) +_i16 sl_Bind(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen); +#endif + +/*! + \brief Listen for connections on a socket + + The willingness to accept incoming connections and a queue + limit for incoming connections are specified with listen(), + and then the connections are accepted with accept. + The listen() call applies only to sockets of type SOCK_STREAM + The backlog parameter defines the maximum length the queue of + pending connections may grow to. + + \param[in] sd Socket descriptor (handle) + \param[in] backlog Specifies the listen queue depth. + + \return Zero on success, or negative error code on failure + + \sa sl_Socket sl_Accept sl_Bind + \note Belongs to \ref server_side + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Listen) +_i16 sl_Listen(_i16 sd, _i16 backlog); +#endif + +/*! + \brief Initiate a connection on a socket + + Function connects the socket referred to by the socket + descriptor sd, to the address specified by addr. The addrlen + argument specifies the size of addr. The format of the + address in addr is determined by the address space of the + socket. If it is of type SOCK_DGRAM, this call specifies the + peer with which the socket is to be associated; this address + is that to which datagrams are to be sent, and the only + address from which datagrams are to be received. If the + socket is of type SOCK_STREAM, this call attempts to make a + connection to another socket. The other socket is specified + by address, which is an address in the communications space + of the socket. + + + \param[in] sd Socket descriptor (handle) + \param[in] addr Specifies the destination addr\n + sockaddr:\n - code for the + address format. On this version + only AF_INET is supported.\n - + socket address, the length + depends on the code format + + \param[in] addrlen Contains the size of the structure pointed + to by addr + + \return On success, a socket handle.\n + On a non-blocking connect a possible negative value is SL_EALREADY. + On failure, negative value.\n + SL_POOL_IS_EMPTY may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa sl_Socket + \note belongs to \ref client_side + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Connect) +_i16 sl_Connect(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen); +#endif + +/*! + \brief Monitor socket activity + + Select allow a program to monitor multiple file descriptors, + waiting until one or more of the file descriptors become + "ready" for some class of I/O operation. + If trigger mode is enabled the active fdset is the one that was retrieved in the first triggered call. + To enable the trigger mode, an handler must be statically registered as slcb_SocketTriggerEventHandler in user.h + + + \param[in] nfds The highest-numbered file descriptor in any of the + three sets, plus 1. + \param[out] readsds Socket descriptors list for read monitoring and accept monitoring + \param[out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported + \param[out] exceptsds Socket descriptors list for exception monitoring, not supported. + \param[in] timeout Is an upper bound on the amount of time elapsed + before select() returns. Null or above 0xffff seconds means + infinity timeout. The minimum timeout is 10 milliseconds, + less than 10 milliseconds will be set automatically to 10 milliseconds. + Max microseconds supported is 0xfffc00. + In trigger mode the timout fields must be set to zero. + + \return On success, select() returns the number of + file descriptors contained in the three returned + descriptor sets (that is, the total number of bits that + are set in readfds, writefds, exceptfds) which may be + zero if the timeout expires before anything interesting + happens.\n On error, a negative value is returned. + readsds - return the sockets on which read request will + return without delay with valid data.\n + writesds - return the sockets on which write request + will return without delay.\n + exceptsds - return the sockets closed recently. \n + SL_POOL_IS_EMPTY may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa sl_Socket + \note If the timeout value set to less than 10ms it will automatically set + to 10ms to prevent overload of the system\n + Belongs to \ref basic_api + + Several threads can call sl_Select at the same time.\b + Calling this API while the same command is called from another thread, may result + in one of the following scenarios: + 1. The command will be executed alongside other select callers (success). + 2. The command will wait (internal) until the previous sl_select finish, and then be executed. + 3. There are not enough resources and SL_POOL_IS_EMPTY error will return. + In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try + again later to issue the command. + + In case all the user sockets are open, sl_Select will exhibit the behavior mentioned in (2) + This is due to the fact sl_select supports multiple callers by utilizing one user socket internally. + User who wish to ensure multiple select calls at any given time, must reserve one socket out of the 16 given. + + \warning + multiple select calls aren't supported when trigger mode is active. The two are mutually exclusive. +*/ +#if _SL_INCLUDE_FUNC(sl_Select) +_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout); +#endif + + + +/*! + \brief Set socket options- + + This function manipulate the options associated with a socket.\n + Options may exist at multiple protocol levels; they are always + present at the uppermost socket level.\n + + When manipulating socket options the level at which the option resides + and the name of the option must be specified. To manipulate options at + the socket level, level is specified as SOL_SOCKET. To manipulate + options at any other level the protocol number of the appropriate proto- + col controlling the option is supplied. For example, to indicate that an + option is to be interpreted by the TCP protocol, level should be set to + the protocol number of TCP; \n + + The parameters optval and optlen are used to access optval - + ues for setsockopt(). For getsockopt() they identify a + buffer in which the value for the requested option(s) are to + be returned. For getsockopt(), optlen is a value-result + parameter, initially containing the size of the buffer + pointed to by option_value, and modified on return to + indicate the actual size of the value returned. If no option + value is to be supplied or returned, option_value may be + NULL. + + \param[in] sd Socket handle + \param[in] level Defines the protocol level for this option + - SL_SOL_SOCKET Socket level configurations (L4, transport layer) + - SL_IPPROTO_IP IP level configurations (L3, network layer) + - SL_SOL_PHY_OPT Link level configurations (L2, link layer) + \param[in] optname Defines the option name to interrogate + - SL_SOL_SOCKET + - SL_SO_KEEPALIVE \n + Enable/Disable periodic keep alive. + Keeps TCP connections active by enabling the periodic transmission of messages \n + Timeout is 5 minutes.\n + Default: Enabled \n + This options takes SlSockKeepalive_t struct as parameter + - SL_SO_KEEPALIVETIME \n + Set keep alive timeout. + Value is in seconds \n + Default: 5 minutes \n + - SL_SO_RX_NO_IP_BOUNDARY \n + Enable/Disable rx ip boundary. + In connectionless socket (udp/raw), unread data is dropped (when recvfrom len parameter < data size), Enable this option in order to read the left data on the next recvfrom iteration + Default: Disabled, IP boundary kept, \n + This options takes SlSockRxNoIpBoundary_t struct as parameter + - SL_SO_RCVTIMEO \n + Sets the timeout value that specifies the maximum amount of time an input function waits until it completes. \n + Default: No timeout \n + This options takes SlTimeval_t struct as parameter + - SL_SO_RCVBUF \n + Sets tcp max recv window size. \n + This options takes SlSockWinsize_t struct as parameter + - SL_SO_NONBLOCKING \n + Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n + Default: Blocking. + This options takes SlSockNonblocking_t struct as parameter + - SL_SO_SECMETHOD \n + Sets method to tcp secured socket (SL_SEC_SOCKET) \n + Default: SL_SO_SEC_METHOD_SSLv3_TLSV1_2 \n + This options takes SlSockSecureMethod_t struct as parameter + - SL_SO_SECURE_MASK \n + Sets specific cipher to tcp secured socket (SL_SEC_SOCKET) \n + Default: "Best" cipher suitable to method \n + This options takes SlSockSecureMask_t struct as parameter + - SL_SO_SECURE_FILES_CA_FILE_NAME \n + Map secured socket to CA file by name \n + This options takes _u8 buffer as parameter + - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME \n + Map secured socket to private key by name \n + This options takes _u8 buffer as parameter + - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME \n + Map secured socket to certificate file by name \n + This options takes _u8 buffer as parameter + - SL_SO_SECURE_FILES_DH_KEY_FILE_NAME \n + Map secured socket to Diffie Hellman file by name \n + This options takes _u8 buffer as parameter + - SL_SO_CHANGE_CHANNEL \n + Sets channel in transceiver mode. + This options takes _u32 as channel number parameter + - SL_SO_SECURE_ALPN \n + Sets the ALPN list. the parameter is a bit map consist of or of the following values - + SL_SECURE_ALPN_H1 + SL_SECURE_ALPN_H2 + SL_SECURE_ALPN_H2C + SL_SECURE_ALPN_H2_14 + SL_SECURE_ALPN_H2_16 + SL_SECURE_ALPN_FULL_LIST + - SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP \n + Set with no parameter to indicate that the client uses external signature using netapp request.\n + needs netapp request handler\n + - SL_SO_SECURE_DOMAIN_NAME_VERIFICATION \n + Set a domain name, to check in ssl client connection. + - SL_IPPROTO_IP + - SL_IP_MULTICAST_TTL \n + Set the time-to-live value of outgoing multicast packets for this socket. \n + This options takes _u8 as parameter + - SL_IP_ADD_MEMBERSHIP \n + UDP socket, Join a multicast group. \n + This options takes SlSockIpMreq_t struct as parameter + - SL_IP_DROP_MEMBERSHIP \n + UDP socket, Leave a multicast group \n + This options takes SlSockIpMreq_t struct as parameter + - SL_IP_RAW_RX_NO_HEADER \n + Raw socket remove IP header from received data. \n + Default: data includes ip header \n + This options takes _u32 as parameter + - SL_IP_HDRINCL \n + RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n + the IP_HDRINCL socket option is enabled on the socket. \n + When it is enabled, the packet must contain an IP header. \n + Default: disabled, IPv4 header generated by Network Stack \n + This options takes _u32 as parameter + - SL_IP_RAW_IPV6_HDRINCL (inactive) \n + RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n + the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n + Default: disabled, IPv4 header generated by Network Stack \n + This options takes _u32 as parameter + - SL_SOL_PHY_OPT + - SL_SO_PHY_RATE \n + RAW socket, set WLAN PHY transmit rate \n + The values are based on SlWlanRateIndex_e \n + This options takes _u32 as parameter + - SL_SO_PHY_TX_POWER \n + RAW socket, set WLAN PHY TX power \n + Valid rage is 1-15 \n + This options takes _u32 as parameter + - SL_SO_PHY_NUM_FRAMES_TO_TX \n + RAW socket, set number of frames to transmit in transceiver mode. + Default: 1 packet + This options takes _u32 as parameter + - SL_SO_PHY_PREAMBLE \n + RAW socket, set WLAN PHY preamble for Long/Short\n + This options takes _u32 as parameter + - SL_SO_PHY_TX_INHIBIT_THRESHOLD \n + RAW socket, set WLAN Tx – Set CCA threshold. \n + The values are based on SlTxInhibitThreshold_e \n + This options takes _u32 as parameter + - SL_SO_PHY_TX_TIMEOUT \n + RAW socket, set WLAN Tx – changes the TX timeout (lifetime) of transceiver frames. \n + Value in Ms, maximum value is 100ms \n + This options takes _u32 as parameter + - SL_SO_PHY_ALLOW_ACKS \n + RAW socket, set WLAN Tx – Enable\Disable sending ACKs in transceiver mode \n + 0 = disabled / 1 = enabled \n + This options takes _u32 as parameter + - SL_SO_LINGER \n + Socket lingers on close pending remaining send/receive packets\n + + \param[in] optval Specifies a value for the option + \param[in] optlen Specifies the length of the + option value + + \return Zero on success, or negative error code on failure + + \par Persistent + All params are Non- Persistent + \sa sl_getsockopt + \note Belongs to \ref basic_api + \warning + \par Examples + + - SL_SO_KEEPALIVE (disable Keepalive): + \code + SlSockKeepalive_t enableOption; + enableOption.KeepaliveEnabled = 0; + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_KEEPALIVE, (_u8 *)&enableOption,sizeof(enableOption)); + \endcode +
+ + - SL_SO_KEEPALIVETIME (Set Keepalive timeout): + \code + _i16 Status; + _u32 TimeOut = 120; + sl_SetSockOpt(Sd, SL_SOL_SOCKET, SL_SO_KEEPALIVETIME,( _u8*) &TimeOut, sizeof(TimeOut)); + \endcode +
+ + - SL_SO_RX_NO_IP_BOUNDARY (disable boundary): + \code + SlSockRxNoIpBoundary_t enableOption; + enableOption.RxIpNoBoundaryEnabled = 1; + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RX_NO_IP_BOUNDARY, (_u8 *)&enableOption,sizeof(enableOption)); + \endcode +
+ + - SL_SO_RCVTIMEO: + \code + struct SlTimeval_t timeVal; + timeVal.tv_sec = 1; // Seconds + timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RCVTIMEO, (_u8 *)&timeVal, sizeof(timeVal)); // Enable receive timeout + \endcode +
+ + - SL_SO_RCVBUF: + \code + SlSockWinsize_t size; + size.Winsize = 3000; // bytes + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RCVBUF, (_u8 *)&size, sizeof(size)); + \endcode +
+ + - SL_SO_NONBLOCKING: + \code + + SlSockNonblocking_t enableOption; + enableOption.NonblockingEnabled = 1; + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_NONBLOCKING, (_u8 *)&enableOption,sizeof(enableOption)); // Enable/disable nonblocking mode + \endcode +
+ + - SL_SO_SECMETHOD: + \code + SlSockSecureMethod_t method; + method.SecureMethod = SL_SO_SEC_METHOD_SSLV3; // security method we want to use + SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, SL_SEC_SOCKET); + sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECMETHOD, (_u8 *)&method, sizeof(method)); + \endcode +
+ + - SL_SO_SECURE_MASK: + \code + SlSockSecureMask_t cipher; + cipher.SecureMask = SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA; // cipher type + SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, SL_SEC_SOCKET); + sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_MASK,(_u8 *)&cipher, sizeof(cipher)); + \endcode +
+ + - SL_SO_SECURE_FILES_CA_FILE_NAME: + \code + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_CA_FILE_NAME,"exuifaxCaCert.der",strlen("exuifaxCaCert.der")); + \endcode +
+ + - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME; + \code + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME,"myPrivateKey.der",strlen("myPrivateKey.der")); + \endcode +
+ + - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME: + \code + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME,"myCertificate.der",strlen("myCertificate.der")); + \endcode +
+ + - SL_SO_SECURE_FILES_DH_KEY_FILE_NAME: + \code + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_DH_KEY_FILE_NAME,"myDHinServerMode.der",strlen("myDHinServerMode.der")); + \endcode +
+ + + - SL_IP_MULTICAST_TTL: + \code + _u8 ttl = 20; + sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_MULTICAST_TTL, &ttl, sizeof(ttl)); + \endcode +
+ + - SL_IP_ADD_MEMBERSHIP: + \code + SlSockIpMreq_t mreq; + sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); + \endcode +
+ + - SL_IP_DROP_MEMBERSHIP: + \code + SlSockIpMreq_t mreq; + sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); + \endcode +
+ + - SL_SO_CHANGE_CHANNEL: + \code + _u32 newChannel = 6; // range is 1-13 + sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_CHANGE_CHANNEL, &newChannel, sizeof(newChannel)); + \endcode +
+ + - SL_SO_SECURE_ALPN: + \code + SlSockSecureALPN_t alpn; + alpn.SecureALPN = SL_SECURE_ALPN_H2 | SL_SECURE_ALPN_H2_14; + sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_ALPN, &alpn, sizeof(SlSockSecureALPN_t)); + \endcode +
+ + - SL_IP_RAW_RX_NO_HEADER: + \code + _u32 header = 1; // remove ip header + sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_RAW_RX_NO_HEADER, &header, sizeof(header)); + \endcode +
+ + - SL_IP_HDRINCL: + \code + _u32 header = 1; + sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_HDRINCL, &header, sizeof(header)); + \endcode +
+ + - SL_IP_RAW_IPV6_HDRINCL: + \code + _u32 header = 1; + sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_RAW_IPV6_HDRINCL, &header, sizeof(header)); + \endcode +
+ + - SL_SO_PHY_RATE: + \code + _u32 rate = 6; // see wlan.h SlWlanRateIndex_e for values + sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_RATE, &rate, sizeof(rate)); + \endcode +
+ + - SL_SO_PHY_TX_POWER: + \code + _u32 txpower = 1; // valid range is 1-15 + sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_POWER, &txpower, sizeof(txpower)); + \endcode +
+ + - SL_SO_PHY_NUM_FRAMES_TO_TX: + \code + _u32 numframes = 1; + sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); + \endcode +
+ + - SL_SO_PHY_PREAMBLE: + \code + _u32 preamble = 1; + sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_PREAMBLE, &preamble, sizeof(preamble)); + \endcode +
+ + - SL_SO_PHY_TX_INHIBIT_THRESHOLD: + \code + _u32 thrshld = SL_TX_INHIBIT_THRESHOLD_MED; + sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_INHIBIT_THRESHOLD , &thrshld, sizeof(thrshld)); + \endcode +
+ + - SL_SO_PHY_TX_TIMEOUT: + \code + _u32 timeout = 50; + sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_TIMEOUT , &timeout, sizeof(timeout)); + \endcode +
+ + - SL_SO_PHY_ALLOW_ACKS: + \code + _u32 acks = 1; // 0 = disabled / 1 = enabled + sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_ALLOW_ACKS, &acks, sizeof(acks)); + \endcode +
+ + - SL_SO_LINGER: + \code + SlSocklinger_t linger; + linger.l_onoff = 1; + linger.l_linger = 10; + sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_LINGER, &linger, sizeof(linger)); + \endcode +
+ + - SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP: + \code + int dummy; + sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP, &dummy, sizeof(dummy)); + \endcode +
+ + - SL_SO_SECURE_DOMAIN_NAME_VERIFICATION: + \code + sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_DOMAIN_NAME_VERIFICATION,"www.google.co.il",strlen("www.google.co.il")); + \endcode + +*/ +#if _SL_INCLUDE_FUNC(sl_SetSockOpt) +_i16 sl_SetSockOpt(_i16 sd, _i16 level, _i16 optname, const void *optval, SlSocklen_t optlen); +#endif + +/*! + \brief Get socket options + + This function manipulate the options associated with a socket. + Options may exist at multiple protocol levels; they are always + present at the uppermost socket level.\n + + When manipulating socket options the level at which the option resides + and the name of the option must be specified. To manipulate options at + the socket level, level is specified as SOL_SOCKET. To manipulate + options at any other level the protocol number of the appropriate + protocol controlling the option is supplied. For example, to indicate + that an option is to be interpreted by the TCP protocol, level should + be set to the protocol number of TCP; \n + + The parameters optval and optlen are used to access optvalues + for setsockopt(). For getsockopt() they identify a + buffer in which the value for the requested option(s) are to + be returned. For getsockopt(), optlen is a value-result + parameter, initially containing the size of the buffer + pointed to by option_value, and modified on return to + indicate the actual size of the value returned. If no option + value is to be supplied or returned, option_value may be + NULL. + + + \param[in] sd Socket handle + \param[in] level Defines the protocol level for this option + \param[in] optname defines the option name to interrogate + \param[out] optval Specifies a value for the option + \param[out] optlen Specifies the length of the + option value + + \return Zero on success, or negative error code on failure + \sa sl_SetSockOpt + \note See sl_SetSockOpt + Belongs to \ref ext_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_GetSockOpt) +_i16 sl_GetSockOpt(_i16 sd, _i16 level, _i16 optname, void *optval, SlSocklen_t *optlen); +#endif + +/*! + \brief Read data from TCP socket + + Function receives a message from a connection-mode socket + + \param[in] sd Socket handle + \param[out] buf Points to the buffer where the + message should be stored. + \param[in] len Specifies the length in bytes of + the buffer pointed to by the buffer argument. + Range: 1-16000 bytes + \param[in] flags Specifies the type of message + reception. On this version, this parameter is not + supported. + + \return Return the number of bytes received, + or a negative value if an error occurred.\n + Using a non-blocking recv a possible negative value is SL_EAGAIN.\n + SL_POOL_IS_EMPTY may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa sl_RecvFrom + \note Belongs to \ref recv_api + \warning + \par Examples + + - Receiving data using TCP socket: + \code + SlSockAddrIn_t Addr; + SlSockAddrIn_t LocalAddr; + _i16 AddrSize = sizeof(SlSockAddrIn_t); + _i16 SockID, newSockID; + _i16 Status; + _i8 Buf[RECV_BUF_LEN]; + + LocalAddr.sin_family = SL_AF_INET; + LocalAddr.sin_port = sl_Htons(5001); + LocalAddr.sin_addr.s_addr = 0; + + Addr.sin_family = SL_AF_INET; + Addr.sin_port = sl_Htons(5001); + Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); + + SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); + Status = sl_Bind(SockID, (SlSockAddr_t *)&LocalAddr, AddrSize); + Status = sl_Listen(SockID, 0); + newSockID = sl_Accept(SockID, (SlSockAddr_t*)&Addr, (SlSocklen_t*) &AddrSize); + Status = sl_Recv(newSockID, Buf, 1460, 0); + \endcode +
+ + - Rx transceiver mode using a raw socket: + \code + _i8 buffer[1536]; + _i16 sd; + _u16 size; + SlTransceiverRxOverHead_t *transHeader; + sd = sl_Socket(SL_AF_RF,SL_SOCK_RAW,11); // channel 11 + while(1) + { + size = sl_Recv(sd,buffer,1536,0); + transHeader = (SlTransceiverRxOverHead_t *)buffer; + printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlTransceiverRxOverHead_t)],size); + } + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_Recv) +_i16 sl_Recv(_i16 sd, void *buf, _i16 len, _i16 flags); +#endif + +/*! + \brief Read data from socket + + Function receives a message from a connection-mode or + connectionless-mode socket + + \param[in] sd Socket handle + \param[out] buf Points to the buffer where the message should be stored. + \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. + Range: 1-16000 bytes + \param[in] flags Specifies the type of message + reception. On this version, this parameter is not + supported. + \param[in] from Pointer to an address structure + indicating the source + address.\n sockaddr:\n - code + for the address format. On this + version only AF_INET is + supported.\n - socket address, + the length depends on the code + format + \param[in] fromlen Source address structure + size. This parameter MUST be set to the size of the structure pointed to by addr. + + + \return Return the number of bytes received, + or a negative value if an error occurred.\n + Using a non-blocking recv a possible negative value is SL_EAGAIN. + SL_RET_CODE_INVALID_INPUT (-2) will be returned if fromlen has incorrect length. \n + SL_POOL_IS_EMPTY may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa sl_Recv + \note Belongs to \ref recv_api + \warning + \par Example + + - Receiving data: + \code + SlSockAddrIn_t Addr; + SlSockAddrIn_t LocalAddr; + _i16 AddrSize = sizeof(SlSockAddrIn_t); + _i16 SockID; + _i16 Status; + _i8 Buf[RECV_BUF_LEN]; + + LocalAddr.sin_family = SL_AF_INET; + LocalAddr.sin_port = sl_Htons(5001); + LocalAddr.sin_addr.s_addr = 0; + + SockID = sl_Socket(SL_AF_INET,SL_SOCK_DGRAM, 0); + Status = sl_Bind(SockID, (SlSockAddr_t *)&LocalAddr, AddrSize); + Status = sl_RecvFrom(SockID, Buf, 1472, 0, (SlSockAddr_t *)&Addr, (SlSocklen_t*)&AddrSize); + + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_RecvFrom) +_i16 sl_RecvFrom(_i16 sd, void *buf, _i16 len, _i16 flags, SlSockAddr_t *from, SlSocklen_t *fromlen); +#endif + +/*! + \brief Write data to TCP socket + + This function is used to transmit a message to another socket. + Returns immediately after sending data to device. + In case of TCP failure an async event SL_SOCKET_TX_FAILED_EVENT is going to + be received.\n + In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the + frame data buffer for WLAN FCS + + \param[in] sd Socket handle + \param[in] buf Points to a buffer containing + the message to be sent + \param[in] len Message size in bytes. Range: 1-1460 bytes + \param[in] flags Specifies the type of message + transmission. On this version, this parameter is not + supported for TCP. + For transceiver mode, the SL_WLAN_RAW_RF_TX_PARAMS macro can be used to determine + transmission parameters (channel,rate,tx_power,preamble) + -rate need to be define using slSockTransceiverTXRateTable_e + + + \return Zero on success, or negative error code on failure + + \sa sl_SendTo + \note Belongs to \ref send_api + \warning + \par Example + + - Sending data: + \code + SlSockAddrIn_t Addr; + _i16 AddrSize = sizeof(SlSockAddrIn_t); + _i16 SockID; + _i16 Status; + _i8 Buf[SEND_BUF_LEN]; + + Addr.sin_family = SL_AF_INET; + Addr.sin_port = sl_Htons(5001); + Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); + + SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); + Status = sl_Connect(SockID, (SlSockAddr_t *)&Addr, AddrSize); + Status = sl_Send(SockID, Buf, 1460, 0 ); + \endcode + */ +#if _SL_INCLUDE_FUNC(sl_Send ) +_i16 sl_Send(_i16 sd, const void *buf, _i16 len, _i16 flags); +#endif + +/*! + \brief Write data to socket + + This function is used to transmit a message to another socket + (connection less socket SOCK_DGRAM, SOCK_RAW).\n + Returns immediately after sending data to device.\n + In case of transmission failure an async event SL_SOCKET_TX_FAILED_EVENT is going to + be received. + + \param[in] sd Socket handle + \param[in] buf Points to a buffer containing + the message to be sent + \param[in] len message size in bytes. Range: 1-1460 bytes + \param[in] flags Specifies the type of message + transmission. On this version, this parameter is not + supported + \param[in] to Pointer to an address structure + indicating the destination + address.\n sockaddr:\n - code + for the address format. On this + version only AF_INET is + supported.\n - socket address, + the length depends on the code + format + \param[in] tolen Destination address structure size + + \return Zero on success, or negative error code on failure + + \sa sl_Send + \note Belongs to \ref send_api + \warning + \par Example + + - Sending data: + \code + SlSockAddrIn_t Addr; + _i16 AddrSize = sizeof(SlSockAddrIn_t); + _i16 SockID; + _i16 Status; + _i8 Buf[SEND_BUF_LEN]; + + Addr.sin_family = SL_AF_INET; + Addr.sin_port = sl_Htons(5001); + Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); + + SockID = sl_Socket(SL_AF_INET,SL_SOCK_DGRAM, 0); + Status = sl_SendTo(SockID, Buf, 1472, 0, (SlSockAddr_t *)&Addr, AddrSize); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_SendTo) +_i16 sl_SendTo(_i16 sd, const void *buf, _i16 len, _i16 flags, const SlSockAddr_t *to, SlSocklen_t tolen); +#endif + +/*! + \brief Initiate TLS connection on a socket + + Function Initiate TLS connection on the socket referred to by + the socket descriptor sd. This function will works on blocking + mode until the TLS handshake success or fails. + + \param[in] sd Socket descriptor (handle) + + \return Zero on success, or negative error code on failure + + \sa sl_Socket + \note belongs to \ref client_side + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_StartTLS) +_i16 sl_StartTLS(_i16 sd); +#endif + +/*! + \brief Reorder the bytes of a 32-bit unsigned value + + This function is used to Reorder the bytes of a 32-bit unsigned value from processor order to network order. + + \param[in] val Variable to reorder + + \return Return the reorder variable, + + \sa sl_SendTo sl_Bind sl_Connect sl_RecvFrom sl_Accept + \note Belongs to \ref send_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Htonl ) +_u32 sl_Htonl( _u32 val ); + +#define sl_Ntohl sl_Htonl /* Reorder the bytes of a 16-bit unsigned value from network order to processor orde. */ +#endif + +/*! + \brief Reorder the bytes of a 16-bit unsigned value + + This function is used to Reorder the bytes of a 16-bit unsigned value from processor order to network order. + + \param[in] val Variable to reorder + + \return Return the reorder variable, + + \sa sl_SendTo sl_Bind sl_Connect sl_RecvFrom sl_Accept + \note Belongs to \ref send_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_Htons ) +_u16 sl_Htons( _u16 val ); + +#define sl_Ntohs sl_Htons /* Reorder the bytes of a 16-bit unsigned value from network order to processor orde. */ +#endif + +/*! + \cond DOXYGEN_IGNORE +*/ + +/*! + \brief Select's SlFdSet_t SET function + + Sets current socket descriptor on SlFdSet_t container +*/ +void SL_SOCKET_FD_SET(_i16 fd, SlFdSet_t *fdset); + +/*! + \brief Select's SlFdSet_t CLR function + + Clears current socket descriptor on SlFdSet_t container +*/ +void SL_SOCKET_FD_CLR(_i16 fd, SlFdSet_t *fdset); + + +/*! + \brief Select's SlFdSet_t ISSET function + + Checks if current socket descriptor is set (TRUE/FALSE) + + \return Returns TRUE if set, FALSE if unset + +*/ +_i16 SL_SOCKET_FD_ISSET(_i16 fd, SlFdSet_t *fdset); + +/*! + \brief Select's SlFdSet_t ZERO function + + Clears all socket descriptors from SlFdSet_t +*/ +void SL_SOCKET_FD_ZERO(SlFdSet_t *fdset); + +/*! + \endcond +*/ + +/*! + + Close the Doxygen group. + @} + + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __SOCKET_H__ */ + + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetif/slnetifwifi.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetif/slnetifwifi.c new file mode 100755 index 00000000000..9d9c2d15a22 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetif/slnetifwifi.c @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +/* Macro which split the 8bit security flags from the input flags */ +#define SPLIT_SEC_AND_INPUT_FLAGS(inputFlags, secFlags) (secFlags = inputFlags >> 24) + +/* Disable the 8bit security flags */ +#define SECURITY_FLAGS_IN_32BIT_REPRESENTATION (0xFF000000) +#define DISABLE_SEC_BITS_FROM_INPUT_FLAGS(inputFlags) (inputFlags &= ~SECURITY_FLAGS_IN_32BIT_REPRESENTATION) + + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global declarations */ +/*****************************************************************************/ + +/*! + SlNetIfConfigWifi structure contains all the function callbacks that are expected to be filled by the relevant network stack interface + Each interface has different capabilities, so not all the API's must be supported. + Interface that is not supporting a non-mandatory API are set to NULL +*/ +SlNetIf_Config_t SlNetIfConfigWifi = +{ + SlNetIfWifi_socket, // Callback function sockCreate in slnetif module + SlNetIfWifi_close, // Callback function sockClose in slnetif module + NULL, // Callback function sockShutdown in slnetif module + SlNetIfWifi_accept, // Callback function sockAccept in slnetif module + SlNetIfWifi_bind, // Callback function sockBind in slnetif module + SlNetIfWifi_listen, // Callback function sockListen in slnetif module + SlNetIfWifi_connect, // Callback function sockConnect in slnetif module + NULL, // Callback function sockGetPeerName in slnetif module + NULL, // Callback function sockGetLocalName in slnetif module + SlNetIfWifi_select, // Callback function sockSelect in slnetif module + SlNetIfWifi_setSockOpt, // Callback function sockSetOpt in slnetif module + SlNetIfWifi_getSockOpt, // Callback function sockGetOpt in slnetif module + SlNetIfWifi_recv, // Callback function sockRecv in slnetif module + SlNetIfWifi_recvFrom, // Callback function sockRecvFrom in slnetif module + SlNetIfWifi_send, // Callback function sockSend in slnetif module + SlNetIfWifi_sendTo, // Callback function sockSendTo in slnetif module + SlNetIfWifi_sockstartSec, // Callback function sockstartSec in slnetif module + SlNetIfWifi_getHostByName, // Callback function utilGetHostByName in slnetif module + SlNetIfWifi_getIPAddr, // Callback function ifGetIPAddr in slnetif module + SlNetIfWifi_getConnectionStatus, // Callback function ifGetConnectionStatus in slnetif module + SlNetIfWifi_loadSecObj, // Callback function ifLoadSecObj in slnetif module + NULL // Callback function ifCreateContext in slnetif module +}; + +static const int16_t StartSecOptName[10] = +{ + SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME, + SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME, + SL_SO_SECURE_FILES_CA_FILE_NAME, + SL_SO_SECURE_FILES_PEER_CERT_OR_DH_KEY_FILE_NAME, + SL_SO_SECMETHOD, + SL_SO_SECURE_MASK, + SL_SO_SECURE_ALPN, + SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP, + SL_SO_SECURE_DOMAIN_NAME_VERIFICATION, + SL_SO_SECURE_DISABLE_CERTIFICATE_STORE +}; + +static const int16_t socketType[8] = +{ + SL_SOCK_STREAM, + SL_SOCK_DGRAM, + SL_SOCK_RAW, + SLNETSOCK_SOCK_RX_MTR, + SL_SOCK_DGRAM, + SL_SOCK_RAW, + SLNETSOCK_SOCK_BRIDGE, + SLNETSOCK_SOCK_ROUTER, +}; + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +//***************************************************************************** +// +// SlNetIfWifi_socket - Create an endpoint for communication +// +//***************************************************************************** +int16_t SlNetIfWifi_socket(void *ifContext, int16_t Domain, int16_t Type, int16_t Protocol, void **sdContext) +{ + /* Create socket and return the return value of the function */ + int16_t mappedSocketType = socketType[Type - 1]; + return (sl_Socket(Domain, mappedSocketType, Protocol)); +} + + +//***************************************************************************** +// +// SlNetIfWifi_close - Gracefully close socket +// +//***************************************************************************** +int32_t SlNetIfWifi_close(int16_t sd, void *sdContext) +{ + /* Close socket and return the return value of the function */ + return sl_Close(sd); +} + + +//***************************************************************************** +// +// SlNetIfWifi_accept - Accept a connection on a socket +// +//***************************************************************************** +int16_t SlNetIfWifi_accept(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext) +{ + return sl_Accept(sd, (SlSockAddr_t *)addr, addrlen); +} + + +//***************************************************************************** +// +// SlNetIfWifi_bind - Assign a name to a socket +// +//***************************************************************************** +int32_t SlNetIfWifi_bind(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen) +{ + return sl_Bind(sd, (const SlSockAddr_t *)addr, addrlen); +} + + +//***************************************************************************** +// +// SlNetIfWifi_listen - Listen for connections on a socket +// +//***************************************************************************** +int32_t SlNetIfWifi_listen(int16_t sd, void *sdContext, int16_t backlog) +{ + return sl_Listen(sd, backlog); +} + + +//***************************************************************************** +// +// SlNetIfWifi_connect - Initiate a connection on a socket +// +//***************************************************************************** +int32_t SlNetIfWifi_connect(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags) +{ + return sl_Connect(sd, (const SlSockAddr_t *)addr, addrlen); +} + + +//***************************************************************************** +// +// SlNetIfWifi_getSockName - Returns the local address info of the socket +// descriptor +// +//***************************************************************************** +int32_t SlNetIfWifi_getSockName(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen) +{ +// Not implemented in NWP + return SLNETERR_INVALPARAM; +} + + +//***************************************************************************** +// +// SlNetIfWifi_select - Monitor socket activity +// +//***************************************************************************** +int32_t SlNetIfWifi_select(void *ifContext, int16_t nfds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout) +{ + return sl_Select(nfds, (SlFdSet_t *)readsds, (SlFdSet_t *)writesds, (SlFdSet_t *)exceptsds, (struct SlTimeval_t *)timeout); +} + + +//***************************************************************************** +// +// SlNetIfWifi_setSockOpt - Set socket options +// +//***************************************************************************** +int32_t SlNetIfWifi_setSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen) +{ + return sl_SetSockOpt(sd, level, optname, optval, optlen); +} + + +//***************************************************************************** +// +// SlNetIfWifi_getSockOpt - Get socket options +// +//***************************************************************************** +int32_t SlNetIfWifi_getSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen) +{ + return sl_GetSockOpt(sd, level, optname, optval, optlen); +} + + +//***************************************************************************** +// +// SlNetIfWifi_recv - Read data from TCP socket +// +//***************************************************************************** +int32_t SlNetIfWifi_recv(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags) +{ + DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); + return sl_Recv(sd, buf, len, flags); +} + + +//***************************************************************************** +// +// SlNetIfWifi_recvFrom - Read data from socket +// +//***************************************************************************** +int32_t SlNetIfWifi_recvFrom(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen) +{ + DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); + return sl_RecvFrom(sd, buf, len, flags, (SlSockAddr_t *)from, fromlen); +} + + +//***************************************************************************** +// +// SlNetIfWifi_send - Write data to TCP socket +// +//***************************************************************************** +int32_t SlNetIfWifi_send(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags) +{ + DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); + return sl_Send(sd, buf, len, flags); +} + + +//***************************************************************************** +// +// SlNetIfWifi_sendTo - Write data to socket +// +//***************************************************************************** +int32_t SlNetIfWifi_sendTo(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen) +{ + DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); + return sl_SendTo(sd, buf, len, flags, (const SlSockAddr_t *)to, tolen); +} + + +//***************************************************************************** +// +// SlNetIfWifi_sockstartSec - Start a security session on an opened socket +// +//***************************************************************************** +int32_t SlNetIfWifi_sockstartSec(int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags) +{ + SlNetSock_SecAttribNode_t *tempSecAttrib = *secAttrib; + int32_t retVal = SLNETERR_RET_CODE_OK; + + if ( 0 != (flags & SLNETSOCK_SEC_BIND_CONTEXT_ONLY) ) + { + /* run over all attributes and set them */ + while (NULL != tempSecAttrib) + { + if ( tempSecAttrib->attribName <= SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE) + { + retVal = sl_SetSockOpt(sd, SL_SOL_SOCKET, StartSecOptName[tempSecAttrib->attribName], tempSecAttrib->attribBuff, tempSecAttrib->attribBuffLen); + } + else + { + return SLNETERR_RET_CODE_INVALID_INPUT; + } + tempSecAttrib = tempSecAttrib->next; + } + } + + if ( 0 != (flags & SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY) ) + { + /* Start TLS session */ + retVal = sl_StartTLS(sd); + } + + return retVal; +} + + +//***************************************************************************** +// +// SlNetIfWifi_getHostByName - Obtain the IP Address of machine on network, by +// machine name +// +//***************************************************************************** +int32_t SlNetIfWifi_getHostByName(void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family) +{ + int32_t retVal = SLNETERR_RET_CODE_OK; + + /* sl_NetAppDnsGetHostByName can receive only one ipAddr variable, so + only the first slot of the array will be used and the ipAddrLen will + be updated to 1 when function is successfully */ + retVal = sl_NetAppDnsGetHostByName((signed char *)name, nameLen, (_u32 *)ipAddr, family); + + if (retVal == SLNETERR_RET_CODE_OK) + { + *ipAddrLen = 1; + } + + return retVal; + + +} + + +//***************************************************************************** +// +// SlNetIfWifi_getIPAddr - Get IP Address of specific interface +// +//***************************************************************************** +int32_t SlNetIfWifi_getIPAddr(void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr) +{ + uint16_t ipAddrLen = sizeof(ipAddr); + return sl_NetCfgGet(addrType, addrConfig, &ipAddrLen, (unsigned char *)ipAddr); +} + + +//***************************************************************************** +// +// SlNetIfWifi_getConnectionStatus - Get interface connection status +// +//***************************************************************************** +int32_t SlNetIfWifi_getConnectionStatus(void *ifContext) +{ + SlWlanConnStatusParam_t connectionParams; + uint16_t Opt = 0; + int32_t retVal = 0; + uint16_t Size = 0; + + memset(&connectionParams, 0, sizeof(SlWlanConnStatusParam_t)); + + retVal = sl_WlanGet(SL_WLAN_CONNECTION_INFO, &Opt, &Size, (uint8_t *)&connectionParams); + + /* Check if the function returned an error */ + if (retVal < SLNETERR_RET_CODE_OK) + { + /* Return error code */ + return retVal; + } + return connectionParams.ConnStatus; +} + + +//***************************************************************************** +// +// SlNetIfWifi_loadSecObj - Load secured buffer to the network stack +// +//***************************************************************************** +int32_t SlNetIfWifi_loadSecObj(void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen) +{ + int32_t retVal; /* negative retVal is an error */ + char *deviceFileName = objName; + int32_t DeviceFileHandle = -1; + uint32_t Offset = 0; + uint32_t MasterToken = 0; + int32_t OpenFlags = 0; + uint8_t macAddress[SL_MAC_ADDR_LEN]; + uint16_t macAddressLen = SL_MAC_ADDR_LEN; + + /* Check if the inputs exists */ + if ( (NULL == objName) || (NULL == objBuff) ) + { + /* input not valid, return error code */ + return SLNETERR_RET_CODE_INVALID_INPUT; + } + + /* Print device Mac address */ + retVal = sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, &macAddress[0]); + + /* The masterToken is the Xor combination between the mac address of + the device and the object file name. */ + MasterToken = (uint32_t)deviceFileName ^ (uint32_t)macAddress; + + /* Create a file and write data. The file is secured, without + signature and with a fail safe commit, with vendor token which is + a Xor combination between the mac address of the device and the + object file name */ + OpenFlags = SL_FS_CREATE; + OpenFlags |= SL_FS_OVERWRITE; + OpenFlags |= SL_FS_CREATE_SECURE; + OpenFlags |= SL_FS_CREATE_VENDOR_TOKEN; + OpenFlags |= SL_FS_CREATE_NOSIGNATURE; + OpenFlags |= SL_FS_CREATE_FAILSAFE; + + /* Create a secure file if not exists and open it for write. */ + DeviceFileHandle = sl_FsOpen((unsigned char *)deviceFileName, OpenFlags | SL_FS_CREATE_MAX_SIZE( objBuffLen ), (unsigned long *)&MasterToken); + + /* Check if file created successfully */ + if ( DeviceFileHandle < SLNETERR_RET_CODE_OK ) + { + return DeviceFileHandle; + } + + Offset = 0; + /* Write the buffer to the new file */ + retVal = sl_FsWrite(DeviceFileHandle, Offset, (unsigned char *)objBuff, objBuffLen); + + /* Close the file */ + retVal = sl_FsClose(DeviceFileHandle, NULL, NULL , 0); + + return retVal; +} + +//***************************************************************************** +// +// SlNetIfWifi_CreateContext - Allocate and store interface data +// +//***************************************************************************** +int32_t SlNetIfWifi_CreateContext(uint16_t ifID, const char *ifName, void **context) +{ + return SLNETERR_RET_CODE_OK; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetifwifi.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetifwifi.h new file mode 100755 index 00000000000..21b365a27f2 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/slnetifwifi.h @@ -0,0 +1,1230 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + +#ifndef __SLNETWIFI_SOCKET_H__ +#define __SLNETWIFI_SOCKET_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup WiFi Socket Stack + \short Controls standard client/server sockets programming options and capabilities + +*/ +/*! + + \addtogroup Socket + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +/* prototype ifConf */ +extern SlNetIf_Config_t SlNetIfConfigWifi; + + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +/*! + + \brief Create an endpoint for communication + + The SlNetIfWifi_socket function creates a new socket of a certain socket + type, identified by an integer number, and allocates system resources to + it.\n + This function is called by the application layer to obtain a socket descriptor (handle). + + \param[in] ifContext Stores interface data if CreateContext function + supported and implemented. + \param[in] domain Specifies the protocol family of the created socket. + For example: + - SLNETSOCK_AF_INET for network protocol IPv4 + - SLNETSOCK_AF_INET6 for network protocol IPv6 + - SLNETSOCK_AF_RF for starting transceiver mode. + Notes: + - sending and receiving any packet overriding 802.11 header + - for optimized power consumption the socket will be started in TX + only mode until receive command is activated + \param[in] type Specifies the socket type, which determines the semantics of communication over + the socket. The socket types supported by the system are implementation-dependent. + Possible socket types include: + - SLNETSOCK_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) + - SLNETSOCK_SOCK_DGRAM (datagram service or Datagram Sockets) + - SLNETSOCK_SOCK_RAW (raw protocols atop the network layer) + - when used with AF_RF: + - SLNETSOCK_SOCK_RX_MTR + - SLNETSOCK_SOCK_MAC_WITH_CCA + - SLNETSOCK_SOCK_MAC_WITH_NO_CCA + - SLNETSOCK_SOCK_BRIDGE + - SLNETSOCK_SOCK_ROUTER + \param[in] protocol Specifies a particular transport to be used with the socket.\n + The most common are + - SLNETSOCK_PROTO_TCP + - SLNETSOCK_PROTO_UDP + - SLNETSOCK_PROTO_RAW + - SLNETSOCK_PROTO_SECURE + The value 0 may be used to select a default + protocol from the selected domain and type + \param[in] sdContext Allocate and store socket data if needed for + using in other slnetwifi socket functions + + \return On success, socket descriptor (handle) that is used for consequent socket operations. \n + A successful return code should be a positive number (int16)\n + On error, a negative value will be returned specifying the error code. + - SLNETERR_BSD_EAFNOSUPPORT - illegal domain parameter + - SLNETERR_BSD_EPROTOTYPE - illegal type parameter + - SLNETERR_BSD_EACCES - permission denied + - SLNETERR_BSD_ENSOCK - exceeded maximal number of socket + - SLNETERR_BSD_ENOMEM - memory allocation error + - SLNETERR_BSD_EINVAL - error in socket configuration + - SLNETERR_BSD_EPROTONOSUPPORT - illegal protocol parameter + - SLNETERR_BSD_EOPNOTSUPP - illegal combination of protocol and type parameters + + \sa SlNetIfWifi_socket + \note + \warning +*/ +int16_t SlNetIfWifi_socket(void *ifContext, int16_t Domain, int16_t Type, int16_t Protocol, void **sdContext); + +/*! + \brief Gracefully close socket + + The SlNetIfWifi_close function causes the system to release resources allocated to a socket. \n + In case of TCP, the connection is terminated. + + \param[in] sd Socket descriptor (handle), received in SlNetIfWifi_socket + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + + \return Zero on success, or negative error code on failure + + \sa SlNetIfWifi_socket + \note + \warning +*/ +int32_t SlNetIfWifi_close(int16_t sd, void *sdContext); + +/*! + \brief Accept a connection on a socket + + The SlNetIfWifi_accept function is used with connection-based socket types (SOCK_STREAM).\n + It extracts the first connection request on the queue of pending + connections, creates a new connected socket, and returns a new file + descriptor referring to that socket.\n + The newly created socket is not in the listening state. The + original socket sd is unaffected by this call. \n + The argument sd is a socket that has been created with + SlNetIfWifi_socket(), bound to a local address with SlNetIfWifi_bind(), and is + listening for connections after a SlNetIfWifi_listen(). \n The argument + \e addr is a pointer to a sockaddr structure. This structure + is filled in with the address of the peer socket, as known to + the communications layer. \n The exact format of the address + returned addr is determined by the socket's address family. \n + The \b \e addrlen argument is a value-result argument: it + should initially contain the size of the structure pointed to + by addr, on return it will contain the actual length (in + bytes) of the address returned. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[out] addr The argument addr is a pointer + to a sockaddr structure. This + structure is filled in with the + address of the peer socket, as + known to the communications + layer. The exact format of the + address returned addr is + determined by the socket's + address\n + sockaddr:\n - code for the + address format.\n - + socket address, the length + depends on the code format + \param[out] addrlen The addrlen argument is a value-result + argument: it should initially contain the + size of the structure pointed to by addr + \param[in] flags Specifies socket descriptor flags. \n + The available flags are: + - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY + - SLNETSOCK_SEC_BIND_CONTEXT_ONLY + Note: This flags can be used in order to start + security session if needed + \param[in] acceptedSdContext Allocate and store data for the new socket + if needed in other to use it in other + slnetwifi socket functions + + \return On success, a socket descriptor.\n + On a non-blocking accept a possible negative value is SLNETERR_BSD_EAGAIN.\n + On failure, negative error code.\n + SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa SlNetIfWifi_Socket SlNetIfWifi_Bind SlNetIfWifi_Listen + \note + \warning +*/ +int16_t SlNetIfWifi_accept(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext); + +/*! + \brief Assign a name to a socket + + This SlNetIfWifi_bind function gives the socket the local address addr. + addr is addrlen bytes long. \n Traditionally, this is called + When a socket is created with socket, it exists in a name + space (address family) but has no name assigned. \n + It is necessary to assign a local address before a SOCK_STREAM + socket may receive connections. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[in] addr Specifies the destination + addrs\n sockaddr:\n - code for + the address format.\n - socket address, + the length depends on the code + format + \param[in] addrlen Contains the size of the structure pointed to by addr + + \return Zero on success, or negative error code on failure + + \sa SlNetIfWifi_Socket SlNetIfWifi_accept SlNetIfWifi_Listen + \note + \warning +*/ +int32_t SlNetIfWifi_bind(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen); + +/*! + \brief Listen for connections on a socket + + The willingness to accept incoming connections and a queue + limit for incoming connections are specified with SlNetIfWifi_listen(), + and then the connections are accepted with SlNetIfWifi_accept(). \n + The SlNetIfWifi_listen() call applies only to sockets of type SOCK_STREAM + The backlog parameter defines the maximum length the queue of + pending connections may grow to. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[in] backlog Specifies the listen queue depth. + + \return Zero on success, or negative error code on failure + + \sa SlNetIfWifi_Socket SlNetIfWifi_accept SlNetIfWifi_bind + \note + \warning +*/ +int32_t SlNetIfWifi_listen(int16_t sd, void *sdContext, int16_t backlog); + +/*! + \brief Initiate a connection on a socket + + Function connects the socket referred to by the socket + descriptor sd, to the address specified by addr. \n The addrlen + argument specifies the size of addr. \n The format of the + address in addr is determined by the address space of the + socket. \n If it is of type SLNETSOCK_SOCK_DGRAM, this call + specifies the peer with which the socket is to be associated; + this address is that to which datagrams are to be sent, and + the only address from which datagrams are to be received. \n If + the socket is of type SLNETSOCK_SOCK_STREAM, this call + attempts to make a connection to another socket. \n The other + socket is specified by address, which is an address in the + communications space of the socket. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[in] addr Specifies the destination addr\n + sockaddr:\n - code for the + address format.\n - + socket address, the length + depends on the code format + \param[in] addrlen Contains the size of the structure pointed + to by addr + \param[in] flags Specifies socket descriptor flags. \n + The available flags are: + - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY + - SLNETSOCK_SEC_BIND_CONTEXT_ONLY + Note: This flags can be used in order to start + security session if needed + + \return On success, a socket descriptor (handle).\n + On a non-blocking connect a possible negative value is NETSCOK_EALREADY. + On failure, negative value.\n + NETSCOK_POOL_IS_EMPTY may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa SlNetIfWifi_socket + \note + \warning +*/ +int32_t SlNetIfWifi_connect(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags); + +/*! + \brief Get local address info by socket descriptor\n + Returns the local address info of the socket descriptor. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[out] addr The argument addr is a pointer + to a SlNetSock_Addr_t structure. This + structure is filled in with the + address of the peer socket, as + known to the communications + layer. The exact format of the + address returned addr is + determined by the socket's + address\n + SlNetSock_Addr_t:\n - code for the + address format.\n - + socket address, the length + depends on the code format + \param[out] addrlen The addrlen argument is a value-result + argument: it should initially contain the + size of the structure pointed to by addr + + \return Zero on success, or negative on failure.\n + + + \sa SlNetSock_create SlNetSock_bind + \note If the provided buffer is too small the returned address will be + truncated and the addrlen will contain the actual size of the + socket address + \warning +*/ +int32_t SlNetIfWifi_getSockName(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); + +/*! + \brief Monitor socket activity + + SlNetIfWifi_send allow a program to monitor multiple file descriptors, + waiting until one or more of the file descriptors become + "ready" for some class of I/O operation. + If trigger mode is enabled the active sdset is the one that retrieved in the first triggered call. + To enable the trigger mode, an handler must be statically registered to the slcb_SocketTriggerEventHandler (user.h) + + \param[in] ifContext Stores interface data if CreateContext function + supported and implemented. + Can be used in all SlNetIf_Config_t functions + \param[in] nsds The highest-numbered file descriptor in any of the + three sets, plus 1. + \param[in,out] readsds Socket descriptors list for read monitoring and accept monitoring + \param[in,out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported + \param[in,out] exceptsds Socket descriptors list for exception monitoring, not supported. + \param[in] timeout Is an upper bound on the amount of time elapsed + before SlNetIfWifi_send() returns. Null or above 0xffff seconds means + infinity timeout. The minimum timeout is 10 milliseconds, + less than 10 milliseconds will be set automatically to 10 milliseconds. + Max microseconds supported is 0xfffc00. + In trigger mode the timeout fields must be set to zero. + + \return On success, SlNetIfWifi_send() returns the number of + file descriptors contained in the three returned + descriptor sets (that is, the total number of bits that + are set in readsds, writesds, exceptsds) which may be + zero if the timeout expires before anything interesting + happens.\n On error, a negative value is returned. + readsds - return the sockets on which Read request will + return without delay with valid data.\n + writesds - return the sockets on which Write request + will return without delay.\n + exceptsds - return the sockets closed recently. \n + SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa SlNetIfWifi_socket + \note If the timeout value set to less than 10ms it will automatically set + to 10ms to prevent overload of the system\n + + Only one SlNetIfWifi_send can be handled at a time. \b + Calling this API while the same command is called from another thread, may result + in one of the following scenarios: + 1. The command will wait (internal) until the previous command finish, and then be executed. + 2. There are not enough resources and SLNETERR_BSD_ENOMEM error will return. + In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try + again later to issue the command. + 3. In case there is already a triggered SlNetIfWifi_send in progress, the following call will return + with SLNETSOCK_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR. + + \warning +*/ +int32_t SlNetIfWifi_select(void *ifContext, int16_t nfds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); + + +/*! + \brief Set socket options- + + The SlNetIfWifi_setSockOpt function manipulate the options associated with a socket.\n + Options may exist at multiple protocol levels; they are always + present at the uppermost socket level.\n + + When manipulating socket options the level at which the option resides + and the name of the option must be specified. To manipulate options at + the socket level, level is specified as SOL_SOCKET. To manipulate + options at any other level the protocol number of the appropriate protocol + controlling the option is supplied. For example, to indicate that an + option is to be interpreted by the TCP protocol, level should be set to + the protocol number of TCP; \n + + The parameters optval and optlen are used to access opt_values + for SlNetIfWifi_setSockOpt(). For SlNetIfWifi_getSockOpt() they identify a + buffer in which the value for the requested option(s) are to + be returned. For SlNetIfWifi_getSockOpt(), optlen is a value-result + parameter, initially containing the size of the buffer + pointed to by option_value, and modified on return to + indicate the actual size of the value returned. If no option + value is to be supplied or returned, option_value may be + NULL. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[in] level Defines the protocol level for this option + - SLNETSOCK_LVL_SOCKET Socket level configurations (L4, transport layer) + - SLNETSOCK_LVL_IP IP level configurations (L3, network layer) + - SLNETSOCK_LVL_PHY Link level configurations (L2, link layer) + \param[in] optname Defines the option name to interrogate + - SLNETSOCK_LVL_SOCKET + - SLNETSOCK_OPSOCK_RCV_BUF \n + Sets tcp max recv window size. \n + This options takes SlNetSock_Winsize_t struct as parameter + - SLNETSOCK_OPSOCK_RCV_TIMEO \n + Sets the timeout value that specifies the maximum amount of time an input function waits until it completes. \n + Default: No timeout \n + This options takes SlNetSock_Timeval_t struct as parameter + - SLNETSOCK_OPSOCK_KEEPALIVE \n + Enable or Disable periodic keep alive. + Keeps TCP connections active by enabling the periodic transmission of messages \n + Timeout is 5 minutes.\n + Default: Enabled \n + This options takes SlNetSock_Keepalive_t struct as parameter + - SLNETSOCK_OPSOCK_KEEPALIVE_TIME \n + Set keep alive timeout. + Value is in seconds \n + Default: 5 minutes \n + - SLNETSOCK_OPSOCK_LINGER \n + Socket lingers on close pending remaining send/receive packets\n + - SLNETSOCK_OPSOCK_NON_BLOCKING \n + Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n + Default: Blocking. + This options takes SlNetSock_Nonblocking_t struct as parameter + - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY \n + Enable or Disable rx ip boundary. + In connectionless socket (udp/raw), unread data is dropped (when SlNetIfWifi_recvfrom len parameter < data size), Enable this option in order to read the left data on the next SlNetIfWifi_recvfrom iteration + Default: Disabled, IP boundary kept, \n + This options takes SlNetSock_NonIpBoundary_t struct as parameter + - SLNETSOCK_LVL_IP + - SLNETSOCK_OPIP_MULTICAST_TTL \n + Set the time-to-live value of outgoing multicast packets for this socket. \n + This options takes uint8_t as parameter + - SLNETSOCK_OPIP_ADD_MEMBERSHIP \n + UDP socket, Join a multicast group. \n + This options takes SlNetSock_IpMreq_t struct as parameter + - SLNETSOCK_OPIP_DROP_MEMBERSHIP \n + UDP socket, Leave a multicast group \n + This options takes SlNetSock_IpMreq_t struct as parameter + - SLNETSOCK_OPIP_HDRINCL \n + RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n + the IP_HDRINCL socket option is enabled on the socket. \n + When it is enabled, the packet must contain an IP header. \n + Default: disabled, IPv4 header generated by Network Stack \n + This options takes uint32_t as parameter + - SLNETSOCK_OPIP_RAW_RX_NO_HEADER \n + Raw socket remove IP header from received data. \n + Default: data includes ip header \n + This options takes uint32_t as parameter + - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (inactive) \n + RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n + the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n + Default: disabled, IPv4 header generated by Network Stack \n + This options takes uint32_t as parameter + - SLNETSOCK_LVL_PHY + - SLNETSOCK_OPPHY_CHANNEL \n + Sets channel in transceiver mode. + This options takes uint32_t as channel number parameter + - SLNETSOCK_OPPHY_RATE \n + RAW socket, set WLAN PHY transmit rate \n + The values are based on SlWlanRateIndex_e \n + This options takes uint32_t as parameter + - SLNETSOCK_OPPHY_TX_POWER \n + RAW socket, set WLAN PHY TX power \n + Valid rage is 1-15 \n + This options takes uint32_t as parameter + - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX \n + RAW socket, set number of frames to transmit in transceiver mode. + Default: 1 packet + This options takes uint32_t as parameter + - SLNETSOCK_OPPHY_PREAMBLE \n + RAW socket, set WLAN PHY preamble for Long/Short\n + This options takes uint32_t as parameter + - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD \n + RAW socket, set WLAN Tx - Set CCA threshold. \n + The values are based on SlNetSockTxInhibitThreshold_e \n + This options takes uint32_t as parameter + - SLNETSOCK_OPPHY_TX_TIMEOUT \n + RAW socket, set WLAN Tx - changes the TX timeout (lifetime) of transceiver frames. \n + Value in Ms, maximum value is 10ms \n + This options takes uint32_t as parameter + - SLNETSOCK_OPPHY_ALLOW_ACKS \n + RAW socket, set WLAN Tx - Enable or Disable sending ACKs in transceiver mode \n + 0 = disabled / 1 = enabled \n + This options takes uint32_t as parameter + + + \param[in] optval Specifies a value for the option + \param[in] optlen Specifies the length of the + option value + + \return Zero on success, or negative error code on failure + + \par Persistent + All params are Non- Persistent + \sa SlNetIfWifi_getSockOpt + \note + \warning + \par Examples + + - SLNETSOCK_OPSOCK_RCV_BUF: + \code + SlNetSock_Winsize_t size; + size.winsize = 3000; // bytes + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_BUF, (uint8_t *)&size, sizeof(size)); + \endcode +
+ + - SLNETSOCK_OPSOCK_RCV_TIMEO: + \code + struct SlNetSock_Timeval_t timeVal; + timeVal.tv_sec = 1; // Seconds + timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_TIMEO, (uint8_t *)&timeVal, sizeof(timeVal)); // Enable receive timeout + \endcode +
+ + - SLNETSOCK_OPSOCK_KEEPALIVE: //disable Keepalive + \code + SlNetSock_Keepalive_t enableOption; + enableOption.keepaliveEnabled = 0; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE, (uint8_t *)&enableOption, sizeof(enableOption)); + \endcode +
+ + - SLNETSOCK_OPSOCK_KEEPALIVE_TIME: //Set Keepalive timeout + \code + int16_t Status; + uint32_t TimeOut = 120; + SlNetIfWifi_setSockOpt(Sd, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE_TIME, (uint8_t *)&TimeOut, sizeof(TimeOut)); + \endcode +
+ + - SLNETSOCK_OPSOCK_NON_BLOCKING: //Enable or disable nonblocking mode + \code + SlNetSock_Nonblocking_t enableOption; + enableOption.nonBlockingEnabled = 1; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_BLOCKING, (uint8_t *)&enableOption, sizeof(enableOption)); + \endcode +
+ + - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY: //disable boundary + \code + SlNetSock_NonIpBoundary_t enableOption; + enableOption.nonIpBoundaryEnabled = 1; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_IP_BOUNDARY, (uint8_t *)&enableOption, sizeof(enableOption)); + \endcode +
+ + - SLNETSOCK_OPSOCK_LINGER: + \code + SlNetSock_linger_t linger; + linger.l_onoff = 1; + linger.l_linger = 10; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_LINGER, &linger, sizeof(linger)); + \endcode +
+ + - SLNETSOCK_OPIP_MULTICAST_TTL: + \code + uint8_t ttl = 20; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_MULTICAST_TTL, &ttl, sizeof(ttl)); + \endcode +
+ + - SLNETSOCK_OPIP_ADD_MEMBERSHIP: + \code + SlNetSock_IpMreq_t mreq; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); + \endcode +
+ + - SLNETSOCK_OPIP_DROP_MEMBERSHIP: + \code + SlNetSock_IpMreq_t mreq; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); + \endcode +
+ + - SLNETSOCK_OPIP_RAW_RX_NO_HEADER: + \code + uint32_t header = 1; // remove ip header + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_RX_NO_HEADER, &header, sizeof(header)); + \endcode +
+ + - SLNETSOCK_OPIP_HDRINCL: + \code + uint32_t header = 1; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_HDRINCL, &header, sizeof(header)); + \endcode +
+ + - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL: + \code + uint32_t header = 1; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_IPV6_HDRINCL, &header, sizeof(header)); + \endcode +
+ + - SLNETSOCK_OPPHY_CHANNEL: + \code + uint32_t newChannel = 6; // range is 1-13 + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPPHY_CHANNEL, &newChannel, sizeof(newChannel)); + \endcode +
+ + - SLNETSOCK_OPPHY_RATE: + \code + uint32_t rate = 6; // see wlan.h SlWlanRateIndex_e for values + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_RATE, &rate, sizeof(rate)); + \endcode +
+ + - SLNETSOCK_OPPHY_TX_POWER: + \code + uint32_t txpower = 1; // valid range is 1-15 + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_POWER, &txpower, sizeof(txpower)); + \endcode +
+ + - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX: + \code + uint32_t numframes = 1; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); + \endcode +
+ + - SLNETSOCK_OPPHY_PREAMBLE: + \code + uint32_t preamble = 1; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_PREAMBLE, &preamble, sizeof(preamble)); + \endcode +
+ + - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD: + \code + uint32_t thrshld = SLNETSOCK_TX_INHIBIT_THRESHOLD_MED; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD , &thrshld, sizeof(thrshld)); + \endcode +
+ + - SLNETSOCK_OPPHY_TX_TIMEOUT: + \code + uint32_t timeout = 50; + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_TIMEOUT , &timeout, sizeof(timeout)); + \endcode +
+ + - SLNETSOCK_OPPHY_ALLOW_ACKS: + \code + uint32_t acks = 1; // 0 = disabled / 1 = enabled + SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_ALLOW_ACKS, &acks, sizeof(acks)); + \endcode +
+ +*/ +int32_t SlNetIfWifi_setSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); + +/*! + \brief Get socket options + + The SlNetIfWifi_getSockOpt function gets the options associated with a socket. + Options may exist at multiple protocol levels; they are always + present at the uppermost socket level.\n + + The parameters optval and optlen identify a + buffer in which the value for the requested option(s) are to + be returned. optlen is a value-result + parameter, initially containing the size of the buffer + pointed to by option_value, and modified on return to + indicate the actual size of the value returned. If no option + value is to be supplied or returned, option_value may be + NULL. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[in] level Defines the protocol level for this option + \param[in] optname defines the option name to interrogate + \param[out] optval Specifies a value for the option + \param[out] optlen Specifies the length of the + option value + + \return Zero on success, or negative error code on failure + \sa SlNetIfWifi_setSockOpt + \note + \warning +*/ +int32_t SlNetIfWifi_getSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); + +/*! + \brief Read data from TCP socket + + The SlNetIfWifi_recv function receives a message from a connection-mode socket + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[out] buf Points to the buffer where the + message should be stored. + \param[in] len Specifies the length in bytes of + the buffer pointed to by the buffer argument. + Range: 1-16000 bytes + \param[in] flags Upper 8 bits specifies the security flags + Lower 24 bits specifies the type of message + reception. On this version, the lower 24 bits are not + supported + + \return Return the number of bytes received, + or a negative value if an error occurred.\n + Using a non-blocking recv a possible negative value is SLNETERR_BSD_EAGAIN.\n + SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa SlNetIfWifi_recvFrom + \note + \warning + \par Examples + + - Receiving data using TCP socket: + \code + SlNetSock_AddrIn_t Addr; + SlNetSock_AddrIn_t LocalAddr; + int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); + int16_t SockID, newSockID; + int16_t Status; + int8_t Buf[RECV_BUF_LEN]; + + LocalAddr.sin_family = SLNETSOCK_AF_INET; + LocalAddr.sin_port = SlNetSock_htons(5001); + LocalAddr.sin_addr.s_addr = 0; + + Addr.sin_family = SLNETSOCK_AF_INET; + Addr.sin_port = SlNetSock_htons(5001); + Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); + + SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); + Status = SlNetIfWifi_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); + Status = SlNetIfWifi_listen(SockID, 0); + newSockID = SlNetIfWifi_accept(SockID, (SlNetSock_Addr_t*)&Addr, (SlNetSocklen_t*) &AddrSize); + Status = SlNetIfWifi_recv(newSockID, Buf, 1460, 0); + \endcode +
+ + - Rx transceiver mode using a raw socket: + \code + int8_t buffer[1536]; + int16_t sd; + uint16_t size; + SlNetSock_TransceiverRxOverHead_t *transHeader; + sd = SlNetIfWifi_socket(SLNETSOCK_AF_RF, SLNETSOCK_SOCK_RAW, 11, 0, 0); // channel 11 + while(1) + { + size = SlNetIfWifi_recv(sd,buffer,1536,0); + transHeader = (SlNetSock_TransceiverRxOverHead_t *)buffer; + printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlNetSock_TransceiverRxOverHead_t)],size); + } + \endcode +*/ +int32_t SlNetIfWifi_recv(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags); + +/*! + \brief Read data from socket + + SlNetIfWifi_recvFrom function receives a message from a connection-mode or + connectionless-mode socket + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[out] buf Points to the buffer where the message should be stored. + \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. + Range: 1-16000 bytes + \param[in] flags Upper 8 bits specifies the security flags + Lower 24 bits specifies the type of message + reception. On this version, the lower 24 bits are not + supported + \param[in] from Pointer to an address structure + indicating the source + address.\n sockaddr:\n - code + for the address format.\n - socket address, + the length depends on the code + format + \param[in] fromlen Source address structure + size. This parameter MUST be set to the size of the structure pointed to by addr. + + + \return Return the number of bytes received, + or a negative value if an error occurred.\n + Using a non-blocking recv a possible negative value is SLNETERR_BSD_EAGAIN. + SLNETSOCK_RET_CODE_INVALID_INPUT (-2) will be returned if fromlen has incorrect length. \n + SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system + In this case try again later or increase MAX_CONCURRENT_ACTIONS + + \sa SlNetIfWifi_recv + \note + \warning + \par Example + + - Receiving data: + \code + SlNetSock_AddrIn_t Addr; + SlNetSock_AddrIn_t LocalAddr; + int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); + int16_t SockID; + int16_t Status; + int8_t Buf[RECV_BUF_LEN]; + + LocalAddr.sin_family = SLNETSOCK_AF_INET; + LocalAddr.sin_port = SlNetSock_htons(5001); + LocalAddr.sin_addr.s_addr = 0; + + SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); + Status = SlNetIfWifi_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); + Status = SlNetIfWifi_recvFrom(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, (SlNetSocklen_t*)&AddrSize); + + \endcode +*/ +int32_t SlNetIfWifi_recvFrom(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); + +/*! + \brief Write data to TCP socket + + The SlNetIfWifi_send function is used to transmit a message to another socket. + Returns immediately after sending data to device. + In case of TCP failure an async event SLNETSOCK_SOCKET_TX_FAILED_EVENT is going to + be received.\n + In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the + frame data buffer for WLAN FCS + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[in] buf Points to a buffer containing + the message to be sent + \param[in] len Message size in bytes. Range: 1-1460 bytes + \param[in] flags Upper 8 bits specifies the security flags + Lower 24 bits specifies the type of message + reception. On this version, the lower 24 bits are not + supported for TCP. + For transceiver mode, the SLNETSOCK_WLAN_RAW_RF_TX_PARAMS macro can be used to determine + transmission parameters (channel,rate,tx_power,preamble) + + \return Zero on success, or negative error code on failure + + \sa SlNetIfWifi_sendTo + \note + \warning + \par Example + + - Sending data: + \code + SlNetSock_AddrIn_t Addr; + int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); + int16_t SockID; + int16_t Status; + int8_t Buf[SEND_BUF_LEN]; + + Addr.sin_family = SLNETSOCK_AF_INET; + Addr.sin_port = SlNetSock_htons(5001); + Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); + + SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); + Status = SlNetIfWifi_connect(SockID, (SlNetSock_Addr_t *)&Addr, AddrSize); + Status = SlNetIfWifi_send(SockID, Buf, 1460, 0 ); + \endcode +*/ +int32_t SlNetIfWifi_send(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags); + +/*! + \brief Write data to socket + + The SlNetIfWifi_sendTo function is used to transmit a message on a connectionless socket + (connection less socket SLNETSOCK_SOCK_DGRAM, SLNETSOCK_SOCK_RAW).\n + Returns immediately after sending data to device.\n + In case of transmission failure an async event SLNETSOCK_SOCKET_TX_FAILED_EVENT is going to + be received. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[in] buf Points to a buffer containing + the message to be sent + \param[in] len message size in bytes. Range: 1-1460 bytes + \param[in] flags Upper 8 bits specifies the security flags + Lower 24 bits specifies the type of message + reception. On this version, the lower 24 bits are not + supported + \param[in] to Pointer to an address structure + indicating the destination + address.\n sockaddr:\n - code + for the address format.\n - socket address, + the length depends on the code + format + \param[in] tolen Destination address structure size + + \return Zero on success, or negative error code on failure + + \sa SlNetIfWifi_send + \note + \warning + \par Example + + - Sending data: + \code + SlNetSock_AddrIn_t Addr; + int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); + int16_t SockID; + int16_t Status; + int8_t Buf[SEND_BUF_LEN]; + + Addr.sin_family = SLNETSOCK_AF_INET; + Addr.sin_port = SlNetSock_htons(5001); + Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); + + SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); + Status = SlNetIfWifi_sendTo(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, AddrSize); + \endcode +*/ +int32_t SlNetIfWifi_sendTo(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); + + +/*! + \brief Start a security session on an opened socket + + The SlNetIfWifi_sockstartSec function is used start a security session on + an opened socket. If the security handle is NULL the session would + be started with the default security settings. + + \param[in] sd Socket descriptor (handle) + \param[in] sdContext May store socket data if implemented in the + SlNetIfWifi_socket function. + \param[in] secAttrib Secure attribute handle + \param[in] flags Specifies flags. \n + The available flags are: + - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY + - SLNETSOCK_SEC_BIND_CONTEXT_ONLY + - SLNETSOCK_SEC_IS_SERVER + + \return Zero on success, or negative error code + on failure + + \sa + \note + \warning + \par Example + + - start security session on an opened socket: + \code + + \endcode +*/ +int32_t SlNetIfWifi_sockstartSec(int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); + + +/*! + \brief Get host IP by name\n + Obtain the IP Address of machine on network, by machine name. + + \param[in] ifContext Stores interface data if CreateContext function + supported and implemented. + Can be used in all SlNetIf_Config_t functions + \param[in] ifBitmap Specifies the interfaces which the host ip + needs to be retrieved from (according to + the priority until one of them will return + an answer).\n + The values of the interface identifiers + is defined with the prefix SLNETIF_ID_ + which defined in slnetif.h + \param[in] name Host name + \param[in] nameLen Name length + \param[out] ipAddr This parameter is filled in with + host IP addresses. In case that host name is not + resolved, out_ip_addr is zero. + \param[in,out] ipAddrLen Holds the size of the ipAddr array, when function + successful, the ipAddrLen parameter will be updated with + the number of the IP addresses found. + \param[in] family Protocol family + + \return Zero on success, or negative on failure.\n + SLNETUTIL_POOL_IS_EMPTY may be return in case + there are no resources in the system\n + In this case try again later or increase + MAX_CONCURRENT_ACTIONS + Possible DNS error codes: + - SLNETUTIL_DNS_QUERY_NO_RESPONSE + - SLNETUTIL_DNS_NO_SERVER + - SLNETUTIL_DNS_QUERY_FAILED + - SLNETUTIL_DNS_MALFORMED_PACKET + - SLNETUTIL_DNS_MISMATCHED_RESPONSE + + \sa + \note Only one sl_NetAppDnsGetHostByName can be handled at a time.\n + Calling this API while the same command is called from another + thread, may result in one of the two scenarios: + 1. The command will wait (internal) until the previous command + finish, and then be executed. + 2. There are not enough resources and POOL_IS_EMPTY error will + return.\n + In this case, MAX_CONCURRENT_ACTIONS can be increased (result + in memory increase) or try again later to issue the command. + \warning + In case an IP address in a string format is set as input, without + any prefix (e.g. "1.2.3.4") the device will not try to access the + DNS and it will return the input address on the 'out_ip_addr' field + \par Example + - Getting host by name: + \code + uint16_t DestIPListSize = 1; + uint32_t DestIP[1]; + uint32_t ifID; + int16_t SockId; + SlNetSock_AddrIn_t LocalAddr; //address of the server to connect to + int32_t LocalAddrSize; + + SlNetIfWifi_getHostByName(0, "www.google.com", strlen("www.google.com"), (uint32_t *)DestIP, &DestIPListSize, SLNETSOCK_PF_INET); + + LocalAddr.sin_family = SLNETSOCK_AF_INET; + LocalAddr.sin_addr.s_addr = SlNetUtil_htonl(DestIP[0]); + LocalAddr.sin_port = SlNetUtil_htons(80); + LocalAddrSize = sizeof(SlNetSock_AddrIn_t); + + SockId = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, ifID, 0); + + if (SockId >= 0) + { + status = SlNetIfWifi_connect(SockId, (SlNetSock_Addr_t *) &LocalAddr, LocalAddrSize); + } + \endcode +*/ +int32_t SlNetIfWifi_getHostByName(void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); + + +/*! + \brief Get IP Address of specific interface + + The SlNetIfWifi_getIPAddr function retrieve the IP address of a specific + interface according to the Address Type, IPv4, IPv6 LOCAL + or IPv6 GLOBAL.\n + + \n + + \param[in] ifContext Stores interface data if CreateContext function + supported and implemented. + Can be used in all SlNetIf_Config_t functions + \param[in] ifID Specifies the interface which its connection + state needs to be retrieved.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + \param[in] addrType Address type: + - SLNETIF_IPV4_ADDR + - SLNETIF_IPV6_ADDR_LOCAL + - SLNETIF_IPV6_ADDR_GLOBAL + \param[out] addrConfig Address config: + - SLNETIF_ADDR_CFG_UNKNOWN + - SLNETIF_ADDR_CFG_DHCP + - SLNETIF_ADDR_CFG_DHCP_LLA + - SLNETIF_ADDR_CFG_STATIC + - SLNETIF_ADDR_CFG_STATELESS + - SLNETIF_ADDR_CFG_STATEFUL + \param[out] ipAddr IP Address according to the Address Type + + \return Zero on success, or negative error code on failure + + \sa SlNetIfAddressType_e + \note + \warning + \par Examples + + \code + SlNetSock_In6Addr_t IPAdd; + uint16_t addressConfig = 0; + SlNetIfWifi_getIPAddr(SLNETIF_ID_1 ,SLNETIF_IPV6_ADDR_LOCAL ,&addressConfig ,(uint8_t *)ipAddr); + \endcode +
+*/ +int32_t SlNetIfWifi_getIPAddr(void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); + + +/*! + \brief Get interface connection status + + The SlNetIfWifi_getConnectionStatus function gets the connection status of the + interface (connected Or disconnected).\n + + \param[in] ifContext Stores interface data if CreateContext function + supported and implemented. + Can be used in all SlNetIf_Config_t functions + + \return Connection status of the interface on success, + or negative error code on failure + + \sa + \note + \warning + \par Examples + + \code + int16_t connection_status + connection_status = SlNetIfWifi_getConnectionStatus(); + \endcode +
+*/ +int32_t SlNetIfWifi_getConnectionStatus(void *ifContext); + + +/*! + \brief Load secured buffer to the network stack + + The SlNetSock_secLoadObj function loads buffer/files into the inputted + network stack for future usage of the socket SSL/TLS connection. + This option is relevant for network stacks with file system and also for + network stacks that lack file system that can store the secured files. + + \param[in] ifContext Stores interface data if CreateContext function + supported and implemented. + Can be used in all SlNetIf_Config_t functions + \param[in] objType Specifies the security object type which + could be one of the following:\n + - SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY + - SLNETIF_SEC_OBJ_TYPE_CERTIFICATE + - SLNETIF_SEC_OBJ_TYPE_DH_KEY + \param[in] objName Specifies the name/input identifier of the + secured buffer loaded + for file systems - this can be the file name + for plain text buffer loading this can be the + name of the object + \param[in] objNameLen Specifies the buffer name length to be loaded.\n + \param[in] objBuff Specifies the pointer to the secured buffer to + be loaded.\n + \param[in] objBuffLen Specifies the buffer length to be loaded.\n + + \return On success, buffer type handler index to be + used when attaching the secured buffer to a + socket.\n + A successful return code should be a positive + number (int16)\n + On error, a negative value will be returned + specifying the error code. + - SLNETERR_STATUS_ERROR - load operation failed + + \sa SlNetIfWifi_setSockOpt + \note + \warning +*/ +int32_t SlNetIfWifi_loadSecObj(void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen); + + +/*! + \brief Allocate and store interface data + + The SlNetIfWifi_CreateContext function stores interface related data.\n + + \param[in] ifContext Allocate and store interface data if needed. + Can be used in all slnetwifi interface functions + + \return Zero on success, or negative error code on failure. + + \sa + \note + \warning + \par Examples + + \code + void *ifContext; + connection_status = SlNetIfWifi_CreateContext(&context); + \endcode +
+*/ +int32_t SlNetIfWifi_CreateContext(uint16_t ifID, const char *ifName, void **ifContext); + + +/*! + + Close the Doxygen group. + @} + + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __SOCKET_H__ */ + + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/device.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/device.c new file mode 100755 index 00000000000..423ab5d0a80 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/device.c @@ -0,0 +1,782 @@ +/* + * device.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include + +/*****************************************************************************/ +/* Internal functions */ +/*****************************************************************************/ + +static _i16 _SlDeviceGetStartResponseConvert(_i32 Status); +void _SlDeviceHandleResetRequestInternally(void); +void _SlDeviceResetRequestInitCompletedCB(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo); + +#ifdef SL_PLATFORM_MULTI_THREADED +extern void wait_us(int usec); +#endif + +#define RESET_REQUEST_STOP_TIMEOUT (300) + +#ifndef SL_IF_OPEN_FLAGS +#define SL_IF_OPEN_FLAGS (0x0) +#endif + +#ifndef SL_IF_UART_REOPEN_FLAGS +#define SL_IF_UART_REOPEN_FLAGS (0x1) +#endif + +typedef struct +{ + const void *pIfHdl; /* Holds the last opened interface handle */ + _i8 *pDevName; /* Holds the last opened interface parameters */ + _u32 ResetRequestSessionNumber; /* Special session number to be verified upon every reset request during provisioning */ +} _SlDeviceCb_t; + +_SlDeviceCb_t DeviceCB; /* the device control block */ + +static const _i16 StartResponseLUT[16] = +{ + ROLE_RESERVED, + ROLE_STA, + SL_ERROR_ROLE_STA_ERR, + ROLE_AP, + SL_ERROR_ROLE_AP_ERR, + ROLE_P2P, + SL_ERROR_ROLE_P2P_ERR, + SL_ERROR_CALIB_FAIL, + SL_ERROR_FS_CORRUPTED_ERR, + SL_ERROR_FS_ALERT_ERR, + SL_ERROR_RESTORE_IMAGE_COMPLETE, + SL_ERROR_INCOMPLETE_PROGRAMMING, + ROLE_RESERVED2, + SL_ERROR_GENERAL_ERR, + SL_ERROR_GENERAL_ERR, + SL_ERROR_GENERAL_ERR +}; + +static _i16 _SlDeviceGetStartResponseConvert(_i32 Status) +{ + return StartResponseLUT[Status & 0xF]; +} + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* sl_Task */ +/*****************************************************************************/ +#if _SL_INCLUDE_FUNC(sl_Task) +void* sl_Task(void* pEntry) +{ +#ifdef _SlTaskEntry + return (void*)_SlTaskEntry(); +#else + return (void*)0; +#endif +} +#endif + +/*****************************************************************************/ +/* sl_Start */ +/*****************************************************************************/ +#if _SL_INCLUDE_FUNC(sl_Start) +_i16 sl_Start(const void* pIfHdl, _i8* pDevName, const P_INIT_CALLBACK pInitCallBack) +{ + _u8 ObjIdx = MAX_CONCURRENT_ACTIONS; + InitComplete_t AsyncRsp; + + _SlDrvMemZero(&AsyncRsp, sizeof(InitComplete_t)); + + /* verify no error handling in progress. if in progress than + ignore the API execution and return immediately with an error */ + VERIFY_NO_ERROR_HANDLING_IN_PROGRESS(); + if (SL_IS_DEVICE_STARTED) + { + return SL_RET_CODE_DEV_ALREADY_STARTED; + } + /* Perform any preprocessing before enable networking services */ +#ifdef sl_DeviceEnablePreamble + sl_DeviceEnablePreamble(); +#endif + + /* ControlBlock init */ + (void)_SlDrvDriverCBInit(); + + /* open the interface: usually SPI or UART */ + if (NULL == pIfHdl) + { + g_pCB->FD = sl_IfOpen((void *)pDevName, SL_IF_OPEN_FLAGS); + } + else + { + g_pCB->FD = (_SlFd_t)pIfHdl; + } + + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8 *)&AsyncRsp, START_STOP_ID, SL_MAX_SOCKETS); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + if( g_pCB->FD >= (_SlFd_t)0) + { + /* store the interface parameters for the internal call of the + sl_start to be called upon reset request handling */ + DeviceCB.pIfHdl = pIfHdl; + DeviceCB.pDevName = pDevName; + + /* Mark that device is in progress! */ + SL_SET_DEVICE_START_IN_PROGRESS; + + sl_DeviceDisable(); + + sl_IfRegIntHdlr((SL_P_EVENT_HANDLER)_SlDrvRxIrqHandler, NULL); + + g_pCB->pInitCallback = pInitCallBack; + sl_DeviceEnable(); + + if (NULL == pInitCallBack) + { +#ifdef SL_TINY + _SlDrvSyncObjWaitForever(&g_pCB->ObjPool[ObjIdx].SyncObj); +#else + + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, INIT_COMPLETE_TIMEOUT, SL_OPCODE_DEVICE_INITCOMPLETE)); +#endif + + SL_UNSET_DEVICE_START_IN_PROGRESS; + + SL_SET_DEVICE_STARTED; + + /* release Pool Object */ + _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex); + return _SlDeviceGetStartResponseConvert(AsyncRsp.Status); + } + else + { + return SL_RET_CODE_OK; + } + } + return SL_BAD_INTERFACE; +} +#endif + +/*************************************************************************** +_SlDeviceHandleAsync_InitComplete - handles init complete signalling to +a waiting object +****************************************************************************/ +_SlReturnVal_t _SlDeviceHandleAsync_InitComplete(void *pVoidBuf) +{ + InitComplete_t *pMsgArgs = (InitComplete_t *)_SL_RESP_ARGS_START(pVoidBuf); + SlDeviceInitInfo_t DeviceInitInfo; + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + if(g_pCB->pInitCallback) + { + DeviceInitInfo.ChipId = pMsgArgs->ChipId; + DeviceInitInfo.MoreData = pMsgArgs->MoreData; + g_pCB->pInitCallback(_SlDeviceGetStartResponseConvert(pMsgArgs->Status), &DeviceInitInfo); + } + else + { + sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(InitComplete_t)); + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + } + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + if(g_pCB->pInitCallback) + { + SL_SET_DEVICE_STARTED; + SL_UNSET_DEVICE_START_IN_PROGRESS; + _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex); + } + + return SL_OS_RET_CODE_OK; + } + + +/*************************************************************************** +_SlDeviceHandleAsync_Stop - handles stop signalling to +a waiting object +****************************************************************************/ +void _SlDeviceHandleAsync_Stop(void *pVoidBuf) +{ + _BasicResponse_t *pMsgArgs = (_BasicResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); + + VERIFY_SOCKET_CB(NULL != g_pCB->StopCB.pAsyncRsp); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + if (g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs != NULL) + { + sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(_BasicResponse_t)); + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + } + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + return; +} + + +/***************************************************************************** +sl_stop +******************************************************************************/ +typedef union +{ + SlDeviceStopCommand_t Cmd; + _BasicResponse_t Rsp; +}_SlStopMsg_u; + +static const _SlCmdCtrl_t _SlStopCmdCtrl = +{ + SL_OPCODE_DEVICE_STOP_COMMAND, + (_SlArgSize_t)sizeof(SlDeviceStopCommand_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +#if _SL_INCLUDE_FUNC(sl_Stop) +_i16 sl_Stop(const _u16 Timeout) +{ + _i16 RetVal=0; + _SlStopMsg_u Msg; + _BasicResponse_t AsyncRsp; + _u8 ObjIdx = MAX_CONCURRENT_ACTIONS; + _u8 ReleasePoolObject = FALSE; + _u8 IsProvInProgress = FALSE; + + /* In case the device has already stopped, + * return an error code . + */ + if (!SL_IS_DEVICE_STARTED) + { + return SL_RET_CODE_DEV_NOT_STARTED; + } + + /* NOTE: don't check VERIFY_API_ALLOWED(), this command is not + * filtered in error handling and also not filtered in NWP lock state. + * If we are in the middle of assert handling than ignore stopping + * the device with timeout and force immediate shutdown as we would like + * to avoid any additional commands to the NWP */ + if( (Timeout != 0) +#ifndef SL_TINY + && (!SL_IS_RESTART_REQUIRED) +#endif + ) + { + /* Clear the Async response structure */ + _SlDrvMemZero(&AsyncRsp, sizeof(_BasicResponse_t)); + + /* let the device make the shutdown using the defined timeout */ + Msg.Cmd.Timeout = Timeout; + + IsProvInProgress = SL_IS_PROVISIONING_IN_PROGRESS; + + /* if provisioning in progress do not take pool object as we are not going to wait for it */ + if (!IsProvInProgress) + { + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8 *)&AsyncRsp, START_STOP_ID, SL_MAX_SOCKETS); + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + ReleasePoolObject = TRUE; + } + + /* Set the stop-in-progress flag */ + SL_SET_DEVICE_STOP_IN_PROGRESS; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlStopCmdCtrl, &Msg, NULL)); + + /* Do not wait for stop async event if provisioning is in progress */ + if((SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) && (!(IsProvInProgress))) + { + +#ifdef SL_TINY + _SlDrvSyncObjWaitForever(&g_pCB->ObjPool[ObjIdx].SyncObj); + /* Wait for sync object to be signaled */ +#else + + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, STOP_DEVICE_TIMEOUT, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE)); +#endif + Msg.Rsp.status = AsyncRsp.status; + RetVal = Msg.Rsp.status; + } + + /* Release pool object only if taken */ + if (ReleasePoolObject == TRUE) + { + _SlDrvReleasePoolObj(ObjIdx); + } + + /* This macro wait for the NWP to raise a ready for shutdown indication. + * This function is unique for the CC32XX family, and expected to return + * in less than 600 mSec, which is the time takes for NWP to gracefully shutdown. */ + WAIT_NWP_SHUTDOWN_READY; + } + else + { + /* Set the stop-in-progress flag */ + SL_SET_DEVICE_STOP_IN_PROGRESS; + } + /* Release (signal) all active and pending commands */ + _SlDrvReleaseAllActivePendingPoolObj(); + +#ifdef SL_PLATFORM_MULTI_THREADED + /* Do not continue until all sync object deleted (in relevant context) */ + while (g_pCB->NumOfDeletedSyncObj < MAX_CONCURRENT_ACTIONS) + { + wait_us(100000); + } +#endif + sl_IfRegIntHdlr(NULL, NULL); + sl_DeviceDisable(); + RetVal = sl_IfClose(g_pCB->FD); + + (void)_SlDrvDriverCBDeinit(); + + /* clear the stop-in-progress flag */ + SL_UNSET_DEVICE_STOP_IN_PROGRESS; + + /* clear the device started flag */ + SL_UNSET_DEVICE_STARTED; + + return RetVal; +} +#endif + + +/***************************************************************************** +sl_DeviceEventMaskSet +*****************************************************************************/ +typedef union +{ + SlDeviceMaskEventSetCommand_t Cmd; + _BasicResponse_t Rsp; +}_SlEventMaskSetMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskSet) + +static const _SlCmdCtrl_t _SlEventMaskSetCmdCtrl = +{ + SL_OPCODE_DEVICE_EVENTMASKSET, + (_SlArgSize_t)sizeof(SlDeviceMaskEventSetCommand_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + + +_i16 sl_DeviceEventMaskSet(const _u8 EventClass ,const _u32 Mask) +{ + _SlEventMaskSetMsg_u Msg; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); + + Msg.Cmd.Group = EventClass; + Msg.Cmd.Mask = Mask; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlEventMaskSetCmdCtrl, &Msg, NULL)); + + return (_i16)Msg.Rsp.status; +} +#endif + +/****************************************************************************** +sl_EventMaskGet +******************************************************************************/ +typedef union +{ + SlDeviceMaskEventGetCommand_t Cmd; + SlDeviceMaskEventGetResponse_t Rsp; +}_SlEventMaskGetMsg_u; + + + +#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskGet) + +static const _SlCmdCtrl_t _SlEventMaskGetCmdCtrl = +{ + SL_OPCODE_DEVICE_EVENTMASKGET, + (_SlArgSize_t)sizeof(SlDeviceMaskEventGetCommand_t), + (_SlArgSize_t)sizeof(SlDeviceMaskEventGetResponse_t) +}; + + +_i16 sl_DeviceEventMaskGet(const _u8 EventClass,_u32 *pMask) +{ + _SlEventMaskGetMsg_u Msg; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); + + Msg.Cmd.Group = EventClass; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlEventMaskGetCmdCtrl, &Msg, NULL)); + + *pMask = Msg.Rsp.Mask; + + return SL_RET_CODE_OK; +} +#endif + + + +/****************************************************************************** +sl_DeviceGet +******************************************************************************/ + +typedef union +{ + SlDeviceSetGet_t Cmd; + SlDeviceSetGet_t Rsp; +}_SlDeviceMsgGet_u; + + + +#if _SL_INCLUDE_FUNC(sl_DeviceGet) + +static const _SlCmdCtrl_t _SlDeviceGetCmdCtrl = +{ + SL_OPCODE_DEVICE_DEVICEGET, + (_SlArgSize_t)sizeof(SlDeviceSetGet_t), + (_SlArgSize_t)sizeof(SlDeviceSetGet_t) +}; + +_i16 sl_DeviceGet(const _u8 DeviceGetId, _u8 *pOption,_u16 *pConfigLen, _u8 *pValues) +{ + _SlDeviceMsgGet_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); + + if (*pConfigLen == 0) + { + return SL_EZEROLEN; + } + + if( pOption ) + { + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)*pConfigLen; + CmdExt.pRxPayload = (_u8 *)pValues; + + Msg.Cmd.DeviceSetId = DeviceGetId; + + Msg.Cmd.Option = (_u16)*pOption; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlDeviceGetCmdCtrl, &Msg, &CmdExt)); + + if( pOption ) + { + *pOption = (_u8)Msg.Rsp.Option; + } + + if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) + { + *pConfigLen = (_u16)CmdExt.RxPayloadLen; + + return SL_ESMALLBUF; + } + else + { + *pConfigLen = (_u16)CmdExt.ActualRxPayloadLen; + } + + return (_i16)Msg.Rsp.Status; + } + else + { + return SL_RET_CODE_INVALID_INPUT; + } +} +#endif + +/****************************************************************************** +sl_DeviceSet +******************************************************************************/ +typedef union +{ + SlDeviceSetGet_t Cmd; + _BasicResponse_t Rsp; +}_SlDeviceMsgSet_u; + + + +#if _SL_INCLUDE_FUNC(sl_DeviceSet) + +static const _SlCmdCtrl_t _SlDeviceSetCmdCtrl = +{ + SL_OPCODE_DEVICE_DEVICESET, + (_SlArgSize_t)sizeof(SlDeviceSetGet_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_i16 sl_DeviceSet(const _u8 DeviceSetId ,const _u8 Option,const _u16 ConfigLen,const _u8 *pValues) +{ + _SlDeviceMsgSet_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); + + _SlDrvResetCmdExt(&CmdExt); + + CmdExt.TxPayload1Len = (ConfigLen+3) & (~3); + CmdExt.pTxPayload1 = (_u8 *)pValues; + + Msg.Cmd.DeviceSetId = DeviceSetId; + Msg.Cmd.ConfigLen = ConfigLen; + Msg.Cmd.Option = Option; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlDeviceSetCmdCtrl, &Msg, &CmdExt)); + + return (_i16)Msg.Rsp.status; +} +#endif + + +/****************************************************************************** +_SlDeviceEventHandler - handles internally device async events +******************************************************************************/ +_SlReturnVal_t _SlDeviceEventHandler(void* pEventInfo) +{ + DeviceEventInfo_t* pInfo = (DeviceEventInfo_t*)pEventInfo; + _SlResponseHeader_t* pHdr = (_SlResponseHeader_t *)pInfo->pAsyncMsgBuff; + _BasicResponse_t *pMsgArgs = (_BasicResponse_t *)_SL_RESP_ARGS_START(pHdr); + SlDeviceEvent_t DeviceEvent; + + _SlDrvMemZero(&DeviceEvent, sizeof(DeviceEvent)); + + switch(pHdr->GenHeader.Opcode) + { + case SL_OPCODE_DEVICE_INITCOMPLETE: + _SlDeviceHandleAsync_InitComplete(pHdr); + break; + case SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE: + _SlDeviceHandleAsync_Stop(pHdr); + break; + case SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT: + { + SlDeviceResetRequestData_t *pResetRequestData = (SlDeviceResetRequestData_t*)pMsgArgs; + +#if defined(slcb_DeviceGeneralEvtHdlr) || defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) + if (pResetRequestData->Caller == SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING_EXTERNAL_CONFIGURATION) + { + /* call the registered events handlers (application/external lib) */ + DeviceEvent.Id = SL_DEVICE_EVENT_RESET_REQUEST; + DeviceEvent.Data.ResetRequest.Status = 0; + DeviceEvent.Data.ResetRequest.Caller = pResetRequestData->Caller; + _SlDrvHandleGeneralEvents(&DeviceEvent); + break; + } +#endif + + if (!_SlDrvIsApiInProgress() && SL_IS_PROVISIONING_IN_PROGRESS) + { + if (pResetRequestData->SessionNumber != DeviceCB.ResetRequestSessionNumber) + { + /* store the last session number */ + DeviceCB.ResetRequestSessionNumber = pResetRequestData->SessionNumber; + + /* perform the reset request */ + _SlDeviceHandleResetRequestInternally(); + } + } + } + break; + + case SL_OPCODE_DEVICE_ABORT: + { + /* release global lock of cmd context */ + if (pInfo->bInCmdContext == TRUE) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + } + +#ifndef SL_TINY + _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_DEVICE_ABORT, + *((_u32*)pMsgArgs - 1), /* Abort type */ + *((_u32*)pMsgArgs)); /* Abort data */ +#endif + } + break; + + case SL_OPCODE_DEVICE_DEVICE_ASYNC_GENERAL_ERROR: + { +#if defined(slcb_DeviceGeneralEvtHdlr) || defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) + + DeviceEvent.Id = SL_DEVICE_EVENT_ERROR; + DeviceEvent.Data.Error.Code = pMsgArgs->status; + DeviceEvent.Data.Error.Source = (SlDeviceSource_e)pMsgArgs->sender; + _SlDrvHandleGeneralEvents(&DeviceEvent); +#endif + } + break; + + case SL_OPCODE_DEVICE_FLOW_CTRL_ASYNC_EVENT: + _SlFlowContSet((void *)pHdr); + break; + default: + SL_ERROR_TRACE2(MSG_306, "ASSERT: _SlDeviceEventHandler : invalid opcode = 0x%x = %1", pHdr->GenHeader.Opcode, pHdr->GenHeader.Opcode); + } + + return SL_OS_RET_CODE_OK; +} + + +void _SlDeviceResetRequestInitCompletedCB(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo) +{ + /* Do nothing...*/ +} + + +void _SlDeviceHandleResetRequestInternally(void) +{ + _u8 irqCountLast = RxIrqCnt; +#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) + _SlTimeoutParams_t TimeoutInfo={0}; + + _SlDrvStartMeasureTimeout(&TimeoutInfo, 2*RESET_REQUEST_STOP_TIMEOUT); +#endif + + /* Here we send stop command with timeout, but the API will not blocked + Till the stop complete event is received as we in the middle of async event handling */ + sl_Stop(RESET_REQUEST_STOP_TIMEOUT); + + /* wait till the stop complete cmd & async + event messages are received (2 Irqs) */ + do + { +#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) + if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) + { + break; + } +#endif + } + while((RxIrqCnt - irqCountLast) < 2); + + /* start the device again */ + sl_Start(DeviceCB.pIfHdl, DeviceCB.pDevName ,_SlDeviceResetRequestInitCompletedCB); + +} + + +/****************************************************************************** +sl_DeviceUartSetMode +******************************************************************************/ +#ifdef SL_IF_TYPE_UART +typedef union +{ + SlDeviceUartSetModeCommand_t Cmd; + SlDeviceUartSetModeResponse_t Rsp; +}_SlUartSetModeMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_DeviceUartSetMode) + + +const _SlCmdCtrl_t _SlUartSetModeCmdCtrl = +{ + SL_OPCODE_DEVICE_SETUARTMODECOMMAND, + (_SlArgSize_t)sizeof(SlDeviceUartSetModeCommand_t), + (_SlArgSize_t)sizeof(SlDeviceUartSetModeResponse_t) +}; + +_i16 sl_DeviceUartSetMode(const SlDeviceUartIfParams_t *pUartParams) +{ + _SlUartSetModeMsg_u Msg; + _u32 magicCode = (_u32)0xFFFFFFFF; + + Msg.Cmd.BaudRate = pUartParams->BaudRate; + Msg.Cmd.FlowControlEnable = pUartParams->FlowControlEnable; + + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlUartSetModeCmdCtrl, &Msg, NULL)); + + /* cmd response OK, we can continue with the handshake */ + if (SL_RET_CODE_OK == Msg.Rsp.status) + { + sl_IfMaskIntHdlr(); + + /* Close the comm port */ + sl_IfClose(g_pCB->FD); + + /* Re-open the comm port */ + sl_IfOpen((void * )pUartParams, SL_IF_UART_REOPEN_FLAGS); + + sl_IfUnMaskIntHdlr(); + + /* send the magic code and wait for the response */ + sl_IfWrite(g_pCB->FD, (_u8* )&magicCode, 4); + + magicCode = UART_SET_MODE_MAGIC_CODE; + sl_IfWrite(g_pCB->FD, (_u8* )&magicCode, 4); + + /* clear magic code */ + magicCode = 0; + + /* wait (blocking) till the magic code to be returned from device */ + sl_IfRead(g_pCB->FD, (_u8* )&magicCode, 4); + + /* check for the received magic code matching */ + if (UART_SET_MODE_MAGIC_CODE != magicCode) + { + _SL_ASSERT(0); + } + } + + return (_i16)Msg.Rsp.status; +} +#endif +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.c new file mode 100755 index 00000000000..0c0313720a0 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.c @@ -0,0 +1,3269 @@ +/* + * driver.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +#ifndef SL_PLATFORM_MULTI_THREADED + +#define GLOBAL_LOCK_CONTEXT_OWNER_APP (1) +#define GLOBAL_LOCK_CONTEXT_OWNER_SPAWN (2) + +_u8 gGlobalLockContextOwner = GLOBAL_LOCK_CONTEXT_OWNER_APP; + +#endif + +_u8 gGlobalLockCntRequested=0; +_u8 gGlobalLockCntReleased=0; + +#if defined(SL_PLATFORM_MULTI_THREADED) +extern void * pthread_self(void); +#endif +/* static functions declaration */ +static void _SlDrvUpdateApiInProgress(_i8 Value); + +#define API_IN_PROGRESS_UPDATE_NONE (0) +#define API_IN_PROGRESS_UPDATE_INCREMENT (1) +#define API_IN_PROGRESS_UPDATE_DECREMENT (-1) + +#define GLOBAL_LOCK_FLAGS_NONE (0x0) +#define GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS (0x1) /* Bit 0 */ +#define GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API (0x2) /* Bit 1*/ +#define GLOBAL_LOCK_FLAGS_STARTING_DEVICE (0x4) /* Bit 2 */ + + +/* 2 LSB of the N2H_SYNC_PATTERN are for sequence number +only in SPI interface +support backward sync pattern */ +#define N2H_SYNC_PATTERN_SEQ_NUM_BITS ((_u32)0x00000003) /* Bits 0..1 - use the 2 LBS for seq num */ +#define N2H_SYNC_PATTERN_SEQ_NUM_EXISTS ((_u32)0x00000004) /* Bit 2 - sign that sequence number exists in the sync pattern */ +#define N2H_SYNC_PATTERN_MASK ((_u32)0xFFFFFFF8) /* Bits 3..31 - constant SYNC PATTERN */ +#define N2H_SYNC_SPI_BUGS_MASK ((_u32)0x7FFF7F7F) /* Bits 7,15,31 - ignore the SPI (8,16,32 bites bus) error bits */ +#define BUF_SYNC_SPIM(pBuf) ((*(_u32 *)(pBuf)) & N2H_SYNC_SPI_BUGS_MASK) + +#define N2H_SYNC_SPIM (N2H_SYNC_PATTERN & N2H_SYNC_SPI_BUGS_MASK) +#define N2H_SYNC_SPIM_WITH_SEQ(TxSeqNum) ((N2H_SYNC_SPIM & N2H_SYNC_PATTERN_MASK) | N2H_SYNC_PATTERN_SEQ_NUM_EXISTS | ((TxSeqNum) & (N2H_SYNC_PATTERN_SEQ_NUM_BITS))) +#define MATCH_WOUT_SEQ_NUM(pBuf) ( BUF_SYNC_SPIM(pBuf) == N2H_SYNC_SPIM ) +#define MATCH_WITH_SEQ_NUM(pBuf, TxSeqNum) ( BUF_SYNC_SPIM(pBuf) == (N2H_SYNC_SPIM_WITH_SEQ(TxSeqNum)) ) +#define N2H_SYNC_PATTERN_MATCH(pBuf, TxSeqNum) \ + ( \ + ( (*((_u32 *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && ( MATCH_WITH_SEQ_NUM(pBuf, TxSeqNum) ) ) || \ + ( !(*((_u32 *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && ( MATCH_WOUT_SEQ_NUM(pBuf ) ) ) \ + ) + +#define OPCODE(_ptr) (((_SlResponseHeader_t *)(_ptr))->GenHeader.Opcode) +#define RSP_PAYLOAD_LEN(_ptr) (((_SlResponseHeader_t *)(_ptr))->GenHeader.Len - _SL_RESP_SPEC_HDR_SIZE) +#define SD(_ptr) (((SlSocketAddrResponse_u *)(_ptr))->IpV4.Sd) +/* Actual size of Recv/Recvfrom response data */ +#define ACT_DATA_SIZE(_ptr) (((SlSocketAddrResponse_u *)(_ptr))->IpV4.StatusOrLen) + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) +#define MULTI_SELECT_MASK (~(1 << SELECT_ID)) +#else +#define MULTI_SELECT_MASK (0xFFFFFFFF) +#endif +/* Internal function prototype declaration */ + + +/* General Events handling*/ +#if defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) + +typedef _SlEventPropogationStatus_e (*general_callback) (SlDeviceEvent_t *); + +static const general_callback general_callbacks[] = +{ +#ifdef SlExtLib1GeneralEventHandler + SlExtLib1GeneralEventHandler, +#endif + +#ifdef SlExtLib2GeneralEventHandler + SlExtLib2GeneralEventHandler, +#endif + +#ifdef SlExtLib3GeneralEventHandler + SlExtLib3GeneralEventHandler, +#endif + +#ifdef SlExtLib4GeneralEventHandler + SlExtLib4GeneralEventHandler, +#endif + +#ifdef SlExtLib5GeneralEventHandler + SlExtLib5GeneralEventHandler, +#endif +}; + +#undef _SlDrvHandleGeneralEvents + +/******************************************************************** + _SlDrvHandleGeneralEvents + Iterates through all the general(device) event handlers which are + registered by the external libs/user application. +*********************************************************************/ +void _SlDrvHandleGeneralEvents(SlDeviceEvent_t *slGeneralEvent) +{ + _u8 i; + + /* Iterate over all the extenal libs handlers */ + for ( i = 0 ; i < sizeof(general_callbacks)/sizeof(general_callbacks[0]) ; i++ ) + { + if (EVENT_PROPAGATION_BLOCK == general_callbacks[i](slGeneralEvent) ) + { + /* exit immediately and do not call the user specific handler as well */ + return; + } + } + +/* At last call the Application specific handler if registered */ +#ifdef slcb_DeviceGeneralEvtHdlr + slcb_DeviceGeneralEvtHdlr(slGeneralEvent); +#endif + +} +#endif + + +/* WLAN Events handling*/ + +#if defined (EXT_LIB_REGISTERED_WLAN_EVENTS) + +typedef _SlEventPropogationStatus_e (*wlan_callback) (SlWlanEvent_t *); + +static wlan_callback wlan_callbacks[] = +{ +#ifdef SlExtLib1WlanEventHandler + SlExtLib1WlanEventHandler, +#endif + +#ifdef SlExtLib2WlanEventHandler + SlExtLib2WlanEventHandler, +#endif + +#ifdef SlExtLib3WlanEventHandler + SlExtLib3WlanEventHandler, +#endif + +#ifdef SlExtLib4WlanEventHandler + SlExtLib4WlanEventHandler, +#endif + +#ifdef SlExtLib5WlanEventHandler + SlExtLib5WlanEventHandler, +#endif +}; + +#undef _SlDrvHandleWlanEvents + +/*********************************************************** + _SlDrvHandleWlanEvents + Iterates through all the wlan event handlers which are + registered by the external libs/user application. +************************************************************/ +void _SlDrvHandleWlanEvents(SlWlanEvent_t *slWlanEvent) +{ + _u8 i; + + /* Iterate over all the extenal libs handlers */ + for ( i = 0 ; i < sizeof(wlan_callbacks)/sizeof(wlan_callbacks[0]) ; i++ ) + { + if ( EVENT_PROPAGATION_BLOCK == wlan_callbacks[i](slWlanEvent) ) + { + /* exit immediately and do not call the user specific handler as well */ + return; + } + } + +/* At last call the Application specific handler if registered */ +#ifdef slcb_WlanEvtHdlr + slcb_WlanEvtHdlr(slWlanEvent); +#endif + +} +#endif + + +/* NetApp Events handling */ +#if defined (EXT_LIB_REGISTERED_NETAPP_EVENTS) + +typedef _SlEventPropogationStatus_e (*netApp_callback) (SlNetAppEvent_t *); + +static const netApp_callback netApp_callbacks[] = +{ +#ifdef SlExtLib1NetAppEventHandler + SlExtLib1NetAppEventHandler, +#endif + +#ifdef SlExtLib2NetAppEventHandler + SlExtLib2NetAppEventHandler, +#endif + +#ifdef SlExtLib3NetAppEventHandler + SlExtLib3NetAppEventHandler, +#endif + +#ifdef SlExtLib4NetAppEventHandler + SlExtLib4NetAppEventHandler, +#endif + +#ifdef SlExtLib5NetAppEventHandler + SlExtLib5NetAppEventHandler, +#endif +}; + +#undef _SlDrvHandleNetAppEvents + +/************************************************************ + _SlDrvHandleNetAppEvents + Iterates through all the net app event handlers which are + registered by the external libs/user application. +************************************************************/ +void _SlDrvHandleNetAppEvents(SlNetAppEvent_t *slNetAppEvent) +{ + _u8 i; + + /* Iterate over all the extenal libs handlers */ + for ( i = 0 ; i < sizeof(netApp_callbacks)/sizeof(netApp_callbacks[0]) ; i++ ) + { + if (EVENT_PROPAGATION_BLOCK == netApp_callbacks[i](slNetAppEvent) ) + { + /* exit immediately and do not call the user specific handler as well */ + return; + } + } + +/* At last call the Application specific handler if registered */ +#ifdef slcb_NetAppEvtHdlr + slcb_NetAppEvtHdlr(slNetAppEvent); +#endif + +} +#endif + + +/* Http Server Events handling */ +#if defined (EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) + +typedef _SlEventPropogationStatus_e (*httpServer_callback) (SlNetAppHttpServerEvent_t*, SlNetAppHttpServerResponse_t*); + +static const httpServer_callback httpServer_callbacks[] = +{ +#ifdef SlExtLib1HttpServerEventHandler + SlExtLib1HttpServerEventHandler, +#endif + +#ifdef SlExtLib2HttpServerEventHandler + SlExtLib2HttpServerEventHandler, +#endif + +#ifdef SlExtLib3HttpServerEventHandler + SlExtLib3HttpServerEventHandler, +#endif + +#ifdef SlExtLib4HttpServerEventHandler + SlExtLib4HttpServerEventHandler, +#endif + +#ifdef SlExtLib5HttpServerEventHandler + SlExtLib5HttpServerEventHandler, +#endif +}; + +#undef _SlDrvHandleHttpServerEvents + +/******************************************************************* + _SlDrvHandleHttpServerEvents + Iterates through all the http server event handlers which are + registered by the external libs/user application. +********************************************************************/ +void _SlDrvHandleHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse) +{ + _u8 i; + + /* Iterate over all the external libs handlers */ + for ( i = 0 ; i < sizeof(httpServer_callbacks)/sizeof(httpServer_callbacks[0]) ; i++ ) + { + if ( EVENT_PROPAGATION_BLOCK == httpServer_callbacks[i](slHttpServerEvent, slHttpServerResponse) ) + { + /* exit immediately and do not call the user specific handler as well */ + return; + } + } + +/* At last call the Application specific handler if registered */ +#ifdef slcb_NetAppHttpServerHdlr + slcb_NetAppHttpServerHdlr(slHttpServerEvent, slHttpServerResponse); +#endif + +} +#endif + + +/* Socket Events */ +#if defined (EXT_LIB_REGISTERED_SOCK_EVENTS) + +typedef _SlEventPropogationStatus_e (*sock_callback) (SlSockEvent_t *); + +static const sock_callback sock_callbacks[] = +{ +#ifdef SlExtLib1SockEventHandler + SlExtLib1SockEventHandler, +#endif + +#ifdef SlExtLib2SockEventHandler + SlExtLib2SockEventHandler, +#endif + +#ifdef SlExtLib3SockEventHandler + SlExtLib3SockEventHandler, +#endif + +#ifdef SlExtLib4SockEventHandler + SlExtLib4SockEventHandler, +#endif + +#ifdef SlExtLib5SockEventHandler + SlExtLib5SockEventHandler, +#endif +}; + +/************************************************************* + _SlDrvHandleSockEvents + Iterates through all the socket event handlers which are + registered by the external libs/user application. +**************************************************************/ +void _SlDrvHandleSockEvents(SlSockEvent_t *slSockEvent) +{ + _u8 i; + + /* Iterate over all the external libs handlers */ + for ( i = 0 ; i < sizeof(sock_callbacks)/sizeof(sock_callbacks[0]) ; i++ ) + { + if ( EVENT_PROPAGATION_BLOCK == sock_callbacks[i](slSockEvent) ) + { + /* exit immediately and do not call the user specific handler as well */ + return; + } + } + +/* At last call the Application specific handler if registered */ +#ifdef slcb_SockEvtHdlr + slcb_SockEvtHdlr(slSockEvent); +#endif + +} + +#endif + +/* Fatal Error Events handling*/ +#if defined (EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) + +typedef _SlEventPropogationStatus_e (*fatal_error_callback) (SlDeviceEvent_t *); + +static const fatal_error_callback fatal_error_callbacks[] = +{ +#ifdef SlExtLib1FatalErrorEventHandler + SlExtLib1FatalErrorEventHandler, +#endif + +#ifdef SlExtLib2FatalErrorEventHandler + SlExtLib2FatalErrorEventHandler, +#endif + +#ifdef SlExtLib3FatalErrorEventHandler + SlExtLib3FatalErrorEventHandler, +#endif + +#ifdef SlExtLib4FatalErrorEventHandler + SlExtLib4FatalErrorEventHandler, +#endif + +#ifdef SlExtLib5FatalErrorEventHandler + SlExtLib5FatalErrorEventHandler, +#endif +}; + +#undef _SlDrvHandleFatalErrorEvents + +/******************************************************************** + _SlDrvHandleFatalErrorEvents + Iterates through all the fatal error (device) event handlers which are + registered by the external libs/user application. +*********************************************************************/ +void _SlDrvHandleFatalErrorEvents(SlDeviceFatal_t *slFatalErrorEvent) +{ + _u8 i; + + /* Iterate over all the extenal libs handlers */ + for ( i = 0 ; i < sizeof(fatal_error_callbacks)/sizeof(fatal_error_callbacks[0]) ; i++ ) + { + if (EVENT_PROPAGATION_BLOCK == fatal_error_callbacks[i](slFatalErrorEvent) ) + { + /* exit immediately and do not call the user specific handler as well */ + return; + } + } + +/* At last call the Application specific handler if registered */ +#ifdef slcb_DeviceFatalErrorEvtHdlr + slcb_DeviceFatalErrorEvtHdlr(slFatalErrorEvent); +#endif + +} +#endif + +/* NetApp request handler */ +#if defined (EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) + +typedef _SlEventPropogationStatus_e (*netapp_request_callback) (SlNetAppRequest_t*, SlNetAppResponse_t*); + +static const netapp_request_callback netapp_request_callbacks[] = +{ +#ifdef SlExtLib1NetAppRequestEventHandler + SlExtLib1NetAppRequestEventHandler, +#endif + +#ifdef SlExtLib2NetAppRequestEventHandler + SlExtLib2NetAppRequestEventHandler, +#endif + +#ifdef SlExtLib3NetAppRequestEventHandler + SlExtLib3NetAppRequestEventHandler, +#endif + +#ifdef SlExtLib4NetAppRequestEventHandler + SlExtLib4NetAppRequestEventHandler, +#endif + +#ifdef SlExtLib5NetAppRequestEventHandler + SlExtLib5NetAppRequestEventHandler, +#endif +}; + +#undef _SlDrvHandleNetAppRequestEvents + +/******************************************************************** + _SlDrvHandleNetAppRequest + Iterates through all the netapp request handlers which are + registered by the external libs/user application. +*********************************************************************/ +void _SlDrvHandleNetAppRequestEvents(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse) +{ + _u8 i; + + /* Iterate over all the extenal libs handlers */ + for ( i = 0 ; i < sizeof(netapp_request_callbacks)/sizeof(netapp_request_callbacks[0]) ; i++ ) + { + if (EVENT_PROPAGATION_BLOCK == netapp_request_callbacks[i](pNetAppRequest, pNetAppResponse) ) + { + /* exit immediately and do not call the user specific handler as well */ + return; + } + } + +/* At last call the Application specific handler if registered */ +#ifdef slcb_NetAppRequestHdlr + slcb_NetAppRequestHdlr(pNetAppRequest, pNetAppResponse); +#endif + +} +#endif + + +#ifndef SL_MEMORY_MGMT_DYNAMIC +typedef struct +{ + _u32 Align; +#ifdef SL_PLATFORM_MULTI_THREADED + _SlAsyncRespBuf_t AsyncBufPool[SL_MAX_ASYNC_BUFFERS]; +#endif + _u8 AsyncRespBuf[SL_ASYNC_MAX_MSG_LEN]; +}_SlStatMem_t; + +static _SlStatMem_t g_StatMem; +#endif + + +/*****************************************************************************/ +/* Variables */ +/*****************************************************************************/ +_SlDriverCb_t g_CB; +static const _SlSyncPattern_t g_H2NSyncPattern = H2N_SYNC_PATTERN; + +#ifndef SL_IF_TYPE_UART +static const _SlSyncPattern_t g_H2NCnysPattern = H2N_CNYS_PATTERN; +#endif +_volatile _u8 RxIrqCnt; + +_u16 g_SlDeviceStatus = 0; +_SlLockObj_t GlobalLockObj; +_u8 g_IsGlobalLockObjInit = 0; + + +#ifndef SL_TINY + + +const _SlActionLookup_t _SlActionLookupTable[] = +{ + {ACCEPT_ID, SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE, (_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Accept}, + {CONNECT_ID, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Connect}, + {SELECT_ID, SL_OPCODE_SOCKET_SELECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Select}, + {GETHOSYBYNAME_ID, SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_DnsGetHostByName}, + {GETHOSYBYSERVICE_ID, SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_DnsGetHostByService}, + {PING_ID, SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE, (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_PingResponse}, + {NETAPP_RECEIVE_ID, SL_OPCODE_NETAPP_RECEIVE, (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_NetAppReceive}, + {START_STOP_ID, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE,(_SlSpawnEntryFunc_t)_SlDeviceHandleAsync_Stop}, + {NETUTIL_CMD_ID, SL_OPCODE_NETUTIL_COMMANDASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetUtilHandleAsync_Cmd}, + {CLOSE_ID, SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Close}, + {START_TLS_ID, SL_OPCODE_SOCKET_SOCKETASYNCEVENT,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_StartTLS} +}; +#else +const _SlActionLookup_t _SlActionLookupTable[] = +{ + {CONNECT_ID, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Connect}, + {GETHOSYBYNAME_ID, SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_DnsGetHostByName}, + {START_STOP_ID, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE,(_SlSpawnEntryFunc_t)_SlDeviceHandleAsync_Stop}, + {CLOSE_ID, SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Close} +}; +#endif + + + +typedef struct +{ + _u16 opcode; + _u8 event; +} OpcodeKeyVal_t; + + +/* The table translates opcode to user's event type */ +const OpcodeKeyVal_t OpcodeTranslateTable[] = +{ + {SL_OPCODE_WLAN_STA_ASYNCCONNECTEDRESPONSE, SL_WLAN_EVENT_CONNECT}, + {SL_OPCODE_WLAN_P2PCL_ASYNCCONNECTEDRESPONSE, SL_WLAN_EVENT_P2P_CONNECT}, + {SL_OPCODE_WLAN_STA_ASYNCDISCONNECTEDRESPONSE, SL_WLAN_EVENT_DISCONNECT}, + {SL_OPCODE_WLAN_P2PCL_ASYNCDISCONNECTEDRESPONSE,SL_WLAN_EVENT_P2P_DISCONNECT}, + {SL_OPCODE_WLAN_ASYNC_STA_ADDED, SL_WLAN_EVENT_STA_ADDED}, + {SL_OPCODE_WLAN_ASYNC_P2PCL_ADDED,SL_WLAN_EVENT_P2P_CLIENT_ADDED}, + {SL_OPCODE_WLAN_ASYNC_STA_REMOVED, SL_WLAN_EVENT_STA_REMOVED}, + {SL_OPCODE_WLAN_ASYNC_P2PCL_REMOVED,SL_WLAN_EVENT_P2P_CLIENT_REMOVED}, + {SL_OPCODE_WLAN_P2P_DEV_FOUND,SL_WLAN_EVENT_P2P_DEVFOUND}, + {SL_OPCODE_WLAN_P2P_NEG_REQ_RECEIVED, SL_WLAN_EVENT_P2P_REQUEST}, + {SL_OPCODE_WLAN_P2P_CONNECTION_FAILED, SL_WLAN_EVENT_P2P_CONNECTFAIL}, + {SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT, SL_WLAN_EVENT_PROVISIONING_STATUS}, + {SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE, SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED}, + {SL_OPCODE_WLAN_RX_FILTER_ASYNC_RESPONSE,SL_WLAN_EVENT_RXFILTER}, + {SL_OPCODE_WLAN_RESERVED_RESPONSE, SL_WLAN_EVENT_RESERVED}, + + {SL_OPCODE_NETAPP_IPACQUIRED, SL_NETAPP_EVENT_IPV4_ACQUIRED}, + {SL_OPCODE_NETAPP_IPACQUIRED_V6, SL_NETAPP_EVENT_IPV6_ACQUIRED}, + {SL_OPCODE_NETAPP_IP_LEASED, SL_NETAPP_EVENT_DHCPV4_LEASED}, + {SL_OPCODE_NETAPP_IP_RELEASED, SL_NETAPP_EVENT_DHCPV4_RELEASED}, + {SL_OPCODE_NETAPP_IP_COLLISION, SL_NETAPP_EVENT_IP_COLLISION}, + {SL_OPCODE_NETAPP_IPV4_LOST, SL_NETAPP_EVENT_IPV4_LOST}, + {SL_OPCODE_NETAPP_DHCP_IPV4_ACQUIRE_TIMEOUT, SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT}, + {SL_OPCODE_NETAPP_IPV6_LOST_V6, SL_NETAPP_EVENT_IPV6_LOST}, + {SL_OPCODE_NETAPP_RESERVED1, SL_NETAPP_EVENT_RESERVED1}, + {SL_OPCODE_NETAPP_RESERVED2, SL_NETAPP_EVENT_RESERVED2}, + {SL_OPCODE_NETAPP_RESERVED3, SL_NETAPP_EVENT_RESERVED3}, + {SL_OPCODE_SOCKET_TXFAILEDASYNCRESPONSE, SL_SOCKET_TX_FAILED_EVENT}, + {SL_OPCODE_SOCKET_SOCKETASYNCEVENT, SL_SOCKET_ASYNC_EVENT} + +}; + + + +_SlDriverCb_t* g_pCB = NULL; +P_SL_DEV_PING_CALLBACK pPingCallBackFunc = NULL; + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ +static _SlReturnVal_t _SlDrvMsgRead(_u16* outMsgReadLen, _u8** pAsyncBuf); +static _SlReturnVal_t _SlDrvMsgWrite(_SlCmdCtrl_t *pCmdCtrl,_SlCmdExt_t *pCmdExt, _u8 *pTxRxDescBuff); +static _SlReturnVal_t _SlDrvMsgReadCmdCtx(_u16 cmdOpcode, _u8 IsLockRequired); +static _SlReturnVal_t _SlDrvClassifyRxMsg(_SlOpcode_t Opcode ); +static _SlReturnVal_t _SlDrvRxHdrRead(_u8 *pBuf); +static void _SlDrvAsyncEventGenericHandler(_u8 bInCmdContext, _u8 *pAsyncBuffer); +static void _SlDrvRemoveFromList(_u8* ListIndex, _u8 ItemIndex); +static _SlReturnVal_t _SlDrvFindAndSetActiveObj(_SlOpcode_t Opcode, _u8 Sd); +static _SlReturnVal_t _SlDrvObjGlobalLockWaitForever(_u32 Flags); + +/*****************************************************************************/ +/* Internal functions */ +/*****************************************************************************/ + + +/***************************************************************************** +_SlDrvDriverCBInit - init Driver Control Block +*****************************************************************************/ + +_SlReturnVal_t _SlDrvDriverCBInit(void) +{ + _u8 Idx =0; + + g_pCB = &g_CB; + +#ifndef SL_PLATFORM_MULTI_THREADED + { + extern _SlNonOsCB_t g__SlNonOsCB; + sl_Memset(&g__SlNonOsCB, 0, sizeof(g__SlNonOsCB)); + } +#endif + + _SlDrvMemZero(g_pCB, (_u16)sizeof(_SlDriverCb_t)); + RxIrqCnt = 0; + OSI_RET_OK_CHECK( sl_SyncObjCreate(&g_pCB->CmdSyncObj, "CmdSyncObj") ); + SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->CmdSyncObj); + + if (g_IsGlobalLockObjInit == 0) + { + OSI_RET_OK_CHECK( sl_LockObjCreate(&GlobalLockObj, "GlobalLockObj") ); + g_IsGlobalLockObjInit = 1; + } + + OSI_RET_OK_CHECK( sl_LockObjCreate(&g_pCB->ProtectionLockObj, "ProtectionLockObj") ); + g_pCB->NumOfDeletedSyncObj = 0; +#if defined(slcb_SocketTriggerEventHandler) + g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = MAX_CONCURRENT_ACTIONS; +#endif + /* Init Drv object */ + _SlDrvMemZero(&g_pCB->ObjPool[0], (_u16)(MAX_CONCURRENT_ACTIONS*sizeof(_SlPoolObj_t))); + /* place all Obj in the free list*/ + g_pCB->FreePoolIdx = 0; + + for (Idx = 0 ; Idx < MAX_CONCURRENT_ACTIONS ; Idx++) + { + g_pCB->ObjPool[Idx].NextIndex = Idx + 1; + g_pCB->ObjPool[Idx].AdditionalData = SL_MAX_SOCKETS; + + OSI_RET_OK_CHECK( sl_SyncObjCreate(&g_pCB->ObjPool[Idx].SyncObj, "SyncObj")); + SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->ObjPool[Idx].SyncObj); + } + + g_pCB->ActivePoolIdx = MAX_CONCURRENT_ACTIONS; + g_pCB->PendingPoolIdx = MAX_CONCURRENT_ACTIONS; + +#ifdef SL_PLATFORM_MULTI_THREADED + +#ifdef SL_MEMORY_MGMT_DYNAMIC + /* reset the spawn messages list */ + g_pCB->spawnMsgList = NULL; +#else + for (Idx = 0; Idx < SL_MAX_ASYNC_BUFFERS; Idx++) + { + g_StatMem.AsyncBufPool[Idx].ActionIndex = 0xFF; + g_StatMem.AsyncBufPool[Idx].AsyncHndlr = NULL; + } +#endif +#else + /* clear the global lock owner */ + _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); +#endif + /* Flow control init */ + g_pCB->FlowContCB.TxPoolCnt = FLOW_CONT_MIN; + OSI_RET_OK_CHECK(sl_LockObjCreate(&g_pCB->FlowContCB.TxLockObj, "TxLockObj")); + OSI_RET_OK_CHECK(sl_SyncObjCreate(&g_pCB->FlowContCB.TxSyncObj, "TxSyncObj")); + g_pCB->FlowContCB.MinTxPayloadSize = 1536; /* init maximum length */ + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + OSI_RET_OK_CHECK(sl_LockObjCreate(&g_pCB->MultiSelectCB.SelectLockObj, "SelectLockObj")); + OSI_RET_OK_CHECK(sl_SyncObjCreate(&g_pCB->MultiSelectCB.SelectSyncObj, "SelectSyncObj")); + SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->MultiSelectCB.SelectSyncObj); + g_pCB->MultiSelectCB.CtrlSockFD = 0xFF; +#endif + return SL_OS_RET_CODE_OK; +} + +/***************************************************************************** +_SlDrvDriverCBDeinit - De init Driver Control Block +*****************************************************************************/ +_SlReturnVal_t _SlDrvDriverCBDeinit(void) +{ + _SlSpawnMsgItem_t* pCurr; + _SlSpawnMsgItem_t* pNext; + + /* Flow control de-init */ + g_pCB->FlowContCB.TxPoolCnt = 0; + + SL_SET_DEVICE_STATUS(0); + + SL_UNSET_DEVICE_STARTED; + + OSI_RET_OK_CHECK(sl_LockObjDelete(&g_pCB->FlowContCB.TxLockObj)); + OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->FlowContCB.TxSyncObj)); +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + OSI_RET_OK_CHECK(sl_LockObjDelete(&g_pCB->MultiSelectCB.SelectLockObj)); + OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->MultiSelectCB.SelectSyncObj)); +#endif + OSI_RET_OK_CHECK( sl_SyncObjDelete(&g_pCB->CmdSyncObj)); + + OSI_RET_OK_CHECK( sl_LockObjDelete(&g_pCB->ProtectionLockObj) ); + + g_pCB->FreePoolIdx = 0; + g_pCB->PendingPoolIdx = MAX_CONCURRENT_ACTIONS; + g_pCB->ActivePoolIdx = MAX_CONCURRENT_ACTIONS; + +#ifdef SL_MEMORY_MGMT_DYNAMIC + /* Release linked list of async buffers */ + pCurr = g_pCB->spawnMsgList; + while (NULL != pCurr) + { + pNext = pCurr->next; + sl_Free(pCurr->Buffer); + sl_Free(pCurr); + pCurr = pNext; + } + g_pCB->spawnMsgList = NULL; + +#endif + + g_pCB = NULL; + +#ifndef SL_TINY + /* Clear the restart device flag */ + SL_UNSET_RESTART_REQUIRED; +#endif + return SL_OS_RET_CODE_OK; +} + +/***************************************************************************** +_SlDrvRxIrqHandler - Interrupt handler +*****************************************************************************/ +_SlReturnVal_t _SlDrvRxIrqHandler(void *pValue) +{ + (void)pValue; + + sl_IfMaskIntHdlr(); + + RxIrqCnt++; + + if (TRUE == g_pCB->WaitForCmdResp) + { + OSI_RET_OK_CHECK( sl_SyncObjSignalFromIRQ(&g_pCB->CmdSyncObj) ); + } + else + { + (void)sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER); + } + return SL_OS_RET_CODE_OK; +} + +/***************************************************************************** +_SlDrvDriverIsApiAllowed - on LOCKED state, only 3 commands are allowed +*****************************************************************************/ +_SlReturnVal_t _SlDrvDriverIsApiAllowed(_u16 Silo) +{ + if (!SL_IS_COMMAND_ALLOWED) + { + if (SL_IS_DEVICE_STOP_IN_PROGRESS) + { + return SL_RET_CODE_STOP_IN_PROGRESS; + } + + if ((SL_IS_DEVICE_LOCKED) && (SL_OPCODE_SILO_FS != Silo)) + { + /* All APIs except the FS ones must be aborted if device is locked */ + return SL_RET_CODE_DEV_LOCKED; + } + if (SL_IS_RESTART_REQUIRED) + { + /* API has been aborted due command not allowed when Restart required */ + /* The opcodes allowed are: SL_OPCODE_DEVICE_STOP_COMMAND */ + return SL_API_ABORTED; + } + + if (!SL_IS_DEVICE_STARTED) + { + return SL_RET_CODE_DEV_NOT_STARTED; + } + + if (( SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_INITIATED_BY_USER) && !(SL_IS_PROVISIONING_API_ALLOWED)) + { + /* API has ignored due to provisioning in progress */ + return SL_RET_CODE_PROVISIONING_IN_PROGRESS; + } + + } + + return SL_OS_RET_CODE_OK; +} + + +/***************************************************************************** +_SlDrvCmdOp +*****************************************************************************/ +_SlReturnVal_t _SlDrvCmdOp( + _SlCmdCtrl_t *pCmdCtrl , + void *pTxRxDescBuff , + _SlCmdExt_t *pCmdExt) +{ + _SlReturnVal_t RetVal; + _u8 IsLockRequired = TRUE; + + IsLockRequired = (SL_IS_PROVISIONING_IN_PROGRESS && (pCmdCtrl->Opcode == SL_OPCODE_DEVICE_STOP_COMMAND)) ? FALSE: TRUE; + + if (IsLockRequired) + { + _u32 GlobalLockFlags = GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS; + + /* check the special case of provisioning stop command */ + if (pCmdCtrl->Opcode == SL_OPCODE_WLAN_PROVISIONING_COMMAND) + { + SlWlanProvisioningParams_t *pParams = (SlWlanProvisioningParams_t *)pTxRxDescBuff; + + /* No timeout specifies it is a stop provisioning command */ + if (pParams->InactivityTimeoutSec == 0) + { + GlobalLockFlags |= GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API; + } + + } + + GlobalLockFlags |= (((_u32)pCmdCtrl->Opcode) << 16); + SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GlobalLockFlags); + } + +#ifndef SL_TINY + /* In case the global was successfully taken but error in progress + it means it has been released as part of an error handling and we should abort immediately */ + if (SL_IS_RESTART_REQUIRED) + { + if (IsLockRequired) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + } + + return SL_API_ABORTED; + } +#endif + + g_pCB->WaitForCmdResp = TRUE; + + SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdOp: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); + + /* send the message */ + RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); + + if(SL_OS_RET_CODE_OK == RetVal) + { + /* wait for respond */ + RetVal = _SlDrvMsgReadCmdCtx(pCmdCtrl->Opcode, IsLockRequired); /* will free global lock */ + SL_TRACE1(DBG_MSG, MSG_314, "\n\r_SlDrvCmdOp: exited _SlDrvMsgReadCmdCtx: %x\n\r", pCmdCtrl->Opcode); + } + else + { + if (IsLockRequired) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + } + + } + + return RetVal; +} + +/***************************************************************************** +_SlDrvDataReadOp +*****************************************************************************/ +_SlReturnVal_t _SlDrvDataReadOp( + _SlSd_t Sd, + _SlCmdCtrl_t *pCmdCtrl , + void *pTxRxDescBuff , + _SlCmdExt_t *pCmdExt) +{ + _SlReturnVal_t RetVal; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + _SlArgsData_t pArgsData; + + /* Validate input arguments */ + _SL_ASSERT_ERROR(NULL != pCmdExt->pRxPayload, SL_RET_CODE_INVALID_INPUT); + + /* If zero bytes is requested, return error. */ + /* This allows us not to fill remote socket's IP address in return arguments */ + VERIFY_PROTOCOL(0 != pCmdExt->RxPayloadLen); + + /* Validate socket */ + if((Sd & SL_BSD_SOCKET_ID_MASK) >= SL_MAX_SOCKETS) + { + return SL_ERROR_BSD_EBADF; + } + + /*Use Obj to issue the command, if not available try later*/ + ObjIdx = _SlDrvWaitForPoolObj(RECV_ID, Sd & SL_BSD_SOCKET_ID_MASK); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) + { + return SL_RET_CODE_STOP_IN_PROGRESS; + } + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + pArgsData.pData = pCmdExt->pRxPayload; + pArgsData.pArgs = (_u8 *)pTxRxDescBuff; + g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&pArgsData; + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + + /* Do Flow Control check/update for DataWrite operation */ + SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->FlowContCB.TxLockObj); + + + /* Clear SyncObj for the case it was signaled before TxPoolCnt */ + /* dropped below '1' (last Data buffer was taken) */ + /* OSI_RET_OK_CHECK( sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj) ); */ + SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->FlowContCB.TxSyncObj); + + if(g_pCB->FlowContCB.TxPoolCnt <= FLOW_CONT_MIN) + { + + /* If TxPoolCnt was increased by other thread at this moment, + TxSyncObj won't wait here */ +#if defined (SL_PLATFORM_MULTI_THREADED) + if (_SlDrvIsSpawnOwnGlobalLock()) + { + while (TRUE) + { + /* If we are in spawn context, this is an API which was called from event handler, + read any async event and check if we got signaled */ + _SlInternalSpawnWaitForEvent(); + /* is it mine? */ + if (0 == sl_SyncObjWait(&g_pCB->FlowContCB.TxSyncObj, SL_OS_NO_WAIT)) + { + break; + } + } + } + else +#endif + { + SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->FlowContCB.TxSyncObj); + } + + } + + SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); + +#ifndef SL_TINY + /* In case the global was successfully taken but error in progress + it means it has been released as part of an error handling and we should abort immediately */ + if (SL_IS_RESTART_REQUIRED) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + return SL_API_ABORTED; + } +#endif + + /* Here we consider the case in which some cmd has been sent to the NWP, + And its allocated packet has not been freed yet. */ + VERIFY_PROTOCOL(g_pCB->FlowContCB.TxPoolCnt > (FLOW_CONT_MIN - 1)); + g_pCB->FlowContCB.TxPoolCnt--; + + SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); + + /* send the message */ + RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, (_u8 *)pTxRxDescBuff); + + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + + if(SL_OS_RET_CODE_OK == RetVal) + { +#ifndef SL_TINY + /* in case socket is non-blocking one, the async event should be received immediately */ + if( g_pCB->SocketNonBlocking & (1<<(Sd & SL_BSD_SOCKET_ID_MASK) )) + { + _u16 opcodeAsyncEvent = (pCmdCtrl->Opcode == SL_OPCODE_SOCKET_RECV) ? SL_OPCODE_SOCKET_RECVASYNCRESPONSE : SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE; + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, opcodeAsyncEvent)); + } + else +#endif + { + /* Wait for response message. Will be signaled by _SlDrvMsgRead. */ + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); + } + + } + + _SlDrvReleasePoolObj(ObjIdx); + return RetVal; +} + +/* ******************************************************************************/ +/* _SlDrvDataWriteOp */ +/* ******************************************************************************/ +_SlReturnVal_t _SlDrvDataWriteOp( + _SlSd_t Sd, + _SlCmdCtrl_t *pCmdCtrl , + void *pTxRxDescBuff , + _SlCmdExt_t *pCmdExt) +{ + _SlReturnVal_t RetVal = SL_ERROR_BSD_EAGAIN; /* initiated as SL_EAGAIN for the non blocking mode */ + _u32 allocTxPoolPkts; + + while( 1 ) + { + /* Do Flow Control check/update for DataWrite operation */ + SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->FlowContCB.TxLockObj); + + /* Clear SyncObj for the case it was signaled before TxPoolCnt */ + /* dropped below '1' (last Data buffer was taken) */ + /* OSI_RET_OK_CHECK( sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj) ); */ + SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->FlowContCB.TxSyncObj); + + /* number of tx pool packet that will be used */ + allocTxPoolPkts = 1 + (pCmdExt->TxPayload1Len-1) / g_pCB->FlowContCB.MinTxPayloadSize; /* MinTxPayloadSize will be updated by Asunc event from NWP */ + /* we have indication that the last send has failed - socket is no longer valid for operations */ + if(g_pCB->SocketTXFailure & (1<<(Sd & SL_BSD_SOCKET_ID_MASK))) + { + SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); + return SL_ERROR_BSD_SOC_ERROR; + } + if(g_pCB->FlowContCB.TxPoolCnt <= FLOW_CONT_MIN + allocTxPoolPkts) + { + /* we have indication that this socket is set as blocking and we try to */ + /* unblock it - return an error */ + if( g_pCB->SocketNonBlocking & (1<<(Sd & SL_BSD_SOCKET_ID_MASK) )) + { +#if defined (SL_PLATFORM_MULTI_THREADED) + if (_SlDrvIsSpawnOwnGlobalLock()) + { + _SlInternalSpawnWaitForEvent(); + } +#endif + SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); + return RetVal; + } + /* If TxPoolCnt was increased by other thread at this moment, */ + /* TxSyncObj won't wait here */ +#if defined (SL_PLATFORM_MULTI_THREADED) + if (_SlDrvIsSpawnOwnGlobalLock()) + { + while (TRUE) + { + /* If we are in spawn context, this is an API which was called from event handler, + read any async event and check if we got signaled */ + _SlInternalSpawnWaitForEvent(); + /* is it mine? */ + if (0 == sl_SyncObjWait(&g_pCB->FlowContCB.TxSyncObj, SL_OS_NO_WAIT)) + { + break; + } + } + } + else +#endif + { + SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->FlowContCB.TxSyncObj); + } + } + if(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN + allocTxPoolPkts ) + { + break; + } + else + { + SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); + } + } + + SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); + +#ifndef SL_TINY + /* In case the global was succesffully taken but error in progress + it means it has been released as part of an error handling and we should abort immediately */ + if (SL_IS_RESTART_REQUIRED) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + return SL_API_ABORTED; + } +#endif + + /* Here we consider the case in which some cmd has been sent to the NWP, + And its allocated packet has not been freed yet. */ + VERIFY_PROTOCOL(g_pCB->FlowContCB.TxPoolCnt > (FLOW_CONT_MIN + allocTxPoolPkts -1) ); + g_pCB->FlowContCB.TxPoolCnt -= (_u8)allocTxPoolPkts; + + SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); + + SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdOp: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); + + /* send the message */ + RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + + return RetVal; +} + +/* ******************************************************************************/ +/* _SlDrvMsgWrite */ +/* ******************************************************************************/ +static _SlReturnVal_t _SlDrvMsgWrite(_SlCmdCtrl_t *pCmdCtrl,_SlCmdExt_t *pCmdExt, _u8 *pTxRxDescBuff) +{ + _u8 sendRxPayload = FALSE; + _SL_ASSERT_ERROR(NULL != pCmdCtrl, SL_API_ABORTED); + + g_pCB->FunctionParams.pCmdCtrl = pCmdCtrl; + g_pCB->FunctionParams.pTxRxDescBuff = pTxRxDescBuff; + g_pCB->FunctionParams.pCmdExt = pCmdExt; + + g_pCB->TempProtocolHeader.Opcode = pCmdCtrl->Opcode; + g_pCB->TempProtocolHeader.Len = (_u16)(_SL_PROTOCOL_CALC_LEN(pCmdCtrl, pCmdExt)); + + if (pCmdExt && pCmdExt->RxPayloadLen < 0 ) + { + pCmdExt->RxPayloadLen = pCmdExt->RxPayloadLen * (-1); /* change sign */ + sendRxPayload = TRUE; + g_pCB->TempProtocolHeader.Len = g_pCB->TempProtocolHeader.Len + pCmdExt->RxPayloadLen; + } + +#ifdef SL_START_WRITE_STAT + sl_IfStartWriteSequence(g_pCB->FD); +#endif + +#ifdef SL_IF_TYPE_UART + /* Write long sync pattern */ + NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NSyncPattern.Long, 2*SYNC_PATTERN_LEN); +#else + /* Write short sync pattern */ + NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NSyncPattern.Short, SYNC_PATTERN_LEN); +#endif + + /* Header */ + NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_pCB->TempProtocolHeader, _SL_CMD_HDR_SIZE); + + /* Descriptors */ + if (pTxRxDescBuff && pCmdCtrl->TxDescLen > 0) + { + NWP_IF_WRITE_CHECK(g_pCB->FD, pTxRxDescBuff, + _SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen)); + } + + /* A special mode where Rx payload and Rx length are used as Tx as well */ + /* This mode requires no Rx payload on the response and currently used by fs_Close and sl_Send on */ + /* transceiver mode */ + if (sendRxPayload == TRUE ) + { + NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pRxPayload, + _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->RxPayloadLen)); + } + + + /* if the message has some payload */ + if (pCmdExt) + { + /* If the message has payload, it is mandatory that the message's arguments are protocol aligned. */ + /* Otherwise the aligning of arguments will create a gap between arguments and payload. */ + VERIFY_PROTOCOL(_SL_IS_PROTOCOL_ALIGNED_SIZE(pCmdCtrl->TxDescLen)); + + /* In case two seperated buffers were supplied we should merge the two buffers*/ + if ((pCmdExt->TxPayload1Len > 0) && (pCmdExt->TxPayload2Len > 0)) + { + _u8 BuffInTheMiddle[4]; + _u8 FirstPayloadReminder = 0; + _u8 SecondPayloadOffset = 0; + + FirstPayloadReminder = pCmdExt->TxPayload1Len & 3; /* calulate the first payload reminder */ + + /* we first write the 4-bytes aligned payload part */ + pCmdExt->TxPayload1Len -= FirstPayloadReminder; + + /* writing the first transaction*/ + NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload1, pCmdExt->TxPayload1Len); + + /* Only if we the first payload is not aligned we need the intermediate transaction */ + if (FirstPayloadReminder != 0) + { + /* here we count how many bytes we need to take from the second buffer */ + SecondPayloadOffset = 4 - FirstPayloadReminder; + + /* copy the first payload reminder */ + sl_Memcpy(&BuffInTheMiddle[0], pCmdExt->pTxPayload1 + pCmdExt->TxPayload1Len, FirstPayloadReminder); + + /* add the beginning of the second payload to complete 4-bytes transaction */ + sl_Memcpy(&BuffInTheMiddle[FirstPayloadReminder], pCmdExt->pTxPayload2, SecondPayloadOffset); + + /* write the second transaction of the 4-bytes buffer */ + NWP_IF_WRITE_CHECK(g_pCB->FD, &BuffInTheMiddle[0], 4); + } + + + /* if we still has bytes to write in the second buffer */ + if (pCmdExt->TxPayload2Len > SecondPayloadOffset) + { + /* write the third transaction (truncated second payload) */ + NWP_IF_WRITE_CHECK(g_pCB->FD, + pCmdExt->pTxPayload2 + SecondPayloadOffset, + _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload2Len - SecondPayloadOffset)); + } + + } + else if (pCmdExt->TxPayload1Len > 0) + { + /* Only 1 payload supplied (Payload1) so just align to 4 bytes and send it */ + NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload1, + _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload1Len)); + } + else if (pCmdExt->TxPayload2Len > 0) + { + /* Only 1 payload supplied (Payload2) so just align to 4 bytes and send it */ + NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload2, + _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload2Len)); + + } + } + + _SL_DBG_CNT_INC(MsgCnt.Write); + +#ifdef SL_START_WRITE_STAT + sl_IfEndWriteSequence(g_pCB->FD); +#endif + + return SL_OS_RET_CODE_OK; +} + +/* ******************************************************************************/ +/* _SlDrvMsgRead */ +/* ******************************************************************************/ +_SlReturnVal_t _SlDrvMsgRead(_u16* outMsgReadLen, _u8** pOutAsyncBuf) +{ + /* alignment for small memory models */ + union + { + _u8 TempBuf[_SL_RESP_HDR_SIZE]; + _u32 DummyBuf[2]; + } uBuf; + _u8 TailBuffer[4]; + _u16 LengthToCopy; + _u16 AlignedLengthRecv; + _u8 *pAsyncBuf = NULL; + _u16 OpCode; + _u16 RespPayloadLen; + _u8 sd = SL_MAX_SOCKETS; + _SlReturnVal_t RetVal; + _SlRxMsgClass_e RxMsgClass; + + /* Save parameters in global CB */ + g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = NULL; + _SlDrvMemZero(&TailBuffer[0], sizeof(TailBuffer)); + +#ifdef SL_TINY + VERIFY_RET_OK(_SlDrvRxHdrRead((_u8*)(uBuf.TempBuf))); +#else + if (_SlDrvRxHdrRead((_u8*)(uBuf.TempBuf)) == SL_API_ABORTED) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + + _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_SYNC_LOSS, 0, 0); + return SL_API_ABORTED; + } +#endif + + OpCode = OPCODE(uBuf.TempBuf); + RespPayloadLen = (_u16)(RSP_PAYLOAD_LEN(uBuf.TempBuf)); + + /* Update the NWP status */ + g_pCB->FlowContCB.TxPoolCnt = ((_SlResponseHeader_t *)uBuf.TempBuf)->TxPoolCnt; + g_pCB->SocketNonBlocking = ((_SlResponseHeader_t *)uBuf.TempBuf)->SocketNonBlocking; + g_pCB->SocketTXFailure = ((_SlResponseHeader_t *)uBuf.TempBuf)->SocketTXFailure; + g_pCB->FlowContCB.MinTxPayloadSize = ((_SlResponseHeader_t *)uBuf.TempBuf)->MinMaxPayload; + + SL_SET_DEVICE_STATUS(((_SlResponseHeader_t *)uBuf.TempBuf)->DevStatus); + + if(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN) + { + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->FlowContCB.TxSyncObj); + } + + /* Find the RX message class and set its Async event handler */ + _SlDrvClassifyRxMsg(OpCode); + + RxMsgClass = g_pCB->FunctionParams.AsyncExt.RxMsgClass; + + switch(RxMsgClass) + { + case ASYNC_EVT_CLASS: + { + VERIFY_PROTOCOL(NULL == pAsyncBuf); + +#ifdef SL_MEMORY_MGMT_DYNAMIC + *pOutAsyncBuf = (_u8*)sl_Malloc(SL_ASYNC_MAX_MSG_LEN); + +#else + *pOutAsyncBuf = g_StatMem.AsyncRespBuf; +#endif + /* set the local pointer to the allocated one */ + pAsyncBuf = *pOutAsyncBuf; + + MALLOC_OK_CHECK(pAsyncBuf); + + /* clear the async buffer */ + _SlDrvMemZero(pAsyncBuf, (_u16)SL_ASYNC_MAX_MSG_LEN); + sl_Memcpy(pAsyncBuf, uBuf.TempBuf, _SL_RESP_HDR_SIZE); + + /* add the protocol header length */ + *outMsgReadLen = _SL_RESP_HDR_SIZE; + + if (_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) <= SL_ASYNC_MAX_PAYLOAD_LEN) + { + AlignedLengthRecv = (_u16)_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen); + } + else + { + AlignedLengthRecv = (_u16)_SL_PROTOCOL_ALIGN_SIZE(SL_ASYNC_MAX_PAYLOAD_LEN); + } + + /* complete the read of the entire message to the async buffer */ + if (RespPayloadLen > 0) + { + NWP_IF_READ_CHECK(g_pCB->FD, + pAsyncBuf + _SL_RESP_HDR_SIZE, + AlignedLengthRecv); + *outMsgReadLen += AlignedLengthRecv; + } + /* In case ASYNC RX buffer length is smaller then the received data length, dump the rest */ + if ((_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) > SL_ASYNC_MAX_PAYLOAD_LEN)) + { + AlignedLengthRecv = (_u16)(_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) - SL_ASYNC_MAX_PAYLOAD_LEN); + while (AlignedLengthRecv > 0) + { + NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); + AlignedLengthRecv = AlignedLengthRecv - 4; + } + } + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + if ( +#ifndef SL_TINY + (SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE == OpCode) || + (SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE_V6 == OpCode) || +#endif + (SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE == OpCode) || + (SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT == OpCode) + ) + { + /* go over the active list if exist to find obj waiting for this Async event */ + sd = ((((SlSocketResponse_t *)(pAsyncBuf + _SL_RESP_HDR_SIZE))->Sd) & SL_BSD_SOCKET_ID_MASK); + } +#ifndef SL_TINY + if (SL_OPCODE_SOCKET_SOCKETASYNCEVENT == OpCode) + { + /* Save the socket descriptor which has been waiting for this opcode */ + sd = ((((SlSocketAsyncEvent_t *)(pAsyncBuf + _SL_RESP_HDR_SIZE))->Sd) & SL_BSD_SOCKET_ID_MASK); + } +#endif + + (void)_SlDrvFindAndSetActiveObj(OpCode, sd); + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + break; + } + + case RECV_RESP_CLASS: + { + _u8 ExpArgSize; /* Expected size of Recv/Recvfrom arguments */ + + switch(OpCode) + { + case SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE: + ExpArgSize = (_u8)RECVFROM_IPV4_ARGS_SIZE; + break; +#ifndef SL_TINY + case SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6: + ExpArgSize = (_u8)RECVFROM_IPV6_ARGS_SIZE; + break; +#endif + default: + /* SL_OPCODE_SOCKET_RECVASYNCRESPONSE: */ + ExpArgSize = (_u8)RECV_ARGS_SIZE; + } + + /* Read first 4 bytes of Recv/Recvfrom response to get SocketId and actual */ + /* response data length */ + NWP_IF_READ_CHECK(g_pCB->FD, &uBuf.TempBuf[4], RECV_ARGS_SIZE); + + /* Validate Socket ID and Received Length value. */ + VERIFY_PROTOCOL((SD(&uBuf.TempBuf[4])& SL_BSD_SOCKET_ID_MASK) < SL_MAX_SOCKETS); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + /* go over the active list if exist to find obj waiting for this Async event */ + RetVal = _SlDrvFindAndSetActiveObj(OpCode, SD(&uBuf.TempBuf[4]) & SL_BSD_SOCKET_ID_MASK); + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + /* This case is for reading the receive response sent by clearing the control socket. */ + if((RetVal == SL_RET_CODE_SELF_ERROR) && (SD(&uBuf.TempBuf[4]) == g_pCB->MultiSelectCB.CtrlSockFD)) + { + _u8 buffer[16]; + + sl_Memcpy(&buffer[0], &uBuf.TempBuf[4], RECV_ARGS_SIZE); + + if(ExpArgSize > (_u8)RECV_ARGS_SIZE) + { + NWP_IF_READ_CHECK(g_pCB->FD, + &buffer[RECV_ARGS_SIZE], + ExpArgSize - RECV_ARGS_SIZE); + } + + /* Here g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData contains requested(expected) Recv/Recvfrom DataSize. */ + /* Overwrite requested DataSize with actual one. */ + /* If error is received, this information will be read from arguments. */ + if(ACT_DATA_SIZE(&uBuf.TempBuf[4]) > 0) + { + + /* Read 4 bytes aligned from interface */ + /* therefore check the requested length and read only */ + /* 4 bytes aligned data. The rest unaligned (if any) will be read */ + /* and copied to a TailBuffer */ + LengthToCopy = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (3)); + AlignedLengthRecv = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (~3)); + if( AlignedLengthRecv >= 4) + { + NWP_IF_READ_CHECK(g_pCB->FD, &buffer[ExpArgSize], AlignedLengthRecv); + } + /* copy the unaligned part, if any */ + if( LengthToCopy > 0) + { + NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); + /* copy TailBuffer unaligned part (1/2/3 bytes) */ + sl_Memcpy(&buffer[ExpArgSize + AlignedLengthRecv], TailBuffer, LengthToCopy); + } + } + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + } + else +#endif + { + /* if _SlDrvFindAndSetActiveObj returned an error, release the protection lock, and return. */ + if(RetVal < 0) + { + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return SL_API_ABORTED; + } + + /* Verify data is waited on this socket. The pArgs should have been set by _SlDrvDataReadOp(). */ + VERIFY_SOCKET_CB(NULL != ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData))->pArgs); + + sl_Memcpy( ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pArgs, &uBuf.TempBuf[4], RECV_ARGS_SIZE); + + if(ExpArgSize > (_u8)RECV_ARGS_SIZE) + { + NWP_IF_READ_CHECK(g_pCB->FD, + ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pArgs + RECV_ARGS_SIZE, + ExpArgSize - RECV_ARGS_SIZE); + } + + /* Here g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData contains requested(expected) Recv/Recvfrom DataSize. */ + /* Overwrite requested DataSize with actual one. */ + /* If error is received, this information will be read from arguments. */ + if(ACT_DATA_SIZE(&uBuf.TempBuf[4]) > 0) + { + VERIFY_SOCKET_CB(NULL != ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData); + + /* Read 4 bytes aligned from interface */ + /* therefore check the requested length and read only */ + /* 4 bytes aligned data. The rest unaligned (if any) will be read */ + /* and copied to a TailBuffer */ + LengthToCopy = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (3)); + AlignedLengthRecv = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (~3)); + if( AlignedLengthRecv >= 4) + { + NWP_IF_READ_CHECK(g_pCB->FD,((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData, AlignedLengthRecv); + } + /* copy the unaligned part, if any */ + if( LengthToCopy > 0) + { + NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); + /* copy TailBuffer unaligned part (1/2/3 bytes) */ + sl_Memcpy(((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData + AlignedLengthRecv,TailBuffer,LengthToCopy); + } + } + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + SL_DRV_PROTECTION_OBJ_UNLOCK(); + } + + break; + } + + case CMD_RESP_CLASS: + { + /* Some commands pass a maximum arguments size. */ + /* In this case Driver will send extra dummy patterns to NWP if */ + /* the response message is smaller than maximum. */ + /* When RxDescLen is not exact, using RxPayloadLen is forbidden! */ + /* If such case cannot be avoided - parse message here to detect */ + /* arguments/payload border. */ + NWP_IF_READ_CHECK(g_pCB->FD, + g_pCB->FunctionParams.pTxRxDescBuff, + _SL_PROTOCOL_ALIGN_SIZE(g_pCB->FunctionParams.pCmdCtrl->RxDescLen)); + + if((NULL != g_pCB->FunctionParams.pCmdExt) && (0 != g_pCB->FunctionParams.pCmdExt->RxPayloadLen)) + { + /* Actual size of command's response payload: - */ + _i16 ActDataSize = (_i16)(RSP_PAYLOAD_LEN(uBuf.TempBuf) - g_pCB->FunctionParams.pCmdCtrl->RxDescLen); + + g_pCB->FunctionParams.pCmdExt->ActualRxPayloadLen = ActDataSize; + + /* Check that the space prepared by user for the response data is sufficient. */ + if(ActDataSize <= 0) + { + g_pCB->FunctionParams.pCmdExt->RxPayloadLen = 0; + } + else + { + /* In case the user supplied Rx buffer length which is smaller then the received data length, copy according to user length */ + if (ActDataSize > g_pCB->FunctionParams.pCmdExt->RxPayloadLen) + { + LengthToCopy = (_u16)(g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (3)); + AlignedLengthRecv = (_u16)(g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (~3)); + } + else + { + LengthToCopy = (_u16)(ActDataSize & (3)); + AlignedLengthRecv = (_u16)(ActDataSize & (~3)); + } + /* Read 4 bytes aligned from interface */ + /* therefore check the requested length and read only */ + /* 4 bytes aligned data. The rest unaligned (if any) will be read */ + /* and copied to a TailBuffer */ + + if( AlignedLengthRecv >= 4) + { + NWP_IF_READ_CHECK(g_pCB->FD, + g_pCB->FunctionParams.pCmdExt->pRxPayload, + AlignedLengthRecv ); + + } + /* copy the unaligned part, if any */ + if( LengthToCopy > 0) + { + NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); + /* copy TailBuffer unaligned part (1/2/3 bytes) */ + sl_Memcpy(g_pCB->FunctionParams.pCmdExt->pRxPayload + AlignedLengthRecv, + TailBuffer, + LengthToCopy); + ActDataSize = ActDataSize-4; + } + /* In case the user supplied Rx buffer length which is smaller then the received data length, dump the rest */ + if (ActDataSize > g_pCB->FunctionParams.pCmdExt->RxPayloadLen) + { + /* calculate the rest of the data size to dump */ + AlignedLengthRecv = (_u16)( (ActDataSize + 3 - g_pCB->FunctionParams.pCmdExt->RxPayloadLen) & (~3) ); + while( AlignedLengthRecv > 0) + { + NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer, 4 ); + AlignedLengthRecv = AlignedLengthRecv - 4; + } + } + } + } + + break; + } + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + case MULTI_SELECT_RESP_CLASS: + { + /* In case we read Select Response from NWP, and we're not waiting for + * command complete, that means that a select command was send for a select Joiner. */ + + _u8 Idx; + + NWP_IF_READ_CHECK(g_pCB->FD, + (_u8*)(&g_pCB->MultiSelectCB.SelectCmdResp), + _SL_PROTOCOL_ALIGN_SIZE(sizeof(_BasicResponse_t))); + + if(g_pCB->MultiSelectCB.SelectCmdResp.status != SL_RET_CODE_OK) + { + /* If a select response returns without Status O.K, this means that + * something terribly wrong have happen. So we stop all waiting select callers, + * and return command error. */ + g_pCB->MultiSelectCB.ActiveSelect = FALSE; + + for(Idx = 0 ; Idx < MAX_CONCURRENT_ACTIONS ; Idx++) + { + if(g_pCB->MultiSelectCB.SelectEntry[Idx] != NULL) + { + sl_SyncObjSignal(&g_pCB->ObjPool[Idx].SyncObj); + } + } + /* Clean all table entries, and clear the global read/write fds */ + _SlDrvMemZero(&g_pCB->MultiSelectCB, sizeof(_SlMultiSelectCB_t)); + } + + break; + } +#endif + + default: + /* DUMMY_MSG_CLASS: Flow control message has no payload. */ + break; + } + + _SL_DBG_CNT_INC(MsgCnt.Read); + + /* Unmask Interrupt call */ + sl_IfUnMaskIntHdlr(); + + return SL_OS_RET_CODE_OK; +} + + +/* ******************************************************************************/ +/* _SlDrvAsyncEventGenericHandler */ +/* ******************************************************************************/ +static void _SlDrvAsyncEventGenericHandler(_u8 bInCmdContext, _u8 *pAsyncBuffer) +{ + _u32 SlAsyncEvent = 0; + _u8 OpcodeFound = FALSE; + _u8 i; + + _u32* pEventLocation = NULL; /* This pointer will override the async buffer with the translated event type */ + _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)pAsyncBuffer; + + + /* if no async event registered nothing to do..*/ + if (g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler == NULL) + { + return; + } + + /* In case we in the middle of the provisioning, filter out + all the async events except the provisioning ones */ + if ( (( SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_INITIATED_BY_USER) && !(SL_IS_PROVISIONING_API_ALLOWED)) && + (pHdr->GenHeader.Opcode != SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT) && + (pHdr->GenHeader.Opcode != SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT) && + (pHdr->GenHeader.Opcode != SL_OPCODE_DEVICE_INITCOMPLETE) && + (pHdr->GenHeader.Opcode != SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE) && + (pHdr->GenHeader.Opcode != SL_OPCODE_NETAPP_REQUEST) ) + { + return; + } + + /* Iterate through all the opcode in the table */ + for (i=0; i< (_u8)(sizeof(OpcodeTranslateTable) / sizeof(OpcodeKeyVal_t)); i++) + { + if (OpcodeTranslateTable[i].opcode == pHdr->GenHeader.Opcode) + { + SlAsyncEvent = OpcodeTranslateTable[i].event; + OpcodeFound = TRUE; + break; + } + } + + /* No Async event found in the table */ + if (OpcodeFound == FALSE) + { + if ((pHdr->GenHeader.Opcode & SL_OPCODE_SILO_MASK) == SL_OPCODE_SILO_DEVICE) + { + DeviceEventInfo_t deviceEvent; + + deviceEvent.pAsyncMsgBuff = pAsyncBuffer; + deviceEvent.bInCmdContext = bInCmdContext; + + g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&deviceEvent); + } + else + { + /* This case handles all the async events handlers of the DEVICE & SOCK Silos which are handled internally. + For these cases we send the async even buffer as is */ + g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(pAsyncBuffer); + } + } + else + { + /* calculate the event type location to be filled in the async buffer */ + pEventLocation = (_u32*)(pAsyncBuffer + sizeof (_SlResponseHeader_t) - sizeof(SlAsyncEvent)); + + /* Override the async buffer (before the data starts ) with our event type */ + *pEventLocation = SlAsyncEvent; + + /* call the event handler registered by the user with our async buffer which now holds + the User's event type and its related data */ + g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(pEventLocation); + + } +} + +/* ******************************************************************************/ +/* _SlDrvMsgReadCmdCtx */ +/* ******************************************************************************/ +static _SlReturnVal_t _SlDrvMsgReadCmdCtx(_u16 cmdOpcode, _u8 IsLockRequired) +{ +#ifndef SL_TINY + _u32 CmdCmpltTimeout; + _i16 RetVal=0; + _u8 *pAsyncBuf = NULL; + + /* the sl_FsOpen/sl_FsProgram APIs may take long time */ + if ((cmdOpcode == SL_OPCODE_NVMEM_FILEOPEN) || (cmdOpcode == SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND)) + { + CmdCmpltTimeout = ((_u32)SL_DRIVER_TIMEOUT_LONG * 10); + } + else + { + /* For any FS command, the timeout will be the long one as the commnad response holds the full response data */ + CmdCmpltTimeout = (SL_OPCODE_SILO_FS & cmdOpcode)? (_u32)(SL_DRIVER_TIMEOUT_LONG) : (_u32)SL_DRIVER_TIMEOUT_SHORT; + } +#endif + + /* after command response is received and WaitForCmdResp */ + /* flag is set FALSE, it is necessary to read out all */ + /* Async messages in Commands context, because ssiDma_IsrHandleSignalFromSlave */ + /* could have dispatched some Async messages to g_NwpIf.CmdSyncObj */ + /* after command response but before this response has been processed */ + /* by spi_singleRead and WaitForCmdResp was set FALSE. */ + while (TRUE == g_pCB->WaitForCmdResp) + { + if(_SL_PENDING_RX_MSG(g_pCB)) + { + _u16 outMsgLen = 0; +#ifdef SL_TINY + VERIFY_RET_OK(_SlDrvMsgRead(&outMsgLen)); +#else + RetVal = _SlDrvMsgRead(&outMsgLen,&pAsyncBuf); + + if (RetVal != SL_OS_RET_CODE_OK) + { + g_pCB->WaitForCmdResp = FALSE; + + if ((IsLockRequired) && (RetVal != SL_API_ABORTED)) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + } + + return SL_API_ABORTED; + } +#endif + g_pCB->RxDoneCnt++; + + if (CMD_RESP_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) + { + g_pCB->WaitForCmdResp = FALSE; + /* In case CmdResp has been read without waiting on CmdSyncObj - that */ + /* Sync object. That to prevent old signal to be processed. */ + SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->CmdSyncObj); + } + else if (ASYNC_EVT_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) + { + +#ifdef SL_PLATFORM_MULTI_THREADED + /* Do not handle async events in command context */ + /* All async events data will be stored in list and handled in spawn context */ + RetVal = _SlSpawnMsgListInsert(outMsgLen, pAsyncBuf); + if (SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR == RetVal) + { + _SlFindAndReleasePendingCmd(); + } + +#else + _SlDrvAsyncEventGenericHandler(TRUE, pAsyncBuf); +#endif + +#ifdef SL_MEMORY_MGMT_DYNAMIC + sl_Free(pAsyncBuf); +#else + pAsyncBuf = NULL; +#endif + } +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + else if(MULTI_SELECT_RESP_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) + { + sl_SyncObjSignal(&g_pCB->MultiSelectCB.SelectSyncObj); + } +#endif + } + else + { +#ifdef SL_TINY + /* CmdSyncObj will be signaled by IRQ */ + _SlDrvSyncObjWaitForever(&g_pCB->CmdSyncObj); +#else + + RetVal = sl_SyncObjWait(&g_pCB->CmdSyncObj, CmdCmpltTimeout); + if (RetVal != 0) + { + g_pCB->WaitForCmdResp = FALSE; + + if (IsLockRequired) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + } + + /* only if device started handle the fatal error */ + if (SL_IS_DEVICE_STARTED) + { + _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_NO_CMD_ACK, cmdOpcode, (_u32)CmdCmpltTimeout); + } + + return SL_API_ABORTED; + } +#endif + } + } + +#ifdef SL_PLATFORM_MULTI_THREADED + if (_SlSpawnMsgListGetCount() > 0) + { + /* signal the spawn task to process the pending async events received during the cmd */ + sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_CMD_PROCESS); + } +#endif + + /* If there are more pending Rx Msgs after CmdResp is received, */ + /* that means that these are Async, Dummy or Read Data Msgs. */ + /* Spawn _SlDrvMsgReadSpawnCtx to trigger reading these messages from */ + /* Temporary context. */ + /* sl_Spawn is activated, using a different context */ + if (IsLockRequired) + { + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + } + + if(_SL_PENDING_RX_MSG(g_pCB)) + { + sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_CMD_CTX); + } + + return SL_OS_RET_CODE_OK; +} + +/* ******************************************************************************/ +/* _SlDrvMsgReadSpawnCtx */ +/* ******************************************************************************/ +_SlReturnVal_t _SlDrvMsgReadSpawnCtx(void *pValue) +{ + _SlReturnVal_t RetVal = SL_OS_RET_CODE_OK; + _u16 outMsgLen = 0; + _u8 *pAsyncBuf = NULL; + +#ifdef SL_POLLING_MODE_USED + + /* for polling based systems */ + do + { + if (GlobalLockObj != NULL) + { + RetVal = sl_LockObjLock(&GlobalLockObj, 0); + + if (SL_OS_RET_CODE_OK != RetVal ) + { + if (TRUE == g_pCB->WaitForCmdResp) + { + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->CmdSyncObj); + return SL_RET_CODE_OK; + } + } + + } + + } + while (SL_OS_RET_CODE_OK != RetVal); + +#else + SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); +#endif + +#ifndef SL_PLATFORM_MULTI_THREADED + /* set the global lock owner (spawn context) */ + _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_SPAWN); +#endif + /* pValue parameter is currently not in use */ + (void)pValue; + + /* Messages might have been read by CmdResp context. Therefore after */ + /* getting LockObj, check again where the Pending RX Msg is still present. */ + if(FALSE == (_SL_PENDING_RX_MSG(g_pCB))) + { +#ifndef SL_PLATFORM_MULTI_THREADED + /* clear the global lock owner (spawn context) */ + _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); +#endif + SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); + + return SL_RET_CODE_OK; + } + +#ifdef SL_TINY + VERIFY_RET_OK(_SlDrvMsgRead(&outMsgLen)); +#else + RetVal = _SlDrvMsgRead(&outMsgLen,&pAsyncBuf); + + if (RetVal != SL_OS_RET_CODE_OK) + { + if (RetVal != SL_API_ABORTED) + { +#ifndef SL_PLATFORM_MULTI_THREADED + /* clear the global lock owner (spawn context) */ + _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); +#endif + SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); + } + + return SL_API_ABORTED; + } +#endif + + g_pCB->RxDoneCnt++; + + switch(g_pCB->FunctionParams.AsyncExt.RxMsgClass) + { + case ASYNC_EVT_CLASS: + /* If got here and protected by LockObj a message is waiting */ + /* to be read */ + VERIFY_PROTOCOL(NULL != pAsyncBuf); + + + _SlDrvAsyncEventGenericHandler(FALSE, pAsyncBuf); + +#ifdef SL_MEMORY_MGMT_DYNAMIC + sl_Free(pAsyncBuf); +#else + pAsyncBuf = NULL; +#endif + break; + case DUMMY_MSG_CLASS: + case RECV_RESP_CLASS: + /* These types are legal in this context. Do nothing */ + break; + case CMD_RESP_CLASS: + /* Command response is illegal in this context - */ + /* One exception exists though: 'Select' response (SL_OPCODE_SOCKET_SELECTRESPONSE) Opcode = 0x1407 */ + break; +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + case MULTI_SELECT_RESP_CLASS: + /* If everything's OK, we signal for any other joiners to call 'Select'.*/ + sl_SyncObjSignal(&g_pCB->MultiSelectCB.SelectSyncObj); + break; +#endif + default: + _SL_ASSERT_ERROR(0, SL_API_ABORTED); + } +#ifndef SL_PLATFORM_MULTI_THREADED + /* clear the global lock owner (spawn context) */ + _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); +#endif + SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); + + return(SL_RET_CODE_OK); +} + +/* + +#define SL_OPCODE_SILO_DEVICE ( 0x0 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_WLAN ( 0x1 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_SOCKET ( 0x2 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_NETAPP ( 0x3 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_FS ( 0x4 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_NETCFG ( 0x5 << SL_OPCODE_SILO_OFFSET ) + +*/ + +/* The Lookup table below holds the event handlers to be called according to the incoming + RX message SILO type */ +static const _SlSpawnEntryFunc_t RxMsgClassLUT[] = { + (_SlSpawnEntryFunc_t)_SlDeviceEventHandler, /* SL_OPCODE_SILO_DEVICE */ +#if defined(slcb_WlanEvtHdlr) || defined(EXT_LIB_REGISTERED_WLAN_EVENTS) + (_SlSpawnEntryFunc_t)_SlDrvHandleWlanEvents, /* SL_OPCODE_SILO_WLAN */ +#else + NULL, +#endif +#if defined (slcb_SockEvtHdlr) || defined(EXT_LIB_REGISTERED_SOCK_EVENTS) + (_SlSpawnEntryFunc_t)_SlDrvHandleSockEvents, /* SL_OPCODE_SILO_SOCKET */ +#else + NULL, +#endif +#if defined(slcb_NetAppEvtHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_EVENTS) + (_SlSpawnEntryFunc_t)_SlDrvHandleNetAppEvents, /* SL_OPCODE_SILO_NETAPP */ +#else + NULL, +#endif + NULL, /* SL_OPCODE_SILO_FS */ + NULL, /* SL_OPCODE_SILO_NETCFG */ + (_SlSpawnEntryFunc_t)_SlNetUtilHandleAsync_Cmd, /* SL_OPCODE_SILO_NETUTIL */ + NULL +}; + + +/* ******************************************************************************/ +/* _SlDrvClassifyRxMsg */ +/* ******************************************************************************/ +static _SlReturnVal_t _SlDrvClassifyRxMsg( + _SlOpcode_t Opcode) +{ + _SlSpawnEntryFunc_t AsyncEvtHandler = NULL; + _SlRxMsgClass_e RxMsgClass = CMD_RESP_CLASS; + _u8 Silo; + + + if (0 == (SL_OPCODE_SYNC & Opcode)) + { /* Async event has received */ + + if (SL_OPCODE_DEVICE_DEVICEASYNCDUMMY == Opcode) + { + RxMsgClass = DUMMY_MSG_CLASS; + } + else if ( (SL_OPCODE_SOCKET_RECVASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE == Opcode) +#ifndef SL_TINY + || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 == Opcode) +#endif + ) + { + RxMsgClass = RECV_RESP_CLASS; + } + else + { + /* This is Async Event class message */ + RxMsgClass = ASYNC_EVT_CLASS; + + /* Despite the fact that 4 bits are allocated in the SILO field, we actually have only 6 SILOs + So we can use the 8 options of SILO in look up table */ + Silo = (_u8)((Opcode >> SL_OPCODE_SILO_OFFSET) & 0x7); + + VERIFY_PROTOCOL(Silo < (_u8)(sizeof(RxMsgClassLUT)/sizeof(_SlSpawnEntryFunc_t))); + + /* Set the SILO's async event handler according to the LUT + If this specific event requires a direct async event handler, the + async event handler will be overwrite according to the action table */ + AsyncEvtHandler = RxMsgClassLUT[Silo]; + + if ((SL_OPCODE_NETAPP_HTTPGETTOKENVALUE == Opcode) || (SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE == Opcode) || + (SL_OPCODE_NETAPP_REQUEST == Opcode) || (SL_OPCODE_NETAPP_RESPONSE == Opcode) || (SL_OPCODE_NETAPP_SEND == Opcode)) + { + AsyncEvtHandler = _SlNetAppEventHandler; + } +#ifndef SL_TINY + else if (SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE == Opcode) + { + AsyncEvtHandler = (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_PingResponse; + } +#endif + } + } +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + else if((Opcode == SL_OPCODE_SOCKET_SELECTRESPONSE) && + (g_pCB->FunctionParams.pCmdCtrl->Opcode != SL_OPCODE_SOCKET_SELECT)) + { + /* Only in case this response came from a 'Select' sent in an Async event, Mark the message as MULTI_SELECT_RESPONSE */ + RxMsgClass = MULTI_SELECT_RESP_CLASS; + } +#endif + g_pCB->FunctionParams.AsyncExt.RxMsgClass = RxMsgClass; + g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = AsyncEvtHandler; + + return SL_RET_CODE_OK; +} + + +/* ******************************************************************************/ +/* _SlDrvRxHdrRead */ +/* ******************************************************************************/ +static _SlReturnVal_t _SlDrvRxHdrRead(_u8 *pBuf) +{ + _u8 ShiftIdx; + _u8 TimeoutState = TIMEOUT_STATE_INIT_VAL; + _u8 SearchSync = TRUE; + _u8 SyncPattern[4]; +#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) + _SlTimeoutParams_t TimeoutInfo={0}; +#endif + +#ifndef SL_IF_TYPE_UART + /* 1. Write CNYS pattern to NWP when working in SPI mode only */ + NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NCnysPattern.Short, SYNC_PATTERN_LEN); +#endif + +#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) + _SlDrvStartMeasureTimeout(&TimeoutInfo, SYNC_PATTERN_TIMEOUT_IN_MSEC); +#endif + + /* 2. Read 8 bytes (protocol aligned) - expected to be the sync pattern */ + NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], 8); + + /* read while first 4 bytes are different than last 4 bytes */ + while ( *(_u32 *)&pBuf[0] == *(_u32 *)&pBuf[4]) + { + NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[4], 4); +#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) + if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) + { + return SL_API_ABORTED; + } +#endif + } + + /* scan for the sync pattern till found or timeout elapsed (if configured) */ + while (SearchSync && TimeoutState) + { + /* scan till we get the real sync pattern */ + for (ShiftIdx =0; ShiftIdx <=4 ; ShiftIdx++) + { + /* copy to local variable to ensure starting address which is 4-bytes aligned */ + sl_Memcpy(&SyncPattern[0], &pBuf[ShiftIdx], 4); + + /* sync pattern found so complete the read to 4 bytes aligned */ + if (N2H_SYNC_PATTERN_MATCH(&SyncPattern[0], g_pCB->TxSeqNum)) + { + /* copy the bytes following the sync pattern to the buffer start */ + sl_Memcpy(&pBuf[0], &pBuf[ShiftIdx + SYNC_PATTERN_LEN], 4); + + if (ShiftIdx != 0) + { + /* read the rest of the bytes (only if wer'e not aligned) (expected to complete the opcode + length fields ) */ + NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[SYNC_PATTERN_LEN - ShiftIdx], ShiftIdx); + } + + /* here we except to get the opcode + length or false doubled sync..*/ + SearchSync = FALSE; + break; + } + } + + if (SearchSync == TRUE) + { + /* sync not found move top 4 bytes to bottom */ + *(_u32 *)&pBuf[0] = *(_u32 *)&pBuf[4]; + + /* read 4 more bytes to the buffer top */ + NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[4], 4); + } + + #if (defined (slcb_GetTimestamp)) && (!defined (SL_TINY)) + + /* if we got here after first timeout detection, it means that we gave + one more chance, and we can now exit the loop with timeout expiry */ + if (TIMEOUT_ONE_MORE_SHOT == TimeoutState) + { + TimeoutState = TIMEOUT_STATE_EXPIRY; + break; + } + + /* Timeout occured. do not break now as we want to give one more chance in case + the timeout occured due to some external context switch */ + if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) + { + TimeoutState = TIMEOUT_ONE_MORE_SHOT; + } + +#endif + } /* end of while */ + +#if (defined (slcb_GetTimestamp)) && (!defined (SL_TINY)) + if (TIMEOUT_STATE_EXPIRY == TimeoutState) + { + return SL_API_ABORTED; + } +#endif + + /* 6. Scan for Double pattern. */ + while ( N2H_SYNC_PATTERN_MATCH(pBuf, g_pCB->TxSeqNum) ) + { + _SL_DBG_CNT_INC(Work.DoubleSyncPattern); + NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], SYNC_PATTERN_LEN); + } + g_pCB->TxSeqNum++; + + /* 7. Here we've read Generic Header (4 bytes opcode+length). + * Now Read the Resp Specific header (4 more bytes). */ + NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[SYNC_PATTERN_LEN], _SL_RESP_SPEC_HDR_SIZE); + + return SL_RET_CODE_OK; +} + +/* ***************************************************************************** */ +/* _SlDrvBasicCmd */ +/* ***************************************************************************** */ +typedef union +{ + _BasicResponse_t Rsp; +}_SlBasicCmdMsg_u; + + +#ifndef SL_TINY +_SlReturnVal_t _SlDrvBasicCmd(_SlOpcode_t Opcode) +{ + _SlBasicCmdMsg_u Msg; + _SlCmdCtrl_t CmdCtrl; + + _SlDrvMemZero(&Msg, (_u16)sizeof(_SlBasicCmdMsg_u)); + CmdCtrl.Opcode = Opcode; + CmdCtrl.TxDescLen = 0; + CmdCtrl.RxDescLen = (_SlArgSize_t)sizeof(_BasicResponse_t); + + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); + + return (_SlReturnVal_t)Msg.Rsp.status; +} +#endif + +/***************************************************************************** + _SlDrvCmdSend_noLock + Send SL command without waiting for command response + This function is unprotected and the caller should make + sure global lock is active. Used to send data within async event handler, where the driver is already locked. +*****************************************************************************/ +_SlReturnVal_t _SlDrvCmdSend_noLock( + _SlCmdCtrl_t *pCmdCtrl , + void *pTxRxDescBuff , + _SlCmdExt_t *pCmdExt) +{ + _SlReturnVal_t RetVal; + _u8 WaitForCmdRespOriginalVal; + + _SlFunctionParams_t originalFuncParms; + + /* save the current RespWait flag before clearing it */ + WaitForCmdRespOriginalVal = g_pCB->WaitForCmdResp; + + /* save the current command paramaters */ + sl_Memcpy(&originalFuncParms, &g_pCB->FunctionParams, sizeof(_SlFunctionParams_t)); + + g_pCB->WaitForCmdResp = FALSE; + + SL_TRACE0(DBG_MSG, MSG_312, "_SlDrvCmdSend_noLock: call _SlDrvMsgWrite"); + + /* send the message */ + RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); + + /* restore the original RespWait flag */ + g_pCB->WaitForCmdResp = WaitForCmdRespOriginalVal; + + /* restore the original command paramaters */ + sl_Memcpy(&g_pCB->FunctionParams, &originalFuncParms, sizeof(_SlFunctionParams_t)); + + return RetVal; +} +/***************************************************************************** + _SlDrvCmdSend_noWait + Send SL command without waiting for command response + This function send command form any possiable context, without waiting. +*****************************************************************************/ +_SlReturnVal_t _SlDrvCmdSend_noWait( + _SlCmdCtrl_t *pCmdCtrl , + void *pTxRxDescBuff , + _SlCmdExt_t *pCmdExt) +{ + _SlReturnVal_t RetVal; + + _SlFunctionParams_t originalFuncParms; + + SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdSend_noLock: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); + + /* Save the current function parameters */ + sl_Memcpy(&originalFuncParms, &g_pCB->FunctionParams, sizeof(_SlFunctionParams_t)); + + /* send the message */ + RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); + + /* Restore */ + sl_Memcpy(&g_pCB->FunctionParams, &originalFuncParms, sizeof(_SlFunctionParams_t)); + + return RetVal; +} + +/***************************************************************************** + _SlDrvCmdSend + Send SL command without waiting for command response +*****************************************************************************/ +#ifndef SL_TINY +_SlReturnVal_t _SlDrvCmdSend( + _SlCmdCtrl_t *pCmdCtrl , + void *pTxRxDescBuff , + _SlCmdExt_t *pCmdExt) +{ + _SlReturnVal_t RetVal; + + _SlDrvObjLockWaitForever(&GlobalLockObj); + + g_pCB->WaitForCmdResp = FALSE; + + SL_TRACE1(DBG_MSG, MSG_312, "_SlDrvCmdSend: call _SlDrvMsgWrite:%x", pCmdCtrl->Opcode); + + /* send the message */ + RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); + + _SlDrvObjUnLock(&GlobalLockObj); + + return RetVal; +} + +#endif + + +/* ***************************************************************************** */ +/* _SlDrvProtectAsyncRespSetting */ +/* ***************************************************************************** */ +_SlReturnVal_t _SlDrvProtectAsyncRespSetting(_u8 *pAsyncRsp, _SlActionID_e ActionID, _u8 SocketID) +{ + _i16 ObjIdx; + + /* Use Obj to issue the command, if not available try later */ + ObjIdx = _SlDrvWaitForPoolObj(ActionID, SocketID); + + if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) + { + return SL_RET_CODE_STOP_IN_PROGRESS; + } + else if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return MAX_CONCURRENT_ACTIONS; + } + else + { + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + g_pCB->ObjPool[ObjIdx].pRespArgs = pAsyncRsp; + SL_DRV_PROTECTION_OBJ_UNLOCK(); + } + + return ObjIdx; +} + + +/* ***************************************************************************** */ +/* _SlDrvIsSpawnOwnGlobalLock */ +/* ***************************************************************************** */ +_u8 _SlDrvIsSpawnOwnGlobalLock() +{ +#ifdef SL_PLATFORM_MULTI_THREADED + _u32 ThreadId = (_i32)pthread_self(); + return _SlInternalIsItSpawnThread(ThreadId); +#else + return (gGlobalLockContextOwner == GLOBAL_LOCK_CONTEXT_OWNER_SPAWN); +#endif +} + +/* ***************************************************************************** */ +/* _SlDrvWaitForPoolObj */ +/* ***************************************************************************** */ +_SlReturnVal_t _SlDrvWaitForPoolObj(_u8 ActionID, _u8 SocketID) +{ + _u8 CurrObjIndex = MAX_CONCURRENT_ACTIONS; + + /* Get free object */ + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + if (MAX_CONCURRENT_ACTIONS > g_pCB->FreePoolIdx) + { + /* save the current obj index */ + CurrObjIndex = g_pCB->FreePoolIdx; + /* set the new free index */ +#ifndef SL_TINY + if (MAX_CONCURRENT_ACTIONS > g_pCB->ObjPool[CurrObjIndex].NextIndex) + { + g_pCB->FreePoolIdx = g_pCB->ObjPool[CurrObjIndex].NextIndex; + } + else +#endif + { + /* No further free actions available */ + g_pCB->FreePoolIdx = MAX_CONCURRENT_ACTIONS; + } + } + else + { + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return CurrObjIndex; + } + g_pCB->ObjPool[CurrObjIndex].ActionID = (_u8)ActionID; + if (SL_MAX_SOCKETS > SocketID) + { + g_pCB->ObjPool[CurrObjIndex].AdditionalData = SocketID; + } +#ifndef SL_TINY + /*In case this action is socket related, SocketID bit will be on + In case SocketID is set to SL_MAX_SOCKETS, the socket is not relevant to the action. In that case ActionID bit will be on */ + while ( ( (SL_MAX_SOCKETS > SocketID) && (g_pCB->ActiveActionsBitmap & (1<ActiveActionsBitmap & ( MULTI_SELECT_MASK & (1<ObjPool[CurrObjIndex].ActionID = 0; + g_pCB->ObjPool[CurrObjIndex].AdditionalData = SL_MAX_SOCKETS; + g_pCB->FreePoolIdx = CurrObjIndex; + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return MAX_CONCURRENT_ACTIONS; + } + /* action in progress - move to pending list */ + g_pCB->ObjPool[CurrObjIndex].NextIndex = g_pCB->PendingPoolIdx; + g_pCB->PendingPoolIdx = CurrObjIndex; + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + /* wait for action to be free */ + (void)_SlDrvSyncObjWaitForever(&g_pCB->ObjPool[CurrObjIndex].SyncObj); + if (SL_IS_DEVICE_STOP_IN_PROGRESS) + { + OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[CurrObjIndex].SyncObj)); + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + g_pCB->NumOfDeletedSyncObj++; + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return SL_RET_CODE_STOP_IN_PROGRESS; + } + + /* set params and move to active (remove from pending list at _SlDrvReleasePoolObj) */ + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + } +#endif + /* mark as active. Set socket as active if action is on socket, otherwise mark action as active */ + if (SL_MAX_SOCKETS > SocketID) + { + g_pCB->ActiveActionsBitmap |= (1<ActiveActionsBitmap |= (1<ObjPool[CurrObjIndex].NextIndex = g_pCB->ActivePoolIdx; + g_pCB->ActivePoolIdx = CurrObjIndex; + + /* unlock */ + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + /* Increment the API in progress counter as this routine is called for every + API, which will be waiting for async event to be released */ + _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_INCREMENT); + + return CurrObjIndex; +} + +/* ******************************************************************************/ +/* _SlDrvReleasePoolObj */ +/* ******************************************************************************/ +_SlReturnVal_t _SlDrvReleasePoolObj(_u8 ObjIdx) +{ +#ifndef SL_TINY + _u8 PendingIndex; +#endif + + /* Delete sync obj in case stop in progress and return */ + if (SL_IS_DEVICE_STOP_IN_PROGRESS) + { + OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[ObjIdx].SyncObj)); + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + g_pCB->NumOfDeletedSyncObj++; + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return SL_RET_CODE_OK; + } + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + /* In Tiny mode, there is only one object pool so no pending actions are available */ +#ifndef SL_TINY + /* go over the pending list and release other pending action if needed */ + PendingIndex = g_pCB->PendingPoolIdx; + + while(MAX_CONCURRENT_ACTIONS > PendingIndex) + { + /* In case this action is socket related, SocketID is in use, otherwise will be set to SL_MAX_SOCKETS */ + if ( (g_pCB->ObjPool[PendingIndex].ActionID == g_pCB->ObjPool[ObjIdx].ActionID) && + ( (SL_MAX_SOCKETS == (g_pCB->ObjPool[PendingIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK)) || + ((SL_MAX_SOCKETS > (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)) && ( (g_pCB->ObjPool[PendingIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK) == (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK) ))) ) + { + /* remove from pending list */ + _SlDrvRemoveFromList(&g_pCB->PendingPoolIdx, PendingIndex); + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[PendingIndex].SyncObj); + break; + } + PendingIndex = g_pCB->ObjPool[PendingIndex].NextIndex; + } +#endif + + if (SL_MAX_SOCKETS > (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)) + { + /* unset socketID */ + g_pCB->ActiveActionsBitmap &= ~(1<<(g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)); + } + else + { + /* unset actionID */ + g_pCB->ActiveActionsBitmap &= ~(1<ObjPool[ObjIdx].ActionID); + } + + /* delete old data */ + g_pCB->ObjPool[ObjIdx].pRespArgs = NULL; + g_pCB->ObjPool[ObjIdx].ActionID = 0; + g_pCB->ObjPool[ObjIdx].AdditionalData = SL_MAX_SOCKETS; + + /* remove from active list */ + _SlDrvRemoveFromList(&g_pCB->ActivePoolIdx, ObjIdx); + + /* move to free list */ + g_pCB->ObjPool[ObjIdx].NextIndex = g_pCB->FreePoolIdx; + g_pCB->FreePoolIdx = ObjIdx; + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + /* Here we decrement the API in progrees counter as we just released the pool object, + which is held till the API is finished (async event received) */ + _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_DECREMENT); + return SL_RET_CODE_OK; +} + +/* ******************************************************************************/ +/* _SlDrvReleaseAllActivePendingPoolObj */ +/* ******************************************************************************/ +_SlReturnVal_t _SlDrvReleaseAllActivePendingPoolObj() +{ + _u8 ActiveIndex; + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + /* go over the active list and release each action with error */ + ActiveIndex = g_pCB->ActivePoolIdx; + + while (MAX_CONCURRENT_ACTIONS > ActiveIndex) + { + /* Set error in case sync objects release due to stop device command */ + if (g_pCB->ObjPool[ActiveIndex].ActionID == NETUTIL_CMD_ID) + { + ((_SlNetUtilCmdData_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->Status = SL_RET_CODE_STOP_IN_PROGRESS; + } + else if (g_pCB->ObjPool[ActiveIndex].ActionID == RECV_ID) + { + ((SlSocketResponse_t *)((_SlArgsData_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->pArgs)->StatusOrLen = SL_RET_CODE_STOP_IN_PROGRESS; + } + /* First 2 bytes of all async response holds the status except with NETUTIL_CMD_ID and RECV_ID */ + else + { + ((SlSocketResponse_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->StatusOrLen = SL_RET_CODE_STOP_IN_PROGRESS; + } + /* Signal the pool obj*/ + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[ActiveIndex].SyncObj); + ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; + } + + /* go over the pending list and release each action */ + ActiveIndex = g_pCB->PendingPoolIdx; + + while (MAX_CONCURRENT_ACTIONS > ActiveIndex) + { + /* Signal the pool obj*/ + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[ActiveIndex].SyncObj); + ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; + } + +#ifndef SL_TINY + /* Delete only unoccupied objects from the Free list, other obj (pending and active) + will be deleted from the relevant context */ + ActiveIndex = g_pCB->FreePoolIdx; + while(MAX_CONCURRENT_ACTIONS > ActiveIndex) +#endif + { + OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[ActiveIndex].SyncObj)); + g_pCB->NumOfDeletedSyncObj++; + ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; + } + /* In case trigger select in progress, delete the sync obj */ +#if defined(slcb_SocketTriggerEventHandler) + if (MAX_CONCURRENT_ACTIONS != g_pCB->SocketTriggerSelect.Info.ObjPoolIdx) + { + OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[g_pCB->SocketTriggerSelect.Info.ObjPoolIdx].SyncObj)); + g_pCB->NumOfDeletedSyncObj++; + } +#endif + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return SL_RET_CODE_OK; +} + +/* ******************************************************************************/ +/* _SlDrvRemoveFromList */ +/* ******************************************************************************/ +static void _SlDrvRemoveFromList(_u8 *ListIndex, _u8 ItemIndex) +{ +#ifndef SL_TINY + _u8 Idx; +#endif + + if (MAX_CONCURRENT_ACTIONS == g_pCB->ObjPool[*ListIndex].NextIndex) + { + *ListIndex = MAX_CONCURRENT_ACTIONS; + } + /* As MAX_CONCURRENT_ACTIONS is equal to 1 in Tiny mode */ +#ifndef SL_TINY + /* need to remove the first item in the list and therefore update the global which holds this index */ + else if (*ListIndex == ItemIndex) + { + *ListIndex = g_pCB->ObjPool[ItemIndex].NextIndex; + } + else + { + Idx = *ListIndex; + + while(MAX_CONCURRENT_ACTIONS > Idx) + { + /* remove from list */ + if (g_pCB->ObjPool[Idx].NextIndex == ItemIndex) + { + g_pCB->ObjPool[Idx].NextIndex = g_pCB->ObjPool[ItemIndex].NextIndex; + break; + } + + Idx = g_pCB->ObjPool[Idx].NextIndex; + } + } +#endif +} + + +/* ******************************************************************************/ +/* _SlDrvFindAndSetActiveObj */ +/* ******************************************************************************/ +static _SlReturnVal_t _SlDrvFindAndSetActiveObj(_SlOpcode_t Opcode, _u8 Sd) +{ + _u8 ActiveIndex; + + ActiveIndex = g_pCB->ActivePoolIdx; + /* go over the active list if exist to find obj waiting for this Async event */ +#ifndef SL_TINY + while (MAX_CONCURRENT_ACTIONS > ActiveIndex) +#else + /* Only one Active action is availabe in tiny mode, so we can replace the loop with if condition */ + if (MAX_CONCURRENT_ACTIONS > ActiveIndex) +#endif + { + /* unset the Ipv4\IPv6 bit in the opcode if family bit was set */ + if (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) + { + Opcode &= ~SL_OPCODE_IPV6; + } + + if ((g_pCB->ObjPool[ActiveIndex].ActionID == RECV_ID) && (Sd == g_pCB->ObjPool[ActiveIndex].AdditionalData) && + ( (SL_OPCODE_SOCKET_RECVASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE == Opcode) +#ifndef SL_TINY + || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 == Opcode) +#endif + ) + ) + { + g_pCB->FunctionParams.AsyncExt.ActionIndex = ActiveIndex; + return SL_RET_CODE_OK; + } + /* In case this action is socket related, SocketID is in use, otherwise will be set to SL_MAX_SOCKETS */ + if ( (_SlActionLookupTable[ g_pCB->ObjPool[ActiveIndex].ActionID - MAX_SOCKET_ENUM_IDX].ActionAsyncOpcode == Opcode) && + ( ((Sd == (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK) ) && (SL_MAX_SOCKETS > Sd)) || (SL_MAX_SOCKETS == (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK)) ) ) + { + /* set handler */ + g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = _SlActionLookupTable[ g_pCB->ObjPool[ActiveIndex].ActionID - MAX_SOCKET_ENUM_IDX].AsyncEventHandler; + g_pCB->FunctionParams.AsyncExt.ActionIndex = ActiveIndex; + return SL_RET_CODE_OK; + } + ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; + } + + return SL_RET_CODE_SELF_ERROR; +} + +#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) +void _SlDrvDispatchHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse) +{ + _SlDrvHandleHttpServerEvents (slHttpServerEvent, slHttpServerResponse); +} +#endif + +#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) +void _SlDrvDispatchNetAppRequestEvents(SlNetAppRequest_t *slNetAppRequestEvent, SlNetAppResponse_t *slNetAppResponse) +{ + _SlDrvHandleNetAppRequestEvents (slNetAppRequestEvent, slNetAppResponse); +} +#endif + + +/* Wrappers for the object functions */ +_SlReturnVal_t _SlDrvSyncObjSignal(_SlSyncObj_t *pSyncObj) +{ + OSI_RET_OK_CHECK(sl_SyncObjSignal(pSyncObj)); + return SL_OS_RET_CODE_OK; +} + +_SlReturnVal_t _SlDrvObjLockWaitForever(_SlLockObj_t *pLockObj) +{ + /* DPL_MG */ + OSI_RET_OK_CHECK(sl_LockObjLock(pLockObj, SL_OS_WAIT_FOREVER)); + return SL_OS_RET_CODE_OK; +} + +_SlReturnVal_t _SlDrvProtectionObjLockWaitForever(void) +{ + OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER)); + + return SL_OS_RET_CODE_OK; +} + +_SlReturnVal_t _SlDrvObjUnLock(_SlLockObj_t *pLockObj) +{ + OSI_RET_OK_CHECK(sl_LockObjUnlock(pLockObj)); + + return SL_OS_RET_CODE_OK; +} + +_SlReturnVal_t _SlDrvProtectionObjUnLock(void) +{ + OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj)); + return SL_OS_RET_CODE_OK; +} + +static _SlReturnVal_t _SlDrvObjGlobalLockWaitForever(_u32 Flags) +{ + _SlReturnVal_t ret; + _u16 Opcode; + _u16 Silo; + _u8 UpdateApiInProgress = (Flags & GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); + _u16 IsProvStopApi = (Flags & GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API); + +#ifndef SL_TINY + if (SL_IS_RESTART_REQUIRED) + { + return SL_API_ABORTED; + } +#endif + + gGlobalLockCntRequested++; + + + ret = sl_LockObjLock(&GlobalLockObj, SL_OS_WAIT_FOREVER); + + /* start/stop device is in progress so return right away */ + if (SL_IS_DEVICE_START_IN_PROGRESS || SL_IS_DEVICE_STOP_IN_PROGRESS || SL_IS_PROVISIONING_IN_PROGRESS) + { + return ret; + } + + /* after the lock acquired check if API is allowed */ + if (0 == ret) + { + + Opcode = (Flags >> 16); + Silo = Opcode & ((0xF << SL_OPCODE_SILO_OFFSET)); + + /* After acquiring the lock, check if there is stop in progress */ + if (Opcode != SL_OPCODE_DEVICE_STOP_COMMAND) + { + _i16 Status = _SlDrvDriverIsApiAllowed(Silo); + + if (Status) + { + sl_LockObjUnlock(&GlobalLockObj); + return Status; + } + } + } + + /* if lock was successfully taken and increment of the API in progress is required */ + if ((0 == ret) && (UpdateApiInProgress)) + { + if (!SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_API_ALLOWED) + { + /* Increment the API in progress counter */ + _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_INCREMENT); + } + /* if we are in provisioning than don't abort the stop provisioning cmd.. */ + else if (FALSE == IsProvStopApi ) + { + /* Provisioning is active so release the lock immediately as + we do not want to allow more APIs to run. */ + SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); + return SL_RET_CODE_PROVISIONING_IN_PROGRESS; + } + } + + return ret; +} +_SlReturnVal_t _SlDrvGlobalObjUnLock(_u8 bDecrementApiInProgress) +{ + gGlobalLockCntReleased++; + + OSI_RET_OK_CHECK(sl_LockObjUnlock(&GlobalLockObj)); + + if (bDecrementApiInProgress) + { + _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_DECREMENT); + } + + return SL_OS_RET_CODE_OK; +} + +void _SlDrvMemZero(void* Addr, _u16 size) +{ + sl_Memset(Addr, 0, size); +} + + +void _SlDrvResetCmdExt(_SlCmdExt_t* pCmdExt) +{ + _SlDrvMemZero(pCmdExt, (_u16)sizeof (_SlCmdExt_t)); +} + + +#ifdef SL_TINY + +_SlReturnVal_t _SlDrvSyncObjWaitForever(_SlSyncObj_t *pSyncObj) +{ + return sl_SyncObjWait(pSyncObj, SL_OS_WAIT_FOREVER); +} + +#else +_SlReturnVal_t _SlDrvSyncObjWaitForever(_SlSyncObj_t *pSyncObj) +{ + _SlReturnVal_t RetVal = sl_SyncObjWait(pSyncObj, SL_OS_WAIT_FOREVER); + + /* if the wait is finished and we detect that restart is required (we in the middle of error handling), + than we should abort immediately from the current API command execution + */ + if (SL_IS_RESTART_REQUIRED) + { + return SL_API_ABORTED; + } + + return RetVal; +} + +#endif + + +#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) + +void _SlDrvStartMeasureTimeout(_SlTimeoutParams_t *pTimeoutInfo, _u32 TimeoutInMsec) +{ + _SlDrvMemZero(pTimeoutInfo, sizeof (_SlTimeoutParams_t)); + + pTimeoutInfo->Total10MSecUnits = TimeoutInMsec / 10; + pTimeoutInfo->TSPrev = slcb_GetTimestamp(); +} + +_u8 _SlDrvIsTimeoutExpired(_SlTimeoutParams_t *pTimeoutInfo) +{ + _u32 TSCount; + + pTimeoutInfo->TSCurr = slcb_GetTimestamp(); + + if (pTimeoutInfo->TSCurr >= pTimeoutInfo->TSPrev) + { + pTimeoutInfo->DeltaTicks = pTimeoutInfo->TSCurr - pTimeoutInfo->TSPrev; + } + else + { + pTimeoutInfo->DeltaTicks = (SL_TIMESTAMP_MAX_VALUE - pTimeoutInfo->TSPrev) + pTimeoutInfo->TSCurr; + } + + TSCount = pTimeoutInfo->DeltaTicksReminder + pTimeoutInfo->DeltaTicks; + + + if (TSCount > SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) + { + pTimeoutInfo->Total10MSecUnits -= (TSCount / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS); + pTimeoutInfo->DeltaTicksReminder = TSCount % SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS; + + if (pTimeoutInfo->Total10MSecUnits > 0) + { + pTimeoutInfo->TSPrev = pTimeoutInfo->TSCurr; + } + else + { + return TRUE; + } + } + + return FALSE; +} + +#endif + +void _SlDrvHandleFatalError(_u32 errorId, _u32 info1, _u32 info2) +{ + _u8 i; + SlDeviceFatal_t FatalEvent; + + _SlDrvMemZero(&FatalEvent, sizeof(FatalEvent)); + + if (SL_IS_RESTART_REQUIRED) + { + return; + } + + /* set the restart flag */ + SL_SET_RESTART_REQUIRED; + + /* Upon the deletion of the mutex, all thread waiting on this + mutex will return immediately with an error (i.e. MUTEX_DELETED status) */ + (void)sl_LockObjDelete(&GlobalLockObj); + + /* Mark the global lock as deleted */ + g_IsGlobalLockObjInit = 0; + + /* signal all waiting sync objects */ + for (i=0; i< MAX_CONCURRENT_ACTIONS; i++) + { + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[i].SyncObj); + } + + /* prepare the event and notify the user app/ext libraries */ + FatalEvent.Id = errorId; + + switch (errorId) + { + case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: + { + /* set the Abort Type */ + FatalEvent.Data.DeviceAssert.Code = info1; + + /* set the Abort Data */ + FatalEvent.Data.DeviceAssert.Value = info2; + } + break; + + case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: + { + /* set the command opcode */ + FatalEvent.Data.NoCmdAck.Code = info1; + } + break; + + case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: + { + /* set the expected async event opcode */ + FatalEvent.Data.CmdTimeout.Code = info1; + } + break; + + case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: + case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: + /* No Info to transport */ + break; + + } + +#if defined(slcb_DeviceFatalErrorEvtHdlr) || defined (EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) + /* call the registered fatal error handlers */ + _SlDrvHandleFatalErrorEvents(&FatalEvent); +#endif +} + +_SlReturnVal_t _SlDrvSyncObjWaitTimeout(_SlSyncObj_t *pSyncObj, _u32 timeoutVal, _u32 asyncEventOpcode) +{ + _SlReturnVal_t ret = sl_SyncObjWait(pSyncObj, timeoutVal); + + /* if timeout occured...*/ + if (ret) + { + _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, asyncEventOpcode, timeoutVal); + return SL_API_ABORTED; + } + else if (SL_IS_RESTART_REQUIRED) + { + return SL_API_ABORTED; + } + + return SL_RET_CODE_OK; +} + + +static void _SlDrvUpdateApiInProgress(_i8 Value) +{ + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + g_pCB->ApiInProgressCnt += Value; + + SL_DRV_PROTECTION_OBJ_UNLOCK(); +} + +_i8 _SlDrvIsApiInProgress(void) +{ + if (g_pCB != NULL) + { + return (g_pCB->ApiInProgressCnt > 0); + } + + return TRUE; +} + + +#ifdef slcb_GetTimestamp + +void _SlDrvSleep(_u16 DurationInMsec) +{ + _SlTimeoutParams_t TimeoutInfo={0}; + + _SlDrvStartMeasureTimeout(&TimeoutInfo, DurationInMsec); + + while(!_SlDrvIsTimeoutExpired(&TimeoutInfo)); +} +#endif + +#ifndef SL_PLATFORM_MULTI_THREADED +void _SlDrvSetGlobalLockOwner(_u8 Owner) +{ + gGlobalLockContextOwner = Owner; +} +#endif + + +_SlReturnVal_t _SlDrvWaitForInternalAsyncEvent(_u8 ObjIdx , _u32 Timeout, _SlOpcode_t Opcode) +{ + +#if (defined(SL_PLATFORM_EXTERNAL_SPAWN) || !defined(SL_PLATFORM_MULTI_THREADED)) + SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->ObjPool[ObjIdx].SyncObj); + return SL_OS_RET_CODE_OK; +#else + _SlTimeoutParams_t SlTimeoutInfo = { 0 }; + if (_SlDrvIsSpawnOwnGlobalLock()) + { +#if (!defined (SL_TINY)) && (defined(slcb_GetTimestamp)) + _SlDrvStartMeasureTimeout(&SlTimeoutInfo, Timeout); + while (!Timeout || !_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) +#endif + { + /* If we are in spawn context, this is an API which was called from event handler, + read any async event and check if we got signaled */ + _SlInternalSpawnWaitForEvent(); + /* is it mine? */ + if (0 == sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_NO_WAIT)) + { + return SL_OS_RET_CODE_OK; + } + } + /* if timeout occured...*/ + _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, Opcode, Timeout); + return SL_API_ABORTED; + } + else + { + if (Timeout) + { + SL_DRV_SYNC_OBJ_WAIT_TIMEOUT(&g_pCB->ObjPool[ObjIdx].SyncObj, Timeout, Opcode); + } + else + { + SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->ObjPool[ObjIdx].SyncObj); + } + return SL_OS_RET_CODE_OK; + } + +#endif +} + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(SL_MEMORY_MGMT_DYNAMIC)) +_SlAsyncRespBuf_t* _SlGetStatSpawnListItem(_u16 AsyncEventLen) +{ + _u8 Idx = 0; + /* Find free buffer from the pool */ + while (Idx < SL_MAX_ASYNC_BUFFERS) + { + if (0xFF == g_StatMem.AsyncBufPool[Idx].ActionIndex) + { + /* copy buffer */ + return &g_StatMem.AsyncBufPool[Idx]; + } + Idx++; + } + return NULL; +} +#endif + +#if defined(SL_PLATFORM_MULTI_THREADED) +_SlReturnVal_t _SlSpawnMsgListInsert(_u16 AsyncEventLen, _u8 *pAsyncBuf) +{ + _SlReturnVal_t RetVal = SL_OS_RET_CODE_OK; + + /* protect the item insertion */ + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + +#ifdef SL_MEMORY_MGMT_DYNAMIC + _SlSpawnMsgItem_t* pCurr = NULL; + _SlSpawnMsgItem_t* pItem; + + pItem = (_SlSpawnMsgItem_t*)sl_Malloc(sizeof(_SlSpawnMsgItem_t)); + /* now allocate the buffer itself */ + pItem->Buffer = (void*)sl_Malloc(AsyncEventLen); + pItem->next = NULL; + /* if list is empty point to the allocated one */ + if (g_pCB->spawnMsgList == NULL) + { + g_pCB->spawnMsgList = pItem; + } + else + { + pCurr = g_pCB->spawnMsgList; + /* go to end of list */ + while (pCurr->next != NULL) + { + pCurr = pCurr->next; + } + /* we point to last item in list - add the new one */ + pCurr->next = pItem; + } +#else + _SlAsyncRespBuf_t* pItem = (_SlAsyncRespBuf_t*)_SlGetStatSpawnListItem(AsyncEventLen); +#endif + if (NULL != pItem) + { + /* save the action idx */ + pItem->ActionIndex = g_pCB->FunctionParams.AsyncExt.ActionIndex; + /* save the corresponding AsyncHndlr (if registered) */ + pItem->AsyncHndlr = g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler; + /* copy the async event that we read to the buffer */ + sl_Memcpy(pItem->Buffer, pAsyncBuf, AsyncEventLen); + } + else + { + RetVal = SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR; + } + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return RetVal; +} + +_SlReturnVal_t _SlSpawnMsgListProcess() +{ + +#ifdef SL_MEMORY_MGMT_DYNAMIC + _SlSpawnMsgItem_t* pHead = g_pCB->spawnMsgList; + _SlSpawnMsgItem_t* pCurr = pHead; + _SlSpawnMsgItem_t* pLast = pHead; + + while (pCurr != NULL) + { + /* lock during action */ + SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); + /* load the async event params */ + g_pCB->FunctionParams.AsyncExt.ActionIndex = pCurr->ActionIndex; + g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = pCurr->AsyncHndlr; + + pLast = pCurr; + pCurr = pCurr->next; + + /* move the list head to point to the next item (or null) */ + g_pCB->spawnMsgList = pCurr; + /* Handle async event: here we are in spawn context, after context + * switch from command context. */ + _SlDrvAsyncEventGenericHandler(FALSE, pLast->Buffer); + + /* free the copied buffer inside the item */ + sl_Free(pLast->Buffer); + + /* free the spawn msg item */ + sl_Free(pLast); + + SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); + } + +#else + _u8 i; + + for (i = 0; i < SL_MAX_ASYNC_BUFFERS; i++) + { + if (0xFF != g_StatMem.AsyncBufPool[i].ActionIndex) + { + /* lock during action */ + + SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); + + /* load the async event params */ + g_pCB->FunctionParams.AsyncExt.ActionIndex = g_StatMem.AsyncBufPool[i].ActionIndex; + g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = g_StatMem.AsyncBufPool[i].AsyncHndlr; + + /* Handle async event: here we are in spawn context, after context + * switch from command context. */ + _SlDrvAsyncEventGenericHandler(FALSE, (unsigned char *)&(g_StatMem.AsyncBufPool[i].Buffer)); + + SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + g_StatMem.AsyncBufPool[i].ActionIndex = 0xFF; + SL_DRV_PROTECTION_OBJ_UNLOCK(); + } + } +#endif + return SL_OS_RET_CODE_OK; +} + +_u16 _SlSpawnMsgListGetCount() +{ + _u16 NumOfItems = 0; +#ifdef SL_MEMORY_MGMT_DYNAMIC + _SlSpawnMsgItem_t* pCurr = g_pCB->spawnMsgList; + + /* protect the item insertion */ + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + while (pCurr != NULL) + { + NumOfItems++; + + pCurr = pCurr->next; + } + SL_DRV_PROTECTION_OBJ_UNLOCK(); + +#else + _u8 i; + /* protect counting parameters */ + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + for (i = 0; i < SL_MAX_ASYNC_BUFFERS; i++) + { + if (0xFF != g_StatMem.AsyncBufPool[i].ActionIndex) + { + NumOfItems++; + } + } + SL_DRV_PROTECTION_OBJ_UNLOCK(); +#endif + return NumOfItems; +} + + +void _SlFindAndReleasePendingCmd() +{ + /* In case there is no free buffer to store the async event until context switch release the command and return specific error */ + ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR; + /* signal pending cmd */ + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.h new file mode 100755 index 00000000000..bed0d8c6ef9 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/driver.h @@ -0,0 +1,515 @@ +/* + * driver.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef __DRIVER_INT_H__ +#define __DRIVER_INT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define TIMEOUT_STATE_EXPIRY (0) +#define TIMEOUT_ONE_MORE_SHOT (1) +#define TIMEOUT_STATE_INIT_VAL (2) + +/* Timeouts for the sync objects */ +#ifndef SL_DRIVER_TIMEOUT_SHORT +#define SL_DRIVER_TIMEOUT_SHORT (10000) /* msec units */ +#endif +#ifndef SL_DRIVER_TIMEOUT_LONG +#define SL_DRIVER_TIMEOUT_LONG (65535) /* msec units */ +#endif + +#define INIT_COMPLETE_TIMEOUT SL_DRIVER_TIMEOUT_LONG +#define STOP_DEVICE_TIMEOUT SL_DRIVER_TIMEOUT_LONG + +#ifndef SYNC_PATTERN_TIMEOUT_IN_MSEC +#define SYNC_PATTERN_TIMEOUT_IN_MSEC (50) /* the sync patttern timeout in milliseconds units */ +#endif +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +#ifndef CPU_FREQ_IN_MHZ + #define CPU_FREQ_IN_MHZ (200) +#endif +#define USEC_DELAY (50) + +#define SL_DRV_PROTECTION_OBJ_UNLOCK() (void)_SlDrvProtectionObjUnLock(); +#define SL_DRV_PROTECTION_OBJ_LOCK_FOREVER() (void)_SlDrvProtectionObjLockWaitForever(); +#define SL_DRV_OBJ_UNLOCK(pObj) (void)_SlDrvObjUnLock(pObj); +#define SL_DRV_OBJ_LOCK_FOREVER(pObj) (void)_SlDrvObjLockWaitForever(pObj); +#define SL_DRV_SYNC_OBJ_SIGNAL(pObj) (void)_SlDrvSyncObjSignal(pObj); +#define SL_DRV_SYNC_OBJ_CLEAR(pObj) (void)sl_SyncObjWait(pObj,SL_OS_NO_WAIT); + + +#ifdef SL_TINY +#define SL_DRV_SYNC_OBJ_WAIT_FOREVER(SyncObj) (void)_SlDrvSyncObjWaitForever(SyncObj); +#define SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(Flags) (void)_SlDrvObjGlobalLockWaitForever(Flags); +#define SL_DRV_LOCK_GLOBAL_UNLOCK(bDecrementApiInProgress) (void)_SlDrvGlobalObjUnLock(bDecrementApiInProgress); +#else +#define SL_DRV_SYNC_OBJ_WAIT_FOREVER(SyncObj) { \ +if (SL_API_ABORTED == _SlDrvSyncObjWaitForever(SyncObj)) \ +{ \ + return SL_API_ABORTED; \ +} \ +} +#define SL_DRV_SYNC_OBJ_WAIT_TIMEOUT(SyncObj, timeoutVal, opcode) { \ +if (SL_API_ABORTED == _SlDrvSyncObjWaitTimeout(SyncObj, timeoutVal, opcode)) \ +{ \ + return SL_API_ABORTED; \ +} \ +} +#define SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(Flags) { \ +_SlReturnVal_t retVal; \ + \ +retVal = _SlDrvObjGlobalLockWaitForever(Flags); \ +if (retVal) \ +{ \ + return retVal; \ +} \ +} + +#define SL_DRV_LOCK_GLOBAL_UNLOCK(bDecrementApiInProgress) { \ +_SlReturnVal_t retVal; \ + \ +retVal = _SlDrvGlobalObjUnLock(bDecrementApiInProgress); \ +if (retVal) \ +{ \ + return retVal; \ +} \ +} +#endif + +#define SL_IS_RESTART_REQUIRED (g_SlDeviceStatus & _SL_DRV_STATUS_BIT_RESTART_REQUIRED) /* bit 8 indicates restart is required due to fatal error */ +#define SL_IS_DEVICE_STARTED (g_SlDeviceStatus & _SL_DRV_STATUS_BIT_DEVICE_STARTED) /* bit 9 indicates device is started */ +#define SL_IS_DEVICE_LOCKED (g_SlDeviceStatus & _SL_DEV_STATUS_BIT_LOCKED) /* bits 0-7 devStatus from NWP, bit 2 = device locked */ +#define SL_IS_PROVISIONING_ACTIVE (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE)) /* bits 0-7 devStatus from NWP, bit 3 = provisioning active */ +#define SL_IS_PROVISIONING_INITIATED_BY_USER (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED)) /* bits 0-7 devStatus from NWP, bit 4 = provisioning initiated by the user */ +#define SL_IS_PROVISIONING_API_ALLOWED (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_ENABLE_API)) +#define SL_IS_DEVICE_STOP_IN_PROGRESS (!!(g_SlDeviceStatus & _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS)) +#define SL_IS_DEVICE_START_IN_PROGRESS (!!(g_SlDeviceStatus & _SL_DRV_STATUS_BIT_START_IN_PROGRESS)) + +#define SL_IS_PROVISIONING_IN_PROGRESS (!!(g_SlDeviceStatus & ( _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED | _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE))) +/* Check the following conditions: + 1. Device started + 2. Restart device is not required + 3. Provisioning is active + 4. Provisioning was already initiated by the user + 5. Device is not locked +*/ +#define SL_IS_COMMAND_ALLOWED ((g_SlDeviceStatus & (_SL_DRV_STATUS_BIT_DEVICE_STARTED | \ + _SL_DRV_STATUS_BIT_RESTART_REQUIRED | \ + _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE | \ + _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED | \ + _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS | \ + _SL_DEV_STATUS_BIT_LOCKED)) == 0x200) + +#define SL_SET_RESTART_REQUIRED (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_RESTART_REQUIRED) /* bit 8 indicates restart is required due to fatal error */ +#define SL_UNSET_RESTART_REQUIRED (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_RESTART_REQUIRED)) /* bit 8 indicates restart is required due to fatal error */ +#define SL_SET_DEVICE_STARTED (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_DEVICE_STARTED) /* bit 9 indicates device is started */ +#define SL_UNSET_DEVICE_STARTED (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_DEVICE_STARTED)) /* bit 9 indicates device is started */ + +#define SL_SET_DEVICE_STOP_IN_PROGRESS (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS) /* bit 10 indicates there is stop in progress */ +#define SL_UNSET_DEVICE_STOP_IN_PROGRESS (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_STOP_IN_PROGRESS)) /* bit 10 indicates there is stop in progress */ + +/* Start in progress */ +#define SL_SET_DEVICE_START_IN_PROGRESS (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_START_IN_PROGRESS) /* bit 11 indicates there is start in progress */ +#define SL_UNSET_DEVICE_START_IN_PROGRESS (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_START_IN_PROGRESS)) /* bit 11 indicates there is start in progress */ + + +#define SL_SET_DEVICE_STATUS(x) (g_SlDeviceStatus = ((g_SlDeviceStatus & 0xFF00) | (_u16)x) ) /* bits 0-7 devStatus from NWP */ + +#define _SL_PENDING_RX_MSG(pDriverCB) (RxIrqCnt != (pDriverCB)->RxDoneCnt) + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +typedef struct _SlSpawnMsgItem_s +{ + _SlSpawnEntryFunc_t AsyncHndlr; + _u8 ActionIndex; + void *Buffer; + struct _SlSpawnMsgItem_s *next; +} _SlSpawnMsgItem_t; + + +typedef struct +{ + _u32 TSPrev; + _u32 TSCurr; + _u32 DeltaTicks; + _u32 DeltaTicksReminder; + _i32 Total10MSecUnits; +} _SlTimeoutParams_t; + +typedef struct +{ + _u8 *pAsyncMsgBuff; + _u8 bInCmdContext; +} DeviceEventInfo_t; + +typedef struct +{ + _SlOpcode_t Opcode; + _SlArgSize_t TxDescLen; + _SlArgSize_t RxDescLen; +}_SlCmdCtrl_t; + +typedef struct +{ + _u16 TxPayload1Len; + _u16 TxPayload2Len; + _i16 RxPayloadLen; + _i16 ActualRxPayloadLen; + _u8 *pTxPayload1; + _u8 *pTxPayload2; + _u8 *pRxPayload; +}_SlCmdExt_t; + +typedef struct _SlArgsData_t +{ + _u8 *pArgs; + _u8 *pData; +} _SlArgsData_t; + +typedef struct _SlPoolObj_t +{ + _SlSyncObj_t SyncObj; + _u8 *pRespArgs; + _u8 ActionID; + _u8 AdditionalData; /* use for socketID and one bit which indicate supprt IPV6 or not (1=support, 0 otherwise) */ + _u8 NextIndex; +} _SlPoolObj_t; + +typedef enum +{ + SOCKET_0, + SOCKET_1, + SOCKET_2, + SOCKET_3, + SOCKET_4, + SOCKET_5, + SOCKET_6, + SOCKET_7, + SOCKET_8, + SOCKET_9, + SOCKET_10, + SOCKET_11, + SOCKET_12, + SOCKET_13, + SOCKET_14, + SOCKET_15, + MAX_SOCKET_ENUM_IDX, +#ifndef SL_TINY + ACCEPT_ID = MAX_SOCKET_ENUM_IDX, + CONNECT_ID, +#else + CONNECT_ID = MAX_SOCKET_ENUM_IDX, +#endif +#ifndef SL_TINY + SELECT_ID, +#endif + GETHOSYBYNAME_ID, +#ifndef SL_TINY + GETHOSYBYSERVICE_ID, + PING_ID, + NETAPP_RECEIVE_ID, +#endif + START_STOP_ID, + NETUTIL_CMD_ID, + CLOSE_ID, + START_TLS_ID, + /**********/ + RECV_ID /* Please note!! this member must be the last in this action enum */ +}_SlActionID_e; + +typedef struct _SlActionLookup_t +{ + _u8 ActionID; + _u16 ActionAsyncOpcode; + _SlSpawnEntryFunc_t AsyncEventHandler; + +} _SlActionLookup_t; + +typedef struct +{ + _u8 TxPoolCnt; + _u16 MinTxPayloadSize; + _SlLockObj_t TxLockObj; + _SlSyncObj_t TxSyncObj; +}_SlFlowContCB_t; + +typedef enum +{ + RECV_RESP_CLASS, + CMD_RESP_CLASS, + ASYNC_EVT_CLASS, +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + MULTI_SELECT_RESP_CLASS, +#endif + DUMMY_MSG_CLASS +}_SlRxMsgClass_e; + +typedef struct +{ + _u8 ActionIndex; + _SlSpawnEntryFunc_t AsyncEvtHandler; /* place to write pointer to AsyncEvent handler (calc-ed by Opcode) */ + _SlRxMsgClass_e RxMsgClass; /* type of Rx message */ +} AsyncExt_t; + +typedef _u8 _SlSd_t; + +typedef struct +{ + _SlCmdCtrl_t *pCmdCtrl; + _u8 *pTxRxDescBuff; + _SlCmdExt_t *pCmdExt; + AsyncExt_t AsyncExt; +}_SlFunctionParams_t; + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + +typedef struct SlSelectEntry_t +{ + SlSelectAsyncResponse_t Response; + _u32 TimeStamp; + _u16 readlist; + _u16 writelist; + _u8 ObjIdx; +}_SlSelectEntry_t; + +typedef struct _SlMultiSelectCB_t +{ + _u16 readsds; + _u16 writesds; + _u16 CtrlSockFD; + _u8 ActiveSelect; + _u8 ActiveWaiters; + _BasicResponse_t SelectCmdResp; + _SlSyncObj_t SelectSyncObj; + _SlLockObj_t SelectLockObj; + _SlSelectEntry_t* SelectEntry[MAX_CONCURRENT_ACTIONS]; +}_SlMultiSelectCB_t; + +#else + +typedef enum +{ + SOCK_TRIGGER_READY, + SOCK_TRIGGER_WAITING_FOR_RESP, + SOCK_TRIGGER_RESP_RECEIVED +} _SlSockTriggerState_e; + +typedef struct +{ + _SlSockTriggerState_e State; + _u8 ObjPoolIdx; +} _SlSockTriggerData_t; + +typedef struct +{ + _SlSockTriggerData_t Info; + SlSelectAsyncResponse_t Resp; +} _SlSockTriggerSelect_t; + +#endif + +typedef struct +{ + _SlFd_t FD; + _SlCommandHeader_t TempProtocolHeader; + P_INIT_CALLBACK pInitCallback; + + _SlPoolObj_t ObjPool[MAX_CONCURRENT_ACTIONS]; + _u8 FreePoolIdx; + _u8 PendingPoolIdx; + _u8 ActivePoolIdx; + _u32 ActiveActionsBitmap; + _SlLockObj_t ProtectionLockObj; + + _SlSyncObj_t CmdSyncObj; + _u8 WaitForCmdResp; + _SlFlowContCB_t FlowContCB; + _u8 TxSeqNum; + _u8 RxDoneCnt; + _u16 SocketNonBlocking; + _u16 SocketTXFailure; + /* for stack reduction the parameters are globals */ + _SlFunctionParams_t FunctionParams; + + _u8 ActionIndex; + _i8 ApiInProgressCnt; /* Counts how many APIs are in progress */ + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + /* Multiple Select Control block */ + _SlMultiSelectCB_t MultiSelectCB; +#endif + +#if defined(slcb_SocketTriggerEventHandler) + /* Trigger mode control block */ + _SlSockTriggerSelect_t SocketTriggerSelect; +#endif + +#ifdef SL_MEMORY_MGMT_DYNAMIC + _SlSpawnMsgItem_t *spawnMsgList; +#endif + _u8 NumOfDeletedSyncObj; +}_SlDriverCb_t; + +typedef struct +{ + _SlSpawnEntryFunc_t AsyncHndlr; + _u8 ActionIndex; + _u8 Buffer[SL_ASYNC_MAX_MSG_LEN]; +}_SlAsyncRespBuf_t; + +extern _volatile _u8 RxIrqCnt; + +extern _SlLockObj_t GlobalLockObj; +extern _u16 g_SlDeviceStatus; + +extern _SlDriverCb_t* g_pCB; +extern P_SL_DEV_PING_CALLBACK pPingCallBackFunc; + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ +extern _SlReturnVal_t _SlDrvDriverCBInit(void); +extern _SlReturnVal_t _SlDrvDriverCBDeinit(void); +extern _SlReturnVal_t _SlDrvRxIrqHandler(void *pValue); +extern _SlReturnVal_t _SlDrvCmdOp(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); +extern _SlReturnVal_t _SlDrvCmdSend_noLock(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); +extern _SlReturnVal_t _SlDrvCmdSend_noWait(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); +extern _SlReturnVal_t _SlDrvCmdSend(_SlCmdCtrl_t *pCmdCtrl , void *pTxRxDescBuff , _SlCmdExt_t *pCmdExt); +extern _SlReturnVal_t _SlDrvDataReadOp(_SlSd_t Sd, _SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); +extern _SlReturnVal_t _SlDrvDataWriteOp(_SlSd_t Sd, _SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); +extern _SlReturnVal_t _SlDeviceHandleAsync_InitComplete(void *pVoidBuf); +extern _SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf); +extern _SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf); +extern _SlReturnVal_t _SlDrvGlobalObjUnLock(_u8 bDecrementApiInProgress); +extern _SlReturnVal_t _SlDrvDriverIsApiAllowed(_u16 Silo); +extern _SlReturnVal_t _SlDrvMsgReadSpawnCtx(void *pValue); +extern void _SlInternalSpawnWaitForEvent(void); +extern void _SlDrvSetGlobalLockOwner(_u8 Owner); +extern _u8 _SlDrvIsSpawnOwnGlobalLock(); +#ifndef SL_TINY +extern _SlReturnVal_t _SlDrvBasicCmd(_SlOpcode_t Opcode); +extern _SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf); +extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf); +extern _SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf); +extern _SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf); +extern _SlReturnVal_t _SlDrvReleaseAllActivePendingPoolObj(); + +#ifdef slcb_GetTimestamp +extern void _SlDrvStartMeasureTimeout(_SlTimeoutParams_t *pTimeoutInfo, _u32 TimeoutInMsec); +extern _u8 _SlDrvIsTimeoutExpired(_SlTimeoutParams_t *pTimeoutInfo); +extern void _SlDrvSleep(_u16 DurationInMsec); +#endif + +#endif + +#if defined(SL_PLATFORM_MULTI_THREADED) +extern void * pthread_self(void); +#endif + +extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf); +extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByAddr(void *pVoidBuf); +extern _SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf); +extern _SlReturnVal_t _SlNetAppEventHandler(void* pArgs); + +#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) +extern void _SlDrvDispatchHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse); +#endif + +#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) +extern void _SlDrvDispatchNetAppRequestEvents(SlNetAppRequest_t *slNetAppRequestEvent, SlNetAppResponse_t *slNetAppResponse); +#endif + +extern void _SlDeviceHandleAsync_Stop(void *pVoidBuf); +extern void _SlNetUtilHandleAsync_Cmd(void *pVoidBuf); +extern _SlReturnVal_t _SlDrvWaitForPoolObj(_u8 ActionID, _u8 SocketID); +extern _SlReturnVal_t _SlDrvReleasePoolObj(_u8 pObj); +extern void _SlDrvReleaseAllPendingPoolObj(); +extern _SlReturnVal_t _SlDrvAlignSize(_u16 msgLen); +extern _SlReturnVal_t _SlDrvProtectAsyncRespSetting(_u8 *pAsyncRsp, _SlActionID_e ActionID, _u8 SocketID); +extern void _SlNetAppHandleAsync_NetAppReceive(void *pVoidBuf); + + +extern _SlReturnVal_t _SlDeviceEventHandler(void* pEventInfo); +extern _SlReturnVal_t _SlDrvSyncObjWaitForever(_SlSyncObj_t *pSyncObj); +extern _SlReturnVal_t _SlDrvObjLockWaitForever(_SlLockObj_t *pLockObj); +extern _SlReturnVal_t _SlDrvSyncObjWaitTimeout(_SlSyncObj_t *pSyncObj, + _u32 timeoutVal, + _u32 asyncEventOpcode); + +extern _SlReturnVal_t _SlDrvSyncObjSignal(_SlSyncObj_t *pSyncObj); +extern _SlReturnVal_t _SlDrvObjLock(_SlLockObj_t *pLockObj, _SlTime_t Timeout); +extern _SlReturnVal_t _SlDrvProtectionObjLockWaitForever(void); +extern _SlReturnVal_t _SlDrvObjUnLock(_SlLockObj_t *pLockObj); +extern _SlReturnVal_t _SlDrvProtectionObjUnLock(void); + +extern void _SlDrvMemZero(void* Addr, _u16 size); +extern void _SlDrvResetCmdExt(_SlCmdExt_t* pCmdExt); + +extern _i8 _SlDrvIsApiInProgress(void); +extern void _SlDrvHandleResetRequest(const void* pIfHdl, _i8* pDevName); +extern _SlReturnVal_t _SlDrvWaitForInternalAsyncEvent(_u8 ObjIdx, _u32 Timeout, _SlOpcode_t Opcode); +extern _SlReturnVal_t _SlSpawnMsgListInsert(_u16 AsyncEventLen, _u8 *pAsyncBuf); +extern _SlReturnVal_t _SlSpawnMsgListProcess(void); +extern _u16 _SlSpawnMsgListGetCount(void); +#ifndef SL_TINY +extern void _SlDrvHandleFatalError(_u32 errorId, _u32 info1, _u32 info2); +extern void _SlDrvHandleAssert(void); +extern void _SlFindAndReleasePendingCmd(); +#endif + +#define _SL_PROTOCOL_ALIGN_SIZE(msgLen) (((msgLen)+3) & (~3)) +#define _SL_IS_PROTOCOL_ALIGNED_SIZE(msgLen) (!((msgLen) & 3)) + + +#define _SL_PROTOCOL_CALC_LEN(pCmdCtrl,pCmdExt) ((pCmdExt) ? \ + (_SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen) + _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload1Len + pCmdExt->TxPayload2Len)) : \ + (_SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen))) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __DRIVER_INT_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.c new file mode 100755 index 00000000000..5bdf01552af --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.c @@ -0,0 +1,61 @@ +/* + * flowcont.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include + + +/*****************************************************************************/ +/* _SlDrvFlowContInit */ +/*****************************************************************************/ +void _SlFlowContSet(void *pVoidBuf) +{ + SlDeviceFlowCtrlAsyncEvent_t *pFlowCtrlAsyncEvent = (SlDeviceFlowCtrlAsyncEvent_t *)_SL_RESP_ARGS_START(pVoidBuf); + + if (pFlowCtrlAsyncEvent->MinTxPayloadSize != 0) + { + g_pCB->FlowContCB.MinTxPayloadSize = pFlowCtrlAsyncEvent->MinTxPayloadSize; + } + +} + + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.h new file mode 100755 index 00000000000..24670a6d4f5 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/flowcont.h @@ -0,0 +1,58 @@ +/* + * flowcont.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef __FLOWCONT_H__ +#define __FLOWCONT_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ +#define FLOW_CONT_MIN 2 + +extern void _SlFlowContSet(void *pVoidBuf); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __FLOWCONT_H__ */ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/fs.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/fs.c new file mode 100755 index 00000000000..368d5049161 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/fs.c @@ -0,0 +1,832 @@ +/* + * fs.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ +#define sl_min(a,b) (((a) < (b)) ? (a) : (b)) +#define MAX_NVMEM_CHUNK_SIZE 1456 /*should be 16 bytes align, because of encryption data*/ + +/*****************************************************************************/ +/* Internal functions */ +/*****************************************************************************/ + +#ifndef SL_TINY +static _u16 _SlFsStrlen(const _u8 *buffer); + +static _u32 FsGetCreateFsMode(_u8 Mode, _u32 MaxSizeInBytes,_u32 AccessFlags); + +/*****************************************************************************/ +/* _SlFsStrlen */ +/*****************************************************************************/ +static _u16 _SlFsStrlen(const _u8 *buffer) +{ + _u16 len = 0; + if( buffer != NULL ) + { + while(*buffer++) len++; + } + return len; +} +#endif +/*****************************************************************************/ +/* _SlFsGetCreateFsMode */ +/*****************************************************************************/ + +/* Convert the user flag to the file System flag */ +#define FS_CONVERT_FLAGS( ModeAndMaxSize ) (((_u32)ModeAndMaxSize & SL_FS_OPEN_FLAGS_BIT_MASK)>>SL_NUM_OF_MAXSIZE_BIT) + +typedef enum +{ + FS_MODE_OPEN_READ = 0, + FS_MODE_OPEN_WRITE, + FS_MODE_OPEN_CREATE, + FS_MODE_OPEN_WRITE_CREATE_IF_NOT_EXIST +}FsFileOpenAccessType_e; + +#define FS_MODE_ACCESS_RESERVED_OFFSET (27) +#define FS_MODE_ACCESS_RESERVED_MASK (0x1F) +#define FS_MODE_ACCESS_FLAGS_OFFSET (16) +#define FS_MODE_ACCESS_FLAGS_MASK (0x7FF) +#define FS_MODE_ACCESS_OFFSET (12) +#define FS_MODE_ACCESS_MASK (0xF) +#define FS_MODE_OPEN_SIZE_GRAN_OFFSET (8) +#define FS_MODE_OPEN_SIZE_GRAN_MASK (0xF) +#define FS_MODE_OPEN_SIZE_OFFSET (0) +#define FS_MODE_OPEN_SIZE_MASK (0xFF) +#define FS_MAX_MODE_SIZE (0xFF) + +/* SizeGran is up to 4 bit , Size can be up to 8 bit */ +#define FS_MODE(Access, SizeGran, Size,Flags) (_u32)(((_u32)((Access) &FS_MODE_ACCESS_MASK)<= MaxSizeInBytes ) + break; + } + granNum = MaxSizeInBytes/granTable[granIdx]; + if( MaxSizeInBytes % granTable[granIdx] != 0 ) + granNum++; + + return (_u32)FS_MODE( Mode, granIdx, granNum, AccessFlags ); + +} + +#endif + +/*****************************************************************************/ +/* API functions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* sl_FsOpen */ +/*****************************************************************************/ +typedef union +{ + SlFsOpenCommand_t Cmd; + SlFsOpenResponse_t Rsp; +}_SlFsOpenMsg_u; + +#if _SL_INCLUDE_FUNC(sl_FsOpen) + +static const _SlCmdCtrl_t _SlFsOpenCmdCtrl = +{ + SL_OPCODE_NVMEM_FILEOPEN, + (_SlArgSize_t)sizeof(SlFsOpenCommand_t), + (_SlArgSize_t)sizeof(SlFsOpenResponse_t) +}; + +_i32 sl_FsOpen(const _u8 *pFileName,const _u32 ModeAndMaxSize, _u32 *pToken) +{ + + _SlFsOpenMsg_u Msg; + _SlCmdExt_t CmdExt; + _i32 FileHandle; + _u32 MaxSizeInBytes; + _u32 OpenMode; + _u8 CreateMode; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); + + if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) + { + return SL_ERROR_FS_WRONG_FILE_NAME; + } + + CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ + CmdExt.pTxPayload1 = (_u8*)pFileName; + + OpenMode = ModeAndMaxSize & SL_FS_OPEN_MODE_BIT_MASK; + + /*convert from the interface flags to the device flags*/ + if( OpenMode == SL_FS_READ ) + { + Msg.Cmd.Mode = FS_MODE(FS_MODE_OPEN_READ, 0, 0, 0); + } + else if (( OpenMode == SL_FS_WRITE ) ||( OpenMode == SL_FS_OVERWRITE)) + { + Msg.Cmd.Mode = FS_MODE(FS_MODE_OPEN_WRITE, 0, 0, FS_CONVERT_FLAGS ( ModeAndMaxSize)); + } + /* one of the creation mode */ + else if ( ( OpenMode == (SL_FS_CREATE | SL_FS_OVERWRITE )) || ( OpenMode == SL_FS_CREATE) ||(OpenMode == (SL_FS_CREATE | SL_FS_WRITE ))) + { + /* test that the size is correct */ + MaxSizeInBytes = (ModeAndMaxSize & SL_FS_OPEN_MAXSIZE_BIT_MASK) * 256; + if (MaxSizeInBytes > 0xFF0000 ) + { + return SL_ERROR_FS_FILE_MAX_SIZE_EXCEEDED; + } + + CreateMode = ((OpenMode == (SL_FS_CREATE | SL_FS_OVERWRITE )) ? FS_MODE_OPEN_WRITE_CREATE_IF_NOT_EXIST : FS_MODE_OPEN_CREATE ); + + Msg.Cmd.Mode = FsGetCreateFsMode( CreateMode ,MaxSizeInBytes, FS_CONVERT_FLAGS ( ModeAndMaxSize) ); + } + else + { + return SL_ERROR_FS_INVALID_FILE_MODE; + } + + if(pToken != NULL) + { + Msg.Cmd.Token = *pToken; + } + else + { + Msg.Cmd.Token = 0; + } + + _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsOpenCmdCtrl, &Msg, &CmdExt); + FileHandle = (_i32)Msg.Rsp.FileHandle; + if (pToken != NULL) + { + *pToken = Msg.Rsp.Token; + } + + /* in case of an error, return the erros file handler as an error code */ + return FileHandle; +} +#endif + +/*****************************************************************************/ +/* sl_FsClose */ +/*****************************************************************************/ +typedef union +{ + SlFsCloseCommand_t Cmd; + _BasicResponse_t Rsp; +}_SlFsCloseMsg_u; + +#if _SL_INCLUDE_FUNC(sl_FsClose) + +static const _SlCmdCtrl_t _SlFsCloseCmdCtrl = +{ + SL_OPCODE_NVMEM_FILECLOSE, + (_SlArgSize_t)sizeof(SlFsCloseCommand_t), + (_SlArgSize_t)sizeof(SlFsCloseResponse_t) +}; + +_i16 sl_FsClose(const _i32 FileHdl, const _u8* pCeritificateFileName,const _u8* pSignature ,const _u32 SignatureLen) +{ + _SlFsCloseMsg_u Msg; + _SlCmdExt_t ExtCtrl; + + _SlDrvMemZero(&Msg, (_u16)sizeof(SlFsCloseCommand_t)); + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + Msg.Cmd.FileHandle = (_u32)FileHdl; + if( pCeritificateFileName != NULL ) + { + Msg.Cmd.CertificFileNameLength = (_u32)((_SlFsStrlen(pCeritificateFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ + } + Msg.Cmd.SignatureLen = SignatureLen; + + _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); + + ExtCtrl.TxPayload1Len = (_u16)(((SignatureLen+3) & (~3))); /* align */ + ExtCtrl.pTxPayload1 = (_u8*)pSignature; + ExtCtrl.RxPayloadLen = (_i16)Msg.Cmd.CertificFileNameLength; + ExtCtrl.pRxPayload = (_u8*)pCeritificateFileName; /* Add signature */ + + if(ExtCtrl.pRxPayload != NULL && ExtCtrl.RxPayloadLen != 0) + { + ExtCtrl.RxPayloadLen = ExtCtrl.RxPayloadLen * (-1); + } + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsCloseCmdCtrl, &Msg, &ExtCtrl)); + + return (_i16)((_i16)Msg.Rsp.status); +} +#endif + + +/*****************************************************************************/ +/* sl_FsRead */ +/*****************************************************************************/ +typedef union +{ + SlFsReadCommand_t Cmd; + SlFsReadResponse_t Rsp; +}_SlFsReadMsg_u; + +#if _SL_INCLUDE_FUNC(sl_FsRead) + +static const _SlCmdCtrl_t _SlFsReadCmdCtrl = +{ + SL_OPCODE_NVMEM_FILEREADCOMMAND, + (_SlArgSize_t)sizeof(SlFsReadCommand_t), + (_SlArgSize_t)sizeof(SlFsReadResponse_t) +}; + +_i32 sl_FsRead(const _i32 FileHdl,_u32 Offset, _u8* pData,_u32 Len) +{ + _SlFsReadMsg_u Msg; + _SlCmdExt_t ExtCtrl; + _u16 ChunkLen; + _SlReturnVal_t RetVal =0; + _i32 RetCount = 0; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); + + ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); + ExtCtrl.RxPayloadLen = (_i16)ChunkLen; + ExtCtrl.pRxPayload = (_u8 *)(pData); + Msg.Cmd.Offset = Offset; + Msg.Cmd.Len = ChunkLen; + Msg.Cmd.FileHandle = (_u32)FileHdl; + do + { + RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsReadCmdCtrl, &Msg, &ExtCtrl); + if(SL_OS_RET_CODE_OK == RetVal) + { + if( Msg.Rsp.status < 0) + { + if( RetCount > 0) + { + return RetCount; + } + else + { + return Msg.Rsp.status; + } + } + RetCount += (_i32)Msg.Rsp.status; + Len -= ChunkLen; + Offset += ChunkLen; + Msg.Cmd.Offset = Offset; + ExtCtrl.pRxPayload += ChunkLen; + ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); + ExtCtrl.RxPayloadLen = (_i16)ChunkLen; + Msg.Cmd.Len = ChunkLen; + Msg.Cmd.FileHandle = (_u32)FileHdl; + } + else + { + return RetVal; + } + }while(ChunkLen > 0); + + return (_i32)RetCount; +} +#endif + +/*****************************************************************************/ +/* sl_FsWrite */ +/*****************************************************************************/ +typedef union +{ + SlFsWriteCommand_t Cmd; + SlFsWriteResponse_t Rsp; +}_SlFsWriteMsg_u; + +#if _SL_INCLUDE_FUNC(sl_FsWrite) + +static const _SlCmdCtrl_t _SlFsWriteCmdCtrl = +{ + SL_OPCODE_NVMEM_FILEWRITECOMMAND, + (_SlArgSize_t)sizeof(SlFsWriteCommand_t), + (_SlArgSize_t)sizeof(SlFsWriteResponse_t) +}; + +_i32 sl_FsWrite(const _i32 FileHdl,_u32 Offset, _u8* pData,_u32 Len) +{ + _SlFsWriteMsg_u Msg; + _SlCmdExt_t ExtCtrl; + _u16 ChunkLen; + _SlReturnVal_t RetVal; + _i32 RetCount = 0; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); + + ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); + ExtCtrl.TxPayload1Len = ChunkLen; + ExtCtrl.pTxPayload1 = (_u8 *)(pData); + Msg.Cmd.Offset = Offset; + Msg.Cmd.Len = ChunkLen; + Msg.Cmd.FileHandle = (_u32)FileHdl; + + do + { + RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsWriteCmdCtrl, &Msg, &ExtCtrl); + if(SL_OS_RET_CODE_OK == RetVal) + { + if( Msg.Rsp.status < 0) + { + if( RetCount > 0) + { + return RetCount; + } + else + { + return Msg.Rsp.status; + } + } + + RetCount += (_i32)Msg.Rsp.status; + Len -= ChunkLen; + Offset += ChunkLen; + Msg.Cmd.Offset = Offset; + ExtCtrl.pTxPayload1 += ChunkLen; + ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); + ExtCtrl.TxPayload1Len = ChunkLen; + Msg.Cmd.Len = ChunkLen; + Msg.Cmd.FileHandle = (_u32)FileHdl; + } + else + { + return RetVal; + } + }while(ChunkLen > 0); + + return (_i32)RetCount; +} +#endif + +/*****************************************************************************/ +/* sl_FsGetInfo */ +/*****************************************************************************/ +typedef union +{ + SlFsGetInfoCommand_t Cmd; + SlFsGetInfoResponse_t Rsp; +}_SlFsGetInfoMsg_u; + +#if _SL_INCLUDE_FUNC(sl_FsGetInfo) + +static const _SlCmdCtrl_t _SlFsGetInfoCmdCtrl = +{ + SL_OPCODE_NVMEM_FILEGETINFOCOMMAND, + (_SlArgSize_t)sizeof(SlFsGetInfoCommand_t), + (_SlArgSize_t)sizeof(SlFsGetInfoResponse_t) +}; + +const _u16 FlagsTranslate[] = +{ + SL_FS_INFO_OPEN_WRITE, + SL_FS_INFO_OPEN_READ, + SL_FS_INFO_NOT_FAILSAFE, + SL_FS_INFO_NOT_VALID, + SL_FS_INFO_SYS_FILE, + SL_FS_INFO_MUST_COMMIT, + SL_FS_INFO_BUNDLE_FILE, + SL_FS_INFO_PENDING_COMMIT, + SL_FS_INFO_PENDING_BUNDLE_COMMIT, + 0, + SL_FS_INFO_SECURE, + SL_FS_INFO_NOSIGNATURE, + SL_FS_INFO_PUBLIC_WRITE, + SL_FS_INFO_PUBLIC_READ, + 0, + 0 +}; + +_i16 sl_FsGetInfo(const _u8 *pFileName,const _u32 Token,SlFsFileInfo_t* pFsFileInfo) +{ + _SlFsGetInfoMsg_u Msg; + _SlCmdExt_t CmdExt; + _u16 BitNum; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); + + if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) + { + return SL_ERROR_FS_WRONG_FILE_NAME; + } + + CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ + CmdExt.pTxPayload1 = (_u8*)pFileName; + + Msg.Cmd.Token = Token; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsGetInfoCmdCtrl, &Msg, &CmdExt)); + + /* convert flags */ + pFsFileInfo->Flags = 0; + for (BitNum = 0; BitNum < 16; BitNum++ ) + { + if (( Msg.Rsp.Flags >> BitNum) & 0x1 ) + { + pFsFileInfo->Flags |= FlagsTranslate[BitNum]; + } + } + + pFsFileInfo->Len = Msg.Rsp.FileLen; + pFsFileInfo->MaxSize = Msg.Rsp.AllocatedLen; + pFsFileInfo->Token[0] = Msg.Rsp.Token[0]; + pFsFileInfo->Token[1] = Msg.Rsp.Token[1]; + pFsFileInfo->Token[2] = Msg.Rsp.Token[2]; + pFsFileInfo->Token[3] = Msg.Rsp.Token[3]; + pFsFileInfo->StorageSize = Msg.Rsp.FileStorageSize; + pFsFileInfo->WriteCounter = Msg.Rsp.FileWriteCounter; + + return (_i16)((_i16)Msg.Rsp.Status); +} +#endif + +/*****************************************************************************/ +/* sl_FsDel */ +/*****************************************************************************/ +typedef union +{ + SlFsDeleteCommand_t Cmd; + SlFsDeleteResponse_t Rsp; +}_SlFsDeleteMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_FsDel) + +static const _SlCmdCtrl_t _SlFsDeleteCmdCtrl = +{ + SL_OPCODE_NVMEM_FILEDELCOMMAND, + (_SlArgSize_t)sizeof(SlFsDeleteCommand_t), + (_SlArgSize_t)sizeof(SlFsDeleteResponse_t) +}; + +_i16 sl_FsDel(const _u8 *pFileName,const _u32 Token) +{ + _SlFsDeleteMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) + { + return SL_ERROR_FS_WRONG_FILE_NAME; + } + + _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); + + CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ + CmdExt.pTxPayload1 = (_u8*)pFileName; + Msg.Cmd.Token = Token; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsDeleteCmdCtrl, &Msg, &CmdExt)); + + return (_i16)((_i16)Msg.Rsp.status); +} +#endif + +/*****************************************************************************/ +/* sl_FsCtl */ +/*****************************************************************************/ +typedef union +{ + SlFsFileSysControlCommand_t Cmd; + SlFsFileSysControlResponse_t Rsp; +}_SlFsFileSysControlMsg_u; + +#if _SL_INCLUDE_FUNC(sl_FsCtl) + +const _SlCmdCtrl_t _SlFsFileSysControlCmdCtrl = +{ + SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLCOMMAND, + sizeof(SlFsFileSysControlCommand_t), + sizeof(SlFsFileSysControlResponse_t) +}; + +_i32 sl_FsCtl( SlFsCtl_e Command, _u32 Token, _u8 *pFileName, const _u8 *pData, _u16 DataLen, _u8 *pOutputData, _u16 OutputDataLen,_u32 *pNewToken ) +{ + _SlFsFileSysControlMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + Msg.Cmd.Token = Token; + Msg.Cmd.Operation = (_u8)Command; + + _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); + + if ((SL_FS_CTL_ROLLBACK == Command) || (SL_FS_CTL_COMMIT == Command )) + { + Msg.Cmd.FileNameLength = _SlFsStrlen(pFileName) + 1 ; + + if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) + { + return SL_ERROR_FS_WRONG_FILE_NAME; + } + + /*the data is aligned*/ + CmdExt.RxPayloadLen = DataLen; + CmdExt.pRxPayload = (_u8 *)(pData); + + CmdExt.TxPayload1Len = (_SlFsStrlen(pFileName) + 4) & (~3); + CmdExt.pTxPayload1 = pFileName; + + Msg.Cmd.BufferLength = CmdExt.RxPayloadLen + CmdExt.TxPayload1Len; + + if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) + { + CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); + } + } + else if( SL_FS_CTL_RENAME == Command ) + { + if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) + { + return SL_ERROR_FS_WRONG_FILE_NAME; + } + + Msg.Cmd.FileNameLength = (_SlFsStrlen(pFileName) + 4) & (~3); + + /*current file name*/ + CmdExt.RxPayloadLen = (_u16)Msg.Cmd.FileNameLength; + CmdExt.pRxPayload = pFileName; + + /*New file name*/ + CmdExt.TxPayload1Len = (_SlFsStrlen(pData) + 4) & (~3);; + CmdExt.pTxPayload1 = (_u8 *)(pData); + + Msg.Cmd.BufferLength = CmdExt.RxPayloadLen + CmdExt.TxPayload1Len; + + if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) + { + CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); + } + } + else + { + Msg.Cmd.FileNameLength = 0; + + CmdExt.TxPayload1Len = (DataLen + 3) & (~3); + CmdExt.pTxPayload1 = (_u8 *)(pData); + + CmdExt.RxPayloadLen = OutputDataLen; + CmdExt.pRxPayload = pOutputData; + + Msg.Cmd.BufferLength = CmdExt.TxPayload1Len; + } + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsFileSysControlCmdCtrl, &Msg, &CmdExt)); + + if( pNewToken != NULL ) + { + *pNewToken = Msg.Rsp.Token; + } + + return (_i32)((_i32)Msg.Rsp.Status); +} +#endif + + +/*****************************************************************************/ +/* sl_FsProgram */ +/*****************************************************************************/ +typedef union +{ + SlFsProgramCommand_t Cmd; + SlFsProgramResponse_t Rsp; +}_SlFsProgrammingMsg_u; + +#if _SL_INCLUDE_FUNC(sl_FsProgram) + +const _SlCmdCtrl_t _SlFsProgrammingCmdCtrl = +{ + SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND, + sizeof(SlFsProgramCommand_t), + sizeof(SlFsProgramResponse_t) +}; + +_i32 sl_FsProgram(const _u8* pData , _u16 DataLen ,const _u8 * pKey , _u32 Flags ) +{ + _SlFsProgrammingMsg_u Msg; + _SlCmdExt_t CmdExt; + _u16 ChunkLen; + + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + Msg.Cmd.Flags = (_u32)Flags; + + _SlDrvResetCmdExt(&CmdExt); + + /* no data and no key, called only for extracting the image */ + if( (DataLen == 0) && (pKey == NULL) ) + { + Msg.Cmd.ChunkLen = 0; + Msg.Cmd.KeyLen = 0; + Msg.Cmd.Flags = Flags; + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); + } + else if( (DataLen> 0) && ( pData == NULL)) + { + //return( ((_i32)SL_ERROR_FS_WRONG_INPUT_SIZE) << 16 ); + // Remove warning + return (_i16)( ((_u32)SL_ERROR_FS_WRONG_INPUT_SIZE) << 16 ); + } + else if( (DataLen == 0) && (pKey != NULL) ) + { + Msg.Cmd.ChunkLen = 0; + Msg.Cmd.KeyLen = sizeof(SlFsKey_t);; + Msg.Cmd.Flags = Flags; + CmdExt.pTxPayload1 = (_u8*)pKey; + CmdExt.TxPayload1Len = sizeof(SlFsKey_t); + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); + } + else /* DataLen > 0 */ + { + if( (DataLen & 0xF) > 0) + { + return (_i32)(((_u32)SL_ERROR_FS_NOT_16_ALIGNED) << 16 ); + } + Msg.Cmd.Flags = Flags; + + CmdExt.pTxPayload1 = (_u8 *)pData; + ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE, DataLen); + + while(ChunkLen > 0) + { + Msg.Cmd.ChunkLen = ChunkLen; + CmdExt.TxPayload1Len = ChunkLen; + if( pKey != NULL ) + { + Msg.Cmd.KeyLen = sizeof(SlFsKey_t); + CmdExt.RxPayloadLen = sizeof(SlFsKey_t); + CmdExt.pRxPayload = (_u8 *)pKey; + + if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) + { + CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); + } + } + else /* No key */ + { + Msg.Cmd.KeyLen = 0; + CmdExt.RxPayloadLen = 0; + CmdExt.pRxPayload = NULL; + } + + VERIFY_RET_OK( _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); + + if( Msg.Rsp.Status <= 0 ) /* Error or finished */ + { + return (_i32)(Msg.Rsp.Status); + } + + DataLen -= ChunkLen; + CmdExt.pTxPayload1 += ChunkLen; + + ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE, DataLen); + } + } + + return (_i32)(Msg.Rsp.Status); +} +#endif + +/*****************************************************************************/ +/* sl_FsGetFileList */ +/*****************************************************************************/ +typedef union +{ + SlFsGetFileListCommand_t Cmd; + SlFsGetFileListResponse_t Rsp; +}_SlFsGetFileListMsg_u; + +#if _SL_INCLUDE_FUNC(sl_FsGetFileList) + +const _SlCmdCtrl_t _SlFsGetFileListCmdCtrl = +{ + SL_OPCODE_NVMEM_NVMEMGETFILELISTCOMMAND, + sizeof(SlFsGetFileListCommand_t), + sizeof(SlFsGetFileListResponse_t) +}; + +_i32 sl_FsGetFileList(_i32* pIndex, _u8 Count, _u8 MaxEntryLen , _u8* pBuff, SlFileListFlags_t Flags ) +{ + _SlFsGetFileListMsg_u Msg; + _SlCmdExt_t CmdExt; + _u16 OutputBufferSize; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); + + _SlDrvResetCmdExt(&CmdExt); + + Msg.Cmd.Index = *pIndex; + Msg.Cmd.MaxEntryLen = MaxEntryLen & (~3); /* round to modulu 4 */ + Msg.Cmd.Count = Count; + Msg.Cmd.Flags = (_u8)Flags; + + OutputBufferSize = Msg.Cmd.Count * Msg.Cmd.MaxEntryLen; + if( OutputBufferSize > MAX_NVMEM_CHUNK_SIZE ) + { + return SL_ERROR_FS_WRONG_INPUT_SIZE; + } + + CmdExt.RxPayloadLen = OutputBufferSize; + CmdExt.pRxPayload = pBuff; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsGetFileListCmdCtrl, &Msg, &CmdExt)); + + *pIndex = Msg.Rsp.Index; + + return (_i32)((_i32)Msg.Rsp.NumOfEntriesOrError); +} +#endif + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netapp.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netapp.c new file mode 100755 index 00000000000..78c404d6b6d --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netapp.c @@ -0,0 +1,1669 @@ +/* + * netapp.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Functions prototypes */ +/*****************************************************************************/ +_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf); + +#ifndef SL_TINY +_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf); +_SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf); +static void _SlNetAppCopyPingResultsToReport(SlPingReportResponse_t *pResults,SlNetAppPingReport_t *pReport); +#endif + +_i16 _SlNetAppMDNSRegisterUnregisterService(const _i8* pServiceName, + const _u8 ServiceNameLen, + const _i8* pText, + const _u8 TextLen, + const _u16 Port, + const _u32 TTL, + const _u32 Options); + + +_u16 _SlNetAppSendTokenValue(SlNetAppHttpServerData_t * Token); + +_u16 _SlNetAppSendResponse( _u16 handle, SlNetAppResponse_t *NetAppResponse); + +#define SL_NETAPP_SERVICE_SIZE_MASK (0x7) +#define SL_NETAPP_PING_GUARD_INTERVAL (20000) + +static _u16 NetAppServiceSizeLUT[] = +{ + (_u16)sizeof(_BasicResponse_t), /* 0 - Default value */ + (_u16)sizeof(SlNetAppGetFullServiceWithTextIpv4List_t), /* 1 - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE */ + (_u16)sizeof(SlNetAppGetFullServiceIpv4List_t), /* 2 - SL_NETAPP_FULL_SERVICE_IPV4_TYPE */ + (_u16)sizeof(SlNetAppGetShortServiceIpv4List_t), /* 3 - SL_NETAPP_SHORT_SERVICE_IPV4_TYPE */ + (_u16)sizeof(SlNetAppGetFullServiceWithTextIpv6List_t), /* 4 - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE */ + (_u16)sizeof(SlNetAppGetFullServiceIpv6List_t), /* 5 - SL_NETAPP_FULL_SERVICE_IPV6_TYPE */ + (_u16)sizeof(SlNetAppGetShortServiceIpv6List_t), /* 6 - SL_NETAPP_SHORT_SERVICE_IPV6_TYPE */ + (_u16)sizeof(_BasicResponse_t), /* 7 - Default value */ +}; + +typedef union +{ + _NetAppStartStopCommand_t Cmd; + _NetAppStartStopResponse_t Rsp; +}_SlNetAppStartStopMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_NetAppStart) + +static const _SlCmdCtrl_t _SlNetAppStartCtrl = +{ + SL_OPCODE_NETAPP_START_COMMAND, + (_SlArgSize_t)sizeof(_NetAppStartStopCommand_t), + (_SlArgSize_t)sizeof(_NetAppStartStopResponse_t) +}; + +_i16 sl_NetAppStart(const _u32 AppBitMap) +{ + _SlNetAppStartStopMsg_u Msg; + Msg.Cmd.AppId = AppBitMap; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppStartCtrl, &Msg, NULL)); + + return Msg.Rsp.status; +} +#endif + +/***************************************************************************** + sl_NetAppStop +*****************************************************************************/ +#if _SL_INCLUDE_FUNC(sl_NetAppStop) + +static const _SlCmdCtrl_t _SlNetAppStopCtrl = +{ + SL_OPCODE_NETAPP_STOP_COMMAND, + (_SlArgSize_t)sizeof(_NetAppStartStopCommand_t), + (_SlArgSize_t)sizeof(_NetAppStartStopResponse_t) +}; + +_i16 sl_NetAppStop(const _u32 AppBitMap) +{ + _SlNetAppStartStopMsg_u Msg; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + Msg.Cmd.AppId = AppBitMap; + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppStopCtrl, &Msg, NULL)); + + return Msg.Rsp.status; +} +#endif + + +/***************************************************************************** + sl_NetAppArpFlush +*****************************************************************************/ + +#if _SL_INCLUDE_FUNC(sl_NetAppArpFlush) + + +_i16 sl_NetAppArpFlush(void) +{ + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + return _SlDrvBasicCmd(SL_OPCODE_NETAPP_ARPFLUSH); +} +#endif + +/***************************************************************************** + sl_NetAppNdFlush +*****************************************************************************/ + +#if _SL_INCLUDE_FUNC(sl_NetAppNdFlush) + + +_i16 sl_NetAppNdFlush(void) +{ + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + return _SlDrvBasicCmd(SL_OPCODE_NETAPP_NDFLUSH_V6); +} +#endif + +/******************************************************************************/ +/* sl_NetAppGetServiceList */ +/******************************************************************************/ +typedef struct +{ + _u8 IndexOffest; + _u8 MaxServiceCount; + _u8 Flags; + _i8 Padding; +}NetappGetServiceListCMD_t; + +typedef union +{ + NetappGetServiceListCMD_t Cmd; + _BasicResponse_t Rsp; +}_SlNetappGetServiceListMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_NetAppGetServiceList) + +static const _SlCmdCtrl_t _SlGetServiceListeCtrl = +{ + SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE, + (_SlArgSize_t)sizeof(NetappGetServiceListCMD_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_i16 sl_NetAppGetServiceList(const _u8 IndexOffest, + const _u8 MaxServiceCount, + const _u8 Flags, + _i8 *pBuffer, + const _u32 BufferLength + ) +{ + + _i32 retVal= 0; + _SlNetappGetServiceListMsg_u Msg; + _SlCmdExt_t CmdExt; + _u16 ServiceSize = 0; + _u16 BufferSize = 0; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + /* + Calculate RX pBuffer size + WARNING: + if this size is BufferSize than 1480 error should be returned because there + is no place in the RX packet. + */ + ServiceSize = NetAppServiceSizeLUT[Flags & SL_NETAPP_SERVICE_SIZE_MASK]; + BufferSize = MaxServiceCount * ServiceSize; + + /* Check the size of the requested services is smaller than size of the user buffer. + If not an error is returned in order to avoid overwriting memory. */ + if(BufferLength < BufferSize) + { + return SL_ERROR_NET_APP_RX_BUFFER_LENGTH; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)BufferSize; + CmdExt.pRxPayload = (_u8 *)pBuffer; + + Msg.Cmd.IndexOffest = IndexOffest; + Msg.Cmd.MaxServiceCount = MaxServiceCount; + Msg.Cmd.Flags = Flags; + Msg.Cmd.Padding = 0; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetServiceListeCtrl, &Msg, &CmdExt)); + retVal = Msg.Rsp.status; + + return (_i16)retVal; +} + +#endif + +/*****************************************************************************/ +/* sl_mDNSRegisterService */ +/*****************************************************************************/ +/* + * The below struct depicts the constant parameters of the command/API RegisterService. + * + 1. ServiceLen - The length of the service should be smaller than SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. + 2. TextLen - The length of the text should be smaller than SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. + 3. port - The port on this target host. + 4. TTL - The TTL of the service + 5. Options - bitwise parameters: + bit 0 - is unique (means if the service needs to be unique) + bit 31 - for internal use if the service should be added or deleted (set means ADD). + bit 1-30 for future. + + NOTE: + + 1. There are another variable parameter is this API which is the service name and the text. + 2. According to now there is no warning and Async event to user on if the service is a unique. +* + */ + +typedef struct +{ + _u8 ServiceNameLen; + _u8 TextLen; + _u16 Port; + _u32 TTL; + _u32 Options; +}NetappMdnsSetService_t; + +typedef union +{ + NetappMdnsSetService_t Cmd; + _BasicResponse_t Rsp; +}_SlNetappMdnsRegisterServiceMsg_u; + +#if (_SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) || _SL_INCLUDE_FUNC(sl_NetAppMDNSUnregisterService)) + +static const _SlCmdCtrl_t _SlRegisterServiceCtrl = +{ + SL_OPCODE_NETAPP_MDNSREGISTERSERVICE, + (_SlArgSize_t)sizeof(NetappMdnsSetService_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +/****************************************************************************** + + sl_NetAppMDNSRegisterService + + CALLER user from its host + + + DESCRIPTION: + Add/delete service + The function manipulates the command that register the service and call + to the NWP in order to add/delete the service to/from the mDNS package and to/from the DB. + + This register service is a service offered by the application. + This unregister service is a service offered by the application before. + + The service name should be full service name according to RFC + of the DNS-SD - means the value in name field in SRV answer. + + Example for service name: + 1. PC1._ipp._tcp.local + 2. PC2_server._ftp._tcp.local + + If the option is_unique is set, mDNS probes the service name to make sure + it is unique before starting to announce the service on the network. + Instance is the instance portion of the service name. + + + + + PARAMETERS: + + The command is from constant parameters and variables parameters. + + Constant parameters are: + + ServiceLen - The length of the service. + TextLen - The length of the service should be smaller than 64. + port - The port on this target host. + TTL - The TTL of the service + Options - bitwise parameters: + bit 0 - is unique (means if the service needs to be unique) + bit 31 - for internal use if the service should be added or deleted (set means ADD). + bit 1-30 for future. + + The variables parameters are: + + Service name(full service name) - The service name. + Example for service name: + 1. PC1._ipp._tcp.local + 2. PC2_server._ftp._tcp.local + + Text - The description of the service. + should be as mentioned in the RFC + (according to type of the service IPP,FTP...) + + NOTE - pay attention + + 1. Temporary - there is an allocation on stack of internal buffer. + Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. + It means that the sum of the text length and service name length cannot be bigger than + SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. + If it is - An error is returned. + + 2. According to now from certain constraints the variables parameters are set in the + attribute part (contain constant parameters) + + + + RETURNS: Status - the immediate response of the command status. + 0 means success. + +******************************************************************************/ +_i16 _SlNetAppMDNSRegisterUnregisterService(const _i8* pServiceName, + const _u8 ServiceNameLen, + const _i8* pText, + const _u8 TextLen, + const _u16 Port, + const _u32 TTL, + const _u32 Options) +{ + _SlNetappMdnsRegisterServiceMsg_u Msg; + _SlCmdExt_t CmdExt ; + _i8 ServiceNameAndTextBuffer[SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH]; + _i8 *TextPtr; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + /* + + NOTE - pay attention + + 1. Temporary - there is an allocation on stack of internal buffer. + Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. + It means that the sum of the text length and service name length cannot be bigger than + SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. + If it is - An error is returned. + + 2. According to now from certain constraints the variables parameters are set in the + attribute part (contain constant parameters) + + */ + + /*build the attribute part of the command. + It contains the constant parameters of the command*/ + + Msg.Cmd.ServiceNameLen = ServiceNameLen; + Msg.Cmd.Options = Options; + Msg.Cmd.Port = Port; + Msg.Cmd.TextLen = TextLen; + Msg.Cmd.TTL = TTL; + + /*Build the payload part of the command + Copy the service name and text to one buffer. + NOTE - pay attention + The size of the service length + the text length should be smaller than 255, + Until the simplelink drive supports to variable length through SPI command. */ + if(TextLen + ServiceNameLen > (SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH - 1 )) /*-1 is for giving a place to set null termination at the end of the text*/ + { + return -1; + } + + _SlDrvMemZero(ServiceNameAndTextBuffer, (_u16)SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH); + + /*Copy the service name*/ + sl_Memcpy(ServiceNameAndTextBuffer, + pServiceName, + ServiceNameLen); + + if(TextLen > 0 ) + { + TextPtr = &ServiceNameAndTextBuffer[ServiceNameLen]; + /*Copy the text just after the service name*/ + sl_Memcpy(TextPtr, + pText, + TextLen); + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = (TextLen + ServiceNameLen); + CmdExt.pTxPayload1 = (_u8 *)ServiceNameAndTextBuffer; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlRegisterServiceCtrl, &Msg, &CmdExt)); + + return (_i16)Msg.Rsp.status; +} +#endif + +/**********************************************************************************************/ +#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) + +_i16 sl_NetAppMDNSRegisterService(const _i8* pServiceName, + const _u8 ServiceNameLen, + const _i8* pText, + const _u8 TextLen, + const _u16 Port, + const _u32 TTL, + _u32 Options) +{ + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + /* + + NOTE - pay attention + + 1. Temporary - there is an allocation on stack of internal buffer. + Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. + It means that the sum of the text length and service name length cannot be bigger than + SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. + If it is - An error is returned. + + 2. According to now from certain constraints the variables parameters are set in the + attribute part (contain constant parameters) + + */ + + /*Set the add service bit in the options parameter. + In order not use different opcodes for the register service and unregister service + bit 31 in option is taken for this purpose. if it is set it means in NWP that the service should be added + if it is cleared it means that the service should be deleted and there is only meaning to pServiceName + and ServiceNameLen values. */ + Options |= SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT; + + return _SlNetAppMDNSRegisterUnregisterService(pServiceName, + ServiceNameLen, + pText, + TextLen, + Port, + TTL, + Options); +} +#endif +/**********************************************************************************************/ + + +/**********************************************************************************************/ +#if _SL_INCLUDE_FUNC(sl_NetAppMDNSUnRegisterService) + +_i16 sl_NetAppMDNSUnRegisterService(const _i8* pServiceName, + const _u8 ServiceNameLen,_u32 Options) +{ + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + /* + + NOTE - pay attention + + The size of the service length should be smaller than 255, + Until the simplelink drive supports to variable length through SPI command. + + + */ + + /*Clear the add service bit in the options parameter. + In order not use different opcodes for the register service and unregister service + bit 31 in option is taken for this purpose. if it is set it means in NWP that the service should be added + if it is cleared it means that the service should be deleted and there is only meaning to pServiceName + and ServiceNameLen values.*/ + + Options &= (~SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT); + + return _SlNetAppMDNSRegisterUnregisterService( pServiceName, + ServiceNameLen, + NULL, + 0, + 0, + 0, + Options); + + +} +#endif +/**********************************************************************************************/ + + +/*****************************************************************************/ +/* sl_DnsGetHostByService */ +/*****************************************************************************/ +/* + * The below struct depicts the constant parameters of the command/API sl_DnsGetHostByService. + * + 1. ServiceLen - The length of the service should be smaller than 255. + 2. AddrLen - TIPv4 or IPv6 (SL_AF_INET , SL_AF_INET6). +* + */ + +typedef struct +{ + _u8 ServiceLen; + _u8 AddrLen; + _u16 Padding; +}_GetHostByServiceCommand_t; + +/* + * The below structure depict the constant parameters that are returned in the Async event answer + * according to command/API sl_DnsGetHostByService for IPv4 and IPv6. + * + 1Status - The status of the response. + 2.Address - Contains the IP address of the service. + 3.Port - Contains the port of the service. + 4.TextLen - Contains the max length of the text that the user wants to get. + it means that if the test of service is bigger that its value than + the text is cut to inout_TextLen value. + Output: Contain the length of the text that is returned. Can be full text or part + of the text (see above). +* +*/ + +typedef struct +{ + _u16 Status; + _u16 TextLen; + _u32 Port; + _u32 Address[4]; +}_GetHostByServiceIPv6AsyncResponse_t; + +/* + * The below struct contains pointers to the output parameters that the user gives + * + */ +typedef struct +{ + _i16 Status; + _u32 *out_pAddr; + _u32 *out_pPort; + _u16 *inout_TextLen; /* in: max len , out: actual len */ + _i8 *out_pText; +}_GetHostByServiceAsyncResponse_t; + +typedef union +{ + _GetHostByServiceCommand_t Cmd; + _BasicResponse_t Rsp; +}_SlGetHostByServiceMsg_u; + +#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByService) + +static const _SlCmdCtrl_t _SlGetHostByServiceCtrl = +{ + SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICE, + (_SlArgSize_t)sizeof(_GetHostByServiceCommand_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +/******************************************************************************/ + +_i16 sl_NetAppDnsGetHostByService(_i8 *pServiceName, /* string containing all (or only part): name + subtype + service */ + const _u8 ServiceLen, + const _u8 Family, /* 4-IPv4 , 16-IPv6 */ + _u32 pAddr[], + _u32 *pPort, + _u16 *pTextLen, /* in: max len , out: actual len */ + _i8 *pText + ) +{ + _SlGetHostByServiceMsg_u Msg; + _SlCmdExt_t CmdExt ; + _GetHostByServiceAsyncResponse_t AsyncRsp; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + _SlDrvMemZero(&AsyncRsp, sizeof(_GetHostByServiceAsyncResponse_t)); + +/* + Note: + 1. The return's attributes are belonged to first service that is found. + It can be other services with the same service name will response to + the query. The results of these responses are saved in the peer cache of the NWP, and + should be read by another API. + + 2. Text length can be 120 bytes only - not more + It is because of constraints in the NWP on the buffer that is allocated for the Async event. + + 3.The API waits to Async event by blocking. It means that the API is finished only after an Async event + is sent by the NWP. + + 4.No rolling option!!! - only PTR type is sent. + +*/ + /*build the attribute part of the command. + It contains the constant parameters of the command */ + + Msg.Cmd.ServiceLen = ServiceLen; + Msg.Cmd.AddrLen = Family; + + /*Build the payload part of the command + Copy the service name and text to one buffer.*/ + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = ServiceLen; + CmdExt.pTxPayload1 = (_u8 *)pServiceName; + + /*set pointers to the output parameters (the returned parameters). + This pointers are belonged to local struct that is set to global Async response parameter. + It is done in order not to run more than one sl_DnsGetHostByService at the same time. + The API should be run only if global parameter is pointed to NULL. */ + AsyncRsp.out_pText = pText; + AsyncRsp.inout_TextLen = (_u16* )pTextLen; + AsyncRsp.out_pPort = pPort; + AsyncRsp.out_pAddr = (_u32 *)&pAddr[0]; + + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, GETHOSYBYSERVICE_ID, SL_MAX_SOCKETS); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + if (SL_AF_INET6 == Family) + { + g_pCB->ObjPool[ObjIdx].AdditionalData |= SL_NETAPP_FAMILY_MASK; + } + /* Send the command */ + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetHostByServiceCtrl, &Msg, &CmdExt)); + + /* If the immediate reponse is O.K. than wait for aSYNC event response. */ + if(SL_RET_CODE_OK == Msg.Rsp.status) + { + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); + + /* If we are - it means that Async event was sent. + The results are copied in the Async handle return functions */ + + Msg.Rsp.status = AsyncRsp.Status; + } + + _SlDrvReleasePoolObj(ObjIdx); + return Msg.Rsp.status; +} +#endif + +/******************************************************************************/ + +/****************************************************************************** + _SlNetAppHandleAsync_DnsGetHostByService + + CALLER NWP - Async event on sl_DnsGetHostByService with IPv4 Family + + + DESCRIPTION: + + Async event on sl_DnsGetHostByService command with IPv4 Family. + Return service attributes like IP address, port and text according to service name. + The user sets a service name Full/Part (see example below), and should get the: + 1. IP of the service + 2. The port of service. + 3. The text of service. + + Hence it can make a connection to the specific service and use it. + It is similar to get host by name method. + + It is done by a single shot query with PTR type on the service name. + + + + Note: + 1. The return's attributes are belonged to first service that is found. + It can be other services with the same service name will response to + the query. The results of these responses are saved in the peer cache of the NWP, and + should be read by another API. + + + PARAMETERS: + + pVoidBuf - is point to opcode of the event. + it contains the outputs that are given to the user + + outputs description: + + 1.out_pAddr[] - output: Contain the IP address of the service. + 2.out_pPort - output: Contain the port of the service. + 3.inout_TextLen - Input: Contain the max length of the text that the user wants to get. + it means that if the test of service is bigger that its value than + the text is cut to inout_TextLen value. + Output: Contain the length of the text that is returned. Can be full text or part + of the text (see above). + + 4.out_pText - Contain the text of the service (full or part see above- inout_TextLen description). + + * + + + RETURNS: success or fail. + +******************************************************************************/ +#ifndef SL_TINY +_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf) +{ + _u16 TextLen; + _u16 UserTextLen; + _GetHostByServiceAsyncResponse_t* Res= NULL; + _GetHostByServiceIPv6AsyncResponse_t *pMsgArgs = (_GetHostByServiceIPv6AsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); + + VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); + /*Res pointed to mDNS global object struct */ + Res = (_GetHostByServiceAsyncResponse_t*)g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs; + /*IPv6*/ + if(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) + { + Res->out_pAddr[1] = pMsgArgs->Address[1]; /* Copy data from IPv6 address to Host user's pAddr. The array must be at least 4 cells of _u32 */ + Res->out_pAddr[2] = pMsgArgs->Address[2]; + Res->out_pAddr[3] = pMsgArgs->Address[3]; + } + + TextLen = pMsgArgs->TextLen; + + /*It is 4 bytes so we avoid from memcpy*/ + Res->out_pAddr[0] = pMsgArgs->Address[0]; /* Copy first cell data from IPv4/6 address to Host user's pAddr */ + Res->out_pPort[0] = pMsgArgs->Port; + Res->Status = (_i16)pMsgArgs->Status; + /*set to TextLen the text length of the user (input fromthe user).*/ + UserTextLen = Res->inout_TextLen[0]; + + /*Cut the service text if the user requested for smaller text.*/ + UserTextLen = (TextLen <= UserTextLen) ? TextLen : UserTextLen; + Res->inout_TextLen[0] = UserTextLen ; + + /************************************************************************************************** + + 2. Copy the payload part of the evnt (the text) to the payload part of the response + the lenght of the copy is according to the text length in the attribute part. */ + + /*IPv6*/ + if (g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) + { + sl_Memcpy(Res->out_pText, + (_i8 *)(& pMsgArgs[1]), /* & pMsgArgs[1] -> 1st byte after the fixed header = 1st byte of variable text.*/ + UserTextLen); + } + else + { + sl_Memcpy(Res->out_pText, + (_i8 *)(& pMsgArgs->Address[1]), /* & pMsgArgs[1] -> 1st byte after the fixed header = 1st byte of variable text.*/ + UserTextLen); + } + + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + + return SL_OS_RET_CODE_OK; +} + +/*****************************************************************************/ +/* _SlNetAppHandleAsync_DnsGetHostByAddr */ +/*****************************************************************************/ +_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByAddr(void *pVoidBuf) +{ + SL_TRACE0(DBG_MSG, MSG_303, "STUB: _SlNetAppHandleAsync_DnsGetHostByAddr not implemented yet!"); + return SL_OS_RET_CODE_OK; +} +#endif + +/*****************************************************************************/ +/* sl_DnsGetHostByName */ +/*****************************************************************************/ +typedef union +{ + NetAppGetHostByNameIPv4AsyncResponse_t IpV4; + NetAppGetHostByNameIPv6AsyncResponse_t IpV6; +}_GetHostByNameAsyncResponse_u; + +typedef union +{ + NetAppGetHostByNameCommand_t Cmd; + _BasicResponse_t Rsp; +}_SlGetHostByNameMsg_u; + +#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByName) +static const _SlCmdCtrl_t _SlGetHostByNameCtrl = +{ + SL_OPCODE_NETAPP_DNSGETHOSTBYNAME, + (_SlArgSize_t)sizeof(NetAppGetHostByNameCommand_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_i16 sl_NetAppDnsGetHostByName(_i8 * pHostName,const _u16 NameLen, _u32* OutIpAddr,const _u8 Family ) +{ + _SlGetHostByNameMsg_u Msg; + _SlCmdExt_t ExtCtrl; + _GetHostByNameAsyncResponse_u AsyncRsp; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + _SlDrvResetCmdExt(&ExtCtrl); + ExtCtrl.TxPayload1Len = NameLen; + ExtCtrl.pTxPayload1 = (_u8 *)pHostName; + + Msg.Cmd.Len = NameLen; + Msg.Cmd.Family = Family; + + /*Use Obj to issue the command, if not available try later */ + ObjIdx = _SlDrvWaitForPoolObj(GETHOSYBYNAME_ID,SL_MAX_SOCKETS); + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) + { + return SL_RET_CODE_STOP_IN_PROGRESS; + } + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp; + /*set bit to indicate IPv6 address is expected */ + if (SL_AF_INET6 == Family) + { + g_pCB->ObjPool[ObjIdx].AdditionalData |= SL_NETAPP_FAMILY_MASK; + } + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetHostByNameCtrl, &Msg, &ExtCtrl)); + + if(SL_RET_CODE_OK == Msg.Rsp.status) + { + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); + + Msg.Rsp.status = (_i16)AsyncRsp.IpV4.Status; + + if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) + { + sl_Memcpy((_i8 *)OutIpAddr, + (_i8 *)&AsyncRsp.IpV4.Ip0, + (SL_AF_INET == Family) ? SL_IPV4_ADDRESS_SIZE : SL_IPV6_ADDRESS_SIZE); + } + } + _SlDrvReleasePoolObj(ObjIdx); + return Msg.Rsp.status; +} +#endif + + +/******************************************************************************/ +/* _SlNetAppHandleAsync_DnsGetHostByName */ +/******************************************************************************/ +_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf) +{ + NetAppGetHostByNameIPv4AsyncResponse_t *pMsgArgs = (NetAppGetHostByNameIPv4AsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); + + /*IPv6 */ + if(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) + { + sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(NetAppGetHostByNameIPv6AsyncResponse_t)); + } + /*IPv4 */ + else + { + sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(NetAppGetHostByNameIPv4AsyncResponse_t)); + } + + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return SL_OS_RET_CODE_OK; +} + +#ifndef SL_TINY +static void _SlNetAppCopyPingResultsToReport(SlPingReportResponse_t *pResults,SlNetAppPingReport_t *pReport) +{ + pReport->PacketsSent = pResults->NumSendsPings; + pReport->PacketsReceived = pResults->NumSuccsessPings; + pReport->MinRoundTime = pResults->RttMin; + pReport->MaxRoundTime = pResults->RttMax; + pReport->AvgRoundTime = pResults->RttAvg; + pReport->TestTime = pResults->TestTime; +} + +/*****************************************************************************/ +/* _SlNetAppHandleAsync_PingResponse */ +/*****************************************************************************/ +_SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf) +{ + SlPingReportResponse_t *pMsgArgs = (SlPingReportResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); + SlNetAppPingReport_t pingReport; + + if(pPingCallBackFunc) + { + _SlNetAppCopyPingResultsToReport(pMsgArgs,&pingReport); + pPingCallBackFunc(&pingReport); + } + else + { + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + VERIFY_SOCKET_CB(NULL != g_pCB->PingCB.PingAsync.pAsyncRsp); + + if (NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs) + { + sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(SlPingReportResponse_t)); + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + } + SL_DRV_PROTECTION_OBJ_UNLOCK(); + } + + return SL_OS_RET_CODE_OK; +} +#endif + +/*****************************************************************************/ +/* sl_NetAppPing */ +/*****************************************************************************/ +typedef union +{ + SlNetAppPingCommand_t Cmd; + SlPingReportResponse_t Rsp; +}_SlPingStartMsg_u; + +typedef enum +{ + CMD_PING_TEST_RUNNING = 0, + CMD_PING_TEST_STOPPED +}_SlPingStatus_e; + +#if _SL_INCLUDE_FUNC(sl_NetAppPing) +_i16 sl_NetAppPing(const SlNetAppPingCommand_t* pPingParams, const _u8 Family, SlNetAppPingReport_t *pReport, const P_SL_DEV_PING_CALLBACK pPingCallback) +{ + _SlCmdCtrl_t CmdCtrl = {0, (_SlArgSize_t)sizeof(SlNetAppPingCommand_t), (_SlArgSize_t)sizeof(_BasicResponse_t)}; + _SlPingStartMsg_u Msg; + SlPingReportResponse_t PingRsp; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + _u32 PingTimeout = 0; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + if(NULL != pPingParams) + { + if(SL_AF_INET == Family) + { + CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART; + sl_Memcpy(&Msg.Cmd.Ip, &pPingParams->Ip, SL_IPV4_ADDRESS_SIZE); + } + else + { + CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART_V6; + sl_Memcpy(&Msg.Cmd.Ip, &pPingParams->Ip, SL_IPV6_ADDRESS_SIZE); + } + + Msg.Cmd.PingIntervalTime = pPingParams->PingIntervalTime; + Msg.Cmd.PingSize = pPingParams->PingSize; + Msg.Cmd.PingRequestTimeout = pPingParams->PingRequestTimeout; + Msg.Cmd.TotalNumberOfAttempts = pPingParams->TotalNumberOfAttempts; + Msg.Cmd.Flags = pPingParams->Flags; + + + /* calculate the ping timeout according to the parmas + the guard interval */ + PingTimeout = SL_NETAPP_PING_GUARD_INTERVAL + (pPingParams->PingIntervalTime * pPingParams->TotalNumberOfAttempts); + + if (Msg.Cmd.Ip != 0) + { + /* If the following conditions are met, return an error + Wrong ping parameters - ping cannot be called with the following parameters: + 1. infinite ping packet + 2. report only when finished + 3. no callback supplied */ + if ((pPingCallback == NULL) && (pPingParams->Flags == 0) && (pPingParams->TotalNumberOfAttempts == 0)) + { + return SL_RET_CODE_NET_APP_PING_INVALID_PARAMS; + } + + if( pPingCallback ) + { + pPingCallBackFunc = pPingCallback; + } + else + { + /* Use Obj to issue the command, if not available try later */ + ObjIdx = _SlDrvWaitForPoolObj(PING_ID,SL_MAX_SOCKETS); + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) + { + return SL_RET_CODE_STOP_IN_PROGRESS; + } + OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER)); + /* async response handler for non callback mode */ + g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&PingRsp; + pPingCallBackFunc = NULL; + OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj)); + } + } + } + /* Issue Stop Command */ + else + { + CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART; + Msg.Cmd.Ip = 0; + } + /* send the command */ + VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); + if (Msg.Cmd.Ip != 0) + { + if(CMD_PING_TEST_RUNNING == (_i16)Msg.Rsp.Status || CMD_PING_TEST_STOPPED == (_i16)Msg.Rsp.Status ) + { + /* block waiting for results if no callback function is used */ + if( NULL == pPingCallback ) + { +#ifdef SL_TINY + _SlDrvSyncObjWaitForever(&g_pCB->ObjPool[ObjIdx].SyncObj); +#else + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, PingTimeout, SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE)); +#endif + + if( SL_OS_RET_CODE_OK == (_i16)PingRsp.Status ) + { + _SlNetAppCopyPingResultsToReport(&PingRsp,pReport); + } + _SlDrvReleasePoolObj(ObjIdx); + } + } + else + { /* ping failure, no async response */ + if( NULL == pPingCallback ) + { + _SlDrvReleasePoolObj(ObjIdx); + } + } + } + return (_i16)Msg.Rsp.Status; +} +#endif + +/*****************************************************************************/ +/* sl_NetAppSet */ +/*****************************************************************************/ +typedef union +{ + SlNetAppSetGet_t Cmd; + _BasicResponse_t Rsp; +}_SlNetAppMsgSet_u; + +#if _SL_INCLUDE_FUNC(sl_NetAppSet) + +static const _SlCmdCtrl_t _SlNetAppSetCmdCtrl = +{ + SL_OPCODE_NETAPP_NETAPPSET, + (_SlArgSize_t)sizeof(SlNetAppSetGet_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_i16 sl_NetAppSet(const _u8 AppId ,const _u8 Option, const _u8 OptionLen, const _u8 *pOptionValue) +{ + _SlNetAppMsgSet_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = (OptionLen+3) & (~3); + CmdExt.pTxPayload1 = (_u8 *)pOptionValue; + + Msg.Cmd.AppId = AppId; + Msg.Cmd.ConfigLen = OptionLen; + Msg.Cmd.ConfigOpt = Option; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppSetCmdCtrl, &Msg, &CmdExt)); + + return (_i16)Msg.Rsp.status; +} +#endif + +/*****************************************************************************/ +/* sl_NetAppSendTokenValue */ +/*****************************************************************************/ +typedef union +{ + SlNetAppHttpServerSendToken_t Cmd; + _BasicResponse_t Rsp; +}_SlNetAppMsgSendTokenValue_u; + +const _SlCmdCtrl_t _SlNetAppSendTokenValueCmdCtrl = +{ + SL_OPCODE_NETAPP_HTTPSENDTOKENVALUE, + (_SlArgSize_t)sizeof(SlNetAppHttpServerSendToken_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_u16 _SlNetAppSendTokenValue(SlNetAppHttpServerData_t * Token_value) +{ + _SlNetAppMsgSendTokenValue_u Msg; + _SlCmdExt_t CmdExt; + + _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); + + CmdExt.TxPayload1Len = (Token_value->ValueLen+3) & (~3); + CmdExt.pTxPayload1 = (_u8 *) Token_value->pTokenValue; + + Msg.Cmd.TokenValueLen = Token_value->ValueLen; + Msg.Cmd.TokenNameLen = Token_value->NameLen; + sl_Memcpy(&Msg.Cmd.TokenName[0], Token_value->pTokenName, Token_value->NameLen); + + VERIFY_RET_OK(_SlDrvCmdSend_noLock((_SlCmdCtrl_t *)&_SlNetAppSendTokenValueCmdCtrl, &Msg, &CmdExt)); + + return Msg.Rsp.status; +} + +/*****************************************************************************/ +/* sl_NetAppSendResponse */ +/*****************************************************************************/ +#ifndef SL_TINY +typedef union +{ + SlProtocolNetAppResponse_t Cmd; + _BasicResponse_t Rsp; +}_SlNetAppMsgSendResponse_u; + +const _SlCmdCtrl_t _SlNetAppSendResponseCmdCtrl = +{ + SL_OPCODE_NETAPP_RESPONSE, + sizeof(SlProtocolNetAppResponse_t), + sizeof(_BasicResponse_t) +}; + +_u16 _SlNetAppSendResponse( _u16 handle, SlNetAppResponse_t *NetAppResponse) +{ + _SlNetAppMsgSendResponse_u Msg; + _SlCmdExt_t CmdExt; + _SlReturnVal_t RetVal; + _u16 dataLen; + + _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); + + dataLen = NetAppResponse->ResponseData.MetadataLen + NetAppResponse->ResponseData.PayloadLen; + + if ((NetAppResponse->ResponseData.MetadataLen <= SL_NETAPP_REQUEST_MAX_METADATA_LEN) && (dataLen <= SL_NETAPP_REQUEST_MAX_DATA_LEN)) + { + if (dataLen > 0) + { + /* Zero copy of the two parts: metadata + payload */ + CmdExt.pTxPayload1 = NetAppResponse->ResponseData.pMetadata; + CmdExt.TxPayload1Len = NetAppResponse->ResponseData.MetadataLen; + + CmdExt.pTxPayload2 = NetAppResponse->ResponseData.pPayload; + CmdExt.TxPayload2Len = NetAppResponse->ResponseData.PayloadLen; + } + else + { + CmdExt.pTxPayload1 = NULL; + CmdExt.pTxPayload2 = NULL; + } + + CmdExt.RxPayloadLen = 0; + CmdExt.pRxPayload = NULL; + + Msg.Cmd.Handle = handle; + Msg.Cmd.status = NetAppResponse->Status; + Msg.Cmd.MetadataLen = NetAppResponse->ResponseData.MetadataLen; + Msg.Cmd.PayloadLen = NetAppResponse->ResponseData.PayloadLen; + Msg.Cmd.Flags = NetAppResponse->ResponseData.Flags; + + RetVal = _SlDrvCmdSend_noLock((_SlCmdCtrl_t *)&_SlNetAppSendResponseCmdCtrl, &Msg, &CmdExt); + } + else + { + /* TODO: how to return the error code asynchronously? */ + RetVal = SL_ERROR_BSD_ENOMEM; + } + + return RetVal; +} + +/*****************************************************************************/ +/* sl_NetAppRecv */ +/*****************************************************************************/ +typedef union +{ + SlProtocolNetAppReceiveRequest_t Cmd; + _BasicResponse_t Rsp; /* Not used. do we need it? */ +}_SlNetAppReceiveMsg_u; + +#if _SL_INCLUDE_FUNC(sl_NetAppRecv) + +const _SlCmdCtrl_t _SlNetAppReceiveCmdCtrl = +{ + SL_OPCODE_NETAPP_RECEIVEREQUEST, + sizeof(SlProtocolNetAppReceiveRequest_t), + sizeof(_BasicResponse_t) /* Where is this used? */ +}; + +_SlReturnVal_t sl_NetAppRecv( _u16 Handle, _u16 *DataLen, _u8 *pData, _u32 *Flags) +{ + _SlNetAppReceiveMsg_u Msg; + _SlCmdExt_t CmdExt; + SlProtocolNetAppReceive_t AsyncRsp; /* Will be filled when SL_OPCODE_NETAPP_RECEIVE async event is arrived */ + + _SlReturnVal_t RetVal; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + _SlArgsData_t pArgsData; + + /* Validate input arguments */ + if ((NULL == pData) || (0==DataLen)) + { + return SL_ERROR_BSD_EINVAL; + } + + /* Save the user RX bufer. Rx data will be copied into it on the SL_OPCODE_NETAPP_RECEIVE async event */ + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = *DataLen; + CmdExt.pRxPayload = pData; + + /* Prepare the command args */ + Msg.Cmd.Handle = Handle; + Msg.Cmd.MaxBufferLen = *DataLen; + Msg.Cmd.Flags = *Flags; + + /* Use Obj to issue the command, if not available try later */ + ObjIdx = _SlDrvWaitForPoolObj(NETAPP_RECEIVE_ID, SL_MAX_SOCKETS); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) + { + return SL_RET_CODE_STOP_IN_PROGRESS; + } + + /* Save the AsyncRsp and cmdExt information for the SL_OPCODE_NETAPP_RECEIVE async event */ + AsyncRsp.Handle = Handle; /* Handle we are waiting for */ + AsyncRsp.Flags = 0; + AsyncRsp.PayloadLen = 0; /* 0 will indicate an error in the SL_OPCODE_NETAPP_RECEIVE async event and that no data arrived. */ + + _SlDrvProtectionObjLockWaitForever(); + + pArgsData.pData = (_u8 *) &CmdExt; + pArgsData.pArgs = (_u8 *) &AsyncRsp; + + g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&pArgsData; + + _SlDrvProtectionObjUnLock(); + + /* Send the command */ + RetVal = _SlDrvCmdSend((_SlCmdCtrl_t *)&_SlNetAppReceiveCmdCtrl, &Msg, &CmdExt); + + if(SL_OS_RET_CODE_OK == RetVal) + { + /* Wait for SL_OPCODE_NETAPP_RECEIVE async event. Will be signaled by _SlNetAppHandleAsync_NetAppReceive. */ + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); + + /* Update information for the user */ + *DataLen = AsyncRsp.PayloadLen; + *Flags = AsyncRsp.Flags; + } + + _SlDrvReleasePoolObj(ObjIdx); + + return RetVal; +} + +#endif + +/*****************************************************************************/ +/* _SlNetAppHandleAsync_NetAppReceive */ +/*****************************************************************************/ +void _SlNetAppHandleAsync_NetAppReceive(void *pVoidBuf) +{ + _u8 *pData; + _u16 len; + SlProtocolNetAppReceive_t *AsyncRsp; + _SlCmdExt_t *CmdExt; + SlProtocolNetAppReceive_t *pMsgArgs = (SlProtocolNetAppReceive_t *)_SL_RESP_ARGS_START(pVoidBuf); + + pData = (_u8 *)((SlProtocolNetAppReceive_t *)pMsgArgs + 1); /* Points to the netapp receive payload */ + + _SlDrvProtectionObjLockWaitForever(); + + if (NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs) + { + AsyncRsp = (SlProtocolNetAppReceive_t *) ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))-> pArgs; + CmdExt = (_SlCmdExt_t *) ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))-> pData; + + if (pMsgArgs->Handle == AsyncRsp->Handle) + { + if (pMsgArgs->PayloadLen <= CmdExt->RxPayloadLen) + { + len = pMsgArgs->PayloadLen; + } + else + { + len = CmdExt->RxPayloadLen; + } + + /* Copy the data to the user buffer */ + sl_Memcpy (CmdExt->pRxPayload, pData, len); + + /* Update len and flags */ + AsyncRsp->PayloadLen = len; + AsyncRsp->Flags = pMsgArgs->Flags; + } + } + + _SlDrvSyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + _SlDrvProtectionObjUnLock(); + + return; +} + +#endif + +/*****************************************************************************/ +/* sl_NetAppSend */ +/*****************************************************************************/ +typedef union +{ + SlProtocolNetAppSend_t Cmd; + _BasicResponse_t Rsp; +}_SlNetAppMsgSend_u; + +const _SlCmdCtrl_t _SlNetAppSendCmdCtrl = +{ + SL_OPCODE_NETAPP_SEND, + sizeof(SlProtocolNetAppSend_t), + sizeof(_BasicResponse_t) +}; + +_u16 sl_NetAppSend( _u16 Handle, _u16 DataLen, _u8* pData, _u32 Flags) +{ + _SlNetAppMsgSend_u Msg; + _SlCmdExt_t CmdExt; + + _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); + + if ((((Flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) == SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) && (DataLen <= SL_NETAPP_REQUEST_MAX_METADATA_LEN)) || + (((Flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) == 0) && (DataLen <= SL_NETAPP_REQUEST_MAX_DATA_LEN))) + { + CmdExt.TxPayload1Len = (DataLen+3) & (~3); + CmdExt.pTxPayload1 = (_u8 *) pData; + + Msg.Cmd.Handle = Handle; + Msg.Cmd.DataLen = DataLen; + Msg.Cmd.Flags = Flags; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppSendCmdCtrl, &Msg, &CmdExt)); + } + else + { + Msg.Rsp.status = SL_ERROR_BSD_ENOMEM; + } + + return Msg.Rsp.status; +} + +/*****************************************************************************/ +/* sl_NetAppGet */ +/*****************************************************************************/ +typedef union +{ + SlNetAppSetGet_t Cmd; + SlNetAppSetGet_t Rsp; +}_SlNetAppMsgGet_u; + +#if _SL_INCLUDE_FUNC(sl_NetAppGet) +static const _SlCmdCtrl_t _SlNetAppGetCmdCtrl = +{ + SL_OPCODE_NETAPP_NETAPPGET, + (_SlArgSize_t)sizeof(SlNetAppSetGet_t), + (_SlArgSize_t)sizeof(SlNetAppSetGet_t) +}; + +_i16 sl_NetAppGet(const _u8 AppId, const _u8 Option,_u8 *pOptionLen, _u8 *pOptionValue) +{ + _SlNetAppMsgGet_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); + + if (*pOptionLen == 0) + { + return SL_EZEROLEN; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)(*pOptionLen); + CmdExt.pRxPayload = (_u8 *)pOptionValue; + + Msg.Cmd.AppId = AppId; + Msg.Cmd.ConfigOpt = Option; + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppGetCmdCtrl, &Msg, &CmdExt)); + + + if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) + { + *pOptionLen = (_u8)CmdExt.RxPayloadLen; + return SL_ESMALLBUF; + } + else + { + *pOptionLen = (_u8)CmdExt.ActualRxPayloadLen; + } + + return (_i16)Msg.Rsp.Status; +} +#endif + +/*****************************************************************************/ +/* _SlNetAppEventHandler */ +/*****************************************************************************/ +_SlReturnVal_t _SlNetAppEventHandler(void* pArgs) +{ + _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)pArgs; +#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) + SlNetAppHttpServerEvent_t httpServerEvent; + SlNetAppHttpServerResponse_t httpServerResponse; +#endif + switch(pHdr->GenHeader.Opcode) + { + case SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE: + case SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE_V6: + _SlNetAppHandleAsync_DnsGetHostByName(pArgs); + break; +#ifndef SL_TINY + case SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE: + case SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE_V6: + _SlNetAppHandleAsync_DnsGetHostByService(pArgs); + break; + case SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE: + _SlNetAppHandleAsync_PingResponse(pArgs); + break; +#endif + + case SL_OPCODE_NETAPP_HTTPGETTOKENVALUE: + { +#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) + _u8 *pTokenName; + SlNetAppHttpServerData_t Token_value; + SlNetAppHttpServerGetToken_t *httpGetToken = (SlNetAppHttpServerGetToken_t *)_SL_RESP_ARGS_START(pHdr); + pTokenName = (_u8 *)((SlNetAppHttpServerGetToken_t *)httpGetToken + 1); + + httpServerResponse.Response = SL_NETAPP_HTTPSETTOKENVALUE; + httpServerResponse.ResponseData.TokenValue.Len = SL_NETAPP_MAX_TOKEN_VALUE_LEN; + + /* Reuse the async buffer for getting the token value response from the user */ + httpServerResponse.ResponseData.TokenValue.pData = (_u8 *)_SL_RESP_ARGS_START(pHdr) + SL_NETAPP_MAX_TOKEN_NAME_LEN; + + httpServerEvent.Event = SL_NETAPP_EVENT_HTTP_TOKEN_GET; + httpServerEvent.EventData.HttpTokenName.Len = httpGetToken->TokenNameLen; + httpServerEvent.EventData.HttpTokenName.pData = pTokenName; + + Token_value.pTokenName = pTokenName; + + _SlDrvDispatchHttpServerEvents (&httpServerEvent, &httpServerResponse); + + Token_value.ValueLen = httpServerResponse.ResponseData.TokenValue.Len; + Token_value.NameLen = httpServerEvent.EventData.HttpTokenName.Len; + Token_value.pTokenValue = httpServerResponse.ResponseData.TokenValue.pData; + + _SlNetAppSendTokenValue(&Token_value); +#else + + _u8 *pTokenName; + SlNetAppHttpServerData_t Token_value; + SlNetAppHttpServerGetToken_t *httpGetToken = (SlNetAppHttpServerGetToken_t*)_SL_RESP_ARGS_START(pHdr); + pTokenName = (_u8 *)((SlNetAppHttpServerGetToken_t *)httpGetToken + 1); + + Token_value.pTokenName = pTokenName; + Token_value.ValueLen = 0; + Token_value.NameLen = httpGetToken->TokenNameLen; + Token_value.pTokenValue = NULL; + + _SlNetAppSendTokenValue(&Token_value); +#endif + } + break; + + case SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE: + { +#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) + _u8 *pPostParams; + + SlNetAppHttpServerPostToken_t *httpPostTokenArgs = (SlNetAppHttpServerPostToken_t *)_SL_RESP_ARGS_START(pHdr); + pPostParams = (_u8 *)((SlNetAppHttpServerPostToken_t *)httpPostTokenArgs + 1); + + httpServerEvent.Event = SL_NETAPP_EVENT_HTTP_TOKEN_POST; + + httpServerEvent.EventData.HttpPostData.Action.Len = httpPostTokenArgs->PostActionLen; + httpServerEvent.EventData.HttpPostData.Action.pData = pPostParams; + pPostParams+=httpPostTokenArgs->PostActionLen; + + httpServerEvent.EventData.HttpPostData.TokenName.Len = httpPostTokenArgs->TokenNameLen; + httpServerEvent.EventData.HttpPostData.TokenName.pData = pPostParams; + pPostParams+=httpPostTokenArgs->TokenNameLen; + + httpServerEvent.EventData.HttpPostData.TokenValue.Len = httpPostTokenArgs->TokenValueLen; + httpServerEvent.EventData.HttpPostData.TokenValue.pData = pPostParams; + + httpServerResponse.Response = SL_NETAPP_HTTPRESPONSE_NONE; + + _SlDrvDispatchHttpServerEvents (&httpServerEvent, &httpServerResponse); +#endif + } + break; +#ifndef SL_TINY + case SL_OPCODE_NETAPP_REQUEST: + { +#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) + _u8 *pData; + SlNetAppRequest_t NetAppRequest; + SlNetAppResponse_t NetAppResponse; + _u16 status; + + /* Points to the Netapp request Arguments */ + SlProtocolNetAppRequest_t *protocol_NetAppRequest = (SlProtocolNetAppRequest_t*)_SL_RESP_ARGS_START(pHdr); + + NetAppRequest.AppId = protocol_NetAppRequest->AppId; + NetAppRequest.Type = protocol_NetAppRequest->RequestType; + NetAppRequest.Handle = protocol_NetAppRequest->Handle; + NetAppRequest.requestData.Flags = protocol_NetAppRequest->Flags; + + /* Prepare the Metadata*/ + pData = (_u8 *)((SlProtocolNetAppRequest_t *)protocol_NetAppRequest + 1);/* Points to the netapp request Data (start of Metadata + payload) */ + NetAppRequest.requestData.pMetadata = pData; /* Just pass the pointer */ + NetAppRequest.requestData.MetadataLen = protocol_NetAppRequest->MetadataLen; + + /* Preare the Payload */ + pData+=protocol_NetAppRequest->MetadataLen; + NetAppRequest.requestData.pPayload = pData; /* Just pass the pointer */ + NetAppRequest.requestData.PayloadLen = protocol_NetAppRequest->PayloadLen; + + /* Just in case - clear the response outout data */ + sl_Memset(&NetAppResponse, 0, sizeof (NetAppResponse)); + NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; + + /* Call the request handler dispatcher */ + _SlDrvDispatchNetAppRequestEvents (&NetAppRequest, &NetAppResponse); + + /* Handle the response */ + status = _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); + +#if (defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_NetAppRequestMemFree)) + if(1 == _SlIsEventRegistered(SL_EVENT_HDL_MEM_FREE)) + { + if ((NetAppResponse.ResponseData.MetadataLen > 0) && (NetAppResponse.ResponseData.pMetadata != NULL)) + { + _SlDrvHandleNetAppRequestMemFreeEvents (NetAppResponse.ResponseData.pMetadata); + } + + if ((NetAppResponse.ResponseData.PayloadLen > 0) && (NetAppResponse.ResponseData.pPayload != NULL)) + { + _SlDrvHandleNetAppRequestMemFreeEvents (NetAppResponse.ResponseData.pPayload); + } + } +#endif + + if (status != 0 ) + { + /* Error - just send resource not found */ + NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; + NetAppResponse.ResponseData.pMetadata = NULL; + NetAppResponse.ResponseData.MetadataLen = 0; + NetAppResponse.ResponseData.pPayload = NULL; + NetAppResponse.ResponseData.PayloadLen = 0; + NetAppResponse.ResponseData.Flags = 0; + + /* Handle the response */ + _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); + } +#else + + SlNetAppResponse_t NetAppResponse; + + /* Points to the Netapp request Arguments */ + SlProtocolNetAppRequest_t *protocol_NetAppRequest = (SlProtocolNetAppRequest_t *)_SL_RESP_ARGS_START(pHdr); + + /* Prepare the response */ + NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; + NetAppResponse.ResponseData.pMetadata = NULL; + NetAppResponse.ResponseData.MetadataLen = 0; + NetAppResponse.ResponseData.pPayload = NULL; + NetAppResponse.ResponseData.PayloadLen = 0; + NetAppResponse.ResponseData.Flags = 0; + + /* Handle the response */ + _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); +#endif + + } + break; +#endif + + default: + // SL_ERROR_TRACE2(MSG_305, "ASSERT: _SlNetAppEventHandler : invalid opcode = 0x%x = %1", pHdr->GenHeader.Opcode, pHdr->GenHeader.Opcode); + VERIFY_PROTOCOL(0); + } + + return SL_OS_RET_CODE_OK; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netcfg.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netcfg.c new file mode 100755 index 00000000000..702fc0a0038 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netcfg.c @@ -0,0 +1,151 @@ +/* + * netcfg.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include + +/*****************************************************************************/ +/* sl_NetCfgSet */ +/*****************************************************************************/ +typedef union +{ + SlNetCfgSetGet_t Cmd; + _BasicResponse_t Rsp; +}_SlNetCfgMsgSet_u; + +#if _SL_INCLUDE_FUNC(sl_NetCfgSet) + +static const _SlCmdCtrl_t _SlNetCfgSetCmdCtrl = +{ + SL_OPCODE_DEVICE_NETCFG_SET_COMMAND, + (_SlArgSize_t)sizeof(SlNetCfgSetGet_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_i16 sl_NetCfgSet(const _u16 ConfigId,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues) +{ + _SlNetCfgMsgSet_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETCFG); + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = (ConfigLen+3) & (~3); + CmdExt.pTxPayload1 = (_u8 *)pValues; + + Msg.Cmd.ConfigId = ConfigId; + Msg.Cmd.ConfigLen = ConfigLen; + Msg.Cmd.ConfigOpt = ConfigOpt; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetCfgSetCmdCtrl, &Msg, &CmdExt)); + + return (_i16)Msg.Rsp.status; +} +#endif + +/*****************************************************************************/ +/* sl_NetCfgGet */ +/*****************************************************************************/ +typedef union +{ + SlNetCfgSetGet_t Cmd; + SlNetCfgSetGet_t Rsp; +}_SlNetCfgMsgGet_u; + +#if _SL_INCLUDE_FUNC(sl_NetCfgGet) + +static const _SlCmdCtrl_t _SlNetCfgGetCmdCtrl = +{ + SL_OPCODE_DEVICE_NETCFG_GET_COMMAND, + (_SlArgSize_t)sizeof(SlNetCfgSetGet_t), + (_SlArgSize_t)sizeof(SlNetCfgSetGet_t) +}; + +_i16 sl_NetCfgGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues) +{ + _SlNetCfgMsgGet_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETCFG); + + if (*pConfigLen == 0) + { + return SL_EZEROLEN; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)(*pConfigLen); + CmdExt.pRxPayload = (_u8 *)pValues; + + _SlDrvMemZero((void*) &Msg, sizeof(Msg)); + + Msg.Cmd.ConfigLen = *pConfigLen; + Msg.Cmd.ConfigId = ConfigId; + + if( pConfigOpt ) + { + Msg.Cmd.ConfigOpt = (_u16)*pConfigOpt; + } + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetCfgGetCmdCtrl, &Msg, &CmdExt)); + + if( pConfigOpt ) + { + *pConfigOpt = (_u8)Msg.Rsp.ConfigOpt; + } + if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) + { + *pConfigLen = (_u8)CmdExt.RxPayloadLen; + return SL_ESMALLBUF; + } + else + { + *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen; + } + + return Msg.Rsp.Status; +} +#endif + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netutil.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netutil.c new file mode 100755 index 00000000000..ff498794080 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/netutil.c @@ -0,0 +1,223 @@ +/* + * netutil.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include + +/*****************************************************************************/ +/* Internal functions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + + +/****************************************************************************** +sl_UtilsGet +******************************************************************************/ + +typedef union +{ + SlNetUtilSetGet_t Cmd; + SlNetUtilSetGet_t Rsp; +} SlNetUtilMsgGet_u; + +#if _SL_INCLUDE_FUNC(sl_NetUtilGet) + +const _SlCmdCtrl_t _SlNetUtilGetCmdCtrl = +{ + SL_OPCODE_NETUTIL_GET, + sizeof(SlNetUtilSetGet_t), + sizeof(SlNetUtilSetGet_t) +}; + +_i16 sl_NetUtilGet(const _u16 Option, const _u32 ObjID, _u8 *pValues, _u16 *pValueLen) +{ + SlNetUtilMsgGet_u Msg; + _SlCmdExt_t CmdExt; + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = *pValueLen; + CmdExt.pRxPayload = (_u8 *)pValues; + + Msg.Cmd.Option = Option; + Msg.Cmd.ObjId = ObjID; + Msg.Cmd.ValueLen = *pValueLen; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetUtilGetCmdCtrl, &Msg, &CmdExt)); + + if(CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) + { + *pValueLen = CmdExt.RxPayloadLen; + return SL_ESMALLBUF; + } + else + { + *pValueLen = CmdExt.ActualRxPayloadLen; + } + + return (_i16)Msg.Rsp.Status; +} +#endif + + +/*************************************************************************** +_SlNetUtilHandleAsync_Cmd - handles NetUtil Cmd response, signalling to +a waiting object +****************************************************************************/ +void _SlNetUtilHandleAsync_Cmd(void *pVoidBuf) +{ + _SlNetUtilCmdData_t *pOutData; + SlNetUtilCmdRsp_t *pMsgArgs = (SlNetUtilCmdRsp_t *)_SL_RESP_ARGS_START(pVoidBuf); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); + + pOutData = (_SlNetUtilCmdData_t*)g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs; + + pOutData->Status = pMsgArgs->Status; + + if(SL_RET_CODE_OK == pMsgArgs->Status) + { + if (*(pOutData->pOutputLen) < pMsgArgs->OutputLen) + { + pOutData->Status = SL_ESMALLBUF; + } + else + { + *(pOutData->pOutputLen) = pMsgArgs->OutputLen; + + if(*(pOutData->pOutputLen) > 0) + { + /* copy only the data from the global async buffer */ + sl_Memcpy(pOutData->pOutputValues, (char*)pMsgArgs + sizeof(SlNetUtilCmdRsp_t), *(pOutData->pOutputLen)); + } + } + } + + _SlDrvSyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + _SlDrvProtectionObjUnLock(); + return; +} + + +/***************************************************************************** +sl_NetUtilCmd +******************************************************************************/ +typedef union +{ + SlNetUtilCmd_t Cmd; + _BasicResponse_t Rsp; +} SlNetUtilCmdMsg_u; + +#if _SL_INCLUDE_FUNC(sl_NetUtilCmd) +const _SlCmdCtrl_t _SlNetUtilCmdCtrl = +{ + SL_OPCODE_NETUTIL_COMMAND, + sizeof(SlNetUtilCmd_t), + sizeof(_BasicResponse_t) +}; + +_i16 sl_NetUtilCmd(const _u16 Cmd, const _u8 *pAttrib, const _u16 AttribLen, + const _u8 *pInputValues, const _u16 InputLen, + _u8 *pOutputValues, _u16 *pOutputLen) +{ + _i16 RetVal=0; + SlNetUtilCmdMsg_u Msg; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + _SlCmdExt_t CmdExt; + _SlNetUtilCmdData_t OutData; + + /* prepare the Cmd (control structure and data-buffer) */ + Msg.Cmd.Cmd = Cmd; + Msg.Cmd.AttribLen = AttribLen; + Msg.Cmd.InputLen = InputLen; + Msg.Cmd.OutputLen = *pOutputLen; + + _SlDrvResetCmdExt(&CmdExt); + _SlDrvMemZero(&OutData, sizeof(_SlNetUtilCmdData_t)); + + if(AttribLen > 0) + { + CmdExt.pTxPayload1 = (_u8*)pAttrib; + CmdExt.TxPayload1Len = AttribLen; + } + + if (InputLen > 0) + { + CmdExt.pTxPayload2 = (_u8*)pInputValues; + CmdExt.TxPayload2Len = InputLen; + } + + /* Set the pointers to be filled upon the async event reception */ + OutData.pOutputValues = pOutputValues; + OutData.pOutputLen = pOutputLen; + + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&OutData, NETUTIL_CMD_ID, SL_MAX_SOCKETS); + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + /* send the command */ + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetUtilCmdCtrl, &Msg, &CmdExt)); + + if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) + { + /* after the async event is signaled, the data will be copied to the pOutputValues buffer */ + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); + + /* the response header status */ + RetVal = OutData.Status; + + } + else + { + RetVal = Msg.Rsp.status; + } + _SlDrvReleasePoolObj((_u8)ObjIdx); + + return RetVal; +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.c new file mode 100755 index 00000000000..011324492a9 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.c @@ -0,0 +1,119 @@ +/* + * nonos.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include + +#ifndef SL_PLATFORM_MULTI_THREADED + +#include "nonos.h" + +_SlNonOsCB_t g__SlNonOsCB; + +_SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags) +{ + _i8 i = 0; + + /* The parameter is currently not in use */ + (void)flags; + +#ifndef SL_TINY + for (i=0 ; iIsAllocated == FALSE) + { + pE->pValue = pValue; + pE->pEntry = pEntry; + pE->IsAllocated = TRUE; +#ifndef SL_TINY + break; +#endif + } + } + + return NONOS_RET_OK; +} + +_SlNonOsRetVal_t _SlNonOsHandleSpawnTask(void) +{ + _i8 i=0; + void* pValue; + +#ifndef SL_TINY + for (i=0 ; iIsAllocated == TRUE) + { + _SlSpawnEntryFunc_t pF = pE->pEntry; + pValue = pE->pValue; + + /* Clear the entry */ + pE->pEntry = NULL; + pE->pValue = NULL; + pE->IsAllocated = FALSE; + + /* execute the spawn function */ + pF(pValue); + } + } + return NONOS_RET_OK; +} + +void tiDriverSpawnCallback(void) +{ + /* If we are in cmd context and waiting for its cmd response + * do not handle async events from spawn, as the global lock was already taken when sending the command, + * and the Async event would be handled in read cmd context, so we do nothing. + */ + if (FALSE == g_pCB->WaitForCmdResp) + { + (void)_SlNonOsHandleSpawnTask(); + } +} + +#endif + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.h new file mode 100755 index 00000000000..18bf9657431 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/nonos.h @@ -0,0 +1,165 @@ +/* + * nonos.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#ifndef __NONOS_H__ +#define __NONOS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef SL_PLATFORM_MULTI_THREADED + +/* This function call the user defined function, if defined, from the sync wait loop */ +/* The use case of this function is to allow nonos system to call a user function to put the device into sleep */ +/* The wake up should be activated after getting an interrupt from the device to Host */ +/* The user function must return without blocking to prevent a delay on the event handling */ +/* +#define _SlSyncWaitLoopCallback UserSleepFunction +*/ + +#ifndef SL_TINY_EXT +#define NONOS_MAX_SPAWN_ENTRIES (5) +#else +#define NONOS_MAX_SPAWN_ENTRIES (1) +#endif + +#define NONOS_WAIT_FOREVER ~(0UL) +#define NONOS_NO_WAIT (0x0) + +#define NONOS_RET_OK (0) +#define NONOS_RET_ERR (0xFF) +#define OSI_OK (NONOS_RET_OK) + +typedef struct +{ + _SlSpawnEntryFunc_t pEntry; + void* pValue; + _u8 IsAllocated; +}_SlNonOsSpawnEntry_t; + +typedef struct +{ + _SlNonOsSpawnEntry_t SpawnEntries[NONOS_MAX_SPAWN_ENTRIES]; +}_SlNonOsCB_t; + + +/*! + \brief type definition for the return values of this adaptation layer +*/ +typedef _u32 _SlNonOsRetVal_t; + +/*! + \brief type definition for a time value +*/ +typedef _u32 _SlNonOsTime_t; + + +#define _SlTime_t _SlNonOsTime_t + +#define SL_OS_WAIT_FOREVER NONOS_WAIT_FOREVER + +#define SL_OS_RET_CODE_OK NONOS_RET_OK + +#define SL_OS_NO_WAIT NONOS_NO_WAIT + + +/*! + \brief This function call the pEntry callback from a different context + + \param pEntry - pointer to the entry callback function + + \param pValue - pointer to any type of memory structure that would be + passed to pEntry callback from the execution thread. + + \param flags - execution flags - reserved for future usage + + \return upon successful registration of the spawn the function return 0 + (the function is not blocked till the end of the execution of the function + and could be returned before the execution is actually completed) + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +_SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); + + +/*! + \brief This function is called form the main context, while waiting on a sync object. + + \param None + + \return None + + \note + \warning +*/ +void tiDriverSpawnCallback(void); + + +/*! + \brief This function is called directly the main context, while in main task loop. + + \param None + + \return None + + \note + \warning +*/ +_SlNonOsRetVal_t _SlNonOsHandleSpawnTask(void); + +extern _SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); + +/***************************************************************************** + + Overwrite SimpleLink driver OS adaptation functions + + *****************************************************************************/ + +#undef sl_Spawn +#define sl_Spawn(pEntry,pValue,flags) _SlNonOsSpawn(pEntry,pValue,flags) + +#undef _SlTaskEntry +#define _SlTaskEntry _SlNonOsHandleSpawnTask + +#endif /* !SL_PLATFORM_MULTI_THREADED */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/objInclusion.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/objInclusion.h new file mode 100755 index 00000000000..5a164970222 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/objInclusion.h @@ -0,0 +1,345 @@ +/* + * objInclusion.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +#include + + +#ifndef OBJINCLUSION_H_ +#define OBJINCLUSION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + + For future use + +*******************************************************************************/ + +#define __inln /* if inline functions requiered: #define __inln inline */ + +#define SL_DEVICE /* Device silo is currently always mandatory */ + + +/****************************************************************************** + + Qualifiers for package customizations + +*******************************************************************************/ + +#if defined (SL_DEVICE) +#define __dev 1 +#else +#define __dev 0 +#endif + +#if defined (SL_DEVICE) && defined (SL_INC_EXT_API) +#define __dev__ext 1 +#else +#define __dev__ext 0 +#endif + + +#if (!defined (SL_PLATFORM_MULTI_THREADED)) || (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) +#define __int__spwn 1 +#else +#define __int__spwn 0 +#endif + +#if defined (SL_INC_NET_APP_PKG) +#define __nap 1 +#else +#define __nap 0 +#endif + +#if defined (SL_INC_NET_APP_PKG) && defined (SL_INC_SOCK_CLIENT_SIDE_API) +#define __nap__clt 1 +#else +#define __nap__clt 0 +#endif + +#if defined (SL_INC_NET_APP_PKG) && defined (SL_INC_EXT_API) +#define __nap__ext 1 +#else +#define __nap__ext 0 +#endif + +#if defined (SL_INC_NET_CFG_PKG) +#define __ncg 1 +#else +#define __ncg 0 +#endif + +#if defined (SL_INC_NET_CFG_PKG) && defined (SL_INC_EXT_API) +#define __ncg__ext 1 +#else +#define __ncg__ext 0 +#endif + +#if defined (SL_INC_NVMEM_PKG) +#define __nvm 1 +#else +#define __nvm 0 +#endif + +#if defined (SL_INC_NVMEM_EXT_PKG) && defined (SL_INC_EXT_API) +#define __nvm__ext 1 +#else +#define __nvm__ext 0 +#endif + +#if defined (SL_INC_SOCKET_PKG) +#define __sck 1 +#else +#define __sck 0 +#endif + +#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_EXT_API) +#define __sck__ext 1 +#else +#define __sck__ext 0 +#endif + +#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_SERVER_SIDE_API) +#define __sck__srv 1 +#else +#define __sck__srv 0 +#endif + +#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_CLIENT_SIDE_API) +#define __sck__clt 1 +#else +#define __sck__clt 0 +#endif + +#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_RECV_API) +#define __sck__rcv 1 +#else +#define __sck__rcv 0 +#endif + +#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_SEND_API) +#define __sck__snd 1 +#else +#define __sck__snd 0 +#endif + +#if defined (SL_INC_WLAN_PKG) +#define __wln 1 +#else +#define __wln 0 +#endif + +#if defined (SL_INC_WLAN_PKG) && defined (SL_INC_EXT_API) +#define __wln__ext 1 +#else +#define __wln__ext 0 +#endif + +/* The return 1 is the function need to be included in the output */ +#define _SL_INCLUDE_FUNC(Name) (_SL_INC_##Name) + +/* Driver */ +#define _SL_INC_sl_NetAppStart __nap__ext +#define _SL_INC_sl_NetAppStop __nap__ext + +#define _SL_INC_sl_NetAppDnsGetHostByName __nap__clt + + +#define _SL_INC_sl_NetAppDnsGetHostByService __nap__ext +#define _SL_INC_sl_NetAppMDNSRegisterService __nap__ext +#define _SL_INC_sl_NetAppMDNSUnRegisterService __nap__ext +#define _SL_INC_sl_NetAppGetServiceList __nap__ext + + +#define _SL_INC_sl_DnsGetHostByAddr __nap__ext +#define _SL_INC_sl_NetAppPing __nap__ext +#define _SL_INC_sl_NetAppSet __nap__ext +#define _SL_INC_sl_NetAppGet __nap__ext +#define _SL_INC_sl_NetAppRecv __nap__ext +#define _SL_INC_sl_NetAppArpFlush __nap__ext +#define _SL_INC_sl_NetAppNdFlush __nap__ext + +#define _SL_INC_sl_NetAppSend __nap__ext + +/* FS */ +#define _SL_INC_sl_FsOpen __nvm + +#define _SL_INC_sl_FsClose __nvm + +#define _SL_INC_sl_FsRead __nvm + +#define _SL_INC_sl_FsWrite __nvm + +#define _SL_INC_sl_FsGetInfo __nvm + +#define _SL_INC_sl_FsDel __nvm + +#define _SL_INC_sl_FsCtl __nvm__ext + +#define _SL_INC_sl_FsProgram __nvm__ext + +#define _SL_INC_sl_FsGetFileList __nvm__ext + +/* netcfg */ +#define _SL_INC_sl_MacAdrrSet __ncg + +#define _SL_INC_sl_MacAdrrGet __ncg + +#define _SL_INC_sl_NetCfgGet __ncg + +#define _SL_INC_sl_NetCfgSet __ncg + +/* socket */ +#define _SL_INC_sl_Socket __sck + +#define _SL_INC_sl_Close __sck + +#define _SL_INC_sl_Accept __sck__srv + +#define _SL_INC_sl_Bind __sck + +#define _SL_INC_sl_Listen __sck__srv + +#define _SL_INC_sl_Connect __sck__clt + +#define _SL_INC_sl_Select __sck + +#define _SL_INC_sl_SetSockOpt __sck + +#define _SL_INC_sl_GetSockOpt __sck__ext + +#define _SL_INC_sl_Recv __sck__rcv + +#define _SL_INC_sl_RecvFrom __sck__rcv + +#define _SL_INC_sl_Write __sck__snd + +#define _SL_INC_sl_Send __sck__snd + +#define _SL_INC_sl_SendTo __sck__snd + +#define _SL_INC_sl_StartTLS __sck + +#define _SL_INC_sl_Htonl __sck + +#define _SL_INC_sl_Htons __sck + +/* wlan */ +#define _SL_INC_sl_WlanConnect __wln__ext + +#define _SL_INC_sl_WlanDisconnect __wln__ext + +#define _SL_INC_sl_WlanProfileAdd __wln__ext + +#define _SL_INC_sl_WlanProfileUpdate __wln__ext + +#define _SL_INC_sl_WlanProfileGet __wln__ext + +#define _SL_INC_sl_WlanProfileDel __wln__ext + +#define _SL_INC_sl_WlanPolicySet __wln__ext + +#define _SL_INC_sl_WlanPolicyGet __wln__ext + +#define _SL_INC_sl_WlanGetNetworkList __wln__ext + +#define _SL_INC_sl_WlanGetExtNetworkList __wln__ext + +#define _SL_INC_sl_WlanRxFilterAdd __wln__ext + +#define _SL_INC_sl_WlanRxFilterSet __wln__ext + +#define _SL_INC_sl_WlanRxFilterGet __wln__ext + +#define _SL_INC_sl_SmartConfigStart __wln + +#define _SL_INC_sl_SmartConfigOptSet __wln__ext + +#define _SL_INC_sl_WlanProvisioning __wln + +#define _SL_INC_sl_WlanSetMode __wln + +#define _SL_INC_sl_WlanSet __wln + +#define _SL_INC_sl_WlanGet __wln + +#define _SL_INC_sl_SmartConfigOptSet __wln__ext + +#define _SL_INC_sl_SmartConfigOptGet __wln__ext + +#define _SL_INC_sl_WlanRxStatStart __wln__ext + +#define _SL_INC_sl_WlanRxStatStop __wln__ext + +#define _SL_INC_sl_WlanRxStatGet __wln__ext + + +/* device */ +#define _SL_INC_sl_Task __int__spwn + +#define _SL_INC_sl_Start __dev + +#define _SL_INC_sl_Stop __dev + +#define _SL_INC_sl_StatusGet __dev + +#ifdef SL_IF_TYPE_UART +#define _SL_INC_sl_DeviceUartSetMode __dev__ext +#endif + +#define _SL_INC_sl_DeviceEventMaskGet __dev__ext + +#define _SL_INC_sl_DeviceEventMaskSet __dev__ext + +#define _SL_INC_sl_DeviceGet __dev__ext + +#define _SL_INC_sl_DeviceSet __dev__ext + +/* netutil */ +#define _SL_INC_sl_NetUtilGet __dev__ext + +#define _SL_INC_sl_NetUtilSet __dev__ext + +#define _SL_INC_sl_NetUtilCmd __dev__ext + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /*OBJINCLUSION_H_ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/protocol.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/protocol.h new file mode 100755 index 00000000000..e72a2aa5ac0 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/protocol.h @@ -0,0 +1,1346 @@ +/* + * protocol.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*******************************************************************************\ +* +* FILE NAME: protocol.h +* +* DESCRIPTION: Constant and data structure definitions and function +* prototypes for the SL protocol module, which implements +* processing of SimpleLink Commands. +* +* AUTHOR: +* +\*******************************************************************************/ + +#ifndef _SL_PROTOCOL_TYPES_H_ +#define _SL_PROTOCOL_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** +** +** User I/F pools definitions +** +****************************************************************************/ + +/**************************************************************************** +** +** Definitions for SimpleLink Commands +** +****************************************************************************/ + + +/* pattern for LE 8/16/32 or BE*/ +#define H2N_SYNC_PATTERN {0xBBDDEEFF,0x4321,0x34,0x12} +#define H2N_CNYS_PATTERN {0xBBDDEEFF,0x8765,0x78,0x56} + +#define H2N_DUMMY_PATTERN (_u32)0xFFFFFFFF +#define N2H_SYNC_PATTERN (_u32)0xABCDDCBA +#define SYNC_PATTERN_LEN (_u32)sizeof(_u32) +#define UART_SET_MODE_MAGIC_CODE (_u32)0xAA55AA55 +#define SPI_16BITS_BUG(pattern) (_u32)((_u32)pattern & (_u32)0xFFFF7FFF) +#define SPI_8BITS_BUG(pattern) (_u32)((_u32)pattern & (_u32)0xFFFFFF7F) + + +typedef struct +{ + _u16 Opcode; + _u16 Len; +}_SlGenericHeader_t; + + +typedef struct +{ + _u32 Long; + _u16 Short; + _u8 Byte1; + _u8 Byte2; +}_SlSyncPattern_t; + +typedef _SlGenericHeader_t _SlCommandHeader_t; + +typedef struct +{ + _SlGenericHeader_t GenHeader; + _u8 TxPoolCnt; + _u8 DevStatus; + _u16 MinMaxPayload; + _u16 SocketTXFailure; + _u16 SocketNonBlocking; +}_SlResponseHeader_t; + +#define _SL_RESP_SPEC_HDR_SIZE (sizeof(_SlResponseHeader_t) - sizeof(_SlGenericHeader_t)) +#define _SL_RESP_HDR_SIZE sizeof(_SlResponseHeader_t) +#define _SL_CMD_HDR_SIZE sizeof(_SlCommandHeader_t) + +#define _SL_RESP_ARGS_START(_pMsg) (((_SlResponseHeader_t *)(_pMsg)) + 1) + +/* Used only in NWP! */ +typedef struct +{ + _SlCommandHeader_t sl_hdr; + _u8 func_args_start; +} T_SCMD; + +/* _SlResponseHeader_t DevStatus bits */ +#define _SL_DEV_STATUS_BIT_WLAN_CONN 0x01 +#define _SL_DEV_STATUS_BIT_DROPPED_EVENTS 0x02 +#define _SL_DEV_STATUS_BIT_LOCKED 0x04 +#define _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE 0x08 +#define _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED 0x10 +#define _SL_DEV_STATUS_BIT_PRESERVATION 0x20 +#define _SL_DEV_STATUS_BIT_PROVISIONING_ENABLE_API 0x40 + + +/* Internal driver bits status (g_SlDeviceStatus) */ +#define _SL_DRV_STATUS_BIT_RESTART_REQUIRED 0x100 +#define _SL_DRV_STATUS_BIT_DEVICE_STARTED 0x200 +#define _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS 0x400 +#define _SL_DRV_STATUS_BIT_START_IN_PROGRESS 0x800 + +/**************************************************************************** +** OPCODES +****************************************************************************/ +#define SL_IPV4_IPV6_OFFSET ( 9 ) +#define SL_OPCODE_IPV4 ( 0x0 << SL_IPV4_IPV6_OFFSET ) +#define SL_OPCODE_IPV6 ( 0x1 << SL_IPV4_IPV6_OFFSET ) + +#define SL_SYNC_ASYNC_OFFSET ( 10 ) +#define SL_OPCODE_SYNC (0x1 << SL_SYNC_ASYNC_OFFSET ) +#define SL_OPCODE_SILO_OFFSET ( 11 ) +#define SL_OPCODE_SILO_MASK ( 0xF << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_DEVICE ( 0x0 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_WLAN ( 0x1 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_SOCKET ( 0x2 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_NETAPP ( 0x3 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_FS ( 0x4 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_NETCFG ( 0x5 << SL_OPCODE_SILO_OFFSET ) +#define SL_OPCODE_SILO_NETUTIL ( 0x6 << SL_OPCODE_SILO_OFFSET ) + +#define SL_FAMILY_SHIFT (0x4) +#define SL_FLAGS_MASK (0xF) + +#define SL_OPCODE_DEVICE_INITCOMPLETE 0x0008 +#define SL_OPCODE_DEVICE_ABORT 0x000C +#define SL_OPCODE_DEVICE_STOP_COMMAND 0x8473 +#define SL_OPCODE_DEVICE_STOP_RESPONSE 0x0473 +#define SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE 0x0073 +#define SL_OPCODE_DEVICE_DEVICEASYNCDUMMY 0x0063 + +#define SL_OPCODE_DEVICE_VERSIONREADCOMMAND 0x8470 +#define SL_OPCODE_DEVICE_VERSIONREADRESPONSE 0x0470 +#define SL_OPCODE_DEVICE_DEVICE_ASYNC_GENERAL_ERROR 0x0078 +#define SL_OPCODE_DEVICE_FLOW_CTRL_ASYNC_EVENT 0x0079 + +#define SL_OPCODE_WLAN_WLANCONNECTCOMMAND 0x8C80 +#define SL_OPCODE_WLAN_WLANCONNECTRESPONSE 0x0C80 +#define SL_OPCODE_WLAN_STA_ASYNCCONNECTEDRESPONSE 0x0880 +#define SL_OPCODE_WLAN_P2PCL_ASYNCCONNECTEDRESPONSE 0x0892 + +#define SL_OPCODE_WLAN_WLANDISCONNECTCOMMAND 0x8C81 +#define SL_OPCODE_WLAN_WLANDISCONNECTRESPONSE 0x0C81 +#define SL_OPCODE_WLAN_STA_ASYNCDISCONNECTEDRESPONSE 0x0881 +#define SL_OPCODE_WLAN_P2PCL_ASYNCDISCONNECTEDRESPONSE 0x0894 + +#define SL_OPCODE_WLAN_ASYNC_STA_ADDED 0x082E +#define SL_OPCODE_WLAN_ASYNC_P2PCL_ADDED 0x0896 +#define SL_OPCODE_WLAN_ASYNC_STA_REMOVED 0x082F +#define SL_OPCODE_WLAN_ASYNC_P2PCL_REMOVED 0x0898 + +#define SL_OPCODE_WLAN_P2P_DEV_FOUND 0x0830 +#define SL_OPCODE_WLAN_P2P_CONNECTION_FAILED 0x0831 +#define SL_OPCODE_WLAN_P2P_NEG_REQ_RECEIVED 0x0832 + +#define SL_OPCODE_WLAN_WLANCONNECTEAPCOMMAND 0x8C82 +#define SL_OPCODE_WLAN_WLANCONNECTEAPCRESPONSE 0x0C82 +#define SL_OPCODE_WLAN_PROFILEADDCOMMAND 0x8C83 +#define SL_OPCODE_WLAN_PROFILEADDRESPONSE 0x0C83 +#define SL_OPCODE_WLAN_PROFILEUPDATECOMMAND 0x8CC2 +#define SL_OPCODE_WLAN_PROFILEUPDATERESPONSE 0x0CC2 +#define SL_OPCODE_WLAN_PROFILEEAPUPDATECOMMAND 0x8CC3 +#define SL_OPCODE_WLAN_PROFILEEAPUPDATERESPONSE 0x0CC0 +#define SL_OPCODE_WLAN_PROFILEGETCOMMAND 0x8C84 +#define SL_OPCODE_WLAN_PROFILEGETRESPONSE 0x0C84 +#define SL_OPCODE_WLAN_PROFILEDELCOMMAND 0x8C85 +#define SL_OPCODE_WLAN_PROFILEDELRESPONSE 0x0C85 +#define SL_OPCODE_WLAN_POLICYSETCOMMAND 0x8C86 +#define SL_OPCODE_WLAN_POLICYSETRESPONSE 0x0C86 +#define SL_OPCODE_WLAN_POLICYGETCOMMAND 0x8C87 +#define SL_OPCODE_WLAN_POLICYGETRESPONSE 0x0C87 +#define SL_OPCODE_WLAN_FILTERADD 0x8C88 +#define SL_OPCODE_WLAN_FILTERADDRESPONSE 0x0C88 +#define SL_OPCODE_WLAN_FILTERGET 0x8C89 +#define SL_OPCODE_WLAN_FILTERGETRESPONSE 0x0C89 +#define SL_OPCODE_WLAN_FILTERDELETE 0x8C8A +#define SL_OPCODE_WLAN_FILTERDELETERESPOSNE 0x0C8A +#define SL_OPCODE_WLAN_WLANGETSTATUSCOMMAND 0x8C8F +#define SL_OPCODE_WLAN_WLANGETSTATUSRESPONSE 0x0C8F +#define SL_OPCODE_WLAN_STARTTXCONTINUESCOMMAND 0x8CAA +#define SL_OPCODE_WLAN_STARTTXCONTINUESRESPONSE 0x0CAA +#define SL_OPCODE_WLAN_STOPTXCONTINUESCOMMAND 0x8CAB +#define SL_OPCODE_WLAN_STOPTXCONTINUESRESPONSE 0x0CAB +#define SL_OPCODE_WLAN_STARTRXSTATCOMMAND 0x8CAC +#define SL_OPCODE_WLAN_STARTRXSTATRESPONSE 0x0CAC +#define SL_OPCODE_WLAN_STOPRXSTATCOMMAND 0x8CAD +#define SL_OPCODE_WLAN_STOPRXSTATRESPONSE 0x0CAD +#define SL_OPCODE_WLAN_GETRXSTATCOMMAND 0x8CAF +#define SL_OPCODE_WLAN_GETRXSTATRESPONSE 0x0CAF +#define SL_OPCODE_WLAN_POLICYSETCOMMANDNEW 0x8CB0 +#define SL_OPCODE_WLAN_POLICYSETRESPONSENEW 0x0CB0 +#define SL_OPCODE_WLAN_POLICYGETCOMMANDNEW 0x8CB1 +#define SL_OPCODE_WLAN_POLICYGETRESPONSENEW 0x0CB1 + +#define SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE 0x08B2 +#define SL_OPCODE_WLAN_SET_MODE 0x8CB4 +#define SL_OPCODE_WLAN_SET_MODE_RESPONSE 0x0CB4 +#define SL_OPCODE_WLAN_CFG_SET 0x8CB5 +#define SL_OPCODE_WLAN_CFG_SET_RESPONSE 0x0CB5 +#define SL_OPCODE_WLAN_CFG_GET 0x8CB6 +#define SL_OPCODE_WLAN_CFG_GET_RESPONSE 0x0CB6 +#define SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND 0x8C67 +#define SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND_RESPONSE 0x0C67 +#define SL_OPCODE_WLAN_RESERVED_RESPONSE 0x08BA + +#define SL_OPCODE_SOCKET_SOCKET 0x9401 +#define SL_OPCODE_SOCKET_SOCKETRESPONSE 0x1401 +#define SL_OPCODE_SOCKET_CLOSE 0x9402 +#define SL_OPCODE_SOCKET_CLOSERESPONSE 0x1402 +#define SL_OPCODE_SOCKET_ACCEPT 0x9403 +#define SL_OPCODE_SOCKET_ACCEPTRESPONSE 0x1403 +#define SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE 0x1003 +#define SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE_V6 0x1203 +#define SL_OPCODE_SOCKET_BIND 0x9404 +#define SL_OPCODE_SOCKET_BIND_V6 0x9604 +#define SL_OPCODE_SOCKET_BINDRESPONSE 0x1404 +#define SL_OPCODE_SOCKET_LISTEN 0x9405 +#define SL_OPCODE_SOCKET_LISTENRESPONSE 0x1405 +#define SL_OPCODE_SOCKET_CONNECT 0x9406 +#define SL_OPCODE_SOCKET_CONNECT_V6 0x9606 +#define SL_OPCODE_SOCKET_CONNECTRESPONSE 0x1406 +#define SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE 0x1006 +#define SL_OPCODE_SOCKET_SELECT 0x9407 +#define SL_OPCODE_SOCKET_SELECTRESPONSE 0x1407 +#define SL_OPCODE_SOCKET_SELECTASYNCRESPONSE 0x1007 +#define SL_OPCODE_SOCKET_SETSOCKOPT 0x9408 +#define SL_OPCODE_SOCKET_SETSOCKOPTRESPONSE 0x1408 +#define SL_OPCODE_SOCKET_GETSOCKOPT 0x9409 +#define SL_OPCODE_SOCKET_GETSOCKOPTRESPONSE 0x1409 +#define SL_OPCODE_SOCKET_RECV 0x940A +#define SL_OPCODE_SOCKET_RECVASYNCRESPONSE 0x100A +#define SL_OPCODE_SOCKET_RECVFROM 0x940B +#define SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE 0x100B +#define SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 0x120B +#define SL_OPCODE_SOCKET_SEND 0x940C +#define SL_OPCODE_SOCKET_SENDTO 0x940D +#define SL_OPCODE_SOCKET_SENDTO_V6 0x960D +#define SL_OPCODE_SOCKET_TXFAILEDASYNCRESPONSE 0x100E +#define SL_OPCODE_SOCKET_SOCKETASYNCEVENT 0x100F +#define SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT 0x1010 +#define SL_OPCODE_NETAPP_START_COMMAND 0x9C0A +#define SL_OPCODE_NETAPP_START_RESPONSE 0x1C0A +#define SL_OPCODE_NETAPP_NETAPPSTARTRESPONSE 0x1C0A +#define SL_OPCODE_NETAPP_STOP_COMMAND 0x9C61 +#define SL_OPCODE_NETAPP_STOP_RESPONSE 0x1C61 +#define SL_OPCODE_NETAPP_NETAPPSET 0x9C0B +#define SL_OPCODE_NETAPP_NETAPPSETRESPONSE 0x1C0B +#define SL_OPCODE_NETAPP_NETAPPGET 0x9C27 +#define SL_OPCODE_NETAPP_NETAPPGETRESPONSE 0x1C27 +#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAME 0x9C20 +#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMERESPONSE 0x1C20 +#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE 0x1820 +#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE_V6 0x1A20 +#define SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE 0x9C71 +#define SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE_RESPONSE 0x1C72 +#define SL_OPCODE_NETAPP_MDNSREGISTERSERVICE 0x9C34 +#define SL_OPCODE_NETAPP_MDNSREGISTERSERVICERESPONSE 0x1C34 +#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICE 0x9C35 +#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICERESPONSE 0x1C35 +#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE 0x1835 +#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE_V6 0x1A35 +#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDR 0x9C26 +#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDR_V6 0x9E26 +#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDRRESPONSE 0x1C26 +#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDRASYNCRESPONSE 0x1826 +#define SL_OPCODE_NETAPP_PINGSTART 0x9C21 +#define SL_OPCODE_NETAPP_PINGSTART_V6 0x9E21 +#define SL_OPCODE_NETAPP_PINGSTARTRESPONSE 0x1C21 +#define SL_OPCODE_NETAPP_PINGREPORTREQUEST 0x9C22 +#define SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE 0x1822 +#define SL_OPCODE_NETAPP_ARPFLUSH 0x9C24 +#define SL_OPCODE_NETAPP_ARPFLUSHRESPONSE 0x1C24 +#define SL_OPCODE_NETAPP_NDFLUSH_V6 0x9EC2 +#define SL_OPCODE_NETAPP_NDFLUSHHRESPONSE_V6 0x1EC3 +#define SL_OPCODE_NETAPP_IPACQUIRED 0x1825 +#define SL_OPCODE_NETAPP_IPV4_LOST 0x1832 +#define SL_OPCODE_NETAPP_DHCP_IPV4_ACQUIRE_TIMEOUT 0x1833 +#define SL_OPCODE_LINK_QUALITY_EVENT 0x1834 +#define SL_OPCODE_NETAPP_IPACQUIRED_V6 0x1A25 +#define SL_OPCODE_NETAPP_IPV6_LOST_V6 0x1A32 +#define SL_OPCODE_NETAPP_IPERFSTARTCOMMAND 0x9C28 +#define SL_OPCODE_NETAPP_IPERFSTARTRESPONSE 0x1C28 +#define SL_OPCODE_NETAPP_IPERFSTOPCOMMAND 0x9C29 +#define SL_OPCODE_NETAPP_IPERFSTOPRESPONSE 0x1C29 +#define SL_OPCODE_NETAPP_CTESTSTARTCOMMAND 0x9C2A +#define SL_OPCODE_NETAPP_CTESTSTARTRESPONSE 0x1C2A +#define SL_OPCODE_NETAPP_CTESTASYNCRESPONSE 0x182A +#define SL_OPCODE_NETAPP_CTESTSTOPCOMMAND 0x9C2B +#define SL_OPCODE_NETAPP_CTESTSTOPRESPONSE 0x1C2B +#define SL_OPCODE_NETAPP_IP_LEASED 0x182C +#define SL_OPCODE_NETAPP_IP_RELEASED 0x182D +#define SL_OPCODE_NETAPP_HTTPGETTOKENVALUE 0x182E +#define SL_OPCODE_NETAPP_HTTPSENDTOKENVALUE 0x9C2F +#define SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE 0x1830 +#define SL_OPCODE_NETAPP_IP_COLLISION 0x1831 +#define SL_OPCODE_NETAPP_RESERVED1 0x18C4 +#define SL_OPCODE_NETAPP_RESERVED2 0x1AC5 +#define SL_OPCODE_NETAPP_RESERVED3 0x1AC6 + +#define SL_OPCODE_NETAPP_REQUEST 0x1878 +#define SL_OPCODE_NETAPP_RESPONSE 0x9C78 +#define SL_OPCODE_NETAPP_SEND 0x9C79 +#define SL_OPCODE_NETAPP_SENDRESPONSE 0x1C79 +#define SL_OPCODE_NETAPP_RECEIVEREQUEST 0x9C7A +#define SL_OPCODE_NETAPP_RECEIVE 0x187B + +#define SL_OPCODE_NVMEM_FILEOPEN 0xA43C +#define SL_OPCODE_NVMEM_FILEOPENRESPONSE 0x243C +#define SL_OPCODE_NVMEM_FILECLOSE 0xA43D +#define SL_OPCODE_NVMEM_FILECLOSERESPONSE 0x243D +#define SL_OPCODE_NVMEM_FILEREADCOMMAND 0xA440 +#define SL_OPCODE_NVMEM_FILEREADRESPONSE 0x2440 +#define SL_OPCODE_NVMEM_FILEWRITECOMMAND 0xA441 +#define SL_OPCODE_NVMEM_FILEWRITERESPONSE 0x2441 +#define SL_OPCODE_NVMEM_FILEGETINFOCOMMAND 0xA442 +#define SL_OPCODE_NVMEM_FILEGETINFORESPONSE 0x2442 +#define SL_OPCODE_NVMEM_FILEDELCOMMAND 0xA443 +#define SL_OPCODE_NVMEM_FILEDELRESPONSE 0x2443 +#define SL_OPCODE_NVMEM_NVMEMFORMATCOMMAND 0xA444 +#define SL_OPCODE_NVMEM_NVMEMFORMATRESPONSE 0x2444 +#define SL_OPCODE_NVMEM_NVMEMGETFILELISTCOMMAND 0xA448 +#define SL_OPCODE_NVMEM_NVMEMGETFILELISTRESPONSE 0x2448 + +#define SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND 0xA44A +#define SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGRESPONSE 0x244A +#define SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLCOMMAND 0xA44B +#define SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLRESPONSE 0x244B +#define SL_OPCODE_NVMEM_NVMEMBUNDLECONTROLCOMMAND 0xA44C +#define SL_OPCODE_NVMEM_NVMEMBUNDLECONTROLRESPONSE 0x244C + + +#define SL_OPCODE_DEVICE_SETDEBUGLEVELCOMMAND 0x846A +#define SL_OPCODE_DEVICE_SETDEBUGLEVELRESPONSE 0x046A + +#define SL_OPCODE_DEVICE_NETCFG_SET_COMMAND 0x8432 +#define SL_OPCODE_DEVICE_NETCFG_SET_RESPONSE 0x0432 +#define SL_OPCODE_DEVICE_NETCFG_GET_COMMAND 0x8433 +#define SL_OPCODE_DEVICE_NETCFG_GET_RESPONSE 0x0433 +/* */ +#define SL_OPCODE_DEVICE_SETUARTMODECOMMAND 0x846B +#define SL_OPCODE_DEVICE_SETUARTMODERESPONSE 0x046B +#define SL_OPCODE_DEVICE_SSISIZESETCOMMAND 0x846B +#define SL_OPCODE_DEVICE_SSISIZESETRESPONSE 0x046B + +/* */ +#define SL_OPCODE_DEVICE_EVENTMASKSET 0x8464 +#define SL_OPCODE_DEVICE_EVENTMASKSETRESPONSE 0x0464 +#define SL_OPCODE_DEVICE_EVENTMASKGET 0x8465 +#define SL_OPCODE_DEVICE_EVENTMASKGETRESPONSE 0x0465 + +#define SL_OPCODE_DEVICE_DEVICEGET 0x8466 +#define SL_OPCODE_DEVICE_DEVICEGETRESPONSE 0x0466 +#define SL_OPCODE_DEVICE_DEVICESET 0x84B7 +#define SL_OPCODE_DEVICE_DEVICESETRESPONSE 0x04B7 + +#define SL_OPCODE_WLAN_SCANRESULTSGETCOMMAND 0x8C8C +#define SL_OPCODE_WLAN_SCANRESULTSGETRESPONSE 0x0C8C +#define SL_OPCODE_WLAN_EXTSCANRESULTSGETCOMMAND 0x8C8D +#define SL_OPCODE_WLAN_EXTSCANRESULTSGETRESPONSE 0x0C8D +#define SL_OPCODE_WLAN_SMARTCONFIGOPTGET 0x8C8E +#define SL_OPCODE_WLAN_SMARTCONFIGOPTGETRESPONSE 0x0C8E + +#define SL_OPCODE_WLAN_PROVISIONING_COMMAND 0x8C98 +#define SL_OPCODE_WLAN_PROVISIONING_RESPONSE 0x0C98 +#define SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT 0x0099 +#define SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT 0x089A + +#define SL_OPCODE_FREE_BSD_RECV_BUFFER 0xCCCB +#define SL_OPCODE_FREE_NON_BSD_READ_BUFFER 0xCCCD + + +/* Rx Filters opcodes */ +#define SL_OPCODE_WLAN_WLANRXFILTERADDCOMMAND 0x8C6C +#define SL_OPCODE_WLAN_WLANRXFILTERADDRESPONSE 0x0C6C +#define SL_OPCODE_WLAN_WLANRXFILTERGETSTATISTICSINFOCOMMAND 0x8C6E +#define SL_OPCODE_WLAN_WLANRXFILTERGETSTATISTICSINFORESPONSE 0x0C6E +#define SL_OPCODE_WLAN_WLANRXFILTERGETINFO 0x8C70 +#define SL_OPCODE_WLAN_WLANRXFILTERGETINFORESPONSE 0x0C70 +#define SL_OPCODE_WLAN_RX_FILTER_ASYNC_RESPONSE 0x089D + +/* Utils */ +#define SL_OPCODE_NETUTIL_SET 0xB4BE +#define SL_OPCODE_NETUTIL_SETRESPONSE 0x34BE +#define SL_OPCODE_NETUTIL_GET 0xB4C0 +#define SL_OPCODE_NETUTIL_GETRESPONSE 0x34C0 +#define SL_OPCODE_NETUTIL_COMMAND 0xB4C1 +#define SL_OPCODE_NETUTIL_COMMANDRESPONSE 0x34C1 +#define SL_OPCODE_NETUTIL_COMMANDASYNCRESPONSE 0x30C1 + +/******************************************************************************************/ +/* Device structs */ +/******************************************************************************************/ +typedef _u32 InitStatus_t; + +typedef struct +{ + _i32 Status; + _i32 ChipId; + _i32 MoreData; +}InitComplete_t; + +typedef struct +{ + _i16 status; + _u16 sender; +}_BasicResponse_t; + +typedef struct +{ + _u32 SessionNumber; + _u16 Caller; + _u16 Padding; +}SlDeviceResetRequestData_t; + +typedef struct +{ + _u16 Timeout; + _u16 Padding; +}SlDeviceStopCommand_t; + +typedef struct +{ + _u32 Group; + _u32 Mask; +}SlDeviceMaskEventSetCommand_t; + +typedef _BasicResponse_t _DevMaskEventSetResponse_t; + +typedef struct +{ + _u32 Group; +} SlDeviceMaskEventGetCommand_t; + +typedef struct +{ + _u32 Group; + _u32 Mask; +} SlDeviceMaskEventGetResponse_t; + +typedef struct +{ + _u32 Group; +} SlDeviceStatusGetCommand_t; + +typedef struct +{ + _u32 Group; + _u32 Status; +} SlDeviceStatusGetResponse_t; + +typedef struct +{ + _u32 ChipId; + _u32 FwVersion[4]; + _u8 PhyVersion[4]; +} SlDeviceVersionReadResponsePart_t; + +typedef struct +{ + SlDeviceVersionReadResponsePart_t part; + _u32 NwpVersion[4]; + _u16 RomVersion; + _u16 Padding; +} SlDeviceVersionReadResponseFull_t; + +typedef struct +{ + _u16 MinTxPayloadSize; + _u8 padding[6]; +} SlDeviceFlowCtrlAsyncEvent_t; + +typedef struct +{ + _u32 BaudRate; + _u8 FlowControlEnable; +} SlDeviceUartSetModeCommand_t; + +typedef _BasicResponse_t SlDeviceUartSetModeResponse_t; + +/******************************************************/ + +typedef struct +{ + _u8 SsiSizeInBytes; + _u8 Padding[3]; +}_StellarisSsiSizeSet_t; + +/*****************************************************************************************/ +/* WLAN structs */ +/*****************************************************************************************/ +#define MAXIMAL_PASSWORD_LENGTH (64) + +typedef struct +{ + _u8 ProvisioningCmd; + _u8 RequestedRoleAfterSuccess; + _u16 InactivityTimeoutSec; + _u32 Flags; +} SlWlanProvisioningParams_t; + +typedef struct{ + _u8 SecType; + _u8 SsidLen; + _u8 Bssid[6]; + _u8 PasswordLen; +} SlWlanConnectCommon_t; + +#define SSID_STRING(pCmd) (_i8 *)((SlWlanConnectCommon_t *)(pCmd) + 1) +#define PASSWORD_STRING(pCmd) (SSID_STRING(pCmd) + ((SlWlanConnectCommon_t *)(pCmd))->SsidLen) + +typedef struct{ + SlWlanConnectCommon_t Common; + _u8 UserLen; + _u8 AnonUserLen; + _u8 CertIndex; + _u32 EapBitmask; +} SlWlanConnectEapCommand_t; + +#define EAP_SSID_STRING(pCmd) (_i8 *)((SlWlanConnectEapCommand_t *)(pCmd) + 1) +#define EAP_PASSWORD_STRING(pCmd) (EAP_SSID_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->Common.SsidLen) +#define EAP_USER_STRING(pCmd) (EAP_PASSWORD_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->Common.PasswordLen) +#define EAP_ANON_USER_STRING(pCmd) (EAP_USER_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->UserLen) + +typedef struct +{ + _u8 PolicyType; + _u8 Padding; + _u8 PolicyOption; + _u8 PolicyOptionLen; +} SlWlanPolicySetGet_t; + +typedef struct{ + _u32 MinDwellTime; + _u32 MaxDwellTime; + _u32 NumProbeResponse; + _u32 G_Channels_mask; + _i32 RssiThershold; + _i32 SnrThershold; + _i32 DefaultTXPower; + _u16 IntervalList[16]; +} SlWlanScanParamSetCommand_t; + +typedef struct{ + _i16 SecType; + _u8 SsidLen; + _u8 Priority; + _u8 Bssid[6]; + _u8 PasswordLen; + _u8 WepKeyId; +} SlWlanAddGetProfile_t; + +typedef struct{ + SlWlanAddGetProfile_t Common; + _u8 UserLen; + _u8 AnonUserLen; + _u8 CertIndex; + _u8 padding; + _u32 EapBitmask; +} SlWlanAddGetEapProfile_t; + + +typedef struct{ + _i16 SecType; + _u8 SsidLen; + _u8 Priority; + _u8 Bssid[6]; + _u8 PasswordLen; + _u8 WepKeyId; + _u32 Index; + _u8 UserLen; + _u8 AnonUserLen; + _u8 CertIndex; + _u8 padding; + _u32 EapBitmask; +} SlWlanUpdateProfile_t; + +#define PROFILE_SSID_STRING(pCmd) ((_i8 *)((SlWlanAddGetProfile_t *)(pCmd) + 1)) +#define PROFILE_PASSWORD_STRING(pCmd) (PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetProfile_t *)(pCmd))->SsidLen) + +#define EAP_PROFILE_SSID_STRING(pCmd) (_i8 *)((SlWlanAddGetEapProfile_t *)(pCmd) + 1) +#define EAP_PROFILE_PASSWORD_STRING(pCmd) (EAP_PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->Common.SsidLen) +#define EAP_PROFILE_USER_STRING(pCmd) (EAP_PROFILE_PASSWORD_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->Common.PasswordLen) +#define EAP_PROFILE_ANON_USER_STRING(pCmd) (EAP_PROFILE_USER_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->UserLen) + +#define PROFILE_SSID_STRING(pCmd) ((_i8 *)((SlWlanAddGetProfile_t *)(pCmd) + 1)) +#define PROFILE_PASSWORD_STRING(pCmd) (PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetProfile_t *)(pCmd))->SsidLen) + +#define UPDATE_PROFILE_SSID_STRING(pCmd) (_i8 *)((SlWlanUpdateProfile_t *)(pCmd) + 1) +#define UPDATE_PROFILE_PASSWORD_STRING(pCmd) (UPDATE_PROFILE_SSID_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->SsidLen) +#define UPDATE_PROFILE_USER_STRING(pCmd) (UPDATE_PROFILE_PASSWORD_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->PasswordLen) +#define UPDATE_PROFILE_ANON_USER_STRING(pCmd) (UPDATE_PROFILE_USER_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->UserLen) + + +typedef struct +{ + _u8 Index; + _u8 Padding[3]; +} SlWlanProfileDelGetCommand_t; + +typedef _BasicResponse_t _WlanGetNetworkListResponse_t; + +typedef struct +{ + _u8 Index; + _u8 Count; + _i8 padding[2]; +} SlWlanGetNetworkListCommand_t; + +typedef _BasicResponse_t _WlanGetExtNetworkListResponse_t; + +typedef struct +{ + _u8 Index; + _u8 Count; + _i8 padding[2]; +} SlWlanGetExtNetworkListCommand_t; + +typedef struct +{ + _u32 GroupIdBitmask; + _u8 Cipher; + _u8 PublicKeyLen; + _u8 Padding[2]; +} SlWlanSmartConfigParams_t; + +#define SMART_CONFIG_START_PUBLIC_KEY_STRING(pCmd) ((_i8 *)((SlWlanSmartConfigParams_t *)(pCmd) + 1)) + +typedef struct +{ + _u8 Mode; + _u8 Padding[3]; +} SlWlanSetMode_t; + +typedef struct +{ + _u16 Status; + _u16 ConfigId; + _u16 ConfigOpt; + _u16 ConfigLen; +} SlWlanCfgSetGet_t; + + +/* ******************************************************************************/ +/* RX filters - Start */ +/* ******************************************************************************/ + +typedef struct +{ + SlWlanRxFilterRuleType_t RuleType; + SlWlanRxFilterFlags_u Flags; + SlWlanRxFilterID_t FilterId; + _u8 Padding; + SlWlanRxFilterRule_u Rule; + SlWlanRxFilterTrigger_t Trigger; + SlWlanRxFilterAction_t Action; +} SlWlanRxFilterAddCommand_t; + +typedef struct +{ + SlWlanRxFilterID_t FilterId; + _i16 Status; + _u8 Padding[1]; +} SlWlanRxFilterAddCommandReponse_t; + +typedef struct +{ + _i16 Status; + _u8 Padding[2]; +} SlWlanRxFilterSetCommandReponse_t; + +typedef struct +{ + _i16 Status; + _u16 OutputBufferLength; + +} SlWlanRxFilterGetCommandReponse_t; + + +/* ******************************************************************************/ +/* RX filters -- End */ +/* ******************************************************************************/ + +typedef struct +{ + _u16 Status; + _u8 WlanRole; /* 0 = station, 2 = AP */ + _u8 Ipv6Enabled; + _u8 DhcpEnabled; + + _u32 Global[4]; + _u32 Local[4]; + _u32 DnsServer[4]; + _u8 DhcpState; +} SlNetappIpV6configRetArgs_t; + +typedef struct +{ + _u8 Ip[4]; + _u8 IpMask[4]; + _u8 IpGateway[4]; + _u8 IpDnsServer[4]; + _u8 IpStart[4]; + _u8 IpEnd[4]; +} SlNetCfgIpV4APArgs_t; + +typedef struct +{ + _u16 Status; + _u8 MacAddr[6]; +} SlMacAddressSetGet_t; + +typedef struct +{ + _u16 Status; + _u16 ConfigId; + _u16 ConfigOpt; + _u16 ConfigLen; +} SlNetCfgSetGet_t; + +typedef struct +{ + _u16 Status; + _u16 DeviceSetId; + _u16 Option; + _u16 ConfigLen; +} SlDeviceSetGet_t; + + +/******************************************************************************************/ +/* Socket structs */ +/******************************************************************************************/ + +typedef struct +{ + _u8 Domain; + _u8 Type; + _u8 Protocol; + _u8 Padding; +} SlSocketCommand_t; + +typedef struct +{ + _i16 StatusOrLen; + _u8 Sd; + _u8 Padding; +} SlSocketResponse_t; + +typedef struct +{ + _u8 Sd; + _u8 Family; + _u8 Padding1; + _u8 Padding2; +} SlAcceptCommand_t; + +typedef struct +{ + _i16 StatusOrLen; + _u8 Sd; + _u8 Family; + _u16 Port; + _u16 PaddingOrAddr; + _u32 Address; +} SlSocketAddrAsyncIPv4Response_t; + +typedef struct +{ + _i16 StatusOrLen; + _u8 Sd; + _u8 Family; + _u16 Port; + _u8 Address[6]; +} SlSocketAddrAsyncIPv6EUI48Response_t; + +typedef struct +{ + _i16 StatusOrLen; + _u8 Sd; + _u8 Family; + _u16 Port; + _u16 PaddingOrAddr; + _u32 Address[4]; +} SlSocketAddrAsyncIPv6Response_t; + +typedef struct +{ + _i16 LenOrPadding; + _u8 Sd; + _u8 FamilyAndFlags; + _u16 Port; + _u16 PaddingOrAddr; + _u32 Address; +} SlSocketAddrIPv4Command_t; + +typedef struct +{ + _i16 LenOrPadding; + _u8 Sd; + _u8 FamilyAndFlags; + _u16 Port; + _u8 Address[6]; +} SlSocketAddrIPv6EUI48Command_t; + +typedef struct +{ + _i16 LenOrPadding; + _u8 Sd; + _u8 FamilyAndFlags; + _u16 Port; + _u16 PaddingOrAddr; + _u32 Address[4]; +} SlSocketAddrIPv6Command_t; + +typedef union { + SlSocketAddrIPv4Command_t IpV4; + SlSocketAddrIPv6EUI48Command_t IpV6EUI48; +#ifdef SL_SUPPORT_IPV6 + SlSocketAddrIPv6Command_t IpV6; +#endif +} SlSocketAddrCommand_u; + +typedef union { + SlSocketAddrAsyncIPv4Response_t IpV4; + SlSocketAddrAsyncIPv6EUI48Response_t IpV6EUI48; +#ifdef SL_SUPPORT_IPV6 + SlSocketAddrAsyncIPv6Response_t IpV6; +#endif +} SlSocketAddrResponse_u; + +typedef struct +{ + _u8 Sd; + _u8 Backlog; + _u8 Padding1; + _u8 Padding2; +} SlListenCommand_t; + +typedef struct +{ + _u8 Sd; + _u8 Padding0; + _u8 Padding1; + _u8 Padding2; +} SlCloseCommand_t; + +typedef struct +{ + _u8 Nfds; + _u8 ReadFdsCount; + _u8 WriteFdsCount; + _u8 Padding; + _u16 ReadFds; + _u16 WriteFds; + _u16 tv_usec; + _u16 tv_sec; +} SlSelectCommand_t; + +typedef struct +{ + _u16 Status; + _u8 ReadFdsCount; + _u8 WriteFdsCount; + _u16 ReadFds; + _u16 WriteFds; +} SlSelectAsyncResponse_t; + +typedef struct +{ + _u8 Sd; + _u8 Level; + _u8 OptionName; + _u8 OptionLen; +} SlSetSockOptCommand_t; + +typedef struct +{ + _u8 Sd; + _u8 Level; + _u8 OptionName; + _u8 OptionLen; +} SlGetSockOptCommand_t; + +typedef struct +{ + _i16 Status; + _u8 Sd; + _u8 OptionLen; +} SlGetSockOptResponse_t; + +typedef struct +{ + _u16 StatusOrLen; + _u8 Sd; + _u8 FamilyAndFlags; +} SlSendRecvCommand_t; + +/***************************************************************************************** +* NETAPP structs +******************************************************************************************/ + +typedef _BasicResponse_t _NetAppStartStopResponse_t; + +typedef struct +{ + _u32 AppId; +}_NetAppStartStopCommand_t; + +typedef struct +{ + _u16 Status; + _u16 AppId; + _u16 ConfigOpt; + _u16 ConfigLen; +} SlNetAppSetGet_t; +typedef struct +{ + _u16 PortNumber; +} SlNetAppHttpServerGetSetPortNum_t; + +typedef struct +{ + _u8 AuthEnable; +} SlNetAppHttpServerGetSetAuthEnable_t; + +typedef struct _SlNetAppHttpServerGetToken_t +{ + _u8 TokenNameLen; + _u8 Padd1; + _u16 Padd2; +}SlNetAppHttpServerGetToken_t; + +typedef struct _SlNetAppHttpServerSendToken_t +{ + _u8 TokenValueLen; + _u8 TokenNameLen; + _u8 TokenName[SL_NETAPP_MAX_TOKEN_NAME_LEN]; + _u16 Padd; +} SlNetAppHttpServerSendToken_t; + +typedef struct _SlNetAppHttpServerPostToken_t +{ + _u8 PostActionLen; + _u8 TokenNameLen; + _u8 TokenValueLen; + _u8 padding; +} SlNetAppHttpServerPostToken_t; + +/***************************************************************************************** +* NETAPP Request/Response/Send/Receive +******************************************************************************************/ +typedef struct _SlProtocolNetAppRequest_t +{ + _u8 AppId; + _u8 RequestType; + _u16 Handle; + _u16 MetadataLen; + _u16 PayloadLen; + _u32 Flags; +} SlProtocolNetAppRequest_t; + +typedef struct _SlProtocolNetAppResponse_t +{ + _u16 Handle; + _u16 status; + _u16 MetadataLen; + _u16 PayloadLen; + _u32 Flags; +} SlProtocolNetAppResponse_t; + +typedef struct _SlProtocolNetAppSend_t +{ + _u16 Handle; + _u16 DataLen; /* can be data payload or metadata, depends on bit 1 in flags */ + _u32 Flags; +} SlProtocolNetAppSend_t; + +typedef struct _SlProtocolNetAppReceiveRequest_t +{ + _u16 Handle; + _u16 MaxBufferLen; + _u32 Flags; +} SlProtocolNetAppReceiveRequest_t; + +typedef struct _SlProtocolNetAppReceive_t +{ + _u16 Handle; + _u16 PayloadLen; + _u32 Flags; +} SlProtocolNetAppReceive_t; + +typedef struct +{ + _u16 Len; + _u8 Family; + _u8 Padding; +} NetAppGetHostByNameCommand_t; + +typedef struct +{ + _u16 Status; + _u16 Padding; + _u32 Ip0; + _u32 Ip1; + _u32 Ip2; + _u32 Ip3; +} NetAppGetHostByNameIPv6AsyncResponse_t; + +typedef struct +{ + _u16 Status; + _u8 Padding1; + _u8 Padding2; + _u32 Ip0; +} NetAppGetHostByNameIPv4AsyncResponse_t; + +typedef enum +{ + CTST_BSD_UDP_TX, + CTST_BSD_UDP_RX, + CTST_BSD_TCP_TX, + CTST_BSD_TCP_RX, + CTST_BSD_TCP_SERVER_BI_DIR, + CTST_BSD_TCP_CLIENT_BI_DIR, + CTST_BSD_UDP_BI_DIR, + CTST_BSD_RAW_TX, + CTST_BSD_RAW_RX, + CTST_BSD_RAW_BI_DIR, + CTST_BSD_SECURED_TCP_TX, + CTST_BSD_SECURED_TCP_RX, + CTST_BSD_SECURED_TCP_SERVER_BI_DIR, + CTST_BSD_SECURED_TCP_CLIENT_BI_DIR, + CTST_BSD_UDP_TX_IPV6, + CTST_BSD_UDP_RX_IPV6, + CTST_BSD_TCP_TX_IPV6, + CTST_BSD_TCP_RX_IPV6, + CTST_BSD_TCP_SERVER_BI_DIR_IPV6, + CTST_BSD_TCP_CLIENT_BI_DIR_IPV6, + CTST_BSD_UDP_BI_DIR_IPV6, + CTST_BSD_RAW_TX_IPV6, + CTST_BSD_RAW_RX_IPV6, + CTST_BSD_RAW_BI_DIR_IPV6, + CTST_BSD_SECURED_TCP_TX_IPV6, + CTST_BSD_SECURED_TCP_RX_IPV6, + CTST_BSD_SECURED_TCP_SERVER_BI_DIR_IPV6, + CTST_BSD_SECURED_TCP_CLIENT_BI_DIR_IPV6, + CTST_RAW_TX, + CTST_RAW_RX + }CommTest_e; + +typedef struct _sl_protocol_CtestStartCommand_t +{ + _u32 Test; + _u16 DestPort; + _u16 SrcPort; + _u32 DestAddr[4]; + _u32 PayloadSize; + _u32 Timeout; + _u32 CsEnabled; + _u32 Secure; + _u32 RawProtocol; + _u8 Reserved1[4]; +}_CtestStartCommand_t; + +typedef struct +{ + _u8 Test; + _u8 Socket; + _i16 Status; + _u32 StartTime; + _u32 EndTime; + _u16 TxKbitsSec; + _u16 RxKbitsSec; + _u32 OutOfOrderPackets; + _u32 MissedPackets; + _i16 Token; +}_CtestAsyncResponse_t; + +typedef struct +{ + _u16 Status; + _u16 RttMin; + _u16 RttMax; + _u16 RttAvg; + _u32 NumSuccsessPings; + _u32 NumSendsPings; + _u32 TestTime; +} SlPingReportResponse_t; + +typedef struct +{ + _u32 Ip; + _u32 Gateway; + _u32 Dns; +} IpV4AcquiredAsync_t; + +typedef enum +{ + ACQUIRED_IPV6_LOCAL = 1, + ACQUIRED_IPV6_GLOBAL +}IpV6AcquiredType_e; + +typedef struct +{ + _u32 Type; + _u32 Ip[4]; + _u32 Gateway[4]; + _u32 Dns[4]; +} IpV6AcquiredAsync_t; + +typedef union +{ + SlSocketCommand_t EventMask; + SlSendRecvCommand_t DeviceInit; +}_device_commands_t; + +/***************************************************************************************** +* FS structs +******************************************************************************************/ + +typedef struct +{ + _u32 FileHandle; + _u32 Offset; + _u16 Len; + _u16 Padding; +} SlFsReadCommand_t; + +typedef struct +{ + _u32 Mode; + _u32 Token; +} SlFsOpenCommand_t; + +typedef struct +{ + _u32 FileHandle; + _u32 Token; +} SlFsOpenResponse_t; + + +typedef struct +{ + _u32 FileHandle; + _u32 CertificFileNameLength; + _u32 SignatureLen; +} SlFsCloseCommand_t; + +typedef _BasicResponse_t SlFsReadResponse_t; +typedef _BasicResponse_t SlFsDeleteResponse_t; +typedef _BasicResponse_t SlFsCloseResponse_t; + +typedef struct +{ + _u16 Status; + _u16 Flags; + _u32 FileLen; + _u32 AllocatedLen; + _u32 Token[4]; + _u32 FileStorageSize; /* The total size that the file required on the storage */ + _u32 FileWriteCounter; /* number of times in which the file have been written successfully */ +} SlFsGetInfoResponse_t; + +typedef struct +{ + _u8 DeviceID; + _u8 Padding[3]; +} SlFsFormatCommand_t; + +typedef _BasicResponse_t SlFsFormatResponse_t; + +typedef struct +{ + _u32 Token; +} SlFsDeleteCommand_t; + +typedef SlFsDeleteCommand_t SlFsGetInfoCommand_t; + +typedef struct +{ + _u32 FileHandle; + _u32 Offset; + _u16 Len; + _u16 Padding; +} SlFsWriteCommand_t; + +typedef _BasicResponse_t SlFsWriteResponse_t; + +typedef struct +{ + _u32 Token; + _u8 Operation; + _u8 Padding[3]; + _u32 FileNameLength; + _u32 BufferLength; +} SlFsFileSysControlCommand_t; + +typedef struct +{ + _i32 Status; + _u32 Token; + _u32 Len; +} SlFsFileSysControlResponse_t; + +typedef struct +{ + _u16 IncludeFileFilters; + _u8 Operation; + _u8 Padding; +} SlFsBundleControlCommand_t; + +typedef struct +{ + _i32 Status; + _u8 BundleState; + _u8 Padding[3]; +} SlFsBundleControlResponse_t; + +typedef struct +{ + _u16 KeyLen; + _u16 ChunkLen; + _u32 Flags; +} SlFsProgramCommand_t; + +typedef struct +{ + _i32 Status; +} SlFsProgramResponse_t; + +typedef struct +{ + _i32 Index; /* start point is -1 */ + _u8 Count; + _u8 MaxEntryLen; + _u8 Flags; + _u8 Padding; +} SlFsGetFileListCommand_t; + +typedef struct +{ + _i32 NumOfEntriesOrError; + _i32 Index; /* -1 , nothing was read */ + _u32 OutputBufferLength; +} SlFsGetFileListResponse_t; + +/* TODO: Set MAx Async Payload length depending on flavor (Tiny, Small, etc.) */ + +#define SL_ASYNC_HTTP_SRV_EVENT_LEN 1600 /* size must be aligned to 4 */ +#ifdef SL_TINY +#define SL_ASYNC_MAX_PAYLOAD_LEN 120 /* size must be aligned to 4 */ +#elif defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) +#define SL_ASYNC_MAX_PAYLOAD_LEN SL_ASYNC_HTTP_SRV_EVENT_LEN +#else +#define SL_ASYNC_MAX_PAYLOAD_LEN 220 /* size must be aligned to 4 */ + +#endif + + + + +#define SL_ASYNC_MAX_MSG_LEN (_SL_RESP_HDR_SIZE + SL_ASYNC_MAX_PAYLOAD_LEN) + + + + +#define RECV_ARGS_SIZE (sizeof(SlSocketResponse_t)) +#define RECVFROM_IPV4_ARGS_SIZE (sizeof(SlSocketAddrAsyncIPv4Response_t)) +#define RECVFROM_IPV6_ARGS_SIZE (sizeof(SlSocketAddrAsyncIPv6Response_t)) + +#define SL_IPV4_ADDRESS_SIZE (sizeof(_u32)) +#define SL_IPV6_ADDRESS_SIZE (4 * sizeof(_u32)) + + +/***************************************************************************************** +* NetUtil structures +******************************************************************************************/ +/* Utils Set Get Header */ +typedef struct +{ + _u32 ObjId; + _i16 Status; + _u16 Option; + _u16 ValueLen; + _u8 Padding[2]; +} SlNetUtilSetGet_t; + + +/* NetUtil Command Header */ +typedef struct +{ + _u16 Cmd; + _u16 AttribLen; + _u16 InputLen; + _u16 OutputLen; +} SlNetUtilCmd_t; + +/* NetUtil Command Response Header */ +typedef struct +{ + _u32 ObjId; + _i16 Status; + _u16 Cmd; + _u16 OutputLen; + _u8 Padding[2]; +} SlNetUtilCmdRsp_t; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _SL_PROTOCOL_TYPES_H_ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/sl_socket.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/sl_socket.c new file mode 100755 index 00000000000..f5d157566a6 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/sl_socket.c @@ -0,0 +1,2011 @@ +/* + * sl_socket.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include + +static void _SlSocketBuildAddress(const SlSockAddr_t *addr, SlSocketAddrCommand_u *pCmd); +_SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf); +_SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf); + +#ifndef SL_TINY +void _SlSocketParseAddress(SlSocketAddrResponse_u *pRsp, SlSockAddr_t *addr, SlSocklen_t *addrlen); +_SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf); +_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf); +_SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf); + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) +static _i16 _SlDrvClearCtrlSocket(void); +static _i8 _SlDrvGetNextTimeoutValue(void); +#endif +#endif + +/*******************************************************************************/ +/* Functions */ +/*******************************************************************************/ + + +/* ******************************************************************************/ +/* _SlSocketBuildAddress */ +/* ******************************************************************************/ +static void _SlSocketBuildAddress(const SlSockAddr_t *addr, SlSocketAddrCommand_u *pCmd) +{ + + /* Note: parsing of family and port in the generic way for all IPV4, IPV6 and EUI48 + is possible as long as these parameters are in the same offset and size for these + three families. */ + pCmd->IpV4.FamilyAndFlags = (_u8)((addr->sa_family << 4) & 0xF0); + pCmd->IpV4.Port = ((SlSockAddrIn_t *)addr)->sin_port; + + if(SL_AF_INET == addr->sa_family) + { + pCmd->IpV4.Address = ((SlSockAddrIn_t *)addr)->sin_addr.s_addr; + } +#ifdef SL_SUPPORT_IPV6 + else + { + sl_Memcpy(pCmd->IpV6.Address, ((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, 16 ); + } +#endif +} + +/*******************************************************************************/ +/* _SlSocketParseAddress */ +/*******************************************************************************/ + +#ifndef SL_TINY +void _SlSocketParseAddress(SlSocketAddrResponse_u *pRsp, SlSockAddr_t *addr, SlSocklen_t *addrlen) +{ + /* Note: parsing of family and port in the generic way for all IPV4, IPV6 and EUI48 */ + /* is possible as long as these parameters are in the same offset and size for these */ + /* three families. */ + addr->sa_family = pRsp->IpV4.Family; + ((SlSockAddrIn_t *)addr)->sin_port = pRsp->IpV4.Port; + + *addrlen = (SL_AF_INET == addr->sa_family) ? sizeof(SlSockAddrIn_t) : sizeof(SlSockAddrIn6_t); + + if(SL_AF_INET == addr->sa_family) + { + ((SlSockAddrIn_t *)addr)->sin_addr.s_addr = pRsp->IpV4.Address; + } +#ifdef SL_SUPPORT_IPV6 + else + { + sl_Memcpy(((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, pRsp->IpV6.Address, 16); + } +#endif +} +#endif + +/*******************************************************************************/ +/* sl_Socket */ +/*******************************************************************************/ +typedef union +{ + _u32 Dummy; + SlSocketCommand_t Cmd; + SlSocketResponse_t Rsp; +}_SlSockSocketMsg_u; + +#if _SL_INCLUDE_FUNC(sl_Socket) + +static const _SlCmdCtrl_t _SlSockSocketCmdCtrl = +{ + SL_OPCODE_SOCKET_SOCKET, + (_SlArgSize_t)sizeof(SlSocketCommand_t), + (_SlArgSize_t)sizeof(SlSocketResponse_t) +}; + +_i16 sl_Socket(_i16 Domain, _i16 Type, _i16 Protocol) +{ + _SlSockSocketMsg_u Msg; + + Msg.Cmd.Domain = (_u8)Domain; + Msg.Cmd.Type = (_u8)Type; + Msg.Cmd.Protocol = (_u8)Protocol; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSockSocketCmdCtrl, &Msg, NULL)); + + if( Msg.Rsp.StatusOrLen < 0 ) + { + return ( Msg.Rsp.StatusOrLen); + } + else + { + return (_i16)((_u8)Msg.Rsp.Sd); + } +} +#endif + +/*******************************************************************************/ +/* sl_Close */ +/*******************************************************************************/ +typedef union +{ + SlCloseCommand_t Cmd; + SlSocketResponse_t Rsp; +}_SlSockCloseMsg_u; + +#if _SL_INCLUDE_FUNC(sl_Close) + +static const _SlCmdCtrl_t _SlSockCloseCmdCtrl = +{ + SL_OPCODE_SOCKET_CLOSE, + (_SlArgSize_t)sizeof(SlCloseCommand_t), + (_SlArgSize_t)sizeof(SlSocketResponse_t) +}; + +_i16 sl_Close(_i16 sd) +{ + _SlSockCloseMsg_u Msg; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + SlSocketResponse_t AsyncRsp; + _SlReturnVal_t RetVal; + _u8 bSocketInAction = FALSE; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + + Msg.Cmd.Sd = (_u8)sd; + _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketResponse_t)); + + /* check if the socket has already action in progress */ + bSocketInAction = !!(g_pCB->ActiveActionsBitmap & (1<sa_family) + { + case SL_AF_INET: + CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND; + CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); + break; +#ifndef SL_TINY +#ifdef SL_SUPPORT_IPV6 + case SL_AF_INET6: + CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND_V6; + CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); + break; +#endif +#endif + case SL_AF_RF: + default: + return SL_RET_CODE_INVALID_INPUT; + } + + Msg.Cmd.IpV4.LenOrPadding = 0; + Msg.Cmd.IpV4.Sd = (_u8)sd; + + _SlSocketBuildAddress(addr, &Msg.Cmd); + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); + + return Msg.Rsp.StatusOrLen; +} +#endif + +/*******************************************************************************/ +/* sl_Sendto */ +/*******************************************************************************/ +typedef union +{ + SlSocketAddrCommand_u Cmd; + /* no response for 'sendto' commands*/ +}_SlSendtoMsg_u; + +#if _SL_INCLUDE_FUNC(sl_SendTo) +_i16 sl_SendTo(_i16 sd, const void *pBuf, _i16 Len, _i16 flags, const SlSockAddr_t *to, SlSocklen_t tolen) +{ + _SlSendtoMsg_u Msg; + _SlCmdCtrl_t CmdCtrl = {0, 0, 0}; + _SlCmdExt_t CmdExt; + _i16 RetVal; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + /* RAW transceiver use only sl_Send */ + if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) + { + return SL_ERROR_BSD_SOC_ERROR; + } + else + { + if (Len < 1) + { + /* ignore */ + return 0; + } + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = (_u16)Len; + CmdExt.pTxPayload1 = (_u8 *)pBuf; + + switch(to->sa_family) + { + case SL_AF_INET: + CmdCtrl.Opcode = SL_OPCODE_SOCKET_SENDTO; + CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); + break; +#ifndef SL_TINY +#ifdef SL_SUPPORT_IPV6 + case SL_AF_INET6: + CmdCtrl.Opcode = SL_OPCODE_SOCKET_SENDTO_V6; + CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); + break; +#endif +#endif + case SL_AF_RF: + default: + return SL_RET_CODE_INVALID_INPUT; + } + + Msg.Cmd.IpV4.LenOrPadding = Len; + Msg.Cmd.IpV4.Sd = (_u8)sd; + _SlSocketBuildAddress(to, &Msg.Cmd); + Msg.Cmd.IpV4.FamilyAndFlags |= flags & 0x0F; + + RetVal = _SlDrvDataWriteOp((_SlSd_t)sd, &CmdCtrl, &Msg, &CmdExt); + if(SL_OS_RET_CODE_OK != RetVal) + { + return RetVal; + } + + return (_i16)Len; +} +#endif + +/*******************************************************************************/ +/* sl_Recvfrom */ +/*******************************************************************************/ +typedef union +{ + SlSendRecvCommand_t Cmd; + SlSocketAddrResponse_u Rsp; +}_SlRecvfromMsg_u; + +static const _SlCmdCtrl_t _SlRecvfomCmdCtrl = +{ + SL_OPCODE_SOCKET_RECVFROM, + (_SlArgSize_t)sizeof(SlSendRecvCommand_t), + (_SlArgSize_t)sizeof(SlSocketAddrResponse_u) +}; + +#if _SL_INCLUDE_FUNC(sl_RecvFrom) +_i16 sl_RecvFrom(_i16 sd, void *buf, _i16 Len, _i16 flags, SlSockAddr_t *from, SlSocklen_t *fromlen) +{ + _SlRecvfromMsg_u Msg; + _SlCmdExt_t CmdExt; + _i16 RetVal; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + + /* RAW transceiver use only sl_Recv */ + if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) + { + return SL_ERROR_BSD_SOC_ERROR; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = Len; + CmdExt.pRxPayload = (_u8 *)buf; + + Msg.Cmd.Sd = (_u8)sd; + Msg.Cmd.StatusOrLen = (_u16)Len; + + /* no size truncation in recv path */ + CmdExt.RxPayloadLen = (_i16)Msg.Cmd.StatusOrLen; + + Msg.Cmd.FamilyAndFlags = (_u8)(flags & 0x0F); + + if(sizeof(SlSockAddrIn_t) == *fromlen) + { + Msg.Cmd.FamilyAndFlags |= (SL_AF_INET << 4); + } + else if (sizeof(SlSockAddrIn6_t) == *fromlen) + { + Msg.Cmd.FamilyAndFlags |= (SL_AF_INET6 << 4); + } + else + { + return SL_RET_CODE_INVALID_INPUT; + } + + RetVal = _SlDrvDataReadOp((_SlSd_t)sd, (_SlCmdCtrl_t *)&_SlRecvfomCmdCtrl, &Msg, &CmdExt); + if( RetVal != SL_OS_RET_CODE_OK ) + { + return RetVal; + } + + RetVal = Msg.Rsp.IpV4.StatusOrLen; + + if(RetVal >= 0) + { + VERIFY_PROTOCOL(sd == (_i16)Msg.Rsp.IpV4.Sd); +#if 0 + _SlSocketParseAddress(&Msg.Rsp, from, fromlen); +#else + from->sa_family = Msg.Rsp.IpV4.Family; + if(SL_AF_INET == from->sa_family) + { + ((SlSockAddrIn_t *)from)->sin_port = Msg.Rsp.IpV4.Port; + ((SlSockAddrIn_t *)from)->sin_addr.s_addr = Msg.Rsp.IpV4.Address; + *fromlen = (SlSocklen_t)sizeof(SlSockAddrIn_t); + } +#ifdef SL_SUPPORT_IPV6 + else if(SL_AF_INET6 == from->sa_family) + { + VERIFY_PROTOCOL(*fromlen >= sizeof(SlSockAddrIn6_t)); + + ((SlSockAddrIn6_t *)from)->sin6_port = Msg.Rsp.IpV6.Port; + sl_Memcpy(((SlSockAddrIn6_t *)from)->sin6_addr._S6_un._S6_u32, Msg.Rsp.IpV6.Address, 16); + *fromlen = sizeof(SlSockAddrIn6_t); + } +#endif +#endif + } + + return (_i16)RetVal; +} +#endif + +/*******************************************************************************/ +/* sl_Connect */ +/*******************************************************************************/ +typedef union +{ + SlSocketAddrCommand_u Cmd; + SlSocketResponse_t Rsp; +}_SlSockConnectMsg_u; + +#if _SL_INCLUDE_FUNC(sl_Connect) +_i16 sl_Connect(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen) +{ + _SlSockConnectMsg_u Msg; + _SlReturnVal_t RetVal; + _SlCmdCtrl_t CmdCtrl = {0, (_SlArgSize_t)0, (_SlArgSize_t)sizeof(SlSocketResponse_t)}; + SlSocketResponse_t AsyncRsp; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketResponse_t)); + + switch(addr->sa_family) + { + case SL_AF_INET : + CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT; + CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); + /* Do nothing - cmd already initialized to this type */ + break; +#ifdef SL_SUPPORT_IPV6 + case SL_AF_INET6: + CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT_V6; + CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); + break; +#endif + case SL_AF_RF: + default: + return SL_RET_CODE_INVALID_INPUT; + } + + Msg.Cmd.IpV4.LenOrPadding = 0; + Msg.Cmd.IpV4.Sd = (_u8)sd; + + _SlSocketBuildAddress(addr, &Msg.Cmd); + + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, CONNECT_ID, (_u8)(sd & SL_BSD_SOCKET_ID_MASK)); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + /* send the command */ + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); + VERIFY_PROTOCOL(Msg.Rsp.Sd == (_u8)sd); + + RetVal = Msg.Rsp.StatusOrLen; + + if(SL_RET_CODE_OK == RetVal) + { +#ifndef SL_TINY + /*In case socket is non-blocking one, the async event should be received immediately */ + if( g_pCB->SocketNonBlocking & (1<<(sd & SL_BSD_SOCKET_ID_MASK) )) + { + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE)); + } + else +#endif + { + + /* wait for async and get Data Read parameters */ + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); + } + + RetVal = AsyncRsp.StatusOrLen; + + if (0 <= RetVal) + { + VERIFY_PROTOCOL(AsyncRsp.Sd == (_u8)sd); + } + } + + _SlDrvReleasePoolObj(ObjIdx); + return RetVal; +} + +#endif + + +/*******************************************************************************/ +/* _SlSocketHandleAsync_Connect */ +/*******************************************************************************/ +_SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf) +{ + SlSocketResponse_t *pMsgArgs = (SlSocketResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); + VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); + + ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; + ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = pMsgArgs->StatusOrLen; + + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + return SL_OS_RET_CODE_OK; +} + +/*******************************************************************************/ +/* _SlSocketHandleAsync_Close */ +/*******************************************************************************/ +_SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf) +{ + SlSocketResponse_t *pMsgArgs = (SlSocketResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); + VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); + + ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; + ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = pMsgArgs->StatusOrLen; + + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + return SL_OS_RET_CODE_OK; +} + +/*******************************************************************************/ +/* sl_Send */ +/*******************************************************************************/ +typedef union +{ + SlSendRecvCommand_t Cmd; + /* no response for 'sendto' commands*/ +}_SlSendMsg_u; + +static const _SlCmdCtrl_t _SlSendCmdCtrl = +{ + SL_OPCODE_SOCKET_SEND, + (_SlArgSize_t)sizeof(SlSendRecvCommand_t), + (_SlArgSize_t)0 +}; + +#if _SL_INCLUDE_FUNC(sl_Send) +_i16 sl_Send(_i16 sd, const void *pBuf, _i16 Len, _i16 flags) +{ + _SlSendMsg_u Msg; + _SlCmdExt_t CmdExt; + _i16 RetVal; + _u32 tempVal; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = (_u16)Len; + CmdExt.pTxPayload1 = (_u8 *)pBuf; + + /* Only for RAW transceiver type socket, relay the flags parameter in the 2 bytes (4 byte aligned) before the actual payload */ + if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) + { + tempVal = (_u32)flags; + CmdExt.pRxPayload = (_u8 *)&tempVal; + CmdExt.RxPayloadLen = -4; /* the (-) sign is used to mark the rx buff as output buff as well*/ + } + else + { + CmdExt.pRxPayload = NULL; + if (Len < 1) + { + /* ignore */ + return 0; + } + } + + Msg.Cmd.StatusOrLen = Len; + Msg.Cmd.Sd = (_u8)sd; + Msg.Cmd.FamilyAndFlags |= flags & 0x0F; + + RetVal = _SlDrvDataWriteOp((_u8)sd, (_SlCmdCtrl_t *)&_SlSendCmdCtrl, &Msg, &CmdExt); + if(SL_OS_RET_CODE_OK != RetVal) + { + return RetVal; + } + + return (_i16)Len; +} +#endif + +/*******************************************************************************/ +/* sl_Listen */ +/*******************************************************************************/ +typedef union +{ + SlListenCommand_t Cmd; + _BasicResponse_t Rsp; +}_SlListenMsg_u; + +#if _SL_INCLUDE_FUNC(sl_Listen) + +static const _SlCmdCtrl_t _SlListenCmdCtrl = +{ + SL_OPCODE_SOCKET_LISTEN, + (_SlArgSize_t)sizeof(SlListenCommand_t), + (_SlArgSize_t)sizeof(_BasicResponse_t), +}; + +_i16 sl_Listen(_i16 sd, _i16 backlog) +{ + _SlListenMsg_u Msg; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + + Msg.Cmd.Sd = (_u8)sd; + Msg.Cmd.Backlog = (_u8)backlog; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlListenCmdCtrl, &Msg, NULL)); + return (_i16)Msg.Rsp.status; +} +#endif + +/*******************************************************************************/ +/* sl_Accept */ +/*******************************************************************************/ +typedef union +{ + SlAcceptCommand_t Cmd; + SlSocketResponse_t Rsp; +}_SlSockAcceptMsg_u; + +#if _SL_INCLUDE_FUNC(sl_Accept) + +static const _SlCmdCtrl_t _SlAcceptCmdCtrl = +{ + SL_OPCODE_SOCKET_ACCEPT, + (_SlArgSize_t)sizeof(SlAcceptCommand_t), + (_SlArgSize_t)sizeof(_BasicResponse_t), +}; + +_i16 sl_Accept(_i16 sd, SlSockAddr_t *addr, SlSocklen_t *addrlen) +{ + _SlSockAcceptMsg_u Msg; + _SlReturnVal_t RetVal; + SlSocketAddrResponse_u AsyncRsp; + + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + + Msg.Cmd.Sd = (_u8)sd; + + if((addr != NULL) && (addrlen != NULL)) + { + /* If addr is present, addrlen has to be provided */ + Msg.Cmd.Family = (_u8)((sizeof(SlSockAddrIn_t) == *addrlen) ? SL_AF_INET : SL_AF_INET6); + } + else + { + /* In any other case, addrlen is ignored */ + Msg.Cmd.Family = (_u8)0; + } + + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, ACCEPT_ID, (_u8)sd & SL_BSD_SOCKET_ID_MASK); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + /* send the command */ + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlAcceptCmdCtrl, &Msg, NULL)); + VERIFY_PROTOCOL(Msg.Rsp.Sd == (_u8)sd); + + RetVal = Msg.Rsp.StatusOrLen; + + if(SL_OS_RET_CODE_OK == RetVal) + { +#ifndef SL_TINY + /* in case socket is non-blocking one, the async event should be received immediately */ + if( g_pCB->SocketNonBlocking & (1<<(sd & SL_BSD_SOCKET_ID_MASK) )) + { + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE)); + } + else +#endif + { + /* wait for async and get Data Read parameters */ + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); + } + + RetVal = AsyncRsp.IpV4.StatusOrLen; + + if (0 <= RetVal) + { + VERIFY_PROTOCOL(AsyncRsp.IpV4.Sd == (_u8)sd); + } + + +#if 0 /* Kept for backup */ + _SlSocketParseAddress(&AsyncRsp, addr, addrlen); +#else + if((addr != NULL) && (addrlen != NULL)) + { + addr->sa_family = AsyncRsp.IpV4.Family; + + if(SL_AF_INET == addr->sa_family) + { + if( *addrlen == (SlSocklen_t)sizeof( SlSockAddrIn_t ) ) + { + ((SlSockAddrIn_t *)addr)->sin_port = AsyncRsp.IpV4.Port; + ((SlSockAddrIn_t *)addr)->sin_addr.s_addr = AsyncRsp.IpV4.Address; + } + else + { + *addrlen = 0; + } + } +#ifdef SL_SUPPORT_IPV6 + else if(SL_AF_INET6 == addr->sa_family) + { + if( *addrlen == sizeof( SlSockAddrIn6_t ) ) + { + ((SlSockAddrIn6_t *)addr)->sin6_port = AsyncRsp.IpV6.Port ; + sl_Memcpy(((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, AsyncRsp.IpV6.Address, 16); + } + else + { + *addrlen = 0; + } + } +#endif + } +#endif + } + + _SlDrvReleasePoolObj(ObjIdx); + return (_i16)RetVal; +} +#endif + + +/*******************************************************************************/ +/* sl_Htonl */ +/*******************************************************************************/ +_u32 sl_Htonl( _u32 val ) +{ + _u32 i = 1; + _i8 *p = (_i8 *)&i; + if (p[0] == 1) /* little endian */ + { + p[0] = ((_i8* )&val)[3]; + p[1] = ((_i8* )&val)[2]; + p[2] = ((_i8* )&val)[1]; + p[3] = ((_i8* )&val)[0]; + return i; + } + else /* big endian */ + { + return val; + } +} + +/*******************************************************************************/ +/* sl_Htonl */ +/*******************************************************************************/ +_u16 sl_Htons( _u16 val ) +{ + _i16 i = 1; + _i8 *p = (_i8 *)&i; + if (p[0] == 1) /* little endian */ + { + p[0] = ((_i8* )&val)[1]; + p[1] = ((_i8* )&val)[0]; + return (_u16)i; + } + else /* big endian */ + { + return val; + } +} + +/*******************************************************************************/ +/* _SlSocketHandleAsync_Accept */ +/*******************************************************************************/ +#ifndef SL_TINY +_SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf) +{ + SlSocketAddrResponse_u *pMsgArgs = (SlSocketAddrResponse_u *)_SL_RESP_ARGS_START(pVoidBuf); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + VERIFY_PROTOCOL(( pMsgArgs->IpV4.Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); + VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); + + sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs,sizeof(SlSocketAddrResponse_u)); + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + return SL_OS_RET_CODE_OK; +} +#endif + +/*******************************************************************************/ +/* sl_Recv */ +/*******************************************************************************/ +typedef union +{ + SlSendRecvCommand_t Cmd; + SlSocketResponse_t Rsp; +}_SlRecvMsg_u; + +#if _SL_INCLUDE_FUNC(sl_Recv) + +static const _SlCmdCtrl_t _SlRecvCmdCtrl = +{ + SL_OPCODE_SOCKET_RECV, + (_SlArgSize_t)sizeof(SlSendRecvCommand_t), + (_SlArgSize_t)sizeof(SlSocketResponse_t) +}; + +_i16 sl_Recv(_i16 sd, void *pBuf, _i16 Len, _i16 flags) +{ + _SlRecvMsg_u Msg; + _SlCmdExt_t CmdExt; + _SlReturnVal_t status; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = Len; + CmdExt.pRxPayload = (_u8 *)pBuf; + + Msg.Cmd.Sd = (_u8)sd; + Msg.Cmd.StatusOrLen = (_u16)Len; + + /* no size truncation in recv path */ + CmdExt.RxPayloadLen = (_i16)Msg.Cmd.StatusOrLen; + + Msg.Cmd.FamilyAndFlags = (_u8)(flags & 0x0F); + + status = _SlDrvDataReadOp((_SlSd_t)sd, (_SlCmdCtrl_t *)&_SlRecvCmdCtrl, &Msg, &CmdExt); + if( status != SL_OS_RET_CODE_OK ) + { + return status; + } + + /* if the Device side sends less than expected it is not the Driver's role */ + /* the returned value could be smaller than the requested size */ + return (_i16)Msg.Rsp.StatusOrLen; +} +#endif + +/*******************************************************************************/ +/* sl_SetSockOpt */ +/*******************************************************************************/ +typedef union +{ + SlSetSockOptCommand_t Cmd; + SlSocketResponse_t Rsp; +}_SlSetSockOptMsg_u; + +static const _SlCmdCtrl_t _SlSetSockOptCmdCtrl = +{ + SL_OPCODE_SOCKET_SETSOCKOPT, + (_SlArgSize_t)sizeof(SlSetSockOptCommand_t), + (_SlArgSize_t)sizeof(SlSocketResponse_t) +}; + +#if _SL_INCLUDE_FUNC(sl_SetSockOpt) +_i16 sl_SetSockOpt(_i16 sd, _i16 level, _i16 optname, const void *optval, SlSocklen_t optlen) +{ + _SlSetSockOptMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = optlen; + CmdExt.pTxPayload1 = (_u8 *)optval; + + Msg.Cmd.Sd = (_u8)sd; + Msg.Cmd.Level = (_u8)level; + Msg.Cmd.OptionLen = (_u8)optlen; + Msg.Cmd.OptionName = (_u8)optname; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSetSockOptCmdCtrl, &Msg, &CmdExt)); + + return (_i16)Msg.Rsp.StatusOrLen; +} +#endif + +/*******************************************************************************/ +/* sl_GetSockOpt */ +/*******************************************************************************/ +typedef union +{ + SlGetSockOptCommand_t Cmd; + SlGetSockOptResponse_t Rsp; +}_SlGetSockOptMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_GetSockOpt) + +static const _SlCmdCtrl_t _SlGetSockOptCmdCtrl = +{ + SL_OPCODE_SOCKET_GETSOCKOPT, + (_SlArgSize_t)sizeof(SlGetSockOptCommand_t), + (_SlArgSize_t)sizeof(SlGetSockOptResponse_t) +}; + +_i16 sl_GetSockOpt(_i16 sd, _i16 level, _i16 optname, void *optval, SlSocklen_t *optlen) +{ + _SlGetSockOptMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + if (*optlen == 0) + { + return SL_EZEROLEN; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)(*optlen); + CmdExt.pRxPayload = optval; + + Msg.Cmd.Sd = (_u8)sd; + Msg.Cmd.Level = (_u8)level; + Msg.Cmd.OptionLen = (_u8)(*optlen); + Msg.Cmd.OptionName = (_u8)optname; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetSockOptCmdCtrl, &Msg, &CmdExt)); + + if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) + { + *optlen = Msg.Rsp.OptionLen; + return SL_ESMALLBUF; + } + else + { + *optlen = (_u8)CmdExt.ActualRxPayloadLen; + } + return (_i16)Msg.Rsp.Status; +} +#endif + +/********************************************************************************/ +/* sl_Select */ +/* ******************************************************************************/ +#ifndef SL_TINY +#if _SL_INCLUDE_FUNC(sl_Select) + +typedef union +{ + SlSelectCommand_t Cmd; + _BasicResponse_t Rsp; +}_SlSelectMsg_u; + +static const _SlCmdCtrl_t _SlSelectCmdCtrl = +{ + SL_OPCODE_SOCKET_SELECT, + (_SlArgSize_t)sizeof(SlSelectCommand_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +/********************************************************************************/ +/* SL_SOCKET_FD_SET */ +/* ******************************************************************************/ +void SL_SOCKET_FD_SET(_i16 fd, SlFdSet_t *fdset) +{ + fdset->fd_array[0] |= (1<< (fd & SL_BSD_SOCKET_ID_MASK)); +} + +/*******************************************************************************/ +/* SL_SOCKET_FD_CLR */ +/*******************************************************************************/ +void SL_SOCKET_FD_CLR(_i16 fd, SlFdSet_t *fdset) +{ + fdset->fd_array[0] &= ~(1<< (fd & SL_BSD_SOCKET_ID_MASK)); +} + +/*******************************************************************************/ +/* SL_SOCKET_FD_ISSET */ +/*******************************************************************************/ +_i16 SL_SOCKET_FD_ISSET(_i16 fd, SlFdSet_t *fdset) +{ + if( fdset->fd_array[0] & (1<< (fd & SL_BSD_SOCKET_ID_MASK)) ) + { + return 1; + } + return 0; +} + +/*******************************************************************************/ +/* SL_SOCKET_FD_ZERO */ +/*******************************************************************************/ +void SL_SOCKET_FD_ZERO(SlFdSet_t *fdset) +{ + fdset->fd_array[0] = 0; +} + +#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) + +/*******************************************************************************/ +/* Multiple Select */ +/*******************************************************************************/ + +/* Multiple Select Defines */ +#define LOCAL_CTRL_PORT (3632) +#define SL_LOOPBACK_ADDR (0x0100007F) +#define DUMMY_BUF_SIZE (4) +#define CTRL_SOCK_FD (((_u16)(1)) << g_pCB->MultiSelectCB.CtrlSockFD) +#define SELECT_TIMEOUT ((_u16)0) +#define SELECT_NO_TIMEOUT (0xFFFFFFFF) + +/* Multiple Select Structures */ +_SlSelectMsg_u Msg; + +static const SlSockAddrIn_t _SlCtrlSockAddr = +{ + SL_AF_INET, + LOCAL_CTRL_PORT, + {SL_INADDR_ANY}, + {0,0,0,0,0,0,0,0} +}; + +static const SlSockAddrIn_t _SlCtrlSockRelease = +{ + SL_AF_INET, + LOCAL_CTRL_PORT, + {SL_LOOPBACK_ADDR}, + {0,0,0,0,0,0,0,0} +}; + +/*******************************************************************************/ +/* CountSetBits */ +/*******************************************************************************/ +static inline _u8 CountSetBits(_u16 fdList) +{ + _u8 Count = 0; + + while(fdList) + { + Count += (fdList & ((_u16)1)); + fdList = fdList >> 1; + } + + return Count; +} + +/*******************************************************************************/ +/* _SlSocketHandleAsync_Select */ +/*******************************************************************************/ +_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf) +{ + _SlReturnVal_t RetVal; + SlSelectAsyncResponse_t *pMsgArgs = (SlSelectAsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); + _u8 RegIdx = 0; + _u32 time_now; + _u8 TimeoutEvent = 0; + _u16 SelectEvent = 0; + _u8 PendingSelect = FALSE; + + _SlDrvMemZero(&Msg, sizeof(_SlSelectMsg_u)); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); + + /* Check if this context was triggered by a 'select joiner' only, + * without timeout occurring, in order to launch the next select as quick as possible */ + if((CTRL_SOCK_FD == pMsgArgs->ReadFds) && (pMsgArgs->Status != SELECT_TIMEOUT)) + { + RetVal = _SlDrvClearCtrlSocket(); + Msg.Cmd.ReadFds = g_pCB->MultiSelectCB.readsds; + Msg.Cmd.WriteFds = g_pCB->MultiSelectCB.writesds; + Msg.Cmd.ReadFds |= CTRL_SOCK_FD; + Msg.Cmd.tv_sec = 0xFFFF; + Msg.Cmd.tv_usec = 0xFFFF; + + RegIdx = _SlDrvGetNextTimeoutValue(); + + SL_TRACE3(DBG_MSG, MSG_312, "\n\rAdded caller: call Select with: Write:%x Sec:%d uSec:%d\n\r", + Msg.Cmd.WriteFds, Msg.Cmd.tv_sec, Msg.Cmd.tv_usec); + + RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL); + + SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + return RetVal; + } + + /* If we're triggered by the NWP, take time-stamps to monitor the time-outs */ + time_now = ((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10); + + /* If it's a proper select response, or if timeout occurred, release the relevant waiters */ + for(RegIdx = 0 ; RegIdx < MAX_CONCURRENT_ACTIONS ; RegIdx++) + { + if(g_pCB->MultiSelectCB.SelectEntry[RegIdx] != NULL) + { + /* In case a certain entry has 100 mSec or less until it's timeout, the overhead + * caused by calling select again with it's fd lists is redundant, just return a time-out. */ + + TimeoutEvent = ((time_now + 100) >= g_pCB->MultiSelectCB.SelectEntry[RegIdx]->TimeStamp); + + if(pMsgArgs->Status != SELECT_TIMEOUT) + { + SelectEvent = ((g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist & pMsgArgs->ReadFds) || + (g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist & pMsgArgs->WriteFds)); + } + + if(SelectEvent || TimeoutEvent) + { + + + /* Clear the global select socket descriptor bitmaps */ + g_pCB->MultiSelectCB.readsds &= ~(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); + g_pCB->MultiSelectCB.writesds &= ~(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); + + if(SelectEvent) + { + /* set the corresponding fd lists. */ + g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFds = (pMsgArgs->ReadFds & g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); + g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFds = (pMsgArgs->WriteFds & g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); + g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFdsCount = CountSetBits(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); + g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFdsCount = CountSetBits(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); + g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.Status = (g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFdsCount + + g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFdsCount); + } + else + { + g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.Status = SELECT_TIMEOUT; + } + + g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFds &= ~(CTRL_SOCK_FD); + + /* Signal the waiting caller. */ + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->MultiSelectCB.SelectEntry[RegIdx]->ObjIdx].SyncObj); + + /* Clean it's table entry */ + g_pCB->MultiSelectCB.SelectEntry[RegIdx] = NULL; + } + else + { + PendingSelect = TRUE; + } + } + } + + /* In case where A caller was added, but also some sockfd were set on the NWP, + * We clear the control socket. */ + if((pMsgArgs->ReadFds & CTRL_SOCK_FD) && (pMsgArgs->Status != SELECT_TIMEOUT)) + { + RetVal = _SlDrvClearCtrlSocket(); + } + + /* If more readers/Writers are present, send select again */ + if((0 != g_pCB->MultiSelectCB.readsds) || (0 != g_pCB->MultiSelectCB.writesds) || (TRUE == PendingSelect)) + { + Msg.Cmd.ReadFds = g_pCB->MultiSelectCB.readsds; + Msg.Cmd.ReadFds |= CTRL_SOCK_FD; + Msg.Cmd.WriteFds = g_pCB->MultiSelectCB.writesds; + + /* Set timeout to blocking, in case there is no caller with timeout value. */ + Msg.Cmd.tv_sec = 0xFFFF; + Msg.Cmd.tv_usec = 0xFFFF; + + /* Get the next awaiting timeout caller */ + RegIdx = _SlDrvGetNextTimeoutValue(); + + SL_TRACE3(DBG_MSG, MSG_312, "\n\rRelease Partial: call Select with: Read:%x Sec:%d uSec:%d\n\r", + Msg.Cmd.ReadFds, Msg.Cmd.tv_sec, Msg.Cmd.tv_usec); + + RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL); + } + else + { + while(g_pCB->MultiSelectCB.ActiveWaiters) + { + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->MultiSelectCB.SelectSyncObj); + g_pCB->MultiSelectCB.ActiveWaiters--; + } + + g_pCB->MultiSelectCB.ActiveSelect = FALSE; + + SL_TRACE1(DBG_MSG, MSG_312, "\n\rSelect isn't Active: %d\n\r", g_pCB->MultiSelectCB.ActiveSelect); + } + + SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + return SL_OS_RET_CODE_OK; +} + +/*******************************************************************************/ +/* SlDrvGetNextTimeoutValue */ +/*******************************************************************************/ +static _i8 _SlDrvGetNextTimeoutValue(void) +{ + _u32 time_now; + _i8 Found = -1; + _u8 idx = 0; + + /* Take a timestamp */ + time_now = ((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10); + + /* Go through all waiting time-outs, and select the closest */ + for(idx = 0 ; idx < MAX_CONCURRENT_ACTIONS ; idx++) + { + if(NULL != g_pCB->MultiSelectCB.SelectEntry[idx]) + { + /* Check if the time-stamp is bigger or equal to current time, and if it's the minimal time-stamp (closest event) */ + if(g_pCB->MultiSelectCB.SelectEntry[idx]->TimeStamp >= time_now) + { + if(Found == -1) + { + Found = idx; + } + else + { + if(g_pCB->MultiSelectCB.SelectEntry[idx]->TimeStamp <= g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp) + { + Found = idx; + } + } + } + } + } + + /* If a non-wait-forever index was found, calculate delta until closest event */ + if(g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp != SELECT_NO_TIMEOUT) + { + _i32 delta = (g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp - time_now); + + if(delta >= 0) + { + Msg.Cmd.tv_sec = (delta / 1000); + Msg.Cmd.tv_usec = (((delta % 1000) * 1000) >> 10); + } + else + { + /* if delta time calculated is negative, call a non-blocking select */ + Msg.Cmd.tv_sec = 0; + Msg.Cmd.tv_usec = 0; + } + } + + return Found; +} + +/*******************************************************************************/ +/* _SlDrvClearCtrlSocket */ +/*******************************************************************************/ +static _i16 _SlDrvClearCtrlSocket(void) +{ + _SlRecvfromMsg_u Msg; + _SlCmdExt_t CmdExt; + _u8 dummyBuf[DUMMY_BUF_SIZE]; + _SlReturnVal_t RetVal; + + /* Prepare a recvFrom Cmd */ + _SlDrvResetCmdExt(&CmdExt); + _SlDrvMemZero(&Msg, sizeof(_SlRecvfromMsg_u)); + + CmdExt.RxPayloadLen = DUMMY_BUF_SIZE; + CmdExt.pRxPayload = (_u8 *)&dummyBuf; + + Msg.Cmd.Sd = (_u8)g_pCB->MultiSelectCB.CtrlSockFD; + Msg.Cmd.StatusOrLen = (_u16)DUMMY_BUF_SIZE; + Msg.Cmd.FamilyAndFlags = (SL_AF_INET << 4); + + RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlRecvfomCmdCtrl, &Msg, &CmdExt); + + return RetVal; +} + +/*******************************************************************************/ +/* _SlDrvOpenCtrlSocket */ +/*******************************************************************************/ +static _i16 _SlDrvOpenCtrlSocket(void) +{ + _i16 retVal; + + /* In case a control socket is already open, return. */ + if(g_pCB->MultiSelectCB.CtrlSockFD != 0xFF) + { + return 0; + } + + /* Open a local control socket */ + retVal = sl_Socket(SL_AF_INET, SL_SOCK_DGRAM, 0); + + if(retVal == SL_ERROR_BSD_ENSOCK) + { + return 0; + } + else if(retVal < 0) + { + return retVal; + } + else + { + g_pCB->MultiSelectCB.CtrlSockFD = retVal; + } + + /* Bind it to local control port */ + retVal = sl_Bind(g_pCB->MultiSelectCB.CtrlSockFD, (const SlSockAddr_t *)&_SlCtrlSockAddr, sizeof(SlSockAddrIn_t)); + + return retVal; +} + +/*******************************************************************************/ +/* _SlDrvCloseCtrlSocket */ +/*******************************************************************************/ +static _i16 _SlDrvCloseCtrlSocket(void) +{ + _i16 retVal = 0; + _i16 sockfd = 0xFF; + + /* Close the internal Control socket */ + sockfd = g_pCB->MultiSelectCB.CtrlSockFD; + + if(sockfd != 0xFF) + { + /* Close the local control socket */ + retVal = sl_Close(sockfd); + } + + g_pCB->MultiSelectCB.CtrlSockFD = 0xFF; + + if(retVal < 0) + { + return SL_ERROR_BSD_SOC_ERROR; + } + + return retVal; +} + +/*******************************************************************************/ +/* to_Msec */ +/*******************************************************************************/ +static inline _u32 to_mSec(struct SlTimeval_t* timeout) +{ + return (((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10) + (timeout->tv_sec * 1000) + (timeout->tv_usec / 1000)); +} + +/*******************************************************************************/ +/* _SlDrvUnRegisterForSelectAsync */ +/*******************************************************************************/ +static _i16 _SlDrvUnRegisterForSelectAsync(_SlSelectEntry_t* pEntry, _u8 SelectInProgress) +{ + SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); + + /* Clear the global select fd lists */ + g_pCB->MultiSelectCB.readsds &= ~(pEntry->readlist); + g_pCB->MultiSelectCB.writesds &= ~(pEntry->writelist); + + /* Empty the caller's table entry. */ + g_pCB->MultiSelectCB.SelectEntry[pEntry->ObjIdx] = NULL; + + if(g_pCB->MultiSelectCB.ActiveSelect == FALSE) + { + _SlDrvCloseCtrlSocket(); + } + + SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); + + /* Release it's pool object */ + _SlDrvReleasePoolObj(pEntry->ObjIdx); + + return SL_ERROR_BSD_SOC_ERROR; +} + +/*******************************************************************************/ +/* _SlDrvRegisterForSelectAsync */ +/*******************************************************************************/ +static _i16 _SlDrvRegisterForSelectAsync(_SlSelectEntry_t* pEntry, _SlSelectMsg_u* pMsg, struct SlTimeval_t *timeout, _u8 SelectInProgress) +{ + _SlReturnVal_t _RetVal = 0; + _u8 dummyBuf[4] = {0}; + + /* Register this caller's parameters */ + pEntry->readlist = pMsg->Cmd.ReadFds; + pEntry->writelist = pMsg->Cmd.WriteFds; + + if((pMsg->Cmd.tv_sec != 0xFFFF) && (timeout != NULL)) + { + pEntry->TimeStamp = to_mSec(timeout); + } + else + { + pEntry->TimeStamp = SELECT_NO_TIMEOUT; + } + + g_pCB->MultiSelectCB.readsds |= pMsg->Cmd.ReadFds; + g_pCB->MultiSelectCB.writesds |= pMsg->Cmd.WriteFds; + g_pCB->MultiSelectCB.SelectEntry[pEntry->ObjIdx] = pEntry; + + SL_TRACE3(DBG_MSG, MSG_312, "\n\rRegistered: Objidx:%d, sec:%d, usec%d\n\r", + pEntry->ObjIdx, pMsg->Cmd.tv_sec, pMsg->Cmd.tv_usec); + + if((!SelectInProgress) || (g_pCB->MultiSelectCB.ActiveSelect == FALSE)) + { + /* Add ctrl socket to the read list for this 'select' call */ + pMsg->Cmd.ReadFds |= CTRL_SOCK_FD; + + SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); + + _RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, pMsg, NULL); + + if((_RetVal == SL_RET_CODE_OK) && (g_pCB->MultiSelectCB.CtrlSockFD != 0xFF)) + { + /* Signal any waiting "Select" callers */ + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->MultiSelectCB.SelectSyncObj); + } + } + else + { + SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); + + /* Wait here to be signaled by a successfully completed select caller */ + if (_SlDrvIsSpawnOwnGlobalLock()) + { + while (TRUE) + { + /* If we are in spawn context, this is an API which was called from event handler, + read any async event and check if we got signaled */ + _SlInternalSpawnWaitForEvent(); + /* is it mine? */ + if (0 == sl_SyncObjWait(&g_pCB->MultiSelectCB.SelectSyncObj, SL_OS_NO_WAIT)) + { + break; + } + } + } + else + { + SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->MultiSelectCB.SelectSyncObj); + } + + _RetVal = sl_SendTo(g_pCB->MultiSelectCB.CtrlSockFD, + &dummyBuf[0], + sizeof(dummyBuf), + 0, + (const SlSockAddr_t *)&_SlCtrlSockRelease, + sizeof(SlSockAddrIn_t)); + } + + return _RetVal; +} + +/********************************************************************************/ +/* sl_Select */ +/* ******************************************************************************/ +_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout) +{ + _i16 ret; + _u8 isCaller = FALSE; + _SlSelectMsg_u Msg; + _SlSelectEntry_t SelectParams; + _u8 SelectInProgress = FALSE; + + /* verify that this API is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + _SlDrvMemZero(&Msg, sizeof(_SlSelectMsg_u)); + _SlDrvMemZero(&SelectParams, sizeof(_SlSelectEntry_t)); + + Msg.Cmd.Nfds = (_u8)nfds; + + if(readsds) + { + Msg.Cmd.ReadFds = (_u16)readsds->fd_array[0]; + } + + if(writesds) + { + Msg.Cmd.WriteFds = (_u16)writesds->fd_array[0]; + } + + if(NULL == timeout) + { + Msg.Cmd.tv_sec = 0xffff; + Msg.Cmd.tv_usec = 0xffff; + } + else + { + if(0xffff <= timeout->tv_sec) + { + Msg.Cmd.tv_sec = 0xffff; + } + else + { + Msg.Cmd.tv_sec = (_u16)timeout->tv_sec; + } + + /* this divides by 1024 to fit the result in a int16_t. + * Upon receiving, the NWP multiply this value by 1024. */ + timeout->tv_usec = (timeout->tv_usec >> 10); + + if(0xffff <= timeout->tv_usec) + { + Msg.Cmd.tv_usec = 0xffff; + } + else + { + Msg.Cmd.tv_usec = (_u16)timeout->tv_usec; + } + } + + while(FALSE == isCaller) + { + SelectParams.ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&SelectParams.Response, SELECT_ID, SL_MAX_SOCKETS); + + if(MAX_CONCURRENT_ACTIONS == SelectParams.ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); + + /* Check if no other 'Select' calls are in progress */ + if(FALSE == g_pCB->MultiSelectCB.ActiveSelect) + { + g_pCB->MultiSelectCB.ActiveSelect = TRUE; + } + else + { + SelectInProgress = TRUE; + } + + if(!SelectInProgress) + { + ret = _SlDrvOpenCtrlSocket(); + + if(ret < 0) + { + _SlDrvCloseCtrlSocket(); + g_pCB->MultiSelectCB.ActiveSelect = FALSE; + SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); + _SlDrvReleasePoolObj(SelectParams.ObjIdx); + return ret; + } + else + { + /* All conditions are met for calling "Select" */ + isCaller = TRUE; + } + } + else if(g_pCB->MultiSelectCB.CtrlSockFD == 0xFF) + { + _SlDrvReleasePoolObj(SelectParams.ObjIdx); + + /* This is not a first select caller and all sockets are open, + * caller is expected to wait until select is inactive, + * before trying to register again. */ + g_pCB->MultiSelectCB.ActiveWaiters++; + + SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); + + /* Wait here to be signaled by a successfully completed select caller */ + if (_SlDrvIsSpawnOwnGlobalLock()) + { + while (TRUE) + { + /* If we are in spawn context, this is an API which was called from event handler, + read any async event and check if we got signaled */ + _SlInternalSpawnWaitForEvent(); + /* is it mine? */ + if (0 == sl_SyncObjWait(&g_pCB->MultiSelectCB.SelectSyncObj, SL_OS_NO_WAIT)) + { + break; + } + } + } + else + { + SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->MultiSelectCB.SelectSyncObj); + } + + + if((_i16)g_pCB->MultiSelectCB.SelectCmdResp.status != SL_RET_CODE_OK) + { + return (_i16)(g_pCB->MultiSelectCB.SelectCmdResp.status); + } + + SelectInProgress = FALSE; + } + else + { + /* All conditions are met for calling "Select" */ + isCaller = TRUE; + } + } + + /* Register this caller details for an select Async event. + * SelectLockObj is released inside this function, + * right before sending 'Select' command. */ + ret = _SlDrvRegisterForSelectAsync(&SelectParams, &Msg, timeout, SelectInProgress); + + if(ret < 0) + { + return (_SlDrvUnRegisterForSelectAsync(&SelectParams, SelectInProgress)); + } + + /* Wait here for a Async event, or command response in case select fails.*/ + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(SelectParams.ObjIdx, 0, 0)); + _SlDrvReleasePoolObj(SelectParams.ObjIdx); + + ret = (_i16)g_pCB->MultiSelectCB.SelectCmdResp.status; + + if(ret == SL_RET_CODE_OK) + { + ret = (_i16)SelectParams.Response.Status; + + if(ret > SELECT_TIMEOUT) + { + if(readsds) + { + readsds->fd_array[0] = SelectParams.Response.ReadFds; + } + + if(writesds) + { + writesds->fd_array[0] = SelectParams.Response.WriteFds; + } + } + } + + return ret; +} + +#else + +/*******************************************************************************/ +/* _SlSocketHandleAsync_Select */ +/*******************************************************************************/ +_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf) +{ + SlSelectAsyncResponse_t *pMsgArgs = (SlSelectAsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); +#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) + SlSockTriggerEvent_t SockTriggerEvent; +#endif + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); + + sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(SlSelectAsyncResponse_t)); + +#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) + if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) + { + if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_WAITING_FOR_RESP) + { + + SockTriggerEvent.Event = SL_SOCKET_TRIGGER_EVENT_SELECT; + SockTriggerEvent.EventData = 0; + + g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_RESP_RECEIVED; + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + /* call the user handler */ + _SlDrvHandleSocketTriggerEvents(&SockTriggerEvent); + + return SL_OS_RET_CODE_OK; + } + else + { + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + } + } + else +#endif + { + + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + } + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + return SL_OS_RET_CODE_OK; +} + +_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout) +{ + _SlSelectMsg_u Msg; + SlSelectAsyncResponse_t AsyncRsp; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; +#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) + _u8 IsNonBlocking = FALSE; +#endif + + /* verify that this API is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + +#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) + if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) + { + if( NULL != timeout ) + { + /* Set that we are in Non-Blocking mode */ + if ( (0 == timeout->tv_sec) && (0 == timeout->tv_usec) ) + { + IsNonBlocking = TRUE; + } + else + { + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + /* If there is a trigger select running in the progress abort the new blocking request */ + if (g_pCB->SocketTriggerSelect.Info.State > SOCK_TRIGGER_READY) + { + SL_DRV_PROTECTION_OBJ_UNLOCK(); + return SL_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR; + } + + SL_DRV_PROTECTION_OBJ_UNLOCK(); + } + + if (IsNonBlocking == TRUE) + { + /* return EAGAIN if we alreay have select trigger in progress */ + if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_WAITING_FOR_RESP) + { + return SL_ERROR_BSD_EAGAIN; + } + /* return the stored response if already received */ + else if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_RESP_RECEIVED) + { + if( ((_i16)g_pCB->SocketTriggerSelect.Resp.Status) >= 0 ) + { + if( readsds ) + { + readsds->fd_array[0] = g_pCB->SocketTriggerSelect.Resp.ReadFds; + } + if( writesds ) + { + writesds->fd_array[0] = g_pCB->SocketTriggerSelect.Resp.WriteFds; + } + } + + /* Now relaese the pool object */ + _SlDrvReleasePoolObj(g_pCB->SocketTriggerSelect.Info.ObjPoolIdx); + + g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = MAX_CONCURRENT_ACTIONS; + + /* Reset the socket select trigger object */ + g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_READY; + + return (_i16)g_pCB->SocketTriggerSelect.Resp.Status; + } + } + } + } +#endif + + Msg.Cmd.Nfds = (_u8)nfds; + Msg.Cmd.ReadFdsCount = 0; + Msg.Cmd.WriteFdsCount = 0; + + Msg.Cmd.ReadFds = 0; + Msg.Cmd.WriteFds = 0; + + + if( readsds ) + { + Msg.Cmd.ReadFds = (_u16)readsds->fd_array[0]; + } + if( writesds ) + { + Msg.Cmd.WriteFds = (_u16)writesds->fd_array[0]; + } + if( NULL == timeout ) + { + Msg.Cmd.tv_sec = 0xffff; + Msg.Cmd.tv_usec = 0xffff; + } + else + { + if( 0xffff <= timeout->tv_sec ) + { + Msg.Cmd.tv_sec = 0xffff; + } + else + { + Msg.Cmd.tv_sec = (_u16)timeout->tv_sec; + } + + /* convert to milliseconds */ + timeout->tv_usec = timeout->tv_usec >> 10; + + if( 0xffff <= timeout->tv_usec ) + { + Msg.Cmd.tv_usec = 0xffff; + } + else + { + Msg.Cmd.tv_usec = (_u16)timeout->tv_usec; + } + + } + + /* Use Obj to issue the command, if not available try later */ + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, SELECT_ID, SL_MAX_SOCKETS); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + /* send the command */ + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL)); + + if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) + { + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); + + Msg.Rsp.status = (_i16)AsyncRsp.Status; + + /* this code handles the socket trigger mode case */ +#if((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) + if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) + { + /* if no data returned and we are in trigger mode, + send another select cmd but now with timeout infinite, + and return immediately with EAGAIN to the user */ + if ((IsNonBlocking == TRUE) && (AsyncRsp.Status == 0)) + { + /* set the select trigger-in-progress bit */ + g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_WAITING_FOR_RESP; + + Msg.Cmd.tv_sec = 0xffff; + Msg.Cmd.tv_usec = 0xffff; + + /* Release pool object and try to take another call */ + _SlDrvReleasePoolObj(ObjIdx); + + /* Use Obj to issue the command, if not available try later */ + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&g_pCB->SocketTriggerSelect.Resp, SELECT_ID, SL_MAX_SOCKETS); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + /* Save the pool index to be released only after the user read the response */ + g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = ObjIdx; + + /* send the command */ + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL)); + return SL_ERROR_BSD_EAGAIN; + + } + } +#endif + + if( ((_i16)Msg.Rsp.status) >= 0 ) + { + if( readsds ) + { + readsds->fd_array[0] = AsyncRsp.ReadFds; + } + if( writesds ) + { + writesds->fd_array[0] = AsyncRsp.WriteFds; + } + } + } + + _SlDrvReleasePoolObj(ObjIdx); + return (_i16)Msg.Rsp.status; +} + +#endif /* defined(SL_PLATFORM_MULTI_THREADED) || !defined(slcb_SocketTriggerEventHandler) */ +#endif /* _SL_INCLUDE_FUNC(sl_Select) */ +#endif /* SL_TINY */ + +/*******************************************************************************/ +/* sl_StartTLS */ +/*******************************************************************************/ +#if _SL_INCLUDE_FUNC(sl_StartTLS) +_i16 sl_StartTLS(_i16 sd) +{ + _SlReturnVal_t RetVal; + SlSocketAsyncEvent_t AsyncRsp; + _u32 tempValue; + _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); + _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketAsyncEvent_t)); + + ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, START_TLS_ID, (_u8)(sd & SL_BSD_SOCKET_ID_MASK)); + + if (MAX_CONCURRENT_ACTIONS == ObjIdx) + { + return SL_POOL_IS_EMPTY; + } + + /* send Start TLS to sl_SetSockOpt */ + RetVal = sl_SetSockOpt(sd, SL_SOL_SOCKET, SL_SO_STARTTLS, &tempValue, sizeof(tempValue)); + + if(SL_RET_CODE_OK == RetVal) + { + /* wait for async and get Data Read parameters */ + VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); + + VERIFY_PROTOCOL(AsyncRsp.Sd == (_u8)sd); + + if (SL_SSL_NOTIFICATION_CONNECTED_SECURED == AsyncRsp.Type) + { + RetVal = SL_RET_CODE_OK; + } + else + { + RetVal = AsyncRsp.Val; + } + } + + _SlDrvReleasePoolObj(ObjIdx); + return RetVal; +} + +/*******************************************************************************/ +/* _SlSocketHandleAsync_StartTLS */ +/*******************************************************************************/ +_SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf) +{ + SlSocketAsyncEvent_t *pMsgArgs = (SlSocketAsyncEvent_t *)((_u32)pVoidBuf+sizeof(_u32)); + + SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); + + VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); + VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); + + ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; + ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Type = pMsgArgs->Type; + ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Val = pMsgArgs->Val; + + SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); + SL_DRV_PROTECTION_OBJ_UNLOCK(); + + return SL_OS_RET_CODE_OK; +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.c new file mode 100755 index 00000000000..169f54ce306 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.c @@ -0,0 +1,134 @@ +/* + * spawn.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include + +#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) + +typedef struct +{ + _SlSyncObj_t SyncObj; + _u8 IrqWriteCnt; + _u8 IrqReadCnt; + void* pIrqFuncValue; + +#ifdef SL_PLATFORM_MULTI_THREADED + _u32 ThreadId; +#endif +}_SlInternalSpawnCB_t; + +_SlInternalSpawnCB_t g_SlInternalSpawnCB; + +_u8 _SlInternalIsItSpawnThread(_u32 ThreadId) +{ + return (ThreadId == g_SlInternalSpawnCB.ThreadId); +} + +void _SlInternalSpawnWaitForEvent(void) +{ + + sl_SyncObjWait(&g_SlInternalSpawnCB.SyncObj, SL_OS_WAIT_FOREVER); + + /* + * call the processQ function will handle the pending async + * events already read from NWP, and only wait for handling + * the events that have been read only during command execution. */ + _SlSpawnMsgListProcess(); + + /* handle IRQ requests */ + while (g_SlInternalSpawnCB.IrqWriteCnt != g_SlInternalSpawnCB.IrqReadCnt) + { + /* handle the ones that came from ISR context*/ + _SlDrvMsgReadSpawnCtx(g_SlInternalSpawnCB.pIrqFuncValue); + g_SlInternalSpawnCB.IrqReadCnt++; + } + +} + +void* _SlInternalSpawnTaskEntry() +{ + + /* create and clear the sync object */ + sl_SyncObjCreate(&g_SlInternalSpawnCB.SyncObj,"SlSpawnSync"); + sl_SyncObjWait(&g_SlInternalSpawnCB.SyncObj,SL_OS_NO_WAIT); + + g_SlInternalSpawnCB.ThreadId = 0xFFFFFFFF; + +#ifdef SL_PLATFORM_MULTI_THREADED + g_SlInternalSpawnCB.ThreadId = (_i32)pthread_self(); +#endif + + g_SlInternalSpawnCB.IrqWriteCnt = 0; + g_SlInternalSpawnCB.IrqReadCnt = 0; + g_SlInternalSpawnCB.pIrqFuncValue = NULL; + + /* here we ready to execute entries */ + while (TRUE) + { + /* wait for event */ + _SlInternalSpawnWaitForEvent(); + } +} + +_i16 _SlInternalSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags) +{ + _i16 Res = 0; + + /* Increment the counter that specifies that async event has recived + from interrupt context and should be handled by the internal spawn task */ + if ((flags & SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER) || (flags & SL_SPAWN_FLAG_FROM_CMD_CTX)) + { + g_SlInternalSpawnCB.IrqWriteCnt++; + g_SlInternalSpawnCB.pIrqFuncValue = pValue; + SL_DRV_SYNC_OBJ_SIGNAL(&g_SlInternalSpawnCB.SyncObj); + return Res; + } + else if (flags & SL_SPAWN_FLAG_FROM_CMD_PROCESS) + { + SL_DRV_SYNC_OBJ_SIGNAL(&g_SlInternalSpawnCB.SyncObj); + } + + return Res; +} + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.h new file mode 100755 index 00000000000..e9410bd3e56 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/spawn.h @@ -0,0 +1,60 @@ +/* + * spawn.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ +#ifndef __SPAWN_H__ +#define __SPAWN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) + +extern void* _SlInternalSpawnTaskEntry(); +extern _i16 _SlInternalSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); +extern _u8 _SlInternalIsItSpawnThread(_u32 ThreadId); +#undef sl_Spawn +#define sl_Spawn(pEntry,pValue,flags) _SlInternalSpawn(pEntry,pValue,flags) + +#undef _SlTaskEntry +#define _SlTaskEntry _SlInternalSpawnTaskEntry + +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/wlan.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/wlan.c new file mode 100755 index 00000000000..b660f924bc5 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/source/wlan.c @@ -0,0 +1,1208 @@ +/* + * wlan.c - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ +#define MAX_SSID_LEN (32) +#define MAX_KEY_LEN (64) +#define MAX_USER_LEN (64) +#define MAX_ANON_USER_LEN (64) +#define MAX_SMART_CONFIG_KEY (16) + + +/***************************************************************************** +sl_WlanConnect +*****************************************************************************/ +typedef struct +{ + SlWlanConnectEapCommand_t Args; + _i8 Strings[SL_WLAN_SSID_MAX_LENGTH + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; +}_WlanConnectCmd_t; + +typedef union +{ + _WlanConnectCmd_t Cmd; + _BasicResponse_t Rsp; +}_SlWlanConnectMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_WlanConnect) +_i16 sl_WlanConnect(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams) +{ + _SlWlanConnectMsg_u Msg; + _SlCmdCtrl_t CmdCtrl = {0,0,0}; + + _SlDrvMemZero(&Msg, (_u16)sizeof(_SlWlanConnectMsg_u)); + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + CmdCtrl.TxDescLen = 0;/* init */ + CmdCtrl.RxDescLen = (_SlArgSize_t)sizeof(_BasicResponse_t); + + /* verify SSID length */ + VERIFY_PROTOCOL(NameLen <= SL_WLAN_SSID_MAX_LENGTH); + /* verify SSID is not NULL */ + if( NULL == pName ) + { + return SL_INVALPARAM; + } + /* update SSID length */ + Msg.Cmd.Args.Common.SsidLen = (_u8)NameLen; + + /* Profile with no security */ + /* Enterprise security profile */ + if (NULL != pSecExtParams) + { + /* Update command opcode */ + CmdCtrl.Opcode = SL_OPCODE_WLAN_WLANCONNECTEAPCOMMAND; + CmdCtrl.TxDescLen += sizeof(SlWlanConnectEapCommand_t); + /* copy SSID */ + sl_Memcpy(EAP_SSID_STRING(&Msg), pName, NameLen); + CmdCtrl.TxDescLen += NameLen; + /* Copy password if supplied */ + if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) + { + /* update security type */ + Msg.Cmd.Args.Common.SecType = pSecParams->Type; + /* verify key length */ + if (pSecParams->KeyLen > MAX_KEY_LEN) + { + return SL_INVALPARAM; + } + /* update key length */ + Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; + ARG_CHECK_PTR(pSecParams->Key); + /* copy key */ + sl_Memcpy(EAP_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); + CmdCtrl.TxDescLen += pSecParams->KeyLen; + } + else + { + Msg.Cmd.Args.Common.PasswordLen = 0; + } + + ARG_CHECK_PTR(pSecExtParams); + /* Update Eap bitmask */ + Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; + /* Update Certificate file ID index - currently not supported */ + Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; + /* verify user length */ + if (pSecExtParams->UserLen > MAX_USER_LEN) + { + return SL_INVALPARAM; + } + Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; + /* copy user name (identity) */ + if(pSecExtParams->UserLen > 0) + { + sl_Memcpy(EAP_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); + CmdCtrl.TxDescLen += pSecExtParams->UserLen; + } + /* verify Anonymous user length */ + if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) + { + return SL_INVALPARAM; + } + Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; + /* copy Anonymous user */ + if(pSecExtParams->AnonUserLen > 0) + { + sl_Memcpy(EAP_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); + CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; + } + + } + + /* Regular or open security profile */ + else + { + /* Update command opcode */ + CmdCtrl.Opcode = SL_OPCODE_WLAN_WLANCONNECTCOMMAND; + CmdCtrl.TxDescLen += sizeof(SlWlanConnectCommon_t); + /* copy SSID */ + sl_Memcpy(SSID_STRING(&Msg), pName, NameLen); + CmdCtrl.TxDescLen += NameLen; + /* Copy password if supplied */ + if( NULL != pSecParams ) + { + /* update security type */ + Msg.Cmd.Args.Common.SecType = pSecParams->Type; + /* verify key length is valid */ + if (pSecParams->KeyLen > MAX_KEY_LEN) + { + return SL_INVALPARAM; + } + /* update key length */ + Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; + CmdCtrl.TxDescLen += pSecParams->KeyLen; + /* copy key (could be no key in case of WPS pin) */ + if( NULL != pSecParams->Key ) + { + sl_Memcpy(PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); + } + } + /* Profile with no security */ + else + { + Msg.Cmd.Args.Common.PasswordLen = 0; + Msg.Cmd.Args.Common.SecType = SL_WLAN_SEC_TYPE_OPEN; + } + } + /* If BSSID is not null, copy to buffer, otherwise set to 0 */ + if(NULL != pMacAddr) + { + sl_Memcpy(Msg.Cmd.Args.Common.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Common.Bssid)); + } + else + { + _SlDrvMemZero(Msg.Cmd.Args.Common.Bssid, (_u16)sizeof(Msg.Cmd.Args.Common.Bssid)); + } + + VERIFY_RET_OK ( _SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); + + return (_i16)Msg.Rsp.status; +} +#endif + +/*******************************************************************************/ +/* sl_Disconnect */ +/* ******************************************************************************/ +#if _SL_INCLUDE_FUNC(sl_WlanDisconnect) +_i16 sl_WlanDisconnect(void) +{ + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + return _SlDrvBasicCmd(SL_OPCODE_WLAN_WLANDISCONNECTCOMMAND); +} +#endif + +/******************************************************************************/ +/* sl_PolicySet */ +/******************************************************************************/ +typedef union +{ + SlWlanPolicySetGet_t Cmd; + _BasicResponse_t Rsp; +}_SlPolicyMsg_u; + +#if _SL_INCLUDE_FUNC(sl_WlanPolicySet) + +static const _SlCmdCtrl_t _SlPolicySetCmdCtrl = +{ + SL_OPCODE_WLAN_POLICYSETCOMMAND, + (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_i16 sl_WlanPolicySet(const _u8 Type , const _u8 Policy, _u8 *pVal,const _u8 ValLen) +{ + _SlPolicyMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = ValLen; + CmdExt.pTxPayload1 = (_u8 *)pVal; + + Msg.Cmd.PolicyType = Type; + Msg.Cmd.PolicyOption = Policy; + Msg.Cmd.PolicyOptionLen = ValLen; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlPolicySetCmdCtrl, &Msg, &CmdExt)); + + return (_i16)Msg.Rsp.status; +} +#endif + + +/******************************************************************************/ +/* sl_PolicyGet */ +/******************************************************************************/ +typedef union +{ + SlWlanPolicySetGet_t Cmd; + SlWlanPolicySetGet_t Rsp; +}_SlPolicyGetMsg_u; + +#if _SL_INCLUDE_FUNC(sl_WlanPolicyGet) + +static const _SlCmdCtrl_t _SlPolicyGetCmdCtrl = +{ + SL_OPCODE_WLAN_POLICYGETCOMMAND, + (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t), + (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t) +}; + +_i16 sl_WlanPolicyGet(const _u8 Type ,_u8 *pPolicy,_u8 *pVal,_u8 *pValLen) +{ + _SlPolicyGetMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + if (*pValLen == 0) + { + return SL_EZEROLEN; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)(*pValLen); + CmdExt.pRxPayload = pVal; + + Msg.Cmd.PolicyType = Type; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlPolicyGetCmdCtrl, &Msg, &CmdExt)); + + + if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) + { + *pValLen = Msg.Rsp.PolicyOptionLen; + return SL_ESMALLBUF; + } + else + { + /* no pointer valus, fill the results into _i8 */ + *pValLen = (_u8)CmdExt.ActualRxPayloadLen; + *pPolicy = Msg.Rsp.PolicyOption; + + if( 0 == CmdExt.ActualRxPayloadLen ) + { + *pValLen = 1; + } + + } + return (_i16)SL_OS_RET_CODE_OK; +} +#endif + + +/*******************************************************************************/ +/* sl_ProfileAdd */ +/*******************************************************************************/ +typedef struct +{ + SlWlanAddGetEapProfile_t Args; + _i8 Strings[SL_WLAN_SSID_MAX_LENGTH + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; +}_SlProfileParams_t; + +typedef union +{ + _SlProfileParams_t Cmd; + _BasicResponse_t Rsp; +}_SlProfileAddMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_WlanProfileAdd) +_i16 sl_WlanProfileAdd(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority,const _u32 Options) +{ + _SlProfileAddMsg_u Msg; + _SlCmdCtrl_t CmdCtrl = {0,0,0}; + CmdCtrl.TxDescLen = 0;/* init */ + CmdCtrl.RxDescLen = (_SlArgSize_t)(sizeof(_BasicResponse_t)); + + + /* Options parameter is currently not in use */ + (void)Options; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + _SlDrvMemZero(&Msg,sizeof(_SlProfileAddMsg_u)); + + /* update priority */ + Msg.Cmd.Args.Common.Priority = (_u8)Priority; + /* verify SSID is not NULL */ + if( NULL == pName ) + { + return SL_INVALPARAM; + } + /* verify SSID length */ + VERIFY_PROTOCOL(NameLen <= SL_WLAN_SSID_MAX_LENGTH); + /* update SSID length */ + Msg.Cmd.Args.Common.SsidLen = (_u8)NameLen; + + /* Enterprise security profile */ + if (NULL != pSecExtParams) + { + /* Update command opcode */ + CmdCtrl.Opcode = SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND; + CmdCtrl.TxDescLen += sizeof(SlWlanAddGetEapProfile_t); + + /* copy SSID */ + sl_Memcpy(EAP_PROFILE_SSID_STRING(&Msg), pName, NameLen); + CmdCtrl.TxDescLen += NameLen; + + /* Copy password if supplied */ + if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) + { + /* update security type */ + Msg.Cmd.Args.Common.SecType = (_i8)(pSecParams->Type); + + if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.Common.SecType ) + { + Msg.Cmd.Args.Common.WepKeyId = 0; + } + + /* verify key length */ + if (pSecParams->KeyLen > MAX_KEY_LEN) + { + return SL_INVALPARAM; + } + VERIFY_PROTOCOL(pSecParams->KeyLen <= MAX_KEY_LEN); + /* update key length */ + Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; + CmdCtrl.TxDescLen += pSecParams->KeyLen; + ARG_CHECK_PTR(pSecParams->Key); + /* copy key */ + sl_Memcpy(EAP_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); + } + else + { + Msg.Cmd.Args.Common.PasswordLen = 0; + } + + ARG_CHECK_PTR(pSecExtParams); + /* Update Eap bitmask */ + Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; + /* Update Certificate file ID index - currently not supported */ + Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; + /* verify user length */ + if (pSecExtParams->UserLen > MAX_USER_LEN) + { + return SL_INVALPARAM; + } + Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; + /* copy user name (identity) */ + if(pSecExtParams->UserLen > 0) + { + sl_Memcpy(EAP_PROFILE_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); + CmdCtrl.TxDescLen += pSecExtParams->UserLen; + } + + /* verify Anonymous user length (for tunneled) */ + if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) + { + return SL_INVALPARAM; + } + Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; + + /* copy Anonymous user */ + if(pSecExtParams->AnonUserLen > 0) + { + sl_Memcpy(EAP_PROFILE_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); + CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; + } + + } + /* Regular or open security profile */ + else + { + /* Update command opcode */ + CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEADDCOMMAND; + /* update commnad length */ + CmdCtrl.TxDescLen += sizeof(SlWlanAddGetProfile_t); + + if (NULL != pName) + { + /* copy SSID */ + sl_Memcpy(PROFILE_SSID_STRING(&Msg), pName, NameLen); + CmdCtrl.TxDescLen += NameLen; + } + + /* Copy password if supplied */ + if( NULL != pSecParams ) + { + /* update security type */ + Msg.Cmd.Args.Common.SecType = (_i8)(pSecParams->Type); + + if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.Common.SecType ) + { + Msg.Cmd.Args.Common.WepKeyId = 0; + } + + /* verify key length */ + if (pSecParams->KeyLen > MAX_KEY_LEN) + { + return SL_INVALPARAM; + } + /* update key length */ + Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; + CmdCtrl.TxDescLen += pSecParams->KeyLen; + /* copy key (could be no key in case of WPS pin) */ + if( NULL != pSecParams->Key ) + { + sl_Memcpy(PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); + } + } + else + { + Msg.Cmd.Args.Common.SecType = SL_WLAN_SEC_TYPE_OPEN; + Msg.Cmd.Args.Common.PasswordLen = 0; + } + } + + /* If BSSID is not null, copy to buffer, otherwise set to 0 */ + if(NULL != pMacAddr) + { + sl_Memcpy(Msg.Cmd.Args.Common.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Common.Bssid)); + } + else + { + _SlDrvMemZero(Msg.Cmd.Args.Common.Bssid, (_u16)sizeof(Msg.Cmd.Args.Common.Bssid)); + } + + VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); + + return (_i16)Msg.Rsp.status; +} +#endif + + +/*******************************************************************************/ +/* sl_ProfileUpdate */ +/*******************************************************************************/ + +typedef struct +{ + SlWlanUpdateProfile_t Args; + _i8 Strings[MAX_SSID_LEN + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; +}_SlProfileUpdateParams_t; + +typedef union +{ + _SlProfileUpdateParams_t Cmd; + _BasicResponse_t Rsp; +}_SlProfileUpdateMsg_u; + +#if _SL_INCLUDE_FUNC(sl_WlanProfileUpdate) +_i16 sl_WlanProfileUpdate(const _u32 Index, const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority) +{ + _SlProfileUpdateMsg_u Msg; + _SlCmdCtrl_t CmdCtrl = {0,0,0}; + CmdCtrl.TxDescLen = 0;/* init */ + CmdCtrl.RxDescLen = (_SlArgSize_t)(sizeof(_BasicResponse_t)); + + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + _SlDrvMemZero(&Msg,sizeof(_SlProfileUpdateParams_t)); + + Msg.Cmd.Args.Index = Index; + /* update priority */ + Msg.Cmd.Args.Priority = (_u8)Priority; + + /* verify SSID length */ + VERIFY_PROTOCOL(NameLen <= MAX_SSID_LEN); + /* update SSID length */ + Msg.Cmd.Args.SsidLen = (_u8)NameLen; + + + /* Enterprise security profile */ + if (NULL != pSecExtParams) + { + /* Update command opcode */ + CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEEAPUPDATECOMMAND; + CmdCtrl.TxDescLen += sizeof(SlWlanUpdateProfile_t); + + /* If SSID is supplied, copy it */ + if (NULL != pName) + { + sl_Memcpy(UPDATE_PROFILE_SSID_STRING(&Msg), pName, NameLen); + CmdCtrl.TxDescLen += NameLen; + } + else + { + Msg.Cmd.Args.SsidLen = 0; + } + + + /* Copy password if supplied */ + if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) + { + /* update security type */ + Msg.Cmd.Args.SecType = (_i8)(pSecParams->Type); + + if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.SecType ) + { + Msg.Cmd.Args.WepKeyId = 0; + } + + /* verify key length */ + if (pSecParams->KeyLen > MAX_KEY_LEN) + { + return SL_INVALPARAM; + } + VERIFY_PROTOCOL(pSecParams->KeyLen <= MAX_KEY_LEN); + /* update key length */ + Msg.Cmd.Args.PasswordLen = pSecParams->KeyLen; + CmdCtrl.TxDescLen += pSecParams->KeyLen; + ARG_CHECK_PTR(pSecParams->Key); + /* copy key */ + sl_Memcpy(UPDATE_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); + } + else + { + Msg.Cmd.Args.PasswordLen = 0; + } + + ARG_CHECK_PTR(pSecExtParams); + /* Update Eap bitmask */ + Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; + /* Update Certificate file ID index - currently not supported */ + Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; + /* verify user length */ + if (pSecExtParams->UserLen > MAX_USER_LEN) + { + return SL_INVALPARAM; + } + Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; + /* copy user name (identity) */ + if(pSecExtParams->UserLen > 0) + { + sl_Memcpy(UPDATE_PROFILE_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); + CmdCtrl.TxDescLen += pSecExtParams->UserLen; + } + + /* verify Anonymous user length (for tunneled) */ + if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) + { + return SL_INVALPARAM; + } + Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; + + /* copy Anonymous user */ + if(pSecExtParams->AnonUserLen > 0) + { + sl_Memcpy(UPDATE_PROFILE_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); + CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; + } + + } + /* Regular or open security profile */ + else + { + /* Update command opcode */ + CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEUPDATECOMMAND; + /* update commnad length */ + CmdCtrl.TxDescLen += sizeof(SlWlanUpdateProfile_t); + + if (NULL != pName) + { + /* copy SSID */ + sl_Memcpy(UPDATE_PROFILE_SSID_STRING(&Msg), pName, NameLen); + CmdCtrl.TxDescLen += NameLen; + } + else + { + Msg.Cmd.Args.SsidLen = 0; + } + + /* Copy password if supplied */ + if( NULL != pSecParams ) + { + /* update security type */ + Msg.Cmd.Args.SecType = (_i8)(pSecParams->Type); + + if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.SecType ) + { + Msg.Cmd.Args.WepKeyId = 0; + } + + /* verify key length */ + if (pSecParams->KeyLen > MAX_KEY_LEN) + { + return SL_INVALPARAM; + } + /* update key length */ + Msg.Cmd.Args.PasswordLen = pSecParams->KeyLen; + CmdCtrl.TxDescLen += pSecParams->KeyLen; + /* copy key (could be no key in case of WPS pin) */ + if( NULL != pSecParams->Key ) + { + sl_Memcpy(UPDATE_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); + } + } + else + { + Msg.Cmd.Args.SecType = SL_WLAN_SEC_TYPE_OPEN; + Msg.Cmd.Args.PasswordLen = 0; + } + + } + + + /* If BSSID is not null, copy to buffer, otherwise set to 0 */ + if(NULL != pMacAddr) + { + sl_Memcpy(Msg.Cmd.Args.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Bssid)); + } + else + { + _SlDrvMemZero(Msg.Cmd.Args.Bssid, (_u16)sizeof(Msg.Cmd.Args.Bssid)); + } + + VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); + + return (_i16)Msg.Rsp.status; +} +#endif +/*******************************************************************************/ +/* sl_ProfileGet */ +/*******************************************************************************/ +typedef union +{ + SlWlanProfileDelGetCommand_t Cmd; + _SlProfileParams_t Rsp; +}_SlProfileGetMsg_u; + +#if _SL_INCLUDE_FUNC(sl_WlanProfileGet) + +static const _SlCmdCtrl_t _SlProfileGetCmdCtrl = +{ + SL_OPCODE_WLAN_PROFILEGETCOMMAND, + (_SlArgSize_t)sizeof(SlWlanProfileDelGetCommand_t), + (_SlArgSize_t)sizeof(_SlProfileParams_t) +}; + +_i16 sl_WlanProfileGet(const _i16 Index,_i8* pName, _i16 *pNameLen, _u8 *pMacAddr, SlWlanSecParams_t* pSecParams, SlWlanGetSecParamsExt_t* pEntParams, _u32 *pPriority) +{ + _SlProfileGetMsg_u Msg; + Msg.Cmd.Index = (_u8)Index; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProfileGetCmdCtrl, &Msg, NULL)); + + pSecParams->Type = (_u8)(Msg.Rsp.Args.Common.SecType); + if (Msg.Rsp.Args.Common.SecType >= 0) + { + /* since password is not transferred in getprofile, password length should always be zero */ + pSecParams->KeyLen = Msg.Rsp.Args.Common.PasswordLen; + if (NULL != pEntParams) + { + pEntParams->EapMethod = Msg.Rsp.Args.EapBitmask; + pEntParams->UserLen = Msg.Rsp.Args.UserLen; + /* copy user name */ + if (pEntParams->UserLen > 0) + { + sl_Memcpy(pEntParams->User, EAP_PROFILE_USER_STRING(&Msg), pEntParams->UserLen); + } + pEntParams->AnonUserLen = Msg.Rsp.Args.AnonUserLen; + /* copy anonymous user name */ + if (pEntParams->AnonUserLen > 0) + { + sl_Memcpy(pEntParams->AnonUser, EAP_PROFILE_ANON_USER_STRING(&Msg), pEntParams->AnonUserLen); + } + } + + *pNameLen = (_i16)(Msg.Rsp.Args.Common.SsidLen); + *pPriority = Msg.Rsp.Args.Common.Priority; + + //if (NULL != Msg.Rsp.Args.Common.Bssid) + { + sl_Memcpy(pMacAddr, Msg.Rsp.Args.Common.Bssid, sizeof(Msg.Rsp.Args.Common.Bssid)); + } + + sl_Memset(pName, 0, SL_WLAN_SSID_MAX_LENGTH); + sl_Memcpy(pName, EAP_PROFILE_SSID_STRING(&Msg), *pNameLen); + } + return (_i16)Msg.Rsp.Args.Common.SecType; +} +#endif +/*******************************************************************************/ +/* sl_ProfileDel */ +/*******************************************************************************/ +typedef union +{ + SlWlanProfileDelGetCommand_t Cmd; + _BasicResponse_t Rsp; +}_SlProfileDelMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_WlanProfileDel) + +static const _SlCmdCtrl_t _SlProfileDelCmdCtrl = +{ + SL_OPCODE_WLAN_PROFILEDELCOMMAND, + (_SlArgSize_t)sizeof(SlWlanProfileDelGetCommand_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_i16 sl_WlanProfileDel(const _i16 Index) +{ + _SlProfileDelMsg_u Msg; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + Msg.Cmd.Index = (_u8)Index; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProfileDelCmdCtrl, &Msg, NULL)); + + return (_i16)Msg.Rsp.status; +} +#endif + + +/******************************************************************************/ +/* sl_WlanGetNetworkList */ +/******************************************************************************/ +typedef union +{ + SlWlanGetNetworkListCommand_t Cmd; + _WlanGetNetworkListResponse_t Rsp; +}_SlWlanGetNetworkListMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_WlanGetNetworkList) + +static const _SlCmdCtrl_t _SlWlanGetNetworkListCtrl = +{ + SL_OPCODE_WLAN_SCANRESULTSGETCOMMAND, + (_SlArgSize_t)sizeof(SlWlanGetNetworkListCommand_t), + (_SlArgSize_t)sizeof(_WlanGetNetworkListResponse_t) +}; + +_i16 sl_WlanGetNetworkList(const _u8 Index,const _u8 Count, SlWlanNetworkEntry_t *pEntries) +{ + _i16 retVal = 0; + _SlWlanGetNetworkListMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + if (Count == 0) + { + return SL_EZEROLEN; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)(sizeof(SlWlanNetworkEntry_t)*(Count)); + CmdExt.pRxPayload = (_u8 *)pEntries; + + Msg.Cmd.Index = Index; + Msg.Cmd.Count = Count; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanGetNetworkListCtrl, &Msg, &CmdExt)); + retVal = Msg.Rsp.status; + + return (_i16)retVal; +} +#endif + +/******************************************************************************/ +/* sl_WlanGetExtNetworkList */ +/******************************************************************************/ +typedef union +{ + SlWlanGetExtNetworkListCommand_t Cmd; + _WlanGetExtNetworkListResponse_t Rsp; +}_SlWlanGetExtNetworkListMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_WlanGetExtNetworkList) + +static const _SlCmdCtrl_t _SlWlanGetExtNetworkListCtrl = +{ + SL_OPCODE_WLAN_EXTSCANRESULTSGETCOMMAND, + (_SlArgSize_t)sizeof(SlWlanGetExtNetworkListCommand_t), + (_SlArgSize_t)sizeof(_WlanGetExtNetworkListResponse_t) +}; + +_i16 sl_WlanGetExtNetworkList(const _u8 Index,const _u8 Count, SlWlanExtNetworkEntry_t *pEntries) +{ + _i16 retVal = 0; + _SlWlanGetExtNetworkListMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + if (Count == 0) + { + return SL_EZEROLEN; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)(sizeof(SlWlanExtNetworkEntry_t)*(Count)); + CmdExt.pRxPayload = (_u8 *)pEntries; + + Msg.Cmd.Index = Index; + Msg.Cmd.Count = Count; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanGetExtNetworkListCtrl, &Msg, &CmdExt)); + retVal = Msg.Rsp.status; + + return (_i16)retVal; +} +#endif + + +/******************************************************************************/ +/* RX filters message command response structures */ +/******************************************************************************/ + + +typedef union +{ + SlWlanRxFilterAddCommand_t Cmd; + SlWlanRxFilterAddCommandReponse_t Rsp; +}_SlWlanRxFilterAddMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_WlanRxFilterAdd) + +static const _SlCmdCtrl_t _SlWlanRxFilterAddtCmdCtrl = +{ + SL_OPCODE_WLAN_WLANRXFILTERADDCOMMAND, + (_SlArgSize_t)sizeof(SlWlanRxFilterAddCommand_t), + (_SlArgSize_t)sizeof(SlWlanRxFilterAddCommandReponse_t) +}; + + +/***************************************************************************** + RX filters +*****************************************************************************/ +_i16 sl_WlanRxFilterAdd(SlWlanRxFilterRuleType_t RuleType, + SlWlanRxFilterFlags_u Flags, + const SlWlanRxFilterRule_u* const pRule, + const SlWlanRxFilterTrigger_t* const pTrigger, + const SlWlanRxFilterAction_t* const pAction, + SlWlanRxFilterID_t* pFilterId) +{ + _SlWlanRxFilterAddMsg_u Msg; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + Msg.Cmd.RuleType = RuleType; + /* filterId is zero */ + Msg.Cmd.FilterId = 0; + Msg.Cmd.Flags = Flags; + sl_Memcpy( &(Msg.Cmd.Rule), pRule, sizeof(SlWlanRxFilterRule_u) ); + sl_Memcpy( &(Msg.Cmd.Trigger), pTrigger, sizeof(SlWlanRxFilterTrigger_t) ); + sl_Memcpy( &(Msg.Cmd.Action), pAction, sizeof(SlWlanRxFilterAction_t) ); + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanRxFilterAddtCmdCtrl, &Msg, NULL) ); + *pFilterId = Msg.Rsp.FilterId; + return (_i16)Msg.Rsp.Status; +} +#endif + + +/*******************************************************************************/ +/* sl_WlanRxStatStart */ +/*******************************************************************************/ +#if _SL_INCLUDE_FUNC(sl_WlanRxStatStart) +_i16 sl_WlanRxStatStart(void) +{ + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + return _SlDrvBasicCmd(SL_OPCODE_WLAN_STARTRXSTATCOMMAND); +} +#endif + +#if _SL_INCLUDE_FUNC(sl_WlanRxStatStop) +_i16 sl_WlanRxStatStop(void) +{ + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + return _SlDrvBasicCmd(SL_OPCODE_WLAN_STOPRXSTATCOMMAND); +} +#endif + +#if _SL_INCLUDE_FUNC(sl_WlanRxStatGet) +_i16 sl_WlanRxStatGet(SlWlanGetRxStatResponse_t *pRxStat,const _u32 Flags) +{ + _SlCmdCtrl_t CmdCtrl = {SL_OPCODE_WLAN_GETRXSTATCOMMAND, 0, (_SlArgSize_t)sizeof(SlWlanGetRxStatResponse_t)}; + /* Flags paramater is currently not in use */ + (void)Flags; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + _SlDrvMemZero(pRxStat, (_u16)sizeof(SlWlanGetRxStatResponse_t)); + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, pRxStat, NULL)); + + return 0; +} +#endif + +/******************************************************************************/ +/* sl_WlanProvisioning */ +/******************************************************************************/ + +typedef struct +{ + SlWlanSmartConfigParams_t Args; + _i8 Key[MAX_SMART_CONFIG_KEY]; /* public key + groupId1 key + groupId2 key */ +}_SlSmartConfigArgs_t; + +typedef struct +{ + SlWlanProvisioningParams_t ProvParams; + _SlSmartConfigArgs_t SmartConfigParams; +}_SlProvisioning_t; + +typedef union +{ + _SlProvisioning_t Cmd; + _BasicResponse_t Rsp; +}_SlProvisioningStartMsg_u; + +#if _SL_INCLUDE_FUNC(sl_WlanProvisioning) + +const _SlCmdCtrl_t _SlProvisioningCmdCtrl = +{ + SL_OPCODE_WLAN_PROVISIONING_COMMAND, + sizeof(_SlProvisioning_t), + sizeof(_BasicResponse_t) +}; + +_i16 sl_WlanProvisioning(_u8 ProvisioningCmd, _u8 RequestedRoleAfterSuccess, _u16 InactivityTimeoutSec, char *pSmartConfigKey, _u32 Flags) +{ + _SlProvisioningStartMsg_u Msg; + + /* Verify if we can send this command to the NWP + We can send only prov. stop command if command is not allowed */ + if ((!SL_IS_COMMAND_ALLOWED) && (!SL_IS_PROVISIONING_ACTIVE) && (InactivityTimeoutSec != 0)) + { + /* return with the correct error code */ + return _SlDrvDriverIsApiAllowed(SL_OPCODE_SILO_WLAN); + } + + /* If there is an API in progress and the timeout is not zero (it means the + command is not prov. stop) then abort and return an error code */ + if (_SlDrvIsApiInProgress() && (InactivityTimeoutSec !=0)) + { + return SL_RET_CODE_API_COMMAND_IN_PROGRESS; + } + + _SlDrvMemZero(&Msg, (_u16)sizeof (_SlProvisioningStartMsg_u)); + + Msg.Cmd.ProvParams.ProvisioningCmd = (_u8)ProvisioningCmd; + Msg.Cmd.ProvParams.RequestedRoleAfterSuccess = (_u8)RequestedRoleAfterSuccess; + Msg.Cmd.ProvParams.InactivityTimeoutSec = (_u16)InactivityTimeoutSec; + Msg.Cmd.ProvParams.Flags = Flags; + + /* Smart Config parameters */ + if (NULL != pSmartConfigKey) + { + Msg.Cmd.SmartConfigParams.Args.GroupIdBitmask = SL_WLAN_SMART_CONFIG_DEFAULT_GROUP; + Msg.Cmd.SmartConfigParams.Args.Cipher = SL_WLAN_SMART_CONFIG_DEFAULT_CIPHER; + Msg.Cmd.SmartConfigParams.Args.PublicKeyLen = SL_WLAN_SMART_CONFIG_KEY_LENGTH; + + /* copy keys (if exist) after command (one after another) */ + sl_Memcpy(Msg.Cmd.SmartConfigParams.Key, pSmartConfigKey, SL_WLAN_SMART_CONFIG_KEY_LENGTH); + } + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProvisioningCmdCtrl , &Msg, NULL)); + + return (_i16)Msg.Rsp.status; +} +#endif + +/*******************************************************************************/ +/* sl_WlanSetMode */ +/*******************************************************************************/ +typedef union +{ + SlWlanSetMode_t Cmd; + _BasicResponse_t Rsp; +}_SlwlanSetModeMsg_u; + +#if _SL_INCLUDE_FUNC(sl_WlanSetMode) + +static const _SlCmdCtrl_t _SlWlanSetModeCmdCtrl = +{ + SL_OPCODE_WLAN_SET_MODE, + (_SlArgSize_t)sizeof(SlWlanSetMode_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +/* possible values are: +WLAN_SET_STA_MODE = 1 +WLAN_SET_AP_MODE = 2 +WLAN_SET_P2P_MODE = 3 */ +_i16 sl_WlanSetMode(const _u8 Mode) +{ + _SlwlanSetModeMsg_u Msg; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + Msg.Cmd.Mode = Mode; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanSetModeCmdCtrl , &Msg, NULL)); + + return (_i16)Msg.Rsp.status; +} +#endif + +/*******************************************************************************/ +/* sl_WlanSet */ +/* ******************************************************************************/ +typedef union +{ + SlWlanCfgSetGet_t Cmd; + _BasicResponse_t Rsp; +}_SlWlanCfgSetMsg_u; + + +#if _SL_INCLUDE_FUNC(sl_WlanSet) + +static const _SlCmdCtrl_t _SlWlanCfgSetCmdCtrl = +{ + SL_OPCODE_WLAN_CFG_SET, + (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t), + (_SlArgSize_t)sizeof(_BasicResponse_t) +}; + +_i16 sl_WlanSet(const _u16 ConfigId ,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues) +{ + _SlWlanCfgSetMsg_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.TxPayload1Len = (_u16)((ConfigLen+3) & (~3)); + CmdExt.pTxPayload1 = (_u8 *)pValues; + + Msg.Cmd.ConfigId = ConfigId; + Msg.Cmd.ConfigLen = ConfigLen; + Msg.Cmd.ConfigOpt = ConfigOpt; + + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanCfgSetCmdCtrl, &Msg, &CmdExt)); + + return (_i16)Msg.Rsp.status; +} +#endif + + +/******************************************************************************/ +/* sl_WlanGet */ +/******************************************************************************/ +typedef union +{ + SlWlanCfgSetGet_t Cmd; + SlWlanCfgSetGet_t Rsp; +}_SlWlanCfgMsgGet_u; + +#if _SL_INCLUDE_FUNC(sl_WlanGet) + +static const _SlCmdCtrl_t _SlWlanCfgGetCmdCtrl = +{ + SL_OPCODE_WLAN_CFG_GET, + (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t), + (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t) +}; + +_i16 sl_WlanGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues) +{ + _SlWlanCfgMsgGet_u Msg; + _SlCmdExt_t CmdExt; + + /* verify that this api is allowed. if not allowed then + ignore the API execution and return immediately with an error */ + VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); + + if (*pConfigLen == 0) + { + return SL_EZEROLEN; + } + + _SlDrvResetCmdExt(&CmdExt); + CmdExt.RxPayloadLen = (_i16)*pConfigLen; + CmdExt.pRxPayload = (_u8 *)pValues; + Msg.Cmd.ConfigLen = *pConfigLen; + Msg.Cmd.ConfigId = ConfigId; + if( pConfigOpt ) + { + Msg.Cmd.ConfigOpt = (_u16)*pConfigOpt; + } + VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanCfgGetCmdCtrl, &Msg, &CmdExt)); + + if( pConfigOpt ) + { + *pConfigOpt = (_u8)Msg.Rsp.ConfigOpt; + } + if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) + { + *pConfigLen = (_u8)CmdExt.RxPayloadLen; + return SL_ESMALLBUF; + } + else + { + *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen; + } + + return (_i16)Msg.Rsp.Status; +} +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/trace.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/trace.h new file mode 100755 index 00000000000..264c7662cb2 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/trace.h @@ -0,0 +1,226 @@ +/* + * trace.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +#include + +#ifndef __SIMPLELINK_TRACE_H__ +#define __SIMPLELINK_TRACE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +#define SL_SYNC_SCAN_THRESHOLD (( _u32 )2000) + +#ifdef SL_TINY +#define _SlDrvAssert(line ) { while(1); } +#else +#define _SlDrvAssert() _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_DRIVER_ABORT, 0, 0) +#endif + +#define _SL_ASSERT(expr) {if(!(expr)){ _SlDrvAssert();}} +#define _SL_ERROR(expr, error) {if(!(expr)){return (error);}} + +#define _SL_ASSERT_ERROR(expr, error) {if(!(expr)){_SlDrvAssert(); return (error);}} + +#define SL_HANDLING_ASSERT 2 +#define SL_HANDLING_ERROR 1 +#define SL_HANDLING_NONE 0 + +#ifndef SL_TINY +#define SL_SELF_COND_HANDLING SL_HANDLING_ASSERT +#define SL_PROTOCOL_HANDLING SL_HANDLING_ASSERT +#define SL_DRV_RET_CODE_HANDLING SL_HANDLING_ERROR +#define SL_NWP_IF_HANDLING SL_HANDLING_ASSERT +#define SL_OSI_RET_OK_HANDLING SL_HANDLING_ERROR +#define SL_MALLOC_OK_HANDLING SL_HANDLING_ASSERT +#define SL_USER_ARGS_HANDLING SL_HANDLING_ASSERT +#define SL_ERR_IN_PROGRESS_HANDLING SL_HANDLING_ERROR +#define SL_ERR_IN_API_ALLOWED SL_HANDLING_ERROR +#else +#define SL_SELF_COND_HANDLING SL_HANDLING_NONE +#define SL_PROTOCOL_HANDLING SL_HANDLING_NONE +#define SL_DRV_RET_CODE_HANDLING SL_HANDLING_NONE +#define SL_NWP_IF_HANDLING SL_HANDLING_NONE +#define SL_OSI_RET_OK_HANDLING SL_HANDLING_NONE +#define SL_MALLOC_OK_HANDLING SL_HANDLING_NONE +#define SL_USER_ARGS_HANDLING SL_HANDLING_NONE +#define SL_ERR_IN_PROGRESS_HANDLING SL_HANDLING_NONE +#define SL_ERR_IN_API_ALLOWED SL_HANDLING_NONE +#endif + + +#if (SL_ERR_IN_PROGRESS_HANDLING == SL_HANDLING_ERROR) +#define VERIFY_NO_ERROR_HANDLING_IN_PROGRESS() { \ + if (SL_IS_RESTART_REQUIRED) return SL_API_ABORTED; } +#else +#define VERIFY_NO_ERROR_HANDLING_IN_PROGRESS() +#endif + +#if (SL_ERR_IN_API_ALLOWED == SL_HANDLING_ERROR) +#define VERIFY_API_ALLOWED(Silo) { \ + _SlReturnVal_t status = _SlDrvDriverIsApiAllowed(Silo); \ + if ( status ) return status; } +#else +#define VERIFY_API_ALLOWED(Silo) +#endif + +#if (SL_DRV_RET_CODE_HANDLING == SL_HANDLING_ASSERT) +#define VERIFY_RET_OK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)} +#elif (SL_DRV_RET_CODE_HANDLING == SL_HANDLING_ERROR) +#define VERIFY_RET_OK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return (_SlReturnVal_t)_RetVal;} +#else +#define VERIFY_RET_OK(Func) (Func); +#endif + +#if (SL_PROTOCOL_HANDLING == SL_HANDLING_ASSERT) +#define VERIFY_PROTOCOL(expr) _SL_ASSERT(expr) +#elif (SL_PROTOCOL_HANDLING == SL_HANDLING_ERROR) +#define VERIFY_PROTOCOL(expr) _SL_ERROR(expr, SL_RET_CODE_PROTOCOL_ERROR) +#else +#define VERIFY_PROTOCOL(expr) +#endif + +#if (defined(PROTECT_SOCKET_ASYNC_RESP) && (SL_SELF_COND_HANDLING == SL_HANDLING_ASSERT)) +#define VERIFY_SOCKET_CB(expr) _SL_ASSERT(expr) +#elif (defined(PROTECT_SOCKET_ASYNC_RESP) && (SL_SELF_COND_HANDLING == SL_HANDLING_ERROR)) +#define VERIFY_SOCKET_CB(expr) _SL_ERROR(expr, SL_RET_CODE_SELF_ERROR) +#else +#define VERIFY_SOCKET_CB(expr) +#endif + +#if (SL_NWP_IF_HANDLING == SL_HANDLING_ASSERT) +#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { _i16 RetSize, ExpSize = (_i16)(len); RetSize = sl_IfWrite((fd),(pBuff),ExpSize); _SL_ASSERT(ExpSize == RetSize)} +#define NWP_IF_READ_CHECK(fd,pBuff,len) { _i16 RetSize, ExpSize = (_i16)(len); RetSize = sl_IfRead((fd),(pBuff),ExpSize); _SL_ASSERT(ExpSize == RetSize)} +#elif (SL_NWP_IF_HANDLING == SL_HANDLING_ERROR) +#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { _SL_ERROR((len == sl_IfWrite((fd),(pBuff),(len))), SL_RET_CODE_NWP_IF_ERROR);} +#define NWP_IF_READ_CHECK(fd,pBuff,len) { _SL_ERROR((len == sl_IfRead((fd),(pBuff),(len))), SL_RET_CODE_NWP_IF_ERROR);} +#else +#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { sl_IfWrite((fd),(pBuff),(len));} +#define NWP_IF_READ_CHECK(fd,pBuff,len) { sl_IfRead((fd),(pBuff),(len));} +#endif + +#if (SL_OSI_RET_OK_HANDLING == SL_HANDLING_ASSERT) +#define OSI_RET_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)} +#elif (SL_OSI_RET_OK_HANDLING == SL_HANDLING_ERROR) +#define OSI_RET_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return _RetVal;} +#else +#define OSI_RET_OK_CHECK(Func) (Func); +#endif + +#if (SL_MALLOC_OK_HANDLING == SL_HANDLING_ASSERT) +#define MALLOC_OK_CHECK(Ptr) _SL_ASSERT(NULL != Ptr) +#elif (SL_MALLOC_OK_HANDLING == SL_HANDLING_ERROR) +#define MALLOC_OK_CHECK(Ptr) _SL_ERROR((NULL != Ptr), SL_RET_CODE_MALLOC_ERROR) +#else +#define MALLOC_OK_CHECK(Ptr) +#endif + +#ifdef SL_INC_ARG_CHECK + +#if (SL_USER_ARGS_HANDLING == SL_HANDLING_ASSERT) +#define ARG_CHECK_PTR(Ptr) _SL_ASSERT(NULL != Ptr) +#elif (SL_USER_ARGS_HANDLING == SL_HANDLING_ERROR) +#define ARG_CHECK_PTR(Ptr) _SL_ERROR((NULL != Ptr), SL_RET_CODE_INVALID_INPUT) +#else +#define ARG_CHECK_PTR(Ptr) +#endif + +#else +#define ARG_CHECK_PTR(Ptr) +#endif + +/*#define SL_DBG_TRACE_ENABLE*/ +#ifdef SL_DBG_TRACE_ENABLE +#define SL_TRACE0(level,msg_id,str) printf(str) +#define SL_TRACE1(level,msg_id,str,p1) printf(str,(p1)) +#define SL_TRACE2(level,msg_id,str,p1,p2) printf(str,(p1),(p2)) +#define SL_TRACE3(level,msg_id,str,p1,p2,p3) printf(str,(p1),(p2),(p3)) +#define SL_TRACE4(level,msg_id,str,p1,p2,p3,p4) printf(str,(p1),(p2),(p3),(p4)) +#define SL_ERROR_TRACE(msg_id,str) printf(str) +#define SL_ERROR_TRACE1(msg_id,str,p1) printf(str,(p1)) +#define SL_ERROR_TRACE2(msg_id,str,p1,p2) printf(str,(p1),(p2)) +#define SL_ERROR_TRACE3(msg_id,str,p1,p2,p3) printf(str,(p1),(p2),(p3)) +#define SL_ERROR_TRACE4(msg_id,str,p1,p2,p3,p4) printf(str,(p1),(p2),(p3),(p4)) +#define SL_TRACE_FLUSH() +#else +#define SL_TRACE0(level,msg_id,str) +#define SL_TRACE1(level,msg_id,str,p1) +#define SL_TRACE2(level,msg_id,str,p1,p2) +#define SL_TRACE3(level,msg_id,str,p1,p2,p3) +#define SL_TRACE4(level,msg_id,str,p1,p2,p3,p4) +#define SL_ERROR_TRACE(msg_id,str) +#define SL_ERROR_TRACE1(msg_id,str,p1) +#define SL_ERROR_TRACE2(msg_id,str,p1,p2) +#define SL_ERROR_TRACE3(msg_id,str,p1,p2,p3) +#define SL_ERROR_TRACE4(msg_id,str,p1,p2,p3,p4) +#define SL_TRACE_FLUSH() +#endif + +/* #define SL_DBG_CNT_ENABLE */ +#ifdef SL_DBG_CNT_ENABLE +#define _SL_DBG_CNT_INC(Cnt) g_DbgCnt. ## Cnt++ +#define _SL_DBG_SYNC_LOG(index,value) {if(index < SL_DBG_SYNC_LOG_SIZE){*(_u32 *)&g_DbgCnt.SyncLog[index] = *(_u32 *)(value);}} + +#else +#define _SL_DBG_CNT_INC(Cnt) +#define _SL_DBG_SYNC_LOG(index,value) +#endif + +#define SL_DBG_LEVEL_1 1 +#define SL_DBG_LEVEL_2 2 +#define SL_DBG_LEVEL_3 4 +#define SL_DBG_LEVEL_MASK (SL_DBG_LEVEL_2|SL_DBG_LEVEL_3) + +#define SL_INCLUDE_DBG_FUNC(Name) ((Name ## _DBG_LEVEL) & SL_DBG_LEVEL_MASK) + +#define _SlDrvPrintStat_DBG_LEVEL SL_DBG_LEVEL_3 +#define _SlDrvOtherFunc_DBG_LEVEL SL_DBG_LEVEL_1 + +#ifdef __cplusplus +} +#endif + + +#endif /*__SIMPLELINK_TRACE_H__*/ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/wlan.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/wlan.h new file mode 100755 index 00000000000..302d7c280eb --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/net/wifi/wlan.h @@ -0,0 +1,2282 @@ +/* + * wlan.h - CC31xx/CC32xx Host Driver Implementation + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include + +#ifndef __WLAN_H__ +#define __WLAN_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ +/*! + \defgroup Wlan + \short Controls the use of the WiFi WLAN module + +*/ +/*! + + \addtogroup Wlan + - Connection features, such as: profiles, policies, SmartConfig(tm) + - Advanced WLAN features, such as: scans, rx filters and rx statistics collection + + @{ + +*/ + +#define SL_WLAN_BSSID_LENGTH (6) +#define SL_WLAN_SSID_MAX_LENGTH (32) + +#define SL_WLAN_NUM_OF_RATE_INDEXES (20) +#define SL_WLAN_SIZE_OF_RSSI_HISTOGRAM (6) +#define SL_WLAN_SMART_CONFIG_KEY_LENGTH (16) +#define SL_WLAN_SMART_CONFIG_DEFAULT_CIPHER (1) +#define SL_WLAN_SMART_CONFIG_DEFAULT_GROUP (0) + +#define SL_WLAN_MAX_PROFILES (7) +#define SL_WLAN_DEL_ALL_PROFILES (255) + +typedef enum +{ + SL_WLAN_P2P_WPS_METHOD_DEFAULT, + SL_WLAN_P2P_WPS_METHOD_PIN_USER, + SL_WLAN_P2P_WPS_METHOD_PIN_MACHINE, + SL_WLAN_P2P_WPS_METHOD_REKEY, + SL_WLAN_P2P_WPS_METHOD_PBC, + SL_WLAN_P2P_WPS_METHOD_REGISTRAR +} SlWlanP2PWpsMethod_e; + +/* WLAN user events */ +typedef enum +{ + SL_WLAN_EVENT_CONNECT = 1, + SL_WLAN_EVENT_DISCONNECT, + SL_WLAN_EVENT_STA_ADDED, + SL_WLAN_EVENT_STA_REMOVED, + + SL_WLAN_EVENT_P2P_CONNECT, + SL_WLAN_EVENT_P2P_DISCONNECT, + SL_WLAN_EVENT_P2P_CLIENT_ADDED, + SL_WLAN_EVENT_P2P_CLIENT_REMOVED, + SL_WLAN_EVENT_P2P_DEVFOUND, + SL_WLAN_EVENT_P2P_REQUEST, + SL_WLAN_EVENT_P2P_CONNECTFAIL, + + SL_WLAN_EVENT_RXFILTER, + SL_WLAN_EVENT_PROVISIONING_STATUS, + SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED, + SL_WLAN_EVENT_RESERVED, + SL_WLAN_EVENT_MAX + +} SlWlanEventId_e; + + +/* WLAN Disconnect Reason Codes */ +#define SL_WLAN_DISCONNECT_UNSPECIFIED (1) + #define SL_WLAN_DISCONNECT_AUTH_NO_LONGER_VALID (2) + #define SL_WLAN_DISCONNECT_DEAUTH_SENDING_STA_LEAVING (3) + #define SL_WLAN_DISCONNECT_INACTIVITY (4) + #define SL_WLAN_DISCONNECT_TOO_MANY_STA (5) + #define SL_WLAN_DISCONNECT_FRAME_FROM_NONAUTH_STA (6) + #define SL_WLAN_DISCONNECT_FRAME_FROM_NONASSOC_STA (7) + #define SL_WLAN_DISCONNECT_DISS_SENDING_STA_LEAVING (8) + #define SL_WLAN_DISCONNECT_STA_NOT_AUTH (9) + #define SL_WLAN_DISCONNECT_POWER_CAPABILITY_INVALID (10) + #define SL_WLAN_DISCONNECT_SUPPORTED_CHANNELS_INVALID (11) + #define SL_WLAN_DISCONNECT_INVALID_IE (13) + #define SL_WLAN_DISCONNECT_MIC_FAILURE (14) + #define SL_WLAN_DISCONNECT_FOURWAY_HANDSHAKE_TIMEOUT (15) + #define SL_WLAN_DISCONNECT_GROUPKEY_HANDSHAKE_TIMEOUT (16) + #define SL_WLAN_DISCONNECT_REASSOC_INVALID_IE (17) + #define SL_WLAN_DISCONNECT_INVALID_GROUP_CIPHER (18) + #define SL_WLAN_DISCONNECT_INVALID_PAIRWISE_CIPHER (19) + #define SL_WLAN_DISCONNECT_INVALID_AKMP (20) + #define SL_WLAN_DISCONNECT_UNSUPPORTED_RSN_VERSION (21) + #define SL_WLAN_DISCONNECT_INVALID_RSN_CAPABILITIES (22) + #define SL_WLAN_DISCONNECT_IEEE_802_1X_AUTHENTICATION_FAILED (23) + #define SL_WLAN_DISCONNECT_CIPHER_SUITE_REJECTED (24) + #define SL_WLAN_DISCONNECT_DISASSOC_QOS (32) + #define SL_WLAN_DISCONNECT_DISASSOC_QOS_BANDWIDTH (33) + #define SL_WLAN_DISCONNECT_DISASSOC_EXCESSIVE_ACK_PENDING (34) + #define SL_WLAN_DISCONNECT_DISASSOC_TXOP_LIMIT (35) + #define SL_WLAN_DISCONNECT_STA_LEAVING (36) + #define SL_WLAN_DISCONNECT_STA_DECLINED (37) + #define SL_WLAN_DISCONNECT_STA_UNKNOWN_BA (38) + #define SL_WLAN_DISCONNECT_STA_TIMEOUT (39) + #define SL_WLAN_DISCONNECT_STA_UNSUPPORTED_CIPHER_SUITE (40) + #define SL_WLAN_DISCONNECT_USER_INITIATED (200) + #define SL_WLAN_DISCONNECT_AUTH_TIMEOUT (202) + #define SL_WLAN_DISCONNECT_ASSOC_TIMEOUT (203) + #define SL_WLAN_DISCONNECT_SECURITY_FAILURE (204) + #define SL_WLAN_DISCONNECT_WHILE_CONNNECTING (208) + #define SL_WLAN_DISCONNECT_MISSING_CERT (209) + #define SL_WLAN_DISCONNECT_CERTIFICATE_EXPIRED (210) + + + +#define SL_WLAN_STATUS_DISCONNECTED (0) +#define SL_WLAN_STATUS_SCANING (1) +#define SL_WLAN_STATUS_CONNECTING (2) +#define SL_WLAN_STATUS_CONNECTED (3) + +#define SL_WLAN_PROVISIONING_GENERAL_ERROR (0) +#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_NETWORK_NOT_FOUND (1) +#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_CONNECTION_FAILED (2) +#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_CONNECTION_SUCCESS_IP_NOT_ACQUIRED (3) +#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS_FEEDBACK_FAILED (4) +#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS (5) +#define SL_WLAN_PROVISIONING_ERROR_ABORT (6) +#define SL_WLAN_PROVISIONING_ERROR_ABORT_INVALID_PARAM (7) +#define SL_WLAN_PROVISIONING_ERROR_ABORT_HTTP_SERVER_DISABLED (8) +#define SL_WLAN_PROVISIONING_ERROR_ABORT_PROFILE_LIST_FULL (9) +#define SL_WLAN_PROVISIONING_ERROR_ABORT_PROVISIONING_ALREADY_STARTED (10) +#define SL_WLAN_PROVISIONING_AUTO_STARTED (11) +#define SL_WLAN_PROVISIONING_STOPPED (12) +#define SL_WLAN_PROVISIONING_SMART_CONFIG_SYNCED (13) +#define SL_WLAN_PROVISIONING_SMART_CONFIG_SYNC_TIMEOUT (14) +#define SL_WLAN_PROVISIONING_CONFIRMATION_WLAN_CONNECT (15) +#define SL_WLAN_PROVISIONING_CONFIRMATION_IP_ACQUIRED (16) +#define SL_WLAN_PROVISIONING_EXTERNAL_CONFIGURATION_READY (17) + +#define SL_WLAN_SEC_TYPE_OPEN (0) +#define SL_WLAN_SEC_TYPE_WEP (1) +#define SL_WLAN_SEC_TYPE_WPA (2) /* deprecated */ +#define SL_WLAN_SEC_TYPE_WPA_WPA2 (2) +#define SL_WLAN_SEC_TYPE_WPS_PBC (3) +#define SL_WLAN_SEC_TYPE_WPS_PIN (4) +#define SL_WLAN_SEC_TYPE_WPA_ENT (5) +#define SL_WLAN_SEC_TYPE_P2P_PBC (6) +#define SL_WLAN_SEC_TYPE_P2P_PIN_KEYPAD (7) +#define SL_WLAN_SEC_TYPE_P2P_PIN_DISPLAY (8) +#define SL_WLAN_SEC_TYPE_P2P_PIN_AUTO (9) /* NOT Supported yet */ +#define SL_WLAN_SEC_TYPE_WEP_SHARED (10) + +#define SL_TLS (0x1) +#define SL_MSCHAP (0x0) +#define SL_PSK (0x2) +#define SL_TTLS (0x10) +#define SL_PEAP0 (0x20) +#define SL_PEAP1 (0x40) +#define SL_FAST (0x80) + +#define SL_WLAN_FAST_AUTH_PROVISIONING (0x02) +#define SL_WLAN_FAST_UNAUTH_PROVISIONING (0x01) +#define SL_WLAN_FAST_NO_PROVISIONING (0x00) + +#define SL_WLAN_PROVISIONING_CMD_START_MODE_AP (0) +#define SL_WLAN_PROVISIONING_CMD_START_MODE_SC (1) +#define SL_WLAN_PROVISIONING_CMD_START_MODE_APSC (2) +#define SL_WLAN_PROVISIONING_CMD_START_MODE_APSC_EXTERNAL_CONFIGURATION (3) +#define SL_WLAN_PROVISIONING_CMD_STOP (4) +#define SL_WLAN_PROVISIONING_CMD_ABORT_EXTERNAL_CONFIRMATION (5) + +/* Provisioning API Flags */ +#define SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION (0x00000001) + +/* to be used only in provisioning stop command */ +#define SL_WLAN_PROVISIONING_REMAIN_IN_CURRENT_ROLE (0xFF) + + +#define SL_WLAN_EAPMETHOD_PHASE2_SHIFT (8) +#define SL_WLAN_EAPMETHOD_PAIRWISE_CIPHER_SHIFT (19) +#define SL_WLAN_EAPMETHOD_GROUP_CIPHER_SHIFT (27) + +#define SL_WLAN_WPA_CIPHER_CCMP (0x1) +#define SL_WLAN_WPA_CIPHER_TKIP (0x2) +#define SL_WLAN_CC31XX_DEFAULT_CIPHER (SL_WLAN_WPA_CIPHER_CCMP | SL_WLAN_WPA_CIPHER_TKIP) + +#define SL_WLAN_EAPMETHOD(phase1,phase2,pairwise_cipher,group_cipher) \ + ((phase1) | \ + ((phase2) << SL_WLAN_EAPMETHOD_PHASE2_SHIFT ) |\ + ((_u32)(pairwise_cipher) << SL_WLAN_EAPMETHOD_PAIRWISE_CIPHER_SHIFT ) |\ + ((_u32)(group_cipher) << SL_WLAN_EAPMETHOD_GROUP_CIPHER_SHIFT )) + +/* phase1 phase2 pairwise_cipher group_cipher */ +#define SL_WLAN_ENT_EAP_METHOD_TLS SL_WLAN_EAPMETHOD(SL_TLS, 0, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_TTLS_TLS SL_WLAN_EAPMETHOD(SL_TTLS, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_TTLS_MSCHAPv2 SL_WLAN_EAPMETHOD(SL_TTLS, SL_MSCHAP, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_TTLS_PSK SL_WLAN_EAPMETHOD(SL_TTLS, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_PEAP0_TLS SL_WLAN_EAPMETHOD(SL_PEAP0, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_PEAP0_MSCHAPv2 SL_WLAN_EAPMETHOD(SL_PEAP0, SL_MSCHAP, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_PEAP0_PSK SL_WLAN_EAPMETHOD(SL_PEAP0, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_PEAP1_TLS SL_WLAN_EAPMETHOD(SL_PEAP1, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_PEAP1_PSK SL_WLAN_EAPMETHOD(SL_PEAP1, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_FAST_AUTH_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_AUTH_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_FAST_UNAUTH_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_UNAUTH_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) +#define SL_WLAN_ENT_EAP_METHOD_FAST_NO_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_NO_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) + +#define SL_WLAN_LONG_PREAMBLE (0) +#define SL_WLAN_SHORT_PREAMBLE (1) + +#define SL_WLAN_RAW_RF_TX_PARAMS_CHANNEL_SHIFT (0) +#define SL_WLAN_RAW_RF_TX_PARAMS_RATE_SHIFT (6) +#define SL_WLAN_RAW_RF_TX_PARAMS_POWER_SHIFT (11) +#define SL_WLAN_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT (15) + +#define SL_WLAN_RAW_RF_TX_PARAMS(chan,rate,power,preamble) \ + ((chan << SL_WLAN_RAW_RF_TX_PARAMS_CHANNEL_SHIFT) | \ + (rate << SL_WLAN_RAW_RF_TX_PARAMS_RATE_SHIFT) | \ + (power << SL_WLAN_RAW_RF_TX_PARAMS_POWER_SHIFT) | \ + (preamble << SL_WLAN_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT)) + + +/* wlan config application IDs */ +#define SL_WLAN_CFG_AP_ID (0) +#define SL_WLAN_CFG_GENERAL_PARAM_ID (1) +#define SL_WLAN_CFG_P2P_PARAM_ID (2) +#define SL_WLAN_CFG_AP_ACCESS_LIST_ID (3) +#define SL_WLAN_RX_FILTERS_ID (4) +#define SL_WLAN_CONNECTION_INFO (5) + +/* wlan AP Config set/get options */ +#define SL_WLAN_AP_OPT_SSID (0) +#define SL_WLAN_AP_OPT_CHANNEL (3) +#define SL_WLAN_AP_OPT_HIDDEN_SSID (4) +#define SL_WLAN_AP_OPT_SECURITY_TYPE (6) +#define SL_WLAN_AP_OPT_PASSWORD (7) +#define SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE (9) +#define SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER (10) +#define SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER (11) + + + +#define SL_WLAN_P2P_OPT_DEV_NAME (12) +#define SL_WLAN_P2P_OPT_DEV_TYPE (13) +#define SL_WLAN_P2P_OPT_CHANNEL_N_REGS (14) +#define SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT (16) +#define SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS (18) /* change the scan channels and RSSI threshold using this configuration option */ +#define SL_WLAN_AP_OPT_MAX_STATIONS (19) +#define SL_WLAN_AP_ACCESS_LIST_ADD_MAC (20) +#define SL_WLAN_AP_ACCESS_LIST_DEL_MAC (21) +#define SL_WLAN_AP_ACCESS_LIST_DEL_IDX (22) +#define SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES (24) +#define SL_WLAN_AP_ACCESS_LIST_MODE (25) +#define SL_WLAN_AP_OPT_MAX_STA_AGING (26) + +#define SL_WLAN_RX_FILTER_STATE (27) +#define SL_WLAN_RX_FILTER_REMOVE (28) +#define SL_WLAN_RX_FILTER_STORE (29) +#define SL_WLAN_RX_FILTER_UPDATE_ARGS (30) +#define SL_WLAN_RX_FILTER_SYS_STATE (31) +#define SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH (32) +#define SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES (33) + + + +/* SmartConfig CIPHER options */ +#define SL_WLAN_SMART_CONFIG_CIPHER_SFLASH (0) /* password is not delivered by the application. The Simple Manager should + check if the keys are stored in the Flash. */ +#define SL_WLAN_SMART_CONFIG_CIPHER_AES (1) /* AES (other types are not supported) */ +#define SL_WLAN_SMART_CONFIG_CIPHER_NONE (0xFF) /* do not check in the flash */ + + +#define SL_WLAN_POLICY_CONNECTION (0x10) +#define SL_WLAN_POLICY_SCAN (0x20) +#define SL_WLAN_POLICY_PM (0x30) +#define SL_WLAN_POLICY_P2P (0x40) + +#define SL_WLAN_VAL_2_MASK(position,value) ((1 & (value))<<(position)) +#define SL_WLAN_MASK_2_VAL(position,mask) (((1 << position) & (mask)) >> (position)) + +#define SL_WLAN_CONNECTION_POLICY(Auto,Fast,anyP2P,autoProvisioning) (SL_WLAN_VAL_2_MASK(0,Auto) | SL_WLAN_VAL_2_MASK(1,Fast) | SL_WLAN_VAL_2_MASK(2,0) | SL_WLAN_VAL_2_MASK(3,anyP2P) | SL_WLAN_VAL_2_MASK(4,0) | SL_WLAN_VAL_2_MASK(5,autoProvisioning)) +#define SL_WLAN_SCAN_POLICY_EN(policy) (SL_WLAN_MASK_2_VAL(0,policy)) +#define SL_WLAN_SCAN_POLICY(Enable,Enable_Hidden) (SL_WLAN_VAL_2_MASK(0,Enable) | SL_WLAN_VAL_2_MASK(1,Enable_Hidden)) + + +#define SL_WLAN_ENABLE_SCAN (1) +#define SL_WLAN_DISABLE_SCAN (0) +#define SL_WLAN_ALLOW_HIDDEN_SSID_RESULTS (1) +#define SL_WLAN_BLOCK_HIDDEN_SSID_RESULTS (0) + +#define SL_WLAN_NORMAL_POLICY (0) +#define SL_WLAN_LOW_LATENCY_POLICY (1) +#define SL_WLAN_LOW_POWER_POLICY (2) +#define SL_WLAN_ALWAYS_ON_POLICY (3) +#define SL_WLAN_LONG_SLEEP_INTERVAL_POLICY (4) + +#define SL_WLAN_P2P_ROLE_NEGOTIATE (3) +#define SL_WLAN_P2P_ROLE_GROUP_OWNER (15) +#define SL_WLAN_P2P_ROLE_CLIENT (0) + +#define SL_WLAN_P2P_NEG_INITIATOR_ACTIVE (0) +#define SL_WLAN_P2P_NEG_INITIATOR_PASSIVE (1) +#define SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF (2) + +#define SL_WLAN_POLICY_VAL_2_OPTIONS(position,mask,policy) ((mask & policy) << position ) + +#define SL_WLAN_P2P_POLICY(p2pNegType,p2pNegInitiator) (SL_WLAN_POLICY_VAL_2_OPTIONS(0,0xF,(p2pNegType > SL_WLAN_P2P_ROLE_GROUP_OWNER ? SL_WLAN_P2P_ROLE_GROUP_OWNER : p2pNegType)) | \ + SL_WLAN_POLICY_VAL_2_OPTIONS(4,0x1,(p2pNegType > SL_WLAN_P2P_ROLE_GROUP_OWNER ? 1:0)) | \ + SL_WLAN_POLICY_VAL_2_OPTIONS(5,0x3, p2pNegInitiator)) + + +/* Info elements */ +#define SL_WLAN_INFO_ELEMENT_DEFAULT_ID (0) /* 221 will be used */ + +/* info element size is up to 252 bytes (+ 3 bytes of OUI). */ +#define SL_WLAN_INFO_ELEMENT_MAX_SIZE (252) + +/* For AP - the total length of all info elements is 300 bytes (for example - 4 info elements of 75 bytes each) */ +#define SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_AP (300) + +/* For P2P - the total length of all info elements is 160 bytes (for example - 4 info elements of 40 bytes each) */ +#define SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_P2P_GO (160) + +#define SL_WLAN_INFO_ELEMENT_AP_ROLE (0) +#define SL_WLAN_INFO_ELEMENT_P2P_GO_ROLE (1) + +/* we support up to 4 info elements per Role. */ +#define SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED (4) + +#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_0 (0x08) +#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_1 (0x00) +#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_2 (0x28) + +#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI (0x000000) /* 08, 00, 28 will be used */ + +#define SL_WLAN_AP_ACCESS_LIST_MODE_DISABLED 0 +#define SL_WLAN_AP_ACCESS_LIST_MODE_DENY_LIST 1 +#define SL_WLAN_MAX_ACCESS_LIST_STATIONS 8 + + +/* Scan results security information */ +#define SL_WLAN_SCAN_RESULT_GROUP_CIPHER(SecurityInfo) (SecurityInfo & 0xF) /* Possible values: NONE,SL_WLAN_CIPHER_BITMAP_TKIP,SL_WLAN_CIPHER_BITMAP_CCMP */ +#define SL_WLAN_SCAN_RESULT_UNICAST_CIPHER_BITMAP(SecurityInfo) ((SecurityInfo & 0xF0) >> 4 ) /* Possible values: NONE,SL_WLAN_CIPHER_BITMAP_WEP40,SL_WLAN_CIPHER_BITMAP_WEP104,SL_WLAN_CIPHER_BITMAP_TKIP,SL_WLAN_CIPHER_BITMAP_CCMP*/ +#define SL_WLAN_SCAN_RESULT_HIDDEN_SSID(SecurityInfo) (SecurityInfo & 0x2000 ) >> 13 /* Possible values: TRUE/FALSE */ +#define SL_WLAN_SCAN_RESULT_KEY_MGMT_SUITES_BITMAP(SecurityInfo) (SecurityInfo & 0x1800 ) >> 11 /* Possible values: SL_WLAN_KEY_MGMT_SUITE_802_1_X, SL_WLAN_KEY_MGMT_SUITE_PSK */ +#define SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(SecurityInfo) (SecurityInfo & 0x700 ) >> 8 /* Possible values: SL_WLAN_SECURITY_TYPE_BITMAP_OPEN, SL_WLAN_SECURITY_TYPE_BITMAP_WEP, SL_WLAN_SECURITY_TYPE_BITMAP_WPA, SL_WLAN_SECURITY_TYPE_BITMAP_WPA2, 0x6 (mix mode) SL_WLAN_SECURITY_TYPE_BITMAP_WPA | SL_WLAN_SECURITY_TYPE_BITMAP_WPA2 */ + +#define SL_WLAN_SECURITY_TYPE_BITMAP_OPEN 0x0 +#define SL_WLAN_SECURITY_TYPE_BITMAP_WEP 0x1 +#define SL_WLAN_SECURITY_TYPE_BITMAP_WPA 0x2 +#define SL_WLAN_SECURITY_TYPE_BITMAP_WPA2 0x4 + +#define SL_WLAN_CIPHER_BITMAP_WEP40 0x1 +#define SL_WLAN_CIPHER_BITMAP_WEP104 0x2 +#define SL_WLAN_CIPHER_BITMAP_TKIP 0x4 +#define SL_WLAN_CIPHER_BITMAP_CCMP 0x8 + +#define SL_WLAN_KEY_MGMT_SUITE_802_1_X 1 +#define SL_WLAN_KEY_MGMT_SUITE_PSK 2 + + + +#define SL_WLAN_RX_FILTER_MAX_FILTERS (64) /* Max number of filters is 64 filters */ +#define SL_WLAN_RX_FILTER_MAX_SYS_FILTERS_SETS (32) /* The Max number of system filters */ +#define SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS (2) +#define SL_WLAN_RX_FILTER_NUM_OF_FILTER_PAYLOAD_ARGS (2) +#define SL_WLAN_RX_FILTER_RANGE_ARGS (2) +#define SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID (64) +#define SL_WLAN_RX_FILTER_MAX_USER_EVENT_ID ( ( SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID ) - 1 ) + +/* Bit manipulation for 8 bit */ +#define SL_WLAN_ISBITSET8(x,i) ((x[i>>3] & (0x80>>(i&7)))!=0) /* Is bit set, 8 bit unsigned numbers = x , location = i */ +#define SL_WLAN_SETBIT8(x,i) x[i>>3]|=(0x80>>(i&7)); /* Set bit,8 bit unsigned numbers = x , location = i */ +#define SL_WLAN_CLEARBIT8(x,i) x[i>>3]&=(0x80>>(i&7))^0xFF; /* Clear bit,8 bit unsigned numbers = x , location = i */ + + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +typedef enum +{ + SL_WLAN_RATE_1M = 1, + SL_WLAN_RATE_2M = 2, + SL_WLAN_RATE_5_5M = 3, + SL_WLAN_RATE_11M = 4, + SL_WLAN_RATE_6M = 6, + SL_WLAN_RATE_9M = 7, + SL_WLAN_RATE_12M = 8, + SL_WLAN_RATE_18M = 9, + SL_WLAN_RATE_24M = 10, + SL_WLAN_RATE_36M = 11, + SL_WLAN_RATE_48M = 12, + SL_WLAN_RATE_54M = 13, + SL_WLAN_RATE_MCS_0 = 14, + SL_WLAN_RATE_MCS_1 = 15, + SL_WLAN_RATE_MCS_2 = 16, + SL_WLAN_RATE_MCS_3 = 17, + SL_WLAN_RATE_MCS_4 = 18, + SL_WLAN_RATE_MCS_5 = 19, + SL_WLAN_RATE_MCS_6 = 20, + SL_WLAN_RATE_MCS_7 = 21, + SL_WLAN_MAX_NUM_RATES = 0xFF +}SlWlanRateIndex_e; + +typedef enum +{ + SL_WLAN_DEV_PW_DEFAULT = 0, + SL_WLAN_DEV_PW_PIN_KEYPAD = 1, + SL_WLAN_DEV_PW_PUSH_BUTTON = 4, + SL_WLAN_DEV_PW_PIN_DISPLAY = 5 +} SlWlanP2pDevPwdMethod_e; + +typedef struct +{ + _u32 Status; + _u32 SsidLen; + _u8 Ssid[32]; + _u32 PrivateTokenLen; + _u8 PrivateToken[32]; +}SlWlanSmartConfigStartAsyncResponse_t; + +typedef struct +{ + _u16 Status; + _u16 Padding; +}SlWlanSmartConfigStopAsyncResponse_t; + +typedef struct +{ + _u16 Status; + _u16 Padding; +}SlWlanConnFailureAsyncResponse_t; + +typedef struct +{ + _u16 Status; + _u16 Padding; +}SlWlanProvisioningStatusAsyncResponse_t; + +/* rx filter event struct + this event will be sent from the SL device + as a result of a passed rx filter + example: + suppose we have a filter with an action and we set the following: + SlWlanRxFilterAction_t Action; + Action.UserId = 2; + When the filter result is pass, an SlWlanEventRxFilterInfo_t event will be passed to the user as follows: + Type will be set to 0 + bit 2 in UserActionIdBitmap will be set in this event, because 2 is the user input for the action arg above. + an SlWlanEventRxFilterInfo_t event may have several bits set as a result of several rx filters causing different + events to pass */ + +typedef struct +{ + _u8 Type; /* Currently only event type 0 is supported. */ + _u8 UserActionIdBitmap[SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID / 8]; /* Bit X is set indicates that the filter with event action arg X passed. */ +}SlWlanEventRxFilterInfo_t; + +typedef enum +{ + ROLE_STA = 0, + ROLE_RESERVED = 1, + ROLE_AP = 2, + ROLE_P2P = 3, + ROLE_RESERVED2 = 4 +}SlWlanMode_e; + +typedef struct +{ + _u8 SsidLen; + _u8 SsidName[32]; + _u8 Bssid[6]; + _u8 Padding; +} SlWlanEventConnect_t; + +typedef struct +{ + _u8 SsidLen; + _u8 SsidName[32]; + _u8 Bssid[6]; + _u8 ReasonCode; +} SlWlanEventDisconnect_t; + +typedef struct +{ + _u8 Mac[6]; + _u8 Padding[2]; +}SlWlanEventSTAAdded_t, SlWlanEventSTARemoved_t; + + +typedef struct +{ + _u8 SsidLen; + _u8 SsidName[32]; + _u8 Bssid[6]; + _u8 Reserved; + _u8 GoDeviceNameLen; + _u8 GoDeviceName[32]; + _u8 Padding[3]; +} SlWlanEventP2PConnect_t; + +typedef struct +{ + _u8 SsidLen; + _u8 SsidName[32]; + _u8 Bssid[6]; + _u8 ReasonCode; + _u8 GoDeviceNameLen; + _u8 GoDeviceName[32]; + _u8 Padding[3]; +} SlWlanEventP2PDisconnect_t; + +typedef struct +{ + _u8 Mac[6]; + _u8 ClDeviceNameLen; + _u8 ClDeviceName[32]; + _u8 OwnSsidLen; + _u8 OwnSsid[32]; +}SlWlanEventP2PClientAdded_t, SlWlanEventP2PClientRemoved_t; + +typedef struct +{ + _u8 GoDeviceNameLen; + _u8 GoDeviceName[32]; + _u8 Mac[6]; + _u8 WpsMethod; +}SlWlanEventP2PDevFound_t, SlWlanEventP2PRequest_t; + +/**************************************************/ +typedef struct +{ + _u16 Status; + _u16 Padding; +}SlWlanEventP2PConnectFail_t; + +typedef struct +{ + _u8 ProvisioningStatus; + _u8 Role; + _u8 WlanStatus; + _u8 Ssidlen; + _u8 Ssid[32]; + _u32 Reserved; +}SlWlanEventProvisioningStatus_t; + +typedef struct +{ + _u32 Status; + _u32 SsidLen; + _u8 Ssid[32]; + _u32 ReservedLen; + _u8 Reserved[32]; +} SlWlanEventProvisioningProfileAdded_t; + +typedef union +{ + SlWlanEventConnect_t Connect; /* SL_WLAN_EVENT_CONNECT */ + SlWlanEventDisconnect_t Disconnect; /* SL_WLAN_EVENT_DISCONNECT */ + SlWlanEventSTAAdded_t STAAdded; /* SL_WLAN_EVENT_STA_ADDED */ + SlWlanEventSTARemoved_t STARemoved; /* SL_WLAN_EVENT_STA_REMOVED */ + SlWlanEventP2PConnect_t P2PConnect; /* SL_WLAN_EVENT_P2P_CONNECT */ + SlWlanEventP2PDisconnect_t P2PDisconnect; /* SL_WLAN_EVENT_P2P_DISCONNECT */ + SlWlanEventP2PClientAdded_t P2PClientAdded; /* SL_WLAN_EVENT_P2P_CLIENT_ADDED */ + SlWlanEventP2PClientRemoved_t P2PClientRemoved; /* SL_WLAN_EVENT_P2P_CLIENT_REMOVED */ + SlWlanEventP2PDevFound_t P2PDevFound; /* SL_WLAN_EVENT_P2P_DEVFOUND */ + SlWlanEventP2PRequest_t P2PRequest; /* SL_WLAN_EVENT_P2P_REQUEST */ + SlWlanEventP2PConnectFail_t P2PConnectFail; /* SL_WLAN_EVENT_P2P_CONNECTFAIL */ + SlWlanEventRxFilterInfo_t RxFilterInfo; /* SL_WLAN_EVENT_RXFILTER */ + SlWlanEventProvisioningStatus_t ProvisioningStatus; /* SL_WLAN_EVENT_PROVISIONING_STATUS */ + SlWlanEventProvisioningProfileAdded_t ProvisioningProfileAdded; /* SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED */ + +} SlWlanEventData_u; + +typedef struct +{ + _u32 Id; + SlWlanEventData_u Data; +} SlWlanEvent_t; + +typedef struct +{ + _u32 ReceivedValidPacketsNumber; /* sum of the packets that been received OK (include filtered) */ + _u32 ReceivedFcsErrorPacketsNumber; /* sum of the packets that been dropped due to FCS error */ + _u32 ReceivedAddressMismatchPacketsNumber; /* sum of the packets that been received but filtered out by one of the HW filters */ + _i16 AvarageDataCtrlRssi; /* average RSSI for all valid data packets received */ + _i16 AvarageMgMntRssi; /* average RSSI for all valid management packets received */ + _u16 RateHistogram[SL_WLAN_NUM_OF_RATE_INDEXES]; /* rate histogram for all valid packets received */ + _u16 RssiHistogram[SL_WLAN_SIZE_OF_RSSI_HISTOGRAM]; /* RSSI histogram from -40 until -87 (all below and above\n RSSI will appear in the first and last cells */ + _u32 StartTimeStamp; /* the time stamp started collecting the statistics in uSec */ + _u32 GetTimeStamp; /* the time stamp called the get statistics command */ +}SlWlanGetRxStatResponse_t; + +typedef struct +{ + _u8 Ssid[SL_WLAN_SSID_MAX_LENGTH]; + _u8 Bssid[SL_WLAN_BSSID_LENGTH]; + _u8 SsidLen; + _i8 Rssi; + _i16 SecurityInfo; + _u8 Channel; + _i8 Reserved[1]; +}SlWlanNetworkEntry_t; + +typedef struct +{ + _u8 Ssid[SL_WLAN_SSID_MAX_LENGTH]; + _u8 Bssid[SL_WLAN_BSSID_LENGTH]; + _u8 SsidLen; + _i8 Rssi; + _i16 SecurityInfo; + _u8 Channel; + _i8 Reserved[1]; + /* country info extended area */ + _u8 CountryStr[2]; + _u16 Supported_2_4G_Channels; + _u32 Supported_5_0G_Channels; +}SlWlanExtNetworkEntry_t; + +typedef struct +{ + _u8 Type; + _i8* Key; + _u8 KeyLen; +}SlWlanSecParams_t; + +typedef struct +{ + _i8* User; + _u8 UserLen; + _i8* AnonUser; + _u8 AnonUserLen; + _u8 CertIndex; /* not supported */ + _u32 EapMethod; +}SlWlanSecParamsExt_t; + +typedef struct +{ + _i8 User[64]; + _u8 UserLen; + _i8 AnonUser[64]; + _u8 AnonUserLen; + _u8 CertIndex; /* not supported */ + _u32 EapMethod; +}SlWlanGetSecParamsExt_t; + +#define SL_WLAN_CONNECTION_PROTOCOL_STA 1 +#define SL_WLAN_CONNECTION_PROTOCOL_P2PCL 2 + +typedef union +{ + SlWlanEventConnect_t StaConnect; + SlWlanEventP2PConnect_t P2PConnect; +} SlWlanConnectionInfo_u; + +typedef enum +{ + SL_WLAN_DISCONNECTED = 0, + SL_WLAN_CONNECTED_STA, + SL_WLAN_CONNECTED_P2PCL, + SL_WLAN_CONNECTED_P2PGO, + SL_WLAN_AP_CONNECTED_STATIONS +}SlWlanConnStatusFlags_e; + +typedef struct +{ + _u8 Mode; /* ROLE_STA, ROLE_AP, ROLE_P2P */ + _u8 ConnStatus; /* SlWlanConnStatusFlags_e */ + _u8 SecType; /* Current connection security type - (0 in case of disconnect or AP mode) SL_WLAN_SEC_TYPE_OPEN, SL_WLAN_SEC_TYPE_WEP, SL_WLAN_SEC_TYPE_WPA_WPA2, SL_WLAN_SEC_TYPE_WPA_ENT, SL_WLAN_SEC_TYPE_WPS_PBC, SL_WLAN_SEC_TYPE_WPS_PIN */ + _u8 Reserved; + SlWlanConnectionInfo_u ConnectionInfo; +}SlWlanConnStatusParam_t; + +typedef struct +{ + _u32 ChannelsMask; + _i32 RssiThreshold; +}SlWlanScanParamCommand_t; + +typedef struct +{ + _u8 Id; + _u8 Oui[3]; + _u16 Length; + _u8 Data[252]; +} SlWlanInfoElement_t; + +typedef struct +{ + _u8 Index; /* 0 - SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED */ + _u8 Role; /* bit0: AP = 0, GO = 1 */ + SlWlanInfoElement_t IE; +} SlWlanSetInfoElement_t; + +typedef struct +{ + _u16 Reserved; + _u16 Reserved2; + _u16 MaxSleepTimeMs; /* max sleep time in mSec For setting Long Sleep Interval policy use */ + _u16 Reserved3; +} SlWlanPmPolicyParams_t; + +typedef _i8 SlWlanRxFilterID_t; /* Unique filter ID which is allocated by the system , negative number means error */ + +/* Representation of filters Id as a bit field + The bit field is used to declare which filters are involved + in operation. Number of filter can be up to 128 filters. + i.e. 128 bits are needed. On the current release, up to 64 filters can be defined. */ +typedef _u8 SlWlanRxFilterIdMask_t[128/8]; + +typedef _u8 SlWlanRxFilterSysFilters_t; /* Describes the supported system filter sets*/ +/* possible values for SlWlanRxFilterSysFilters_t */ +#define SL_WLAN_RX_FILTER_ARP_AUTO_REPLY_SYS_FILTERS (0) +#define SL_WLAN_RX_FILTER_MULTICASTSIPV4_SYS_FILTERS (1) +#define SL_WLAN_RX_FILTER_MULTICASTSIPV6_SYS_FILTERS (2) +#define SL_WLAN_RX_FILTER_MULTICASTSWIFI_SYS_FILTERS (3) +#define SL_WLAN_RX_FILTER_SELF_MAC_ADDR_DROP_SYS_FILTERS (4) + +/* Describes the supported system filter sets, each bit represents different system filter set + The filter sets are defined at SlWlanRxFilterSysFilters_t */ +typedef _u8 SlWlanRxFilterSysFiltersMask_t[SL_WLAN_RX_FILTER_MAX_SYS_FILTERS_SETS/8]; + +typedef struct +{ + _u16 Offset; /* Offset in payload - Where in the payload to search for the pattern */ + _u8 Length; /* Pattern Length */ + _u8 Reserved; + _u8 Value[16]; /* Up to 16 bytes long (based on pattern length above) */ +}SlWlanRxFilterPatternArg_t; + +typedef _u8 SlWlanRxFilterRuleType_t; /* Different filter types */ +/* possible values for SlWlanRxFilterRuleType_t */ +#define SL_WLAN_RX_FILTER_HEADER (0) +#define SL_WLAN_RX_FILTER_COMBINATION (1) + +typedef _u8 SlWlanRxFilterFlags_u; +/* Possible values for SlWlanRxFilterFlags_u */ +#define SL_WLAN_RX_FILTER_BINARY (0x1) +#define SL_WLAN_RX_FILTER_PERSISTENT (0x8) +#define SL_WLAN_RX_FILTER_ENABLE (0x10) + +/* Used as comparison function for the header type arguments */ +typedef _u8 SlWlanRxFilterRuleHeaderCompareFunction_t; +/* Possible values for SlWlanRxFilterRuleHeaderCompareFunction_t */ +#define SL_WLAN_RX_FILTER_CMP_FUNC_IN_BETWEEN (0) +#define SL_WLAN_RX_FILTER_CMP_FUNC_EQUAL (1) +#define SL_WLAN_RX_FILTER_CMP_FUNC_NOT_EQUAL_TO (2) +#define SL_WLAN_RX_FILTER_CMP_FUNC_NOT_IN_BETWEEN (3) + +typedef _u8 SlWlanRxFilterTriggerCompareFunction_t; +/* Possible values for SlWlanRxFilterTriggerCompareFunction_t */ +#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_EQUAL (0) +#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_NOT_EQUAL_TO (1) /* arg1 == protocolVal ,not supported in current release */ +#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_SMALLER_THAN (2) /* arg1 == protocolVal */ +#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_BIGGER_THAN (3) /* arg1 == protocolVal */ + +typedef _u8 SlWlanRxFilterRuleHeaderField_t; /* Provides list of possible header types which may be defined as part of the rule */ +/* Possible values for SlWlanRxFilterRuleHeaderField_t */ +#define SL_WLAN_RX_FILTER_HFIELD_NULL (0) +#define SL_WLAN_RX_FILTER_HFIELD_FRAME_TYPE (1) /* 802.11 control\data\management */ +#define SL_WLAN_RX_FILTER_HFIELD_FRAME_SUBTYPE (2) /* 802.11 beacon\probe\.. */ +#define SL_WLAN_RX_FILTER_HFIELD_BSSID (3) /* 802.11 bssid type */ +#define SL_WLAN_RX_FILTER_HFIELD_MAC_SRC_ADDR (4) +#define SL_WLAN_RX_FILTER_HFIELD_MAC_DST_ADDR (5) +#define SL_WLAN_RX_FILTER_HFIELD_FRAME_LENGTH (6) +#define SL_WLAN_RX_FILTER_HFIELD_ETHER_TYPE (7) +#define SL_WLAN_RX_FILTER_HFIELD_IP_VERSION (8) +#define SL_WLAN_RX_FILTER_HFIELD_IP_PROTOCOL (9) /* TCP / UDP / ICMP / ICMPv6 / IGMP */ +#define SL_WLAN_RX_FILTER_HFIELD_IPV4_SRC_ADDR (10) +#define SL_WLAN_RX_FILTER_HFIELD_IPV4_DST_ADDR (11) +#define SL_WLAN_RX_FILTER_HFIELD_IPV6_SRC_ADRR (12) +#define SL_WLAN_RX_FILTER_HFIELD_IPV6_DST_ADDR (13) +#define SL_WLAN_RX_FILTER_HFIELD_PORT_SRC (14) +#define SL_WLAN_RX_FILTER_HFIELD_PORT_DST (15) +#define SL_WLAN_RX_FILTER_HFIELD_L4_PAYLOAD_PATTERN (19) /* use to look for patterns on the TCP and UDP payloads (after TCP/UDP header) */ +#define SL_WLAN_RX_FILTER_HFIELD_L1_PAYLOAD_PATTERN (20) /* use to look for patterns on the PHY payload (i.e. beginning of WLAN MAC header) */ +#define SL_WLAN_RX_FILTER_HFIELD_MAX_FIELD (21) /* Definition */ + +/* Holds the header ARGS which are used in case of HDR rule */ +typedef union +{ + /* buffer for pattern matching in payload up to 16 bytes (Binary Values) */ + SlWlanRxFilterPatternArg_t Pattern; + + /* Buffer for ipv4 address filter. binary arguments, number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ + _u8 Ipv4[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][4]; /* Binary Values for comparison */ + + /* Buffer for ipv4 address filter. Ascii arguments - IPv4 address: 4 bytes: ddd.ddd.ddd.ddd - 15 chars. Number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ + _u8 Ipv4Ascii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][16]; /* Ascii Values for comparison */ + + /* Buffer for ipv6 address filter. binary arguments, Ascii format is not supported. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ + _u8 Ipv6[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][16]; /* Binary Values for comparison */ + + /* Buffer for mac address filter. binary arguments. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ + _u8 Mac[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][6]; /* Binary Values for comparison */ + + /* Buffer for mac address filter. Ascii arguments - MAC address: 6 bytes: xx:xx:xx:xx:xx:xx - 17 chars. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ + _u8 MacAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][18]; /* Ascii Values for comparison */ + + /* Buffer for BSSID address filter. binary arguments. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ + _u8 Bssid[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][6]; /* Binary Values for comparison */ + + /* Buffer for frame length filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ + _u32 FrameLength[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ + + /* Buffer for port filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ + _u32 Port[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ + + /* Buffer for Ether filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS (according to host endianity) */ + _u32 EtherType[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ + + /* Buffer for ip version filter. Buffer for binary arguments. IP Version - 4 for IPV4 and 6 for IPV6 */ + _u8 IpVersion; + + /* Buffer for frame type filter. Buffer for binary arguments. Frame Type (0 - management, 1 - Control, 2 - Data) */ + _u8 Frametype[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; + + /* Buffer for frame subtype filter. Buffer for binary arguments. Frame Sub Type (checkout the full list in the 802.11 spec). e.g. Beacon=0x80, Data=0x08, Qos-Data=0x04, ACK=0xD4, etc. */ + _u8 FrameSubtype[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; + + /* Buffer for protocol type filter. Buffer for binary arguments. e.g. 1 – ICMP (IPV4 only), 2 - IGMP (IPV4 only), 6 – TCP. 17 – UDP, 58 – ICMPV6 */ + _u8 IpProtocol[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; + + /* Buffer for ip version filter. Buffer for ASCII arguments. Use for IP version field comparison settings: "IPV4", "IPV6" */ + _u8 IpVersionAscii[4]; + + /* Buffer for frame type filter. Buffer for ASCII arguments. Use for Frame type field comparison settings: "MGMT", "CTRL", "DATA" */ + _u8 FrametypeAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][4]; + + /* Buffer for protocol type filter. Buffer for ASCII arguments. Use for protocol field comparison settings: "ICMP", "IGMP", "TCP, "UDP", "ICMP6" */ + /* Note: Use memcpy with these strings instead of strcpy (no \0 should be at the end, as the array is 5 bytes long and ICMP6 is already 5 bytes long without the \0) */ + _u8 IpProtocolAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][5]; + +}SlWlanRxFilterHeaderArg_u; + +/* Defines the Header Args and mask */ +typedef struct +{ + SlWlanRxFilterHeaderArg_u Value; /* Argument for the comparison function */ + _u8 Mask[16]; /* the mask is used in order to enable partial comparison (bit level), Use the 0xFFFFFFFF in case you don't want to use mask */ + +}SlWlanRxFilterRuleHeaderArgs_t; + +/* defines the Header rule. The header rule defines the compare function on the protocol header + For example destMacAddre is between ( 12:6::78:77, 12:6::78:90 ) */ +typedef struct +{ + SlWlanRxFilterRuleHeaderArgs_t Args; /* Filter arguments */ + SlWlanRxFilterRuleHeaderField_t Field; /* Packet HDR field which will be compared to the argument */ + SlWlanRxFilterRuleHeaderCompareFunction_t CompareFunc; /* type of the comparison function */ + _u8 Padding[2]; +}SlWlanRxFilterRuleHeader_t; + +/* Optional operators for the combination type filterID1 is located in the first arg , filterId2 is the second arg */ +typedef _u8 SlWlanRxFilterRuleCombinationOperator_t; +/* Possible values for SlWlanRxFilterRuleCombinationOperator_t */ +#define SL_WLAN_RX_FILTER_COMBINED_FUNC_NOT (0) /* filterID1 */ +#define SL_WLAN_RX_FILTER_COMBINED_FUNC_AND (1) /* filterID1 && filterID2 */ +#define SL_WLAN_RX_FILTER_COMBINED_FUNC_OR (2) /* filterID1 && filterID2 */ + +/* Defines the structure which define the combination type filter + The combined filter enable to make operation on one or two filter, + for example filterId1 or and(filterId2,filterId3). */ +typedef struct +{ + SlWlanRxFilterRuleCombinationOperator_t Operator; /* combination operator */ + SlWlanRxFilterID_t CombinationFilterId[SL_WLAN_RX_FILTER_RANGE_ARGS]; /* filterID, may be one or two depends on the combination operator type */ + _u8 Padding; +}SlWlanRxFilterRuleCombination_t; + +/* Rule structure composed of behavioral flags and the filter rule definitions */ +typedef union +{ + SlWlanRxFilterRuleHeader_t Header; /* Filter is from type Header */ + SlWlanRxFilterRuleCombination_t Combination; /* Filter is from type Combination */ +}SlWlanRxFilterRule_u; + +/* Bit field which represents the roleId possible values + In the current release only Station (with or without promiscuous modes) and AP roles are supported. + Activating filters before P2P negotiations (i.e. decision whether role is CL or GO) may result with + unexpected behaviour. After this stage, filters can be activated whereas STA role is the equivalent of P2P CL role + AP role is the equivalent of P2P GO role. + */ +typedef _u8 SlWlanRxFilterTriggerRoles_t; +/* Possible values for SlWlanRxFilterTriggerRoles_t */ +#define SL_WLAN_RX_FILTER_ROLE_AP (1) +#define SL_WLAN_RX_FILTER_ROLE_STA (2) +#define SL_WLAN_RX_FILTER_ROLE_TRANCIEVER (4) +#define SL_WLAN_RX_FILTER_ROLE_NULL (0) + +typedef _u8 SlWlanRxFilterTriggerConnectionStates_t; +/* Possible values for SlWlanRxFilterTriggerConnectionStates_t */ +#define SL_WLAN_RX_FILTER_STATE_STA_CONNECTED (0x1) +#define SL_WLAN_RX_FILTER_STATE_STA_NOT_CONNECTED (0x2) +#define SL_WLAN_RX_FILTER_STATE_STA_HAS_IP (0x4) +#define SL_WLAN_RX_FILTER_STATE_STA_HAS_NO_IP (0x8) + +/* There are 8 possible counter. if no counter is needed set to NO_TRIGGER_COUNTER */ +typedef _u8 SlWlanRxFilterCounterId_t; +/* Possible values for SlWlanRxFilterCounterId_t */ +#define SL_WLAN_RX_FILTER_NO_TRIGGER_COUNTER (0) +#define SL_WLAN_RX_FILTER_COUNTER1 (1) +#define SL_WLAN_RX_FILTER_COUNTER2 (2) +#define SL_WLAN_RX_FILTER_COUNTER3 (3) +#define SL_WLAN_RX_FILTER_COUNTER4 (4) +#define SL_WLAN_RX_FILTER_COUNTER5 (5) +#define SL_WLAN_RX_FILTER_COUNTER6 (6) +#define SL_WLAN_RX_FILTER_COUNTER7 (7) +#define SL_WLAN_RX_FILTER_COUNTER8 (8) +#define SL_WLAN_RX_FILTER_MAX_COUNTER (9) + +/* The filter trigger, determine when the filter is triggered, + The filter is triggered in the following condition :\n + 1. The filter parent is triggered\n + 2. The requested connection type exists, i.e. wlan_connect\n + 3. The filter role is the same as the system role\n */ +typedef struct +{ + SlWlanRxFilterID_t ParentFilterID; /* The parent filter ID, this is the way to build filter tree. NULL value means tree root */ + SlWlanRxFilterCounterId_t Counter; /* Trigger only when reach counter threshold */ + SlWlanRxFilterTriggerConnectionStates_t ConnectionState; /* Trigger only with specific connection state */ + SlWlanRxFilterTriggerRoles_t Role; /* Trigger only with specific role */ + _u32 CounterVal; /* Value for the counter if set */ + SlWlanRxFilterTriggerCompareFunction_t CompareFunction; /* The compare function refers to the counter if set */ + _u8 Padding[3]; +} SlWlanRxFilterTrigger_t; + +/* The actions are executed only if the filter is matched,\n + * In case of false match the packet is transferred to the HOST. \n + * The action is composed of bit field structure, up to 2 actions can be defined per filter.\n */ +typedef _u8 SlWlanRxFilterActionType_t; +/* Possible values for SlWlanRxFilterActionType_t */ +#define SL_WLAN_RX_FILTER_ACTION_NULL (0x0) /* No action to execute*/ +#define SL_WLAN_RX_FILTER_ACTION_DROP (0x1) /* If not dropped ,The packet is passed to the next filter or in case it is the last filter to the host */ +#define SL_WLAN_RX_FILTER_ACTION_ON_REG_INCREASE (0x4) /* action increase counter registers */ +#define SL_WLAN_RX_FILTER_ACTION_ON_REG_DECREASE (0x8) /* action decrease counter registers */ +#define SL_WLAN_RX_FILTER_ACTION_ON_REG_RESET (0x10)/* action reset counter registers */ +#define SL_WLAN_RX_FILTER_ACTION_SEND_TEMPLATE (0x20)/* unsupported */ +#define SL_WLAN_RX_FILTER_ACTION_EVENT_TO_HOST (0x40)/* action can send events to host */ + +/* Several actions can be defined The action is executed in case the filter rule is matched. */ +typedef struct +{ + SlWlanRxFilterActionType_t Type; /* Determine which actions are supported */ + _u8 Counter; /* The counter in use. In case the action is of type increase\decrease\reset this arg will contain the counter number, The counter number values are as in ::SlWlanRxFilterCounterId_t.\n*/ + _u16 Reserved; /* Must be set to zero */ + _u8 UserId; /* In case action set to host event, user can set id which will return in the event arguments */ + _u8 Padding[3]; + +} SlWlanRxFilterAction_t; + +/* The supported operation: SL_WLAN_RX_FILTER_STATE, SL_WLAN_RX_FILTER_REMOVE */ +typedef struct +{ + SlWlanRxFilterIdMask_t FilterBitmap; + _u8 Padding[4]; + +} SlWlanRxFilterOperationCommandBuff_t; + +/* The supported operation: SL_WLAN_RX_FILTER_UPDATE_ARGS */ +typedef struct +{ + _u8 FilterId; + _u8 BinaryOrAscii; /* Set 1 for Binary argument representation, 0 - for Ascii representation */ + _u8 Padding[2]; + SlWlanRxFilterRuleHeaderArgs_t Args; + + +} SlWlanRxFilterUpdateArgsCommandBuff_t; + +/* Filters bitmap enable\disable status return value */ +typedef struct +{ + SlWlanRxFilterIdMask_t FilterIdMask; /* The filter set bit map */ + +}SlWlanRxFilterRetrieveStateBuff_t; + +/* Disbale/Enable system filters */ +typedef struct +{ + SlWlanRxFilterSysFiltersMask_t FilterBitmap; /* The filter set bit map */ + +} SlWlanRxFilterSysFiltersSetStateBuff_t; + +/* System filters status return value */ +typedef struct +{ + SlWlanRxFilterSysFiltersMask_t FilterBitmap; /* The filter get bit map */ + +} SlWlanRxFilterSysFiltersRetrieveStateBuff_t; + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + + +/*! + \brief Connect to wlan network as a station + + \param[in] pName Up to 32 bytes in case of STA the name is the SSID of the Access Point + \param[in] NameLen Name length + \param[in] pMacAddr 6 bytes for MAC address + \param[in] pSecParams Security parameters (use NULL key for SL_WLAN_SEC_TYPE_OPEN)\n + security types options: + - SL_WLAN_SEC_TYPE_OPEN + - SL_WLAN_SEC_TYPE_WEP + - SL_WLAN_SEC_TYPE_WEP_SHARED + - SL_WLAN_SEC_TYPE_WPA_WPA2 + - SL_WLAN_SEC_TYPE_WPA_ENT + - SL_WLAN_SEC_TYPE_WPS_PBC + - SL_WLAN_SEC_TYPE_WPS_PIN + + \param[in] pSecExtParams Enterprise parameters (set NULL in case Enterprise parameters is not in use) + + \return Zero on success, or negative error code on failure + + + \sa sl_WlanDisconnect + \note Belongs to \ref ext_api + \warning In this version only single enterprise mode could be used\n + SL_WLAN_SEC_TYPE_WPA is a deprecated definition, the new definition is SL_WLAN_SEC_TYPE_WPA_WPA2 + \par Example + + - Connect without security: + \code + SlWlanSecParams_t secParams; + secParams.Key = ""; + secParams.KeyLen = 0; + secParams.Type = SL_WLAN_SEC_TYPE_OPEN; + sl_WlanConnect("ssid_name", strlen("ssid_name"),0,&secParams,0); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_WlanConnect) +_i16 sl_WlanConnect(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams); +#endif + +/*! + \brief Wlan disconnect + + Disconnect connection + + \return Zero disconnected done successfully, other already disconnected + + \sa sl_WlanConnect + \note belongs to \ref ext_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_WlanDisconnect) +_i16 sl_WlanDisconnect(void); +#endif + +/*! + \brief Add profile + + When auto start is enabled, the device connects to a + station from the profiles table. Up to 7 profiles (SL_WLAN_MAX_PROFILES) are + supported.\n If several profiles configured the device chose + the highest priority profile, within each priority group, + device will chose profile based on security policy, signal + strength, etc parameters. + + \param[in] pName Up to 32 bytes in case of STA the name is the + SSID of the Access Point.\n + In case of P2P the name is the remote device name. + \param[in] NameLen Name length + \param[in] pMacAddr 6 bytes for MAC address + \param[in] pSecParams Security parameters (use NULL key for SL_WLAN_SEC_TYPE_OPEN)\n + Security types options: + - SL_WLAN_SEC_TYPE_OPEN + - SL_WLAN_SEC_TYPE_WEP + - SL_WLAN_SEC_TYPE_WEP_SHARED + - SL_WLAN_SEC_TYPE_WPA_WPA2 + - SL_WLAN_SEC_TYPE_WPA_ENT + - SL_WLAN_SEC_TYPE_WPS_PBC + - SL_WLAN_SEC_TYPE_WPS_PIN + + \param[in] pSecExtParams Enterprise parameters - identity, identity length, + Anonymous, Anonymous length, CertIndex (not supported, + certificates need to be placed in a specific file ID), + EapMethod.\n Use NULL in case Enterprise parameters is not in use + + \param[in] Priority Profile priority. Lowest priority: 0, Highest priority: 15. + \param[in] Options Not supported + + \return Profile stored index on success, or negative error code on failure. + \par Persistent + Profiles are Persistent + \sa sl_WlanProfileGet , sl_WlanProfileDel + \note belongs to \ref ext_api + \warning Only one Enterprise profile is supported.\n + Please Note that in case of adding an existing profile (compared by pName,pMACAddr and security type) + the old profile will be deleted and the same index will be returned.\n + SL_WLAN_SEC_TYPE_WPA is a deprecated definition, the new definition is SL_WLAN_SEC_TYPE_WPA_WPA2 + +*/ +#if _SL_INCLUDE_FUNC(sl_WlanProfileAdd) +_i16 sl_WlanProfileAdd(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority,const _u32 Options); +#endif + +/*! + \brief Get profile + + Read profile from the device + + \param[in] Index Profile stored index, if index does not exists error is return + \param[out] pName Up to 32 bytes, in case of sta mode the name of the Access Point\n + In case of p2p mode the name of the Remote Device + \param[out] pNameLen Name length + \param[out] pMacAddr 6 bytes for MAC address + \param[out] pSecParams Security parameters. Security types options: + - SL_WLAN_SEC_TYPE_OPEN + - SL_WLAN_SEC_TYPE_WEP + - SL_WLAN_SEC_TYPE_WEP_SHARED + - SL_WLAN_SEC_TYPE_WPA_WPA2 + - SL_WLAN_SEC_TYPE_WPA_ENT + - SL_WLAN_SEC_TYPE_WPS_PBC + - SL_WLAN_SEC_TYPE_WPS_PIN + Key and key length are not return. In case of p2p security type pin the key refers to pin code + return due to security reasons. + \param[out] pSecExtParams Enterprise parameters - identity, identity + length, Anonymous, Anonymous length + CertIndex (not supported), EapMethod. + \param[out] pPriority Profile priority + + \return Profile security type is returned (0 or positive number) on success, or negative error code on failure + SL_ERROR_WLAN_GET_PROFILE_INVALID_INDEX is return is profile index does not exist + + \sa sl_WlanProfileAdd , sl_WlanProfileDel + \note belongs to \ref ext_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_WlanProfileGet) +_i16 sl_WlanProfileGet(const _i16 Index,_i8* pName, _i16 *pNameLen, _u8 *pMacAddr, SlWlanSecParams_t* pSecParams, SlWlanGetSecParamsExt_t* pSecExtParams, _u32 *pPriority); +#endif + +/*! + \brief Delete WLAN profile + + Delete WLAN profile + + \param[in] Index number of profile to delete. Possible values are 0 to 6.\n + Index value SL_WLAN_DEL_ALL_PROFILES will delete all saved profiles + + \return Zero on success or a negative error code on failure + \par Persistent + Profile deletion is Persistent + \sa sl_WlanProfileAdd , sl_WlanProfileGet + \note belongs to \ref ext_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_WlanProfileDel) +_i16 sl_WlanProfileDel(const _i16 Index); +#endif + +/*! + \brief Set policy values + + \param[in] Type Type of policy to be modified. The Options are: + - SL_WLAN_POLICY_CONNECTION + - SL_WLAN_POLICY_SCAN + - SL_WLAN_POLICY_PM + - SL_WLAN_POLICY_P2P + \param[in] Policy The option value which depends on action type + \param[in] pVal An optional value pointer + \param[in] ValLen An optional value length, in bytes + \return Zero on success or negative error code on failure. + \par Persistent + All parameters are System Persistent\n + Note that for SL_WLAN_POLICY_SCAN - Interval and Policy will be System persistent, but the hidden SSID option will not be persistent + + \sa sl_WlanPolicyGet + \note belongs to \ref ext_api + \warning + \par Example + + SL_WLAN_POLICY_CONNECTION:
defines options available to connect the CC31xx device to the AP: + The options below could be combined to a single action, if more than one action is required. + + - Auto Connect: If is set, the CC31xx device tries to automatically reconnect to one of its stored profiles, + each time the connection fails or the device is rebooted. To set this option, use: + \code + sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(1,0,0,0),NULL,0) + \endcode +
+ + + - Fast Connect: If is set, the CC31xx device tries to establish a fast connection to AP. + To set this option, use: + \code + sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,1,0,0),NULL,0) + \endcode +
+ + - P2P: If is set (relevant for P2P mode only), CC31xx/CC32xx device tries to automatically + connect to the first P2P device available, supporting push button only. To set this option, use: + \code + sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,0,1,0),NULL,0) + \endcode +
+ + - Auto Provisioning - If is set, the CC31xx device will automatically start the provisioning process + after a long period of disconnection when profiles exist to set this option, use: + \code + sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,0,0,1),NULL,0) + \endcode \n + + + SL_WLAN_POLICY_SCAN:
defines system scan time interval. \nDefault interval is 10 minutes. + After settings scan interval, an immediate scan is activated.\n The next scan will be based on the interval settings. + For AP scan, minimum interval is 10 seconds. + + - With hidden SSID: For example, setting scan interval to 1 minute interval use including hidden ssid: + \code + _u32 intervalInSeconds = 60; + sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_SCAN_POLICY(1,1), (_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); + \endcode +
+ + - No hidden SSID: setting scan interval to 1 minute interval use, not including hidden ssid: + \code + _u32 intervalInSeconds = 60; + sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_SCAN_POLICY(1,0), (_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); + \endcode +
+ + - Disable scan: + \code + #define SL_WLAN_DISABLE_SCAN 0 + _u32 intervalInSeconds = 0; + sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_DISABLE_SCAN,(_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); + \endcode +
+ + SL_WLAN_POLICY_PM:
defines a power management policy for Station mode only: + - Normal power management (default) policy use: + \code + sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_NORMAL_POLICY, NULL,0) + \endcode +
+ + - Low latency power management policy use: + \code + sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LOW_LATENCY_POLICY, NULL,0) + \endcode +
+ + - Low power management policy use: + \code + sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LOW_POWER_POLICY, NULL,0) + \endcode +
+ + - Always on power management policy use: + \code + sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_ALWAYS_ON_POLICY, NULL,0) + \endcode +
+ + - Long Sleep Interval policy use: + \code + SlWlanPmPolicyParams_t PmPolicyParams; + memset(&PmPolicyParams,0,sizeof(SlWlanPmPolicyParams_t)); + PmPolicyParams.MaxSleepTimeMs = 800; //max sleep time in mSec + sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LONG_SLEEP_INTERVAL_POLICY, (_u8*)&PmPolicyParams,sizeof(PmPolicyParams)); + \endcode +
+ + SL_WLAN_POLICY_P2P:
defines p2p negotiation policy parameters for P2P role: + - To set intent negotiation value, set on of the following:\n + SL_WLAN_P2P_ROLE_NEGOTIATE - intent 3 \n + SL_WLAN_P2P_ROLE_GROUP_OWNER - intent 15 \n + SL_WLAN_P2P_ROLE_CLIENT - intent 0 \n +
+ - To set negotiation initiator value (initiator policy of first negotiation action frame), set on of the following: \n + SL_WLAN_P2P_NEG_INITIATOR_ACTIVE \n + SL_WLAN_P2P_NEG_INITIATOR_PASSIVE \n + SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF \n + \code + sl_WlanPolicySet(SL_WLAN_POLICY_P2P, SL_WLAN_P2P_POLICY(SL_WLAN_P2P_ROLE_NEGOTIATE,SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF),NULL,0); + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_WlanPolicySet) +_i16 sl_WlanPolicySet(const _u8 Type , const _u8 Policy, _u8 *pVal,const _u8 ValLen); +#endif +/*! + \brief Get policy values + + \param[in] Type + - SL_WLAN_POLICY_CONNECTION + - SL_WLAN_POLICY_SCAN + - SL_WLAN_POLICY_PM, SL_WLAN_POLICY_P2P + \param[out] pPolicy argument may be set to any value + \param[out] pVal The returned values, depends on each policy type, will be stored in the allocated buffer pointed by pVal + with a maximum buffer length set by the calling function and pointed to by argument *pValLen + \param[out] pValLen actual value length + \return Zero on success, or negative error code on failure + + \sa sl_WlanPolicySet + + \note belongs to \ref ext_api + + \warning The value pointed by the argument *pValLen should be set to a value different from 0 and + greater than the buffer length returned from the SL device. Otherwise, an error will be returned. + + \par Example + + - SL_WLAN_POLICY_CONNECTION - Get connection policy: + \code + _u8 Policy = 0; + int length = sizeof(PolicyOption); + int ret; + ret = sl_WlanPolicyGet(SL_WLAN_POLICY_CONNECTION ,&Policy,0,(_u8*)&length); + + if (Policy & SL_WLAN_CONNECTION_POLICY(1, 1 , 0 , 0 )) + { + printf("Connection Policy is set to Auto + Fast"); + } + \endcode +
+ + - SL_WLAN_POLICY_SCAN - Get scan policy: + \code + int ScanInterval = 0; //default value is 600 seconds + _u8 Policy = 0; //default value is 0 (disabled) + int ret; + length = sizeof(ScanInterval); + ret = sl_WlanPolicyGet(SL_WLAN_POLICY_SCAN ,&Policy,(_u8*)&ScanInterval,(_u8*)&length); + + if (Policy & SL_WLAN_SCAN_POLICY(0 ,1)) + { + printf("Scan Policy is set to Scan visible ssid "); + } + if (Policy & SL_WLAN_SCAN_POLICY(1, 0)) + { + printf("Scan Policy is set to Scan hidden ssid "); + } + \endcode +
+ + - SL_WLAN_POLICY_PM - Get power management policy: + \code + _u8 Policy = 0; + int ret; + SlWlanPmPolicyParams_t PmPolicyParams; + length = sizeof(PmPolicyParams); + ret = sl_WlanPolicyGet(SL_POLICY_PM ,&Policy,&PmPolicyParams,(_u8*)&length); + if (Policy == SL_WLAN_LONG_SLEEP_INTERVAL_POLICY ) + { + printf("Connection Policy is set to LONG SLEEP INTERVAL POLICY with interval = %d ",PmPolicyParams.MaxSleepTimeMs); + } + \endcode +
+ + - SL_WLAN_POLICY_P2P - Get P2P policy: + \code + _u8 Policy = 0; + int ret; + length = sizeof(Policy); + ret = sl_WlanPolicyGet(SL_WLAN_POLICY_P2P ,&Policy,0,(_u8*)&length); + //SL_WLAN_P2P_POLICY(p2pNegType, p2pNegInitiator) + if (Policy & SL_WLAN_P2P_POLICY(0,SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF)) + { + printf("P2P Policy is set to Rand backoff"); + } + if (Policy & SL_WLAN_P2P_POLICY(SL_WLAN_P2P_ROLE_NEGOTIATE,0)) + { + printf("P2P Policy is set to Role Negotiate"); + } + \endcode +
+ +*/ +#if _SL_INCLUDE_FUNC(sl_WlanPolicyGet) +_i16 sl_WlanPolicyGet(const _u8 Type ,_u8 *pPolicy,_u8 *pVal,_u8 *pValLen); +#endif +/*! + \brief Gets the WLAN scan operation results + + Gets scan results , gets entry from scan result table + + \param[in] Index Starting index identifier (range 0-29) for getting scan results + \param[in] Count How many entries to fetch. Max is (30-"Index"). + \param[out] pEntries Pointer to an allocated SlWlanNetworkEntry_t. + The number of array items should match "Count" \n + sec_type: + - SL_WLAN_SCAN_SEC_TYPE_OPEN + - SL_WLAN_SCAN_SEC_TYPE_WEP + - SL_WLAN_SCAN_SEC_TYPE_WPA + - SL_WLAN_SCAN_SEC_TYPE_WPA2 + + \return Number of valid networks list items + \sa + \note belongs to \ref ext_api + \warning This command do not initiate any active scanning action + \par Example + + - Fetching max 10 results: + \code + SlWlanNetworkEntry_t netEntries[10]; + _u8 i; + _i16 resultsCount = sl_WlanGetNetworkList(0,10,&netEntries[0]); + for(i=0; i< resultsCount; i++) + { + printf("%d. ",i+1); + printf("SSID: %.32s ",netEntries[i].Ssid); + printf("BSSID: %x:%x:%x:%x:%x:%x ",netEntries[i].Bssid[0],netEntries[i].Bssid[1],netEntries[i].Bssid[2],netEntries[i].Bssid[3],netEntries[i].Bssid[4],netEntries[i].Bssid[5]); + printf("Channel: %d ",netEntries[i].Channel); + printf("RSSI: %d ",netEntries[i].Rssi); + printf("Security type: %d ",SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(netEntries[i].SecurityInfo)); + printf("Group Cipher: %d ",SL_WLAN_SCAN_RESULT_GROUP_CIPHER(netEntries[i].SecurityInfo)); + printf("Unicast Cipher bitmap: %d ",SL_WLAN_SCAN_RESULT_UNICAST_CIPHER_BITMAP(netEntries[i].SecurityInfo)); + printf("Key Mgmt suites bitmap: %d ",SL_WLAN_SCAN_RESULT_KEY_MGMT_SUITES_BITMAP(netEntries[i].SecurityInfo)); + printf("Hidden SSID: %d\r\n",SL_WLAN_SCAN_RESULT_HIDDEN_SSID(netEntries[i].SecurityInfo)); + } + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_WlanGetNetworkList) +_i16 sl_WlanGetNetworkList(const _u8 Index,const _u8 Count, SlWlanNetworkEntry_t *pEntries); +#endif + +/*! + \brief Start collecting wlan RX statistics, for unlimited time. + + \par Parameters + None + \return Zero on success, or negative error code on failure + + \sa sl_WlanRxStatStop sl_WlanRxStatGet + \note Belongs to \ref ext_api + \warning This API is deprecated and should be removed for next release + \par Example + + - Getting wlan RX statistics: + \code + void RxStatCollectTwice() + { + SlWlanGetRxStatResponse_t rxStat; + _i16 rawSocket; + _i8 DataFrame[200]; + struct SlTimeval_t timeval; + timeval.tv_sec = 0; // Seconds + timeval.tv_usec = 20000; // Microseconds. 10000 microseconds resolution + + sl_WlanRxStatStart(); // set statistics mode + + rawSocket = sl_Socket(SL_AF_RF, SL_SOCK_RAW, eChannel); + // set timeout - in case we have no activity for the specified channel + sl_SetSockOpt(rawSocket,SL_SOL_SOCKET,SL_SO_RCVTIMEO, &timeval, sizeof(timeval)); // Enable receive timeout + status = sl_Recv(rawSocket, DataFrame, sizeof(DataFrame), 0); + + Sleep(1000); // sleep for 1 sec + sl_WlanRxStatGet(&rxStat,0); // statistics has been cleared upon read + Sleep(1000); // sleep for 1 sec + sl_WlanRxStatGet(&rxStat,0); + } + \endcode +*/ +#if _SL_INCLUDE_FUNC(sl_WlanRxStatStart) +_i16 sl_WlanRxStatStart(void); +#endif + +/*! + \brief Stop collecting wlan RX statistic, (if previous called sl_WlanRxStatStart) + + \par Parameters + None + \return Zero on success, or negative error code on failure + + \sa sl_WlanRxStatStart sl_WlanRxStatGet + \note Belongs to \ref ext_api + \warning This API is deprecated and should be removed for next release +*/ +#if _SL_INCLUDE_FUNC(sl_WlanRxStatStop) +_i16 sl_WlanRxStatStop(void); +#endif + + +/*! + \brief Get wlan RX statistics. Upon calling this command, the statistics counters will be cleared. + + \param[in] pRxStat Pointer to SlWlanGetRxStatResponse_t filled with Rx statistics results + \param[in] Flags Should be 0 ( not applicable right now, will be added the future ) + \return Zero on success, or negative error code on failure + + \sa sl_WlanRxStatStart sl_WlanRxStatStop + \note Belongs to \ref ext_api + \warning +*/ +#if _SL_INCLUDE_FUNC(sl_WlanRxStatGet) +_i16 sl_WlanRxStatGet(SlWlanGetRxStatResponse_t *pRxStat,const _u32 Flags); +#endif + + +/*! + \brief The simpleLink will switch to the appropriate role according to the provisioning mode requested + and will start the provisioning process. + + \param[in] ProvisioningCmd + - SL_WLAN_PROVISIONING_CMD_START_MODE_AP 0: Start AP provisioning (AP role) + - SL_WLAN_PROVISIONING_CMD_START_MODE_SC 1: Start Smart Config provisioning (STA role) + - SL_WLAN_PROVISIONING_CMD_START_MODE_APSC 2: Start AP+Smart Config provisioning (AP role) + - SL_WLAN_PROVISIONING_CMD_START_MODE_APSC_EXTERNAL_CONFIGURATION 3: Start AP + Smart Config + WAC provisioning (AP role) + - SL_WLAN_PROVISIONING_CMD_STOP 4: Stop provisioning + - SL_WLAN_PROVISIONING_CMD_ABORT_EXTERNAL_CONFIGURATIONC 5: + \param[in] RequestedRoleAfterSuccess The role that the SimpleLink will switch to in case of a successful provisioning. + 0: STA + 2: AP + 0xFF: stay in current role (relevant only in provisioning_stop) + \param[in] InactivityTimeoutSec - The period of time (in seconds) the system waits before it automatically + stops the provisioning process when no activity is detected. + set to 0 in order to stop provisioning. Minimum InactivityTimeoutSec is 30 seconds. + \param[in] pSmartConfigKey Smart Config key: public key for smart config process (relevant for smart config only) + \param[in] Flags Can have the following values: + - SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION - Confirmation phase will be completed externally by host (e.g. via cloud assist) + + + \return Zero on success, or negative error code on failure + + \sa + \warning + \par Example + + - Start Provisioning - start as STA after success with inactivity timeout of 10 minutes: + \code + sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC, ROLE_STA, 600, "Key0Key0Key0Key0", 0x0); + \endcode +
+ + - Stop Provisioning: + \code + sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP,0xFF,0,NULL, 0x0); + \endcode +
+ + - Start AP Provisioning with inactivity timeout of 10 minutes + \code + sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC,ROLE_AP,600,NULL, 0x0); + \endcode +
+ + - Start AP Provisioning with inactivity timeout of 10 minutes and complete confirmation via user cloud assist + \code + sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC, ROLE_AP, 600, NULL, SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION); + \endcode +
+ +*/ + +#if _SL_INCLUDE_FUNC(sl_WlanProvisioning) +_i16 sl_WlanProvisioning(_u8 ProvisioningCmd, _u8 RequestedRoleAfterSuccess, _u16 InactivityTimeoutSec, char *pSmartConfigKey, _u32 Flags); +#endif + + + +/*! + \brief Wlan set mode + + Setting WLAN mode + + \param[in] Mode WLAN mode to start the CC31xx device. Possible options are + - ROLE_STA - for WLAN station mode + - ROLE_AP - for WLAN AP mode + - ROLE_P2P -for WLAN P2P mode + \return Zero on success, or negative error code on failure + \par Persistent + Mode is Persistent + \sa sl_Start sl_Stop + \note Belongs to \ref ext_api + \warning After setting the mode the system must be restarted for activating the new mode + \par Example + + - Switch from any role to STA: + \code + sl_WlanSetMode(ROLE_STA); + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + \endcode + +*/ +#if _SL_INCLUDE_FUNC(sl_WlanSetMode) +_i16 sl_WlanSetMode(const _u8 Mode); +#endif + + +/*! + \brief Setting WLAN configurations + + \param[in] ConfigId - configuration id + - SL_WLAN_CFG_AP_ID + - SL_WLAN_CFG_GENERAL_PARAM_ID + - SL_WLAN_CFG_P2P_PARAM_ID + - SL_WLAN_RX_FILTERS_ID + + \param[in] ConfigOpt - configurations option + - SL_WLAN_CFG_AP_ID + - SL_WLAN_AP_OPT_SSID \n + Set SSID for AP mode. \n + This options takes _u8 buffer as parameter + - SL_WLAN_AP_OPT_CHANNEL \n + Set channel for AP mode. \n + The channel is dependant on the country code which is set. i.e. for "US" the channel should be in the range of [1-11] \n + This option takes _u8 as a parameter + - SL_WLAN_AP_OPT_HIDDEN_SSID \n + Set Hidden SSID Mode for AP mode.Hidden options: \n + 0: disabled \n + 1: Send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID \n + 2: Clear SSID (ASCII 0), but keep the original length (this may be required with some \n + clients that do not support empty SSID) and ignore probe requests for broadcast SSID \n + This option takes _u8 as a parameter + - SL_WLAN_AP_OPT_SECURITY_TYPE \n + Set Security type for AP mode. Security options are: + - Open security: SL_WLAN_SEC_TYPE_OPEN + - WEP security: SL_WLAN_SEC_TYPE_WEP + - WPA security: SL_WLAN_SEC_TYPE_WPA_WPA2 \n + This option takes _u8 pointer as a parameter + - SL_WLAN_AP_OPT_PASSWORD \n + Set Password for for AP mode (for WEP or for WPA): \n + Password - for WPA: 8 - 63 characters \n + for WEP: 5 / 13 characters (ascii) \n + This options takes _u8 buffer as parameter + - SL_WLAN_AP_OPT_MAX_STATIONS \n + Set Max AP stations - 1..4 - Note: can be less than the number of currently connected stations \n + max_stations - 1 characters \n + This options takes _u8 buffer as parameter + - SL_WLAN_AP_OPT_MAX_STA_AGING \n + Set Max station ageing time - default is 60 seconds \n + max_stations - 2 characters \n + This options takes _u16 buffer as parameter + - SL_WLAN_AP_ACCESS_LIST_MODE \n + Set AP access list mode - DISABLE, DENY_LIST \n + mode - 1 characters \n + This options takes _u8 buffer as parameter + - SL_WLAN_AP_ACCESS_LIST_ADD_MAC \n + Add MAC address to the AP access list: \n + mac_addr - 6 characters \n + This options takes _u8 buffer as parameter + - SL_WLAN_AP_ACCESS_LIST_DEL_MAC \n + Del MAC address from the AP access list: \n + mac_addr - 6 characters \n + This options takes _u8 buffer as parameter + - SL_WLAN_AP_ACCESS_LIST_DEL_IDX \n + Delete MAC address from index in the AP access list: \n + index - 1 character \n + This options takes _u8 buffer as parameter + + - SL_WLAN_CFG_GENERAL_PARAM_ID + - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE \n + Set Country Code for AP mode \n + This options takes _u8 2 bytes buffer as parameter + - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER \n + Set STA mode Tx power level \n + Number between 0-15, as dB offset from max power (0 will set MAX power) \n + This options takes _u8 as parameter + - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER + Set AP mode Tx power level \n + Number between 0-15, as dB offset from max power (0 will set MAX power) \n + This options takes _u8 as parameter + - SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT + Set Info Element for AP mode. \n + The Application can set up to SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED info elements per Role (AP / P2P GO). \n + To delete an info element use the relevant index and length = 0. \n + For AP - no more than SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_AP bytes can be stored for all info elements. \n + For P2P GO - no more than SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_P2P_GO bytes can be stored for all info elements. \n + This option takes SlWlanSetInfoElement_t as parameter + - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS + Set scan parameters: RSSI threshold and channel mask. + - SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES + Set suspended profiles mask (set bits 2 and 4 to suspend profiles 2 and 4). + + - SL_WLAN_CFG_P2P_PARAM_ID + - SL_WLAN_P2P_OPT_DEV_TYPE \n + Set P2P Device type.Maximum length of 17 characters. Device type is published under P2P I.E, \n + allows to make devices easier to recognize. \n + In case no device type is set, the default type is "1-0050F204-1" \n + This options takes _u8 buffer as parameter + - SL_WLAN_P2P_OPT_CHANNEL_N_REGS \n + Set P2P Channels. \n + listen channel (either 1/6/11 for 2.4GHz) \n + listen regulatory class (81 for 2.4GHz) \n + oper channel (either 1/6/11 for 2.4GHz) \n + oper regulatory class (81 for 2.4GHz) \n + listen channel and regulatory class will determine the device listen channel during p2p find listen phase \n + oper channel and regulatory class will determine the operating channel preferred by this device (in case it is group owner this will be the operating channel) \n + channels should be one of the social channels (1/6/11). In case no listen/oper channel selected, a random 1/6/11 will be selected. + This option takes pointer to _u8[4] as parameter + + - SL_WLAN_RX_FILTERS_ID + - SL_WLAN_RX_FILTER_STATE \n + Enable or disable filters. The buffer input is SlWlanRxFilterOperationCommandBuff_t\n + - SL_WLAN_RX_FILTER_SYS_STATE \n + Enable or disable system filters. The buffer input is SlWlanRxFilterSysFiltersSetStateBuff_t\n + - SL_WLAN_RX_FILTER_REMOVE \n + Remove filters. The buffer input is SlWlanRxFilterOperationCommandBuff_t\n + - SL_WLAN_RX_FILTER_STORE \n + Save the filters as persistent. \n + - SL_WLAN_RX_FILTER_UPDATE_ARGS \n + Update filter arguments. The buffer input is SlWlanRxFilterUpdateArgsCommandBuff_t\n + + \param[in] ConfigLen - configurations len + + \param[in] pValues - configurations values + + \return Zero on success, or negative error code on failure + + \par Persistent + System Persistent: + - SL_WLAN_CFG_GENERAL_PARAM_ID + - SL_WLAN_CFG_P2P_PARAM_ID + + Reset: + - SL_WLAN_CFG_AP_ID + + Non- Persistent: + - SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH + \sa + \note + \warning + \par Examples + + - SL_WLAN_AP_OPT_SSID: + \code + _u8 str[33]; + memset(str, 0, 33); + memcpy(str, ssid, len); // ssid string of 32 characters + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_SSID, strlen(ssid), str); + \endcode +
+ + - SL_WLAN_AP_OPT_CHANNEL: + \code + _u8 val = channel; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_CHANNEL, 1, (_u8 *)&val); + \endcode +
+ + - SL_WLAN_AP_OPT_HIDDEN_SSID: + \code + _u8 val = hidden; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_HIDDEN_SSID, 1, (_u8 *)&val); + \endcode +
+ + - SL_WLAN_AP_OPT_SECURITY_TYPE: + \code + _u8 val = SL_WLAN_SEC_TYPE_WPA_WPA2; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_SECURITY_TYPE, 1, (_u8 *)&val); + \endcode +
+ + - SL_WLAN_AP_OPT_PASSWORD: + \code + _u8 str[65]; + _u16 len = strlen(password); + memset(str, 0, 65); + memcpy(str, password, len); + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_PASSWORD, len, (_u8 *)str); + \endcode +
+ + - SL_WLAN_AP_OPT_MAX_STATIONS: + \code + _u8 max_ap_stations = 3; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_MAX_STATIONS, sizeof(max_ap_stations), (_u8 *)&max_ap_stations); + \endcode +
+ + - SL_WLAN_AP_OPT_MAX_STA_AGING: + \code + _u16 max_ap_sta_aging = 60; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_MAX_STA_AGING, sizeof(max_ap_sta_aging), (_u8 *)&max_ap_sta_aging); + \endcode +
+ + - SL_WLAN_AP_ACCESS_LIST_MODE: + \code + _u8 access list_mode = SL_WLAN_AP_ACCESS_LIST_MODE_DENY_LIST; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_MODE, sizeof(access list_mode), (_u8 *)&access list_mode); + \endcode +
+ + - SL_WLAN_AP_ACCESS_LIST_ADD_MAC: + \code + _u8 sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_ADD_MAC, sizeof(sta_mac), (_u8 *)&sta_mac); + \endcode +
+ + - SL_WLAN_AP_ACCESS_LIST_DEL_MAC: + \code + _u8 sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_DEL_MAC, sizeof(sta_mac), (_u8 *)&sta_mac); + \endcode +
+ + - SL_WLAN_AP_ACCESS_LIST_DEL_IDX: + \code + _u8 sta_index = 0; + sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_DEL_IDX, sizeof(sta_index), (_u8 *)&sta_index); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER: + \code + _u8 stapower=(_u8)power; + sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER,1,(_u8 *)&stapower); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE: + \code + _u8* str = (_u8 *) country; // string of 2 characters. i.e. - "US" + sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE, 2, str); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER: + \code + _u8 appower=(_u8)power; + sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER,1,(_u8 *)&appower); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES + \code + _u32 suspendedProfilesMask=(_u32)mask; + sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES,sizeof(suspendedProfilesMask),(_u32 *)&suspendedProfilesMask); + \endcode +
+ + - SL_WLAN_P2P_OPT_DEV_TYPE: + \code + _u8 str[17]; + _u16 len = strlen(device_type); + memset(str, 0, 17); + memcpy(str, device_type, len); + sl_WlanSet(SL_WLAN_CFG_P2P_PARAM_ID, SL_WLAN_P2P_OPT_DEV_TYPE, len, str); + \endcode +
+ + - SL_WLAN_P2P_OPT_CHANNEL_N_REGS + \code + _u8 str[4]; + str[0] = (_u8)11; // listen channel + str[1] = (_u8)81; // listen regulatory class + str[2] = (_u8)6; // oper channel + str[3] = (_u8)81; // oper regulatory class + sl_WlanSet(SL_WLAN_CFG_P2P_PARAM_ID, SL_WLAN_P2P_OPT_CHANNEL_N_REGS, 4, str); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT: + \code + SlWlanSetInfoElement_t infoele; + infoele.Index = Index; // Index of the info element. range: 0 - SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED + infoele.Role = Role; // SL_WLAN_INFO_ELEMENT_AP_ROLE (0) or SL_WLAN_INFO_ELEMENT_P2P_GO_ROLE (1) + infoele.IE.Id = Id; // Info element ID. if SL_WLAN_INFO_ELEMENT_DEFAULT_ID (0) is set, ID will be set to 221. + // Organization unique ID. If all 3 bytes are zero - it will be replaced with 08,00,28. + infoele.IE.Oui[0] = Oui0; // Organization unique ID first Byte + infoele.IE.Oui[1] = Oui1; // Organization unique ID second Byte + infoele.IE.Oui[2] = Oui2; // Organization unique ID third Byte + infoele.IE.Length = Len; // Length of the info element. must be smaller than 253 bytes + memset(infoele.IE.Data, 0, SL_WLAN_INFO_ELEMENT_MAX_SIZE); + if ( Len <= SL_WLAN_INFO_ELEMENT_MAX_SIZE ) + { + memcpy(infoele.IE.Data, IE, Len); // Info element. length of the info element is [0-252] + sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT,sizeof(SlWlanSetInfoElement_t),(_u8* ) &infoele); + } + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS: + \code + SlWlanScanParamCommand_t ScanParamConfig; + _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS; + _u16 OptionLen = sizeof(ScanParamConfig); + // 2.4G channels bits order: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 + + ScanParamConfig.RssiThreshold = -70; + ScanParamConfig.ChannelsMask = 0x1FFF; + sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, &Option, &OptionLen, (_u8 *)&ScanParamConfig); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH: + \code + _u8 param = 1; // 1 means disable the server authentication + sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH,1,¶m); + \endcode +
+ - SL_WLAN_RX_FILTER_STORE: + \code + sl_WlanSet(SL_WLAN_RX_FILTERS_ID, SL_WLAN_RX_FILTER_STORE, 0, NULL); + \endcode + +*/ +#if _SL_INCLUDE_FUNC(sl_WlanSet) +_i16 sl_WlanSet(const _u16 ConfigId ,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues); +#endif + +/*! + \brief Getting WLAN configurations + + \param[in] ConfigId - configuration id + - SL_WLAN_CFG_AP_ID + - SL_WLAN_CFG_GENERAL_PARAM_ID + - SL_WLAN_CFG_P2P_PARAM_ID + - SL_WLAN_CFG_AP_ACCESS_LIST_ID + - SL_WLAN_RX_FILTERS_ID + + \param[out] pConfigOpt - get configurations option + - SL_WLAN_CFG_AP_ID + - SL_WLAN_AP_OPT_SSID \n + Get SSID for AP mode. \n + Get up to 32 characters of SSID \n + This options takes _u8 as parameter + - SL_WLAN_AP_OPT_CHANNEL \n + Get channel for AP mode. \n + This option takes _u8 as a parameter + - SL_WLAN_AP_OPT_HIDDEN_SSID \n + Get Hidden SSID Mode for AP mode.Hidden options: \n + 0: disabled \n + 1: Send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID \n + 2: Clear SSID (ASCII 0), but keep the original length (this may be required with some \n + clients that do not support empty SSID) and ignore probe requests for broadcast SSID \n + This option takes _u8 as a parameter + - SL_WLAN_AP_OPT_SECURITY_TYPE \n + Get Security type for AP mode. Security options are: + - Open security: SL_WLAN_SEC_TYPE_OPEN + - WEP security: SL_WLAN_SEC_TYPE_WEP + - WPA security: SL_WLAN_SEC_TYPE_WPA_WPA2 \n + This option takes _u8 as a parameter + - SL_WLAN_AP_OPT_PASSWORD \n + Get Password for for AP mode (for WEP or for WPA): \n + Returns password - string, fills up to 64 characters. \n + This options takes _u8 buffer as parameter + - SL_WLAN_AP_OPT_MAX_STATIONS \n + Get Max AP allowed stations: \n + This options takes _u8 buffer as parameter + - SL_WLAN_AP_OPT_MAX_STA_AGING \n + Get AP aging time in seconds: \n + This options takes _u16 buffer as parameter + - SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES \n + Get AP access list number of entries: \n + This options takes _u8 buffer as parameter + - SL_WLAN_CFG_AP_ACCESS_LIST_ID + - The option is the start index in the access list \n + Get the AP access list from start index, the number of entries in the list is extracted from the request length. + - SL_WLAN_CFG_GENERAL_PARAM_ID + - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS \n + Get scan parameters. + This option uses SlWlanScanParamCommand_t as parameter + - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE \n + Get Country Code for AP mode \n + This options takes _u8 buffer as parameter + - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER \n + Get STA mode Tx power level \n + Number between 0-15, as dB offset from max power (0 indicates MAX power) \n + This options takes _u8 as parameter + - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER + Get AP mode Tx power level \n + Number between 0-15, as dB offset from max power (0 indicates MAX power) \n + This options takes _u8 as parameter + - SL_WLAN_CFG_P2P_PARAM_ID + - SL_WLAN_P2P_OPT_CHANNEL_N_REGS \n + Get P2P Channels. \n + listen channel (either 1/6/11 for 2.4GHz) \n + listen regulatory class (81 for 2.4GHz) \n + oper channel (either 1/6/11 for 2.4GHz) \n + oper regulatory class (81 for 2.4GHz) \n + listen channel and regulatory class will determine the device listen channel during p2p find listen phase \n + oper channel and regulatory class will determine the operating channel preferred by this device (in case it is group owner this will be the operating channel) \n + channels should be one of the social channels (1/6/11). In case no listen/oper channel selected, a random 1/6/11 will be selected. \n + This option takes pointer to _u8[4] as parameter + - SL_WLAN_RX_FILTERS_ID + - SL_WLAN_RX_FILTER_STATE \n + Retrieves the filters enable/disable status. The buffer input is SlWlanRxFilterRetrieveStateBuff_t \n + - SL_WLAN_RX_FILTER_SYS_STATE \n + Retrieves the system filters enable/disable status. The buffer input is SlWlanRxFilterSysFiltersRetrieveStateBuff_t: + + \param[out] pConfigLen - The length of the allocated memory as input, when the + function complete, the value of this parameter would be + the len that actually read from the device. + If the device return length that is longer from the input + value, the function will cut the end of the returned structure + and will return SL_ESMALLBUF. + + + \param[out] pValues - get configurations values + \return Zero on success, or negative error code on failure + \sa sl_WlanSet + \note + In case the device was started as AP mode, but no SSID was set, the Get SSID will return "mysimplelink" and not "mysimplelink-xxyyzz" + \warning + \par Examples + + - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS: + \code + SlWlanScanParamCommand_t ScanParamConfig; + _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS; + _u16 OptionLen = sizeof(SlWlanScanParamCommand_t); + sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&ScanParamConfig); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER: + \code + _i32 TXPower = 0; + _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER; + _u16 OptionLen = sizeof(TXPower); + sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&TXPower); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPTSTA_TX_POWER: + \code + _i32 TXPower = 0; + _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER; + _u16 OptionLen = sizeof(TXPower); + sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&TXPower); + \endcode +
+ + - SL_WLAN_P2P_OPT_DEV_TYPE: + \code + _i8 device_type[18]; + _u16 len = 18; + _u16 config_opt = SL_WLAN_P2P_OPT_DEV_TYPE; + sl_WlanGet(SL_WLAN_CFG_P2P_PARAM_ID, &config_opt , &len, (_u8* )device_type); + \endcode +
+ + - SL_WLAN_AP_OPT_SSID: + \code + _i8 ssid[33]; + _u16 len = 33; + sl_Memset(ssid,0,33); + _u16 config_opt = SL_WLAN_AP_OPT_SSID; + sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt , &len, (_u8* )ssid); + \endcode +
+ + - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE: + \code + _i8 country[3]; + _u16 len = 3; + _u16 config_opt = SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE; + sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID, &config_opt, &len, (_u8* )country); + \endcode +
+ + - SL_WLAN_AP_OPT_CHANNEL: + \code + _i8 channel; + _u16 len = 1; + _u16 config_opt = SL_WLAN_AP_OPT_CHANNEL; + sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&channel); + \endcode +
+ + - SL_WLAN_AP_OPT_HIDDEN_SSID: + \code + _u8 hidden; + _u16 len = 1; + _u16 config_opt = SL_WLAN_AP_OPT_HIDDEN_SSID; + sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&hidden); + \endcode +
+ + - SL_WLAN_AP_OPT_SECURITY_TYPE: + \code + _u8 sec_type; + _u16 len = 1; + _u16 config_opt = SL_WLAN_AP_OPT_SECURITY_TYPE; + sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&sec_type); + \endcode +
+ + - SL_WLAN_AP_OPT_PASSWORD: + \code + _u8 password[64]; + _u16 len = 64; + sl_Memset(password,0,64); + _u16 config_opt = SL_WLAN_AP_OPT_PASSWORD; + sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )password); + \endcode +
+ + - SL_WLAN_AP_OPT_MAX_STATIONS: + \code + _u8 max_ap_stations + _u16 len = 1; + _u16 config_opt = SL_WLAN_AP_OPT_MAX_STATIONS; + sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&max_ap_stations); + \endcode +
+ + - SL_WLAN_AP_OPT_MAX_STA_AGING: + \code + _u16 ap_sta_aging; + _u16 len = 2; + _u16 config_opt = SL_WLAN_AP_OPT_MAX_STA_AGING; + sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&ap_sta_aging); + \endcode +
+ + - SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES: + \code + _u8 aclist_num_entries; + _u16 config_opt = SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES; + _u16 len = sizeof(aclist_num_entries); + sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&aclist_num_entries); + \endcode +
+ + - SL_WLAN_CFG_AP_ACCESS_LIST_ID: + \code + _u8 aclist_mac[SL_WLAN_MAX_ACCESS_LIST_STATIONS][MAC_LEN]; + unsigned char aclist_num_entries; + unsigned short config_opt; + unsigned short len; + int actual_aclist_num_entries; + unsigned short start_aclist_index; + unsigned short aclist_info_len; + int i; + + start_aclist_index = 0; + aclist_info_len = 2*MAC_LEN; + sl_WlanGet(SL_WLAN_CFG_AP_ACCESS_LIST_ID, &start_aclist_index, &aclist_info_len, (_u8 *)&aclist_mac[start_aclist_index]); + + actual_aclist_num_entries = aclist_info_len / MAC_LEN; + printf("-Print AP Deny list, num stations = %d\n", actual_aclist_num_entries); + for (i=0; i + + - SL_WLAN_P2P_OPT_CHANNEL_N_REGS: + \code + _u16 listen_channel,listen_reg,oper_channel,oper_reg; + _u16 len = 4; + _u16 config_opt = SL_WLAN_P2P_OPT_CHANNEL_N_REGS; + _u8 channel_n_regs[4]; + sl_WlanGet(SL_WLAN_CFG_P2P_PARAM_ID, &config_opt, &len, (_u8* )channel_n_regs); + listen_channel = channel_n_regs[0]; + listen_reg = channel_n_regs[1]; + oper_channel = channel_n_regs[2]; + oper_reg = channel_n_regs[3]; + \endcode +
+ + - SL_WLAN_RX_FILTER_STATE: + \code + int ret = 0; + SlWlanRxFilterIdMask_t FilterIdMask; + _u16 len = sizeof(SlWlanRxFilterIdMask_t);; + _u16 config_opt = SL_WLAN_RX_FILTER_STATE; + memset(FilterIdMask,0,sizeof(FilterIdMask)); + ret = sl_WlanGet(SL_WLAN_RX_FILTERS_ID, &config_opt , &len, (_u8* )FilterIdMask); + \endcode +
+ + - SL_WLAN_RX_FILTER_SYS_STATE: + \code + int ret = 0; + SlWlanRxFilterSysFiltersMask_t FilterSysIdMask; + _u16 len = sizeof(SlWlanRxFilterSysFiltersMask_t);; + _u16 config_opt = SL_WLAN_RX_FILTER_SYS_STATE; + memset(FilterSysIdMask,0,sizeof(FilterSysIdMask)); + ret = sl_WlanGet(SL_WLAN_RX_FILTERS_ID, &config_opt , &len, (_u8* )FilterSysIdMask); + \endcode +
+ + - SL_WLAN_CONNECTION_INFO: + \code + _i16 RetVal = 0 ; + _u16 Len = sizeof(SlWlanConnStatusParam_t) ; + SlWlanConnStatusParam_t WlanConnectInfo ; + RetVal = sl_WlanGet(SL_WLAN_CONNECTION_INFO, NULL , &Len, (_u8*)&WlanConnectInfo); + \endcode +
+ +*/ + +#if _SL_INCLUDE_FUNC(sl_WlanGet) +_i16 sl_WlanGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues); +#endif + +/*! + \brief Adds new filter rule to the system + + \param[in] RuleType The rule type + - SL_WLAN_RX_FILTER_HEADER + - SL_WLAN_RX_FILTER_COMBINATION + + \param[in] Flags Flags which set the type of header rule Args and sets the persistent flag + - SL_WLAN_RX_FILTER_BINARY + - SL_WLAN_RX_FILTER_PERSISTENT + - SL_WLAN_RX_FILTER_ENABLE + + \param[in] pRule Determine the filter rule logic + \param[in] pTrigger Determine when the rule is triggered also sets rule parent. + \param[in] pAction Sets the action to be executed in case the match functions pass + \param[out] pFilterId The filterId which was created + + \par Persistent Save the filters for persistent can be done by calling with SL_WLAN_RX_FILTER_STORE + + \return Zero on success, or negative error code on failure + \sa + \note + \warning + */ +#if _SL_INCLUDE_FUNC(sl_WlanRxFilterAdd) +_i16 sl_WlanRxFilterAdd( SlWlanRxFilterRuleType_t RuleType, + SlWlanRxFilterFlags_u Flags, + const SlWlanRxFilterRule_u* const pRule, + const SlWlanRxFilterTrigger_t* const pTrigger, + const SlWlanRxFilterAction_t* const pAction, + SlWlanRxFilterID_t* pFilterId); + +#endif + +/*! + + Close the Doxygen group. + @} + + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __WLAN_H__ */ + diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.c new file mode 100755 index 00000000000..25b4dc9db0b --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.c @@ -0,0 +1,1420 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC32XX.c ======== + */ + +#include + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif +#include +#include + +#include + +#include +#include + +#if defined(__IAR_SYSTEMS_ICC__) +#include +#endif + +/* driverlib header files */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#define STATUS_BUSY 0x01 + +#define PowerCC32XX_SSPIReadStatusInstruction (0x05) +#define PowerCC32XX_SSPIPowerDownInstruction (0xB9) +#define PowerCC32XX_SSPISemaphoreTakeTries (4000000) +#define PowerCC32XX_SSPICSDelay 33 +#define uSEC_DELAY(x) (ROM_UtilsDelayDirect(x*80/3)) + +#define SYNCBARRIER() { \ + __asm(" dsb \n" \ + " isb \n"); \ +} + +/* Externs */ +extern const PowerCC32XX_ConfigV1 PowerCC32XX_config; + +/* Module_State */ +PowerCC32XX_ModuleState PowerCC32XX_module = { + { NULL, NULL}, /* list */ + 0, /* constraintsMask */ + Power_ACTIVE, /* state */ + /* dbRecords */ + { + PRCM_CAMERA, /* PERIPH_CAMERA */ + PRCM_I2S, /* PERIPH_MCASP */ + PRCM_SDHOST, /* PERIPH_MMCHS */ + PRCM_GSPI, /* PERIPH_MCSPI_A1 */ + PRCM_LSPI, /* PERIPH_MCSPI_A2 */ + PRCM_UDMA, /* PERIPH_UDMA_A */ + PRCM_GPIOA0, /* PERIPH_GPIO_A */ + PRCM_GPIOA1, /* PERIPH_GPIO_B */ + PRCM_GPIOA2, /* PERIPH_GPIO_C */ + PRCM_GPIOA3, /* PERIPH_GPIO_D */ + PRCM_GPIOA4, /* PERIPH_GPIO_E */ + PRCM_WDT, /* PERIPH_WDOG_A */ + PRCM_UARTA0, /* PERIPH_UART_A0 */ + PRCM_UARTA1, /* PERIPH_UART_A1 */ + PRCM_TIMERA0, /* PERIPH_GPT_A0 */ + PRCM_TIMERA1, /* PERIPH_GPT_A1 */ + PRCM_TIMERA2, /* PERIPH_GPT_A2 */ + PRCM_TIMERA3, /* PERIPH_GPT_A3 */ + PRCM_DTHE, /* PERIPH_CRYPTO */ + PRCM_SSPI, /* PERIPH_MCSPI_S0 */ + PRCM_I2CA0 /* PERIPH_I2C */ + }, + /* enablePolicy */ + FALSE, + /* initialized */ + FALSE, + /* refCount */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + /* constraintCounts */ + { 0, 0 }, + /* policyFxn */ + NULL +}; + +/* context save variable */ +PowerCC32XX_SaveRegisters PowerCC32XX_contextSave; + +typedef void (*LPDSFunc)(void); + +/* enter LPDS is an assembly function */ +// TODO: Uncomment this once the PowerCC32XX_enterLPDS has been implemented in assembly for all toolchains +//extern void PowerCC32XX_enterLPDS(LPDSFunc driverlibFunc); + +/* pin parking functions */ +void PowerCC32XX_parkPin(PowerCC32XX_Pin pin, PowerCC32XX_ParkState parkState, + uint32_t * previousState, uint16_t * previousDirection); +void PowerCC32XX_restoreParkedPin(PowerCC32XX_Pin pin, uint32_t type, + uint16_t direction); +void PowerCC32XX_shutdownSSPI(void); + +/* internal functions */ +static int_fast16_t notify(uint_fast16_t eventType); +static void restoreNVICRegs(void); +static void restorePeriphClocks(void); +static void saveNVICRegs(void); +static void parkPins(void); +static void restoreParkedPins(void); + +/* + * ======== Power_disablePolicy ======== + * Do not run the configured policy + */ +bool Power_disablePolicy(void) +{ + bool enablePolicy = PowerCC32XX_module.enablePolicy; + PowerCC32XX_module.enablePolicy = FALSE; + + DebugP_log0("Power: disable policy"); + + return (enablePolicy); +} + +/* + * ======== Power_enablePolicy ======== + * Run the configured policy + */ +void Power_enablePolicy(void) +{ + PowerCC32XX_module.enablePolicy = TRUE; + + DebugP_log0("Power: enable policy"); +} + +/* + * ======== Power_getConstraintMask ======== + * Get a bitmask indicating the constraints that have been registered with + * Power. + */ +uint_fast32_t Power_getConstraintMask(void) +{ + return (PowerCC32XX_module.constraintMask); +} + +/* + * ======== Power_getDependencyCount ======== + * Get the count of dependencies that are currently declared upon a resource. + */ +int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId) +{ + int_fast16_t status; + + if (resourceId >= PowerCC32XX_NUMRESOURCES) { + status = Power_EINVALIDINPUT; + } + else { + status = PowerCC32XX_module.refCount[resourceId]; + } + + return (status); +} + +/* + * ======== Power_getTransitionLatency ======== + * Get the transition latency for a sleep state. The latency is reported + * in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, + uint_fast16_t type) +{ + uint32_t latency = 0; + + if (type == Power_RESUME) { + latency = PowerCC32XX_RESUMETIMELPDS; + } + else { + latency = PowerCC32XX_TOTALTIMELPDS; + } + + return (latency); +} + +/* + * ======== Power_getTransitionState ======== + * Get the current sleep transition state. + */ +uint_fast16_t Power_getTransitionState(void) +{ + return (PowerCC32XX_module.state); +} + +/* + * ======== Power_idleFunc ======== + * Function needs to be plugged into the idle loop. + * It calls the configured policy function if the + * 'enablePolicy' flag is set. + */ +void Power_idleFunc() +{ + if (PowerCC32XX_module.enablePolicy) { + if (PowerCC32XX_module.policyFxn != NULL) { + DebugP_log1("Power: calling policy function (%p)", + (uintptr_t) PowerCC32XX_module.policyFxn); + (*(PowerCC32XX_module.policyFxn))(); + } + } +} + +/* + * ======== Power_init ======== + */ +int_fast16_t Power_init() +{ + /* if this function has already been called, just return */ + if (PowerCC32XX_module.initialized) { + return (Power_SOK); + } + + /* set module state field 'initialized' to true */ + PowerCC32XX_module.initialized = TRUE; + + /* set the module state enablePolicy field */ + PowerCC32XX_module.enablePolicy = PowerCC32XX_config.enablePolicy; + + /* call the config policy init function if its not null */ + if (PowerCC32XX_config.policyInitFxn != NULL) { + (*(PowerCC32XX_config.policyInitFxn))(); + } + + /* copy wakeup settings to module state */ + PowerCC32XX_module.wakeupConfig.enableGPIOWakeupLPDS = + PowerCC32XX_config.enableGPIOWakeupLPDS; + PowerCC32XX_module.wakeupConfig.enableGPIOWakeupShutdown = + PowerCC32XX_config.enableGPIOWakeupShutdown; + PowerCC32XX_module.wakeupConfig.enableNetworkWakeupLPDS = + PowerCC32XX_config.enableNetworkWakeupLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceLPDS = + PowerCC32XX_config.wakeupGPIOSourceLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeLPDS = + PowerCC32XX_config.wakeupGPIOTypeLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS = + PowerCC32XX_config.wakeupGPIOFxnLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg = + PowerCC32XX_config.wakeupGPIOFxnLPDSArg; + PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceShutdown = + PowerCC32XX_config.wakeupGPIOSourceShutdown; + PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeShutdown = + PowerCC32XX_config.wakeupGPIOTypeShutdown; + + /* now configure these wakeup settings in the device... */ + PowerCC32XX_configureWakeup(&PowerCC32XX_module.wakeupConfig); + + /* copy the Power policy function to module state */ + PowerCC32XX_module.policyFxn = PowerCC32XX_config.policyFxn; + + /* spin if too many pins were specified in the pin park array */ + if (PowerCC32XX_config.numPins > PowerCC32XX_NUMPINS) { + while(1){} + } + + return (Power_SOK); +} + +/* + * ======== Power_registerNotify ======== + * Register a function to be called on a specific power event. + */ +int_fast16_t Power_registerNotify(Power_NotifyObj * pNotifyObj, + uint_fast16_t eventTypes, Power_NotifyFxn notifyFxn, uintptr_t clientArg) +{ + int_fast16_t status = Power_SOK; + + /* check for NULL pointers */ + if ((pNotifyObj == NULL) || (notifyFxn == NULL)) { + status = Power_EINVALIDPOINTER; + } + + else { + /* fill in notify object elements */ + pNotifyObj->eventTypes = eventTypes; + pNotifyObj->notifyFxn = notifyFxn; + pNotifyObj->clientArg = clientArg; + + /* place notify object on event notification queue */ + List_put(&PowerCC32XX_module.notifyList, (List_Elem*)pNotifyObj); + } + + DebugP_log3( + "Power: register notify (%p), eventTypes (0x%x), notifyFxn (%p)", + (uintptr_t) pNotifyObj, eventTypes, (uintptr_t) notifyFxn); + + return (status); +} + +/* + * ======== Power_releaseConstraint ======== + * Release a previously declared constraint. + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) +{ + int_fast16_t status = Power_SOK; + uintptr_t key; + uint8_t count; + + /* first ensure constraintId is valid */ + if (constraintId >= PowerCC32XX_NUMCONSTRAINTS) { + status = Power_EINVALIDINPUT; + } + + /* if constraintId is OK ... */ + else { + + /* disable interrupts */ + key = HwiP_disable(); + + /* get the count of the constraint */ + count = PowerCC32XX_module.constraintCounts[constraintId]; + + /* ensure constraint count is not already zero */ + if (count == 0) { + status = Power_EFAIL; + } + + /* if not already zero ... */ + else { + /* decrement the count */ + count--; + + /* save the updated count */ + PowerCC32XX_module.constraintCounts[constraintId] = count; + + /* if constraint count reaches zero, remove constraint from mask */ + if (count == 0) { + PowerCC32XX_module.constraintMask &= ~(1 << constraintId); + } + } + + /* restore interrupts */ + HwiP_restore(key); + + DebugP_log1("Power: release constraint (%d)", constraintId); + } + + return (status); +} + +/* + * ======== Power_releaseDependency ======== + * Release a previously declared dependency. + */ +int_fast16_t Power_releaseDependency(uint_fast16_t resourceId) +{ + int_fast16_t status = Power_SOK; + uint8_t count; + uint32_t id; + uintptr_t key; + + /* first check that resourceId is valid */ + if (resourceId >= PowerCC32XX_NUMRESOURCES) { + status = Power_EINVALIDINPUT; + } + + /* if resourceId is OK ... */ + else { + + /* disable interrupts */ + key = HwiP_disable(); + + /* read the reference count */ + count = PowerCC32XX_module.refCount[resourceId]; + + /* ensure dependency count is not already zero */ + if (count == 0) { + status = Power_EFAIL; + } + + /* if not already zero ... */ + else { + + /* decrement the reference count */ + count--; + + /* if this was the last dependency being released.., */ + if (count == 0) { + /* deactivate this resource ... */ + id = PowerCC32XX_module.dbRecords[resourceId]; + + /* disable clk to peripheral */ + MAP_PRCMPeripheralClkDisable(id, + PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); + } + + /* save the updated count */ + PowerCC32XX_module.refCount[resourceId] = count; + } + + /* restore interrupts */ + HwiP_restore(key); + + DebugP_log1("Power: release dependency (%d)", resourceId); + } + + return (status); +} + +/* + * ======== Power_setConstraint ======== + * Declare an operational constraint. + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId) +{ + int_fast16_t status = Power_SOK; + uintptr_t key; + + /* ensure that constraintId is valid */ + if (constraintId >= PowerCC32XX_NUMCONSTRAINTS) { + status = Power_EINVALIDINPUT; + } + + else { + + /* disable interrupts */ + key = HwiP_disable(); + + /* set the specified constraint in the constraintMask */ + PowerCC32XX_module.constraintMask |= 1 << constraintId; + + /* increment the specified constraint count */ + PowerCC32XX_module.constraintCounts[constraintId]++; + + /* restore interrupts */ + HwiP_restore(key); + + DebugP_log1("Power: set constraint (%d)", constraintId); + } + + return (status); +} + +/* + * ======== Power_setDependency ======== + * Declare a dependency upon a resource. + */ +int_fast16_t Power_setDependency(uint_fast16_t resourceId) +{ + int_fast16_t status = Power_SOK; + uint8_t count; + uint32_t id; + uintptr_t key; + + /* ensure resourceId is valid */ + if (resourceId >= PowerCC32XX_NUMRESOURCES) { + status = Power_EINVALIDINPUT; + } + + /* resourceId is OK ... */ + else { + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and increment reference count */ + count = PowerCC32XX_module.refCount[resourceId]++; + + /* if resource was NOT activated previously ... */ + if (count == 0) { + /* now activate this resource ... */ + id = PowerCC32XX_module.dbRecords[resourceId]; + + /* enable the peripheral clock to the resource */ + MAP_PRCMPeripheralClkEnable(id, + PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); + + /* spin here until status returns TRUE */ + while(!MAP_PRCMPeripheralStatusGet(id)) { + } + } + + /* restore interrupts */ + HwiP_restore(key); + DebugP_log1("Power: set dependency (%d)", resourceId); + } + + return (status); +} + +/* + * ======== Power_setPolicy ======== + * Set the Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy) +{ + PowerCC32XX_module.policyFxn = policy; +} + +/* + * ======== Power_shutdown ======== + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, + uint_fast32_t shutdownTime) +{ + int_fast16_t status = Power_EFAIL; + uint32_t constraints; + uintptr_t hwiKey; + uint64_t counts; + + /* disable interrupts */ + hwiKey = HwiP_disable(); + + /* make sure shutdown request doesn't violate a constraint */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC32XX_DISALLOW_SHUTDOWN)) { + status = Power_ECHANGE_NOT_ALLOWED; + } + else { + if (PowerCC32XX_module.state == Power_ACTIVE) { + /* set new transition state to entering shutdown */ + PowerCC32XX_module.state = Power_ENTERING_SHUTDOWN; + + /* signal all clients registered for pre-shutdown notification */ + status = notify(PowerCC32XX_ENTERING_SHUTDOWN); + /* check for timeout or any other error */ + if (status != Power_SOK) { + PowerCC32XX_module.state = Power_ACTIVE; + HwiP_restore(hwiKey); + return (status); + } + /* shutdown the flash */ + PowerCC32XX_shutdownSSPI(); + /* if shutdown wakeup time was configured to be large enough */ + if (shutdownTime > (PowerCC32XX_TOTALTIMESHUTDOWN / 1000)) { + /* calculate the wakeup time for hibernate in RTC counts */ + counts = + (((uint64_t)(shutdownTime - + (PowerCC32XX_TOTALTIMESHUTDOWN / 1000)) + * 32768) / 1000); + + /* set the hibernate wakeup time */ + MAP_PRCMHibernateIntervalSet(counts); + + /* enable the wake source to be RTC */ + MAP_PRCMHibernateWakeupSourceEnable(PRCM_HIB_SLOW_CLK_CTR); + } + + /* enable IO retention */ + if (PowerCC32XX_config.ioRetentionShutdown) { + MAP_PRCMIORetentionEnable( + PowerCC32XX_config.ioRetentionShutdown); + } + + DebugP_log2( + "Power: entering shutdown state (%d), shutdownTime (%d)", + shutdownState, shutdownTime); + + /* enter hibernate - we should never return from here */ + MAP_PRCMHibernateEnter(); + } + else { + status = Power_EBUSY; + } + } + + /* set state to Power_ACTIVE */ + PowerCC32XX_module.state = Power_ACTIVE; + + /* re-enable interrupts */ + HwiP_restore(hwiKey); + + /* if get here, failed to shutdown, return error code */ + return (status); +} + +/* + * ======== Power_sleep ======== + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState) +{ + int_fast16_t status = Power_SOK; + //uint32_t romMajorVer; + //uint32_t romMinorVer; + uint32_t preEvent; + uint32_t postEvent; + uint32_t semBits; + //bool earlyPG = true; + + /* first validate the sleep state */ + if (sleepState != PowerCC32XX_LPDS) { + status = Power_EINVALIDINPUT; + } + + else if (PowerCC32XX_module.state == Power_ACTIVE) { + + /* set transition state to entering sleep */ + PowerCC32XX_module.state = Power_ENTERING_SLEEP; + + /* setup sleep vars */ + preEvent = PowerCC32XX_ENTERING_LPDS; + postEvent = PowerCC32XX_AWAKE_LPDS; + + /* signal all clients registered for pre-sleep notification */ + status = notify(preEvent); + + /* check for timeout or any other error */ + if (status != Power_SOK) { + PowerCC32XX_module.state = Power_ACTIVE; + return (status); + } + + DebugP_log1("Power: sleep, sleepState (%d)", sleepState); + + /* invoke specific sequence to activate LPDS ...*/ + + /* enable RAM retention */ + MAP_PRCMSRAMRetentionEnable( + PowerCC32XX_config.ramRetentionMaskLPDS, + PRCM_SRAM_LPDS_RET); + + /* call the enter LPDS hook function if configured */ + if (PowerCC32XX_config.enterLPDSHookFxn != NULL) { + (*(PowerCC32XX_config.enterLPDSHookFxn))(); + } + + /* park pins, based upon board file definitions */ + if (PowerCC32XX_config.pinParkDefs != NULL) { + parkPins(); + } + + /* save the NVIC registers */ + saveNVICRegs(); + + /* check if PG >= 2.01 */ + /*romMajorVer = HWREG(0x00000400) & 0xFFFF; + romMinorVer = HWREG(0x00000400) >> 16; + if ((romMajorVer >= 3) || ((romMajorVer == 2) && (romMinorVer >= 1))) { + earlyPG = false; + }*/ + + /* call sync barrier */ + SYNCBARRIER(); + + /* now enter LPDS - function does not return... */ +// TODO:Uncomment +#if 0 + if (PowerCC32XX_config.keepDebugActiveDuringLPDS == TRUE) { + if (earlyPG) { + PowerCC32XX_enterLPDS(PRCMLPDSEnterKeepDebugIf); + } + else { + PowerCC32XX_enterLPDS(ROM_PRCMLPDSEnterKeepDebugIfDirect); + } + } + else { + if (earlyPG) { + PowerCC32XX_enterLPDS(PRCMLPDSEnter); + } + else { + PowerCC32XX_enterLPDS(ROM_PRCMLPDSEnterDirect); + } + } +#endif + /* return here after reset, from Power_resumeLPDS() */ + + /* restore NVIC registers */ + restoreNVICRegs(); + + /* restore clock to those peripherals with dependecy set */ + restorePeriphClocks(); + + /* call PRCMCC3200MCUInit() for any necessary post-LPDS restore */ + MAP_PRCMCC3200MCUInit(); + + /* take the GPIO semaphore bits for the MCU */ + semBits = HWREG(0x400F703C); + semBits = (semBits & ~0x3FF) | 0x155; + HWREG(0x400F703C) = semBits; + + /* call the resume LPDS hook function if configured */ + if (PowerCC32XX_config.resumeLPDSHookFxn != NULL) { + (*(PowerCC32XX_config.resumeLPDSHookFxn))(); + } + + /* re-enable Slow Clock Counter Interrupt */ + MAP_PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR); + + /* set transition state to EXITING_SLEEP */ + PowerCC32XX_module.state = Power_EXITING_SLEEP; + + /* + * signal clients registered for post-sleep notification; for example, + * a driver that needs to reinitialize its peripheral state, that was + * lost during LPDS + */ + status = notify(postEvent); + + /* restore pins parked before LPDS to their previous states */ + if (PowerCC32XX_config.pinParkDefs != NULL) { + restoreParkedPins(); + } + + /* if wake source was GPIO, optionally call wakeup function */ + if (MAP_PRCMLPDSWakeupCauseGet() == PRCM_LPDS_GPIO) { + if (PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS != NULL) { + (*(PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS)) + (PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg); + } + } + + /* now clear the transition state before re-enabling scheduler */ + PowerCC32XX_module.state = Power_ACTIVE; + } + else { + status = Power_EBUSY; + } + + return (status); +} + +/* + * ======== Power_unregisterNotify ======== + * Unregister for a power notification. + * + */ +void Power_unregisterNotify(Power_NotifyObj * pNotifyObj) +{ + uintptr_t key; + + /* disable interrupts */ + key = HwiP_disable(); + + /* remove notify object from its event queue */ + List_remove(&PowerCC32XX_module.notifyList, (List_Elem *)pNotifyObj); + + /* re-enable interrupts */ + HwiP_restore(key); + + DebugP_log1("Power: unregister notify (%p)", (uintptr_t) pNotifyObj); +} + +/*********************** CC32XX-specific functions **************************/ + +/* + * ======== PowerCC32XX_configureWakeup ======== + * Configure LPDS and shutdown wakeups; copy settings into driver state + */ +void PowerCC32XX_configureWakeup(PowerCC32XX_Wakeup *wakeup) +{ + /* configure network (Host IRQ) as wakeup source for LPDS */ + if (wakeup->enableNetworkWakeupLPDS) { + MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_HOST_IRQ); + } + else { + MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_HOST_IRQ); + } + PowerCC32XX_module.wakeupConfig.enableNetworkWakeupLPDS = + wakeup->enableNetworkWakeupLPDS; + + /* configure GPIO as wakeup source for LPDS */ + if (wakeup->enableGPIOWakeupLPDS) { + MAP_PRCMLPDSWakeUpGPIOSelect( + wakeup->wakeupGPIOSourceLPDS, + wakeup->wakeupGPIOTypeLPDS); + MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_GPIO); + } + else { + MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_GPIO); + } + PowerCC32XX_module.wakeupConfig.enableGPIOWakeupLPDS = + wakeup->enableGPIOWakeupLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceLPDS = + wakeup->wakeupGPIOSourceLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeLPDS = + wakeup->wakeupGPIOTypeLPDS; + + /* configure GPIO as wakeup source for Shutdown */ + if (wakeup->enableGPIOWakeupShutdown) { + MAP_PRCMHibernateWakeUpGPIOSelect( + wakeup->wakeupGPIOSourceShutdown, + wakeup->wakeupGPIOTypeShutdown); + MAP_PRCMHibernateWakeupSourceEnable( + wakeup->wakeupGPIOSourceShutdown); + } + else { + MAP_PRCMHibernateWakeupSourceDisable( + wakeup->wakeupGPIOSourceShutdown); + } + PowerCC32XX_module.wakeupConfig.enableGPIOWakeupShutdown = + wakeup->enableGPIOWakeupShutdown; + PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceShutdown = + wakeup->wakeupGPIOSourceShutdown; + PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeShutdown = + wakeup->wakeupGPIOTypeShutdown; + + /* copy the LPDS GPIO wakeup function and arg to module state */ + PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS = + wakeup->wakeupGPIOFxnLPDS; + PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg = + wakeup->wakeupGPIOFxnLPDSArg; +} + +/* + * ======== PowerCC32XX_disableIORetention ======== + * Disable IO retention and unlock pins after exit from Shutdown + */ +void PowerCC32XX_disableIORetention(unsigned long groupFlags) +{ + MAP_PRCMIORetentionDisable(groupFlags); +} + +/* + * ======== PowerCC32XX_getParkState ======== + * Get the current LPDS park state for a pin + */ +PowerCC32XX_ParkState PowerCC32XX_getParkState(PowerCC32XX_Pin pin) +{ + PowerCC32XX_ParkInfo parkInfo; + PowerCC32XX_ParkState state = PowerCC32XX_DONT_PARK; + uint32_t i; + + DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); + + /* step thru the pin park array until find the pin */ + for (i = 0; i < PowerCC32XX_config.numPins; i++) { + + parkInfo = PowerCC32XX_config.pinParkDefs[i]; + + /* if this is the pin to be checked... */ + if (parkInfo.pin == pin) { + state = (PowerCC32XX_ParkState) parkInfo.parkState; + break; + } + } + + return (state); +} + +/* + * ======== PowerCC32XX_getWakeup ======== + * Get the current LPDS and shutdown wakeup configuration + */ +void PowerCC32XX_getWakeup(PowerCC32XX_Wakeup *wakeup) +{ + *wakeup = PowerCC32XX_module.wakeupConfig; +} + +/* + * ======== PowerCC32XX_parkPin ======== + * Park a device pin in preparation for LPDS + */ +void PowerCC32XX_parkPin(PowerCC32XX_Pin pin, PowerCC32XX_ParkState parkState, + uint32_t * previousType, uint16_t * previousDirection) +{ + unsigned long strength; + unsigned long type; + + /* get the current pin configuration */ + MAP_PinConfigGet(pin, &strength, &type); + + /* stash the current pin type */ + *previousType = type; + + /* get and stash the current pin direction */ + *previousDirection = (uint16_t)MAP_PinDirModeGet(pin); + + /* set pin type to the parking state */ + MAP_PinConfigSet(pin, strength, (unsigned long) parkState); + + /* set pin direction to input to HiZ the pin */ + MAP_PinDirModeSet(pin, PIN_DIR_MODE_IN); +} + +/* + * ======== PowerCC32XX_restoreParkedPin ======== + * Restore a pin that was previously parked with PowerCC32XX_parkPin + */ +void PowerCC32XX_restoreParkedPin(PowerCC32XX_Pin pin, uint32_t type, + uint16_t direction) +{ + unsigned long strength; + unsigned long currentType; + + /* get the current pin configuration */ + MAP_PinConfigGet(pin, &strength, ¤tType); + + /* restore the pin type */ + MAP_PinConfigSet(pin, strength, type); + + /* restore the pin direction */ + MAP_PinDirModeSet(pin, (unsigned long)direction); +} + +/* + * ======== PowerCC32XX_restoreParkState ======== + * Restore the LPDS park state for a pin + */ +void PowerCC32XX_restoreParkState(PowerCC32XX_Pin pin, + PowerCC32XX_ParkState state) +{ + PowerCC32XX_ParkInfo parkInfo; + uint32_t i; + + DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); + + /* step thru the park array until find the pin to be updated */ + for (i = 0; i < PowerCC32XX_config.numPins; i++) { + + parkInfo = PowerCC32XX_config.pinParkDefs[i]; + + /* if this is the pin to be restored... */ + if (parkInfo.pin == pin) { + parkInfo.parkState = state; + PowerCC32XX_config.pinParkDefs[i] = parkInfo; + break; + } + } +} + +/* + * ======== PowerCC32XX_setParkState ======== + * Set a new LPDS park state for a pin + */ +void PowerCC32XX_setParkState(PowerCC32XX_Pin pin, uint32_t level) +{ + PowerCC32XX_ParkInfo parkInfo; + PowerCC32XX_ParkState state; + uint32_t i; + + DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); + + /* first check if level indicates "don't park" */ + if (level == (uint32_t)~1) { + state = PowerCC32XX_DONT_PARK; + } + + /* else, check device revision to choose park state */ + /* if ES2.00 or later, drive the pin */ + else if((HWREG(0x00000400) & 0xFFFF) >= 2) { + state = (level) ? PowerCC32XX_DRIVE_HIGH : PowerCC32XX_DRIVE_LOW; + } + /* else, for earlier devices use the weak pull resistor */ + else { + state = (level) ? PowerCC32XX_WEAK_PULL_UP_STD : + PowerCC32XX_WEAK_PULL_DOWN_STD; + } + + /* step thru the park array until find the pin to be updated */ + for (i = 0; i < PowerCC32XX_config.numPins; i++) { + + parkInfo = PowerCC32XX_config.pinParkDefs[i]; + + /* if this is the pin to be updated... */ + if (parkInfo.pin == pin) { + parkInfo.parkState = state; + PowerCC32XX_config.pinParkDefs[i] = parkInfo; + break; + } + } +} + +/* + * ======== PowerCC32XX_shutdownSSPI ======== + * Put SPI flash into Deep Power Down mode + */ +void PowerCC32XX_shutdownSSPI(void) +{ + unsigned long status = 0; + + /* Acquire SSPI HwSpinlock. */ + if (0 != MAP_HwSpinLockTryAcquire(HWSPINLOCK_SSPI, PowerCC32XX_SSPISemaphoreTakeTries)){ + return; + } + + /* Enable clock for SSPI module */ + MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK); + + /* Reset SSPI at PRCM level and wait for reset to complete */ + MAP_PRCMPeripheralReset(PRCM_SSPI); + while(MAP_PRCMPeripheralStatusGet(PRCM_SSPI)== false){ + } + + /* Reset SSPI at module level */ + MAP_SPIReset(SSPI_BASE); + + /* Configure SSPI module */ + MAP_SPIConfigSetExpClk(SSPI_BASE,PRCMPeripheralClockGet(PRCM_SSPI), + 20000000,SPI_MODE_MASTER,SPI_SUB_MODE_0, + (SPI_SW_CTRL_CS | + SPI_4PIN_MODE | + SPI_TURBO_OFF | + SPI_CS_ACTIVELOW | + SPI_WL_8)); + + /* Enable SSPI module */ + MAP_SPIEnable(SSPI_BASE); + + /* Allow settling before enabling chip select */ + uSEC_DELAY(PowerCC32XX_SSPICSDelay); + + /* Enable chip select for the spi flash. */ + MAP_SPICSEnable(SSPI_BASE); + + /* Wait for spi flash. */ + do{ + /* Send status register read instruction and read back a dummy byte. */ + MAP_SPIDataPut(SSPI_BASE,PowerCC32XX_SSPIReadStatusInstruction); + MAP_SPIDataGet(SSPI_BASE,&status); + + /* Write a dummy byte then read back the actual status. */ + MAP_SPIDataPut(SSPI_BASE,0xFF); + MAP_SPIDataGet(SSPI_BASE,&status); + } while((status & 0xFF )== STATUS_BUSY); + + /* Disable chip select for the spi flash. */ + MAP_SPICSDisable(SSPI_BASE); + + /* Start another CS enable sequence for Power down command. */ + MAP_SPICSEnable(SSPI_BASE); + + /* Send Deep Power Down command to spi flash */ + MAP_SPIDataPut(SSPI_BASE,PowerCC32XX_SSPIPowerDownInstruction); + + /* Disable chip select for the spi flash. */ + MAP_SPICSDisable(SSPI_BASE); + + /* Release SSPI HwSpinlock. */ + MAP_HwSpinLockRelease(HWSPINLOCK_SSPI); + + return; +} + +/* + * ======== PowerCC32XX_reset ======== + * Software reset of specific peripheral. + */ +int_fast16_t PowerCC32XX_reset(uint_fast16_t resourceId) +{ + int_fast16_t status = Power_SOK; + uint32_t id; + + /* Ensure resourceId is valid */ + if (resourceId >= PowerCC32XX_NUMRESOURCES) { + status = Power_EINVALIDINPUT; + } + + /* resourceId is OK ... */ + else { + + id = PowerCC32XX_module.dbRecords[resourceId]; + /* Reset the peripheral */ + MAP_PRCMPeripheralReset(id); + } + return (status); +} + +/*************************internal functions ****************************/ + +/* + * ======== notify ======== + * Note: When this function is called hardware interrupts are disabled + */ +static int_fast16_t notify(uint_fast16_t eventType) +{ + int_fast16_t notifyStatus; + Power_NotifyFxn notifyFxn; + uintptr_t clientArg; + List_Elem *elem; + + /* if queue is empty, return immediately */ + if (!List_empty(&PowerCC32XX_module.notifyList)) { + /* point to first client notify object */ + elem = List_head(&PowerCC32XX_module.notifyList); + + /* walk the queue and notify each registered client of the event */ + do { + if (((Power_NotifyObj *)elem)->eventTypes & eventType) { + /* pull params from notify object */ + notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; + clientArg = ((Power_NotifyObj *)elem)->clientArg; + + /* call the client's notification function */ + notifyStatus = (int_fast16_t) (*(Power_NotifyFxn)notifyFxn)( + eventType, 0, clientArg); + + /* if client declared error stop all further notifications */ + if (notifyStatus != Power_NOTIFYDONE) { + return (Power_EFAIL); + } + } + + /* get next element in the notification queue */ + elem = List_next(elem); + + } while (elem != NULL); + } + + return (Power_SOK); +} + +/* + * ======== restoreNVICRegs ======== + * Restore the NVIC registers + */ +static void restoreNVICRegs(void) +{ + uint32_t i; + uint32_t *base_reg_addr; + + /* Restore the NVIC control registers */ + HWREG(NVIC_VTABLE) = PowerCC32XX_contextSave.nvicRegs.vectorTable; + HWREG(NVIC_ACTLR) = PowerCC32XX_contextSave.nvicRegs.auxCtrl; + HWREG(NVIC_APINT) = PowerCC32XX_contextSave.nvicRegs.appInt; + HWREG(NVIC_INT_CTRL) = PowerCC32XX_contextSave.nvicRegs.intCtrlState; + HWREG(NVIC_SYS_CTRL) = PowerCC32XX_contextSave.nvicRegs.sysCtrl; + HWREG(NVIC_CFG_CTRL) = PowerCC32XX_contextSave.nvicRegs.configCtrl; + HWREG(NVIC_SYS_PRI1) = PowerCC32XX_contextSave.nvicRegs.sysPri1; + HWREG(NVIC_SYS_PRI2) = PowerCC32XX_contextSave.nvicRegs.sysPri2; + HWREG(NVIC_SYS_PRI3) = PowerCC32XX_contextSave.nvicRegs.sysPri3; + HWREG(NVIC_SYS_HND_CTRL) = PowerCC32XX_contextSave.nvicRegs.sysHcrs; + + /* Systick registers */ + HWREG(NVIC_ST_CTRL) = PowerCC32XX_contextSave.nvicRegs.systickCtrl; + HWREG(NVIC_ST_RELOAD) = PowerCC32XX_contextSave.nvicRegs.systickReload; + HWREG(NVIC_ST_CAL) = PowerCC32XX_contextSave.nvicRegs.systickCalib; + + /* Restore the interrupt priority registers */ + base_reg_addr = (uint32_t *)NVIC_PRI0; + for(i = 0; i < PowerCC32XX_numNVICIntPriority; i++) { + base_reg_addr[i] = PowerCC32XX_contextSave.nvicRegs.intPriority[i]; + } + + /* Restore the interrupt enable registers */ + base_reg_addr = (uint32_t *)NVIC_EN0; + for(i = 0; i < PowerCC32XX_numNVICSetEnableRegs; i++) { + base_reg_addr[i] = PowerCC32XX_contextSave.nvicRegs.intSetEn[i]; + } + + /* Data and instruction sync barriers */ + SYNCBARRIER(); +} + +/* + * ======== restorePeriphClocks ======== + * Restores the peripheral clocks that had dependency set + */ +static void restorePeriphClocks(void) +{ + uint32_t dependCount; + uint32_t i; + + /* need to re-enable peripheral clocks to those with set dependency */ + for (i = 0; i < PowerCC32XX_NUMRESOURCES; i++) { + dependCount = Power_getDependencyCount(i); + if (dependCount > 0) { + MAP_PRCMPeripheralClkEnable(PowerCC32XX_module.dbRecords[i], + PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); + + while(!MAP_PRCMPeripheralStatusGet(PowerCC32XX_module.dbRecords[i])) { + } + } + } +} + +/* + * ======== saveNVICRegs ======== + * Save away the NVIC registers for LPDS mode. + */ +static void saveNVICRegs(void) +{ + uint32_t i; + uint32_t *base_reg_addr; + + /* Save the NVIC control registers */ + PowerCC32XX_contextSave.nvicRegs.vectorTable = HWREG(NVIC_VTABLE); + PowerCC32XX_contextSave.nvicRegs.auxCtrl = HWREG(NVIC_ACTLR); + PowerCC32XX_contextSave.nvicRegs.intCtrlState = HWREG(NVIC_INT_CTRL); + PowerCC32XX_contextSave.nvicRegs.appInt = HWREG(NVIC_APINT); + PowerCC32XX_contextSave.nvicRegs.sysCtrl = HWREG(NVIC_SYS_CTRL); + PowerCC32XX_contextSave.nvicRegs.configCtrl = HWREG(NVIC_CFG_CTRL); + PowerCC32XX_contextSave.nvicRegs.sysPri1 = HWREG(NVIC_SYS_PRI1); + PowerCC32XX_contextSave.nvicRegs.sysPri2 = HWREG(NVIC_SYS_PRI2); + PowerCC32XX_contextSave.nvicRegs.sysPri3 = HWREG(NVIC_SYS_PRI3); + PowerCC32XX_contextSave.nvicRegs.sysHcrs = HWREG(NVIC_SYS_HND_CTRL); + + /* Systick registers */ + PowerCC32XX_contextSave.nvicRegs.systickCtrl = HWREG(NVIC_ST_CTRL); + PowerCC32XX_contextSave.nvicRegs.systickReload = HWREG(NVIC_ST_RELOAD); + PowerCC32XX_contextSave.nvicRegs.systickCalib = HWREG(NVIC_ST_CAL); + + /* Save the interrupt enable registers */ + base_reg_addr = (uint32_t *)NVIC_EN0; + for (i = 0; i < PowerCC32XX_numNVICSetEnableRegs; i++) { + PowerCC32XX_contextSave.nvicRegs.intSetEn[i] = base_reg_addr[i]; + } + + /* Save the interrupt priority registers */ + base_reg_addr = (uint32_t *)NVIC_PRI0; + for (i = 0; i < PowerCC32XX_numNVICIntPriority; i++) { + PowerCC32XX_contextSave.nvicRegs.intPriority[i] = base_reg_addr[i]; + } +} + +/* + * ======== parkPins ======== + */ +static void parkPins(void) +{ + PowerCC32XX_ParkInfo parkInfo; + uint32_t antpadreg; + uint32_t i; + + DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); + + /* for each pin in the park array ... */ + for (i = 0; i < PowerCC32XX_config.numPins; i++) { + + parkInfo = PowerCC32XX_config.pinParkDefs[i]; + + /* skip this pin if "don't park" is specified */ + if (parkInfo.parkState == PowerCC32XX_DONT_PARK) { + continue; + } + + /* if this is a special antenna select pin, stash current pad state */ + if (parkInfo.pin == PowerCC32XX_PIN29) { + antpadreg = 0x4402E108; + PowerCC32XX_module.stateAntPin29 = (uint16_t) HWREG(antpadreg); + } + else if (parkInfo.pin == PowerCC32XX_PIN30) { + antpadreg = 0x4402E10C; + PowerCC32XX_module.stateAntPin30 = (uint16_t) HWREG(antpadreg); + } + else { + antpadreg = 0; + } + + /* if this is antenna select pin, park via direct writes to pad reg */ + if (antpadreg != 0) { + HWREG(antpadreg) &= 0xFFFFF0EF; /* first clear bits 4, 8-11 */ + if (parkInfo.parkState == PowerCC32XX_NO_PULL_HIZ) { + HWREG(antpadreg) |= 0x00000C00; + } + else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_UP_STD) { + HWREG(antpadreg) |= 0x00000D00; + } + else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_DOWN_STD) { + HWREG(antpadreg) |= 0x00000E00; + } + else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_UP_OPENDRAIN) { + HWREG(antpadreg) |= 0x00000D10; + } + else if (parkInfo.parkState == + PowerCC32XX_WEAK_PULL_DOWN_OPENDRAIN) { + HWREG(antpadreg) |= 0x00000E10; + } + } + + /* else, for all other pins */ + else { + + /* if pin is NOT to be driven, park it to the specified state... */ + if ((parkInfo.parkState != PowerCC32XX_DRIVE_LOW) && + (parkInfo.parkState != PowerCC32XX_DRIVE_HIGH)) { + + PowerCC32XX_parkPin( + (PowerCC32XX_Pin)parkInfo.pin, + (PowerCC32XX_ParkState)parkInfo.parkState, + &PowerCC32XX_module.pinType[i], + &PowerCC32XX_module.pinDir[i]); + } + + /* + * else, now check if the pin CAN be driven (pins 45, 53, and 55 + * can't be driven) + */ + else if ((parkInfo.pin != PowerCC32XX_PIN45) && + (parkInfo.pin != PowerCC32XX_PIN53) && + (parkInfo.pin != PowerCC32XX_PIN55)){ + + /* + * must ensure pin mode is zero; first get/stash current mode, + * then set mode to zero + */ + PowerCC32XX_module.pinMode[i] = + (uint8_t)MAP_PinModeGet(parkInfo.pin); + MAP_PinModeSet(parkInfo.pin, 0); + + /* if pin is to be driven low, set the lock level to 0 */ + if (parkInfo.parkState == PowerCC32XX_DRIVE_LOW) { + MAP_PinLockLevelSet((PowerCC32XX_Pin)parkInfo.pin, 0); + PowerCC32XX_module.pinLockMask |= 1 << + PinToPadGet(parkInfo.pin); + } + + /* else, pin to be driven high, set lock level to 1 */ + else { + MAP_PinLockLevelSet((PowerCC32XX_Pin)parkInfo.pin, 1); + PowerCC32XX_module.pinLockMask |= 1 << + PinToPadGet(parkInfo.pin); + } + } + } + } + + /* if any pins are to be driven, lock them now */ + if (PowerCC32XX_module.pinLockMask) { + MAP_PinLock(PowerCC32XX_module.pinLockMask); + } +} + +/* + * ======== restoreParkedPins ======== + */ +static void restoreParkedPins(void) +{ + PowerCC32XX_ParkInfo parkInfo; + uint32_t i; + + DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); + + /* first, unlock any locked pins (that were driven high or low) */ + if (PowerCC32XX_module.pinLockMask) { + MAP_PinUnlock(); + } + + /* now, for each pin in the park array ... */ + for (i = 0; i < PowerCC32XX_config.numPins; i++) { + + parkInfo = PowerCC32XX_config.pinParkDefs[i]; + + /* skip this pin if "don't park" is specified */ + if (parkInfo.parkState == PowerCC32XX_DONT_PARK) { + continue; + } + + /* if this is special antenna select pin: restore the saved pad state */ + if (parkInfo.pin == PowerCC32XX_PIN29) { + HWREG(0x4402E108) = ((HWREG(0x4402E108) & 0xFFFFF000) | + (PowerCC32XX_module.stateAntPin29 & 0x00000FFF)); + } + + else if (parkInfo.pin == PowerCC32XX_PIN30) { + HWREG(0x4402E10C) = ((HWREG(0x4402E10C) & 0xFFFFF000) | + (PowerCC32XX_module.stateAntPin30 & 0x00000FFF)); + } + + /* else if pin was driven during LPDS, restore the pin mode */ + else if ((parkInfo.parkState == PowerCC32XX_DRIVE_LOW) || + (parkInfo.parkState == PowerCC32XX_DRIVE_HIGH)) { + MAP_PinModeSet(parkInfo.pin, + (unsigned long)PowerCC32XX_module.pinMode[i]); + } + + /* else, restore all others */ + else { + /* if pin parked in a non-driven state, restore type & direction */ + if ((parkInfo.parkState != PowerCC32XX_DRIVE_LOW) && + (parkInfo.parkState != PowerCC32XX_DRIVE_HIGH)) { + + PowerCC32XX_restoreParkedPin( + (PowerCC32XX_Pin)parkInfo.pin, + PowerCC32XX_module.pinType[i], + PowerCC32XX_module.pinDir[i]); + } + } + } +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.h new file mode 100755 index 00000000000..25db541469f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/power/PowerCC32XX.h @@ -0,0 +1,660 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PowerCC32XX.h + * + * @brief Power manager interface for the CC32XX + * + * The Power header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Power.h for a complete description of APIs. + * + * ## Implementation # + * This module defines the power resources, constraints, events, sleep + * states and transition latencies for CC32XX. + * + * A reference power policy is provided which can transition the MCU from the + * active state to one of two sleep states: LPDS or Sleep. + * The policy looks at the estimated idle time remaining, and the active + * constraints, and determine which sleep state to transition to. The + * policy will give first preference to choosing LPDS, but if that is not + * appropriate (e.g., not enough idle time), it will choose Sleep. + * + * ============================================================================ + */ + +#ifndef ti_drivers_power_PowerCC32XX__include +#define ti_drivers_power_PowerCC32XX__include + +#include +#include +#include + +/* driverlib header files */ +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* latency values were measured with a logic analyzer, and rounded up */ + +/*! The latency to reserve for resuming from LPDS (usec) */ +#define PowerCC32XX_RESUMETIMELPDS 2500 + +/*! The total latency to reserve for entry to and exit from LPDS (usec) */ +#define PowerCC32XX_TOTALTIMELPDS 20000 + +/*! The total latency to reserve for entry to and exit from Shutdown (usec) */ +#define PowerCC32XX_TOTALTIMESHUTDOWN 500000 + +/* Power resources */ +#define PowerCC32XX_PERIPH_CAMERA 0 +/*!< Resource ID: Camera */ + +#define PowerCC32XX_PERIPH_I2S 1 +/*!< Resource ID: I2S */ + +#define PowerCC32XX_PERIPH_SDHOST 2 +/*!< Resource ID: SDHost */ + +#define PowerCC32XX_PERIPH_GSPI 3 +/*!< Resource ID: General Purpose SPI (GSPI) */ + +#define PowerCC32XX_PERIPH_LSPI 4 +/*!< Resource ID: LSPI */ + +#define PowerCC32XX_PERIPH_UDMA 5 +/*!< Resource ID: uDMA Controller */ + +#define PowerCC32XX_PERIPH_GPIOA0 6 +/*!< Resource ID: General Purpose I/O Port A0 */ + +#define PowerCC32XX_PERIPH_GPIOA1 7 +/*!< Resource ID: General Purpose I/O Port A1 */ + +#define PowerCC32XX_PERIPH_GPIOA2 8 +/*!< Resource ID: General Purpose I/O Port A2 */ + +#define PowerCC32XX_PERIPH_GPIOA3 9 +/*!< Resource ID: General Purpose I/O Port A3 */ + +#define PowerCC32XX_PERIPH_GPIOA4 10 +/*!< Resource ID: General Purpose I/O Port A4 */ + +#define PowerCC32XX_PERIPH_WDT 11 +/*!< Resource ID: Watchdog module */ + +#define PowerCC32XX_PERIPH_UARTA0 12 +/*!< Resource ID: UART 0 */ + +#define PowerCC32XX_PERIPH_UARTA1 13 +/*!< Resource ID: UART 1 */ + +#define PowerCC32XX_PERIPH_TIMERA0 14 +/*!< Resource ID: General Purpose Timer A0 */ + +#define PowerCC32XX_PERIPH_TIMERA1 15 +/*!< Resource ID: General Purpose Timer A1 */ + +#define PowerCC32XX_PERIPH_TIMERA2 16 +/*!< Resource ID: General Purpose Timer A2 */ + +#define PowerCC32XX_PERIPH_TIMERA3 17 +/*!< Resource ID: General Purpose Timer A3 */ + +#define PowerCC32XX_PERIPH_DTHE 18 +/*!< Resource ID: Cryptography Accelerator (DTHE) */ + +#define PowerCC32XX_PERIPH_SSPI 19 +/*!< Resource ID: Serial Flash SPI (SSPI) */ + +#define PowerCC32XX_PERIPH_I2CA0 20 +/*!< Resource ID: I2C */ + +/* \cond */ +#define PowerCC32XX_NUMRESOURCES 21 /* Number of resources in database */ +/* \endcond */ + +/* + * Power constraints on the CC32XX device + */ +#define PowerCC32XX_DISALLOW_LPDS 0 +/*!< Constraint: Disallow entry to Low Power Deep Sleep (LPDS) */ + +#define PowerCC32XX_DISALLOW_SHUTDOWN 1 +/*!< Constraint: Disallow entry to Shutdown */ + +/* \cond */ +#define PowerCC32XX_NUMCONSTRAINTS 2 /*!< number of constraints */ +/* \endcond */ + +/* + * Power events on the CC32XX device + * + * Each event must be a power of two, and the event IDs must be sequential + * without any gaps. + */ +#define PowerCC32XX_ENTERING_LPDS 0x1 +/*!< Power event: The device is entering the LPDS sleep state */ + +#define PowerCC32XX_ENTERING_SHUTDOWN 0x2 +/*!< Power event: The device is entering the Shutdown state */ + +#define PowerCC32XX_AWAKE_LPDS 0x4 +/*!< Power event: The device is waking from the LPDS sleep state */ + +/* \cond */ +#define PowerCC32XX_NUMEVENTS 3 /*!< number of events */ +/* \endcond */ + +/* Power sleep states */ +#define PowerCC32XX_LPDS 0x1 /*!< The LPDS sleep state */ + +/* \cond */ +/* Use by NVIC Register structure */ +#define PowerCC32XX_numNVICSetEnableRegs 6 +#define PowerCC32XX_numNVICIntPriority 49 +/* \endcond */ + +/* \cond */ +/* Number of pins that can be parked in LPDS */ +#define PowerCC32XX_NUMPINS 34 +/* \endcond */ + +/*! @brief Used to specify parking of a pin during LPDS */ +typedef struct PowerCC32XX_ParkInfo { + uint32_t pin; + /*!< The pin to be parked */ + uint32_t parkState; + /*!< The state to park the pin (an enumerated PowerCC32XX_ParkState) */ +} PowerCC32XX_ParkInfo; + +/*! @brief Power global configuration */ +typedef struct PowerCC32XX_ConfigV1 { + /*! Initialization function for the power policy */ + Power_PolicyInitFxn policyInitFxn; + /*! The power policy function */ + Power_PolicyFxn policyFxn; + /*! + * @brief Hook function called before entering LPDS + * + * This function is called after any notifications are complete, + * and before any pins are parked, just before entry to LPDS. + */ + void (*enterLPDSHookFxn)(void); + /*! + * @brief Hook function called when resuming from LPDS + * + * This function is called early in the wake sequence, before any + * notification functions are run. + */ + void (*resumeLPDSHookFxn)(void); + /*! Determines whether to run the power policy function */ + bool enablePolicy; + /*! Enable GPIO as a wakeup source for LPDS */ + bool enableGPIOWakeupLPDS; + /*! Enable GPIO as a wakeup source for shutdown */ + bool enableGPIOWakeupShutdown; + /*! Enable Network activity as a wakeup source for LPDS */ + bool enableNetworkWakeupLPDS; + /*! + * @brief The GPIO source for wakeup from LPDS + * + * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source + * for LPDS. The GPIO must be specified as one of the following (as + * defined in driverlib/prcm.h): PRCM_LPDS_GPIO2, PRCM_LPDS_GPIO4, + * PRCM_LPDS_GPIO11, PRCM_LPDS_GPIO13, PRCM_LPDS_GPIO17, PRCM_LPDS_GPIO24, + * PRCM_LPDS_GPIO26 + */ + uint32_t wakeupGPIOSourceLPDS; + /*! + * @brief The GPIO trigger type for wakeup from LPDS + * + * Value can be one of the following (defined in driverlib/prcm.h): + * PRCM_LPDS_LOW_LEVEL, PRCM_LPDS_HIGH_LEVEL, + * PRCM_LPDS_FALL_EDGE, PRCM_LPDS_RISE_EDGE + */ + uint32_t wakeupGPIOTypeLPDS; + /*! + * @brief Function to be called when the configured GPIO triggers wakeup + * from LPDS + * + * During LPDS the internal GPIO module is powered off, and special + * periphery logic is used instead to detect the trigger and wake the + * device. No GPIO interrupt service routine will be triggered in this + * case (even if an ISR is configured, and used normally to detect GPIO + * interrupts when not in LPDS). This function can be used in lieu of a + * GPIO ISR, to take specific action upon LPDS wakeup. + * + * A value of NULL indicates no GPIO wakeup function will be called. + * + * An argument for this wakeup function can be specified via + * wakeupGPIOFxnLPDSArg. + * + * Note that this wakeup function will be called as one of the last steps + * in Power_sleep(), after all notifications have been sent out, and after + * pins have been restored to their previous (non-parked) states. + */ + void (*wakeupGPIOFxnLPDS)(uint_least8_t argument); + /*! + * @brief The argument to be passed to wakeupGPIOFxnLPDS() + */ + uint_least8_t wakeupGPIOFxnLPDSArg; + /*! + * @brief The GPIO sources for wakeup from shutdown + * + * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source + * for Shutdown. The GPIO must be specified as one of the following (as + * defined in driverlib/prcm.h): PRCM_HIB_GPIO2, PRCM_HIB_GPIO4, + * PRCM_HIB_GPIO11, PRCM_HIB_GPIO13, PRCM_HIB_GPIO17, PRCM_HIB_GPIO24, + * PRCM_HIB_GPIO26 + */ + uint32_t wakeupGPIOSourceShutdown; + /*! + * @brief The GPIO trigger type for wakeup from shutdown + * + * Value can be one of the following (defined in driverlib/prcm.h): + * PRCM_HIB_LOW_LEVEL, PRCM_HIB_HIGH_LEVEL, + * PRCM_HIB_FALL_EDGE, PRCM_HIB_RISE_EDGE + */ + uint32_t wakeupGPIOTypeShutdown; + /*! + * @brief SRAM retention mask for LPDS + * + * Value can be a mask of the following (defined in driverlib/prcm.h): + * PRCM_SRAM_COL_1, PRCM_SRAM_COL_2, PRCM_SRAM_COL_3, + * PRCM_SRAM_COL_4 + */ + uint32_t ramRetentionMaskLPDS; + /*! + * @brief Keep debug interface active during LPDS + * + * This Boolean controls whether the debug interface will be left active + * when LPDS is entered. For best power savings this flag should be set + * to false. Setting the flag to true will enable better debug + * capability, but will prevent full LPDS, and will result in increased + * power consumption. + */ + bool keepDebugActiveDuringLPDS; + /*! + * @brief IO retention mask for Shutdown + * + * Value can be a mask of the following (defined in driverlib/prcm.h): + * PRCM_IO_RET_GRP_0, PRCM_IO_RET_GRP_1, PRCM_IO_RET_GRP_2 + * PRCM_IO_RET_GRP_3 + */ + uint32_t ioRetentionShutdown; + /*! + * @brief Pointer to an array of pins to be parked during LPDS + * + * A value of NULL will disable parking of any pins during LPDS + */ + PowerCC32XX_ParkInfo * pinParkDefs; + /*! + * @brief Number of pins to be parked during LPDS + */ + uint32_t numPins; +} PowerCC32XX_ConfigV1; + +/*! + * @cond NODOC + * NVIC registers that need to be saved before entering LPDS. + */ +typedef struct PowerCC32XX_NVICRegisters { + uint32_t vectorTable; + uint32_t auxCtrl; + uint32_t intCtrlState; + uint32_t appInt; + uint32_t sysCtrl; + uint32_t configCtrl; + uint32_t sysPri1; + uint32_t sysPri2; + uint32_t sysPri3; + uint32_t sysHcrs; + uint32_t systickCtrl; + uint32_t systickReload; + uint32_t systickCalib; + uint32_t intSetEn[PowerCC32XX_numNVICSetEnableRegs]; + uint32_t intPriority[PowerCC32XX_numNVICIntPriority]; +} PowerCC32XX_NVICRegisters; +/*! @endcond */ + +/*! + * @cond NODOC + * MCU core registers that need to be save before entering LPDS. + */ +typedef struct PowerCC32XX_MCURegisters { + uint32_t msp; + uint32_t psp; + uint32_t psr; + uint32_t primask; + uint32_t faultmask; + uint32_t basepri; + uint32_t control; +} PowerCC32XX_MCURegisters; +/*! @endcond */ + +/*! + * @cond NODOC + * Structure of context registers to save before entering LPDS. + */ +typedef struct PowerCC32XX_SaveRegisters { + PowerCC32XX_MCURegisters m4Regs; + PowerCC32XX_NVICRegisters nvicRegs; +} PowerCC32XX_SaveRegisters; +/*! @endcond */ + +/*! @brief Enumeration of states a pin can be parked in */ +typedef enum { + /*! No pull resistor, leave pin in a HIZ state */ + PowerCC32XX_NO_PULL_HIZ = PIN_TYPE_STD, + /*! Pull-up resistor for standard pin type */ + PowerCC32XX_WEAK_PULL_UP_STD = PIN_TYPE_STD_PU, + /*! Pull-down resistor for standard pin type */ + PowerCC32XX_WEAK_PULL_DOWN_STD = PIN_TYPE_STD_PD, + /*! Pull-up resistor for open drain pin type */ + PowerCC32XX_WEAK_PULL_UP_OPENDRAIN = PIN_TYPE_OD_PU, + /*! Pull-down resistor for open drain pin type */ + PowerCC32XX_WEAK_PULL_DOWN_OPENDRAIN = PIN_TYPE_OD_PD, + /*! Drive pin to a low logic state */ + PowerCC32XX_DRIVE_LOW, + /*! Drive pin to a high logic state */ + PowerCC32XX_DRIVE_HIGH, + /*! Take no action; do not park the pin */ + PowerCC32XX_DONT_PARK +} PowerCC32XX_ParkState; + +/*! @brief Enumeration of pins that can be parked */ +typedef enum { + /*! PIN_01 */ + PowerCC32XX_PIN01 = PIN_01, + /*! PIN_02 */ + PowerCC32XX_PIN02 = PIN_02, + /*! PIN_03 */ + PowerCC32XX_PIN03 = PIN_03, + /*! PIN_04 */ + PowerCC32XX_PIN04 = PIN_04, + /*! PIN_05 */ + PowerCC32XX_PIN05 = PIN_05, + /*! PIN_06 */ + PowerCC32XX_PIN06 = PIN_06, + /*! PIN_07 */ + PowerCC32XX_PIN07 = PIN_07, + /*! PIN_08 */ + PowerCC32XX_PIN08 = PIN_08, + /*! PIN_11 */ + PowerCC32XX_PIN11 = PIN_11, + /*! PIN_12 */ + PowerCC32XX_PIN12 = PIN_12, + /*! PIN_13 */ + PowerCC32XX_PIN13 = PIN_13, + /*! PIN_14 */ + PowerCC32XX_PIN14 = PIN_14, + /*! PIN_15 */ + PowerCC32XX_PIN15 = PIN_15, + /*! PIN_16 */ + PowerCC32XX_PIN16 = PIN_16, + /*! PIN_17 */ + PowerCC32XX_PIN17 = PIN_17, + /*! PIN_18 */ + PowerCC32XX_PIN18 = PIN_18, + /*! PIN_19 */ + PowerCC32XX_PIN19 = PIN_19, + /*! PIN_20 */ + PowerCC32XX_PIN20 = PIN_20, + /*! PIN_21 */ + PowerCC32XX_PIN21 = PIN_21, + /*! PIN_29 */ + PowerCC32XX_PIN29 = 0x1C, + /*! PIN_30 */ + PowerCC32XX_PIN30 = 0x1D, + /*! PIN_45 */ + PowerCC32XX_PIN45 = PIN_45, + /*! PIN_50 */ + PowerCC32XX_PIN50 = PIN_50, + /*! PIN_52 */ + PowerCC32XX_PIN52 = PIN_52, + /*! PIN_53 */ + PowerCC32XX_PIN53 = PIN_53, + /*! PIN_55 */ + PowerCC32XX_PIN55 = PIN_55, + /*! PIN_57 */ + PowerCC32XX_PIN57 = PIN_57, + /*! PIN_58 */ + PowerCC32XX_PIN58 = PIN_58, + /*! PIN_59 */ + PowerCC32XX_PIN59 = PIN_59, + /*! PIN_60 */ + PowerCC32XX_PIN60 = PIN_60, + /*! PIN_61 */ + PowerCC32XX_PIN61 = PIN_61, + /*! PIN_62 */ + PowerCC32XX_PIN62 = PIN_62, + /*! PIN_63 */ + PowerCC32XX_PIN63 = PIN_63, + /*! PIN_64 */ + PowerCC32XX_PIN64 = PIN_64 +} PowerCC32XX_Pin; + +/*! + * @brief Specify the wakeup sources for LPDS and Shutdown + * + * The wakeup sources for LPDS and Shutdown can be dynamically changed + * at runtime, via PowerCC32XX_configureWakeup(). The application + * should fill a structure of this type, and pass it as the parameter + * to PowerCC32XX_configureWakeup() to specify the new wakeup settings. + */ +typedef struct PowerCC32XX_Wakeup { + /*! Enable GPIO as a wakeup source for LPDS */ + bool enableGPIOWakeupLPDS; + /*! Enable GPIO as a wakeup source for shutdown */ + bool enableGPIOWakeupShutdown; + /*! Enable Network activity as a wakeup source for LPDS */ + bool enableNetworkWakeupLPDS; + /*! + * @brief The GPIO source for wakeup from LPDS + * + * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source + * for LPDS. The GPIO must be specified as one of the following (as + * defined in driverlib/prcm.h): PRCM_LPDS_GPIO2, PRCM_LPDS_GPIO4, + * PRCM_LPDS_GPIO11, PRCM_LPDS_GPIO13, PRCM_LPDS_GPIO17, PRCM_LPDS_GPIO24, + * PRCM_LPDS_GPIO26 + */ + uint32_t wakeupGPIOSourceLPDS; + /*! + * @brief The GPIO trigger type for wakeup from LPDS + * + * Value can be one of the following (defined in driverlib/prcm.h): + * PRCM_LPDS_LOW_LEVEL, PRCM_LPDS_HIGH_LEVEL, + * PRCM_LPDS_FALL_EDGE, PRCM_LPDS_RISE_EDGE + */ + uint32_t wakeupGPIOTypeLPDS; + /*! + * @brief Function to be called when the configured GPIO triggers wakeup + * from LPDS + * + * During LPDS the internal GPIO module is powered off, and special + * periphery logic is used instead to detect the trigger and wake the + * device. No GPIO interrupt service routine will be triggered in this + * case (even if an ISR is configured, and used normally to detect GPIO + * interrupts when not in LPDS). This function can be used in lieu of a + * GPIO ISR, to take specific action upon LPDS wakeup. + * + * A value of NULL indicates no GPIO wakeup function will be called. + * + * An argument for this wakeup function can be specified via + * wakeupGPIOFxnLPDSArg. + * + * Note that this wakeup function will be called as one of the last steps + * in Power_sleep(), after all notifications have been sent out, and after + * pins have been restored to their previous (non-parked) states. + */ + void (*wakeupGPIOFxnLPDS)(uint_least8_t argument); + /*! + * @brief The argument to be passed to wakeupGPIOFxnLPDS() + */ + uint_least8_t wakeupGPIOFxnLPDSArg; + /*! + * @brief The GPIO sources for wakeup from shutdown + * + * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source + * for Shutdown. The GPIO must be specified as one of the following (as + * defined in driverlib/prcm.h): PRCM_HIB_GPIO2, PRCM_HIB_GPIO4, + * PRCM_HIB_GPIO11, PRCM_HIB_GPIO13, PRCM_HIB_GPIO17, PRCM_HIB_GPIO24, + * PRCM_HIB_GPIO26 + */ + uint32_t wakeupGPIOSourceShutdown; + /*! + * @brief The GPIO trigger type for wakeup from shutdown + * + * Value can be one of the following (defined in driverlib/prcm.h): + * PRCM_HIB_LOW_LEVEL, PRCM_HIB_HIGH_LEVEL, + * PRCM_HIB_FALL_EDGE, PRCM_HIB_RISE_EDGE + */ + uint32_t wakeupGPIOTypeShutdown; +} PowerCC32XX_Wakeup; + +/*! + * @cond NODOC + * Internal structure defining Power module state. + */ +typedef struct PowerCC32XX_ModuleState { + List_List notifyList; + uint32_t constraintMask; + uint32_t state; + uint16_t dbRecords[PowerCC32XX_NUMRESOURCES]; + bool enablePolicy; + bool initialized; + uint8_t refCount[PowerCC32XX_NUMRESOURCES]; + uint8_t constraintCounts[PowerCC32XX_NUMCONSTRAINTS]; + Power_PolicyFxn policyFxn; + uint32_t pinType[PowerCC32XX_NUMPINS]; + uint16_t pinDir[PowerCC32XX_NUMPINS]; + uint8_t pinMode[PowerCC32XX_NUMPINS]; + uint16_t stateAntPin29; + uint16_t stateAntPin30; + uint32_t pinLockMask; + PowerCC32XX_Wakeup wakeupConfig; +} PowerCC32XX_ModuleState; +/*! @endcond */ + +/*! + * @brief Function configures wakeup for LPDS and shutdown + * + * This function allows the app to configure the GPIO source and + * type for waking up from LPDS and shutdown and the network host + * as a wakeup source for LPDS. This overwrites any previous + * wakeup settings. + * + * @param wakeup Settings applied to wakeup configuration + */ +void PowerCC32XX_configureWakeup(PowerCC32XX_Wakeup *wakeup); + +/*! OS-specific power policy initialization function */ +void PowerCC32XX_initPolicy(void); + +/*! + * @brief Function to get wakeup configuration settings + * + * This function allows an app to query the current LPDS and shutdown + * wakeup configuration settings. + * + * @param wakeup A PowerCC32XX_Wakeup structure to be written into + */ +void PowerCC32XX_getWakeup(PowerCC32XX_Wakeup *wakeup); + +/*! CC32XX-specific function to query the LPDS park state for a pin */ +PowerCC32XX_ParkState PowerCC32XX_getParkState(PowerCC32XX_Pin pin); + +/*! CC32XX-specific function to restore the LPDS park state for a pin */ +void PowerCC32XX_restoreParkState(PowerCC32XX_Pin pin, + PowerCC32XX_ParkState state); + +/*! CC32XX-specific function to dynamically set the LPDS park state for a pin */ +void PowerCC32XX_setParkState(PowerCC32XX_Pin pin, uint32_t level); + +/*! + * @brief Function to disable IO retention and unlock pin groups following + * exit from Shutdown. + * + * PowerCC32XX_ConfigV1.ioRetentionShutdown can be used to specify locking and + * retention of pin groups during Shutdown. Upon exit from Shutdown, and + * when appropriate, an application can call this function, to + * correspondingly disable IO retention, and unlock the specified pin groups. + * + * @param groupFlags A logical OR of one or more of the following + * flags (defined in driverlib/prcm.h): + * PRCM_IO_RET_GRP_0 - all pins except sFlash and JTAG interface + * PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 + * PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 + * PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 + */ +void PowerCC32XX_disableIORetention(unsigned long groupFlags); + +/*! OS-specific power policy function */ +void PowerCC32XX_sleepPolicy(void); + +/*! + * @brief Software reset of a resource + * + * This function performs a software reset of a resource. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param resourceId resource id + * + * @return Power_SOK on success, + * Power_EINVALIDINPUT if the reseourceId is invalid. + * + */ + int_fast16_t PowerCC32XX_reset(uint_fast16_t resourceId); + +/* \cond */ +#define Power_getPerformanceLevel(void) 0 +#define Power_setPerformanceLevel(level) Power_EFAIL +/* \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_power_PowerCC32XX__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.c new file mode 100755 index 00000000000..22179683457 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.c @@ -0,0 +1,803 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define MAX_DMA_TRANSFER_AMOUNT (1024) + +#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) +#define PAD_RESET_STATE 0xC61 + +void SPICC32XXDMA_close(SPI_Handle handle); +int_fast16_t SPICC32XXDMA_control(SPI_Handle handle, uint_fast16_t cmd, + void *arg); +void SPICC32XXDMA_init(SPI_Handle handle); +SPI_Handle SPICC32XXDMA_open(SPI_Handle handle, SPI_Params *params); +bool SPICC32XXDMA_transfer(SPI_Handle handle, SPI_Transaction *transaction); +void SPICC32XXDMA_transferCancel(SPI_Handle handle); + +/* SPI function table for SPICC32XXDMA implementation */ +const SPI_FxnTable SPICC32XXDMA_fxnTable = { + SPICC32XXDMA_close, + SPICC32XXDMA_control, + SPICC32XXDMA_init, + SPICC32XXDMA_open, + SPICC32XXDMA_transfer, + SPICC32XXDMA_transferCancel +}; + +static const uint32_t mode[] = { + SPI_MODE_MASTER, + SPI_MODE_SLAVE +}; + +/* + * This lookup table is used to configure the DMA channels for the appropriate + * (8bit, 16bit or 32bit) transfer sizes. + * Table for an SPI DMA RX channel. + */ +static const uint32_t dmaRxConfig[] = { + UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_1, + UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_1, + UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_1 +}; + +/* + * This lookup table is used to configure the DMA channels for the appropriate + * (8bit, 16bit or 32bit) transfer sizes. + * Table for an SPI DMA TX channel + */ +static const uint32_t dmaTxConfig[] = { + UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_1, + UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_1, + UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_NONE | UDMA_ARB_1 +}; + +/* + * This lookup table is used to configure the DMA channels for the appropriate + * (8bit, 16bit or 32bit) transfer sizes when either txBuf or rxBuf are NULL. + */ +static const uint32_t dmaNullConfig[] = { + UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1, + UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1, + UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1 +}; + +/* + * ======== blockingTransferCallback ======== + */ +static void blockingTransferCallback(SPI_Handle handle, + SPI_Transaction *transaction) +{ + SPICC32XXDMA_Object *object = handle->object; + + SemaphoreP_post(object->transferComplete); +} + +/* + * ======== configDMA ======== + * This functions configures the transmit and receive DMA channels for a given + * SPI_Handle and SPI_Transaction + */ +static void configDMA(SPICC32XXDMA_Object *object, + SPICC32XXDMA_HWAttrsV1 const *hwAttrs, SPI_Transaction *transaction) +{ + uintptr_t key; + void *buf; + uint32_t channelControlOptions; + uint8_t dataFrameSizeInBytes; + uint8_t optionsIndex; + + /* DMA options used vary according to data size. */ + if (object->dataSize < 9) { + optionsIndex = 0; + dataFrameSizeInBytes = sizeof(uint8_t); + } + else if (object->dataSize < 17) { + optionsIndex = 1; + dataFrameSizeInBytes = sizeof(uint16_t);; + } + else { + optionsIndex = 2; + dataFrameSizeInBytes = sizeof(uint32_t); + } + + /* + * The DMA has a max transfer amount of 1024. If the transaction is + * greater; we must transfer it in chunks. object->amtDataXferred has + * how much data has already been sent. + */ + if ((transaction->count - object->amtDataXferred) > MAX_DMA_TRANSFER_AMOUNT) { + object->currentXferAmt = MAX_DMA_TRANSFER_AMOUNT; + } + else { + object->currentXferAmt = (transaction->count - object->amtDataXferred); + } + + if (transaction->txBuf) { + channelControlOptions = dmaTxConfig[optionsIndex]; + /* + * Add an offset for the amount of data transfered. The offset is + * calculated by: object->amtDataXferred * (dataFrameSizeInBytes). + * This accounts for 8, 16 or 32-bit sized transfers. + */ + buf = (void *) ((uint32_t) transaction->txBuf + + ((uint32_t) object->amtDataXferred * dataFrameSizeInBytes)); + } + else { + channelControlOptions = dmaNullConfig[optionsIndex]; + *hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue; + buf = hwAttrs->scratchBufPtr; + } + + /* Setup the TX transfer characteristics & buffers */ + MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, + channelControlOptions); + MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, + UDMA_ATTR_ALTSELECT); + MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, + UDMA_MODE_BASIC, buf, (void *) (hwAttrs->baseAddr + MCSPI_O_TX0), + object->currentXferAmt); + + if (transaction->rxBuf) { + channelControlOptions = dmaRxConfig[optionsIndex]; + /* + * Add an offset for the amount of data transfered. The offset is + * calculated by: object->amtDataXferred * (dataFrameSizeInBytes). + * This accounts for 8 or 16-bit sized transfers. + */ + buf = (void *) ((uint32_t) transaction->rxBuf + + ((uint32_t) object->amtDataXferred * dataFrameSizeInBytes)); + } + else { + channelControlOptions = dmaNullConfig[optionsIndex]; + buf = hwAttrs->scratchBufPtr; + } + + /* Setup the RX transfer characteristics & buffers */ + MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, + channelControlOptions); + MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, + UDMA_ATTR_ALTSELECT); + MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, + UDMA_MODE_BASIC, (void *) (hwAttrs->baseAddr + MCSPI_O_RX0), buf, + object->currentXferAmt); + + /* A lock is needed because we are accessing shared uDMA memory */ + key = HwiP_disable(); + + MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex); + MAP_uDMAChannelAssign(hwAttrs->txChannelIndex); + + /* Enable DMA to generate interrupt on SPI peripheral */ + MAP_SPIDmaEnable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); + MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); + MAP_SPIIntEnable(hwAttrs->baseAddr, SPI_INT_DMARX); + MAP_SPIWordCountSet(hwAttrs->baseAddr, object->currentXferAmt); + + /* Enable channels & start DMA transfers */ + MAP_uDMAChannelEnable(hwAttrs->txChannelIndex); + MAP_uDMAChannelEnable(hwAttrs->rxChannelIndex); + + HwiP_restore(key); + + MAP_SPIEnable(hwAttrs->baseAddr); + MAP_SPICSEnable(hwAttrs->baseAddr); +} + +/* + * ======== getDmaRemainingXfers ======== + */ +static inline uint32_t getDmaRemainingXfers(SPICC32XXDMA_HWAttrsV1 const *hwAttrs) { + uint32_t controlWord; + tDMAControlTable *controlTable; + + controlTable = MAP_uDMAControlBaseGet(); + controlWord = controlTable[(hwAttrs->rxChannelIndex & 0x3f)].ulControl; + + return (((controlWord & UDMA_CHCTL_XFERSIZE_M) >> 4) + 1); +} + +/* + * ======== getPowerMgrId ======== + */ +static uint16_t getPowerMgrId(uint32_t baseAddr) +{ + switch (baseAddr) { + case GSPI_BASE: + return (PowerCC32XX_PERIPH_GSPI); + case LSPI_BASE: + return (PowerCC32XX_PERIPH_LSPI); + default: + return (~0); + } +} + +/* + * ======== initHw ======== + */ +static void initHw(SPICC32XXDMA_Object *object, + SPICC32XXDMA_HWAttrsV1 const *hwAttrs) +{ + /* + * SPI peripheral should remain disabled until a transfer is requested. + * This is done to prevent the RX FIFO from gathering data from other + * transfers. + */ + MAP_SPICSDisable(hwAttrs->baseAddr); + MAP_SPIDisable(hwAttrs->baseAddr); + MAP_SPIReset(hwAttrs->baseAddr); + + MAP_SPIConfigSetExpClk(hwAttrs->baseAddr, + MAP_PRCMPeripheralClockGet(hwAttrs->spiPRCM), object->bitRate, + mode[object->spiMode], object->frameFormat, + (hwAttrs->csControl | hwAttrs->pinMode | hwAttrs->turboMode | + hwAttrs->csPolarity | ((object->dataSize - 1) << 7))); + + MAP_SPIFIFOEnable(hwAttrs->baseAddr, SPI_RX_FIFO | SPI_TX_FIFO); + MAP_SPIFIFOLevelSet(hwAttrs->baseAddr, object->txFifoTrigger, + object->rxFifoTrigger); +} + +/* + * ======== postNotifyFxn ======== + */ +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg) +{ + SPICC32XXDMA_Object *object = ((SPI_Handle) clientArg)->object; + SPICC32XXDMA_HWAttrsV1 const *hwAttrs = ((SPI_Handle) clientArg)->hwAttrs; + + initHw(object, hwAttrs); + + return (Power_NOTIFYDONE); +} + +/* + * ======== spiHwiFxn ======== + */ +static void spiHwiFxn(uintptr_t arg) +{ + uint32_t intFlags; + SPI_Transaction *msg; + SPICC32XXDMA_Object *object = ((SPI_Handle)arg)->object; + SPICC32XXDMA_HWAttrsV1 const *hwAttrs = ((SPI_Handle)arg)->hwAttrs; + + /* + * Although the DMATX interrupt is not used by this driver, it seems like + * it is still triggering DMA interrupts. The code below will clear & + * disable the interrupt thus reducing the amount of spurious interrupts. + */ + intFlags = MAP_SPIIntStatus(hwAttrs->baseAddr, false); + if (intFlags & SPI_INT_DMATX) { + MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMATX); + MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMATX); + } + + if (MAP_uDMAChannelIsEnabled(hwAttrs->rxChannelIndex)) { + /* DMA has not completed if the channel is still enabled */ + return; + } + + /* RX DMA channel has completed; disable peripheral */ + MAP_SPIDmaDisable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); + MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMARX); + MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); + MAP_SPICSDisable(hwAttrs->baseAddr); + MAP_SPIDisable(hwAttrs->baseAddr); + + if (object->transaction->count - object->amtDataXferred > + MAX_DMA_TRANSFER_AMOUNT) { + /* Data still remaining, configure another DMA transfer */ + object->amtDataXferred += object->currentXferAmt; + + configDMA(object, hwAttrs, object->transaction); + } + else { + /* All data sent; set status, perform callback & return */ + object->transaction->status = SPI_TRANSFER_COMPLETED; + + /* Release constraint since transaction is done */ + Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); + + /* + * Use a temporary transaction pointer in case the callback function + * attempts to perform another SPI_transfer call + */ + msg = object->transaction; + + /* Indicate we are done with this transfer */ + object->transaction = NULL; + + object->transferCallbackFxn((SPI_Handle) arg, msg); + } +} + +/* + * ======== spiPollingTransfer ======== + */ +static inline void spiPollingTransfer(SPICC32XXDMA_Object *object, + SPICC32XXDMA_HWAttrsV1 const *hwAttrs, SPI_Transaction *transaction) +{ + uint8_t increment; + uint32_t dummyBuffer; + size_t transferCount; + void *rxBuf; + void *txBuf; + + if (transaction->rxBuf) { + rxBuf = transaction->rxBuf; + } + else { + rxBuf = hwAttrs->scratchBufPtr; + } + + if (transaction->txBuf) { + txBuf = transaction->txBuf; + } + else { + *hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue; + txBuf = hwAttrs->scratchBufPtr; + } + + if (object->dataSize < 9) { + increment = sizeof(uint8_t); + } + else if (object->dataSize < 17) { + increment = sizeof(uint16_t); + } + else { + increment = sizeof(uint32_t); + } + + transferCount = transaction->count; + + /* + * Start the polling transfer - we MUST set word count to 0; not doing so + * will raise spurious RX interrupts flags (though interrupts are not + * enabled). + */ + MAP_SPIWordCountSet(hwAttrs->baseAddr, 0); + MAP_SPIEnable(hwAttrs->baseAddr); + MAP_SPICSEnable(hwAttrs->baseAddr); + + while (transferCount--) { + if (object->dataSize < 9) { + MAP_SPIDataPut(hwAttrs->baseAddr, *((uint8_t *) txBuf)); + MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long *)&dummyBuffer); + *((uint8_t *) rxBuf) = (uint8_t) dummyBuffer; + } + else if (object->dataSize < 17) { + MAP_SPIDataPut(hwAttrs->baseAddr, *((uint16_t *) txBuf)); + MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long *) &dummyBuffer); + *((uint16_t *) rxBuf) = (uint16_t) dummyBuffer; + } + else { + MAP_SPIDataPut(hwAttrs->baseAddr, *((uint32_t *) txBuf)); + MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long * ) rxBuf); + } + + /* Only increment source & destination if buffers were provided */ + if (transaction->rxBuf) { + rxBuf = (void *) (((uint32_t) rxBuf) + increment); + } + if (transaction->txBuf) { + txBuf = (void *) (((uint32_t) txBuf) + increment); + } + } + + MAP_SPICSDisable(hwAttrs->baseAddr); + MAP_SPIDisable(hwAttrs->baseAddr); +} + +/* + * ======== SPICC32XXDMA_close ======== + */ +void SPICC32XXDMA_close(SPI_Handle handle) +{ + uint32_t padRegister; + SPICC32XXDMA_Object *object = handle->object; + SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + + MAP_SPICSDisable(hwAttrs->baseAddr); + MAP_SPIDisable(hwAttrs->baseAddr); + MAP_SPIFIFODisable(hwAttrs->baseAddr, SPI_RX_FIFO | SPI_TX_FIFO); + + /* Release power dependency on SPI. */ + Power_releaseDependency(getPowerMgrId(hwAttrs->baseAddr)); + Power_unregisterNotify(&(object->notifyObj)); + + if (object->hwiHandle) { + HwiP_delete(object->hwiHandle); + } + if (object->transferComplete) { + SemaphoreP_delete(object->transferComplete); + } + + if (object->dmaHandle) { + UDMACC32XX_close(object->dmaHandle); + } + + /* Restore pin pads to their reset states */ + if (hwAttrs->mosiPin != SPICC32XXDMA_PIN_NO_CONFIG) { + padRegister = (PinToPadGet((hwAttrs->mosiPin) & 0xff)<<2) + + PAD_CONFIG_BASE; + HWREG(padRegister) = PAD_RESET_STATE; + } + if (hwAttrs->misoPin != SPICC32XXDMA_PIN_NO_CONFIG) { + padRegister = (PinToPadGet((hwAttrs->misoPin) & 0xff)<<2) + + PAD_CONFIG_BASE; + HWREG(padRegister) = PAD_RESET_STATE; + } + if (hwAttrs->clkPin != SPICC32XXDMA_PIN_NO_CONFIG) { + padRegister = (PinToPadGet((hwAttrs->clkPin) & 0xff)<<2) + + PAD_CONFIG_BASE; + HWREG(padRegister) = PAD_RESET_STATE; + } + if ((hwAttrs->pinMode == SPI_4PIN_MODE) && + (hwAttrs->csPin != SPICC32XXDMA_PIN_NO_CONFIG)) { + padRegister = (PinToPadGet((hwAttrs->csPin) & 0xff)<<2) + + PAD_CONFIG_BASE; + HWREG(padRegister) = PAD_RESET_STATE; + } + + object->isOpen = false; +} + +/* + * ======== SPICC32XXDMA_control ======== + */ +int_fast16_t SPICC32XXDMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (SPI_STATUS_UNDEFINEDCMD); +} + +/* + * ======== SPICC32XXDMA_init ======== + */ +void SPICC32XXDMA_init(SPI_Handle handle) +{ + UDMACC32XX_init(); +} + +/* + * ======== SPICC32XXDMA_open ======== + */ +SPI_Handle SPICC32XXDMA_open(SPI_Handle handle, SPI_Params *params) +{ + uintptr_t key; + uint16_t pin; + uint16_t mode; + uint8_t powerMgrId; + HwiP_Params hwiParams; + SPICC32XXDMA_Object *object = handle->object; + SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + if (object->isOpen) { + HwiP_restore(key); + + return (NULL); + } + object->isOpen = true; + + HwiP_restore(key); + + /* SPI_TI & SPI_MW are not supported */ + if (params->frameFormat == SPI_TI || params->frameFormat == SPI_MW) { + object->isOpen = false; + + return (NULL); + } + + /* Register power dependency - i.e. power up and enable clock for SPI. */ + powerMgrId = getPowerMgrId(hwAttrs->baseAddr); + if (powerMgrId > PowerCC32XX_NUMRESOURCES) { + object->isOpen = false; + + return (NULL); + } + Power_setDependency(powerMgrId); + Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, + postNotifyFxn, (uintptr_t) handle); + + /* Configure the pins */ + if (hwAttrs->mosiPin != SPICC32XXDMA_PIN_NO_CONFIG) { + pin = (hwAttrs->mosiPin) & 0xff; + mode = (hwAttrs->mosiPin >> 8) & 0xff; + MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); + } + + if (hwAttrs->misoPin != SPICC32XXDMA_PIN_NO_CONFIG) { + pin = (hwAttrs->misoPin) & 0xff; + mode = (hwAttrs->misoPin >> 8) & 0xff; + MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); + } + + if (hwAttrs->clkPin != SPICC32XXDMA_PIN_NO_CONFIG) { + pin = (hwAttrs->clkPin) & 0xff; + mode = (hwAttrs->clkPin >> 8) & 0xff; + MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); + } + + if (hwAttrs->pinMode == SPI_4PIN_MODE) { + if (hwAttrs->csPin != SPICC32XXDMA_PIN_NO_CONFIG) { + pin = (hwAttrs->csPin) & 0xff; + mode = (hwAttrs->csPin >> 8) & 0xff; + MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); + } + } + + object->dmaHandle = UDMACC32XX_open(); + if (object->dmaHandle == NULL) { + SPICC32XXDMA_close(handle); + + return (NULL); + } + + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t) handle; + hwiParams.priority = hwAttrs->intPriority; + object->hwiHandle = HwiP_create(hwAttrs->intNum, spiHwiFxn, &hwiParams); + if (object->hwiHandle == NULL) { + SPICC32XXDMA_close(handle); + + return (NULL); + } + + if (params->transferMode == SPI_MODE_BLOCKING) { + /* + * Create a semaphore to block task execution for the duration of the + * SPI transfer + */ + object->transferComplete = SemaphoreP_createBinary(0); + if (object->transferComplete == NULL) { + SPICC32XXDMA_close(handle); + + return (NULL); + } + + object->transferCallbackFxn = blockingTransferCallback; + } + else { + if (params->transferCallbackFxn == NULL) { + SPICC32XXDMA_close(handle); + + return (NULL); + } + + object->transferCallbackFxn = params->transferCallbackFxn; + } + + object->bitRate = params->bitRate; + object->dataSize = params->dataSize; + object->frameFormat = params->frameFormat; + object->spiMode = params->mode; + object->transaction = NULL; + object->transferMode = params->transferMode; + object->transferTimeout = params->transferTimeout; + + /* SPI FIFO trigger sizes vary based on data frame size */ + if (object->dataSize < 9) { + object->rxFifoTrigger = sizeof(uint8_t); + object->txFifoTrigger = sizeof(uint8_t); + } + else if (object->dataSize < 17) { + object->rxFifoTrigger = sizeof(uint16_t); + object->txFifoTrigger = sizeof(uint16_t); + } + else { + object->rxFifoTrigger = sizeof(uint32_t); + object->txFifoTrigger = sizeof(uint32_t); + } + + initHw(object, hwAttrs); + + return (handle); +} + +/* + * ======== SPICC32XXDMA_transfer ======== + */ +bool SPICC32XXDMA_transfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + uintptr_t key; + uint8_t alignMask; + bool buffersAligned; + SPICC32XXDMA_Object *object = handle->object; + SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + + if ((transaction->count == 0) || + (transaction->rxBuf == NULL && transaction->txBuf == NULL) || + (hwAttrs->scratchBufPtr == NULL && (transaction->rxBuf == NULL || + transaction->txBuf == NULL))) { + return (false); + } + + key = HwiP_disable(); + + /* + * alignMask is used to determine if the RX/TX buffers addresses are + * aligned to the data frame size. + */ + alignMask = (object->rxFifoTrigger - 1); + buffersAligned = ((((uint32_t) transaction->rxBuf & alignMask) == 0) && + (((uint32_t) transaction->txBuf & alignMask) == 0)); + + if (object->transaction) { + HwiP_restore(key); + + return (false); + } + else { + object->transaction = transaction; + object->transaction->status = SPI_TRANSFER_STARTED; + object->amtDataXferred = 0; + object->currentXferAmt = 0; + } + + HwiP_restore(key); + + /* Set constraints to guarantee transaction */ + Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); + + /* Polling transfer if BLOCKING mode & transaction->count < threshold */ + if ((object->transferMode == SPI_MODE_BLOCKING && + transaction->count < hwAttrs->minDmaTransferSize) || !buffersAligned) { + spiPollingTransfer(object, hwAttrs, transaction); + + /* Transaction completed; set status & mark SPI ready */ + object->transaction->status = SPI_TRANSFER_COMPLETED; + object->transaction = NULL; + + Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); + } + else { + /* Perform a DMA backed SPI transfer */ + configDMA(object, hwAttrs, transaction); + + if (object->transferMode == SPI_MODE_BLOCKING) { + if (SemaphoreP_pend(object->transferComplete, + object->transferTimeout) != SemaphoreP_OK) { + /* Timeout occurred; cancel the transfer */ + object->transaction->status = SPI_TRANSFER_FAILED; + SPICC32XXDMA_transferCancel(handle); + + /* + * TransferCancel() performs callback which posts + * transferComplete semaphore. This call consumes this extra post. + */ + SemaphoreP_pend(object->transferComplete, SemaphoreP_NO_WAIT); + + return (false); + } + } + } + + return (true); +} + +/* + * ======== SPICC32XXDMA_transferCancel ======== + */ +void SPICC32XXDMA_transferCancel(SPI_Handle handle) +{ + uintptr_t key; + SPI_Transaction *msg; + SPICC32XXDMA_Object *object = handle->object; + SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + + /* + * There are 2 use cases in which to call transferCancel(): + * 1. The driver is in CALLBACK mode. + * 2. The driver is in BLOCKING mode & there has been a transfer timeout. + */ + if (object->transferMode == SPI_MODE_CALLBACK || + object->transaction->status == SPI_TRANSFER_FAILED) { + + key = HwiP_disable(); + + if (object->transaction == NULL || object->cancelInProgress) { + HwiP_restore(key); + + return; + } + object->cancelInProgress = true; + + /* Prevent interrupt from occurring while canceling the transfer */ + HwiP_disableInterrupt(hwAttrs->intNum); + HwiP_clearInterrupt(hwAttrs->intNum); + + /* Clear DMA configuration */ + MAP_uDMAChannelDisable(hwAttrs->rxChannelIndex); + MAP_uDMAChannelDisable(hwAttrs->txChannelIndex); + + MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMARX); + MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); + MAP_SPIDmaDisable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); + + HwiP_restore(key); + + /* + * Disables peripheral, clears all registers & reinitializes it to + * parameters used in SPI_open() + */ + initHw(object, hwAttrs); + + HwiP_enableInterrupt(hwAttrs->intNum); + + /* + * Calculate amount of data which has already been sent & store + * it in transaction->count + */ + object->transaction->count = object->amtDataXferred + + (object->currentXferAmt - getDmaRemainingXfers(hwAttrs)); + + /* Set status CANCELED if we did not cancel due to timeout */ + if (object->transaction->status == SPI_TRANSFER_STARTED) { + object->transaction->status = SPI_TRANSFER_CANCELED; + } + + /* Release constraint set during transaction */ + Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); + + /* + * Use a temporary transaction pointer in case the callback function + * attempts to perform another SPI_transfer call + */ + msg = object->transaction; + + /* Indicate we are done with this transfer */ + object->transaction = NULL; + object->cancelInProgress = false; + object->transferCallbackFxn(handle, msg); + } +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.h new file mode 100755 index 00000000000..58f64a184cc --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/spi/SPICC32XXDMA.h @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SPICC32XXDMA.h + * + * @brief SPI driver implementation for a CC32XX SPI controller using the + * micro DMA controller. + * + * The SPI header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref SPI.h for a complete description of APIs & example of use. + * + * This SPI driver implementation is designed to operate on a CC32XX SPI + * controller using a micro DMA controller. + * + * ## Frame Formats # + * This SPI controller supports 4 phase & polarity formats. Refer to the device + * specific data sheets & technical reference manuals for specifics on each + * format. + * + * ## SPI Chip Select # + * This SPI controller supports a hardware chip select pin. Refer to the + * device's user manual on how this hardware chip select pin behaves in regards + * to the SPI frame format. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Chip select typeSPI_MASTER modeSPI_SLAVE mode
Hardware chip selectNo action is needed by the application to select the peripheral.See the device documentation on it's chip select requirements.
Software chip selectThe application is responsible to ensure that correct SPI slave is + * selected before performing a SPI_transfer().See the device documentation on it's chip select requirements.
+ * + * ## SPI data frames # + * SPI data frames can be any size from 4-bits to 32-bits. The SPI data + * frame size is set in ::SPI_Params.dataSize passed to SPI_open. + * The SPICC32XXDMA driver implementation makes assumptions on the element + * size of the ::SPI_Transaction txBuf and rxBuf arrays, based on the data + * frame size. If the data frame size is less than or equal to 8 bits, + * txBuf and rxBuf are assumed to be arrays of 8-bit uint8_t elements. + * If the data frame size is greater than 8 bits, but less than or equal + * to 16 bits, txBuf and rxBuf are assumed to be arrays of 16-bit uint16_t + * elements. Otherwise, txBuf and rxBuf are assumed to point to 32-bit + * uint32_t elements. + * + * data frame size | buffer element size | + * -------------- | ------------------- | + * 4-8 bits | uint8_t | + * 9-16 bits | uint16_t | + * 17-32 bits | uint32_t | + * + * Data buffers in transactions (rxBuf & txBuf) must be address aligned + * according to the data frame size. For example, if data frame is 9-bit + * (driver assumes buffers are uint16_t) rxBuf & txBuf must be aligned + * on a 16-bit address boundary, if data frame is 20-bit (driver assumes + * buffers are uint32_t) rxBuf & txBuf must be aligned on a 32-bit address + * boundary. + * + * ## DMA Interrupts # + * This driver is designed to operate with the micro DMA. The micro DMA + * generates an interrupt on the perpheral's interrupt vector. This + * implementation automatically installs a DMA aware hardware ISR to service + * the assigned micro DMA channels. + * + * ## DMA accessible memory # + * As this driver uses uDMA to transfer data/from data buffers, it is the + * responsibility of the application to ensure that these buffers reside in + * memory that is accessible by the DMA. + * + * ## Scratch Buffers # + * A uint32_t scratch buffer is used to allow SPI_transfers where txBuf or + * rxBuf are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer + * of size of the transfer count, a single DMA accessible uint32_t scratch + * buffer is used. When rxBuf is NULL, the uDMA will transfer all the SPI data + * receives into the scratch buffer as a "bit-bucket". When txBuf is NULL, the + * scratch buffer is initialized to defaultTxBufValue so the uDMA will send + * some known value. Each SPI driver instance must have its own scratch buffer. + * + * ## Polling SPI transfers # + * When used in blocking mode small SPI transfers are can be done by polling + * the peripheral & sending data frame-by-frame. This will not block the task + * which requested the transfer, but instead immediately perform the transfer + * & return. The minDmaTransferSize field in the hardware attributes is + * the threshold; if the transaction count is below the threshold a polling + * transfer is performed; otherwise a DMA transfer is done. This is intended + * to reduce the overhead of setting up a DMA transfer to only send a few + * data frames. Keep in mind that during polling transfers the current task + * is still being executed; there is no context switch to another task. + ******************************************************************************* + */ + +#ifndef ti_drivers_spi_SPICC32XXDMA__include +#define ti_drivers_spi_SPICC32XXDMA__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +/** + * @addtogroup SPI_STATUS + * SPICC32XXDMA_STATUS_* macros are command codes only defined in the + * SPICC32XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add SPICC32XXDMA_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup SPI_CMD + * SPICC32XXDMA_CMD_* macros are command codes only defined in the + * SPICC32XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add SPICC32XXDMA_CMD_* macros here */ + +/** @}*/ + +/* + * Macros defining possible SPI signal pin mux options + * + * The lower 8 bits of the macro refer to the pin, offset by 1, to match + * driverlib pin defines. For example, SPICC32XXDMA_PIN_05_CLK & 0xff = 4, + * which equals PIN_05 in driverlib pin.h. By matching the PIN_xx defines in + * driverlib pin.h, we can pass the pin directly to the driverlib functions. + * The upper 8 bits of the macro correspond to the pin mux confg mode + * value for the pin to operate in the SPI mode. + * + * PIN_62 is special for the SDSPI driver when using an SD Boosterpack, + * as PIN_62 doesn't have an assigned SPI function yet the SD Boosterpack + * has it tied to the CS signal. + */ +#define SPICC32XXDMA_PIN_05_CLK 0x0704 /*!< PIN 5 is used for SPI CLK */ +#define SPICC32XXDMA_PIN_06_MISO 0x0705 /*!< PIN 6 is used for MISO */ +#define SPICC32XXDMA_PIN_07_MOSI 0x0706 /*!< PIN 7 is used for MOSI */ +#define SPICC32XXDMA_PIN_08_CS 0x0707 /*!< PIN 8 is used for CS */ +#define SPICC32XXDMA_PIN_45_CLK 0x072C /*!< PIN 45 is used for SPI CLK */ +#define SPICC32XXDMA_PIN_50_CS 0x0931 /*!< PIN 50 is used for CS */ +#define SPICC32XXDMA_PIN_52_MOSI 0x0833 /*!< PIN 52 is used for MOSI */ +#define SPICC32XXDMA_PIN_53_MISO 0x0734 /*!< PIN 53 is used for MISO */ + +/*! + * @brief Indicates a pin is not to be configured by the SPICC32XXDMA driver. + */ +#define SPICC32XXDMA_PIN_NO_CONFIG 0xFFFF + +/* SPI function table pointer */ +extern const SPI_FxnTable SPICC32XXDMA_fxnTable; + +/*! + * @brief SPICC32XXDMA Hardware attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CCWare these definitions are found in: + * - driverlib/prcm.h + * - driverlib/spi.h + * - driverlib/udma.h + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * intPriority is the SPI peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * #if defined(__TI_COMPILER_VERSION__) + * #pragma DATA_ALIGN(scratchBuf, 32) + * #elif defined(__IAR_SYSTEMS_ICC__) + * #pragma data_alignment=32 + * #elif defined(__GNUC__) + * __attribute__ ((aligned (32))) + * #endif + * uint32_t scratchBuf; + * + * const SPICC32XXDMA_HWAttrsV1 SPICC32XXDMAHWAttrs[] = { + * { + * .baseAddr = GSPI_BASE, + * .intNum = INT_GSPI, + * .intPriority = (~0), + * .spiPRCM = PRCM_GSPI, + * .csControl = SPI_HW_CTRL_CS, + * .csPolarity = SPI_CS_ACTIVELOW, + * .pinMode = SPI_4PIN_MODE, + * .turboMode = SPI_TURBO_OFF, + * .scratchBufPtr = &scratchBuf, + * .defaultTxBufValue = 0, + * .rxChannelIndex = UDMA_CH6_GSPI_RX, + * .txChannelIndex = UDMA_CH7_GSPI_TX, + * .minDmaTransferSize = 100, + * .mosiPin = SPICC32XXDMA_PIN_07_MOSI, + * .misoPin = SPICC32XXDMA_PIN_06_MISO, + * .clkPin = SPICC32XXDMA_PIN_05_CLK, + * .csPin = SPICC32XXDMA_PIN_08_CS, + * }, + * ... + * }; + * @endcode + */ +typedef struct SPICC32XXDMA_HWAttrsV1 { + /*! SPICC32XXDMA Peripheral's base address */ + uint32_t baseAddr; + + /*! SPICC32XXDMA Peripheral's interrupt vector */ + uint32_t intNum; + + /*! SPICC32XXDMA Peripheral's interrupt priority */ + uint32_t intPriority; + + /*! SPI PRCM peripheral number */ + uint32_t spiPRCM; + + /*! Specify if chip select line will be controlled by SW or HW */ + uint32_t csControl; + + uint32_t csPolarity; + + /*! Set peripheral to work in 3-pin or 4-pin mode */ + uint32_t pinMode; + + /*! Enable or disable SPI TURBO mode */ + uint32_t turboMode; + + /*! Address of a scratch buffer of size uint32_t */ + uint32_t *scratchBufPtr; + + /*! Default TX value if txBuf == NULL */ + uint32_t defaultTxBufValue; + + /*! uDMA RX channel index */ + uint32_t rxChannelIndex; + + /*! uDMA TX channel index */ + uint32_t txChannelIndex; + + /*! Minimum amout of data to start a uDMA transfer */ + uint32_t minDmaTransferSize; + + /*! GSPI MOSI pin assignment */ + uint16_t mosiPin; + + /*! GSPI MISO pin assignment */ + uint16_t misoPin; + + /*! GSPI CLK pin assignment */ + uint16_t clkPin; + + /*! GSPI CS pin assignment */ + uint16_t csPin; +} SPICC32XXDMA_HWAttrsV1; + +/*! + * @brief SPICC32XXDMA Object + * + * The application must not access any member variables of this structure! + */ +typedef struct SPICC32XXDMA_Object { + HwiP_Handle hwiHandle; + Power_NotifyObj notifyObj; + SemaphoreP_Handle transferComplete; + SPI_CallbackFxn transferCallbackFxn; + SPI_Transaction *transaction; + UDMACC32XX_Handle dmaHandle; + + size_t amtDataXferred; + size_t currentXferAmt; + uint32_t bitRate; + uint32_t dataSize; + uint32_t transferTimeout; + + SPI_Mode spiMode; + SPI_TransferMode transferMode; + SPI_FrameFormat frameFormat; + + bool cancelInProgress; + bool isOpen; + uint8_t rxFifoTrigger; + uint8_t txFifoTrigger; +} SPICC32XXDMA_Object, *SPICC32XXDMA_Handle; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_spi_SPICC32XXDMA__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.c new file mode 100755 index 00000000000..84d7ed5f522 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SPI.c ======== + */ + +#include +#include +#include +#include + +#include +#include + +extern const SPI_Config SPI_config[]; +extern const uint_least8_t SPI_count; + +/* Default SPI parameters structure */ +const SPI_Params SPI_defaultParams = { + SPI_MODE_BLOCKING, /* transferMode */ + SPI_WAIT_FOREVER, /* transferTimeout */ + NULL, /* transferCallbackFxn */ + SPI_MASTER, /* mode */ + 1000000, /* bitRate */ + 8, /* dataSize */ + SPI_POL0_PHA0, /* frameFormat */ + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== SPI_close ======== + */ +void SPI_close(SPI_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== SPI_control ======== + */ +int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, void *controlArg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, controlArg)); +} + +/* + * ======== SPI_init ======== + */ +void SPI_init(void) +{ + uint_least8_t i; + uint_fast8_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + /* Only initialize the first SPI instance, the 2nd instance is accessed via mbed OS */ + for (i = 0; i < /*SPI_count*/1; i++) { + SPI_config[i].fxnTablePtr->initFxn((SPI_Handle)&(SPI_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== SPI_open ======== + */ +SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params) +{ + SPI_Handle handle = NULL; + + if (isInitialized && (index < SPI_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (SPI_Params *) &SPI_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (SPI_Handle)&(SPI_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== SPI_Params_init ======== + */ +void SPI_Params_init(SPI_Params *params) +{ + *params = SPI_defaultParams; +} + +/* + * ======== SPI_transfer ======== + */ +bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + return (handle->fxnTablePtr->transferFxn(handle, transaction)); +} + +/* + * ======== SPI_transferCancel ======== + */ +void SPI_transferCancel(SPI_Handle handle) +{ + handle->fxnTablePtr->transferCancelFxn(handle); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.h new file mode 100755 index 00000000000..650b5ec318c --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/ti_SPI.h @@ -0,0 +1,889 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SPI.h + * + * @brief SPI driver interface + * + * The SPI driver interface provides device independent APIs, data types, + * and macros. The SPI header file should be included in an application as + * follows: + * @code + * #include + * @endcode + * + * # Overview # + * The Serial Peripheral Interface (SPI) driver is a generic, full-duplex + * driver that transmits and receives data on a SPI bus. SPI is sometimes + * called SSI (Synchronous Serial Interface). + * The SPI protocol defines the format of a data transfer over the SPI bus, + * but it leaves flow control, data formatting, and handshaking mechanisms + * to higher-level software layers. + * + * The APIs in this driver serve as an interface to a typical RTOS + * application. Its purpose is to redirect the SPI APIs to specific + * driver implementations which are specified using a pointer to a + * #SPI_FxnTable. The specific SPI implementations are responsible for + * creating all the RTOS specific primitives to allow for thread-safe + * operation. + * + * The SPI driver operates on some key definitions and assumptions: + * - The driver operates transparently from the chip select. Some SPI + * controllers feature a hardware chip select to assert SPI slave + * peripherals. See the specific peripheral implementations on chip + * select requirements. + * + * - The SPI protocol does not account for a built-in handshaking mechanism + * and neither does this SPI driver. Therefore, when operating in + * ::SPI_SLAVE mode, the application must provide such a mechanism to + * ensure that the SPI slave is ready for the SPI master. The SPI slave + * must call SPI_transfer() *before* the SPI master starts transmitting. + * Some example application mechanisms could include: + * - Timed delays on the SPI master to guarantee the SPI slave is ready + * for a SPI transaction. + * - A form of GPIO flow control from the slave to the SPI master to notify + * the master when ready. + * + * # Usage # + * + * To use the SPI driver to send data over the SPI bus, the application + * calls the following APIs: + * - SPI_init(): Initialize the SPI driver. + * - SPI_Params_init(): Initialize a #SPI_Params structure with default + * values. Then change the parameters from non-default values as + * needed. + * - SPI_open(): Open an instance of the SPI driver, passing the + * initialized parameters, or NULL, and an index (described later). + * - SPI_transfer(): Transmit/receive data. This function takes a + * #SPI_Transaction argument that specifies buffers for data to be + * transmitted/received. + * - SPI_close(): De-initialize the SPI instance. + * + * The following code example opens a SPI instance as a master SPI, + * and issues a transaction. + * + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * SPI_Transaction spiTransaction; + * uint8_t transmitBuffer[MSGSIZE]; + * uint8_t receiveBuffer[MSGSIZE]; + * bool transferOK; + * + * SPI_init(); // Initialize the SPI driver + * + * SPI_Params_init(&spiParams); // Initialize SPI parameters + * spiParams.dataSize = 8; // 8-bit data size + * + * spi = SPI_open(Board_SPI0, &spiParams); + * if (spi == NULL) { + * while (1); // SPI_open() failed + * } + * + * // Fill in transmitBuffer + * + * spiTransaction.count = MSGSIZE; + * spiTransaction.txBuf = (void *)transmitBuffer; + * spiTransaction.rxBuf = (void *)receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * while (1); + * } + * @endcode + * + * More details on usage are provided in the following subsections. + * + * ### SPI Driver Configuration # + * + * In order to use the SPI APIs, the application is required + * to provide device-specific SPI configuration in the Board.c file. + * The SPI driver interface defines a configuration data structure: + * + * @code + * typedef struct SPI_Config_ { + * SPI_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } SPI_Config; + * @endcode + * + * The application must declare an array of SPI_Config elements, named + * SPI_config[]. Each element of SPI_config[] must be populated with + * pointers to a device specific SPI driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the SPI peripheral's base address, and + * the MOSI and MISO pins. Each element in SPI_config[] corresponds to + * a SPI instance, and none of the elements should have NULL pointers. + * There is no correlation between the index and the + * peripheral designation (such as SPI0 or SPI1). For example, it is + * possible to use SPI_config[0] for SPI1. + * + * Because the SPI configuration is very device dependent, you will need to + * check the doxygen for the device specific SPI implementation. There you + * will find a description of the SPI hardware attributes. Please also + * refer to the Board.c file of any of your examples to see the SPI + * configuration. + * + * ### Initializing the SPI Driver # + * + * SPI_init() must be called before any other SPI APIs. This function + * iterates through the elements of the SPI_config[] array, calling + * the element's device implementation SPI initialization function. + * + * ### SPI Parameters + * + * The #SPI_Params structure is passed to the SPI_open() call. If NULL + * is passed for the parameters, SPI_open() uses default parameters. + * A #SPI_Params structure is initialized with default values by passing + * it to SPI_Params_init(). + * Some of the SPI parameters are described below. To see brief descriptions + * of all the parameters, see #SPI_Params. + * + * #### SPI Mode + * The SPI driver operates in both SPI master and SPI slave modes. + * Logically, the implementation is identical, however the difference + * between these two modes is driven by hardware. The default mode is + * ::SPI_MASTER, but can be set to slave mode by setting ::SPI_Params.mode + * to ::SPI_SLAVE in the parameters passed to SPI_open(). See + * Master/Slave Modes for further + * details. + * + * #### SPI Transfer Mode + * The SPI driver supports two transfer modes of operation: blocking and + * callback. The transfer mode is determined by the transferMode parameter + * in the SPI_Params data structure. The SPI driver + * defaults to blocking mode, if the application does not set it. + * Once a SPI driver is opened, the only way to change the operation mode + * is to close and re-open the SPI instance with the new transfer mode. + * + * In blocking mode, a task's code execution is blocked until a SPI + * transaction has completed or a timeout has occurred. This ensures + * that only one SPI transfer operates at a given time. Other tasks requesting + * SPI transfers while a transfer is currently taking place will receive + * a FALSE return value. If a timeout occurs the transfer is canceled, the + * task is unblocked & will receive a FALSE return value. The transaction + * count field will have the amount of frames which were transferred + * successfully before the timeout. In blocking mode, transfers cannot be + * performed in software or hardware ISR context. + * + * In callback mode, a SPI transaction functions asynchronously, which + * means that it does not block code execution. After a SPI transaction + * has been completed, the SPI driver calls a user-provided hook function. + * Callback mode is supported in the execution context of tasks and + * hardware interrupt routines. However, if a SPI transaction is + * requested while a transaction is taking place, SPI_transfer() returns + * FALSE. + * + * #### SPI Frame Formats and Data Size + * The SPI driver can configure the device's SPI peripheral to transfer + * data in several SPI format options: SPI (with various polarity and phase + * settings), TI, and Micro-wire. The frame format is set with + * SPI_Params.frameFormat. Some SPI implementations may not support all frame + * formats & the SPI driver will fail to opened. Refer to the device specific + * implementation documentation for details on which frame formats are + * supported. + * + * The smallest single unit of data transmitted onto the SPI bus is called + * a SPI frame and is of size SPI_Params.dataSize. A series of SPI frames + * transmitted/received on a SPI bus is known as a SPI transaction. + * + * ### Opening the SPI Driver # + * After initializing the SPI driver by calling SPI_init(), the application + * can open a SPI instance by calling SPI_open(). This function + * takes an index into the SPI_config[] array, and a SPI parameters data + * structure. The SPI instance is specified by the index of the SPI in + * SPI_config[]. Only one SPI index can be used at a time; + * calling SPI_open() a second time with the same index previously + * passed to SPI_open() will result in an error. You can, + * though, re-use the index if the instance is closed via SPI_close(). + * + * If no SPI_Params structure is passed to SPI_open(), default values are + * used. If the open call is successful, it returns a non-NULL value. + * + * Example opening a SPI driver instance in blocking mode: + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * + * SPI_Params_init(&spiParams); + * spiParams.transferMode = SPI_MODE_BLOCKING; + * spi = SPI_open(Board_SPI0, &spiParams); + * + * if (spi == NULL) { + * // Error opening SPI + * while(1); + * } + * @endcode + * + * Example opening a SPI driver instance in callback mode: + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * + * SPI_Params_init(&spiParams); + * spiParams.transferMode = SPI_MODE_CALLBACK; + * spiParams.transferCallbackFxn = UserCallbackFxn; + * + * spi = SPI_open(Board_SPI0, &spiParams); + * if (spi == NULL) { + * // Error opening SPI + * while (1); + * } + * @endcode + * + * + * ### SPI Transactions # + * + * A SPI transaction consists of a series of SPI frames + * transmitted/received on a SPI bus. A SPI transaction is performed + * using SPI_transfer(). SPI_transfer() accepts a pointer to a + * #SPI_Transaction structure that dictates the quantity of data to be + * sent and received. + * The SPI_Transaction.txBuf and SPI_Transaction.rxBuf are both pointers + * to data buffers. If txBuf is NULL, the driver sends SPI frames with all + * data set to the default value specified in the hardware attributes. If + * rxBuf is NULL, the driver discards all SPI frames received. SPI_transfer() + * of a SPI transaction is performed atomically. + * + * @warning The use of NULL as a sentinel txBuf or rxBuf value to determine + * whether the SPI transaction includes a tx or rx component implies + * that it is not possible to perform a transmit or receive transfer + * directly from/to a buffer with a base address of 0x00000000. To support + * this rare use-case, the application will have to manually copy the + * contents of location 0x00000000 to/from a temporary buffer before/after + * the tx/rx SPI transaction. + * + * When the SPI is opened, the dataSize value determines the element types + * of txBuf and rxBuf. If the dataSize is from 4 to 8 bits, the driver + * assumes the data buffers are of type uint8_t (unsigned char). If the + * dataSize is from 8 to 16 bits, the driver assumes the data buffers are + * of type uint16_t (unsigned short). If the dataSize is greater than + * 16 bits, the driver assumes the data buffers are uint32_t (unsigned long). + * Some SPI driver implementations may not support all data sizes; refer + * to device specific SPI implementation documentation for details on + * what data sizes are supported. + * + * The optional SPI_Transaction.arg variable can only be used when the + * SPI driver has been opened in callback mode. This variable is used to + * pass a user-defined value into the user-defined callback function. + * + * SPI_transfer() always performs full-duplex SPI transactions. This means + * the SPI simultaneously receives data as it transmits data. The application + * is responsible for formatting the data to be transmitted as well as + * determining whether the data received is meaningful. + * Specifics about SPI frame formatting and data sizes are provided in + * device-specific data sheets and technical reference manuals. + * + * The following code snippets perform SPI transactions. + * + * Example transferring 6-bit SPI frames. The transmit and receive + * buffers are of type uint8_t. + * @code + * SPI_Transaction spiTransaction; + * uint8_t transmitBuffer[BUFSIZE]; + * uint8_t receiveBuffer[BUFSIZE]; + * bool transferOK; + * + * SPI_Params_init(&spiParams); + * spiParams.dataSize = 6; + * spi = SPI_open(Board_SPI0, &spiParams); + * ... + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * } + * @endcode + * + * Example transferring 12-bit SPI frames. The transmit and receive + * buffers are of type uint16_t. + * @code + * SPI_Transaction spiTransaction; + * uint16_t transmitBuffer[BUFSIZE]; + * uint16_t receiveBuffer[BUFSIZE]; + * bool transferOK; + * + * SPI_Params_init(&spiParams); + * spiParams.dataSize = 12; + * spi = SPI_open(Board_SPI0, &spiParams); + * ... + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * } + * @endcode + * + * ### Canceling a transaction # + * SPI_transferCancel() is used to cancel a SPI transaction when the driver is + * used in ::SPI_MODE_CALLBACK mode. + * + * Calling this API while no transfer is in progress has no effect. If a + * transfer is in progress, it is canceled and the callback functions is + * called. + * The ::SPI_Status status field in the ::SPI_Transaction structure + * can be examined within the callback to determine if the transaction + * succeeded. + * + * Example: + * @code + * SPI_transferCancel(spi); + * @endcode + * + * + *

Master/Slave Modes

+ * This SPI driver functions in both SPI master and SPI slave modes. + * Logically, the implementation is identical, however the difference between + * these two modes is driven by hardware. As a SPI master, the peripheral is + * in control of the clock signal and therefore will commence communications + * to the SPI slave immediately. As a SPI slave, the SPI driver prepares + * the peripheral to transmit and receive data in a way such that the + * peripheral is ready to transfer data when the SPI master initiates a + * transaction. + * + * ### Asserting on Chip Select + * The SPI protocol requires that the SPI master asserts a SPI slave's chip + * select pin prior to starting a SPI transaction. While this protocol is + * generally followed, various types of SPI peripherals have different + * timing requirements as to when and for how long the chip select pin must + * remain asserted for a SPI transaction. + * + * Commonly, the SPI master uses a hardware chip select to assert and + * de-assert the SPI slave for every data frame. In other cases, a SPI slave + * imposes the requirement of asserting the chip select over several SPI + * data frames. This is generally accomplished by using a regular, + * general-purpose output pin. Due to the complexity of such SPI peripheral + * implementations, this SPI driver has been designed to operate + * transparently to the SPI chip select. When the hardware chip + * select is used, the peripheral automatically selects/enables the + * peripheral. When using a software chip select, the application needs to + * handle the proper chip select and pin configuration. Chip select support + * will vary per SPI peripheral, refer to the device specific implementation + * documentation for details on chip select support. + * + * - _Hardware chip select_ No additional action by the application is + * required. + * - _Software chip select_ The application needs to handle the chip select + * assertion and de-assertion for the proper SPI peripheral. + * + * # Implementation # + * + * This module serves as the main interface for RTOS applications. Its + * purpose is to redirect the module's APIs to specific peripheral + * implementations which are specified using a pointer to a #SPI_FxnTable. + * + * The SPI driver interface module is joined (at link time) to an + * array of SPI_Config data structures named *SPI_config*. + * The SPI_config array is implemented in the application with each entry + * being an instance of a SPI peripheral. Each entry in *SPI_config* contains + * the following: + * - (SPI_FxnTable *) A pointer to a set of functions that implement a + * SPI peripheral. + * - (void *) A data object that is associated with the SPI_FxnTable. + * - (void *) The hardware attributes that are associated with the + * SPI_FxnTable. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_SPI__include +#define ti_drivers_SPI__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @defgroup SPI_CONTROL SPI_control command and status codes + * These SPI macros are reservations for SPI.h + * @{ + */ + +/*! + * Common SPI_control command code reservation offset. + * SPI driver implementations should offset command codes with SPI_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define SPIXYZ_CMD_COMMAND0 SPI_CMD_RESERVED + 0 + * #define SPIXYZ_CMD_COMMAND1 SPI_CMD_RESERVED + 1 + * @endcode + */ +#define SPI_CMD_RESERVED (32) + +/*! + * Common SPI_control status code reservation offset. + * SPI driver implementations should offset status codes with + * SPI_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SPIXYZ_STATUS_ERROR0 SPI_STATUS_RESERVED - 0 + * #define SPIXYZ_STATUS_ERROR1 SPI_STATUS_RESERVED - 1 + * #define SPIXYZ_STATUS_ERROR2 SPI_STATUS_RESERVED - 2 + * @endcode + */ +#define SPI_STATUS_RESERVED (-32) + +/** + * @defgroup SPI_STATUS Status Codes + * SPI_STATUS_* macros are general status codes returned by SPI_control() + * @{ + * @ingroup SPI_CONTROL + */ + +/*! + * @brief Successful status code returned by SPI_control(). + * + * SPI_control() returns SPI_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define SPI_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by SPI_control(). + * + * SPI_control() returns SPI_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define SPI_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by SPI_control() for undefined + * command codes. + * + * SPI_control() returns SPI_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define SPI_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup SPI_CMD Command Codes + * SPI_CMD_* macros are general command codes for SPI_control(). Not all SPI + * driver implementations support these command codes. + * @{ + * @ingroup SPI_CONTROL + */ + +/* Add SPI_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief Wait forever define + */ +#define SPI_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a SPI_open() call. + */ +typedef struct SPI_Config_ *SPI_Handle; + +/*! + * @brief Status codes that are set by the SPI driver. + */ +typedef enum SPI_Status_ { + SPI_TRANSFER_COMPLETED = 0, /*!< SPI transfer completed */ + SPI_TRANSFER_STARTED, /*!< SPI transfer started and in progress */ + SPI_TRANSFER_CANCELED, /*!< SPI transfer was canceled */ + SPI_TRANSFER_FAILED, /*!< SPI transfer failed */ + SPI_TRANSFER_CSN_DEASSERT, /*!< SPI chip select was de-asserted */ + SPI_TRANSFER_PEND_CSN_ASSERT, /*!< SPI transfer is pending until the chip select is asserted */ + SPI_TRANSFER_QUEUED /*!< SPI transfer added to transaction queue */ +} SPI_Status; + +/*! + * @brief + * A ::SPI_Transaction data structure is used with SPI_transfer(). It indicates + * how many ::SPI_FrameFormat frames are sent and received from the buffers + * pointed to txBuf and rxBuf. + * The arg variable is an user-definable argument which gets passed to the + * ::SPI_CallbackFxn when the SPI driver is in ::SPI_MODE_CALLBACK. + */ +typedef struct SPI_Transaction_ { + /* User input (write-only) fields */ + size_t count; /*!< Number of frames for this transaction */ + void *txBuf; /*!< void * to a buffer with data to be transmitted */ + void *rxBuf; /*!< void * to a buffer to receive data */ + void *arg; /*!< Argument to be passed to the callback function */ + + /* User output (read-only) fields */ + SPI_Status status; /*!< Status code set by SPI_transfer */ + + void *nextPtr; /*!< Field used internally by the driver and must + never be accessed by the application. */ +} SPI_Transaction; + +/*! + * @brief The definition of a callback function used by the SPI driver + * when used in ::SPI_MODE_CALLBACK + * + * @param SPI_Handle SPI_Handle + * @param SPI_Transaction* SPI_Transaction* + */ +typedef void (*SPI_CallbackFxn) (SPI_Handle handle, + SPI_Transaction *transaction); +/*! + * @brief + * Definitions for various SPI modes of operation. + */ +typedef enum SPI_Mode_ { + SPI_MASTER = 0, /*!< SPI in master mode */ + SPI_SLAVE = 1 /*!< SPI in slave mode */ +} SPI_Mode; + +/*! + * @brief + * Definitions for various SPI data frame formats. + */ +typedef enum SPI_FrameFormat_ { + SPI_POL0_PHA0 = 0, /*!< SPI mode Polarity 0 Phase 0 */ + SPI_POL0_PHA1 = 1, /*!< SPI mode Polarity 0 Phase 1 */ + SPI_POL1_PHA0 = 2, /*!< SPI mode Polarity 1 Phase 0 */ + SPI_POL1_PHA1 = 3, /*!< SPI mode Polarity 1 Phase 1 */ + SPI_TI = 4, /*!< TI mode (not supported on all + implementations) */ + SPI_MW = 5 /*!< Micro-wire mode (not supported on all + implementations) */ +} SPI_FrameFormat; + +/*! + * @brief + * + * SPI transfer mode determines the whether the SPI controller operates + * synchronously or asynchronously. In ::SPI_MODE_BLOCKING mode SPI_transfer() + * blocks code execution until the SPI transaction has completed. In + * ::SPI_MODE_CALLBACK SPI_transfer() does not block code execution and instead + * calls a ::SPI_CallbackFxn callback function when the transaction has + * completed. + */ +typedef enum SPI_TransferMode_ { + /*! + * SPI_transfer() blocks execution. This mode can only be used when called + * within a Task context + */ + SPI_MODE_BLOCKING, + /*! + * SPI_transfer() does not block code execution and will call a + * ::SPI_CallbackFxn. This mode can be used in a Task, software or hardware + * interrupt context. + */ + SPI_MODE_CALLBACK +} SPI_TransferMode; + +/*! + * @brief SPI Parameters + * + * SPI Parameters are used to with the SPI_open() call. Default values for + * these parameters are set using SPI_Params_init(). + * + * @sa SPI_Params_init() + */ +typedef struct SPI_Params_ { + SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ + uint32_t transferTimeout; /*!< Transfer timeout in system + ticks */ + SPI_CallbackFxn transferCallbackFxn;/*!< Callback function pointer */ + SPI_Mode mode; /*!< Master or Slave mode */ + uint32_t bitRate; /*!< SPI bit rate in Hz */ + uint32_t dataSize; /*!< SPI data frame size in bits */ + SPI_FrameFormat frameFormat; /*!< SPI frame format */ + void *custom; /*!< Custom argument used by driver + implementation */ +} SPI_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_close(). + */ +typedef void (*SPI_CloseFxn) (SPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_control(). + */ +typedef int_fast16_t (*SPI_ControlFxn) (SPI_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_init(). + */ +typedef void (*SPI_InitFxn) (SPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_open(). + */ +typedef SPI_Handle (*SPI_OpenFxn) (SPI_Handle handle, SPI_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_transfer(). + */ +typedef bool (*SPI_TransferFxn) (SPI_Handle handle, + SPI_Transaction *transaction); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_transferCancel(). + */ +typedef void (*SPI_TransferCancelFxn) (SPI_Handle handle); + +/*! + * @brief The definition of a SPI function table that contains the + * required set of functions to control a specific SPI driver + * implementation. + */ +typedef struct SPI_FxnTable_ { + /*! Function to close the specified peripheral */ + SPI_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + SPI_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + SPI_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + SPI_OpenFxn openFxn; + + /*! Function to initiate a SPI data transfer */ + SPI_TransferFxn transferFxn; + + /*! Function to cancel SPI data transfer */ + SPI_TransferCancelFxn transferCancelFxn; +} SPI_FxnTable; + +/*! + * @brief SPI Global configuration + * + * The SPI_Config structure contains a set of pointers used to characterize + * the SPI driver implementation. + * + * This structure needs to be defined before calling SPI_init() and it must + * not be changed thereafter. + * + * @sa SPI_init() + */ +typedef struct SPI_Config_ { + /*! Pointer to a table of driver-specific implementations of SPI APIs */ + SPI_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SPI_Config; + +/*! + * @brief Function to close a SPI peripheral specified by the SPI handle + * + * @pre SPI_open() has to be called first. + * + * @param handle A SPI handle returned from SPI_open() + * + * @sa SPI_open() + */ +extern void SPI_close(SPI_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * SPI_Handle. + * + * Commands for SPI_control can originate from SPI.h or from implementation + * specific SPI*.h (_SPICC26XX.h_, _SPIMSP432.h_, etc.. ) files. + * While commands from SPI.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific SPI*.h files add + * unique driver capabilities but are not API portable across all SPI driver + * implementations. + * + * Commands supported by SPI.h follow a SPI_CMD_\ naming + * convention.
+ * Commands supported by SPI*.h follow a SPI*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref SPI_CMD "SPI_control command codes" for command codes. + * + * See @ref SPI_STATUS "SPI_control return status codes" for status codes. + * + * @pre SPI_open() has to be called first. + * + * @param handle A SPI handle returned from SPI_open() + * + * @param cmd SPI.h or SPI*.h commands. + * + * @param controlArg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa SPI_open() + */ +extern int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, + void *controlArg); + +/*! + * @brief This function initializes the SPI module. + * + * @pre The SPI_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other SPI driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void SPI_init(void); + +/*! + * @brief This function opens a given SPI peripheral. + * + * @pre SPI controller has been initialized using SPI_init() + * + * @param index Logical peripheral number for the SPI indexed into + * the SPI_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A SPI_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa SPI_init() + * @sa SPI_close() + */ +extern SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params); + +/*! + * @brief Function to initialize the SPI_Params struct to its defaults + * + * @param params An pointer to SPI_Params structure for + * initialization + * + * Defaults values are: + * transferMode = SPI_MODE_BLOCKING + * transferTimeout = SPI_WAIT_FOREVER + * transferCallbackFxn = NULL + * mode = SPI_MASTER + * bitRate = 1000000 (Hz) + * dataSize = 8 (bits) + * frameFormat = SPI_POL0_PHA0 + */ +extern void SPI_Params_init(SPI_Params *params); + +/*! + * @brief Function to perform SPI transactions + * + * If the SPI is in ::SPI_MASTER mode, it will immediately start the + * transaction. If the SPI is in ::SPI_SLAVE mode, it prepares the driver for + * a transaction with a SPI master device. The device will then wait until + * the master begins the transfer. + * + * In ::SPI_MODE_BLOCKING, %SPI_transfer() will block task execution until the + * transaction has completed or a timeout has occurred. + * + * In ::SPI_MODE_CALLBACK, %SPI_transfer() does not block task execution, but + * calls a ::SPI_CallbackFxn once the transfer has finished. This makes + * %SPI_tranfer() safe to be used within a Task, software or hardware + * interrupt context. + * + * From calling %SPI_transfer() until transfer completion, the SPI_Transaction + * structure must stay persistent and must not be altered by application code. + * It is also forbidden to modify the content of the SPI_Transaction.txBuffer + * during a transaction, even though the physical transfer might not have + * started yet. Doing this can result in data corruption. This is especially + * important for slave operations where %SPI_transfer() might be called a long + * time before the actual data transfer begins. + * + * @param handle A SPI_Handle + * + * @param transaction A pointer to a SPI_Transaction. All of the fields within + * transaction except SPI_Transaction.count and + * SPI_Transaction.status are WO (write-only) unless + * otherwise noted in the driver implementations. If a + * transaction timeout has occurred, SPI_Transaction.count + * will contain the number of frames that were transferred. + * Neither is it allowed to modify the transaction object nor + * the content of SPI_Transaction.txBuffer until the transfer + * has completed. + * + * @return true if started successfully; else false + * + * @sa SPI_open + * @sa SPI_transferCancel + */ +extern bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction); + +/*! + * @brief Function to cancel SPI transactions + * + * In ::SPI_MODE_BLOCKING, SPI_transferCancel has no effect. + * + * In ::SPI_MODE_CALLBACK, SPI_transferCancel() will stop an SPI transfer if + * if one is in progress. + * If a transaction was in progress, its callback function will be called + * in context from which this API is called from. The ::SPI_CallbackFxn + * function can determine if the transaction was successful or not by reading + * the ::SPI_Status status value in the ::SPI_Transaction structure. + * + * @param handle A SPI_Handle + * + * @sa SPI_open + * @sa SPI_transfer + */ +extern void SPI_transferCancel(SPI_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SPI__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.c new file mode 100755 index 00000000000..970ae162263 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2015, 2017 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== List.c ======== + */ +#include +#include + +#include +#include +#include + +/* + * ======== List_clearList ======== + */ +void List_clearList(List_List *list) +{ + uintptr_t key; + + key = HwiP_disable(); + + list->head = list->tail = NULL; + + HwiP_restore(key); +} + + + +/* + * ======== List_get ======== + */ +List_Elem *List_get(List_List *list) +{ + List_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = list->head; + + /* See if the List was empty */ + if (elem != NULL) { + list->head = elem->next; + if (elem->next != NULL) { + elem->next->prev = NULL; + } + else { + list->tail = NULL; + } + } + + HwiP_restore(key); + + return (elem); +} + + +/* + * ======== List_insert ======== + */ +void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) +{ + uintptr_t key; + + key = HwiP_disable(); + + newElem->next = curElem; + newElem->prev = curElem->prev; + if (curElem->prev != NULL) { + curElem->prev->next = newElem; + } + else { + list->head = newElem; + } + curElem->prev = newElem; + + HwiP_restore(key); +} + + +/* + * ======== List_put ======== + */ +void List_put(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = NULL; + elem->prev = list->tail; + if (list->tail != NULL) { + list->tail->next = elem; + } + else { + list->head = elem; + } + + list->tail = elem; + + HwiP_restore(key); +} + +/* + * ======== List_putHead ======== + */ +void List_putHead(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = list->head; + elem->prev = NULL; + if (list->head != NULL) { + list->head->prev = elem; + } + else { + list->tail = elem; + } + + list->head = elem; + + HwiP_restore(key); +} + +/* + * ======== List_remove ======== + */ +void List_remove(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + /* Handle the case where the elem to remove is the last one */ + if (elem->next == NULL) { + list->tail = elem->prev; + } + else { + elem->next->prev = elem->prev; + } + + /* Handle the case where the elem to remove is the first one */ + if (elem->prev == NULL) { + list->head = elem->next; + } + else { + elem->prev->next = elem->next; + } + + HwiP_restore(key); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.h new file mode 100755 index 00000000000..db99729a8c9 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/List.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file List.h + * + * @brief Linked List interface for use in drivers + * + * This module provides simple doubly-link list implementation. There are two + * main structures: + * - ::List_List: The structure that holds the start of a linked list. There + * is no API to create one. It is up to the driver to provide the structure + * itself. + * - ::List_Elem: The structure that must be in the structure that is placed + * onto a linked list. Generally it is the first field in the structure. For + * example: + * @code + * typedef struct MyStruct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * @endcode + * + * The following shows how to create a linked list with three elements. + * + * @code + * + denotes null-terminated + * _______ _______ _______ _______ + * |_______|----->|_______|----->|_______|--->|_______|--//---, + * ,----|_______| ,-|_______|<-----|_______|<---|_______|<-//-, + + * | List + elem elem elem | + * |_____________________________________________________________| + * @endcode + * + * The APIs ::List_get, ::List_put, and ::List_putHead are + * atomic. The other APIs are not necessarily atomic. In other words, when + * traversing a linked list, it is up to the application to provide + * thread-safety (e.g. HwiP_disable/restore or MutexP_pend/post). + * + * Initializing and adding an element to the tail and removing it + * @code + * typedef struct MyStruct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * + * List_List list; + * MyStruct foo; + * MyStruct *bar; + * + * List_clearList(&list); + * List_put(&list, (List_Elem *)&foo); + * bar = (MyStruct *)List_get(&list); + * @endcode + * + * The ::List_put and ::List_get APIs are used to maintain a first-in first-out + * (FIFO) linked list. + * + * The ::List_putHead and ::List_get APIs are used to maintain a last-in first-out + * (LIFO) linked list. + * + * Traversing a list from head to tail. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_head(&list); temp != NULL; temp = List_next(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * Traversing a list from tail to head. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_tail(&list); temp != NULL; temp = List_prev(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_utils_List__include +#define ti_drivers_utils_List__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef struct List_Elem { + struct List_Elem *next; + struct List_Elem *prev; +} List_Elem; + +typedef struct List_List { + List_Elem *head; + List_Elem *tail; +} List_List; + +/*! + * @brief Function to initialize the contents of a List_List + * + * @param list Pointer to a List_List structure that will be used to + * maintain a linked list + */ +extern void List_clearList(List_List *list); + +/*! + * @brief Function to test whether a linked list is empty + * + * @param list A pointer to a linked list + * + * @return true if empty, false if not empty + */ +static inline bool List_empty(List_List *list) +{ + return (list->head == NULL); +} + +/*! + * @brief Function to atomically get the first elem in a linked list + * + * @param list A pointer to a linked list + * + * @return Pointer the first elem in the linked list or NULL if empty + */ +extern List_Elem *List_get(List_List *list); + +/*! + * @brief Function to return the head of a linked list + * + * This function does not remove the head, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the first elem in the linked list or NULL if empty + */ +static inline List_Elem *List_head(List_List *list) +{ + return (list->head); +} + +/*! + * @brief Function to insert an elem into a linked list + * + * @param list A pointer to the linked list + * + * @param newElem New elem to insert + * + * @param curElem Elem to insert the newElem in front of. + * This value cannot be NULL. + */ +extern void List_insert(List_List *list, List_Elem *newElem, + List_Elem *curElem); + +/*! + * @brief Function to return the next elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * next one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the next elem in linked list or NULL if at the end + */ +static inline List_Elem *List_next(List_Elem *elem) +{ + return (elem->next); +} + +/*! + * @brief Function to return the prev elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * prev one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the prev elem in linked list or NULL if at the beginning + */ +static inline List_Elem *List_prev(List_Elem *elem) +{ + return (elem->prev); +} + +/*! + * @brief Function to atomically put an elem onto the end of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the end of the linked list + */ +extern void List_put(List_List *list, List_Elem *elem); + +/*! + * @brief Function to atomically put an elem onto the head of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the beginning of the linked list + */ +extern void List_putHead(List_List *list, List_Elem *elem); + +/*! + * @brief Function to remove an elem from a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to be removed from a linked list + */ +extern void List_remove(List_List *list, List_Elem *elem); + +/*! + * @brief Function to return the tail of a linked list + * + * This function does not remove the tail, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the last elem in the linked list or NULL if empty + */ +static inline List_Elem *List_tail(List_List *list) +{ + return (list->tail); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_List__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.c new file mode 100755 index 00000000000..ace4f012c59 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* + * ======== RingBuf_construct ======== + */ +void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, + size_t bufSize) +{ + object->buffer = bufPtr; + object->length = bufSize; + object->count = 0; + object->head = bufSize - 1; + object->tail = 0; + object->maxCount = 0; +} + +/* + * ======== RingBuf_get ======== + */ +int RingBuf_get(RingBuf_Handle object, unsigned char *data) +{ + unsigned int key; + + key = HwiP_disable(); + + if (!object->count) { + HwiP_restore(key); + return -1; + } + + *data = object->buffer[object->tail]; + object->tail = (object->tail + 1) % object->length; + object->count--; + + HwiP_restore(key); + + return (object->count); +} + +/* + * ======== RingBuf_getCount ======== + */ +int RingBuf_getCount(RingBuf_Handle object) +{ + return (object->count); +} + +/* + * ======== RingBuf_isFull ======== + */ +bool RingBuf_isFull(RingBuf_Handle object) +{ + return (object->count == object->length); +} + +/* + * ======== RingBuf_getMaxCount ======== + */ +int RingBuf_getMaxCount(RingBuf_Handle object) +{ + return (object->maxCount); +} + +/* + * ======== RingBuf_peek ======== + */ +int RingBuf_peek(RingBuf_Handle object, unsigned char *data) +{ + unsigned int key; + int retCount; + + key = HwiP_disable(); + + *data = object->buffer[object->tail]; + retCount = object->count; + + HwiP_restore(key); + + return (retCount); +} + +/* + * ======== RingBuf_put ======== + */ +int RingBuf_put(RingBuf_Handle object, unsigned char data) +{ + unsigned int key; + unsigned int next; + + key = HwiP_disable(); + + if (object->count != object->length) { + next = (object->head + 1) % object->length; + object->buffer[next] = data; + object->head = next; + object->count++; + object->maxCount = (object->count > object->maxCount) ? + object->count : + object->maxCount; + } + else { + + HwiP_restore(key); + return (-1); + } + + HwiP_restore(key); + + return (object->count); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.h new file mode 100755 index 00000000000..29e8c82433e --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/utils/RingBuf.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_uart_RingBuf__include +#define ti_drivers_uart_RingBuf__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef struct RingBuf_Object { + unsigned char *buffer; + size_t length; + size_t count; + size_t head; + size_t tail; + size_t maxCount; +} RingBuf_Object, *RingBuf_Handle; + +/*! + * @brief Initialize circular buffer + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param bufPtr Pointer to data buffer to be used for the circular buffer. + * The buffer is NOT stored in RingBuf_Object. + * + * @param bufSize The size of bufPtr in number of unsigned chars. + */ +void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, + size_t bufSize); + +/*! + * @brief Get an unsigned char from the end of the circular buffer and remove + * it. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. + * + * @return Number of unsigned chars on the buffer after taking it out + * of the circular buffer. If it returns -1, the circular + * buffer was already empty and data is invalid. + */ +int RingBuf_get(RingBuf_Handle object, unsigned char *data); + +/*! + * @brief Get the number of unsigned chars currently stored on the circular + * buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return Number of unsigned chars on the circular buffer. + */ +int RingBuf_getCount(RingBuf_Handle object); + +/*! + * @brief Function to determine if the circular buffer is full or not. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return true if circular buffer is full, else false. + */ +bool RingBuf_isFull(RingBuf_Handle object); + +/*! + * @brief A high-water mark indicating the largest number of unsigned chars + * stored on the circular buffer since it was constructed. + * + * @return Get the largest number of unsigned chars that were at one + * point in the circular buffer. + */ +int RingBuf_getMaxCount(RingBuf_Handle object); + +/*! + * @brief Get an unsigned char from the end of the circular buffer without + * removing it. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. This function does not + * remove the data from the circular buffer. Do not evaluate + * data if the count returned is equal to 0. + * + * @return Number of unsigned chars on the circular buffer. If the + * number != 0, then data will contain the unsigned char at the + * end of the circular buffer. + */ +int RingBuf_peek(RingBuf_Handle object, unsigned char *data); + +/*! + * @brief Put an unsigned char into the end of the circular buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data unsigned char to be placed at the end of the circular + * buffer. + * + * @return Number of unsigned chars on the buffer after it was added, + * or -1 if it's already full. + */ +int RingBuf_put(RingBuf_Handle object, unsigned char data); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart_RingBuf__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slneterr.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slneterr.h new file mode 100755 index 00000000000..56e09fb5e35 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slneterr.h @@ -0,0 +1,674 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#ifndef __SL_NET_ERR_H__ +#define __SL_NET_ERR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup SlNetErr SlNetErr group + + \short Provide BSD and proprietary errors + +*/ +/*! + + \addtogroup SlNetErr + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +#define SLNETERR_RET_CODE_OK (0L) /**< Success */ + +#define SLNETERR_GENERAL_DEVICE (-6L) /**< General device error */ + +/* BSD SOCKET ERRORS CODES */ + +#define SLNETERR_BSD_SOC_ERROR (-1L) /**< Failure */ +#define SLNETERR_BSD_ENXIO (-6L) /**< No such device or address */ +#define SLNETERR_BSD_INEXE (-8L) /**< socket command in execution */ +#define SLNETERR_BSD_EBADF (-9L) /**< Bad file number */ +#define SLNETERR_BSD_ENSOCK (-10L) /**< The system limit on the total number of open socket, has been reached */ +#define SLNETERR_BSD_EAGAIN (-11L) /**< Try again */ +#define SLNETERR_BSD_EWOULDBLOCK SLNETERR_BSD_EAGAIN +#define SLNETERR_BSD_ENOMEM (-12L) /**< Out of memory */ +#define SLNETERR_BSD_EACCES (-13L) /**< Permission denied */ +#define SLNETERR_BSD_EFAULT (-14L) /**< Bad address */ +#define SLNETERR_BSD_ECLOSE (-15L) /**< close socket operation failed to transmit all queued packets */ +#define SLNETERR_BSD_EALREADY_ENABLED (-21L) /**< Transceiver - Transceiver already ON. there could be only one */ +#define SLNETERR_BSD_EINVAL (-22L) /**< Invalid argument */ +#define SLNETERR_BSD_EAUTO_CONNECT_OR_CONNECTING (-69L) /**< Transceiver - During connection, connected or auto mode started */ +#define SLNETERR_BSD_CONNECTION_PENDING (-72L) /**< Transceiver - Device is connected, disconnect first to open transceiver */ +#define SLNETERR_BSD_EUNSUPPORTED_ROLE (-86L) /**< Transceiver - Trying to start when WLAN role is AP or P2P GO */ +#define SLNETERR_BSD_ENOTSOCK (-88L) /**< Socket operation on non-socket */ +#define SLNETERR_BSD_EDESTADDRREQ (-89L) /**< Destination address required */ +#define SLNETERR_BSD_EMSGSIZE (-90L) /**< Message too long */ +#define SLNETERR_BSD_EPROTOTYPE (-91L) /**< Protocol wrong type for socket */ +#define SLNETERR_BSD_ENOPROTOOPT (-92L) /**< Protocol not available */ +#define SLNETERR_BSD_EPROTONOSUPPORT (-93L) /**< Protocol not supported */ +#define SLNETERR_BSD_ESOCKTNOSUPPORT (-94L) /**< Socket type not supported */ +#define SLNETERR_BSD_EOPNOTSUPP (-95L) /**< Operation not supported on transport endpoint */ +#define SLNETERR_BSD_EAFNOSUPPORT (-97L) /**< Address family not supported by protocol */ +#define SLNETERR_BSD_EADDRINUSE (-98L) /**< Address already in use */ +#define SLNETERR_BSD_EADDRNOTAVAIL (-99L) /**< Cannot assign requested address */ +#define SLNETERR_BSD_ENETUNREACH (-101L) /**< Network is unreachable */ +#define SLNETERR_BSD_ECONNABORTED (-103L) /**< Software caused connection abort */ +#define SLNETERR_BSD_ECONNRESET (-104L) /**< Connection reset by peer */ +#define SLNETERR_BSD_ENOBUFS (-105L) /**< No buffer space available */ +#define SLNETERR_BSD_EOBUFF SLNETERR_BSD_ENOBUFS +#define SLNETERR_BSD_EISCONN (-106L) /**< Transport endpoint is already connected */ +#define SLNETERR_BSD_ENOTCONN (-107L) /**< Transport endpoint is not connected */ +#define SLNETERR_BSD_ESHUTDOWN (-108L) /**< Cannot send after transport endpoint shutdown */ +#define SLNETERR_BSD_ETIMEDOUT (-110L) /**< Connection timed out */ +#define SLNETERR_BSD_ECONNREFUSED (-111L) /**< Connection refused */ +#define SLNETERR_BSD_EHOSTDOWN (-112L) /**< Host is down */ +#define SLNETERR_BSD_EHOSTUNREACH (-113L) /**< No route to host */ +#define SLNETERR_BSD_EALREADY (-114L) /**< Non blocking connect in progress, try again */ + +/* ssl tls security start with -300 offset */ +#define SLNETERR_ESEC_CLOSE_NOTIFY (-300L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_UNEXPECTED_MESSAGE (-310L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_BAD_RECORD_MAC (-320L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_DECRYPTION_FAILED (-321L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_RECORD_OVERFLOW (-322L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_DECOMPRESSION_FAILURE (-330L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_HANDSHAKE_FAILURE (-340L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_NO_CERTIFICATE (-341L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_BAD_CERTIFICATE (-342L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_UNSUPPORTED_CERTIFICATE (-343L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_ILLEGAL_PARAMETER (-347L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_ACCESS_DENIED (-349L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_DECODE_ERROR (-350L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_DECRYPT_ERROR1 (-351L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_EXPORT_RESTRICTION (-360L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_PROTOCOL_VERSION (-370L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_INSUFFICIENT_SECURITY (-371L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_INTERNAL_ERROR (-380L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_USER_CANCELLED (-390L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_NO_RENEGOTIATION (-400L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_UNSUPPORTED_EXTENSION (-410L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_CERTIFICATE_UNOBTAINABLE (-411L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_UNRECOGNIZED_NAME (-412L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_BAD_CERTIFICATE_STATUS_RESPONSE (-413L) /**< ssl/tls alerts */ +#define SLNETERR_ESEC_BAD_CERTIFICATE_HASH_VALUE (-414L) /**< ssl/tls alerts */ + + +/* proprietary secure */ +#define SLNETERR_ESEC_GENERAL (-450L) /**< error secure level general error */ +#define SLNETERR_ESEC_DECRYPT (-451L) /**< error secure level, decrypt recv packet fail */ +#define SLNETERR_ESEC_CLOSED (-452L) /**< secure layer is closed by other size, tcp is still connected */ +#define SLNETERR_ESEC_SNO_VERIFY (-453L) /**< Connected without server verification */ +#define SLNETERR_ESEC_NO_CA_FILE (-454L) /**< error secure level CA file not found */ +#define SLNETERR_ESEC_MEMORY (-455L) /**< error secure level No memory space available */ +#define SLNETERR_ESEC_BAD_CA_FILE (-456L) /**< error secure level bad CA file */ +#define SLNETERR_ESEC_BAD_CERT_FILE (-457L) /**< error secure level bad Certificate file */ +#define SLNETERR_ESEC_BAD_PRIVATE_FILE (-458L) /**< error secure level bad private file */ +#define SLNETERR_ESEC_BAD_DH_FILE (-459L) /**< error secure level bad DH file */ +#define SLNETERR_ESEC_T00_MANY_SSL_OPENED (-460L) /**< MAX SSL Sockets are opened */ +#define SLNETERR_ESEC_DATE_ERROR (-461L) /**< connected with certificate date verification error */ +#define SLNETERR_ESEC_HAND_SHAKE_TIMED_OUT (-462L) /**< connection timed out due to handshake time */ +#define SLNETERR_ESEC_TX_BUFFER_NOT_EMPTY (-463L) /**< cannot start ssl connection while send buffer is full */ +#define SLNETERR_ESEC_RX_BUFFER_NOT_EMPTY (-464L) /**< cannot start ssl connection while recv buffer is full */ +#define SLNETERR_ESEC_SSL_DURING_HAND_SHAKE (-465L) /**< cannot use while in handshaking */ +#define SLNETERR_ESEC_NOT_ALLOWED_WHEN_LISTENING (-466L) /**< the operation is not allowed when listening, do before listen */ +#define SLNETERR_ESEC_CERTIFICATE_REVOKED (-467L) /**< connected but on of the certificates in the chain is revoked */ +#define SLNETERR_ESEC_UNKNOWN_ROOT_CA (-468L) /**< connected but the root CA used to validate the peer is unknown */ +#define SLNETERR_ESEC_WRONG_PEER_CERT (-469L) /**< wrong peer cert (server cert) was received while trying to connect to server */ +#define SLNETERR_ESEC_TCP_DISCONNECTED_UNCOMPLETE_RECORD (-470L) /**< the other side disconnected the TCP layer and didn't send the whole ssl record */ +#define SLNETERR_ESEC_HELLO_VERIFY_ERROR (-471L) /**< Hello verification failed in DTLS */ + +#define SLNETERR_ESEC_BUFFER_E (-632L) /**< output buffer too small or input too large */ +#define SLNETERR_ESEC_ALGO_ID_E (-633L) /**< setting algo id error */ +#define SLNETERR_ESEC_PUBLIC_KEY_E (-634L) /**< setting public key error */ +#define SLNETERR_ESEC_DATE_E (-635L) /**< setting date validity error */ +#define SLNETERR_ESEC_SUBJECT_E (-636L) /**< setting subject name error */ +#define SLNETERR_ESEC_ISSUER_E (-637L) /**< setting issuer name error */ +#define SLNETERR_ESEC_CA_TRUE_E (-638L) /**< setting CA basic constraint true error */ +#define SLNETERR_ESEC_EXTENSIONS_E (-639L) /**< setting extensions error */ +#define SLNETERR_ESEC_ASN_PARSE_E (-640L) /**< ASN parsing error, invalid input */ +#define SLNETERR_ESEC_ASN_VERSION_E (-641L) /**< ASN version error, invalid number */ +#define SLNETERR_ESEC_ASN_GETINT_E (-642L) /**< ASN get big int error, invalid data */ +#define SLNETERR_ESEC_ASN_RSA_KEY_E (-643L) /**< ASN key init error, invalid input */ +#define SLNETERR_ESEC_ASN_OBJECT_ID_E (-644L) /**< ASN object id error, invalid id */ +#define SLNETERR_ESEC_ASN_TAG_NULL_E (-645L) /**< ASN tag error, not null */ +#define SLNETERR_ESEC_ASN_EXPECT_0_E (-646L) /**< ASN expect error, not zero */ +#define SLNETERR_ESEC_ASN_BITSTR_E (-647L) /**< ASN bit string error, wrong id */ +#define SLNETERR_ESEC_ASN_UNKNOWN_OID_E (-648L) /**< ASN oid error, unknown sum id */ +#define SLNETERR_ESEC_ASN_DATE_SZ_E (-649L) /**< ASN date error, bad size */ +#define SLNETERR_ESEC_ASN_BEFORE_DATE_E (-650L) /**< ASN date error, current date before */ +#define SLNETERR_ESEC_ASN_AFTER_DATE_E (-651L) /**< ASN date error, current date after */ +#define SLNETERR_ESEC_ASN_SIG_OID_E (-652L) /**< ASN signature error, mismatched oid */ +#define SLNETERR_ESEC_ASN_TIME_E (-653L) /**< ASN time error, unknown time type */ +#define SLNETERR_ESEC_ASN_INPUT_E (-654L) /**< ASN input error, not enough data */ +#define SLNETERR_ESEC_ASN_SIG_CONFIRM_E (-655L) /**< ASN sig error, confirm failure */ +#define SLNETERR_ESEC_ASN_SIG_HASH_E (-656L) /**< ASN sig error, unsupported hash type */ +#define SLNETERR_ESEC_ASN_SIG_KEY_E (-657L) /**< ASN sig error, unsupported key type */ +#define SLNETERR_ESEC_ASN_DH_KEY_E (-658L) /**< ASN key init error, invalid input */ +#define SLNETERR_ESEC_ASN_NTRU_KEY_E (-659L) /**< ASN ntru key decode error, invalid input */ +#define SLNETERR_ESEC_ASN_CRIT_EXT_E (-660L) /**< ASN unsupported critical extension */ +#define SLNETERR_ESEC_ECC_BAD_ARG_E (-670L) /**< ECC input argument of wrong type */ +#define SLNETERR_ESEC_ASN_ECC_KEY_E (-671L) /**< ASN ECC bad input */ +#define SLNETERR_ESEC_ECC_CURVE_OID_E (-672L) /**< Unsupported ECC OID curve type */ +#define SLNETERR_ESEC_BAD_FUNC_ARG (-673L) /**< Bad function argument provided */ +#define SLNETERR_ESEC_NOT_COMPILED_IN (-674L) /**< Feature not compiled in */ +#define SLNETERR_ESEC_UNICODE_SIZE_E (-675L) /**< Unicode password too big */ +#define SLNETERR_ESEC_NO_PASSWORD (-676L) /**< no password provided by user */ +#define SLNETERR_ESEC_ALT_NAME_E (-677L) /**< alt name size problem, too big */ +#define SLNETERR_ESEC_ASN_NO_SIGNER_E (-688L) /**< ASN no signer to confirm failure */ +#define SLNETERR_ESEC_ASN_CRL_CONFIRM_E (-689L) /**< ASN CRL signature confirm failure */ +#define SLNETERR_ESEC_ASN_CRL_NO_SIGNER_E (-690L) /**< ASN CRL no signer to confirm failure */ +#define SLNETERR_ESEC_ASN_OCSP_CONFIRM_E (-691L) /**< ASN OCSP signature confirm failure */ +#define SLNETERR_ESEC_VERIFY_FINISHED_ERROR (-704L) /**< verify problem on finished */ +#define SLNETERR_ESEC_VERIFY_MAC_ERROR (-705L) /**< verify mac problem */ +#define SLNETERR_ESEC_PARSE_ERROR (-706L) /**< parse error on header */ +#define SLNETERR_ESEC_UNKNOWN_HANDSHAKE_TYPE (-707L) /**< weird handshake type */ +#define SLNETERR_ESEC_SOCKET_ERROR_E (-708L) /**< error state on socket */ +#define SLNETERR_ESEC_SOCKET_NODATA (-709L) /**< expected data, not there */ +#define SLNETERR_ESEC_INCOMPLETE_DATA (-710L) /**< don't have enough data to complete task */ +#define SLNETERR_ESEC_UNKNOWN_RECORD_TYPE (-711L) /**< unknown type in record hdr */ +#define SLNETERR_ESEC_INNER_DECRYPT_ERROR (-712L) /**< error during decryption */ +#define SLNETERR_ESEC_FATAL_ERROR (-713L) /**< recvd alert fatal error */ +#define SLNETERR_ESEC_ENCRYPT_ERROR (-714L) /**< error during encryption */ +#define SLNETERR_ESEC_FREAD_ERROR (-715L) /**< fread problem */ +#define SLNETERR_ESEC_NO_PEER_KEY (-716L) /**< need peer's key */ +#define SLNETERR_ESEC_NO_PRIVATE_KEY (-717L) /**< need the private key */ +#define SLNETERR_ESEC_RSA_PRIVATE_ERROR (-718L) /**< error during rsa priv op */ +#define SLNETERR_ESEC_NO_DH_PARAMS (-719L) /**< server missing DH params */ +#define SLNETERR_ESEC_BUILD_MSG_ERROR (-720L) /**< build message failure */ +#define SLNETERR_ESEC_BAD_HELLO (-721L) /**< client hello malformed */ +#define SLNETERR_ESEC_DOMAIN_NAME_MISMATCH (-722L) /**< peer subject name mismatch */ +#define SLNETERR_ESEC_WANT_READ (-723L) /**< want read, call again */ +#define SLNETERR_ESEC_NOT_READY_ERROR (-724L) /**< handshake layer not ready */ +#define SLNETERR_ESEC_PMS_VERSION_ERROR (-725L) /**< pre m secret version error */ +#define SLNETERR_ESEC_WANT_WRITE (-727L) /**< want write, call again */ +#define SLNETERR_ESEC_BUFFER_ERROR (-728L) /**< malformed buffer input */ +#define SLNETERR_ESEC_VERIFY_CERT_ERROR (-729L) /**< verify cert error */ +#define SLNETERR_ESEC_VERIFY_SIGN_ERROR (-730L) /**< verify sign error */ +#define SLNETERR_ESEC_LENGTH_ERROR (-741L) /**< record layer length error */ +#define SLNETERR_ESEC_PEER_KEY_ERROR (-742L) /**< can't decode peer key */ +#define SLNETERR_ESEC_ZERO_RETURN (-743L) /**< peer sent close notify */ +#define SLNETERR_ESEC_SIDE_ERROR (-744L) /**< wrong client/server type */ +#define SLNETERR_ESEC_NO_PEER_CERT (-745L) /**< peer didn't send key */ +#define SLNETERR_ESEC_ECC_CURVETYPE_ERROR (-750L) /**< Bad ECC Curve Type */ +#define SLNETERR_ESEC_ECC_CURVE_ERROR (-751L) /**< Bad ECC Curve */ +#define SLNETERR_ESEC_ECC_PEERKEY_ERROR (-752L) /**< Bad Peer ECC Key */ +#define SLNETERR_ESEC_ECC_MAKEKEY_ERROR (-753L) /**< Bad Make ECC Key */ +#define SLNETERR_ESEC_ECC_EXPORT_ERROR (-754L) /**< Bad ECC Export Key */ +#define SLNETERR_ESEC_ECC_SHARED_ERROR (-755L) /**< Bad ECC Shared Secret */ +#define SLNETERR_ESEC_NOT_CA_ERROR (-757L) /**< Not a CA cert error */ +#define SLNETERR_ESEC_BAD_PATH_ERROR (-758L) /**< Bad path for opendir */ +#define SLNETERR_ESEC_BAD_CERT_MANAGER_ERROR (-759L) /**< Bad Cert Manager */ +#define SLNETERR_ESEC_OCSP_CERT_REVOKED (-760L) /**< OCSP Certificate revoked */ +#define SLNETERR_ESEC_CRL_CERT_REVOKED (-761L) /**< CRL Certificate revoked */ +#define SLNETERR_ESEC_CRL_MISSING (-762L) /**< CRL Not loaded */ +#define SLNETERR_ESEC_MONITOR_RUNNING_E (-763L) /**< CRL Monitor already running */ +#define SLNETERR_ESEC_THREAD_CREATE_E (-764L) /**< Thread Create Error */ +#define SLNETERR_ESEC_OCSP_NEED_URL (-765L) /**< OCSP need an URL for lookup */ +#define SLNETERR_ESEC_OCSP_CERT_UNKNOWN (-766L) /**< OCSP responder doesn't know */ +#define SLNETERR_ESEC_OCSP_LOOKUP_FAIL (-767L) /**< OCSP lookup not successful */ +#define SLNETERR_ESEC_MAX_CHAIN_ERROR (-768L) /**< max chain depth exceeded */ +#define SLNETERR_ESEC_NO_PEER_VERIFY (-778L) /**< Need peer cert verify Error */ +#define SLNETERR_ESEC_UNSUPPORTED_SUITE (-790L) /**< unsupported cipher suite */ +#define SLNETERR_ESEC_MATCH_SUITE_ERROR (-791L) /**< can't match cipher suite */ + + + +/* WLAN ERRORS CODES*/ + +#define SLNETERR_WLAN_KEY_ERROR (-2049L) +#define SLNETERR_WLAN_INVALID_ROLE (-2050L) +#define SLNETERR_WLAN_PREFERRED_NETWORKS_FILE_LOAD_FAILED (-2051L) +#define SLNETERR_WLAN_CANNOT_CONFIG_SCAN_DURING_PROVISIONING (-2052L) +#define SLNETERR_WLAN_INVALID_SECURITY_TYPE (-2054L) +#define SLNETERR_WLAN_PASSPHRASE_TOO_LONG (-2055L) +#define SLNETERR_WLAN_EAP_WRONG_METHOD (-2057L) +#define SLNETERR_WLAN_PASSWORD_ERROR (-2058L) +#define SLNETERR_WLAN_EAP_ANONYMOUS_LEN_ERROR (-2059L) +#define SLNETERR_WLAN_SSID_LEN_ERROR (-2060L) +#define SLNETERR_WLAN_USER_ID_LEN_ERROR (-2061L) +#define SLNETERR_WLAN_PREFERRED_NETWORK_LIST_FULL (-2062L) +#define SLNETERR_WLAN_PREFERRED_NETWORKS_FILE_WRITE_FAILED (-2063L) +#define SLNETERR_WLAN_ILLEGAL_WEP_KEY_INDEX (-2064L) +#define SLNETERR_WLAN_INVALID_DWELL_TIME_VALUES (-2065L) +#define SLNETERR_WLAN_INVALID_POLICY_TYPE (-2066L) +#define SLNETERR_WLAN_PM_POLICY_INVALID_OPTION (-2067L) +#define SLNETERR_WLAN_PM_POLICY_INVALID_PARAMS (-2068L) +#define SLNETERR_WLAN_WIFI_NOT_CONNECTED (-2069L) +#define SLNETERR_WLAN_ILLEGAL_CHANNEL (-2070L) +#define SLNETERR_WLAN_WIFI_ALREADY_DISCONNECTED (-2071L) +#define SLNETERR_WLAN_TRANSCEIVER_ENABLED (-2072L) +#define SLNETERR_WLAN_GET_NETWORK_LIST_EAGAIN (-2073L) +#define SLNETERR_WLAN_GET_PROFILE_INVALID_INDEX (-2074L) +#define SLNETERR_WLAN_FAST_CONN_DATA_INVALID (-2075L) +#define SLNETERR_WLAN_NO_FREE_PROFILE (-2076L) +#define SLNETERR_WLAN_AP_SCAN_INTERVAL_TOO_LOW (-2077L) +#define SLNETERR_WLAN_SCAN_POLICY_INVALID_PARAMS (-2078L) + +#define SLNETERR_RXFL_OK (0L) /**< O.K */ +#define SLNETERR_RXFL_RANGE_COMPARE_PARAMS_ARE_INVALID (-2079L) +#define SLNETERR_RXFL_RXFL_INVALID_PATTERN_LENGTH (-2080L) /**< requested length for L1/L4 payload matching must not exceed 16 bytes */ +#define SLNETERR_RXFL_ACTION_USER_EVENT_ID_TOO_BIG (-2081L) /**< user action id for host event must not exceed SLNETERR_WLAN_RX_FILTER_MAX_USER_EVENT_ID */ +#define SLNETERR_RXFL_OFFSET_TOO_BIG (-2082L) /**< requested offset for L1/L4 payload matching must not exceed 1535 bytes */ +#define SLNETERR_RXFL_STAT_UNSUPPORTED (-2083L) /**< get rx filters statistics not supported */ +#define SLNETERR_RXFL_INVALID_FILTER_ARG_UPDATE (-2084L) /**< invalid filter args request */ +#define SLNETERR_RXFL_INVALID_SYSTEM_STATE_TRIGGER_FOR_FILTER_TYPE (-2085L) /**< system state not supported for this filter type */ +#define SLNETERR_RXFL_INVALID_FUNC_ID_FOR_FILTER_TYPE (-2086L) /**< function id not supported for this filter type */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_3 (-2087L) /**< filter parent doesn't exist */ +#define SLNETERR_RXFL_OUTPUT_OR_INPUT_BUFFER_LENGTH_TOO_SMALL (-2088L) /**< ! The output buffer length is smaller than required for that operation */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_SOFTWARE_FILTER_NOT_FIT (-2089L) /**< Node filter can't be child of software filter and vice_versa */ +#define SLNETERR_RXFL_DEPENDENCY_IS_NOT_PERSISTENT (-2090L) /**< Dependency filter is not persistent */ +#define SLNETERR_RXFL_RXFL_ALLOCATION_PROBLEM (-2091L) +#define SLNETERR_RXFL_SYSTEM_STATE_NOT_SUPPORTED_FOR_THIS_FILTER (-2092L) /**< System state is not supported */ +#define SLNETERR_RXFL_TRIGGER_USE_REG5_TO_REG8 (-2093L) /**< Only counters 5 - 8 are allowed, for trigger */ +#define SLNETERR_RXFL_TRIGGER_USE_REG1_TO_REG4 (-2094L) /**< Only counters 1 - 4 are allowed, for trigger */ +#define SLNETERR_RXFL_ACTION_USE_REG5_TO_REG8 (-2095L) /**< Only counters 5 - 8 are allowed, for action */ +#define SLNETERR_RXFL_ACTION_USE_REG1_TO_REG4 (-2096L) /**< Only counters 1 - 4 are allowed, for action */ +#define SLNETERR_RXFL_FIELD_SUPPORT_ONLY_EQUAL_AND_NOTEQUAL (-2097L) /**< Rule compare function Id is out of range */ +#define SLNETERR_RXFL_WRONG_MULTICAST_BROADCAST_ADDRESS (-2098L) /**< The address should be of type multicast or broadcast */ +#define SLNETERR_RXFL_THE_FILTER_IS_NOT_OF_HEADER_TYPE (-2099L) /**< The filter should be of header type */ +#define SLNETERR_RXFL_WRONG_COMPARE_FUNC_FOR_BROADCAST_ADDRESS (-2100L) /**< The compare function is not suitable for broadcast address */ +#define SLNETERR_RXFL_WRONG_MULTICAST_ADDRESS (-2101L) /**< The address should be of multicast type */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_IS_NOT_PERSISTENT (-2102L) /**< The dependency filter is not persistent */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_IS_NOT_ENABLED (-2103L) /**< The dependency filter is not enabled */ +#define SLNETERR_RXFL_FILTER_HAS_CHILDS (-2104L) /**< The filter has childs and can't be removed */ +#define SLNETERR_RXFL_CHILD_IS_ENABLED (-2105L) /**< Can't disable filter while the child is enabled */ +#define SLNETERR_RXFL_DEPENDENCY_IS_DISABLED (-2106L) /**< Can't enable filter in case its dependency filter is disabled */ +#define SLNETERR_RXFL_MAC_SEND_MATCHDB_FAILED (-2107L) +#define SLNETERR_RXFL_MAC_SEND_ARG_DB_FAILED (-2108L) +#define SLNETERR_RXFL_MAC_SEND_NODEDB_FAILED (-2109L) +#define SLNETERR_RXFL_MAC_OPERTATION_RESUME_FAILED (-2110L) +#define SLNETERR_RXFL_MAC_OPERTATION_HALT_FAILED (-2111L) +#define SLNETERR_RXFL_NUMBER_OF_CONNECTION_POINTS_EXCEEDED (-2112L) /**< Number of connection points exceeded */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_DEPENDENCY_ACTION_IS_DROP (-2113L) /**< The dependent filter has Drop action, thus the filter can't be created */ +#define SLNETERR_RXFL_FILTER_DO_NOT_EXISTS (-2114L) /**< The filter doesn't exists */ +#define SLNETERR_RXFL_DEPEDENCY_NOT_ON_THE_SAME_LAYER (-2115L) /**< The filter and its dependency must be on the same layer */ +#define SLNETERR_RXFL_NUMBER_OF_ARGS_EXCEEDED (-2116L) /**< Number of arguments exceeded */ +#define SLNETERR_RXFL_ACTION_NO_REG_NUMBER (-2117L) /**< Action require counter number */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_LAYER_DO_NOT_FIT (-2118L) /**< the filter and its dependency should be from the same layer */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_SYSTEM_STATE_DO_NOT_FIT (-2119L) /**< The filter and its dependency system state don't fit */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_2 (-2120L) /**< The parent filter don't exist */ +#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_1 (-2121L) /**< The parent filter is null */ +#define SLNETERR_RXFL_RULE_HEADER_ACTION_TYPE_NOT_SUPPORTED (-2122L) /**< The action type is not supported */ +#define SLNETERR_RXFL_RULE_HEADER_TRIGGER_COMPARE_FUNC_OUT_OF_RANGE (-2123L) /**< The Trigger comparison function is out of range */ +#define SLNETERR_RXFL_RULE_HEADER_TRIGGER_OUT_OF_RANGE (-2124L) /**< The Trigger is out of range */ +#define SLNETERR_RXFL_RULE_HEADER_COMPARE_FUNC_OUT_OF_RANGE (-2125L) /**< The rule compare function is out of range */ +#define SLNETERR_RXFL_FRAME_TYPE_NOT_SUPPORTED (-2126L) /**< ASCII frame type string is illegal */ +#define SLNETERR_RXFL_RULE_FIELD_ID_NOT_SUPPORTED (-2127L) /**< Rule field ID is out of range */ +#define SLNETERR_RXFL_RULE_HEADER_FIELD_ID_ASCII_NOT_SUPPORTED (-2128L) /**< This ASCII field ID is not supported */ +#define SLNETERR_RXFL_RULE_HEADER_NOT_SUPPORTED (-2129L) /**< The header rule is not supported on current release */ +#define SLNETERR_RXFL_RULE_HEADER_OUT_OF_RANGE (-2130L) /**< The header rule is out of range */ +#define SLNETERR_RXFL_RULE_HEADER_COMBINATION_OPERATOR_OUT_OF_RANGE (-2131L) /**< Combination function Id is out of range */ +#define SLNETERR_RXFL_RULE_HEADER_FIELD_ID_OUT_OF_RANGE (-2132L) /**< rule field Id is out of range */ +#define SLNETERR_RXFL_UPDATE_NOT_SUPPORTED (-2133L) /**< Update not supported */ +#define SLNETERR_RXFL_NO_FILTER_DATABASE_ALLOCATE (-2134L) +#define SLNETERR_RXFL_ALLOCATION_FOR_GLOBALS_STRUCTURE_FAILED (-2135L) +#define SLNETERR_RXFL_ALLOCATION_FOR_DB_NODE_FAILED (-2136L) +#define SLNETERR_RXFL_READ_FILE_FILTER_ID_ILLEGAL (-2137L) +#define SLNETERR_RXFL_READ_FILE_NUMBER_OF_FILTER_FAILED (-2138L) +#define SLNETERR_RXFL_READ_FILE_FAILED (-2139L) +#define SLNETERR_RXFL_NO_FILTERS_ARE_DEFINED (-2140L) /**< No filters are defined in the system */ +#define SLNETERR_RXFL_NUMBER_OF_FILTER_EXCEEDED (-2141L) /**< Number of max filters exceeded */ +#define SLNETERR_RXFL_BAD_FILE_MODE (-2142L) +#define SLNETERR_RXFL_FAILED_READ_NVFILE (-2143L) +#define SLNETERR_RXFL_FAILED_INIT_STORAGE (-2144L) +#define SLNETERR_RXFL_CONTINUE_WRITE_MUST_BE_MOD_4 (-2145L) +#define SLNETERR_RXFL_FAILED_LOAD_FILE (-2146L) +#define SLNETERR_RXFL_INVALID_HANDLE (-2147L) +#define SLNETERR_RXFL_FAILED_TO_WRITE (-2148L) +#define SLNETERR_RXFL_OFFSET_OUT_OF_RANGE (-2149L) +#define SLNETERR_RXFL_ALLOC (-2150L) +#define SLNETERR_RXFL_READ_DATA_LENGTH (-2151L) +#define SLNETERR_RXFL_INVALID_FILE_ID (-2152L) +#define SLNETERR_RXFL_FILE_FILTERS_NOT_EXISTS (-2153L) +#define SLNETERR_RXFL_FILE_ALREADY_IN_USE (-2154L) +#define SLNETERR_RXFL_INVALID_ARGS (-2155L) +#define SLNETERR_RXFL_FAILED_TO_CREATE_FILE (-2156L) +#define SLNETERR_RXFL_FS_ALREADY_LOADED (-2157L) +#define SLNETERR_RXFL_UNKNOWN (-2158L) +#define SLNETERR_RXFL_FAILED_TO_CREATE_LOCK_OBJ (-2159L) +#define SLNETERR_RXFL_DEVICE_NOT_LOADED (-2160L) +#define SLNETERR_RXFL_INVALID_MAGIC_NUM (-2161L) +#define SLNETERR_RXFL_FAILED_TO_READ (-2162L) +#define SLNETERR_RXFL_NOT_SUPPORTED (-2163L) +#define SLNETERR_WLAN_INVALID_COUNTRY_CODE (-2164L) +#define SLNETERR_WLAN_NVMEM_ACCESS_FAILED (-2165L) +#define SLNETERR_WLAN_OLD_FILE_VERSION (-2166L) +#define SLNETERR_WLAN_TX_POWER_OUT_OF_RANGE (-2167L) +#define SLNETERR_WLAN_INVALID_AP_PASSWORD_LENGTH (-2168L) +#define SLNETERR_WLAN_PROVISIONING_ABORT_PROVISIONING_ALREADY_STARTED (-2169L) +#define SLNETERR_WLAN_PROVISIONING_ABORT_HTTP_SERVER_DISABLED (-2170L) +#define SLNETERR_WLAN_PROVISIONING_ABORT_PROFILE_LIST_FULL (-2171L) +#define SLNETERR_WLAN_PROVISIONING_ABORT_INVALID_PARAM (-2172L) +#define SLNETERR_WLAN_PROVISIONING_ABORT_GENERAL_ERROR (-2173L) +#define SLNETERR_WLAN_MULTICAST_EXCEED_MAX_ADDR (-2174L) +#define SLNETERR_WLAN_MULTICAST_INVAL_ADDR (-2175L) +#define SLNETERR_WLAN_AP_SCAN_INTERVAL_TOO_SHORT (-2176L) +#define SLNETERR_WLAN_PROVISIONING_CMD_NOT_EXPECTED (-2177L) + + +#define SLNETERR_WLAN_AP_ACCESS_LIST_NO_ADDRESS_TO_DELETE (-2178L) /**< List is empty, no address to delete */ +#define SLNETERR_WLAN_AP_ACCESS_LIST_FULL (-2179L) /**< access list is full */ +#define SLNETERR_WLAN_AP_ACCESS_LIST_DISABLED (-2180L) /**< access list is disabled */ +#define SLNETERR_WLAN_AP_ACCESS_LIST_MODE_NOT_SUPPORTED (-2181L) /**< Trying to switch to unsupported mode */ +#define SLNETERR_WLAN_AP_STA_NOT_FOUND (-2182L) /**< trying to disconnect station which is not connected */ + + + +/* DEVICE ERRORS CODES*/ +#define SLNETERR_SUPPLICANT_ERROR (-4097L) +#define SLNETERR_HOSTAPD_INIT_FAIL (-4098L) +#define SLNETERR_HOSTAPD_INIT_IF_FAIL (-4099L) +#define SLNETERR_WLAN_DRV_INIT_FAIL (-4100L) +#define SLNETERR_MDNS_ENABLE_FAIL (-4103L) /**< mDNS enable failed */ +#define SLNETERR_ROLE_STA_ERR (-4107L) /**< Failure to load MAC/PHY in STA role */ +#define SLNETERR_ROLE_AP_ERR (-4108L) /**< Failure to load MAC/PHY in AP role */ +#define SLNETERR_ROLE_P2P_ERR (-4109L) /**< Failure to load MAC/PHY in P2P role */ +#define SLNETERR_CALIB_FAIL (-4110L) /**< Failure of calibration */ +#define SLNETERR_RESTORE_IMAGE_COMPLETE (-4113L) /**< Return to factory image completed, perform reset */ +#define SLNETERR_UNKNOWN_ERR (-4114L) +#define SLNETERR_GENERAL_ERR (-4115L) /**< General error during init */ +#define SLNETERR_WRONG_ROLE (-4116L) +#define SLNETERR_INCOMPLETE_PROGRAMMING (-4117L) /**< Error during programming, Program new image should be invoked (see sl_FsProgram) */ + + +#define SLNETERR_PENDING_TXRX_STOP_TIMEOUT_EXP (-4118L) /**< Timeout expired before completing all TX/RX */ +#define SLNETERR_PENDING_TXRX_NO_TIMEOUT (-4119L) /**< No Timeout, still have pending TX/RX */ +#define SLNETERR_INVALID_PERSISTENT_CONFIGURATION (-4120L) /**< persistency configuration can only be set to 0 (disabled) or 1 (enabled) */ + + + +/* NETAPP ERRORS CODES*/ +#define SLNETERR_MDNS_CREATE_FAIL (-6145L) /**< mDNS create failed */ +#define SLNETERR_DEVICE_NAME_LEN_ERR (-6146L) /**< Set Dev name error codes */ +#define SLNETERR_DEVICE_NAME_INVALID (-6147L) /**< Set Dev name error codes */ +#define SLNETERR_DOMAIN_NAME_LEN_ERR (-6148L) /**< Set domain name error codes */ +#define SLNETERR_DOMAIN_NAME_INVALID (-6149L) /**< Set domain name error codes */ +#define SLNETERR_NET_APP_DNS_QUERY_NO_RESPONSE (-6150L) /**< DNS query failed, no response */ +#define SLNETERR_NET_APP_DNS_ERROR (-6151L) /**< DNS internal error */ +#define SLNETERR_NET_APP_DNS_NO_SERVER (-6152L) /**< No DNS server was specified */ +#define SLNETERR_NET_APP_DNS_TIMEOUTR (-6153L) /**< mDNS parameters error */ +#define SLNETERR_NET_APP_DNS_QUERY_FAILED (-6154L) /**< DNS query failed; no DNS server sent an 'answer' */ +#define SLNETERR_NET_APP_DNS_BAD_ADDRESS_ERROR (-6155L) /**< Improperly formatted IPv4 or IPv6 address */ +#define SLNETERR_NET_APP_DNS_SIZE_ERROR (-6156L) /**< DNS destination size is too small */ +#define SLNETERR_NET_APP_DNS_MALFORMED_PACKET (-6157L) /**< Improperly formed or corrupted DNS packet received */ +#define SLNETERR_NET_APP_DNS_BAD_ID_ERROR (-6158L) /**< DNS packet from server does not match query ID */ +#define SLNETERR_NET_APP_DNS_PARAM_ERROR (-6159L) /**< Invalid params */ +#define SLNETERR_NET_APP_DNS_SERVER_NOT_FOUND (-6160L) /**< Server not found in Client list of DNS servers */ +#define SLNETERR_NET_APP_DNS_PACKET_CREATE_ERROR (-6161L) /**< Error creating DNS packet */ +#define SLNETERR_NET_APP_DNS_EMPTY_DNS_SERVER_LIST (-6162L) /**< DNS Client's list of DNS servers is empty */ +#define SLNETERR_NET_APP_DNS_SERVER_AUTH_ERROR (-6163L) /**< Server not able to authenticate answer/authority data*/ +#define SLNETERR_NET_APP_DNS_ZERO_GATEWAY_IP_ADDRESS (-6164L) /**< DNS Client IP instance has a zero gateway IP address */ +#define SLNETERR_NET_APP_DNS_MISMATCHED_RESPONSE (-6165L) /**< Server response type does not match the query request*/ +#define SLNETERR_NET_APP_DNS_DUPLICATE_ENTRY (-6166L) /**< Duplicate entry exists in DNS server table */ +#define SLNETERR_NET_APP_DNS_RETRY_A_QUERY (-6167L) /**< SOA status returned; web site only exists as IPv4 */ +#define SLNETERR_NET_APP_DNS_INVALID_ADDRESS_TYPE (-6168L) /**< IP address type (e.g. IPv6L) not supported */ +#define SLNETERR_NET_APP_DNS_IPV6_NOT_SUPPORTED (-6169L) /**< IPv6 disabled */ +#define SLNETERR_NET_APP_DNS_NEED_MORE_RECORD_BUFFER (-6170L) /**< The buffer size is not enough. */ +#define SLNETERR_NET_APP_MDNS_ERROR (-6171L) /**< MDNS internal error. */ +#define SLNETERR_NET_APP_MDNS_PARAM_ERROR (-6172L) /**< MDNS parameters error. */ +#define SLNETERR_NET_APP_MDNS_CACHE_ERROR (-6173L) /**< The Cache size is not enough. */ +#define SLNETERR_NET_APP_MDNS_UNSUPPORTED_TYPE (-6174L) /**< The unsupported resource record type. */ +#define SLNETERR_NET_APP_MDNS_DATA_SIZE_ERROR (-6175L) /**< The data size is too big. */ +#define SLNETERR_NET_APP_MDNS_AUTH_ERROR (-6176L) /**< Attempting to parse too large a data. */ +#define SLNETERR_NET_APP_MDNS_PACKET_ERROR (-6177L) /**< The packet can not add the resource record. */ +#define SLNETERR_NET_APP_MDNS_DEST_ADDRESS_ERROR (-6178L) /**< The destination address error. */ +#define SLNETERR_NET_APP_MDNS_UDP_PORT_ERROR (-6179L) /**< The udp port error. */ +#define SLNETERR_NET_APP_MDNS_NOT_LOCAL_LINK (-6180L) /**< The message that not originate from the local link. */ +#define SLNETERR_NET_APP_MDNS_EXCEED_MAX_LABEL (-6181L) /**< The data exceed the max laber size. */ +#define SLNETERR_NET_APP_MDNS_EXIST_UNIQUE_RR (-6182L) /**< At least one Unqiue record in the cache. */ +#define SLNETERR_NET_APP_MDNS_EXIST_ANSWER (-6183L) /**< At least one answer record in the cache. */ +#define SLNETERR_NET_APP_MDNS_EXIST_SAME_QUERY (-6184L) /**< Exist the same query. */ +#define SLNETERR_NET_APP_MDNS_DUPLICATE_SERVICE (-6185L) /**< Duplicate service. */ +#define SLNETERR_NET_APP_MDNS_NO_ANSWER (-6186L) /**< No response for one-shot query. */ +#define SLNETERR_NET_APP_MDNS_NO_KNOWN_ANSWER (-6187L) /**< No known answer for query. */ +#define SLNETERR_NET_APP_MDNS_NAME_MISMATCH (-6188L) /**< The name mismatch. */ +#define SLNETERR_NET_APP_MDNS_NOT_STARTED (-6189L) /**< MDNS does not start. */ +#define SLNETERR_NET_APP_MDNS_HOST_NAME_ERROR (-6190L) /**< MDNS host name error. */ +#define SLNETERR_NET_APP_MDNS_NO_MORE_ENTRIES (-6191L) /**< No more entries be found. */ +#define SLNETERR_NET_APP_MDNS_SERVICE_TYPE_MISMATCH (-6192L) /**< The service type mismatch */ +#define SLNETERR_NET_APP_MDNS_LOOKUP_INDEX_ERROR (-6193L) /**< Index is bigger than number of services. */ +#define SLNETERR_NET_APP_MDNS_MAX_SERVICES_ERROR (-6194L) +#define SLNETERR_NET_APP_MDNS_IDENTICAL_SERVICES_ERROR (-6195L) +#define SLNETERR_NET_APP_MDNS_EXISTED_SERVICE_ERROR (-6196L) +#define SLNETERR_NET_APP_MDNS_ERROR_SERVICE_NAME_ERROR (-6197L) +#define SLNETERR_NET_APP_MDNS_RX_PACKET_ALLOCATION_ERROR (-6198L) +#define SLNETERR_NET_APP_MDNS_BUFFER_SIZE_ERROR (-6199L) +#define SLNETERR_NET_APP_MDNS_NET_APP_SET_ERROR (-6200L) +#define SLNETERR_NET_APP_MDNS_GET_SERVICE_LIST_FLAG_ERROR (-6201L) +#define SLNETERR_NET_APP_MDNS_MDNS_NO_CONFIGURATION_ERROR (-6202L) +#define SLNETERR_NET_APP_MDNS_STATUS_ERROR (-6203L) +#define SLNETERR_NET_APP_ENOBUFS (-6204L) +#define SLNETERR_NET_APP_DNS_IPV6_REQ_BUT_IPV6_DISABLED (-6205L) /**< trying to issue ipv6 DNS request but ipv6 is disabled */ +#define SLNETERR_NET_APP_DNS_INVALID_FAMILY_TYPE (-6206L) /**< Family type is not ipv4 and not ipv6 */ +#define SLNETERR_NET_APP_DNS_REQ_TOO_BIG (-6207L) /**< DNS request size is too big */ +#define SLNETERR_NET_APP_DNS_ALLOC_ERROR (-6208L) /**< Allocation error */ +#define SLNETERR_NET_APP_DNS_EXECUTION_ERROR (-6209L) /**< Execution error */ +#define SLNETERR_NET_APP_P2P_ROLE_IS_NOT_CONFIGURED (-6210L) /**< role p2p is not configured yet, should be CL or GO in order to execute command */ +#define SLNETERR_NET_APP_INCORECT_ROLE_FOR_APP (-6211L) /**< incorrect role for specific application */ +#define SLNETERR_NET_APP_INCORECT_APP_MASK (-6212L) /**< mask does not match any app */ +#define SLNETERR_NET_APP_MDNS_ALREADY_STARTED (-6213L) /**< mdns application already started */ +#define SLNETERR_NET_APP_HTTP_SERVER_ALREADY_STARTED (-6214L) /**< http server application already started */ + +#define SLNETERR_NET_APP_HTTP_GENERAL_ERROR (-6216L) /**< New error - Http handle request failed */ +#define SLNETERR_NET_APP_HTTP_INVALID_TIMEOUT (-6217L) /**< New error - Http timeout invalid argument */ +#define SLNETERR_NET_APP_INVALID_URN_LENGTH (-6218L) /**< invalid URN length */ +#define SLNETERR_NET_APP_RX_BUFFER_LENGTH (-6219L) /**< size of the requested services is smaller than size of the user buffer */ + + + +/*< NETCFG ERRORS CODES*/ +#define SLNETERR_STATIC_ADDR_SUBNET_ERROR (-8193L) +#define SLNETERR_INCORRECT_IPV6_STATIC_LOCAL_ADDR (-8194L) /**< Ipv6 Local address perfix is wrong */ +#define SLNETERR_INCORRECT_IPV6_STATIC_GLOBAL_ADDR (-8195L) /**< Ipv6 Global address perfix is wrong */ +#define SLNETERR_IPV6_LOCAL_ADDR_SHOULD_BE_SET_FIRST (-8195L) /**< Attempt to set ipv6 global address before ipv6 local address is set */ + + + +/* NETUTIL ERRORS CODES */ +#define SLNETERR_NETUTIL_CRYPTO_GENERAL (-12289L) +#define SLNETERR_NETUTIL_CRYPTO_INVALID_INDEX (-12290L) +#define SLNETERR_NETUTIL_CRYPTO_INVALID_PARAM (-12291L) +#define SLNETERR_NETUTIL_CRYPTO_MEM_ALLOC (-12292L) +#define SLNETERR_NETUTIL_CRYPTO_INVALID_DB_VER (-12293L) +#define SLNETERR_NETUTIL_CRYPTO_UNSUPPORTED_OPTION (-12294L) +#define SLNETERR_NETUTIL_CRYPTO_BUFFER_TOO_SMALL (-12295L) +#define SLNETERR_NETUTIL_CRYPTO_EMPTY_DB_ENTRY (-12296L) +#define SLNETERR_NETUTIL_CRYPTO_NON_TEMPORARY_KEY (-12297L) +#define SLNETERR_NETUTIL_CRYPTO_DB_ENTRY_NOT_FREE (-12298L) +#define SLNETERR_NETUTIL_CRYPTO_CORRUPTED_DB_FILE (-12299L) + + + +/* GENERAL ERRORS CODES*/ +#define SLNETERR_INVALID_OPCODE (-14337L) +#define SLNETERR_INVALID_PARAM (-14338L) +#define SLNETERR_STATUS_ERROR (-14341L) +#define SLNETERR_NVMEM_ACCESS_FAILED (-14342L) +#define SLNETERR_NOT_ALLOWED_NWP_LOCKED (-14343L) /**< Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ + +/* SECURITY ERRORS CODE */ +#define SLNETERR_LOADING_CERTIFICATE_STORE (-28673L) + +/* Device is Locked! Return to Factory Image or Program new + image should be invoked (see sl_FsCtl, sl_FsProgram) */ +#define SLNETERR_DEVICE_LOCKED_SECURITY_ALERT (-28674L) + + + +/* INTERNAL HOST ERRORS CODES*/ + +/* Receive this error in case there are no resources to issue the command + If possible, increase the number of MAX_CONCURRENT_ACTIONS (result in memory increase) + If not, try again later */ +#define SLNETERR_POOL_IS_EMPTY (-2000L) + +/* Receive this error in case a given length for RX buffer was too small. + Receive payload was bigger than the given buffer size. Therefore, payload is cut according to receive size + Recommend to increase buffer size */ +#define SLNETERR_ESMALLBUF (-2001L) + +/* Receive this error in case zero length is supplied to a "get" API + Recommend to supply length according to requested information (view options defines for help) */ +#define SLNETERR_EZEROLEN (-2002L) + +/* User supplied invalid parameter */ +#define SLNETERR_INVALPARAM (-2003L) + +/* Failed to open interface */ +#define SLNETERR_BAD_INTERFACE (-2004L) + +/* API has been aborted due to an error detected by host driver */ +#define SLNETERR_API_ABORTED (-2005L) + +/* Parameters are invalid */ +#define SLNETERR_RET_CODE_INVALID_INPUT (-2006L) + +/* Driver internal error */ +#define SLNETERR_RET_CODE_SELF_ERROR (-2007L) + +/* NWP internal error */ +#define SLNETERR_RET_CODE_NWP_IF_ERROR (-2008L) + +/* malloc error */ +#define SLNETERR_RET_CODE_MALLOC_ERROR (-2009L) + +/* protocol error */ +#define SLNETERR_RET_CODE_PROTOCOL_ERROR (-2010L) + +/* API has been aborted, command is not allowed in device lock state */ +#define SLNETERR_RET_CODE_DEV_LOCKED (-2011L) + +/* SlNetSock_Start cannot be invoked twice */ +#define SLNETERR_RET_CODE_DEV_ALREADY_STARTED (-2012L) + +/* SL Net API is in progress */ +#define SLNETERR_RET_CODE_API_COMMAND_IN_PROGRESS (-2013L) + +/* Provisioning is in progress - */ +#define SLNETERR_RET_CODE_PROVISIONING_IN_PROGRESS (-2014L) + +/* Wrong ping parameters - ping cannot be called with the following parameters: +1. infinite ping packet +2. report only when finished +3. no callback supplied */ +#define SLNETERR_RET_CODE_NET_APP_PING_INVALID_PARAMS (-2015L) + + +/* SlNetSock select already in progress. + this error will be returned if app will try to call + SlNetSock_select blocking when there is already select trigger in progress */ +#define SLNETERR_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR (-2016L) + +#define SLNETERR_RET_CODE_STOP_IN_PROGRESS (-2017L) + + +/* The device has not been started yet */ +#define SLNETERR_RET_CODE_DEV_NOT_STARTED (-2018L) + +/* The event link was not found in the list */ +#define SLNETERR_RET_CODE_EVENT_LINK_NOT_FOUND (-2019L) + +/* Function couldn't find any free space/location */ +#define SLNETERR_RET_CODE_NO_FREE_SPACE (-2020L) + +/* Function couldn't execute correctly */ +#define SLNETERR_RET_CODE_FUNCTION_FAILED (-2021L) + +/* Mutex creation failed */ +#define SLNETERR_RET_CODE_MUTEX_CREATION_FAILED (-2022L) + +/* Function couldn't find the requested resource */ +#define SLNETERR_RET_CODE_COULDNT_FIND_RESOURCE (-2023L) + +/* Interface doesn't support the non mandatory function */ +#define SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN (-2024L) + +/* Socket creation in progress */ +#define SLNETERR_RET_CODE_SOCKET_CREATION_IN_PROGRESS (-2025L) + +/* Unsupported scenario, option or feature */ +#define SLNETERR_RET_CODE_UNSUPPORTED (-2026L) + + +/* sock related API's from SlNetIf_Config_t failed */ +#define SLNETSOCK_ERR_SOCKCREATE_FAILED (-3000L) +#define SLNETSOCK_ERR_SOCKCLOSE_FAILED (-3001L) +#define SLNETSOCK_ERR_SOCKSELECT_FAILED (-3002L) +#define SLNETSOCK_ERR_SOCKSETOPT_FAILED (-3003L) +#define SLNETSOCK_ERR_SOCKGETOPT_FAILED (-3004L) +#define SLNETSOCK_ERR_SOCKRECVFROM_FAILED (-3005L) +#define SLNETSOCK_ERR_SOCKSENDTO_FAILED (-3006L) +#define SLNETSOCK_ERR_SOCKSHUTDOWN_FAILED (-3007L) +#define SLNETSOCK_ERR_SOCKACCEPT_FAILED (-3008L) +#define SLNETSOCK_ERR_SOCKBIND_FAILED (-3009L) +#define SLNETSOCK_ERR_SOCKLISTEN_FAILED (-3000L) +#define SLNETSOCK_ERR_SOCKCONNECT_FAILED (-3001L) +#define SLNETSOCK_ERR_SOCKGETPEERNAME_FAILED (-3002L) +#define SLNETSOCK_ERR_SOCKGETLOCALNAME_FAILED (-3003L) +#define SLNETSOCK_ERR_SOCKRECV_FAILED (-3004L) +#define SLNETSOCK_ERR_SOCKSEND_FAILED (-3005L) +#define SLNETSOCK_ERR_SOCKSTARTSEC_FAILED (-3006L) + +/* util related API's from SlNetIf_Config_t failed */ +#define SLNETUTIL_ERR_UTILGETHOSTBYNAME_FAILED (-3100L) + +/* if related API's from SlNetIf_Config_t failed */ +#define SLNETIF_ERR_IFLOADSECOBJ_FAILED (-3200L) +#define SLNETIF_ERR_IFGETIPADDR_FAILED (-3201L) +#define SLNETIF_ERR_IFGETCONNECTIONSTATUS_FAILED (-3202L) +#define SLNETIF_ERR_IFCREATECONTEXT_FAILED (-3203L) + +/*! + + Close the Doxygen group. + @} + +*/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __SL_NET_ERR_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetif.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetif.h new file mode 100755 index 00000000000..dfb58221578 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetif.h @@ -0,0 +1,642 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#ifndef __SL_NET_IF_H__ +#define __SL_NET_IF_H__ + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup SlNetIf SlNetIf group + + \short Controls standard stack/interface options and capabilities + +*/ +/*! + + \addtogroup SlNetIf + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +/* Interface ID bit pool to be used in interface add and in socket creation */ +#define SLNETIF_ID_1 (1 << 0) //can be used for wifi interface +#define SLNETIF_ID_2 (1 << 1) //can be used for eth interface +#define SLNETIF_ID_3 (1 << 2) +#define SLNETIF_ID_4 (1 << 3) +#define SLNETIF_ID_5 (1 << 4) +#define SLNETIF_ID_6 (1 << 5) +#define SLNETIF_ID_7 (1 << 6) +#define SLNETIF_ID_8 (1 << 7) +#define SLNETIF_ID_9 (1 << 8) +#define SLNETIF_ID_10 (1 << 9) +#define SLNETIF_ID_11 (1 << 10) +#define SLNETIF_ID_12 (1 << 11) +#define SLNETIF_ID_13 (1 << 12) +#define SLNETIF_ID_14 (1 << 13) +#define SLNETIF_ID_15 (1 << 14) +#define SLNETIF_ID_16 (1 << 15) + +/* Maximum interfaces */ +#define SLNETIF_MAX_IF (16) + +/* this macro returns 0 when only one bit is set and a number when it isn't */ +#define ONLY_ONE_BIT_IS_SET(x) (((x > 0) && ((x & (x - 1)) == 0))?true:false) + + +/* Interface connection status bit pool to be used in set interface connection status function */ + +#define SLNETIF_STATUS_DISCONNECTED (0) +#define SLNETIF_STATUS_CONNECTED (1) + +/*! + \brief Interface state bit pool to be used in set interface state function +*/ +typedef enum +{ + SLNETIF_STATE_DISABLE = 0, + SLNETIF_STATE_ENABLE = 1 +} SlNetIfState_e; + +/*! + \brief Address type enum to be used in get ip address function +*/ +typedef enum +{ + SLNETIF_IPV4_ADDR = 0, + SLNETIF_IPV6_ADDR_LOCAL = 1, + SLNETIF_IPV6_ADDR_GLOBAL = 2 +} SlNetIfAddressType_e; + +/* Address config return values that can be retrieved in get ip address function */ +#define SLNETIF_ADDR_CFG_UNKNOWN (0) +#define SLNETIF_ADDR_CFG_DHCP (1) +#define SLNETIF_ADDR_CFG_DHCP_LLA (2) +#define SLNETIF_ADDR_CFG_STATIC (4) +#define SLNETIF_ADDR_CFG_STATELESS (5) +#define SLNETIF_ADDR_CFG_STATEFUL (6) + +/* Security object types for load Sec Obj function */ +#define SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY (1) +#define SLNETIF_SEC_OBJ_TYPE_CERTIFICATE (2) +#define SLNETIF_SEC_OBJ_TYPE_DH_KEY (3) + + +/* The 32bit queryBitmap structure - SlNetIf_queryIf function: + Bit 0 : Interface state - Check if interface state set to enable + Bit 1 : Interface connection status - Check if interface connection status is up + Bit 2 : Force answer - Return last found netIf, if none of the existing interfaces answers the query + Bits 3-31 : Reserved +*/ +#define SLNETIF_QUERY_IF_STATE_BIT (1 << 0) +#define SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT (1 << 1) +#define SLNETIF_QUERY_IF_ALLOW_PARTIAL_MATCH_BIT (1 << 2) + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +/*! + \brief SlNetIf_Config_t structure contains all the function callbacks that are expected to be filled by the relevant network stack interface \n + Each interface has different capabilities, so not all the API's must be supported therefore an API's can be defined as: + - Mandatory API's - must be supported by the interface in order to be part of SlNetSock layer + - Non-Mandatory API's - can be supported, but not mandatory for basic SlNetSock proper operation + + \note Interface that is not supporting a non-mandatory API should set it to \b NULL in its function list + + \sa SlNetIf_Config_t +*/ +typedef struct SlNetIf_Config_t +{ + /* socket related API's */ + int16_t (*sockCreate) (void *ifContext, int16_t domain, int16_t type, int16_t protocol, void **sdContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_create */ + int32_t (*sockClose) (int16_t sd, void *sdContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_close */ + int32_t (*sockShutdown) (int16_t sd, void *sdContext, int16_t how); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_shutdown */ + int16_t (*sockAccept) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_accept */ + int32_t (*sockBind) (int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_bind */ + int32_t (*sockListen) (int16_t sd, void *sdContext, int16_t backlog); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_listen */ + int32_t (*sockConnect) (int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_connect */ + int32_t (*sockGetPeerName) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_getPeerName */ + int32_t (*sockGetLocalName) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_getSockName */ + int32_t (*sockSelect) (void *ifContext, int16_t nsds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_select */ + int32_t (*sockSetOpt) (int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_setOpt */ + int32_t (*sockGetOpt) (int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_getOpt */ + int32_t (*sockRecv) (int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_recv */ + int32_t (*sockRecvFrom) (int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_recvFrom */ + int32_t (*sockSend) (int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_send */ + int32_t (*sockSendTo) (int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_sendTo */ + int32_t (*sockstartSec) (int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_startSec */ + + /* util related API's */ + int32_t (*utilGetHostByName) (void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetUtil_getHostByName */ + + /* if related API's */ + int32_t (*ifGetIPAddr) (void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetIf_getIPAddr */ + int32_t (*ifGetConnectionStatus) (void *ifContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetIf_getConnectionStatus */ + int32_t (*ifLoadSecObj) (void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetIf_loadSecObj */ + int32_t (*ifCreateContext) (uint16_t ifID, const char *ifName, void **ifContext); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetIf_add */ + +} SlNetIf_Config_t; + + +/*! + \brief The SlNetIf_t structure holds the configuration of the interface + Its ID, name, flags and the configuration list - ::SlNetIf_Config_t. +*/ +typedef struct SlNetIf_t +{ + uint32_t ifID; + char *ifName; + int32_t flags; + SlNetIf_Config_t *ifConf; + void *ifContext; +} SlNetIf_t; + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +/*! + + \brief Initialize the SlNetIf module + + \param[in] flags For future usage, + The value 0 may be used in order to run the + default flags + + \return Zero on success, or negative error code on failure + +*/ +int32_t SlNetIf_init(int32_t flags); + +/*! + \brief Add a new SlNetIf-compatible interface to the system + + The SlNetIf_add function allows the application to add specific interfaces + with their priorities and function list.\n + This function gives full control to the application on the interfaces. + + \param[in] ifID Specifies the interface which needs + to be added.\n + The values of the interface identifier + is defined with the prefix SLNETIF_ID_ + which defined in slnetif.h + \param[in] ifName Specifies the name of the interface, + \b Note: Can be set to NULL, but when set to NULL + cannot be used with SlNetIf_getIDByName + \param[in] ifConf Specifies the function list for the + interface + \param[in] priority Specifies the priority needs to be + set (In ascending order). + Note: maximum priority is 15 + + \return Zero on success, or negative error code on failure + + \slnetif_not_threadsafe + + \par Examples + + \code + uint8_t priority = 10; + SlNetIf_add(SLNETIF_ID_1, "WiFi_Interface", &SlNetIfConfigWifi, priority); + \endcode +
+*/ +int32_t SlNetIf_add(uint16_t ifID, char *ifName, const SlNetIf_Config_t *ifConf, uint8_t priority); + + +/*! + \brief Get interface configuration from interface ID + + The SlNetIf_getIfByID function retrieves the configuration of the + requested interface. + + \param[in] ifID Specifies the interface which its configuration + needs to be retrieved.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + + \return A pointer to the configuration of the + interface on success, or NULL on failure + + \sa SlNetIf_add() + + \slnetif_not_threadsafe + + \par Examples + + \code + SlNetIf_t *InterfaceName; + InterfaceName = SlNetIf_getNameByID(SLNETIF_ID_1); + \endcode +
+*/ +SlNetIf_t * SlNetIf_getIfByID(uint16_t ifID); + + +/*! + \brief Get highest priority interface configuration using interface bitmap + + The SlNetIf_getIfByID function retrieves highest priority interface + configuration that can be found in the interface bitmap, or the highest + exists when ifBitmap is zero. + + \param[in,out] ifBitmap Specifies the interface that needs to be checked + according to the queryBitmap and return the + interface with the highest priority.\n + The values of the interface Bitmap is a combination + of the interface identifiers defined with the prefix + SLNETIF_ID_ which defined in slnetif.h + Note: Zero is not a valid parameter, an error will + be returned + \param[in] queryBitmap Specifies the additional criterias for the query + that will be use along the interface priority and + interface ID.\n + queryBitmap bits: + - #SLNETIF_QUERY_IF_STATE_BIT + - #SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT + + \return A pointer to the configuration of the + interface on success, or NULL on failure + + \sa SlNetIf_add() + \slnetif_not_threadsafe + + \par Examples + + \code + SlNetIf_t *InterfaceName; + InterfaceName = SlNetIf_queryIf(SLNETIF_ID_1 | SLNETIF_ID_2 | SLNETIF_ID_3, SLNETIF_QUERY_IF_STATE_BIT | SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT); + \endcode +
+*/ +SlNetIf_t * SlNetIf_queryIf(uint32_t ifBitmap, uint32_t queryBitmap); + + +/*! + \brief Get interface Name from interface ID + + The SlNetIf_getNameByID function retrieves the name of the requested + interface. + + \param[in] ifID Specifies the interface which its name needs + to be retrieved.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + + \return A pointer to the name of the interface on + success, or NULL on failure + + \sa SlNetIf_add() + \sa SlNetIf_getIDByName() + + \slnetif_not_threadsafe + + \par Examples + + \code + char *InterfaceName; + InterfaceName = SlNetIf_getNameByID(SLNETIF_ID_1); + \endcode +
+*/ +const char * SlNetIf_getNameByID(uint16_t ifID); + + +/*! + \brief Get interface ID from interface name + + The SlNetIf_getIDByName function retrieves the interface identifier of the + requested interface name. + + \param[in] ifName Specifies the interface which its interface + identifier needs to be retrieved.\n + + \return The interface identifier value of the interface + on success, or negative error code on failure + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + + \sa SlNetIf_add() + \sa SlNetIf_getNameByID() + \sa SlNetSock_getIfID() + + \note - Input NULL as ifName will return error code. + - When using more than one interface with the same + name, the ID of the highest priority interface + will be returned + \slnetif_not_threadsafe + + \par Examples + + \code + int16_t InterfaceID; + InterfaceID = SlNetIf_getIDByName("WiFi_Interface"); + \endcode +
+*/ +int32_t SlNetIf_getIDByName(char *ifName); + + +/*! + \brief Get interface priority + + The SlNetIf_getPriority function retrieves the priority of the + interface. + + \param[in] ifID Specifies the interface which its priority + needs to be retrieved.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + + \return The priority value of the interface on success, + or negative error code on failure + + \sa SlNetIf_add() + \sa SlNetIf_setPriority() + + \slnetif_not_threadsafe + + \par Examples + + \code + int16_t Priority; + Priority = SlNetIf_getPriority(SLNETIF_ID_1); + \endcode +
+*/ +int32_t SlNetIf_getPriority(uint16_t ifID); + + +/*! + \brief Set interface priority + + The SlNetIf_setPriority function sets new priority to the requested interface. + + \param[in] ifID Specifies the interface which its priority + needs to be changed.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + \param[in] priority Specifies the priority needs to be set. + (In ascending order) + Note: maximum priority is 15 + + \return Zero on success, or negative error code on + failure + + \sa SlNetIf_add() + \sa SlNetIf_getPriority() + + \slnetif_not_threadsafe + + \par Examples + + \code + uint8_t priority = 10; + SlNetIf_setPriority(SLNETIF_ID_1, priority); + \endcode +
+*/ +int32_t SlNetIf_setPriority(uint16_t ifID, uint8_t priority); + + +/*! + \brief Set interface state + + Enable or disable the interface. + + \param[in] ifID Specifies the interface which its state + needs to be changed.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + \param[in] ifState Specifies the interface state.\n + The values of the interface state are defined + with the prefix SLNETIF_INTERFACE_ which + defined in slnetif.h + + \return Zero on success, or negative error code on + failure + + \sa SlNetIf_add() + \sa SlNetIf_getState() + + \slnetif_not_threadsafe + + \par Examples + + \code + SlNetIf_setState(SLNETIF_STATE_ENABLE); + \endcode +
+*/ +int32_t SlNetIf_setState(uint16_t ifID, SlNetIfState_e ifState); + + +/*! + \brief Get interface state + + Obtain the current state of the interface. + + \param[in] ifID Specifies the interface which its state needs + to be retrieved.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + + \return State of the interface on success, or negative + error code on failure + + \sa SlNetIf_add() + \sa SlNetIf_setState() + + \slnetif_not_threadsafe + + \par Examples + + \code + int16_t InterfaceState + InterfaceState = SlNetIf_getState(SLNETIF_ID_1); + \endcode +
+*/ +int32_t SlNetIf_getState(uint16_t ifID); + + +/*! + \brief Get interface connection status + + Obtain the connection status of the interface. + + \param[in] ifID Specifies the interface which its connection + status needs to be retrieved.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + + \return Connection status of the interface on success, + or negative error code on failure + + \sa SlNetIf_add() + + \slnetif_not_threadsafe + + \par Examples + + \code + int16_t connection_status + connection_status = SlNetIf_getConnectionStatus(SLNETIF_ID_1); + \endcode +
+*/ +int32_t SlNetIf_getConnectionStatus(uint16_t ifID); + + +/*! + \brief Get IP Address of specific interface + + The SlNetIf_getIPAddr function retrieve the IP address of a specific + interface according to the Address Type, IPv4, IPv6 LOCAL + or IPv6 GLOBAL. + + \param[in] ifID Specifies the interface which its connection + state needs to be retrieved.\n + The values of the interface identifier is + defined with the prefix SLNETIF_ID_ which + defined in slnetif.h + \param[in] addrType Address type: + - #SLNETIF_IPV4_ADDR + - #SLNETIF_IPV6_ADDR_LOCAL + - #SLNETIF_IPV6_ADDR_GLOBAL + \param[out] addrConfig Address config: + - #SLNETIF_ADDR_CFG_UNKNOWN + - #SLNETIF_ADDR_CFG_DHCP + - #SLNETIF_ADDR_CFG_DHCP_LLA + - #SLNETIF_ADDR_CFG_STATIC + - #SLNETIF_ADDR_CFG_STATELESS + - #SLNETIF_ADDR_CFG_STATEFUL + \param[out] ipAddr IP Address according to the Address Type + + \return Zero on success, or negative error code on failure + + \sa SlNetIfAddressType_e + + \slnetif_not_threadsafe + + \par Examples + + \code + SlNetSock_In6Addr_t IPAdd; + uint16_t addressConfig = 0; + SlNetIf_getIPAddr(SLNETIF_ID_1, SLNETIF_IPV6_ADDR_LOCAL, &addressConfig, (uint8_t *)ipAddr); + \endcode +
+*/ +int32_t SlNetIf_getIPAddr(uint16_t ifID, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); + + +/*! + \brief Load secured buffer to the network stack + + The SlNetSock_secLoadObj function loads buffer/files into the inputted + network stack for future usage of the socket SSL/TLS connection. + This option is relevant for network stacks with file system and also for + network stacks that lack file system that can store the secured files. + + \param[in] objType Specifies the security object type which + could be one of the following:\n + - #SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY + - #SLNETIF_SEC_OBJ_TYPE_CERTIFICATE + - #SLNETIF_SEC_OBJ_TYPE_DH_KEY + \param[in] objName Specifies the name/input identifier of the + secured buffer loaded + for file systems - this can be the file name + for plain text buffer loading this can be the + name of the object + \param[in] objNameLen Specifies the buffer name length to be loaded.\n + \param[in] objBuff Specifies the pointer to the secured buffer to + be loaded.\n + \param[in] objBuffLen Specifies the buffer length to be loaded.\n + \param[in] ifBitmap Specifies the interfaces which the security + objects needs to be added to.\n + The values of the interface identifiers + is defined with the prefix SLNETIF_ID_ + which defined in slnetif.h + + \return On success, buffer type handler index to be + used when attaching the secured buffer to a + socket.\n + A successful return code should be a positive + number (int16)\n + On error, a negative value will be returned + specifying the error code. + - #SLNETERR_STATUS_ERROR - load operation failed + + \sa SlNetSock_setOpt() + + \slnetif_not_threadsafe + +*/ +int32_t SlNetIf_loadSecObj(uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen, uint32_t ifBitmap); + +/*! + + Close the Doxygen group. + @} + +*/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __SL_NET_IF_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetsock.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetsock.h new file mode 100755 index 00000000000..804113a8aef --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetsock.h @@ -0,0 +1,1846 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /*! + + + \page SlNetSock_overview SlNetSock + + \section intro_sec Introduction + +SlNetSock provides a standard BSD API for TCP and UDP transport +layers, and a lower-level SlNetSock API for basic and extended +usage. Supported use cases include: + + - Support of multi interface (WiFi NS, Ethernet NDK) + - Selecting which interfaces the host will use, one or more. + - Support of different types of sockets (TCP, TLS, UDP, RAW, RF, etc.) + - BSD and proprietary errors + + The SlNetSock API's lead to easier portability to microcontrollers, + without compromising the capabilities and robustness of the final + application. + + + \section modules_sec Module Names + TI's SlNetSock layer is divided into the following software modules: + -# \ref SlNetSock - Controls standard client/server sockets options and capabilities + -# \ref SlNetIf - Controls standard stack/interface options and capabilities + -# \ref SlNetUtils - Provides sockets related commands and configuration + -# \ref SlNetErr - Provide BSD and proprietary errors + +In addition, SlNetSock provides a standard BSD API, built atop the +SlNet* APIs. The BSD headers are placed in ti/net/bsd directory, +which users should place on their include path. + +Also, there is a light +\subpage porting_guide "SL Interface Porting Guide" +with information available for adding SlNetSock support for other stacks. + + \page porting_guide SL Interface Porting Guide + + \section Introduction + +The generic SlNetSock layer sits between the application/service and +the interface stack. This guide describes the details of adding a network stack into the SlNetSock environment. + +The porting steps for adding new interface: + -# Create slnetifxxx file for the new interface + -# Select the capabilities set + -# Adding the interface to your application/service + -# Add the relevant functions to your application/service + -# Test your code to validate the correctness of your porting + + \subsection porting_step1 Step 1 - slnetifxxx.c and slnetifxxx.h file for your interface + + - Create slnetifxxx file (replace xxx with your interface/stack + name). Likely you will copy from an existing port. + + - Implement the needed API's. + +Each interface needs to provide a set of API's to work with the +interface. Some are mandatory, others are optional (but recommended). + + - Mandatory API's: + - \ref SlNetIf_Config_t.sockCreate "sockCreate" + - \ref SlNetIf_Config_t.sockClose "sockClose" + - \ref SlNetIf_Config_t.sockSelect "sockSelect" + - \ref SlNetIf_Config_t.sockSetOpt "sockSetOpt" + - \ref SlNetIf_Config_t.sockGetOpt "sockGetOpt" + - \ref SlNetIf_Config_t.sockRecvFrom "sockRecvFrom" + - \ref SlNetIf_Config_t.sockSendTo "sockSendTo" + - \ref SlNetIf_Config_t.ifGetIPAddr "ifGetIPAddr" + - \ref SlNetIf_Config_t.ifGetConnectionStatus "ifGetConnectionStatus" + + - The non-mandatory API's set: + - \ref SlNetIf_Config_t.sockShutdown "sockShutdown" + - \ref SlNetIf_Config_t.sockAccept "sockAccept" + - \ref SlNetIf_Config_t.sockBind "sockBind" + - \ref SlNetIf_Config_t.sockListen "sockListen" + - \ref SlNetIf_Config_t.sockConnect "sockConnect" + - \ref SlNetIf_Config_t.sockGetPeerName "sockGetPeerName" + - \ref SlNetIf_Config_t.sockGetLocalName "sockGetLocalName" + - \ref SlNetIf_Config_t.sockRecv "sockRecv" + - \ref SlNetIf_Config_t.sockSend "sockSend" + - \ref SlNetIf_Config_t.sockstartSec "sockstartSec" + - \ref SlNetIf_Config_t.utilGetHostByName "utilGetHostByName" + - \ref SlNetIf_Config_t.ifLoadSecObj "ifLoadSecOjb" + - \ref SlNetIf_Config_t.ifCreateContext "ifCreateContext" + + + \note The list of API's and more data can be found in ::SlNetIf_Config_t structure in SlNetIf module \n \n + + \subsection porting_step2 Step 2 - Select the capabilities set + + The capabilities prototype should be declared in your slnetifxxx.h and implemented in your slnetifxxx.c + + Each mandatory API's must be set, additional API's can be set or must + be set to NULL. + + An example config declaration for TI's SimpleLink CC31XX/CC32xx + + \code + SlNetIfConfig SlNetIfConfigWiFi = + { + SlNetIfWifi_socket, // Callback function sockCreate in slnetif module + SlNetIfWifi_close, // Callback function sockClose in slnetif module + NULL, // Callback function sockShutdown in slnetif module + SlNetIfWifi_accept, // Callback function sockAccept in slnetif module + SlNetIfWifi_bind, // Callback function sockBind in slnetif module + SlNetIfWifi_listen, // Callback function sockListen in slnetif module + SlNetIfWifi_connect, // Callback function sockConnect in slnetif module + NULL, // Callback function sockGetPeerName in slnetif module + NULL, // Callback function sockGetLocalName in slnetif module + SlNetIfWifi_select, // Callback function sockSelect in slnetif module + SlNetIfWifi_setSockOpt, // Callback function sockSetOpt in slnetif module + SlNetIfWifi_getSockOpt, // Callback function sockGetOpt in slnetif module + SlNetIfWifi_recv, // Callback function sockRecv in slnetif module + SlNetIfWifi_recvFrom, // Callback function sockRecvFrom in slnetif module + SlNetIfWifi_send, // Callback function sockSend in slnetif module + SlNetIfWifi_sendTo, // Callback function sockSendTo in slnetif module + SlNetIfWifi_sockstartSec, // Callback function sockstartSec in slnetif module + SlNetIfWifi_getHostByName, // Callback function utilGetHostByName in slnetif module + SlNetIfWifi_getIPAddr, // Callback function ifGetIPAddr in slnetif module + SlNetIfWifi_getConnectionStatus, // Callback function ifGetConnectionStatus in slnetif module + SlNetIfWifi_loadSecObj, // Callback function ifLoadSecObj in slnetif module + NULL // Callback function ifCreateContext in slnetif module + }; + \endcode + + In the example above the following API's are not supported by the interface, + and are set to NULL: + - sockShutdown + - sockGetPeerName + - sockGetLocalName + - utilGetHostByName + - ifCreateContext + + \subsection porting_step3 Step 3 - Adding the interface to your application/service + + \b Include the new file in the board header file in the application. + + \subsection porting_step4 Step 4 - Add the relevant functions to your application/service + + After configuring the capabilities of the interface, Adding the interface to the SlNetSock + is required. + + Use ::SlNetIf_add in order to add the interface and set his ID, Name, function list and priority. + Later on you need to use the BSD API's or SlNetSock API's for socket handling. + + \subsection porting_step5 Step 5 - Test your code to validate the correctness of your porting + + After porting the layer into your setup, validate that your code work as expected + +*/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#ifndef __SL_NET_SOCK_H__ +#define __SL_NET_SOCK_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/*! + \defgroup SlNetSock SlNetSock group + + \short Controls standard client/server sockets options and capabilities + +*/ +/*! + + \addtogroup SlNetSock + @{ + +*/ + +/*****************************************************************************/ +/* Macro declarations */ +/*****************************************************************************/ + +#define SLNETSOCK_MAX_CONCURRENT_SOCKETS (32) /**< Declares the maximum sockets that can be opened */ + +/* Address families. */ +#define SLNETSOCK_AF_UNSPEC (0) /**< Unspecified address family */ +#define SLNETSOCK_AF_INET (2) /**< IPv4 socket (UDP, TCP, etc) */ +#define SLNETSOCK_AF_INET6 (3) /**< IPv6 socket (UDP, TCP, etc) */ +#define SLNETSOCK_AF_RF (6) /**< Data include RF parameter, All layer by user (Wifi could be disconnected) */ +#define SLNETSOCK_AF_PACKET (17) /**< Network bypass */ + +/* Protocol families, same as address families. */ +#define SLNETSOCK_PF_UNSPEC SLNETSOCK_AF_UNSPEC +#define SLNETSOCK_PF_INET SLNETSOCK_AF_INET +#define SLNETSOCK_PF_INET6 SLNETSOCK_AF_INET6 + +/* Define argument types specifies the socket type. */ +#define SLNETSOCK_SOCK_STREAM (1) /**< TCP Socket */ +#define SLNETSOCK_SOCK_DGRAM (2) /**< UDP Socket */ +#define SLNETSOCK_SOCK_RAW (3) /**< Raw socket */ +#define SLNETSOCK_SOCK_RX_MTR (4) /**< RX Metrics socket */ +#define SLNETSOCK_SOCK_MAC_WITH_CCA (5) +#define SLNETSOCK_SOCK_MAC_WITH_NO_CCA (6) +#define SLNETSOCK_SOCK_BRIDGE (7) +#define SLNETSOCK_SOCK_ROUTER (8) + +/* Define some BSD protocol constants. */ +#define SLNETSOCK_PROTO_TCP (6) /**< TCP Raw Socket */ +#define SLNETSOCK_PROTO_UDP (17) /**< UDP Raw Socket */ +#define SLNETSOCK_PROTO_RAW (255) /**< Raw Socket */ +#define SLNETSOCK_PROTO_SECURE (100) /**< Secured Socket Layer (SSL,TLS) */ + +/* bind any addresses */ +#define SLNETSOCK_INADDR_ANY (0) +#define SLNETSOCK_IN6ADDR_ANY (0) + + +/* socket options */ + +/* possible values for the level parameter in slNetSock_setOpt / slNetSock_getOpt */ +#define SLNETSOCK_LVL_SOCKET (1) /**< Define the socket option category. */ +#define SLNETSOCK_LVL_IP (2) /**< Define the IP option category. */ +#define SLNETSOCK_LVL_PHY (3) /**< Define the PHY option category. */ + +/* possible values for the option parameter in slNetSock_setOpt / slNetSock_getOpt */ + +/* socket level options (SLNETSOCK_LVL_SOCKET) */ +#define SLNETSOCK_OPSOCK_RCV_BUF (8) /**< Setting TCP receive buffer size (window size) - This options takes SlNetSock_Winsize_t struct as parameter */ +#define SLNETSOCK_OPSOCK_RCV_TIMEO (20) /**< Enable receive timeout - This options takes SlNetSock_Timeval_t struct as parameter */ +#define SLNETSOCK_OPSOCK_KEEPALIVE (9) /**< Connections are kept alive with periodic messages - This options takes SlNetSock_Keepalive_t struct as parameter */ +#define SLNETSOCK_OPSOCK_KEEPALIVE_TIME (37) /**< keepalive time out - This options takes uint32_t as parameter */ +#define SLNETSOCK_OPSOCK_LINGER (13) /**< Socket lingers on close pending remaining send/receive packets - This options takes SlNetSock_linger_t struct as parameter */ +#define SLNETSOCK_OPSOCK_NON_BLOCKING (24) /**< Enable/disable nonblocking mode - This options takes SlNetSock_Nonblocking_t struct as parameter */ +#define SLNETSOCK_OPSOCK_NON_IP_BOUNDARY (39) /**< connectionless socket disable rx boundary - This options takes SlNetSock_NonIpBoundary_t struct as parameter */ +#define SLNETSOCK_OPSOCK_ERROR (58) /**< Socket level error code */ +#define SLNETSOCK_OPSOCK_SLNETSOCKSD (59) /**< Used by the BSD layer in order to retrieve the slnetsock sd */ + +/* IP level options (SLNETSOCK_LVL_IP) */ +#define SLNETSOCK_OPIP_MULTICAST_TTL (61) /**< Specify the TTL value to use for outgoing multicast packet. - This options takes uint8_t as parameter */ +#define SLNETSOCK_OPIP_ADD_MEMBERSHIP (65) /**< Join IPv4 multicast membership - This options takes SlNetSock_IpMreq_t struct as parameter */ +#define SLNETSOCK_OPIP_DROP_MEMBERSHIP (66) /**< Leave IPv4 multicast membership - This options takes SlNetSock_IpMreq_t struct as parameter */ +#define SLNETSOCK_OPIP_HDRINCL (67) /**< Raw socket IPv4 header included - This options takes uint32_t as parameter */ +#define SLNETSOCK_OPIP_RAW_RX_NO_HEADER (68) /**< Proprietary socket option that does not includeIPv4/IPv6 header (and extension headers) on received raw sockets - This options takes uint32_t as parameter */ +#define SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (69) /**< Transmitted buffer over IPv6 socket contains IPv6 header - This options takes uint32_t as parameter */ +#define SLNETSOCK_OPIPV6_ADD_MEMBERSHIP (70) /**< Join IPv6 multicast membership - This options takes SlNetSock_IpV6Mreq_t struct as parameter */ +#define SLNETSOCK_OPIPV6_DROP_MEMBERSHIP (71) /**< Leave IPv6 multicast membership - This options takes SlNetSock_IpV6Mreq_t struct as parameter */ +#define SLNETSOCK_OPIPV6_MULTICAST_HOPS (72) /**< Specify the hops value to use for outgoing multicast packet. */ + +/* PHY level options (SLNETSOCK_LVL_PHY) */ +#define SLNETSOCK_OPPHY_CHANNEL (28) /**< This option is available only when transceiver started - This options takes uint32_t as channel number parameter */ +#define SLNETSOCK_OPPHY_RATE (100) /**< WLAN Transmit rate - This options takes uint32_t as parameter based on SlWlanRateIndex_e */ +#define SLNETSOCK_OPPHY_TX_POWER (101) /**< TX Power level - This options takes uint32_t as parameter */ +#define SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX (102) /**< Number of frames to transmit - This options takes uint32_t as parameter */ +#define SLNETSOCK_OPPHY_PREAMBLE (103) /**< Preamble for transmission - This options takes uint32_t as parameter */ +#define SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD (104) /**< TX Inhibit Threshold (CCA) - This options takes uint32_t as parameter based on SlNetSockTxInhibitThreshold_e */ +#define SLNETSOCK_OPPHY_TX_TIMEOUT (105) /**< TX timeout for Transceiver frames (lifetime) in miliseconds (max value is 100ms) - This options takes uint32_t as parameter */ +#define SLNETSOCK_OPPHY_ALLOW_ACKS (106) /**< Enable sending ACKs in transceiver mode - This options takes uint32_t as parameter */ + +/*! + \brief The SlNetSockTxInhibitThreshold_e enumerations is used in SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD PHY level option +*/ +typedef enum +{ + SLNETSOCK_TX_INHIBIT_THRESHOLD_MIN = 1, + SLNETSOCK_TX_INHIBIT_THRESHOLD_LOW = 2, + SLNETSOCK_TX_INHIBIT_THRESHOLD_DEFAULT = 3, + SLNETSOCK_TX_INHIBIT_THRESHOLD_MED = 4, + SLNETSOCK_TX_INHIBIT_THRESHOLD_HIGH = 5, + SLNETSOCK_TX_INHIBIT_THRESHOLD_MAX = 6 +} SlNetSockTxInhibitThreshold_e; + +/*! + \brief The SlNetSockSecAttrib_e enumerations are used to declare security + attribute objects in SlNetSock_secAttribSet(). + + \sa SlNetSock_secAttribSet() +*/ +typedef enum +{ + SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY = 0, + SLNETSOCK_SEC_ATTRIB_LOCAL_CERT = 1, + SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA = 2, + SLNETSOCK_SEC_ATTRIB_DH_KEY = 3, + SLNETSOCK_SEC_ATTRIB_METHOD = 4, + SLNETSOCK_SEC_ATTRIB_CIPHERS = 5, + SLNETSOCK_SEC_ATTRIB_ALPN = 6, + SLNETSOCK_SEC_ATTRIB_EXT_CLIENT_CHLNG_RESP = 7, + SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME = 8, + + /*! + @c SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE is + currently only supported on CC3x20 devices. + + The certificate store is a file, provided by TI, + containing a list of known and trusted root CAs by TI. + For more information, see the CC3x20 documentation. + + The certificate store is used only in client mode. Servers + use a proprietary root CA to authenticate clients, and + therefore cannot use the certificate store. + + Using this attribute allows using root CA which isn't a + part of the provided certificate store. + */ + + SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE = 9 +} SlNetSockSecAttrib_e; + +/* available values for SLNETSOCK_SEC_ATTRIB_METHOD */ +#define SLNETSOCK_SEC_METHOD_SSLV3 (0) /**< security method SSL v3 */ +#define SLNETSOCK_SEC_METHOD_TLSV1 (1) /**< security method TLS v1 */ +#define SLNETSOCK_SEC_METHOD_TLSV1_1 (2) /**< security method TLS v1_1 */ +#define SLNETSOCK_SEC_METHOD_TLSV1_2 (3) /**< security method TLS v1_2 */ +#define SLNETSOCK_SEC_METHOD_SSLv3_TLSV1_2 (4) /**< use highest possible version from SSLv3 - TLS 1.2 */ +#define SLNETSOCK_SEC_METHOD_DLSV1 (5) /**< security method DTL v1 */ + +/* available values for SLNETSOCK_SEC_ATTRIB_CIPHERS. The value is bitmap! */ +#define SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_SHA (1 << 0) +#define SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_MD5 (1 << 1) +#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA (1 << 2) +#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_256_CBC_SHA (1 << 3) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA (1 << 4) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_RC4_128_SHA (1 << 5) +#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_128_CBC_SHA256 (1 << 6) +#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA256 (1 << 7) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (1 << 8) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (1 << 9) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA (1 << 10) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA (1 << 11) +#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_128_GCM_SHA256 (1 << 12) +#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_GCM_SHA384 (1 << 13) +#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 14) +#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 15) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 16) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 17) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (1 << 18) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 (1 << 19) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 20) +#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 21) +#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 22) +#define SLNETSOCK_SEC_CIPHER_FULL_LIST (0xFFFFFFFF) + +/* available values for SLNETSOCK_SEC_ATTRIB_ALPN */ +#define SLNETSOCK_SEC_ALPN_H1 (1 << 0) +#define SLNETSOCK_SEC_ALPN_H2 (1 << 1) +#define SLNETSOCK_SEC_ALPN_H2C (1 << 2) +#define SLNETSOCK_SEC_ALPN_H2_14 (1 << 3) +#define SLNETSOCK_SEC_ALPN_H2_16 (1 << 4) +#define SLNETSOCK_SEC_ALPN_FULL_LIST ((SLNETSOCK_SEC_ALPN_H2_16 << 1 ) - 1) + +/* available values for the flags of the SlNetSock_startSec function */ +#define SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY (1 << 0) /**< Sends the command that will start the security session for a specific socket descriptor */ +#define SLNETSOCK_SEC_BIND_CONTEXT_ONLY (1 << 1) /**< Binds the security context to a specific socket descriptor */ +#define SLNETSOCK_SEC_IS_SERVER (1 << 2) /**< Used to define if the socket is client/server socket */ + +/* available values for the flags of the SlNetSock_create function */ + +#define SLNETSOCK_CREATE_IF_STATE_ENABLE (1 << 0) /**< Creation of the socket will be on enabled state */ +#define SLNETSOCK_CREATE_IF_STATUS_CONNECTED (1 << 1) /**< Creation of the socket will be on status connected */ +#define SLNETSOCK_CREATE_ALLOW_PARTIAL_MATCH (1 << 2) /**< Creation of the socket will be on the interface with + the highest priority if the other flags will fail */ + +/* Definitions for shutting down some or all parts of a full duplex connection */ +#define SLNETSOCK_SHUT_RD (0) /**< Further receptions will be disallowed */ +#define SLNETSOCK_SHUT_WR (1) /**< Further transmissions will be disallowed */ +#define SLNETSOCK_SHUT_RDWR (2) /**< Further receptions and transmissions will be disallowed */ + +/* Length of address string representation */ +#define SLNETSOCK_INET6_ADDRSTRLEN (46) +#define SLNETSOCK_INET_ADDRSTRLEN (16) + +/* flags used in send/recv and friends. + * + * Note these flags must not exceed 24-bits. The implementation will + * OR the 8-bits of security flags into the remaining high 8 bits of + * 32-bit flag variables. + */ +#define SLNETSOCK_MSG_OOB (0x0001) +#define SLNETSOCK_MSG_PEEK (0x0002) +#define SLNETSOCK_MSG_WAITALL (0x0004) +#define SLNETSOCK_MSG_DONTWAIT (0x0008) +#define SLNETSOCK_MSG_DONTROUTE (0x0010) +#define SLNETSOCK_MSG_NOSIGNAL (0x0020) + + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +/*! + \brief Internet address +*/ +typedef struct SlNetSock_InAddr_t +{ +#ifndef s_addr + uint32_t s_addr; /* Internet address 32 bits */ +#else +/*! + \brief Different representations for in addr for different hosts. +*/ + union S_un + { + uint32_t S_addr; + struct + { + uint8_t s_b1,s_b2,s_b3,s_b4; + } S_un_b; + struct + { + uint16_t s_w1,s_w2; + } S_un_w; + } S_un; +#endif +} SlNetSock_InAddr_t; + +/*! + \brief IpV6 or Ipv6 EUI64 +*/ +typedef struct SlNetSock_In6Addr_t +{ + union + { + uint8_t _S6_u8[16]; + uint16_t _S6_u16[8]; + uint32_t _S6_u32[4]; + } _S6_un; +} SlNetSock_In6Addr_t; + +/*! + \brief The SlNetSock_Keepalive_t structure is used in #SLNETSOCK_OPSOCK_KEEPALIVE socket level option +*/ +typedef struct SlNetSock_Keepalive_t +{ + uint32_t keepaliveEnabled; /**< 0 = disabled;1 = enabled; default = 1 */ +} SlNetSock_Keepalive_t; + +/*! + \brief The SlNetSock_NonIpBoundary_t structure is used in #SLNETSOCK_OPSOCK_NON_IP_BOUNDARY socket level option +*/ +typedef struct SlNetSock_NonIpBoundary_t +{ + int32_t nonIpBoundaryEnabled; /**< 0 = keep IP boundary; 1 = don`t keep ip boundary; default = 0; */ +} SlNetSock_NonIpBoundary_t; + +/*! + \brief The SlNetSock_Winsize_t structure is used in #SLNETSOCK_OPSOCK_RCV_BUF socket level option +*/ +typedef struct SlNetSock_Winsize_t +{ + uint32_t winSize; /**< receive window size for tcp sockets */ +} SlNetSock_Winsize_t; + +/*! + \brief The SlNetSock_Nonblocking_t structure is used in #SLNETSOCK_OPSOCK_NON_BLOCKING socket level option +*/ +typedef struct SlNetSock_Nonblocking_t +{ + uint32_t nonBlockingEnabled; /**< 0 = disabled, 1 = enabled, default = 1*/ +} SlNetSock_Nonblocking_t; + +/*! + \brief Secure socket attribute context +*/ +typedef struct SlNetSock_SecAttribNode_t +{ + SlNetSockSecAttrib_e attribName; /**< Security attribute name */ + uint8_t *attribBuff; /**< Security attribute buffer */ + uint16_t attribBuffLen; /**< Security attribute buffer length */ + struct SlNetSock_SecAttribNode_t *next; +} SlNetSock_SecAttribNode_t; + +/*! + \brief Secure socket attribute handler +*/ +typedef SlNetSock_SecAttribNode_t * SlNetSockSecAttrib_t; + +/*! + \brief Secure ALPN structure +*/ +typedef struct SlNetSock_SecureALPN_t +{ + uint32_t secureALPN; +} SlNetSock_SecureALPN_t; + +/*! + \brief Secure Mask structure +*/ +typedef struct SlNetSock_SecureMask_t +{ + uint32_t secureMask; +} SlNetSock_SecureMask_t; + +/*! + \brief Secure Method structure +*/ +typedef struct SlNetSock_SecureMethod_t +{ + uint8_t secureMethod; +} SlNetSock_SecureMethod_t; + +/*! + \brief The SlNetSock_IpMreq_t structure is used in #SLNETSOCK_OPIP_ADD_MEMBERSHIP and #SLNETSOCK_OPIP_DROP_MEMBERSHIP IP level option +*/ +typedef struct SlNetSock_IpMreq_t +{ + SlNetSock_InAddr_t imr_multiaddr; /**< The IPv4 multicast address to join */ + uint32_t imr_interface; /**< The interface to use for this group */ +} SlNetSock_IpMreq_t; + +/*! + \brief The SlNetSock_IpV6Mreq_t structure is used in #SLNETSOCK_OPIPV6_ADD_MEMBERSHIP and #SLNETSOCK_OPIPV6_DROP_MEMBERSHIP IP level option +*/ +typedef struct SlNetSock_IpV6Mreq_t +{ + SlNetSock_In6Addr_t ipv6mr_multiaddr; /**< IPv6 multicast address of group */ + uint32_t ipv6mr_interface; /**< should be 0 to choose the default multicast interface */ +} SlNetSock_IpV6Mreq_t; + +/*! + \brief The SlNetSock_linger_t structure is used in #SLNETSOCK_OPSOCK_LINGER socket level option +*/ +typedef struct SlNetSock_linger_t +{ + uint32_t l_onoff; /**< 0 = disabled; 1 = enabled; default = 0; */ + uint32_t l_linger; /**< linger time in seconds; default = 0; */ +} SlNetSock_linger_t; + +/*! + \brief The SlNetSockTime_t is used for setting/getting time in seconds +*/ +typedef int32_t SlNetSockTime_t; +/*! + \brief The SlNetSockuseconds_t is used for setting/getting time in micro-seconds +*/ +typedef int32_t SlNetSockuseconds_t; + +/*! + \brief The SlNetSock_Timeval_t structure is used in #SLNETSOCK_OPSOCK_RCV_TIMEO socket level option +*/ +typedef struct SlNetSock_Timeval_t +{ + SlNetSockTime_t tv_sec; /**< Seconds */ + SlNetSockuseconds_t tv_usec; /**< Microseconds */ +} SlNetSock_Timeval_t; + +/*! + \brief The SlNetSocklen_t is used for declaring the socket length parameter +*/ +typedef uint16_t SlNetSocklen_t; + +/*! + \brief IpV4 socket address +*/ +typedef struct SlNetSock_Addr_t +{ + uint16_t sa_family; /**< Address family (e.g. AF_INET) */ + uint8_t sa_data[14]; /**< Protocol- specific address information */ +} SlNetSock_Addr_t; + +/*! + \brief SlNetSock IPv6 address, Internet style +*/ +typedef struct SlNetSock_AddrIn6_t +{ + uint16_t sin6_family; /**< SLNETSOCK_AF_INET6 */ + uint16_t sin6_port; /**< Transport layer port. */ + uint32_t sin6_flowinfo; /**< IPv6 flow information. */ + SlNetSock_In6Addr_t sin6_addr; /**< IPv6 address. */ + uint32_t sin6_scope_id; /**< set of interfaces for a scope. */ +} SlNetSock_AddrIn6_t; + +/*! + \brief SlNetSock IPv4 address, Internet style +*/ +typedef struct SlNetSock_AddrIn_t +{ + uint16_t sin_family; /**< Internet Protocol (AF_INET). */ + uint16_t sin_port; /**< Address port (16 bits). */ + SlNetSock_InAddr_t sin_addr; /**< Internet address (32 bits). */ + int8_t sin_zero[8]; /**< Not used. */ +} SlNetSock_AddrIn_t; + +/*! + \brief The SlNetSock_SdSet_t structure holds the sd array for SlNetSock_select function +*/ +typedef struct SlNetSock_SdSet_t /**< The select socket array manager */ +{ + uint32_t sdSetBitmap[(SLNETSOCK_MAX_CONCURRENT_SOCKETS + (uint8_t)31)/(uint8_t)32]; /* Bitmap of SOCKET Descriptors */ +} SlNetSock_SdSet_t; + + +/*! + \brief The SlNetSock_TransceiverRxOverHead_t structure holds the data for Rx transceiver mode using a raw socket when using SlNetSock_recv function +*/ +typedef struct SlNetSock_TransceiverRxOverHead_t +{ + uint8_t rate; /**< Received Rate */ + uint8_t channel; /**< The received channel */ + int8_t rssi; /**< The computed RSSI value in db of current frame */ + uint8_t padding; /**< pad to align to 32 bits */ + uint32_t timestamp; /**< Timestamp in microseconds */ +} SlNetSock_TransceiverRxOverHead_t; + + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +/*! + + \brief Initialize the SlNetSock module + + \param[in] flags Reserved + + \return Zero on success, or negative error code on failure +*/ +int32_t SlNetSock_init(int32_t flags); + +/*! + + \brief Create an endpoint for communication + + SlNetSock_create() creates a new socket of a certain socket type, + identified by an integer number, and allocates system resources to it.\n + This function is called by the application layer to obtain a socket descriptor (handle). + + \param[in] domain Specifies the protocol family of the created socket. + For example: + - #SLNETSOCK_AF_INET for network protocol IPv4 + - #SLNETSOCK_AF_INET6 for network protocol IPv6 + - #SLNETSOCK_AF_RF for starting transceiver mode. + Notes: + - sending and receiving any packet overriding 802.11 header + - for optimized power consumption the socket will be started in TX + only mode until receive command is activated + \param[in] type Specifies the socket type, which determines the semantics of communication over + the socket. The socket types supported by the system are implementation-dependent. + Possible socket types include: + - #SLNETSOCK_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) + - #SLNETSOCK_SOCK_DGRAM (datagram service or Datagram Sockets) + - #SLNETSOCK_SOCK_RAW (raw protocols atop the network layer) + - when used with AF_RF: + - #SLNETSOCK_SOCK_RX_MTR + - #SLNETSOCK_SOCK_MAC_WITH_CCA + - #SLNETSOCK_SOCK_MAC_WITH_NO_CCA + - #SLNETSOCK_SOCK_BRIDGE + - #SLNETSOCK_SOCK_ROUTER + \param[in] protocol Specifies a particular transport to be used with the socket.\n + The most common are + - #SLNETSOCK_PROTO_TCP + - #SLNETSOCK_PROTO_UDP + - #SLNETSOCK_PROTO_RAW + - #SLNETSOCK_PROTO_SECURE + \param[in] ifBitmap Specifies the interface(s) which the socket will be create on + according to the priority until one of them will return an answer.\n + Value 0 is used in order to choose automatic interfaces selection + according to the priority interface list. + Value can be combination of interfaces by OR'ing multiple interfaces bit identifiers + (SLNETIFC_IDENT_ defined in slnetif.h) + Note: interface identifier bit must be configured prior to this socket creation + using SlNetIf_add(). + \param[in] flags Specifies flags. + - #SLNETSOCK_CREATE_IF_STATE_ENABLE - Creation of the socket will be on enabled state + - #SLNETSOCK_CREATE_IF_STATUS_CONNECTED - Creation of the socket will be on status connected + - #SLNETSOCK_CREATE_ALLOW_PARTIAL_MATCH - Creation of the socket will be on the interface with + the highest priority if the other flags will fail + The value 0 may be used in order to run the default flags: + - #SLNETSOCK_CREATE_IF_STATE_ENABLE + - #SLNETSOCK_CREATE_IF_STATUS_CONNECTED + + \return On success, socket descriptor (handle) that is used for consequent socket operations. \n + A successful return code should be a positive number\n + On error, a negative value will be returned specifying the error code. + - #SLNETERR_BSD_EAFNOSUPPORT - illegal domain parameter + - #SLNETERR_BSD_EPROTOTYPE - illegal type parameter + - #SLNETERR_BSD_EACCES - permission denied + - #SLNETERR_BSD_ENSOCK - exceeded maximal number of socket + - #SLNETERR_BSD_ENOMEM - memory allocation error + - #SLNETERR_BSD_EINVAL - error in socket configuration + - #SLNETERR_BSD_EPROTONOSUPPORT - illegal protocol parameter + - #SLNETERR_BSD_EOPNOTSUPP - illegal combination of protocol and type parameters + + \slnetsock_init_precondition + + \remark Not all platforms support all options. + + \remark A @c protocol value of zero can be used to select the default protocol from the selected @c domain and @c type. + + \sa SlNetSock_close() +*/ +int16_t SlNetSock_create(int16_t domain, int16_t type, int16_t protocol, uint32_t ifBitmap, int16_t flags); + + +/*! + \brief Gracefully close socket + + Release resources allocated to a socket. + + \param[in] sd Socket descriptor (handle), received in SlNetSock_create() + + \return Zero on success, or negative error code on failure + + \slnetsock_init_precondition + + \remark In the case of TCP, the connection is terminated. + + \sa SlNetSock_create() +*/ +int32_t SlNetSock_close(int16_t sd); + + +/*! + \brief Shutting down parts of a full-duplex connection + + Shuts down parts of a full-duplex connection according to how parameter.\n + + \param[in] sd Socket descriptor (handle), received in SlNetSock_create + \param[in] how Specifies which part of a full-duplex connection to shutdown. \n + The options are + - #SLNETSOCK_SHUT_RD - further receptions will be disallowed + - #SLNETSOCK_SHUT_WR - further transmissions will be disallowed + - #SLNETSOCK_SHUT_RDWR - further receptions and transmissions will be disallowed + + \return Zero on success, or negative error code on failure + + \slnetsock_init_precondition + + \sa SlNetSock_create() + \sa SlNetSock_connect() + \sa SlNetSock_accept() +*/ +int32_t SlNetSock_shutdown(int16_t sd, int16_t how); + + +/*! + \brief Accept a connection on a socket + + The SlNetSock_accept function is used with connection-based socket types (#SLNETSOCK_SOCK_STREAM). + + It extracts the first connection request on the queue of pending + connections, creates a new connected socket, and returns a new file + descriptor referring to that socket. + + The newly created socket is not in the listening state. The + original socket sd is unaffected by this call. + + The argument sd is a socket that has been created with + SlNetSock_create(), bound to a local address with + SlNetSock_bind(), and is listening for connections after a + SlNetSock_listen(). + + The argument \c addr is a pointer to a sockaddr structure. This + structure is filled in with the address of the peer socket, as + known to the communications layer. + + The exact format of the address returned \c addr is determined by the socket's address family. + + \c addrlen is a value-result argument: it should initially contain + the size of the structure pointed to by addr, on return it will + contain the actual length (in bytes) of the address returned. + + \param[in] sd Socket descriptor (handle) + \param[out] addr The argument addr is a pointer + to a sockaddr structure. This + structure is filled in with the + address of the peer socket, as + known to the communications + layer. The exact format of the + address returned addr is + determined by the socket's + address\n + sockaddr:\n - code for the + address format.\n - + socket address, the length + depends on the code format + \param[out] addrlen The addrlen argument is a value-result + argument: it should initially contain the + size of the structure pointed to by addr + + \return On success, a socket descriptor.\n + On a non-blocking accept a possible negative value is #SLNETERR_BSD_EAGAIN.\n + On failure, negative error code.\n + #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system + + \slnetsock_init_precondition + + \sa SlNetSock_create() + \sa SlNetSock_bind() + \sa SlNetSock_listen() +*/ +int16_t SlNetSock_accept(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); + + +/*! + \brief Assign a name to a socket + + This SlNetSock_bind function gives the socket the local address + addr. addr is addrlen bytes long. + + Traditionally, this is called when a socket is created with + socket, it exists in a name space (address family) but has no name + assigned. + + It is necessary to assign a local address before a #SLNETSOCK_SOCK_STREAM + socket may receive connections. + + \param[in] sd Socket descriptor (handle) + \param[in] addr Specifies the destination + addrs\n sockaddr:\n - code for + the address format.\n - socket address, + the length depends on the code + format + \param[in] addrlen Contains the size of the structure pointed to by addr + + \return Zero on success, or negative error code on failure + + \slnetsock_init_precondition + + \sa SlNetSock_create() + \sa SlNetSock_accept() + \sa SlNetSock_listen() +*/ +int32_t SlNetSock_bind(int16_t sd, const SlNetSock_Addr_t *addr, int16_t addrlen); + + +/*! + \brief Listen for connections on a socket + + The willingness to accept incoming connections and a queue + limit for incoming connections are specified with SlNetSock_listen(), + and then the connections are accepted with SlNetSock_accept(). + + \param[in] sd Socket descriptor (handle) + \param[in] backlog Specifies the listen queue depth. + + \return Zero on success, or negative error code on failure + + \slnetsock_init_precondition + + \remark The SlNetSock_listen() call applies only to sockets of + type #SLNETSOCK_SOCK_STREAM. + + \remark The \c backlog parameter defines the maximum length the queue of + pending connections may grow to. + + \sa SlNetSock_create() + \sa SlNetSock_accept() + \sa SlNetSock_bind() +*/ +int32_t SlNetSock_listen(int16_t sd, int16_t backlog); + + +/*! + \brief Initiate a connection on a socket + + Function connects the socket referred to by the socket + descriptor sd, to the address specified by \c addr. + + The format of the address in addr is determined by the address + space of the socket. + + If it is of type #SLNETSOCK_SOCK_DGRAM, this call specifies the + peer with which the socket is to be associated; this address is + that to which datagrams are to be sent, and the only address from + which datagrams are to be received. + + If the socket is of type #SLNETSOCK_SOCK_STREAM, this call + attempts to make a connection to another socket. + + The other socket is specified by address, which is an address in + the communications space of the socket. + + \param[in] sd Socket descriptor (handle) + \param[in] addr Specifies the destination addr\n + sockaddr:\n - code for the + address format.\n - + socket address, the length + depends on the code format + \param[in] addrlen Contains the size of the structure pointed + to by addr + + \return On success, a socket descriptor (handle).\n + On failure, negative value.\n + On a non-blocking connect a possible negative value is #SLNETERR_BSD_EALREADY. + #SLNETERR_POOL_IS_EMPTY may be returned in case there are no resources in the system + + \slnetsock_init_precondition + + \sa SlNetSock_create() + \note + \warning +*/ +int32_t SlNetSock_connect(int16_t sd, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen); + +/*! + \brief Return address info about the remote side of the connection + + Returns a struct SlNetSock_AddrIn_t + filled with information about the peer device that is connected + on the other side of the socket descriptor. + + \param[in] sd Socket descriptor (handle) + \param[out] addr returns the struct addr\n + SlNetSockAddrIn filled with information + about the peer device:\n - code for the + address format.\n - + socket address, the length + depends on the code format + \param[out] addrlen Contains the size of the structure pointed + to by addr + + \return Zero on success, or negative error code on failure + + \slnetsock_init_precondition + + \sa SlNetSock_accept() + \sa SlNetSock_connect() +*/ +int32_t SlNetSock_getPeerName(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); + + +/*! + \brief Get local address info by socket descriptor + + Returns the local address info of the socket descriptor. + + \param[in] sd Socket descriptor (handle) + \param[out] addr The argument addr is a pointer + to a SlNetSock_Addr_t structure. This + structure is filled in with the + address of the peer socket, as + known to the communications + layer. The exact format of the + address returned addr is + determined by the socket's + address\n + SlNetSock_Addr_t:\n - code for the + address format.\n - + socket address, the length + depends on the code format + \param[out] addrlen The addrlen argument is a value-result + argument: it should initially contain the + size of the structure pointed to by addr + + \return Zero on success, or negative on failure. + + \slnetsock_init_precondition + + \remark If the provided buffer is too small the returned address + will be truncated and \c addrlen will contain the + actual size of the socket address. + + \sa SlNetSock_create() + \sa SlNetSock_bind() +*/ +int32_t SlNetSock_getSockName(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); + + +/*! + \brief Monitor socket activity + + SlNetSock_select() allow a program to monitor multiple file descriptors, + waiting until one or more of the file descriptors become + "ready" for some class of I/O operation. + + \param[in] nsds The highest-numbered file descriptor in any of the + three sets, plus 1. + \param[in,out] readsds Socket descriptors list for read monitoring and accept monitoring + \param[in,out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported + \param[in,out] exceptsds Socket descriptors list for exception monitoring, not supported. + \param[in] timeout Is an upper bound on the amount of time elapsed + before SlNetSock_select() returns. Null or above 0xffff seconds means + infinity timeout. The minimum timeout is 10 milliseconds, + less than 10 milliseconds will be set automatically to 10 milliseconds. + Max microseconds supported is 0xfffc00. + In trigger mode the timeout fields must be set to zero. + + \return On success, SlNetSock_select() returns the number of + file descriptors contained in the three returned + descriptor sets (that is, the total number of bits that + are set in readsds, writesds, exceptsds) which may be + zero if the timeout expires before anything interesting + happens.\n On error, a negative value is returned. + readsds - return the sockets on which Read request will + return without delay with valid data.\n + writesds - return the sockets on which Write request + will return without delay.\n + exceptsds - return the sockets closed recently. \n + #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system + + \slnetsock_init_precondition + + \remark If \c timeout is set to less than 10ms it will + automatically set to 10ms to prevent overload of the + system + + \sa SlNetSock_create() +*/ +int32_t SlNetSock_select(int16_t nsds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); + + +/*! + \brief SlNetSock_select's SlNetSock_SdSet_t SET function + + Sets current socket descriptor on SlNetSock_SdSet_t container +*/ +int32_t SlNetSock_sdsSet(int16_t sd, SlNetSock_SdSet_t *sdset); + + +/*! + \brief SlNetSock_select's SlNetSock_SdSet_t CLR function + + Clears current socket descriptor on SlNetSock_SdSet_t container +*/ +int32_t SlNetSock_sdsClr(int16_t sd, SlNetSock_SdSet_t *sdset); + + +/*! + \brief SlNetSock_select's SlNetSock_SdSet_t ZERO function + + Clears all socket descriptors from SlNetSock_SdSet_t +*/ +int32_t SlNetSock_sdsClrAll(SlNetSock_SdSet_t *sdset); + + +/*! + \brief SlNetSock_select's SlNetSock_SdSet_t ISSET function + + Checks if current socket descriptor is set (true/false) + + \return Returns true if set, false if unset + +*/ +int32_t SlNetSock_sdsIsSet(int16_t sd, SlNetSock_SdSet_t *sdset); + + +/*! + \brief Set socket options + + SlNetSock_setOpt() manipulates the options associated with a socket. + + Options may exist at multiple protocol levels; they are always + present at the uppermost socket level. + + When manipulating socket options the level at which the option resides + and the name of the option must be specified. To manipulate options at + the socket level, level is specified as #SLNETSOCK_LVL_SOCKET. To manipulate + options at any other level the protocol number of the appropriate protocol + controlling the option is supplied. For example, to indicate that an + option is to be interpreted by the TCP protocol, level should be set to + the protocol number of TCP. + + \c optval and \c optlen are used to access opt_values + for SlNetSock_setOpt(). For SlNetSock_getOpt() they identify a + buffer in which the value for the requested option(s) are to + be returned. For SlNetSock_getOpt(), \c optlen is a value-result + parameter, initially containing the size of the buffer + pointed to by option_value, and modified on return to + indicate the actual size of the value returned. If no option + value is to be supplied or returned, \c optval may be \c NULL. + + \param[in] sd Socket descriptor (handle) + \param[in] level Defines the protocol level for this option + - #SLNETSOCK_LVL_SOCKET - Socket level configurations (L4, transport layer) + - #SLNETSOCK_LVL_IP - IP level configurations (L3, network layer) + - #SLNETSOCK_LVL_PHY - Link level configurations (L2, link layer) + \param[in] optname Defines the option name to interrogate + - #SLNETSOCK_LVL_SOCKET + - #SLNETSOCK_OPSOCK_RCV_BUF\n + Sets tcp max recv window size.\n + This options takes SlNetSock_Winsize_t struct as parameter + - #SLNETSOCK_OPSOCK_RCV_TIMEO\n + Sets the timeout value that specifies the maximum amount of time an input function waits until it completes.\n + Default: No timeout\n + This options takes SlNetSock_Timeval_t struct as parameter + - #SLNETSOCK_OPSOCK_KEEPALIVE\n + Enable or Disable periodic keep alive. + Keeps TCP connections active by enabling the periodic transmission of messages \n + Timeout is 5 minutes.\n + Default: Enabled \n + This options takes SlNetSock_Keepalive_t struct as parameter + - #SLNETSOCK_OPSOCK_KEEPALIVE_TIME\n + Set keep alive timeout. + Value is in seconds \n + Default: 5 minutes \n + - #SLNETSOCK_OPSOCK_LINGER\n + Socket lingers on close pending remaining send/receive packets\n + - #SLNETSOCK_OPSOCK_NON_BLOCKING\n + Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n + Default: Blocking. + This options takes SlNetSock_Nonblocking_t struct as parameter + - #SLNETSOCK_OPSOCK_NON_IP_BOUNDARY\n + Enable or Disable rx ip boundary. + In connectionless socket (udp/raw), unread data is dropped (when SlNetSock_recvFrom() len parameter < data size), Enable this option in order to read the left data on the next SlNetSock_recvFrom() iteration\n + Default: Disabled, IP boundary kept\n + This options takes SlNetSock_NonIpBoundary_t struct as parameter + - #SLNETSOCK_LVL_IP + - #SLNETSOCK_OPIP_MULTICAST_TTL\n + Set the time-to-live value of outgoing multicast packets for this socket. \n + This options takes uint8_t as parameter + - #SLNETSOCK_OPIP_ADD_MEMBERSHIP \n + UDP socket, Join a multicast group. \n + This options takes SlNetSock_IpMreq_t struct as parameter + - #SLNETSOCK_OPIP_DROP_MEMBERSHIP \n + UDP socket, Leave a multicast group \n + This options takes SlNetSock_IpMreq_t struct as parameter + - #SLNETSOCK_OPIP_HDRINCL \n + RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n + the IP_HDRINCL socket option is enabled on the socket. \n + When it is enabled, the packet must contain an IP header. \n + Default: disabled, IPv4 header generated by Network Stack \n + This options takes uint32_t as parameter + - #SLNETSOCK_OPIP_RAW_RX_NO_HEADER \n + Raw socket remove IP header from received data. \n + Default: data includes ip header \n + This options takes uint32_t as parameter + - #SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (inactive) \n + RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n + the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n + Default: disabled, IPv4 header generated by Network Stack \n + This options takes uint32_t as parameter + - #SLNETSOCK_LVL_PHY + - #SLNETSOCK_OPPHY_CHANNEL \n + Sets channel in transceiver mode. + This options takes uint32_t as channel number parameter + - #SLNETSOCK_OPPHY_RATE \n + RAW socket, set WLAN PHY transmit rate \n + The values are based on SlWlanRateIndex_e \n + This options takes uint32_t as parameter + - #SLNETSOCK_OPPHY_TX_POWER \n + RAW socket, set WLAN PHY TX power \n + Valid rage is 1-15 \n + This options takes uint32_t as parameter + - #SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX \n + RAW socket, set number of frames to transmit in transceiver mode. + Default: 1 packet + This options takes uint32_t as parameter + - #SLNETSOCK_OPPHY_PREAMBLE \n + RAW socket, set WLAN PHY preamble for Long/Short\n + This options takes uint32_t as parameter + - #SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD \n + RAW socket, set WLAN Tx - Set CCA threshold. \n + The values are based on SlNetSockTxInhibitThreshold_e \n + This options takes uint32_t as parameter + - #SLNETSOCK_OPPHY_TX_TIMEOUT \n + RAW socket, set WLAN Tx - changes the TX timeout (lifetime) of transceiver frames. \n + Value in Ms, maximum value is 10ms \n + This options takes uint32_t as parameter + - #SLNETSOCK_OPPHY_ALLOW_ACKS \n + RAW socket, set WLAN Tx - Enable or Disable sending ACKs in transceiver mode \n + 0 = disabled / 1 = enabled \n + This options takes uint32_t as parameter + + + \param[in] optval Specifies a value for the option + \param[in] optlen Specifies the length of the + option value + + \return Zero on success, or negative error code on failure + + \par Persistent + All params are Non- Persistent + + \slnetsock_init_precondition + + \par Examples + + - SLNETSOCK_OPSOCK_RCV_BUF: + \code + SlNetSock_Winsize_t size; + size.winsize = 3000; // bytes + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_BUF, (uint8_t *)&size, sizeof(size)); + \endcode +
+ + - SLNETSOCK_OPSOCK_RCV_TIMEO: + \code + struct SlNetSock_Timeval_t timeVal; + timeVal.tv_sec = 1; // Seconds + timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_TIMEO, (uint8_t *)&timeVal, sizeof(timeVal)); // Enable receive timeout + \endcode +
+ + - SLNETSOCK_OPSOCK_KEEPALIVE: //disable Keepalive + \code + SlNetSock_Keepalive_t enableOption; + enableOption.keepaliveEnabled = 0; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE, (uint8_t *)&enableOption, sizeof(enableOption)); + \endcode +
+ + - SLNETSOCK_OPSOCK_KEEPALIVE_TIME: //Set Keepalive timeout + \code + int16_t Status; + uint32_t TimeOut = 120; + SlNetSock_setOpt(Sd, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE_TIME, (uint8_t *)&TimeOut, sizeof(TimeOut)); + \endcode +
+ + - SLNETSOCK_OPSOCK_NON_BLOCKING: //Enable or disable nonblocking mode + \code + SlNetSock_Nonblocking_t enableOption; + enableOption.nonBlockingEnabled = 1; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_BLOCKING, (uint8_t *)&enableOption, sizeof(enableOption)); + \endcode +
+ + - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY: //disable boundary + \code + SlNetSock_NonIpBoundary_t enableOption; + enableOption.nonIpBoundaryEnabled = 1; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_IP_BOUNDARY, (uint8_t *)&enableOption, sizeof(enableOption)); + \endcode +
+ + - SLNETSOCK_OPSOCK_LINGER: + \code + SlNetSock_linger_t linger; + linger.l_onoff = 1; + linger.l_linger = 10; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_LINGER, &linger, sizeof(linger)); + \endcode +
+ + - SLNETSOCK_OPIP_MULTICAST_TTL: + \code + uint8_t ttl = 20; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_MULTICAST_TTL, &ttl, sizeof(ttl)); + \endcode +
+ + - SLNETSOCK_OPIP_ADD_MEMBERSHIP: + \code + SlNetSock_IpMreq_t mreq; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); + \endcode +
+ + - SLNETSOCK_OPIP_DROP_MEMBERSHIP: + \code + SlNetSock_IpMreq_t mreq; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); + \endcode +
+ + - SLNETSOCK_OPIP_RAW_RX_NO_HEADER: + \code + uint32_t header = 1; // remove ip header + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_RX_NO_HEADER, &header, sizeof(header)); + \endcode +
+ + - SLNETSOCK_OPIP_HDRINCL: + \code + uint32_t header = 1; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_HDRINCL, &header, sizeof(header)); + \endcode +
+ + - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL: + \code + uint32_t header = 1; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_IPV6_HDRINCL, &header, sizeof(header)); + \endcode +
+ + - SLNETSOCK_OPPHY_CHANNEL: + \code + uint32_t newChannel = 6; // range is 1-13 + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPPHY_CHANNEL, &newChannel, sizeof(newChannel)); + \endcode +
+ + - SLNETSOCK_OPPHY_RATE: + \code + uint32_t rate = 6; // see wlan.h SlWlanRateIndex_e for values + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_RATE, &rate, sizeof(rate)); + \endcode +
+ + - SLNETSOCK_OPPHY_TX_POWER: + \code + uint32_t txpower = 1; // valid range is 1-15 + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_POWER, &txpower, sizeof(txpower)); + \endcode +
+ + - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX: + \code + uint32_t numframes = 1; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); + \endcode +
+ + - SLNETSOCK_OPPHY_PREAMBLE: + \code + uint32_t preamble = 1; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_PREAMBLE, &preamble, sizeof(preamble)); + \endcode +
+ + - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD: + \code + uint32_t thrshld = SLNETSOCK_TX_INHIBIT_THRESHOLD_MED; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD, &thrshld, sizeof(thrshld)); + \endcode +
+ + - SLNETSOCK_OPPHY_TX_TIMEOUT: + \code + uint32_t timeout = 50; + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_TIMEOUT, &timeout, sizeof(timeout)); + \endcode +
+ + - SLNETSOCK_OPPHY_ALLOW_ACKS: + \code + uint32_t acks = 1; // 0 = disabled / 1 = enabled + SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_ALLOW_ACKS, &acks, sizeof(acks)); + \endcode + + \sa slNetSock_create() + \sa SlNetSock_getOpt() +*/ +int32_t SlNetSock_setOpt(int16_t sd, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); + + +/*! + \brief Get socket options + + The SlNetSock_getOpt function gets the options associated with a socket. + Options may exist at multiple protocol levels; they are always + present at the uppermost socket level. + + The parameters optval and optlen identify a + buffer in which the value for the requested option(s) are to + be returned. \c optlen is a value-result + parameter, initially containing the size of the buffer + pointed to by option_value, and modified on return to + indicate the actual size of the value returned. If no option + value is to be supplied or returned, \c optval may be \c NULL. + + + \param[in] sd Socket descriptor (handle) + \param[in] level Defines the protocol level for this option + \param[in] optname defines the option name to interrogate + \param[out] optval Specifies a value for the option + \param[out] optlen Specifies the length of the + option value + + \return Zero on success, or negative error code on failure + + \slnetsock_init_precondition + + \sa SlNetSock_create() + \sa SlNetSock_setOpt() +*/ +int32_t SlNetSock_getOpt(int16_t sd, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); + + +/*! + \brief Read data from TCP socket + + The SlNetSock_recv function receives a message from a connection-mode socket + + \param[in] sd Socket descriptor (handle) + \param[out] buf Points to the buffer where the + message should be stored. + \param[in] len Specifies the length in bytes of + the buffer pointed to by the buffer argument. + Range: 1-16000 bytes + \param[in] flags Specifies the type of message + reception. On this version, this parameter is not + supported. + + \return Return the number of bytes received, + or a negative value if an error occurred.\n + Using a non-blocking recv a possible negative value is SLNETERR_BSD_EAGAIN.\n + SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system + + \slnetsock_init_precondition + + \par Examples + + - Receiving data using TCP socket: + \code + SlNetSock_AddrIn_t Addr; + SlNetSock_AddrIn_t LocalAddr; + int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); + int16_t SockID, newSockID; + int16_t Status; + int8_t Buf[RECV_BUF_LEN]; + + LocalAddr.sin_family = SLNETSOCK_AF_INET; + LocalAddr.sin_port = SlNetSock_htons(5001); + LocalAddr.sin_addr.s_addr = 0; + + Addr.sin_family = SLNETSOCK_AF_INET; + Addr.sin_port = SlNetSock_htons(5001); + Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); + + SockID = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); + Status = SlNetSock_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); + Status = SlNetSock_listen(SockID, 0); + newSockID = SlNetSock_accept(SockID, (SlNetSock_Addr_t *)&Addr, (SlNetSocklen_t *)&AddrSize); + Status = SlNetSock_recv(newSockID, Buf, 1460, 0); + \endcode +
+ + - Rx transceiver mode using a raw socket: + \code + int8_t buffer[1536]; + int16_t sd; + uint16_t size; + SlNetSock_TransceiverRxOverHead_t *transHeader; + sd = SlNetSock_create(SLNETSOCK_AF_RF, SLNETSOCK_SOCK_RAW, 11, 0, 0); // channel 11 + while(1) + { + size = SlNetSock_recv(sd,buffer,1536,0); + transHeader = (SlNetSock_TransceiverRxOverHead_t *)buffer; + printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlNetSock_TransceiverRxOverHead_t)],size); + } + \endcode + + \sa SlNetSock_create() + \sa SlNetSock_recvFrom() +*/ +int32_t SlNetSock_recv(int16_t sd, void *buf, uint32_t len, uint32_t flags); + + +/*! + \brief Read data from socket + + SlNetSock_recvFrom function receives a message from a connection-mode or + connectionless-mode socket + + \param[in] sd Socket descriptor (handle) + \param[out] buf Points to the buffer where the message should be stored. + \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. + Range: 1-16000 bytes + \param[in] flags Specifies the type of message + reception. On this version, this parameter is not + supported + \param[in] from Pointer to an address structure + indicating the source + address.\n sockaddr:\n - code + for the address format.\n - socket address, + the length depends on the code + format + \param[in] fromlen Source address structure + size. This parameter MUST be set to the size of the structure pointed to by addr. + + + \return Return the number of bytes received, + or a negative value if an error occurred.\n + Using a non-blocking recv a possible negative value is #SLNETERR_BSD_EAGAIN. + #SLNETERR_RET_CODE_INVALID_INPUT will be returned if fromlen has incorrect length.\n + #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system + + \slnetsock_init_precondition + + \par Example + + - Receiving data: + \code + SlNetSock_AddrIn_t Addr; + SlNetSock_AddrIn_t LocalAddr; + int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); + int16_t SockID; + int16_t Status; + int8_t Buf[RECV_BUF_LEN]; + + LocalAddr.sin_family = SLNETSOCK_AF_INET; + LocalAddr.sin_port = SlNetSock_htons(5001); + LocalAddr.sin_addr.s_addr = 0; + + SockID = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); + Status = SlNetSock_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); + Status = SlNetSock_recvFrom(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, (SlNetSocklen_t*)&AddrSize); + + \endcode + + \sa SlNetSock_create() + \sa SlNetSock_recv() +*/ +int32_t SlNetSock_recvFrom(int16_t sd, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); + + +/*! + \brief Write data to TCP socket + + Transmits a message to another socket. + Returns immediately after sending data to device. + In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the + frame data buffer for WLAN FCS + + \param[in] sd Socket descriptor (handle) + \param[in] buf Points to a buffer containing + the message to be sent + \param[in] len Message size in bytes. + \param[in] flags Specifies the type of message + transmission. On this version, this parameter is not + supported for TCP. + + \return Return the number of bytes sent, + or a negative value if an error occurred. + + \slnetsock_init_precondition + + \par Example + + - Sending data: + \code + SlNetSock_AddrIn_t Addr; + int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); + int16_t SockID; + int16_t Status; + int8_t Buf[SEND_BUF_LEN]; + + Addr.sin_family = SLNETSOCK_AF_INET; + Addr.sin_port = SlNetSock_htons(5001); + Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); + + SockID = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); + Status = SlNetSock_connect(SockID, (SlNetSock_Addr_t *)&Addr, AddrSize); + Status = SlNetSock_send(SockID, Buf, 1460, 0 ); + \endcode + + \sa SlNetSock_create() + \sa SlNetSock_sendTo() +*/ +int32_t SlNetSock_send(int16_t sd, const void *buf, uint32_t len, uint32_t flags); + + +/*! + \brief Write data to socket + + The SlNetSock_sendTo function is used to transmit a message on a connectionless socket + (connection less socket #SLNETSOCK_SOCK_DGRAM, #SLNETSOCK_SOCK_RAW). + + Returns immediately after sending data to device. + + \param[in] sd Socket descriptor (handle) + \param[in] buf Points to a buffer containing + the message to be sent + \param[in] len message size in bytes. + \param[in] flags Specifies the type of message + transmission. On this version, this parameter is not + supported + \param[in] to Pointer to an address structure + indicating the destination + address.\n sockaddr:\n - code + for the address format.\n - socket address, + the length depends on the code + format + \param[in] tolen Destination address structure size + + \return Return the number of bytes sent, + or a negative value if an error occurred.\n + + \slnetsock_init_precondition + + \par Example + + - Sending data: + \code + SlNetSock_AddrIn_t Addr; + int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); + int16_t SockID; + int16_t Status; + int8_t Buf[SEND_BUF_LEN]; + + Addr.sin_family = SLNETSOCK_AF_INET; + Addr.sin_port = SlNetSock_htons(5001); + Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); + + SockID = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); + Status = SlNetSock_sendTo(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, AddrSize); + \endcode + + \sa SlNetSock_create() + \sa SlNetSock_send() +*/ +int32_t SlNetSock_sendTo(int16_t sd, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); + + +/*! + \brief Get interface ID from socket descriptor (sd) + + Retrieves the priority of the requested interface. + + \param[in] sd Specifies the socket descriptor which its + interface identifier needs to be retrieved.\n + + \return The interface identifier value of the + interface on success, or negative error code + on failure The values of the interface + identifier is defined with the prefix + SLNETIF_ID_ which defined in slnetif.h + + \slnetsock_init_precondition + + \par Examples + + \code + int16_t InterfaceID; + InterfaceID = SlNetSock_getIfID(SLNETIF_ID_1); + \endcode + + \sa SlNetSock_create() + \sa SlNetIf_add() + \sa SlNetIf_getIDByName() +*/ +int32_t SlNetSock_getIfID(uint16_t sd); + + +/*! + \brief Creates a security attributes object + + Create a security attribute, which is required in order to start a secure session. + + \remark When the security attributes object is no longer needed, call + SlNetSock_secAttribDelete() to destroy it. + + \remark A single security object can be used to initiate several secure + sessions (provided they all have the same security attributes). + + \slnetsock_init_precondition + + \sa SlNetSock_startSec() + \sa SlNetSock_secAttribDelete() +*/ +SlNetSockSecAttrib_t *SlNetSock_secAttribCreate(void); + + +/*! + \brief Deletes a security attributes object + + \param[in] secAttrib Secure attribute handle + + \return Zero on success, or negative error code + on failure + + \slnetsock_init_precondition + + \remark \c secAttrib must be created using SlNetSock_secAttribCreate() + + \sa SlNetSock_secAttribCreate() + \sa SlNetSock_secAttribSet() + \sa SlNetSock_startSec() +*/ +int32_t SlNetSock_secAttribDelete(SlNetSockSecAttrib_t *secAttrib); + + +/*! + \brief set a security attribute + + The SlNetSock_secAttribSet function is used to set a security + attribute of a security attribute object. + + \param[in] secAttrib Secure attribute handle + \param[in] attribName Define the actual attribute to set. Applicable values: + - #SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY \n + Sets the private key corresponding to the local certificate \n + This attribute takes the name of security object containing the private key and the name's length (including the NULL terminating character) as parameters \n + - #SLNETSOCK_SEC_ATTRIB_LOCAL_CERT \n + Sets the local certificate chain \n + This attribute takes the name of the security object containing the certificate and the name's length (including the NULL terminating character) as parameters \n + For certificate chains, each certificate in the chain can be added via a separate call to SlNetSock_secAttribSet, starting with the root certificate of the chain \n + - #SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA \n + Sets the root CA certificate \n + This attribute takes the name of the security object containing the certificate and the name's length (including the NULL terminating character) as parameters \n + - #SLNETSOCK_SEC_ATTRIB_DH_KEY \n + Sets the DH Key \n + This attribute takes the name of the security object containing the DH Key and the name's length (including the NULL terminating character) as parameters \n + - #SLNETSOCK_SEC_ATTRIB_METHOD \n + Sets the TLS protocol version \n + This attribute takes a SLNETSOCK_SEC_METHOD_* option and sizeof(uint8_t) as parameters \n + - #SLNETSOCK_SEC_ATTRIB_CIPHERS \n + Sets the ciphersuites to be used for the connection \n + This attribute takes a bit mask formed using SLNETSOCK_SEC_CIPHER_* options and sizeof(uint32_t) as parameters \n + - #SLNETSOCK_SEC_ATTRIB_ALPN \n + Sets the ALPN \n + This attribute takes a bit mask formed using SLNETSOCK_SEC_ALPN_* options and sizeof(uint32_t) as parameters \n + - #SLNETSOCK_SEC_ATTRIB_EXT_CLIENT_CHLNG_RESP \n + Sets the EXT CLIENT CHLNG RESP \n + Format TBD \n + - #SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME \n + Sets the domain name for verification during connection \n + This attribute takes a string with the domain name and the string's length (including the NULL-terminating character) as parameters \n + - #SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE\n + Sets whether to disable the certificate store \n + This attribute takes 1 (disable) or 0 (enable) and sizeof(uint32_t) as parameters \n + + \param[in] val + \param[in] len + + \return Zero on success, or negative error code + on failure + + \slnetsock_init_precondition + + \note Once an attribute is set, it cannot be unset or set to something + different. Doing so may result in undefined behavior. + Instead, SlNetSock_secAttribDelete() should be called on the + existing object, and a new security object should be created with + the new attribute set. + + \note The @c SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE value + is currently being evaluated, and may be removed in a + future release. It is currently only supported on CC3x20 + devices. For more details, see + #SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE. + + \par Examples + + - SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY: + \code + #define PRIVATE_KEY_FILE "DummyKey" + SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY, PRIVATE_KEY_FILE, strlen(PRIVATE_KEY_FILE), srvKeyPem, srvKeyPemLen, SLNETIF_ID_2); + SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY, PRIVATE_KEY_FILE, sizeof(PRIVATE_KEY_FILE)); + \endcode +
+ + - SLNETSOCK_SEC_ATTRIB_LOCAL_CERT: + \code + #define ROOT_CA_CERT_FILE "DummyCA" + #define TRUSTED_CERT_FILE "DummyTrustedCert" + + // create a local certificate chain + SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, ROOT_CA_CERT_FILE, strlen(ROOT_CA_CERT_FILE), srvCAPem, srvCAPemLen, SLNETIF_ID_2); + SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, TRUSTED_CERT_FILE, strlen(TRUSTED_CERT_FILE), srvCertPem, srvCertPemLen, SLNETIF_ID_2); + SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_LOCAL_CERT, ROOT_CA_CERT_FILE, sizeof(ROOT_CA_CERT_FILE)); + SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_LOCAL_CERT, TRUSTED_CERT_FILE, sizeof(TRUSTED_CERT_FILE)); + \endcode +
+ + - SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA: + \code + #define ROOT_CA_CERT_FILE "DummyCA" + SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, ROOT_CA_CERT_FILE, strlen(ROOT_CA_CERT_FILE), srvCAPem, srvCAPemLen, SLNETIF_ID_2); + SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA, ROOT_CA_CERT_FILE, sizeof(ROOT_CA_CERT_FILE)); + \endcode +
+ + - SLNETSOCK_SEC_ATTRIB_METHOD: + \code + uint8_t SecurityMethod = SLNETSOCK_SEC_METHOD_SSLV3; + SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_METHOD, (void *)&(SecurityMethod), sizeof(SecurityMethod)); + \endcode +
+ + - SLNETSOCK_SEC_ATTRIB_CIPHERS: + \code + uint32_t SecurityCipher = SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_SHA | SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA; + SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_METHOD, (void *)&(SecurityCipher), sizeof(SecurityCipher)); + \endcode +
+ + - SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME: + \code + char addr[] = "www.ti.com"; + SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME, (void *)addr, strlen(addr) + 1); + \endcode +
+ + + \sa SlNetSock_secAttribCreate() +*/ +int32_t SlNetSock_secAttribSet(SlNetSockSecAttrib_t *secAttrib, SlNetSockSecAttrib_e attribName, void *val, uint16_t len); + + +/*! + \brief Start a security session on an opened socket + + \param[in] sd Socket descriptor (handle) + \param[in] secAttrib Secure attribute handle. This can be NULL only + if the SLNETSOCK_SEC_BIND_CONTEXT_ONLY flag is + not thrown. + \param[in] flags Specifies flags. \n + The available flags are: + - #SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY + - #SLNETSOCK_SEC_BIND_CONTEXT_ONLY + - #SLNETSOCK_SEC_IS_SERVER + + \return Zero on success, or negative error code + on failure + + \slnetsock_init_precondition + + \remark If \c secAttrib is \c NULL, the session will be started with + default security settings. + + \sa SlNetSock_create() + \sa SlNetSock_secAttribCreate() +*/ +int32_t SlNetSock_startSec(int16_t sd, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); + + +/*! + + Close the Doxygen group. + @} + +*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NET_SOCK_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetutils.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetutils.h new file mode 100755 index 00000000000..51eb8d1e04f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/net/slnetutils.h @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#ifndef __SL_NET_UTILS_H__ +#define __SL_NET_UTILS_H__ + +#include "slnetsock.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \defgroup SlNetUtils SlNetUtils group + + \short Sockets related commands and configuration + +*/ +/*! + + \addtogroup SlNetUtils + @{ + +*/ + +/*****************************************************************************/ +/* Structure/Enum declarations */ +/*****************************************************************************/ + +/* Creating one address parameter from 4 separate address parameters */ +#define SLNETUTIL_IPV4_VAL(add_3,add_2,add_1,add_0) ((((uint32_t)add_3 << 24) & 0xFF000000) | (((uint32_t)add_2 << 16) & 0xFF0000) | (((uint32_t)add_1 << 8) & 0xFF00) | ((uint32_t)add_0 & 0xFF) ) + +/*****************************************************************************/ +/* Function prototypes */ +/*****************************************************************************/ + +/*! + + \brief Initialize the SlNetUtil module + + \param[in] flags Reserved + + \return Zero on success, or negative error code on failure +*/ +int32_t SlNetUtil_init(int32_t flags); + +/*! + \brief Get host IP by name\n + Obtain the IP Address of machine on network, by machine name. + + \param[in] ifBitmap Specifies the interfaces which the the host ip + needs to be retrieved from according tothe + priority until one of them will return an answer.\n + Value 0 is used in order to choose automatic + interfaces selection according to the priority + interface list. + Value can be combination of interfaces by OR'ing + multiple interfaces bit identifiers (SLNETIFC_IDENT_ + defined in slnetif.h) + Note: interface identifier bit must be configured + prior to this socket creation using SlNetIf_add(). + \param[in] name Host name + \param[in] nameLen Name length + \param[out] ipAddr This parameter is filled in with an array of + IP addresses. In case that host name is not + resolved, ipAddrLen is zero. + \param[in,out] ipAddrLen Holds the size of the ipAddr array, when function + successful, the ipAddrLen parameter will be updated with + the number of the IP addresses found. + \param[in] family Protocol family + + \return The interface ID of the interface which run + successfully the function, or negative on failure.\n + #SLNETERR_POOL_IS_EMPTY may be return in case + there are no resources in the system\n + Possible DNS error codes: + - #SLNETERR_NET_APP_DNS_QUERY_NO_RESPONSE + - #SLNETERR_NET_APP_DNS_NO_SERVER + - #SLNETERR_NET_APP_DNS_QUERY_FAILED + - #SLNETERR_NET_APP_DNS_MALFORMED_PACKET + - #SLNETERR_NET_APP_DNS_MISMATCHED_RESPONSE + + \slnetutil_init_precondition + + \warning + In case an IP address in a string format is set as input, without + any prefix (e.g. "1.2.3.4") the device will not try to access the + DNS and it will return the input address in the \c ipAddr field + \par Example + - Getting IPv4 using get host by name: + \code + uint16_t DestIPListSize = 1; + uint32_t DestIP[1]; + uint32_t ifID; + int16_t SockId; + SlNetSock_AddrIn_t LocalAddr; //address of the server to connect to + int32_t LocalAddrSize; + + ifID = SlNetUtil_getHostByName(0, "www.google.com", strlen("www.google.com"), DestIP, &DestIPListSize, SLNETSOCK_PF_INET); + + LocalAddr.sin_family = SLNETSOCK_AF_INET; + LocalAddr.sin_addr.s_addr = SlNetUtil_htonl(DestIP[0]); + LocalAddr.sin_port = SlNetUtil_htons(80); + LocalAddrSize = sizeof(SlNetSock_AddrIn_t); + + SockId = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, ifID, 0); + + if (SockId >= 0) + { + status = SlNetSock_connect(SockId, (SlNetSock_Addr_t *)&LocalAddr, LocalAddrSize); + } + \endcode +*/ +int32_t SlNetUtil_getHostByName(uint32_t ifBitmap, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); + + +/*! + \brief Reorder the bytes of a 32-bit unsigned value + + This function is used to reorder the bytes of a 32-bit unsigned value + from host order to network order. + + \param[in] val Variable in host order + + \return Return the variable in network order + + \slnetutil_init_precondition + + \sa SlNetSock_bind() + \sa SlNetSock_connect() + \sa SlNetSock_recvFrom() + \sa SlNetSock_accept() +*/ +uint32_t SlNetUtil_htonl(uint32_t val); + + +/*! + \brief Reorder the bytes of a 32-bit unsigned value + + This function is used to reorder the bytes of a 32-bit unsigned + value from network order to host order. + + \param[in] val Variable in network order + + \return Return the variable in host order + + \slnetutil_init_precondition + + \sa SlNetSock_bind() + \sa SlNetSock_connect() + \sa SlNetSock_recvFrom() + \sa SlNetSock_accept() +*/ +uint32_t SlNetUtil_ntohl(uint32_t val); + + +/*! + \brief Reorder the bytes of a 16-bit unsigned value + + This functions is used to reorder the bytes of a 16-bit unsigned + value from host order to network order. + + \param[in] val Variable in host order + + \return Return the variable in network order + + \slnetutil_init_precondition + + \sa SlNetSock_bind() + \sa SlNetSock_connect() + \sa SlNetSock_recvFrom() + \sa SlNetSock_accept() +*/ +uint16_t SlNetUtil_htons(uint16_t val); + + +/*! + \brief Reorder the bytes of a 16-bit unsigned value + + This functions is used to reorder the bytes of a 16-bit unsigned value + from network order to host order. + + \param[in] val Variable in network order + + \return Return the variable in host order + + \slnetutil_init_precondition + + \sa SlNetSock_bind() + \sa SlNetSock_connect() + \sa SlNetSock_recvFrom() + \sa SlNetSock_accept() +*/ +uint16_t SlNetUtil_ntohs(uint16_t val); + + +/*! + \brief Converts IP address in binary representation to string representation + + This functions is used to converts IP address in binary representation + to IP address in string representation. + + \param[in] addrFamily Specifies the address family of the created + socket + For example: + - #SLNETSOCK_AF_INET for network address IPv4 + - #SLNETSOCK_AF_INET6 for network address IPv6 + \param[in] binaryAddr Pointer to an IP address structure indicating the + address in binary representation + \param[out] strAddr Pointer to the address string representation + for IPv4 or IPv6 according to the address + family + \param[in] strAddrLen Specifies the length of the StrAddress_dst, + the maximum length of the address in string + representation for IPv4 or IPv6 according to + the address family + + \return strAddr on success, or NULL on failure + + \slnetutil_init_precondition + + \par Example + - IPv4 demo of inet_ntop() + \code + SlNetSock_AddrIn_t sa; + char str[SLNETSOCK_INET_ADDRSTRLEN]; + + // store this IP address in sa: + SlNetUtil_inetPton(SLNETSOCK_AF_INET, "192.0.2.33", &(sa.sin_addr)); + // now get it back and print it + SlNetUtil_inetNtop(SLNETSOCK_AF_INET, &(sa.sin_addr), str, SLNETSOCK_INET_ADDRSTRLEN); + \endcode +*/ +const char *SlNetUtil_inetNtop(int16_t addrFamily, const void *binaryAddr, char *strAddr, SlNetSocklen_t strAddrLen); + + +/*! + \brief Converts IP address in string representation to binary representation + + This functions is used to converts IP address in string representation + to IP address in binary representation. + + \param[in] addrFamily Specifies the address family of the created + socket + For example: + - #SLNETSOCK_AF_INET for network address IPv4 + - #SLNETSOCK_AF_INET6 for network address IPv6 + \param[out] strAddr Specifies the IP address in string representation + for IPv4 or IPv6 according to the address + family + \param[in] binaryAddr Pointer to an address structure that will be + filled by the IP address in Binary representation + + \return 1 on success, -1 on failure, or 0 if the input + isn't a valid IP address + + \slnetutil_init_precondition + + \par Example + - IPv6 demo of inet_pton() + \code + SlNetSock_AddrIn6_t sa; + + // store this IP address in sa: + SlNetUtil_inetPton(SLNETSOCK_AF_INET6, "0:0:0:0:0:0:0:0", &(sa.sin6_addr)); + \endcode +*/ +int32_t SlNetUtil_inetPton(int16_t addrFamily, const char *strAddr, void *binaryAddr); + +/*! + + Close the Doxygen group. + @} + +*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __SL_NET_UTILS_H__ */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c new file mode 100644 index 00000000000..104a525f19f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c @@ -0,0 +1,89 @@ +/* + * Hardware entropy collector for the CC3200 + * + * Copyright (C) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* + * Reference: section 15.1.1.6 True Random Number in swru455e + */ + +#if defined(DEVICE_TRNG) + +#include "stdio.h" +#include "trng_api.h" +#include "ti/drivers/net/wifi/netutil.h" +#include "CC3220SF_Init.h" + +void trng_init(trng_t *obj) +{ + static bool trng_initialized = false; + + (void)obj; + if (!trng_initialized) + { + int ret = CC3220SF_initSimplelink(); + if (ret == 0) + { + trng_initialized = true; + } + else + { + printf("trng_init failed with %d\n", ret); + } + } +} + +void trng_free(trng_t *obj) +{ + (void)obj; +} + + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + _u16 bytes_count = length; + _i16 status; + + (void)obj; + /* Retrieve a buffer of true random numbers from the networking subsystem. + Maximum buffer length is 172 bytes for each retrieval. if the requested length exceeds 172 bytes, it is trimmed to 172 bytes.*/ + if (length > 172) + { + bytes_count = 172; + } + if (output) + { + status = sl_NetUtilGet(SL_NETUTIL_TRUE_RANDOM,0,output,&bytes_count); + if (output_length) + { + if (status == 0) + { + *output_length = bytes_count; + return 0; + } + else + { + printf("sl_NetUtilGet failed with %d\n", status); + *output_length = 0; + } + } + } + return -1; +} + +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c new file mode 100644 index 00000000000..4aeb613faf2 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c @@ -0,0 +1,99 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stdlib.h" +#include "us_ticker_api.h" +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/inc/hw_memmap.h" +#include "ti/devices/cc32xx/driverlib/ti_timer.h" + +/* There're 4 timers running from system clock (80MHz). Configure split 16b TimerA timer counting down. We'll post process it to make it appear count up. + * When the timer is configured in periodic down count mode, GPTMTAPR register acts as a true prescaler. A scaler of 80 yields 1MHz timer. + */ +#define US_TICKER_COUNTER_BITS 16u +#define US_TICKER_FREQ 1000000 + +bool us_ticker_initialized = false; + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + US_TICKER_FREQ, + US_TICKER_COUNTER_BITS + }; + return &info; +} +void us_ticker_init(void) +{ + if (!us_ticker_initialized) + { + TimerDisable(TIMERA0_BASE, TIMER_A); + TimerConfigure(TIMERA0_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC); + TimerIntClear(TIMERA0_BASE, TIMER_TIMA_DMA | TIMER_TIMA_MATCH | TIMER_CAPA_EVENT | + TIMER_CAPA_MATCH | TIMER_TIMA_TIMEOUT); + TimerPrescaleSet(TIMERA0_BASE, TIMER_A, (80-1)); + TimerEnable(TIMERA0_BASE, TIMER_A); + NVIC_ClearPendingIRQ(INT_TIMERA0A_IRQn); + NVIC_SetVector(INT_TIMERA0A_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(INT_TIMERA0A_IRQn); + us_ticker_initialized = true; + } + else + { + // Disable match interrupt. This is mbed OS requirement. + TimerIntDisable(TIMERA0_BASE, TIMER_TIMA_MATCH); + // Clear pending interrupt + TimerIntClear(TIMERA0_BASE, TIMER_TIMA_MATCH | TIMER_TIMA_TIMEOUT); + } +} + +uint32_t us_ticker_read(void) +{ + return (0xFFFF & ~TimerValueGet(TIMERA0_BASE, TIMER_A)); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + // Clear pending interrupt + TimerIntClear(TIMERA0_BASE, TIMER_TIMA_MATCH); + TimerMatchSet(TIMERA0_BASE, TIMER_A, 0xFFFF & (~(timestamp & 0xFFFF))); + TimerIntEnable(TIMERA0_BASE, TIMER_TIMA_MATCH); +} + +void us_ticker_disable_interrupt(void) +{ + TimerIntDisable(TIMERA0_BASE, TIMER_TIMA_MATCH); +} + +void us_ticker_clear_interrupt(void) +{ + TimerIntClear(TIMERA0_BASE, TIMER_TIMA_MATCH | TIMER_TIMA_TIMEOUT); +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INT_TIMERA0A_IRQn); +} + +void us_ticker_free(void) +{ + if (us_ticker_initialized) + { + TimerDisable(TIMERA0_BASE, TIMER_A); + NVIC_DisableIRQ(INT_TIMERA0A_IRQn); + us_ticker_initialized = false; + } +} diff --git a/targets/TARGET_TI/mbed_rtx.h b/targets/TARGET_TI/mbed_rtx.h new file mode 100644 index 00000000000..1fe5545ef32 --- /dev/null +++ b/targets/TARGET_TI/mbed_rtx.h @@ -0,0 +1,30 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#include + +#if defined(TARGET_CC3220SF) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20040000UL) +#endif + +#endif /* defined(TARGET_CC3220SF) */ + +#endif /* MBED_MBED_RTX_H */ diff --git a/targets/targets.json b/targets/targets.json index 2c4c1ca3ec1..51ed99def13 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8774,6 +8774,44 @@ "release_versions": ["5"], "device_name": "STM32L151CBxxA" }, + "TI": { + "inherits": ["Target"], + "public": false, + "extra_labels": ["TI"] + }, + "CC32XX": { + "inherits": ["TI"], + "public": false, + "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "release_versions": ["5"] + }, + "CC3220SF": { + "inherits": ["CC32XX"], + "macros": ["MBED_MPU_CUSTOM"], + "core": "Cortex-M4", + "device_name": "CC3220SF" + }, + "CC3220SF_LAUNCHXL": { + "inherits": ["CC3220SF"], + "components_add": ["SD", "FLASHIAP"], + "device_has": ["USTICKER", + "SERIAL", + "SERIAL_FC", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "INTERRUPTIN", + "SPI", + "ANALOGIN", + "FLASH", + "TRNG", + "RTC"], + "bootloader_supported": true, + "overrides": { + "network-default-interface-type": "WIFI" + } + }, "__build_tools_metadata__": { "version": "1", "public": false From 387bb666f472af51f963fa13bd2afc92a98b5019 Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Wed, 17 Jul 2019 14:18:19 -0500 Subject: [PATCH 2/6] Added CC3220 related changes to tools --- tools/arm_pack_manager/index.json | 50 ++++++++++++++++++++++- tools/export/iar/iar_definitions.json | 6 +++ tools/test_configs/CC3220SFInterface.json | 22 ++++++++++ tools/test_configs/config_paths.json | 3 +- tools/test_configs/target_configs.json | 5 +++ 5 files changed, 84 insertions(+), 2 deletions(-) create mode 100644 tools/test_configs/CC3220SFInterface.json diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index 0fe5a9deb27..2ad2d043486 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -472622,5 +472622,53 @@ "sub_family": null, "vendor": "Nordic Semiconductor:54" }, + "CC3220SF": { + "sectors": [ + [ 0, + 2048 + ] + ], + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 262144, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 1048576, + "start": 16777216, + "startup": true + } + }, + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "0", + "mpu": "Present", + "units": 1 + } + }, + "vendor": "TI" + }, "version": "0.2.0" -} \ No newline at end of file +} diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index 9577544d7c9..753aca9dcbc 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -370,5 +370,11 @@ }, "STM32H743ZI": { "OGChipSelectEditMenu": "STM32H743ZI\tST STM32H743ZI" + }, + "CC3220SF": { + "OGChipSelectEditMenu": "CC3220SF\tTexasInstruments CC3220SF", + "CoreVariant": 39, + "GFPUCoreSlave": 39, + "GBECoreSlave": 39 } } diff --git a/tools/test_configs/CC3220SFInterface.json b/tools/test_configs/CC3220SFInterface.json new file mode 100644 index 00000000000..7d3c421127e --- /dev/null +++ b/tools/test_configs/CC3220SFInterface.json @@ -0,0 +1,22 @@ +{ + "config": { + "echo-server-addr" : { + "help" : "IP address of echo server", + "value" : "\"echo.mbedcloudtesting.com\"" + }, + "echo-server-port" : { + "help" : "Port of echo server", + "value" : "7" + } + }, + "target_overrides": { + "*": { + "target.features_add" : ["STORAGE"], + "target.components_add" : ["SD"], + "target.network-default-interface-type": "WIFI", + "nsapi.default-wifi-security" : "WPA_WPA2", + "nsapi.default-wifi-ssid" : "\"SSID\"", + "nsapi.default-wifi-password" : "\"PASSWORD\"" + } + } +} diff --git a/tools/test_configs/config_paths.json b/tools/test_configs/config_paths.json index e8684f6f88a..e51851b1cbc 100644 --- a/tools/test_configs/config_paths.json +++ b/tools/test_configs/config_paths.json @@ -14,5 +14,6 @@ "THREAD_END_DEVICE" : "ThreadInterface_end_device.json", "THREAD_ROUTER" : "ThreadInterface_router.json", "NO_NETWORK": "no_network.json", - "NANOSTACK_MAC_TESTER": "NanostackMACTester.json" + "NANOSTACK_MAC_TESTER": "NanostackMACTester.json", + "CC3220SF_WIFI": "CC3220SFInterface.json" } diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index 5216eb41dab..e9bdb0587e3 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -66,5 +66,10 @@ "TB_SENSE_1": { "default_test_configuration": "NO_NETWORK", "test_configurations": ["6LOWPAN_HOST", "6LOWPAN_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER"] + }, + "CC3220SF": { + "nsapi.socket-stats-enable": true, + "default_test_configuration": "CC3220SF_WIFI", + "test_configurations": ["CC3220SF_WIFI"] } } From 2a06ae20ccbf3fc534e868a91deb1f1262458d2c Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Tue, 23 Jul 2019 14:52:50 -0500 Subject: [PATCH 3/6] Added missing pinmap definitions. Fixed target JSON config to avoid treating cc3220sf a target --- .../TARGET_CC3220SF/PeripheralPins.h | 21 ++++++++- .../PeripheralNames.h | 4 ++ .../TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c | 45 ++++++++++++++++++- .../TARGET_CC3220SF/analogin_api.c | 4 ++ .../TARGET_CC3220SF/pwmout_api.c | 5 +++ .../TARGET_CC3220SF/serial_api.c | 32 +++++++++++++ .../TARGET_CC32XX/TARGET_CC3220SF/spi_api.c | 21 +++++++++ targets/targets.json | 3 +- 8 files changed, 132 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h index 9d4d30b4ed9..cf3ad860850 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h @@ -24,12 +24,31 @@ extern const PinMap PinMap_GPIO[]; /************PWM****************/ +#if DEVICE_PWMOUT extern const PinMap PinMap_PWM[]; +#endif /************UART***************/ +#if DEVICE_SERIAL extern const PinMap PinMap_UART_TX[]; extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_CTS[]; +#if DEVICE_SERIAL_FC extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif +#endif + +/************ADC***************/ +#if DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +/************SPI***************/ +#if DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif #endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h index a1cc02c6394..97f72f739ec 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h @@ -43,6 +43,10 @@ typedef enum { PWM_6 } PWMName; +typedef enum { + GSPI = 0 +} SPIName; + #define STDIO_UART_TX USBTX #define STDIO_UART_RX USBRX #define STDIO_UART UART_0 diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c index f2fa9cf76de..33a53adabee 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralPins.c @@ -62,6 +62,7 @@ const PinMap PinMap_GPIO[] = { }; /************PWM***************/ +#if DEVICE_PWMOUT const PinMap PinMap_PWM[] = { {PIN_01, PWM_1, 3}, {PIN_02, PWM_2, 3}, @@ -69,9 +70,12 @@ const PinMap PinMap_PWM[] = { {PIN_19, PWM_4, 8}, {PIN_21, PWM_5, 9}, {PIN_64, PWM_6, 3}, + {NC, NC, 0} }; +#endif /************UART***************/ +#if DEVICE_SERIAL const PinMap PinMap_UART_TX[] = { {PIN_01, UART_1, 7}, {PIN_03, UART_0, 7}, @@ -97,7 +101,7 @@ const PinMap PinMap_UART_RX[] = { {PIN_59, UART_1, 6}, {NC, NC, 0} }; - +#if DEVICE_SERIAL_FC const PinMap PinMap_UART_RTS[] = { {PIN_50, UART_0, 3}, {PIN_50, UART_1, 10}, @@ -114,3 +118,42 @@ const PinMap PinMap_UART_CTS[] = { {PIN_61, UART_1, 3}, {NC, NC, 0} }; +#endif +#endif + +#if DEVICE_ANALOGIN +const PinMap PinMap_ADC[] = { + {PIN_57, ADC0_0, 0}, + {PIN_58, ADC0_1, 0}, + {PIN_59, ADC0_2, 0}, + {PIN_60, ADC0_3, 0}, + {NC, NC, 0} +}; +#endif + +#if DEVICE_SPI +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PIN_05, GSPI, 7}, + {PIN_45, GSPI, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PIN_07, GSPI, 7}, + {PIN_52, GSPI, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PIN_06, GSPI, 7}, + {PIN_53, GSPI, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PIN_08, GSPI, 7}, + {PIN_50, GSPI, 7}, + {NC, NC, 0} +}; +#endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c index 9368a8fa69a..b754440c4f1 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c @@ -55,3 +55,7 @@ float analogin_read(analogin_t *obj) { return (float)value * (1.0f / (float)ADC_RESOLUTION); } +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c index ea87b010672..bf345c5fb1a 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c @@ -179,3 +179,8 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { void pwmout_pulsewidth_us(pwmout_t* obj, int us) { } + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c index de15b60cdf8..4b2da425fbc 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c @@ -403,3 +403,35 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi break; } } + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ +#if !DEVICE_SERIAL_FC + static const PinMap PinMap_UART_CTS[] = { + {NC, NC, 0} + }; +#endif + + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ +#if !DEVICE_SERIAL_FC + static const PinMap PinMap_UART_RTS[] = { + {NC, NC, 0} + }; +#endif + + return PinMap_UART_RTS; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c index 2f8d8e19f7b..cdfc8ac9228 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c @@ -25,6 +25,7 @@ #include "ti/devices/cc32xx/driverlib/rom_map.h" #include "ti/devices/cc32xx/driverlib/ti_spi_driverlib.h" #include "ti/devices/cc32xx/driverlib/prcm.h" +#include "PeripheralPins.h" #define PIN_MODE_SPI 7 #define SPI_WL_MASK 0xF80 @@ -56,6 +57,26 @@ static void spi_configure_driver_instance(spi_t *obj) } } +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + /** Initialize the SPI peripheral * * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral diff --git a/targets/targets.json b/targets/targets.json index 51ed99def13..fe65817a8df 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8782,17 +8782,18 @@ "CC32XX": { "inherits": ["TI"], "public": false, - "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], "release_versions": ["5"] }, "CC3220SF": { "inherits": ["CC32XX"], + "public": false, "macros": ["MBED_MPU_CUSTOM"], "core": "Cortex-M4", "device_name": "CC3220SF" }, "CC3220SF_LAUNCHXL": { "inherits": ["CC3220SF"], + "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], "components_add": ["SD", "FLASHIAP"], "device_has": ["USTICKER", "SERIAL", From eebe00b9d1ac68bba42ad1e13424f9bce72dee10 Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Tue, 30 Jul 2019 11:09:44 -0500 Subject: [PATCH 4/6] Implement PWMOUT --- .../CC3220SF_LAUNCHXL.c | 64 ++ .../CC3220SF_LAUNCHXL.h | 5 +- .../device/CC3220SF_WiFiInterface.cpp | 2 +- .../device/cc3200_simplelink.cpp | 8 +- .../TARGET_CC32XX/TARGET_CC3220SF/objects.h | 8 +- .../TARGET_CC3220SF/pwmout_api.c | 180 ++--- .../TARGET_CC3220SF/ti/drivers/PWM.c | 156 ++++ .../TARGET_CC3220SF/ti/drivers/PWM.h | 594 ++++++++++++++ .../TARGET_CC3220SF/ti/drivers/Timer.h | 549 +++++++++++++ .../ti/drivers/pwm/PWMTimerCC32XX.c | 728 ++++++++++++++++++ .../ti/drivers/pwm/PWMTimerCC32XX.h | 318 ++++++++ .../ti/drivers/timer/TimerCC32XX.c | 605 +++++++++++++++ .../ti/drivers/timer/TimerCC32XX.h | 242 ++++++ 13 files changed, 3333 insertions(+), 126 deletions(-) create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Timer.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.h create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.c create mode 100644 targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.h diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c index 47c9772384f..6500d968eb7 100755 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -215,6 +215,70 @@ const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = { const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT; +/* + * =============================== PWM =============================== + */ +#include +#include + +PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; + +const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { + { /* CC3220SF_LAUNCHXL_PWM6 */ + .pwmPin = PWMTimerCC32XX_PIN_01 + }, + { /* CC3220SF_LAUNCHXL_PWM7 */ + .pwmPin = PWMTimerCC32XX_PIN_02 + }, + { /* CC3220SF_LAUNCHXL_PWM0 */ + .pwmPin = PWMTimerCC32XX_PIN_17 + }, + { /* CC3220SF_LAUNCHXL_PWM3 */ + .pwmPin = PWMTimerCC32XX_PIN_19 + }, + { /* CC3220SF_LAUNCHXL_PWM2 */ + .pwmPin = PWMTimerCC32XX_PIN_21 + }, + { /* CC3220SF_LAUNCHXL_PWM5 */ + .pwmPin = PWMTimerCC32XX_PIN_64 + }, +}; + +const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] + }, + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] + }, + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM0], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM0] + }, + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM3], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM3] + }, + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM2], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM2] + }, + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM5], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM5] + } +}; + +const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; + /* * =============================== DMA =============================== */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h index d33152ffc34..efd23d0bbaa 100755 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h @@ -138,7 +138,10 @@ typedef enum CC3220SF_LAUNCHXL_I2SName { typedef enum CC3220SF_LAUNCHXL_PWMName { CC3220SF_LAUNCHXL_PWM6 = 0, CC3220SF_LAUNCHXL_PWM7, - + CC3220SF_LAUNCHXL_PWM0, + CC3220SF_LAUNCHXL_PWM3, + CC3220SF_LAUNCHXL_PWM2, + CC3220SF_LAUNCHXL_PWM5, CC3220SF_LAUNCHXL_PWMCOUNT } CC3220SF_LAUNCHXL_PWMName; diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp index ac3703e48a5..4515891ff61 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp @@ -588,7 +588,7 @@ void CC3220SFInterface::_socket_background_thread() } _mutex.unlock(); } - wait_ms(READ_THREAD_SLEEP_MS); + ThisThread::sleep_for(READ_THREAD_SLEEP_MS); } } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp index 7feee346011..683a37d4222 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp @@ -378,7 +378,7 @@ int CC3200_SIMPLELINK::scan(WiFiAccessPoint *res, unsigned count) while(triggeredScanTrials < MAX_SCAN_ATTEMPTS) { /* We wait for one second for the NWP to complete the initiated scan and collect results */ - wait_ms(1000); + ThisThread::sleep_for(1000); /* Collect results form one-shot scans.*/ ret = sl_WlanGetNetworkList(0, entries_count, netEntries); @@ -663,7 +663,7 @@ nsapi_error_t CC3200_SIMPLELINK::connect_socket(uint32_t sd, const SocketAddress { if (status == SL_ERROR_BSD_EALREADY && 1 == nonBlocking) { - wait_ms(1); + ThisThread::sleep_for(1); continue; } else if (status < 0) @@ -711,7 +711,7 @@ int CC3200_SIMPLELINK::sendto_socket(uint32_t sd, const void * buf, uint32_t buf status = sl_SendTo(sd, buf, bufLen, 0, sa, addrSize); if (status == SL_ERROR_BSD_EAGAIN && 1 == SOCKET_IS_NON_BLOCKING) { - wait_ms(1); + ThisThread::sleep_for(1); continue; } else if (status < 0) @@ -733,7 +733,7 @@ int32_t CC3200_SIMPLELINK::send(int sd, const void *data, uint32_t size) status = sl_Send(sd, data, size, 0); if (status == SL_ERROR_BSD_EAGAIN && 1 == SOCKET_IS_NON_BLOCKING) { - wait_ms(1); + ThisThread::sleep_for(1); continue; } else if (status < 0) diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h index 0f219473083..821bc030176 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h @@ -40,8 +40,8 @@ struct gpio_irq_s { uint32_t port; PinName pin; uint32_t ch; - unsigned long pin_mask; - unsigned long irq_offset; + unsigned long pin_mask; + unsigned long irq_offset; }; struct port_s { @@ -52,7 +52,9 @@ struct port_s { }; struct pwmout_s { - uint32_t pwmPin; + uint32_t period_us; + float duty_percent; + void * handle; PWMName pwm; }; diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c index bf345c5fb1a..348bd2fc0f4 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c @@ -15,148 +15,89 @@ */ #include "mbed_assert.h" #include "pwmout_api.h" -#include "cmsis.h" #include "pinmap.h" #include "PeripheralPins.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const uint32_t timerBaseAddresses[4] = { - CC3220SF_TIMERA0_BASE, - CC3220SF_TIMERA1_BASE, - CC3220SF_TIMERA2_BASE, - CC3220SF_TIMERA3_BASE, -}; - -static const uint32_t timerHalves[2] = { - TIMER_A, - TIMER_B, -}; - -/*static const uint32_t gpioBaseAddresses[4] = { - CC3220SF_GPIOA0_BASE, - CC3220SF_GPIOA1_BASE, - CC3220SF_GPIOA2_BASE, - CC3220SF_GPIOA3_BASE, -};*/ - -/*static const uint32_t gpioPinIndexes[8] = { - GPIO_PIN_0, - GPIO_PIN_1, - GPIO_PIN_2, - GPIO_PIN_3, - GPIO_PIN_4, - GPIO_PIN_5, - GPIO_PIN_6, - GPIO_PIN_7, -};*/ - -#define PinConfigTimerPort(config) (((config) >> 28) & 0xF) -#define PinConfigTimerHalf(config) (((config) >> 24) & 0xF) -#define PinConfigGPIOPort(config) (((config) >> 20) & 0xF) -#define PinConfigGPIOPinIndex(config) (((config) >> 16) & 0xF) -#define PinConfigPinMode(config) (((config) >> 8) & 0xF) -#define PinConfigPin(config) (((config) >> 0) & 0x3F) - -#define PWMTimerCC32XX_T0A (0x00 << 24) -#define PWMTimerCC32XX_T0B (0x01 << 24) -#define PWMTimerCC32XX_T1A (0x10 << 24) -#define PWMTimerCC32XX_T1B (0x11 << 24) -#define PWMTimerCC32XX_T2A (0x20 << 24) -#define PWMTimerCC32XX_T2B (0x21 << 24) -#define PWMTimerCC32XX_T3A (0x30 << 24) -#define PWMTimerCC32XX_T3B (0x31 << 24) - -#define PWMTimerCC32XX_GPIO9 (0x11 << 16) -#define PWMTimerCC32XX_GPIO10 (0x12 << 16) -#define PWMTimerCC32XX_GPIO11 (0x13 << 16) -#define PWMTimerCC32XX_GPIO24 (0x30 << 16) -#define PWMTimerCC32XX_GPIO25 (0x31 << 16) - -#define PWMTimerCC32XX_GPIONONE (0xFF << 16) - -#define PWMTimerCC32XX_PIN_01 (PWMTimerCC32XX_T3A | PWMTimerCC32XX_GPIO10 | 0x0300) -#define PWMTimerCC32XX_PIN_02 (PWMTimerCC32XX_T3B | PWMTimerCC32XX_GPIO11 | 0x0301) -#define PWMTimerCC32XX_PIN_17 (PWMTimerCC32XX_T0A | PWMTimerCC32XX_GPIO24 | 0x0510) -#define PWMTimerCC32XX_PIN_19 (PWMTimerCC32XX_T1B | PWMTimerCC32XX_GPIONONE | 0x0812) -#define PWMTimerCC32XX_PIN_21 (PWMTimerCC32XX_T1A | PWMTimerCC32XX_GPIO25 | 0x0914) -#define PWMTimerCC32XX_PIN_64 (PWMTimerCC32XX_T2B | PWMTimerCC32XX_GPIO9 | 0x033F) - -//static unsigned int pwm_clock_mhz; +#include +#include +#include + +extern const PWM_Config PWM_config[]; void pwmout_init(pwmout_t* obj, PinName pin) { + PWM_Params pwmParams; + int pwmIndex = CC3220SF_LAUNCHXL_PWMCOUNT; + + PWM_init(); + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); MBED_ASSERT(pwm != (PWMName)NC); + obj->pwm = pwm; switch(pin) { - case PIN_01: obj->pwmPin = PWMTimerCC32XX_PIN_01; break; - case PIN_02: obj->pwmPin = PWMTimerCC32XX_PIN_02; break; - case PIN_17: obj->pwmPin = PWMTimerCC32XX_PIN_17; break; - case PIN_19: obj->pwmPin = PWMTimerCC32XX_PIN_19; break; - case PIN_21: obj->pwmPin = PWMTimerCC32XX_PIN_21; break; - case PIN_64: obj->pwmPin = PWMTimerCC32XX_PIN_64; break; - default: break; - } + case PIN_01: + pwmIndex = CC3220SF_LAUNCHXL_PWM6; + break; - uint32_t timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(obj->pwmPin)]; - uint16_t halfTimer = timerHalves[PinConfigTimerHalf(obj->pwmPin)]; - - MAP_TimerDisable(timerBaseAddr, halfTimer); - - /* - * The CC32XX SDK TimerConfigure API halts both timers when it is - * used to configure a single half timer. The code below performs - * the register operations necessary to configure each half timer - * individually. - */ - /* Enable CCP to IO path */ - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_GPT_TRIG_SEL) = 0xFF; - - /* Split the timer and configure it as a PWM */ - uint32_t timerConfigVal = ((halfTimer & (TIMER_CFG_A_PWM | TIMER_CFG_B_PWM)) | - TIMER_CFG_SPLIT_PAIR); - HWREG(timerBaseAddr + TIMER_O_CFG) |= (timerConfigVal >> 24); - if (halfTimer & TIMER_A) { - HWREG(timerBaseAddr + TIMER_O_TAMR) = timerConfigVal & 255; - } - else { - HWREG(timerBaseAddr + TIMER_O_TBMR) = (timerConfigVal >> 8) & 255; + case PIN_02: + pwmIndex = CC3220SF_LAUNCHXL_PWM7; + break; + + case PIN_17: + pwmIndex = CC3220SF_LAUNCHXL_PWM0; + break; + + case PIN_19: + pwmIndex = CC3220SF_LAUNCHXL_PWM3; + break; + + case PIN_21: + pwmIndex = CC3220SF_LAUNCHXL_PWM2; + break; + + case PIN_64: + pwmIndex = CC3220SF_LAUNCHXL_PWM5; + break; + + default: + while(1); } - /* Set the peripheral output to active-high */ - MAP_TimerControlLevel(timerBaseAddr, halfTimer, true); + obj->handle = (void *)&PWM_config[pwmIndex]; + + // Initialize the PWM parameters + PWM_Params_init(&pwmParams); - uint16_t mode = PinConfigPinMode(obj->pwmPin); + obj->duty_percent = PWM_DEFAULT_DUTY_PERCENT; + obj->period_us = PWM_DEFAULT_PERIOD_US; - /* Start the timer & set pinmux to PWM mode */ - MAP_TimerEnable(timerBaseAddr, halfTimer); - MAP_PinTypeTimer((unsigned long)pin, (unsigned long)mode); + if (PWM_open(pwmIndex, &pwmParams)) + { + PWM_start((PWM_Handle)obj->handle); + } + else + { + while(1); + } } void pwmout_free(pwmout_t* obj) { - // [TODO] + PWM_stop((PWM_Handle)obj->handle); + PWM_close((PWM_Handle)obj->handle); } void pwmout_write(pwmout_t* obj, float value) { - + PWM_setDuty((PWM_Handle)obj->handle, value*100); + obj->duty_percent = value; } float pwmout_read(pwmout_t* obj) { - return 0; + return (obj->duty_percent); } void pwmout_period(pwmout_t* obj, float seconds) { - pwmout_period_us(obj, seconds * 1000000.0f); + pwmout_period_us(obj, seconds * 1000 * 1000); } void pwmout_period_ms(pwmout_t* obj, int ms) { @@ -165,7 +106,8 @@ void pwmout_period_ms(pwmout_t* obj, int ms) { // Set the PWM period, keeping the duty cycle the same. void pwmout_period_us(pwmout_t* obj, int us) { - + PWM_setPeriod((PWM_Handle)obj->handle, us); + obj->period_us = us; } void pwmout_pulsewidth(pwmout_t* obj, float seconds) { @@ -177,7 +119,11 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { } void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - + if (obj->period_us) + { + float value = (float)us / (float)obj->period_us; + pwmout_write(obj, value); + } } const PinMap *pwmout_pinmap() diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.c new file mode 100644 index 00000000000..7332b511539 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PWM.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const PWM_Config PWM_config[]; +extern const uint_least8_t PWM_count; + +/* Default PWM parameters structure */ +const PWM_Params PWM_defaultParams = { + .periodUnits = PWM_PERIOD_US, /* Period is defined in Hz */ + .periodValue = PWM_DEFAULT_PERIOD_US, /* 1US */ + .dutyUnits = PWM_DUTY_FRACTION, /* Duty is fraction of period */ + .dutyValue = PWM_DEFAULT_DUTY_PERCENT, /* 0% duty cycle */ + .idleLevel = PWM_IDLE_LOW, /* Low idle level */ + .custom = NULL /* No custom params */ +}; + +static bool isInitialized = false; + +/* + * ======== PWM_close ======== + */ +void PWM_close(PWM_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== PWM_control ======== + */ +int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, void *arg) +{ + return handle->fxnTablePtr->controlFxn(handle, cmd, arg); +} + +/* + * ======== PWM_init ======== + */ +void PWM_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < PWM_count; i++) { + PWM_config[i].fxnTablePtr->initFxn((PWM_Handle) &(PWM_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== PWM_open ======== + */ +PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params) +{ + PWM_Handle handle = NULL; + + if (isInitialized && (index < PWM_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (PWM_Params *) &PWM_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (PWM_Handle) &(PWM_config[index]); + + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== PWM_Params_init ======== + */ +void PWM_Params_init(PWM_Params *params) +{ + *params = PWM_defaultParams; +} + +/* + * ======== PWM_setDuty ======== + */ +int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty) +{ + return(handle->fxnTablePtr->setDutyFxn(handle, duty)); +} + +/* + * ======== PWM_setDuty ======== + */ +int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period) +{ + return(handle->fxnTablePtr->setPeriodFxn(handle, period)); +} + +/* + * ======== PWM_start ======== + */ +void PWM_start(PWM_Handle handle) +{ + handle->fxnTablePtr->startFxn(handle); +} + +/* + * ======== PWM_stop ======== + */ +void PWM_stop(PWM_Handle handle) +{ + handle->fxnTablePtr->stopFxn(handle); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.h new file mode 100644 index 00000000000..091141747ba --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/PWM.h @@ -0,0 +1,594 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PWM.h + * @brief PWM driver interface + * + * To use the PWM driver, ensure that the correct driver library for your + * device is linked in and include this header file as follows: + * @code + * #include + * @endcode + * + * This module serves as the main interface for applications. Its purpose + * is to redirect the PWM APIs to specific driver implementations + * which are specified using a pointer to a #PWM_FxnTable. + * + * # Overview # + * The PWM driver in TI-RTOS facilitates the generation of Pulse Width + * Modulated signals via simple and portable APIs. PWM instances must be + * opened by calling PWM_open() while passing in a PWM index and a parameters + * data structure. + * + * The driver APIs serve as an interface to a typical TI-RTOS application. + * The specific peripheral implementations are responsible for creating all OS + * specific primitives to allow for thread-safe operation. + * + * When a PWM instance is opened, the period, duty cycle and idle level are + * configured and the PWM is stopped (waveforms not generated until PWM_start() + * is called). The maximum period and duty supported is device dependent; + * refer to the implementation specific documentation for values. + * + * PWM outputs are active-high, meaning the duty will control the duration of + * high output on the pin (at 0% duty, the output is always low, at 100% duty, + * the output is always high). + * + * # Usage # + * + * @code + * PWM_Handle pwm; + * PWM_Params pwmParams; + * + * // Initialize the PWM driver. + * PWM_init(); + * + * // Initialize the PWM parameters + * PWM_Params_init(&pwmParams); + * pwmParams.idleLevel = PWM_IDLE_LOW; // Output low when PWM is not running + * pwmParams.periodUnits = PWM_PERIOD_HZ; // Period is in Hz + * pwmParams.periodValue = 1e6; // 1MHz + * pwmParams.dutyUnits = PWM_DUTY_FRACTION; // Duty is in fractional percentage + * pwmParams.dutyValue = 0; // 0% initial duty cycle + * + * // Open the PWM instance + * pwm = PWM_open(Board_PWM0, &pwmParams); + * + * if (pwm == NULL) { + * // PWM_open() failed + * while (1); + * } + * + * PWM_start(pwm); // start PWM with 0% duty cycle + * + * PWM_setDuty(pwm, + * (PWM_DUTY_FRACTION_MAX / 2)); // set duty cycle to 50% + * @endcode + * + * Details for the example code above are described in the following + * subsections. + * + * ### PWM Driver Configuration # + * + * In order to use the PWM APIs, the application is required + * to provide device-specific PWM configuration in the Board.c file. + * The PWM driver interface defines a configuration data structure: + * + * @code + * typedef struct PWM_Config_ { + * PWM_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } PWM_Config; + * @endcode + * + * The application must declare an array of PWM_Config elements, named + * PWM_config[]. Each element of PWM_config[] is populated with + * pointers to a device specific PWM driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as which pin will be driven, and which timer peripheral + * will be used. Each element in PWM_config[] corresponds to + * a PWM instance, and none of the elements should have NULL pointers. + * + * Additionally, the PWM driver interface defines a global integer variable + * 'PWM_count' which is initialized to the number of PWM instances the + * application has defined in the PWM_Config array. + * + * You will need to check the device-specific PWM driver implementation's + * header file for example configuration. Please also refer to the + * Board.c file of any of your examples to see the PWM configuration. + * + * ### Initializing the PWM Driver # + * + * PWM_init() must be called before any other PWM APIs. This function + * calls the device implementation's PWM initialization function, for each + * element of PWM_config[]. + * + * ### Opening the PWM Driver # + * + * Opening a PWM requires four steps: + * 1. Create and initialize a PWM_Params structure. + * 2. Fill in the desired parameters. + * 3. Call PWM_open(), passing the index of the PWM in the PWM_config + * structure, and the address of the PWM_Params structure. The + * PWM instance is specified by the index in the PWM_config structure. + * 4. Check that the PWM handle returned by PWM_open() is non-NULL, + * and save it. The handle will be used to read and write to the + * PWM you just opened. + * + * Only one PWM index can be used at a time; calling PWM_open() a second + * time with the same index previously passed to PWM_open() will result in + * an error. You can, though, re-use the index if the instance is closed + * via PWM_close(). + * In the example code, Board_PWM0 is passed to PWM_open(). This macro + * is defined in the example's Board.h file. + * + * ### Modes of Operation # + * + * A PWM instance can be configured to interpret the period as one of three + * units: + * - #PWM_PERIOD_US: The period is in microseconds. + * - #PWM_PERIOD_HZ: The period is in (reciprocal) Hertz. + * - #PWM_PERIOD_COUNTS: The period is in timer counts. + * + * A PWM instance can be configured to interpret the duty as one of three + * units: + * - #PWM_DUTY_US: The duty is in microseconds. + * - #PWM_DUTY_FRACTION: The duty is in a fractional part of the period + * where 0 is 0% and #PWM_DUTY_FRACTION_MAX is 100%. + * - #PWM_DUTY_COUNTS: The period is in timer counts and must be less than + * the period. + * + * The idle level parameter is used to set the output to high/low when the + * PWM is not running (stopped or not started). The idle level can be + * set to: + * - #PWM_IDLE_LOW + * - #PWM_IDLE_HIGH + * + * The default PWM configuration is to set a duty of 0% with a 1MHz frequency. + * The default period units are in PWM_PERIOD_HZ and the default duty units + * are in PWM_DUTY_FRACTION. Finally, the default output idle level is + * PWM_IDLE_LOW. It is the application's responsibility to set the duty for + * each PWM output used. + * + * ### Controlling the PWM Duty Cycle # + * + * Once the PWM instance has been opened and started, the primary API used + * by the application will be #PWM_setDuty() to control the duty cycle of a + * PWM pin: + * + * @code + * PWM_setDuty(pwm, PWM_DUTY_FRACTION_MAX / 2); // Set 50% duty cycle + * @endcode + * + * # Implementation # + * + * The PWM driver interface module is joined (at link time) to an + * array of PWM_Config data structures named *PWM_config*. + * PWM_config is implemented in the application with each entry being a + * PWM instance. Each entry in *PWM_config* contains a: + * - (PWM_FxnTable *) to a set of functions that implement a PWM peripheral + * - (void *) data object that is associated with the PWM_FxnTable + * - (void *) hardware attributes that are associated with the PWM_FxnTable + * + * The PWM APIs are redirected to the device specific implementations + * using the PWM_FxnTable pointer of the PWM_config entry. + * In order to use device specific functions of the PWM driver directly, + * link in the correct driver library for your device and include the + * device specific PWM driver header file (which in turn includes PWM.h). + * For example, for the MSP432 family of devices, you would include the + * following header file: + * @code + * #include + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_PWM__include +#define ti_drivers_PWM__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define PWM_DEFAULT_PERIOD_US 1 +#define PWM_DEFAULT_DUTY_PERCENT 0 + +/*! + * @brief Maximum duty (100%) when configuring duty cycle as a fraction of + * period. + */ +#define PWM_DUTY_FRACTION_MAX ((uint32_t) 100) + +/*! + * Common PWM_control command code reservation offset. + * PWM driver implementations should offset command codes with PWM_CMD_RESERVED + * growing positively. + * + * Example implementation specific command codes: + * @code + * #define PWMXYZ_COMMAND0 (PWM_CMD_RESERVED + 0) + * #define PWMXYZ_COMMAND1 (PWM_CMD_RESERVED + 1) + * @endcode + */ +#define PWM_CMD_RESERVED (32) + +/*! + * Common PWM_control status code reservation offset. + * PWM driver implementations should offset status codes with + * PWM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define PWMXYZ_STATUS_ERROR0 (PWM_STATUS_RESERVED - 0) + * #define PWMXYZ_STATUS_ERROR1 (PWM_STATUS_RESERVED - 1) + * #define PWMXYZ_STATUS_ERROR2 (PWM_STATUS_RESERVED - 2) + * @endcode + */ +#define PWM_STATUS_RESERVED (-32) + +/*! + * @brief Success status code returned by: + * PWM_control(), PWM_setDuty(), PWM_setPeriod(). + * + * Functions return PWM_STATUS_SUCCESS if the call was executed + * successfully. + */ +#define PWM_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by PWM_control(). + * + * PWM_control() returns PWM_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define PWM_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by PWM_control() for undefined + * command codes. + * + * PWM_control() returns PWM_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define PWM_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by PWM_setPeriod(). + * + * PWM_setPeriod() returns PWM_STATUS_INVALID_PERIOD if the period argument is + * invalid for the current configuration. + */ +#define PWM_STATUS_INVALID_PERIOD (-3) + +/*! + * @brief An error status code returned by PWM_setDuty(). + * + * PWM_setDuty() returns PWM_STATUS_INVALID_DUTY if the duty cycle argument is + * invalid for the current configuration. + */ +#define PWM_STATUS_INVALID_DUTY (-4) + +/*! + * @brief PWM period unit definitions. Refer to device specific + * implementation if using PWM_PERIOD_COUNTS (raw PWM/Timer counts). + */ +typedef enum PWM_Period_Units_ { + PWM_PERIOD_US, /*!< Period in microseconds */ + PWM_PERIOD_HZ, /*!< Period in (reciprocal) Hertz + (for example 2MHz = 0.5us period) */ + PWM_PERIOD_COUNTS /*!< Period in timer counts */ +} PWM_Period_Units; + +/*! + * @brief PWM duty cycle unit definitions. Refer to device specific + * implementation if using PWM_DUTY_COUNTS (raw PWM/Timer counts). + */ +typedef enum PWM_Duty_Units_ { + PWM_DUTY_US, /*!< Duty cycle in microseconds */ + PWM_DUTY_FRACTION, /*!< Duty as a fractional part of PWM_DUTY_FRACTION_MAX */ + PWM_DUTY_COUNTS /*!< Duty in timer counts */ +} PWM_Duty_Units; + +/*! + * @brief Idle output level when PWM is not running (stopped / not started). + */ +typedef enum PWM_IdleLevel_ { + PWM_IDLE_LOW = 0, + PWM_IDLE_HIGH = 1, +} PWM_IdleLevel; + +/*! + * @brief PWM Parameters + * + * PWM Parameters are used to with the PWM_open() call. Default values for + * these parameters are set using PWM_Params_init(). + * + * @sa PWM_Params_init() + */ +typedef struct PWM_Params_ { + PWM_Period_Units periodUnits; /*!< Units in which the period is specified */ + uint32_t periodValue; /*!< PWM initial period */ + PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */ + uint32_t dutyValue; /*!< PWM initial duty */ + PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */ + void *custom; /*!< Custom argument used by driver + implementation */ +} PWM_Params; + +/*! + * @brief A handle that is returned from a PWM_open() call. + */ +typedef struct PWM_Config_ *PWM_Handle; + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_close(). + */ +typedef void (*PWM_CloseFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_control(). + */ +typedef int_fast16_t (*PWM_ControlFxn) (PWM_Handle handle, uint_fast16_t cmd, + void *arg); +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_init(). + */ +typedef void (*PWM_InitFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_open(). + */ +typedef PWM_Handle (*PWM_OpenFxn) (PWM_Handle handle, PWM_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setDuty(). + */ +typedef int_fast16_t (*PWM_SetDutyFxn) (PWM_Handle handle, + uint32_t duty); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setPeriod(). + */ +typedef int_fast16_t (*PWM_SetPeriodFxn) (PWM_Handle handle, + uint32_t period); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_start(). + */ +typedef void (*PWM_StartFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_stop(). + */ +typedef void (*PWM_StopFxn) (PWM_Handle handle); + +/*! + * @brief The definition of a PWM function table that contains the + * required set of functions to control a specific PWM driver + * implementation. + */ +typedef struct PWM_FxnTable_ { + /*! Function to close the specified instance */ + PWM_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + PWM_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + PWM_InitFxn initFxn; + /*! Function to open the specified instance */ + PWM_OpenFxn openFxn; + /*! Function to set the duty cycle for a specific instance */ + PWM_SetDutyFxn setDutyFxn; + /*! Function to set the period for a specific instance */ + PWM_SetPeriodFxn setPeriodFxn; + /*! Function to start the PWM output for a specific instance */ + PWM_StartFxn startFxn; + /*! Function to stop the PWM output for a specific instance */ + PWM_StopFxn stopFxn; +} PWM_FxnTable; + +/*! + * @brief PWM Global configuration. + * + * The PWM_Config structure contains a set of pointers used to characterize + * the PWM driver implementation. + * + */ +typedef struct PWM_Config_ { + /*! Pointer to a table of driver-specific implementations of PWM APIs */ + PWM_FxnTable const *fxnTablePtr; + /*! Pointer to a driver specific data object */ + void *object; + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} PWM_Config; + +/*! + * @brief Function to close a PWM instance specified by the PWM handle. + * + * @pre PWM_open() must have been called first. + * @pre PWM_stop() must have been called first if PWM was started. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_start() + * @sa PWM_stop() + */ +extern void PWM_close(PWM_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * PWM_Handle. + * + * @pre PWM_open() must have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @param cmd A command value defined by the driver specific + * implementation. + * + * @param arg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd. + * + * @return A PWM_Status describing an error or success state. Negative values + * indicate an error occurred. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief This function initializes the PWM module. + * + * @pre The PWM_config structure must exist and be persistent before this + * function can be called. This function must be called before any + * other PWM driver APIs. This function does not modify any peripheral + * registers & should only be called once. + */ +extern void PWM_init(void); + +/*! + * @brief This function opens a given PWM instance and sets the period, + * duty and idle level to those specified in the params argument. + * + * @param index Logical instance number for the PWM indexed into + * the PWM_config table. + * + * @param params Pointer to an parameter structure. If NULL default + * values are used. + * + * @return A PWM_Handle if successful or NULL on an error or if it has been + * opened already. If NULL is returned further PWM API calls will + * result in undefined behavior. + * + * @sa PWM_close() + */ +extern PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params); + +/*! + * @brief Function to initialize the PWM_Params structure to default values. + * + * @param params A pointer to PWM_Params structure for initialization. + * + * Defaults values are: + * Period units: PWM_PERIOD_HZ + * Period: 1e6 (1MHz) + * Duty cycle units: PWM_DUTY_FRACTION + * Duty cycle: 0% + * Idle level: PWM_IDLE_LOW + */ +extern void PWM_Params_init(PWM_Params *params); + +/*! + * @brief Function to set the duty cycle of the specified PWM handle. PWM + * instances run in active high output mode; 0% is always low output, + * 100% is always high output. This API can be called while the PWM + * is running & duty must always be lower than or equal to the period. + * If an error occurs while calling the function the PWM duty cycle + * will remain unchanged. + * + * @pre PWM_open() must have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @param duty Duty cycle in the units specified by the params used + * in PWM_open(). + * + * @return A PWM status describing an error or success. Negative values + * indicate an error. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty); + +/*! + * @brief Function to set the period of the specified PWM handle. This API + * can be called while the PWM is running & the period must always be + * larger than the duty cycle. + * If an error occurs while calling the function the PWM period + * will remain unchanged. + * + * @pre PWM_open() must have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @param period Period in the units specified by the params used + * in PWM_open(). + * + * @return A PWM status describing an error or success state. Negative values + * indicate an error. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period); + +/*! + * @brief Function to start the specified PWM handle with current settings. + * + * @pre PWM_open() has to have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_stop() + */ +extern void PWM_start(PWM_Handle handle); + +/*! + * @brief Function to stop the specified PWM handle. Output will set to the + * idle level specified by params in PWM_open(). + * + * @pre PWM_open() has to have been called first. + * + * @param handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_start() + */ +extern void PWM_stop(PWM_Handle handle); + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_PWM__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Timer.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Timer.h new file mode 100644 index 00000000000..a35edae0f38 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/Timer.h @@ -0,0 +1,549 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file Timer.h + * @brief Timer driver interface + * + * The timer header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The timer driver serves as the main interface for a typical RTOS + * application. Its purpose is to redirect the timer APIs to device specific + * implementations which are specified using a pointer to a #Timer_FxnTable. + * The device specific implementations are responsible for creating all the + * RTOS specific primitives to allow for thead-safe operation. This driver + * does not have PWM or capture functionalities. These functionalities are + * addressed in both the capture and PWM driver. + * + * The timer driver also handles the general purpose timer resource allocation. + * For each driver that requires use of a general purpose timer, it calls + * Timer_open() to occupy the specified timer, and calls Timer_close() to + * release the occupied timer resource. + * + * # Usage # + * The following example code opens a timer in continuous callback mode. The + * period is set to 1000 Hz. + * + * @code + * Timer_Handle handle; + * Timer_Params params; + * + * Timer_Params_init(¶ms); + * params.periodUnits = Timer_PERIOD_HZ; + * params.period = 1000; + * params.timerMode = Timer_CONTINUOUS_CALLBACK; + * params.timerCallback = UserCallbackFunction; + * + * handle = Timer_open(Board_TIMER0, ¶ms); + * + * if (handle == NULL) { + * // Timer_open() failed + * while (1); + * } + * + * status = Timer_start(handle); + * + * if (status == Timer_STATUS_ERROR) { + * //Timer_start() failed + * while (1); + * } + * + * sleep(10000); + * + * Timer_stop(handle); + * @endcode + * + * ### Timer Driver Configuration # + * + * In order to use the timer APIs, the application is required to provide + * device specific timer configuration in the Board.c file. The timer driver + * interface defines a configuration data structure: + * + * @code + * typedef struct Timer_Config_ { + * Timer_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } Timer_Config; + * @endcode + * + * The application must declare an array of Timer_Config elements, named + * Timer_config[]. Each element of Timer_config[] are populated with + * pointers to a device specific timer driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the timer peripheral's base address, interrupt + * number and interrupt priority. Each element in Timer_config[] corresponds + * to a timer instance, and none of the elements should have NULL pointers. + * There is no correlation between the index and the peripheral designation + * (such as TIMER0 or TIMER1). For example, it is possible to use + * Timer_config[0] for TIMER1. + * + * You will need to check the device specific timer driver implementation's + * header file for example configuration. + * + * ### Initializing the Timer Driver # + * + * Timer_init() must be called before any other timer APIs. This function + * calls the device implementation's timer initialization function, for each + * element of Timer_config[]. + * + * ### Modes of Operation # + * + * The timer driver supports four modes of operation which may be specified in + * the Timer_Params. The device specific implementation may configure the timer + * peripheral as an up or down counter. In any case, Timer_getCount() will + * return a value characteristic of an up counter. + * + * #Timer_ONESHOT_CALLBACK is non-blocking. After Timer_start() is called, + * the calling thread will continue execution. When the timer interrupt + * is triggered, the specified callback function will be called. The timer + * will not generate another interrupt unless Timer_start() is called again. + * Calling Timer_stop() or Timer_close() after Timer_start() but, before the + * timer interrupt, will prevent the specified callback from ever being + * invoked. + * + * #Timer_ONESHOT_BLOCKING is a blocking call. A semaphore is used to block + * the calling thread's execution until the timer generates an interrupt. If + * Timer_stop() is called, the calling thread will become unblocked + * immediately. The behavior of the timer in this mode is similar to a sleep + * function. + * + * #Timer_CONTINUOUS_CALLBACK is non-blocking. After Timer_start() is called, + * the calling thread will continue execution. When the timer interrupt is + * treiggered, the specified callback function will be called. The timer is + * automatically restarted and will continue to periodically generate + * interrupts until Timer_stop() is called. + * + * #Timer_FREE_RUNNING is non-blocking. After Timer_start() is called, + * the calling thread will continue execution. The timer will not + * generate an interrupt in this mode. The timer hardware will run until + * Timer_stop() is called. + * + * # Implementation # + * + * The timer driver interface module is joined (at link time) to an + * array of Timer_Config data structures named *Timer_config*. + * Timer_config is implemented in the application with each entry being an + * instance of a timer peripheral. Each entry in *Timer_config* contains a: + * - (Timer_FxnTable *) to a set of functions that implement a timer peripheral + * - (void *) data object that is associated with the Timer_FxnTable + * - (void *) hardware attributes that are associated with the Timer_FxnTable + * + * The timer APIs are redirected to the device specific implementations + * using the Timer_FxnTable pointer of the Timer_config entry. + * In order to use device specific functions of the timer driver directly, + * link in the correct driver library for your device and include the + * device specific timer driver header file (which in turn includes Timer.h). + * For example, for the MSP432 family of devices, you would include the + * following header file: + * + * @code + * #include + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_Timer__include +#define ti_drivers_Timer__include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/*! + * Common Timer_control command code reservation offset. + * Timer driver implementations should offset command codes with Timer_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define TimerXYZ_CMD_COMMAND0 Timer_CMD_RESERVED + 0 + * #define TimerXYZ_CMD_COMMAND1 Timer_CMD_RESERVED + 1 + * @endcode + */ +#define Timer_CMD_RESERVED (32) + +/*! + * Common Timer_control status code reservation offset. + * Timer driver implementations should offset status codes with + * Timer_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define TimerXYZ_STATUS_ERROR0 Timer_STATUS_RESERVED - 0 + * #define TimerXYZ_STATUS_ERROR1 Timer_STATUS_RESERVED - 1 + * @endcode + */ +#define Timer_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + */ +#define Timer_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + */ +#define Timer_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by Timer_control() for undefined + * command codes. + * + * Timer_control() returns Timer_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define Timer_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief A handle that is returned from a Timer_open() call. + */ +typedef struct Timer_Config_ *Timer_Handle; + +/*! + * @brief Timer mode settings + * + * This enum defines the timer modes that may be specified in #Timer_Params. + */ +typedef enum Timer_Mode_ { + Timer_ONESHOT_CALLBACK, /*!< User routine doesn't get blocked and + user-specified callback function is + invoked once the timer interrupt happens + for only one time */ + Timer_ONESHOT_BLOCKING, /*!< User routine gets blocked until timer + interrupt happens for only one time. */ + Timer_CONTINUOUS_CALLBACK, /*!< User routine doesn't get blocked and + user-specified callback function is + invoked with every timer interrupt. */ + Timer_FREE_RUNNING +} Timer_Mode; + +/*! + * @brief Timer period unit enum + * + * This enum defines the units that may be specified for the period + * in #Timer_Params. This unit has no effect with Timer_getCounts. + */ +typedef enum Timer_PeriodUnits_ { + Timer_PERIOD_US, /*!< Period specified in micro seconds. */ + Timer_PERIOD_HZ, /*!< Period specified in hertz; interrupts per + second. */ + Timer_PERIOD_COUNTS /*!< Period specified in ticks or counts. Varies + from board to board. */ +} Timer_PeriodUnits; + +/*! + * @brief Timer callback function + * + * User definable callback function prototype. The timer driver will call the + * defined function and pass in the timer driver's handle and the pointer to the + * user-specified the argument. + * + * @param handle Timer_Handle + */ +typedef void (*Timer_CallBackFxn)(Timer_Handle handle); + +/*! + * @brief Timer Parameters + * + * Timer parameters are used to with the Timer_open() call. Default values for + * these parameters are set using Timer_Params_init(). + * + */ +typedef struct Timer_Params_ { + /*! Mode to be used by the timer driver. */ + Timer_Mode timerMode; + + /*! Units used to specify the period. */ + Timer_PeriodUnits periodUnits; + + /*! Callback function called when timerMode is Timer_ONESHOT_CALLBACK or + Timer_CONTINUOUS_CALLBACK. */ + Timer_CallBackFxn timerCallback; + + /*! Period in units of periodUnits. */ + uint32_t period; +} Timer_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_control(). + */ +typedef int_fast16_t (*Timer_ControlFxn)(Timer_Handle handle, + uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_close(). + */ +typedef void (*Timer_CloseFxn)(Timer_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_getCount(). + */ +typedef uint32_t (*Timer_GetCountFxn)(Timer_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_init(). + */ +typedef void (*Timer_InitFxn)(Timer_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_open(). + */ +typedef Timer_Handle (*Timer_OpenFxn)(Timer_Handle handle, + Timer_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_start(). + */ +typedef int32_t (*Timer_StartFxn)(Timer_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Timer_stop(). + */ +typedef void (*Timer_StopFxn)(Timer_Handle handle); + +/*! + * @brief The definition of a timer function table that contains the + * required set of functions to control a specific timer driver + * implementation. + */ +typedef struct Timer_FxnTable_ { + /*! Function to close the specified peripheral. */ + Timer_CloseFxn closeFxn; + + /*! Function to implementation specific control function. */ + Timer_ControlFxn controlFxn; + + /*! Function to get the count of the specified peripheral. */ + Timer_GetCountFxn getCountFxn; + + /*! Function to initialize the given data object. */ + Timer_InitFxn initFxn; + + /*! Function to open the specified peripheral. */ + Timer_OpenFxn openFxn; + + /*! Function to start the specified peripheral. */ + Timer_StartFxn startFxn; + + /*! Function to stop the specified peripheral. */ + Timer_StopFxn stopFxn; +} Timer_FxnTable; + +/*! + * @brief Timer Global configuration + * + * The Timer_Config structure contains a set of pointers used to characterize + * the timer driver implementation. + * + * This structure needs to be defined before calling Timer_init() and it must + * not be changed thereafter. + * + * @sa Timer_init() + */ +typedef struct Timer_Config_ { + /*! Pointer to a table of driver-specific implementations of timer APIs. */ + Timer_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object. */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure. */ + void const *hwAttrs; +} Timer_Config; + +/*! + * @brief Function to close a timer. The corresponding timer to the + * Timer_Handle becomes an available timer resource. + * + * @pre Timer_open() has been called. + * + * @param handle A Timer_Handle returned from Timer_open(). + * + * @sa Timer_open() + */ +extern void Timer_close(Timer_Handle handle); + +/*! + * @brief Function performs device specific features on a given + * Timer_Handle. + * + * @pre Timer_open() has been called. + * + * @param handle A Timer_Handle returned from Timer_open(). + * + * @param cmd A command value defined by the driver specific + * implementation. + * + * @param arg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd. + * + * @return A Timer_Status describing an error or success state. Negative values + * indicate an error occurred. + * + * @sa Timer_open() + */ +extern int_fast16_t Timer_control(Timer_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief Function to get the current count of a timer. The value returned + * represents timer counts. The value returned is always + * characteristic of an up counter. This is true even if the timer + * peripheral is counting down. Some device specific implementations + * may employ a prescaler in addition to this timer count. + * + * @pre Timer_open() has been called. + * + * @param handle A Timer_Handle returned from Timer_open(). + * + * @sa Timer_open() + * + * @return The current count of the timer in timer ticks. + * + */ +extern uint32_t Timer_getCount(Timer_Handle handle); + + +/*! + * @brief Function to initialize a timer module. This function will go through + * all available hardware resources and mark them as "available". + * + * @pre The Timer_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other timer driver APIs. + * + * @sa Timer_open() + */ +extern void Timer_init(void); + +/*! + * @brief Function to initialize a given timer peripheral specified by the + * index argument. The Timer_Params specifies which mode the timer + * will operate. The accuracy of the desired period is limited by the + * the clock. For example, a 100 MHz clock will have a tick resolution + * of 10 nanoseconds. This function takes care of timer resource + * allocation. If the particular timer is available to use, the timer + * driver owns it and returns a Timer_Handle. + * + * @pre Timer_init() has been called. + * + * @param index Logical peripheral number for the timer indexed into + * the Timer_config table. + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return A Timer_Handle upon success or NULL. If the desired period results + * in overflow, or saturation, of the timer, NULL is returned. If the + * timer resource is already in use, NULL is returned. + * + * @sa Timer_init() + * @sa Timer_close() + */ +extern Timer_Handle Timer_open(uint_least8_t index, Timer_Params *params); + +/*! + * @brief Function to initialize the Timer_Params struct to its defaults. + * + * @param params A pointer to Timer_Params structure for + * initialization. + * + * Defaults values are: + * timerMode = Timer_ONESHOT_BLOCKING + * periodUnit = Timer_PERIOD_COUNTS + * timerCallback = NULL + * period = (uint16_t) ~0 + */ +extern void Timer_Params_init(Timer_Params *params); + +/*! + * @brief Function to start the timer. + * + * @pre Timer_open() has been called. + * + * @param handle A Timer_Handle returned from Timer_open(). + * + * @return Timer_STATUS_SUCCESS or Timer_STATUS_ERROR. + * + * @sa Timer_stop() + */ +extern int32_t Timer_start(Timer_Handle handle); + +/*! + * @brief Function to stop timer. If the timer is already stopped, this + * function has no effect. + * + * @pre Timer_open() has been called. + * + * @param handle A Timer_Handle returned from Timer_open(). + * + * @sa Timer_start() + */ +extern void Timer_stop(Timer_Handle handle); + +/* The following are included for backwards compatibility. These should not be + * used by the application. + */ +#define TIMER_CMD_RESERVED Timer_CMD_RESERVED +#define TIMER_STATUS_RESERVED Timer_STATUS_RESERVED +#define TIMER_STATUS_SUCCESS Timer_STATUS_SUCCESS +#define TIMER_STATUS_ERROR Timer_STATUS_ERROR +#define TIMER_STATUS_UNDEFINEDCMD Timer_STATUS_UNDEFINEDCMD +#define TIMER_ONESHOT_CB Timer_ONESHOT_CALLBACK +#define TIMER_ONESHOT_BLOCK Timer_ONESHOT_BLOCKING +#define TIMER_CONTINUOUS_CB Timer_CONTINUOUS_CALLBACK +#define TIMER_MODE_FREE_RUNNING Timer_FREE_RUNNING +#define TIMER_PERIOD_US Timer_PERIOD_US +#define TIMER_PERIOD_HZ Timer_PERIOD_HZ +#define TIMER_PERIOD_COUNTS Timer_PERIOD_COUNTS +#define Timer_Period_Units Timer_PeriodUnits + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Timer__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c new file mode 100644 index 00000000000..d70037d5014 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c @@ -0,0 +1,728 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) +#define PAD_RESET_STATE 0xC61 + +void PWMTimerCC32XX_close(PWM_Handle handle); +int_fast16_t PWMTimerCC32XX_control(PWM_Handle handle, uint_fast16_t cmd, + void *arg); +void PWMTimerCC32XX_init(PWM_Handle handle); +PWM_Handle PWMTimerCC32XX_open(PWM_Handle handle, PWM_Params *params); +int_fast16_t PWMTimerCC32XX_setDuty(PWM_Handle handle, uint32_t dutyValue); +int_fast16_t PWMTimerCC32XX_setPeriod(PWM_Handle handle, uint32_t periodValue); +void PWMTimerCC32XX_start(PWM_Handle handle); +void PWMTimerCC32XX_stop(PWM_Handle handle); + +/* PWM function table for PWMTimerCC32XX implementation */ +const PWM_FxnTable PWMTimerCC32XX_fxnTable = { + PWMTimerCC32XX_close, + PWMTimerCC32XX_control, + PWMTimerCC32XX_init, + PWMTimerCC32XX_open, + PWMTimerCC32XX_setDuty, + PWMTimerCC32XX_setPeriod, + PWMTimerCC32XX_start, + PWMTimerCC32XX_stop +}; + +/* + * Internal value to notify an error has occurred while calculating a duty + * or period. + */ +static const uint32_t PWM_INVALID_VALUE = (~0); + +/* + * GPT peripheral load & match registers are 16 bits wide. Max value which + * can be set is 65535. + */ +static const uint16_t PWM_MAX_MATCH_REG_VALUE = (~0); + +/* + * GPT peripherals have 24 bit resolution. The max period value which be + * set is 16777215. + */ +static const uint32_t PWM_MAX_PERIOD_COUNT = (0xFFFFFF); + +/* + * The following fields are used by CC32XX driverlib APIs and therefore + * must be populated by driverlib macro definitions. For CC32XX driverlib + * these definitions are found in: + * - inc/hw_memmap.h + * - driverlib/gpio.h + * - driverlib/pin.h + * - driverlib/timer.h + */ +static const uint32_t timerBaseAddresses[4] = { + TIMERA0_BASE, + TIMERA1_BASE, + TIMERA2_BASE, + TIMERA3_BASE, +}; + +static const uint32_t timerHalves[2] = { + TIMER_A, + TIMER_B, +}; + +static const uint32_t gpioBaseAddresses[4] = { + GPIOA0_BASE, + GPIOA1_BASE, + GPIOA2_BASE, + GPIOA3_BASE, +}; + +static const uint32_t gpioPinIndexes[8] = { + GPIO_PIN_0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, +}; + +#define PinConfigTimerPort(config) (((config) >> 28) & 0xF) +#define PinConfigTimerHalf(config) (((config) >> 24) & 0xF) +#define PinConfigGPIOPort(config) (((config) >> 20) & 0xF) +#define PinConfigGPIOPinIndex(config) (((config) >> 16) & 0xF) +#define PinConfigPinMode(config) (((config) >> 8) & 0xF) +#define PinConfigPin(config) (((config) >> 0) & 0x3F) + +extern uint32_t SystemCoreClock; + +/* + * ======== getDutyCounts ======== + */ +static uint32_t getDutyCounts(PWM_Duty_Units dutyUnits, uint32_t dutyValue, + uint32_t periodCounts) +{ + uint32_t duty = 0; + ClockP_FreqHz freq; + + freq.hi = 0; + freq.lo = SystemCoreClock; + + //ClockP_getCpuFreq(&freq); + + switch (dutyUnits) { + case PWM_DUTY_COUNTS: + duty = dutyValue; + break; + + case PWM_DUTY_FRACTION: + duty = (((uint64_t) dutyValue) * ((uint64_t) periodCounts)) / + PWM_DUTY_FRACTION_MAX; + break; + + case PWM_DUTY_US: + duty = (dutyValue != 0) ? (dutyValue * (freq.lo/1000000)) - 1 : 0; + break; + + default: + /* Unsupported duty units return an invalid duty */ + duty = PWM_INVALID_VALUE; + } + + return (duty); +} + +/* + * ======== getPeriodCounts ======== + */ +static uint32_t getPeriodCounts(PWM_Period_Units periodUnits, + uint32_t periodValue) +{ + uint32_t period = 0; + ClockP_FreqHz freq; + + freq.hi = 0; + freq.lo = SystemCoreClock; + + //ClockP_getCpuFreq(&freq); + + switch (periodUnits) { + case PWM_PERIOD_COUNTS: + period = periodValue; + break; + + case PWM_PERIOD_HZ: + if (periodValue && periodValue <= freq.lo) { + period = (freq.lo / periodValue) - 1; + } + break; + + case PWM_PERIOD_US: + period = (periodValue * (freq.lo/1000000)) - 1; + break; + + default: + /* Unsupported period units return an invalid period */ + period = PWM_INVALID_VALUE; + } + + return (period); +} + +/* + * ======== getPowerMgrId ======== + */ +static uint_fast16_t getPowerMgrId(uint32_t baseAddr) +{ + switch (baseAddr) { + case GPIOA0_BASE: + return (PowerCC32XX_PERIPH_GPIOA0); + case GPIOA1_BASE: + return (PowerCC32XX_PERIPH_GPIOA1); + case GPIOA2_BASE: + return (PowerCC32XX_PERIPH_GPIOA2); + case GPIOA3_BASE: + return (PowerCC32XX_PERIPH_GPIOA3); + case GPIOA4_BASE: + return (PowerCC32XX_PERIPH_GPIOA4); + default: + /* Should never get here */ + return ((unsigned int) -1); + } +} + +/* + * ======== initHw ======== + */ +static int initHw(PWM_Handle handle, uint32_t period, uint32_t duty) +{ + uintptr_t key; + int32_t result; + uint32_t timerConfigVal; + PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; + uint32_t timerBaseAddr; + uint16_t halfTimer; + + timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; + halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; + + key = HwiP_disable(); + + MAP_TimerDisable(timerBaseAddr, halfTimer); + + /* + * The CC32XX SDK TimerConfigure API halts both timers when it is + * used to configure a single half timer. The code below performs + * the register operations necessary to configure each half timer + * individually. + */ + /* Enable CCP to IO path */ + HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_GPT_TRIG_SEL) = 0xFF; + + /* Split the timer and configure it as a PWM */ + timerConfigVal = ((halfTimer & (TIMER_CFG_A_PWM | TIMER_CFG_B_PWM)) | + TIMER_CFG_SPLIT_PAIR); + HWREG(timerBaseAddr + TIMER_O_CFG) |= (timerConfigVal >> 24); + if (halfTimer & TIMER_A) { + HWREG(timerBaseAddr + TIMER_O_TAMR) = timerConfigVal & 255; + } + else { + HWREG(timerBaseAddr + TIMER_O_TBMR) = (timerConfigVal >> 8) & 255; + } + + /* Set the peripheral output to active-high */ + MAP_TimerControlLevel(timerBaseAddr, halfTimer, true); + + HwiP_restore(key); + + result = PWMTimerCC32XX_setPeriod(handle, period); + if (result != PWM_STATUS_SUCCESS) { + return (result); + } + + result = PWMTimerCC32XX_setDuty(handle, duty); + if (result != PWM_STATUS_SUCCESS) { + return (result); + } + + return (PWM_STATUS_SUCCESS); +} + +/* + * ======== postNotifyFxn ======== + * Called by Power module when waking up from LPDS. + */ +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg) +{ + PWM_Handle handle = (PWM_Handle) clientArg; + PWMTimerCC32XX_Object *object = handle->object; + + initHw(handle, object->period, object->duty); + + return (Power_NOTIFYDONE); +} + +/* + * ======== PWMTimerCC32XX_close ======== + * @pre Function assumes that the handle is not NULL + */ +void PWMTimerCC32XX_close(PWM_Handle handle) +{ + PWMTimerCC32XX_Object *object = handle->object; + PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; + TimerCC32XX_SubTimer subTimer; + uint32_t timerBaseAddr; + uint32_t gpioBaseAddr; + uint32_t padRegister; + uintptr_t key; + + timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; + + subTimer = (TimerCC32XX_SubTimer) (TimerCC32XX_timer16A + + PinConfigTimerHalf(hwAttrs->pwmPin)); + + /* + * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr + * is set to 0 & the GPIO power dependencies are not released. + */ + gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) == 0xF) ? + 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; + + PWMTimerCC32XX_stop(handle); + + key = HwiP_disable(); + + TimerCC32XX_freeTimerResource(timerBaseAddr, subTimer); + + /* Remove GPIO power dependency if pin is GPIO capable */ + if (gpioBaseAddr) { + Power_releaseDependency(getPowerMgrId(gpioBaseAddr)); + } + + Power_unregisterNotify(&object->postNotify); + + padRegister = (PinToPadGet((hwAttrs->pwmPin) & 0x3f)<<2) + PAD_CONFIG_BASE; + HWREG(padRegister) = PAD_RESET_STATE; + + object->isOpen = false; + + HwiP_restore(key); + + DebugP_log1("PWM:(%p) is closed", (uintptr_t) handle); +} + +/* + * ======== PWMTimerCC32XX_control ======== + * @pre Function assumes that the handle is not NULL + */ +int_fast16_t PWMTimerCC32XX_control(PWM_Handle handle, uint_fast16_t cmd, + void *arg) +{ + /* No implementation yet */ + return (PWM_STATUS_UNDEFINEDCMD); +} + +/* + * ======== PWMTimerCC32XX_init ======== + * @pre Function assumes that the handle is not NULL + */ +void PWMTimerCC32XX_init(PWM_Handle handle) +{ +} + +/* + * ======== PWMTimerCC32XX_open ======== + * @pre Function assumes that the handle is not NULL + */ +PWM_Handle PWMTimerCC32XX_open(PWM_Handle handle, PWM_Params *params) +{ + uintptr_t key; + PWMTimerCC32XX_Object *object = handle->object; + PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; + TimerCC32XX_SubTimer subTimer; + uint32_t timerBaseAddr; + uint32_t gpioBaseAddr; + uint16_t pin; + + timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; + pin = PinConfigPin(hwAttrs->pwmPin); + + subTimer = (TimerCC32XX_SubTimer) (TimerCC32XX_timer16A + + PinConfigTimerHalf(hwAttrs->pwmPin)); + + key = HwiP_disable(); + + if (object->isOpen) { + HwiP_restore(key); + + DebugP_log1("PWM:(%p) already opened.", (uintptr_t) handle); + + return (NULL); + } + + if (!TimerCC32XX_allocateTimerResource(timerBaseAddr, subTimer)) { + HwiP_restore(key); + + DebugP_log1("Timer: 0x%X unavailable.", timerBaseAddr); + + return (NULL); + } + + object->isOpen = true; + + HwiP_restore(key); + + /* + * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr + * is set to 0 & the GPIO power dependencies are not set. + */ + gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) == 0xF) ? + 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; + + /* Set GPIO power dependency if pin is GPIO capable */ + if (gpioBaseAddr) { + /* Check GPIO power resource Id */ + if (getPowerMgrId(gpioBaseAddr) == ((unsigned int) -1)) { + TimerCC32XX_freeTimerResource(timerBaseAddr, subTimer); + + object->isOpen = false; + + DebugP_log1("PWM:(%p) Failed to determine GPIO power resource ID.", + (uintptr_t) handle); + + return (NULL); + } + + /* Register power dependency for GPIO port */ + Power_setDependency(getPowerMgrId(gpioBaseAddr)); + } + + Power_registerNotify(&object->postNotify, PowerCC32XX_AWAKE_LPDS, + postNotifyFxn, (uintptr_t) handle); + + /* + * Set PWM duty to initial value (not 0) - required when inverting + * output polarity to generate a duty equal to 0 or period. See comments in + * PWMTimerCC32XX_setDuty for more information. + */ + object->duty = 0; + object->period = 0; + object->dutyUnits = params->dutyUnits; + object->idleLevel = params->idleLevel; + object->periodUnits = params->periodUnits; + object->pwmStarted = 0; + + /* Initialize the peripheral & set the period & duty */ + if (initHw(handle, params->periodValue, params->dutyValue) != + PWM_STATUS_SUCCESS) { + PWMTimerCC32XX_close(handle); + + DebugP_log1("PWM:(%p) Failed set initial PWM configuration.", + (uintptr_t) handle); + + return (NULL); + } + + /* Configure the Power_pinParkState based on idleLevel param */ + PowerCC32XX_setParkState((PowerCC32XX_Pin) pin, + (object->idleLevel == PWM_IDLE_HIGH)); + + /* Called to set the initial idleLevel */ + PWMTimerCC32XX_stop(handle); + + DebugP_log3("PWM:(%p) opened; period set to: %d; duty set to: %d", + (uintptr_t) handle, params->periodValue, params->dutyValue); + + return (handle); +} + +/* + * ======== PWMTimerCC32XX_setDuty ======== + * @pre Function assumes that handle is not NULL + */ +int_fast16_t PWMTimerCC32XX_setDuty(PWM_Handle handle, uint32_t dutyValue) +{ + uintptr_t key; + uint32_t duty; + uint32_t period; + PWMTimerCC32XX_Object *object = handle->object; + PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; + uint32_t timerBaseAddr; + uint16_t halfTimer; + + timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; + halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; + + key = HwiP_disable(); + + period = object->period; + duty = getDutyCounts(object->dutyUnits, dutyValue, period); + + if (duty == PWM_INVALID_VALUE) { + HwiP_restore(key); + + DebugP_log1("PWM:(%p) duty units could not be determined.", + (uintptr_t) handle); + + return (PWM_STATUS_ERROR); + } + + if (duty > period) { + HwiP_restore(key); + + DebugP_log1("PWM:(%p) duty is out of range.", (uintptr_t) handle); + + return (PWM_STATUS_INVALID_DUTY); + } + + /* + * The timer peripheral cannot generate a duty equal to the period when + * the timer is counting down. In these cases the PWM duty is set to the + * period value (output remains low) and output polarity is inverted. + * Additionally, if the output is changed from the period the PWM output + * polarity must be inverted again. + * + * The code below uses the previous duty (object->duty) and the new duty to + * determine if the polarity should be inverted. + * For more details refer to the device specific datasheet and the following + * E2E post: + * http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/354826.aspx + */ + if (((duty == period) && (object->duty != period)) || + ((duty != period) && (object->duty == period))) { + HWREG(timerBaseAddr + TIMER_O_CTL) ^= + (halfTimer & (TIMER_CTL_TAPWML | TIMER_CTL_TBPWML)); + } + + /* + * Set & store the new duty. IMPORTANT: this must be saved after output + * inversion is determined and before the duty = 0 corner case. + */ + object->duty = duty; + + /* + * Special corner case, if duty is 0 we set it to the period without + * inverting output + */ + if (duty == 0) { + duty = period; + } + + MAP_TimerPrescaleMatchSet(timerBaseAddr, halfTimer, + duty / PWM_MAX_MATCH_REG_VALUE); + MAP_TimerMatchSet(timerBaseAddr, halfTimer, + duty % PWM_MAX_MATCH_REG_VALUE); + + HwiP_restore(key); + + DebugP_log2("PWM:(%p) duty set to: %d", (uintptr_t) handle, dutyValue); + + return (PWM_STATUS_SUCCESS); +} + +/* + * ======== PWMTimerCC32XX_setPeriod ======== + * @pre Function assumes that handle is not NULL + */ +int_fast16_t PWMTimerCC32XX_setPeriod(PWM_Handle handle, uint32_t periodValue) +{ + uintptr_t key; + uint32_t duty; + uint32_t period; + PWMTimerCC32XX_Object *object = handle->object; + PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; + uint32_t timerBaseAddr; + uint16_t halfTimer; + + timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; + halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; + + key = HwiP_disable(); + + duty = object->duty; + period = getPeriodCounts(object->periodUnits, periodValue); + + if (period == PWM_INVALID_VALUE) { + HwiP_restore(key); + + DebugP_log1("PWM:(%p) period units could not be determined.", + (uintptr_t) handle); + + return (PWM_STATUS_ERROR); + } + + if ((period == 0) || (period <= duty) || (period > PWM_MAX_PERIOD_COUNT)) { + HwiP_restore(key); + + DebugP_log1("PWM:(%p) period is out of range.", (uintptr_t) handle); + + return (PWM_STATUS_INVALID_PERIOD); + } + + /* Set the new period */ + object->period = period; + MAP_TimerPrescaleSet(timerBaseAddr, halfTimer, + period / PWM_MAX_MATCH_REG_VALUE); + MAP_TimerLoadSet(timerBaseAddr, halfTimer, + period % PWM_MAX_MATCH_REG_VALUE); + + HwiP_restore(key); + + DebugP_log2("PWM:(%p) period set to: %d", (uintptr_t) handle, periodValue); + + return (PWM_STATUS_SUCCESS); +} + +/* + * ======== PWMTimerCC32XX_start ======== + * @pre Function assumes that handle is not NULL + */ +void PWMTimerCC32XX_start(PWM_Handle handle) +{ + uintptr_t key; + PWMTimerCC32XX_Object *object = handle->object; + PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; + uint32_t timerBaseAddr; + uint16_t halfTimer; + uint16_t pin; + uint16_t mode; + + timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; + halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; + pin = PinConfigPin(hwAttrs->pwmPin); + mode = PinConfigPinMode(hwAttrs->pwmPin); + + key = HwiP_disable(); + + /* + * GP timer ticks only in Active mode. Cannot be used in HIB or LPDS. + * Set constraint to disallow LPDS. + */ + if (!(object->pwmStarted)) { + Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); + object->pwmStarted = true; + } + + /* Start the timer & set pinmux to PWM mode */ + MAP_TimerEnable(timerBaseAddr, halfTimer); + + MAP_PinTypeTimer((unsigned long)pin, (unsigned long)mode); + + HwiP_restore(key); + + DebugP_log1("PWM:(%p) started.", (uintptr_t) handle); +} + +/* + * ======== PWMTimerCC32XX_stop ======== + * @pre Function assumes that handle is not NULL + */ +void PWMTimerCC32XX_stop(PWM_Handle handle) +{ + uintptr_t key; + uint8_t output; + PWMTimerCC32XX_Object *object = handle->object; + PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; + uint32_t timerBaseAddr; + uint16_t halfTimer; + uint32_t gpioBaseAddr; + uint8_t gpioPinIndex; + uint16_t pin; + + timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; + halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; + pin = PinConfigPin(hwAttrs->pwmPin); + + /* + * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr + * is set to 0 & the GPIO power dependencies are not set. + */ + gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) == 0xF) ? + 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; + gpioPinIndex = (PinConfigGPIOPinIndex(hwAttrs->pwmPin) == 0xF) ? + 0 : gpioPinIndexes[PinConfigGPIOPinIndex(hwAttrs->pwmPin)]; + + key = HwiP_disable(); + + /* Remove the dependency to allow LPDS */ + if (object->pwmStarted) { + Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); + object->pwmStarted = false; + } + + /* Set pin as GPIO with IdleLevel value & stop the timer */ + output = (object->idleLevel) ? gpioPinIndex : 0; + MAP_PinTypeGPIO((unsigned long)pin, PIN_MODE_0, false); + + /* Only configure the pin as GPIO if the pin is GPIO capable */ + if (gpioBaseAddr) { + MAP_GPIODirModeSet(gpioBaseAddr, gpioPinIndex, GPIO_DIR_MODE_OUT); + MAP_GPIOPinWrite(gpioBaseAddr, gpioPinIndex, output); + } + + /* Stop the Timer */ + MAP_TimerDisable(timerBaseAddr, halfTimer); + + HwiP_restore(key); + + DebugP_log1("PWM:(%p) stopped.", (uintptr_t) handle); +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.h new file mode 100644 index 00000000000..18601e5d16f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.h @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! ============================================================================ + * @file PWMTimerCC32XX.h + * + * @brief PWM driver implementation using CC32XX General Purpose Timers. + * + * The PWM header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref PWM.h for a complete description of the PWM + * driver APIs provided and examples of their use. + * + * ## Overview # + * This driver configures a CC32XX General Purpose Timer (GPT) in PWM mode. + * When in PWM mode, each GPT is divided into 2 PWM outputs. This driver + * manages each output as an independent PWM instance. The timer is + * automatically configured in count-down mode using the system clock as + * the source. + * + * The timers operate at the system clock frequency (80 MHz). So each timer + * tick is 12.5 ns. The period and duty registers are 16 bits wide; thus + * 8-bit prescalars are used to extend period and duty registers. The + * maximum value supported is 16777215 timer counts ((2^24) - 1) or + * 209715 microseconds. Updates to a PWM's period or duty will occur + * instantaneously (GPT peripherals do not have shadow registers). + * + * When stopped, the driver will configure the pin in GPIO mode & set the + * output to the PWM_IdleLevel specified in the params used during open. Users + * need be aware that while PIN 19 can be used for PWM it is not GPIO capable, + * so it cannot be set to the PWM_IdleLevel. Output voltage will be PWM output + * at the moment it is stopped. + * + * Finally, when this driver is opened, it automatically changes the + * PWM pin's parking configuration (used when entering low power modes) to + * correspond with the PWM_IDLE_LEVEL set in the PWM_params. However, this + * setting is not reverted once the driver is closed, it is the users + * responsibility to change the parking configuration if necessary. + * + * ### CC32xx PWM Driver Configuration # + * + * In order to use the PWM APIs, the application is required + * to define 4 configuration items in the application Board.c file: + * + * 1. An array of PWMTimerCC32XX_Object elements, which will be used by + * by the driver to maintain instance state. + * Below is an example PWMTimerCC32XX_Object array appropriate for the CC3220SF Launchpad + * board: + * @code + * #include + * #include + * + * PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; + * @endcode + * + * 2. An array of PWMTimerCC32XX_HWAttrsV2 elements that defines which + * pin will be used by the corresponding PWM instance + * (see @ref pwmPinIdentifiersCC32XX). + * Below is an example PWMTimerCC32XX_HWAttrsV2 array appropriate for the CC3220SF Launchpad + * board: + * @code + * const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { + * { + * .pwmPin = PWMTimerCC32XX_PIN_01 + * }, + * { + * .pwmPin = PWMTimerCC32XX_PIN_02 + * } + * }; + * @endcode + * + * 3. An array of @ref PWM_Config elements, one for each PWM instance. Each + * element of this array identifies the device-specific API function table, + * the device specific PWM object instance, and the device specific Hardware + * Attributes to be used for each PWM channel. + * Below is an example @ref PWM_Config array appropriate for the CC3220SF Launchpad + * board: + * @code + * const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { + * { + * .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + * .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], + * .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] + * }, + * { + * .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + * .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], + * .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] + * } + * }; + * @endcode + * + * 4. A global variable, PWM_count, that informs the driver how many PWM + * instances are defined: + * @code + * const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; + * @endcode + * + * ### Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The PWMTimerCC32XX driver explicitly sets a power constraint when the + * PWM is running to prevent LPDS. + * The following statements are valid: + * - After PWM_open(): Clocks are enabled to the timer resource and the + * configured pwmPin. The device is still allowed + * to enter LPDS. + * - After PWM_start(): LPDS is disabled when PWM is running. + * - After PWM_stop(): Conditions are equal as for after PWM_open + * - After PWM_close(): The underlying GPTimer is turned off, and the clocks + * to the timer and pin are disabled.. + * + * ============================================================================= + */ + +#ifndef ti_driver_pwm_PWMTimerCC32XX__include +#define ti_driver_pwm_PWMTimerCC32XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! \cond */ +/* + * PWMTimer port/pin defines for pin configuration. + * + * The timer id (0, 1, 2, or 3) is stored in bits 31 - 28 + * The timer half (0 = A, 1 = B) is stored in bits 27 - 24 + * The GPIO port (0, 1, 2, or 3) is stored in bits 23 - 20 + * The GPIO pin index within the port (0 - 7) is stored in bits 19 - 16 + * The pin mode is stored in bits 11 - 8 + * The pin number is stored in bits 7 - 0 + * + * + * 31 - 28 27 - 24 23 - 20 19 - 16 11 - 8 7 - 0 + * ----------------------------------------------------------------------- + * | Timer id | Timer half | GPIO port | GPIO pin index | pin mode | pin | + * ----------------------------------------------------------------------- + * + * The CC32XX has fixed GPIO assignments and pin modes for a given pin. + * A PWM pin mode for a given pin has a fixed timer/timer-half. + */ +#define PWMTimerCC32XX_T0A (0x00 << 24) +#define PWMTimerCC32XX_T0B (0x01 << 24) +#define PWMTimerCC32XX_T1A (0x10 << 24) +#define PWMTimerCC32XX_T1B (0x11 << 24) +#define PWMTimerCC32XX_T2A (0x20 << 24) +#define PWMTimerCC32XX_T2B (0x21 << 24) +#define PWMTimerCC32XX_T3A (0x30 << 24) +#define PWMTimerCC32XX_T3B (0x31 << 24) + +#define PWMTimerCC32XX_GPIO9 (0x11 << 16) +#define PWMTimerCC32XX_GPIO10 (0x12 << 16) +#define PWMTimerCC32XX_GPIO11 (0x13 << 16) +#define PWMTimerCC32XX_GPIO24 (0x30 << 16) +#define PWMTimerCC32XX_GPIO25 (0x31 << 16) + +#define PWMTimerCC32XX_GPIONONE (0xFF << 16) +/*! \endcond */ + +/*! + * \defgroup pwmPinIdentifiersCC32XX PWMTimerCC32XX_HWAttrs 'pwmPin' field options + * @{ + */ +/*! + * @name PIN 01, GPIO10, uses Timer3A for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_01 (PWMTimerCC32XX_T3A | PWMTimerCC32XX_GPIO10 | 0x0300) /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 02, GPIO11, uses Timer3B for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_02 (PWMTimerCC32XX_T3B | PWMTimerCC32XX_GPIO11 | 0x0301) /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 17, GPIO24, uses Timer0A for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_17 (PWMTimerCC32XX_T0A | PWMTimerCC32XX_GPIO24 | 0x0510) /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 19, uses Timer1B for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_19 (PWMTimerCC32XX_T1B | PWMTimerCC32XX_GPIONONE | 0x0812) /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 21, GPIO25, uses Timer1A for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_21 (PWMTimerCC32XX_T1A | PWMTimerCC32XX_GPIO25 | 0x0914) /*!< @hideinitializer */ +/*! @} */ +/*! + * @name PIN 64, GPIO9, uses Timer2B for PWM. + * @{ + */ +#define PWMTimerCC32XX_PIN_64 (PWMTimerCC32XX_T2B | PWMTimerCC32XX_GPIO9 | 0x033F) /*!< @hideinitializer */ +/*! @} */ +/*! @} */ + +/** + * @addtogroup PWM_STATUS + * PWMTimerCC32XX_STATUS_* macros are command codes only defined in the + * PWMTimerCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add PWMTimerCC32XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup PWM_CMD + * PWMTimerCC32XX_CMD_* macros are command codes only defined in the + * PWMTimerCC32XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add PWMTimerCC32XX_CMD_* macros here */ + +/** @}*/ + +/* PWM function table pointer */ +extern const PWM_FxnTable PWMTimerCC32XX_fxnTable; + +/*! + * @brief PWMTimerCC32XX Hardware attributes + * + * The 'pwmPin' field identifies which physical pin to use for a + * particular PWM channel as well as the corresponding Timer resource used + * to source the PWM signal. The encoded pin identifier macros for + * initializing the 'pwmPin' field must be selected from the + * @ref pwmPinIdentifiersCC32XX macros. + * + * A sample structure is shown below: + * @code + * const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC32XXHWAttrs[] = { + * { + * .pwmPin = PWMTimerCC32XX_PIN_01, + * }, + * { + * .pwmPin = PWMTimerCC32XX_PIN_02, + * } + * }; + * @endcode + */ +typedef struct PWMTimerCC32XX_HWAttrsV2 { + uint32_t pwmPin; /*!< Pin to output PWM signal on + (see @ref pwmPinIdentifiersCC32XX) */ +} PWMTimerCC32XX_HWAttrsV2; + +/*! + * @brief PWMTimerCC32XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct PWMTimerCC32XX_Object { + Power_NotifyObj postNotify; + uint32_t duty; /* Current duty cycle in Duty_Unites */ + uint32_t period; /* Current period PERIOD_Units */ + PWM_Duty_Units dutyUnits; /* Current duty cycle unit */ + PWM_Period_Units periodUnits; /* Current period unit */ + PWM_IdleLevel idleLevel; /* PWM idle level when stopped / not started */ + bool pwmStarted; /* Used to gate Power_set/releaseConstraint() calls */ + bool isOpen; /* open flag used to check if PWM is opened */ +} PWMTimerCC32XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_driver_pwm_PWMTimerCC32XX__include */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.c new file mode 100644 index 00000000000..9abfbda61e2 --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.c @@ -0,0 +1,605 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +/* + * This macro is used to determine a logical shift value for the + * timerState.bitMask. Each timer peripheral occupies two bits in + * timerState.bitMask. + * + * The timer peripherals' base addresses have an offset of 0x1000 starting at + * 0x40030000. That byte is masked using 0xF000 which can result in a value + * ranging from 0x0000 to 0x3000 for this particular hardware instance. This + * value is then shifted right by 12 into the LSB. Lastly, the value is + * multiplied by two because there are two bits in the timerState.bitMask for + * each timer. The value returned is used for the logical shift. + */ +#define timerMaskShift(baseAddress) ((((baseAddress) & 0XF000) >> 12) * 2) + +void TimerCC32XX_close(Timer_Handle handle); +int_fast16_t TimerCC32XX_control(Timer_Handle handle, + uint_fast16_t cmd, void *arg); +uint32_t TimerCC32XX_getCount(Timer_Handle handle); +void TimerCC32XX_init(Timer_Handle handle); +Timer_Handle TimerCC32XX_open(Timer_Handle handle, Timer_Params *params); +int32_t TimerCC32XX_start(Timer_Handle handle); +void TimerCC32XX_stop(Timer_Handle handle); + +/* Internal static Functions */ +static void initHw(Timer_Handle handle); +static void getPrescaler(Timer_Handle handle); +static uint32_t getPowerMgrId(uint32_t baseAddress); +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg); +static void TimerCC32XX_hwiIntFunction(uintptr_t arg); + +/* Function table for TimerCC32XX implementation */ +const Timer_FxnTable TimerCC32XX_fxnTable = { + .closeFxn = TimerCC32XX_close, + .openFxn = TimerCC32XX_open, + .startFxn = TimerCC32XX_start, + .stopFxn = TimerCC32XX_stop, + .initFxn = TimerCC32XX_init, + .getCountFxn = TimerCC32XX_getCount, + .controlFxn = TimerCC32XX_control +}; + +/* + * Internal Timer status structure + * + * bitMask: Each timer peripheral occupies two bits in the bitMask. The least + * significant bit represents the first half width timer, TimerCC32XX_timer16A + * and the most significant bit represents the second half width timer, + * TimerCC32XX_timer16B. If the full width timer, TimerCC32XX_timer32, is used, + * both bits are set to 1. + + * 31 - 8 7 - 6 5 - 4 3 - 2 1 - 0 + * ------------------------------------------------ + * | Reserved | Timer3 | Timer2 | Timer1 | Timer0 | + * ------------------------------------------------ + */ +static struct { + uint32_t bitMask; +} timerState; + +/* + * ======== initHw ======== + */ +static void initHw(Timer_Handle handle) +{ + TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + TimerCC32XX_Object const *object = handle->object; + + /* Ensure the timer is disabled */ + TimerDisable(hwAttrs->baseAddress, object->timer); + + if (object->timer == TIMER_A) { + + HWREG(hwAttrs->baseAddress + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD; + } + else { + + HWREG(hwAttrs->baseAddress + TIMER_O_TBMR) = TIMER_TBMR_TBMR_PERIOD; + } + + if (hwAttrs->subTimer == TimerCC32XX_timer32) { + + HWREG(hwAttrs->baseAddress + TIMER_O_CFG) = TIMER_CFG_32_BIT_TIMER; + } + else { + + HWREG(hwAttrs->baseAddress + TIMER_O_CFG) = TIMER_CFG_16_BIT; + } + + /* Disable all interrupts */ + HWREG(hwAttrs->baseAddress + TIMER_O_IMR) = ~object->timer; + + /* Writing the PSR Register has no effect for full width 32-bit mode */ + TimerPrescaleSet(hwAttrs->baseAddress, object->timer, object->prescaler); + TimerLoadSet(hwAttrs->baseAddress, object->timer, object->period); + + /* This function controls the stall response for the timer. When true, + * the timer stops counting if the processor enters debug mode. The + * default setting for the hardware is false. + */ + TimerControlStall(hwAttrs->baseAddress, object->timer, true); +} + +/* + * ========= getPrescaler ========= + * This function calculates the prescaler and timer interval load register + * for a half timer. The handle is assumed to contain a object->period which + * represents the number of clock cycles in the desired period. The calling + * function, TimerCC32XX_open() checks for overflow before calling this function. + * Therefore, this function is guaranteed to never fail. + */ +static void getPrescaler(Timer_Handle handle) +{ + TimerCC32XX_Object *object = handle->object; + uint32_t bestDiff = ~0, bestPsr = 0, bestIload = 0; + uint32_t diff, intervalLoad, prescaler; + + /* Loop over the 8-bit prescaler */ + for (prescaler = 1; prescaler < 256; prescaler++) { + + /* Calculate timer interval load */ + intervalLoad = object->period / (prescaler + 1); + + /* Will this fit in 16-bits? */ + if (intervalLoad > (uint16_t) ~0) { + continue; + } + + /* How close is the intervalLoad to what we actually want? */ + diff = object->period - intervalLoad * (prescaler + 1); + + /* If it is closer to what we want */ + if (diff <= bestDiff) { + + /* If its a perfect match */ + if (diff == 0) { + object->period = intervalLoad; + object->prescaler = prescaler; + + return; + } + + /* Snapshot in case we don't find something better */ + bestDiff = diff; + bestPsr = prescaler; + bestIload = intervalLoad; + } + } + + /* Never found a perfect match, settle for the best */ + object->period = bestIload; + object->prescaler = bestPsr; +} + +/* + * ======== getPowerMgrId ======== + */ +static uint32_t getPowerMgrId(uint32_t baseAddress) +{ + switch (baseAddress) { + + case TIMERA0_BASE: + + return (PowerCC32XX_PERIPH_TIMERA0); + + case TIMERA1_BASE: + + return (PowerCC32XX_PERIPH_TIMERA1); + + case TIMERA2_BASE: + + return (PowerCC32XX_PERIPH_TIMERA2); + + case TIMERA3_BASE: + + return (PowerCC32XX_PERIPH_TIMERA3); + + default: + + return ((uint32_t) -1); + } +} + +/* + * ======== postNotifyFxn ======== + * This functions is called when a transition from LPDS mode is made. + * clientArg should be a handle of a previously opened Timer instance. + */ +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg) +{ + initHw((Timer_Handle) clientArg); + + return (Power_NOTIFYDONE); +} + +/* + * ======== TimerCC32XX_allocateTimerResource ======== + */ +bool TimerCC32XX_allocateTimerResource(uint32_t baseAddress, + TimerCC32XX_SubTimer subTimer) +{ + uintptr_t key; + uint32_t mask; + uint32_t powerMgrId; + bool status; + + powerMgrId = getPowerMgrId(baseAddress); + + if (powerMgrId == (uint32_t) -1) { + + return (false); + } + + mask = subTimer << timerMaskShift(baseAddress); + + key = HwiP_disable(); + + if (timerState.bitMask & mask) { + + status = false; + } + else { + + Power_setDependency(powerMgrId); + timerState.bitMask = timerState.bitMask | mask; + status = true; + } + + HwiP_restore(key); + + return (status); +} + +/* + * ======== TimerCC32XX_close ======== + */ +void TimerCC32XX_close(Timer_Handle handle) +{ + TimerCC32XX_Object *object = handle->object; + TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Stopping the Timer before closing it */ + TimerCC32XX_stop(handle); + + Power_unregisterNotify(&(object->notifyObj)); + + if (object->hwiHandle) { + + HwiP_clearInterrupt(hwAttrs->intNum); + HwiP_delete(object->hwiHandle); + object->hwiHandle = NULL; + } + + if (object->timerSem) { + + SemaphoreP_delete(object->timerSem); + object->timerSem = NULL; + } + + TimerCC32XX_freeTimerResource(hwAttrs->baseAddress, hwAttrs->subTimer); +} + +/* + * ======== TimerCC32XX_control ======== + */ +int_fast16_t TimerCC32XX_control(Timer_Handle handle, + uint_fast16_t cmd, void *arg) +{ + return (Timer_STATUS_UNDEFINEDCMD); +} + +/* + * ======== TimerCC32XX_freeTimerResource ======== + */ +void TimerCC32XX_freeTimerResource(uint32_t baseAddress, + TimerCC32XX_SubTimer subTimer) +{ + uintptr_t key; + uint32_t mask; + + mask = subTimer << timerMaskShift(baseAddress); + + key = HwiP_disable(); + + timerState.bitMask = (timerState.bitMask & ~mask); + + Power_releaseDependency(getPowerMgrId(baseAddress)); + + HwiP_restore(key); +} + +/* + * ======== TimerCC32XX_getCount ======== + */ +uint32_t TimerCC32XX_getCount(Timer_Handle handle) +{ + TimerCC32XX_HWAttrs const *hWAttrs = handle->hwAttrs; + TimerCC32XX_Object const *object = handle->object; + uint32_t count; + + if (object->timer == TIMER_A) { + count = HWREG(hWAttrs->baseAddress + TIMER_O_TAR); + } + else { + count = HWREG(hWAttrs->baseAddress + TIMER_O_TBR); + } + + /* Virtual up counter */ + count = object->period - count; + + return (count); +} + +/* + * ======== TimerCC32XX_hwiIntFunction ======== + */ +void TimerCC32XX_hwiIntFunction(uintptr_t arg) +{ + Timer_Handle handle = (Timer_Handle) arg; + TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + TimerCC32XX_Object const *object = handle->object; + uint32_t interruptMask; + + /* Only clear the interrupt for this->object->timer */ + interruptMask = object->timer & (TIMER_TIMA_TIMEOUT | TIMER_TIMB_TIMEOUT); + TimerIntClear(hwAttrs->baseAddress, interruptMask); + + /* Hwi is not created when using Timer_FREE_RUNNING */ + if (object->mode != Timer_CONTINUOUS_CALLBACK) { + TimerCC32XX_stop(handle); + } + + if (object-> mode != Timer_ONESHOT_BLOCKING) { + object->callBack(handle); + } +} + +/* + * ======== TimerCC32XX_init ======== + */ +void TimerCC32XX_init(Timer_Handle handle) +{ + return; +} + +/* + * ======== TimerCC32XX_open ======== + */ +Timer_Handle TimerCC32XX_open(Timer_Handle handle, Timer_Params *params) +{ + TimerCC32XX_Object *object = handle->object; + TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + SemaphoreP_Params semParams; + HwiP_Params hwiParams; + ClockP_FreqHz clockFreq; + + /* Check for valid parameters */ + if (((params->timerMode == Timer_ONESHOT_CALLBACK || + params->timerMode == Timer_CONTINUOUS_CALLBACK) && + params->timerCallback == NULL) || + params->period == 0) { + + return (NULL); + } + + if (!TimerCC32XX_allocateTimerResource(hwAttrs->baseAddress, + hwAttrs->subTimer)) { + + return (NULL); + } + + Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, + postNotifyFxn, (uintptr_t) handle); + + object->mode = params->timerMode; + object->isRunning = false; + object->callBack = params->timerCallback; + object->period = params->period; + object->prescaler = 0; + + if (hwAttrs->subTimer == TimerCC32XX_timer16B) { + + object->timer = TIMER_B; + } + else { + + object->timer = TIMER_A; + } + + if (object->mode != Timer_FREE_RUNNING) { + + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t) handle; + hwiParams.priority = hwAttrs->intPriority; + object->hwiHandle = HwiP_create(hwAttrs->intNum, + TimerCC32XX_hwiIntFunction, &hwiParams); + + if (object->hwiHandle == NULL) { + + TimerCC32XX_close(handle); + + return (NULL); + } + + } + + /* Creating the semaphore if mode is blocking */ + if (params->timerMode == Timer_ONESHOT_BLOCKING) { + + SemaphoreP_Params_init(&semParams); + semParams.mode = SemaphoreP_Mode_BINARY; + object->timerSem = SemaphoreP_create(0, &semParams); + + if (object->timerSem == NULL) { + + TimerCC32XX_close(handle); + + return (NULL); + } + } + + /* Formality; CC32XX System Clock fixed to 80.0 MHz */ + ClockP_getCpuFreq(&clockFreq); + + if (params->periodUnits == Timer_PERIOD_US) { + + /* Checks if the calculated period will fit in 32-bits */ + if (object->period >= ((uint32_t) ~0) / (clockFreq.lo / 1000000)) { + + TimerCC32XX_close(handle); + + return (NULL); + } + + object->period = object->period * (clockFreq.lo / 1000000); + } + else if (params->periodUnits == Timer_PERIOD_HZ) { + + /* If (object->period) > clockFreq */ + if ((object->period = clockFreq.lo / object->period) == 0) { + + TimerCC32XX_close(handle); + + return (NULL); + } + } + + /* If using a half timer */ + if (hwAttrs->subTimer != TimerCC32XX_timer32) { + + if (object->period > 0xFFFF) { + + /* 24-bit resolution for the half timer */ + if (object->period >= (1 << 24)) { + + TimerCC32XX_close(handle); + + return (NULL); + } + + getPrescaler(handle); + } + } + + initHw(handle); + + return (handle); +} + +/* + * ======== TimerCC32XX_start ======== + */ +int32_t TimerCC32XX_start(Timer_Handle handle) +{ + TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + TimerCC32XX_Object *object = handle->object; + uint32_t interruptMask; + uintptr_t key; + + interruptMask = object->timer & (TIMER_TIMB_TIMEOUT | TIMER_TIMA_TIMEOUT); + + key = HwiP_disable(); + + if (object->isRunning) { + + HwiP_restore(key); + + return (Timer_STATUS_ERROR); + } + + object->isRunning = true; + + if (object->hwiHandle) { + + TimerIntEnable(hwAttrs->baseAddress, interruptMask); + } + + Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); + + /* Reload the timer */ + if (object->timer == TIMER_A) { + HWREG(hwAttrs->baseAddress + TIMER_O_TAMR) |= TIMER_TAMR_TAILD; + } + else { + HWREG(hwAttrs->baseAddress + TIMER_O_TBMR) |= TIMER_TBMR_TBILD; + } + + TimerEnable(hwAttrs->baseAddress, object->timer); + + HwiP_restore(key); + + if (object->mode == Timer_ONESHOT_BLOCKING) { + + /* Pend forever, ~0 */ + SemaphoreP_pend(object->timerSem, ~0); + } + + return (Timer_STATUS_SUCCESS); +} + +/* + * ======== TimerCC32XX_stop ======== + */ +void TimerCC32XX_stop(Timer_Handle handle) +{ + TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; + TimerCC32XX_Object *object = handle->object; + uint32_t interruptMask; + uintptr_t key; + bool flag = false; + + interruptMask = object->timer & (TIMER_TIMB_TIMEOUT | TIMER_TIMA_TIMEOUT); + + key = HwiP_disable(); + + if (object->isRunning) { + + object->isRunning = false; + + /* Post the Semaphore when called from the Hwi */ + if (object->mode == Timer_ONESHOT_BLOCKING) { + flag = true; + } + + TimerDisable(hwAttrs->baseAddress, object->timer); + TimerIntDisable(hwAttrs->baseAddress, interruptMask); + Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); + } + + HwiP_restore(key); + + if (flag) { + SemaphoreP_post(object->timerSem); + } +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.h new file mode 100644 index 00000000000..f8f3a0de91f --- /dev/null +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/timer/TimerCC32XX.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file TimerCC32XX.h + * @brief Timer driver interface for CC32XX devices + * + * # Operation # + * This driver implements half and full width general purpose timers for the + * CC32XX device. For CC32XX devices, the system clock is 80 MHz and a 16-bit + * timer has an 8-bit prescaler. The desired period may not always be + * achieved due to hardware limitations, such as the aforementioned. The timer + * resolution is limited to 12.5ns due to the 80 MHz clock. A timer period no + * greater than 209,714us can be achieved when operating in 16-bit mode. + * Similarly, a period no greater than 53,687,090us can be achieved when + * operating in 32-bit mode. The same time constraints apply to the 16-bit + * timer when attempting to use a frequency less than 5 Hertz. For additional + * details, refer to the device's technical reference manual. + * + * The timer always operates in count down mode. When using a half width timer, + * an 8-bit prescaler will be implemented by the driver if necessary. If the + * timer is operating in Timer_FREE_RUNNING, the timer will count down from the + * specified period to 0 before restarting. + * + * When using a half width timer, Timer_getCount() will return the + * value of the counter in bits 15:0 and bits 23:16 will contain the + * current free-running value of the prescaler. Bits 31:24 are always 0. + * When using a full width timer, Timer_getCount() will return the + * the value of the 32-bit timer. + * + * #Timer_ONESHOT_CALLBACK is non-blocking. After Timer_start() is called, + * the calling thread will continue execution. When the timer interrupt + * is triggered, the specified callback function will be called. The timer + * will not generate another interrupt unless Timer_start() is called again. + * Calling Timer_stop() or Timer_close() after Timer_start() but, before the + * timer interrupt, will prevent the specified callback from ever being + * invoked. + * + * #Timer_ONESHOT_BLOCKING is a blocking call. A semaphore is used to block + * the calling thead's execution until the timer generates an interrupt. If + * Timer_stop() is called, the calling thread will become unblocked + * immediately. The behavior of the timer in this mode is similar to a sleep + * function. + * + * #Timer_CONTINUOUS_CALLBACK is non-blocking. After Timer_start() is called, + * the calling thread will continue execution. When the timer interrupt is + * treiggered, the specified callback function will be called. The timer is + * automatically restarted and will continue to periodically generate + * interrupts until Timer_stop() is called. + * + * #Timer_FREE_RUNNING is non-blocking. After Timer_start() is called, + * the calling thread will continue execution. The timer will not + * generate an interrupt in this mode. The timer will count down from the + * specified period until it reaches 0. The timer will automatically reload + * the period and start over. The timer will continue running until + * Timer_stop() is called. + * + * # Resource Allocation # + * Each general purpose timer block contains two timers, Timer A and Timer B, + * that can be configured to operate independently; or concatenated to operate + * as one 32-bit timer. This behavior is managed through a set of resource + * allocation APIs. For example, the TimerCC32XX_allocateTimerResource API + * will allocate a timer for exclusive use. Any attempt to allocate this + * resource in the future will result in a false value being returned from the + * allocation API. To free a timer resource, the TimerCC32XX_freeTimerResource + * is used. The application is not responsible for calling these allocation + * APIs directly. + * + * ============================================================================ + */ + +#ifndef ti_drivers_timer_TimerCC32XX__include +#define ti_drivers_timer_TimerCC32XX__include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include +#include +#include +#include + +/*! + * @def TimerCC32XX_SubTimer + * + * @brief Sub-timers on the CC32XX + * + * The timer peripheral supports full width and half width timer operation. + * Use the definitions in this enumerated type to specify a full width timer + * (32-bit) or half width timer (16-bit) in the hardware attributes. There are + * two half width timers per single timer peripheral. A 16-bit timer on this + * device has an 8-bit prescaler. + */ +typedef enum TimerCC32XX_SubTimer_ { + TimerCC32XX_timer16A = 0x0001, /*!< Half width timer A */ + TimerCC32XX_timer16B = 0x0002, /*!< Half width timer B */ + TimerCC32XX_timer32 = 0x0003, /*!< Full width timer */ +} TimerCC32XX_SubTimer; + +extern const Timer_FxnTable TimerCC32XX_fxnTable; + +/*! + * @brief TimerCC32XX Hardware Attributes + * + * Timer hardware attributes that tell the TimerCC32XX driver specific hardware + * configurations and interrupt/priority settings. + * + * A sample structure is shown below: + * @code + * const TimerCC32XX_HWAttrs timerCC32XXHWAttrs[] = + * { + * { + * .baseAddress = TIMERA0_BASE, + * .subTimer = TimerCC32XX_timer32, + * .intNum = INT_TIMERA0A, + * .intPriority = ~0 + * }, + * { + * .baseAddress = TIMERA1_BASE, + * .subTimer = TimerCC32XX_timer16A, + * .intNum = INT_TIMERA1A, + * .intPriority = ~0 + * }, + * { + * .baseAddress = TIMERA1_BASE, + * .subTimer = TimerCC32XX_timer16B, + * .intNum = INT_TIMERA1B, + * .intPriority = ~0 + * } + * }; + * @endcode + */ +typedef struct TimerCC32XX_HWAttrs_ { + /*! The base address of the timer peripheral. */ + uint32_t baseAddress; + + /*! Specifies a full width timer or half-width timer. */ + TimerCC32XX_SubTimer subTimer; + + /*! The hardware interrupt number for the timer peripheral. */ + uint32_t intNum; + + /*! The interrupt priority. */ + uint32_t intPriority; +} TimerCC32XX_HWAttrs; + +/*! + * @brief TimerCC32XX_Object + * + * The application must not access any member variables of this structure! + */ +typedef struct TimerCC32XX_Object_ { + HwiP_Handle hwiHandle; + Power_NotifyObj notifyObj; + SemaphoreP_Handle timerSem; + Timer_CallBackFxn callBack; + Timer_Mode mode; + uint32_t timer; + uint32_t period; + uint32_t prescaler; + bool isRunning; +} TimerCC32XX_Object; + +/*! + * @brief Function to allocate a timer peripheral. + * + * This function is intended to be used by any driver which implements a + * timer hardware peripheral. Calling this function will enable power to the + * timer peripheral specified by the parameter, baseAddress. + * + * @param baseAddress The base address of a timer hardware peripheral. + * + * @param subTimer The TimerCC32XX_subTimer to be allocated. + * + * @return A bool returning true if the timer resource was successfully + * allocated. If the base address is not valid or if the resource is + * not available, false is returned. + * + * @sa TimerCC32XX_freeTimerResource() + */ +extern bool TimerCC32XX_allocateTimerResource(uint32_t baseAddress, + TimerCC32XX_SubTimer subTimer); + +/*! + * @brief Function to de-allocate a timer peripheral. + * + * This function is intended to be used by any driver which implements a + * timer hardware peripheral. Calling this function will disable power to the + * timer peripheral specified by the parameter, baseAddress, if and only if + * the timer peripheral is no longer in use. + * + * @pre A successful call to TimerCC32XX_allocateTimerResource() using the + * baseAddress and subTimer must have been made prior to calling this + * API. + * + * @param baseAddress The base address of a timer hardware peripheral. + * + * @param subTimer The TimerCC32XX_subTimer to be freed. + * + * @sa TimerCC32XX_allocateTimerResource() + */ +extern void TimerCC32XX_freeTimerResource(uint32_t baseAddress, + TimerCC32XX_SubTimer subTimer); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_timer_TimerCC32XX__include */ From c36980c3703d94dc927a096e71a586d1cad97aae Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Wed, 31 Jul 2019 11:51:20 -0500 Subject: [PATCH 5/6] Fix a build break with ARM compiler --- .../TARGET_CC3220SF/device/system_CC3220SF.c | 9 +++++++++ .../TARGET_CC3220SF/device/system_CC3220SF.h | 1 + .../TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c | 12 ++---------- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c index 8adc062c89d..4c2482c0516 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.c @@ -62,3 +62,12 @@ void SystemInit (void) SCB->VTOR = (uint32_t) &__Vectors; CC3220SF_LAUNCHXL_initGeneral(); } + +/* + * ======== ClockP_getCpuFreq ======== + */ +void ClockP_getCpuFreq(ClockP_FreqHz *freq) +{ + freq->lo = (uint32_t)SystemCoreClock; + freq->hi = 0; +} diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h index 95ee0672a27..fb686bb02d5 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/system_CC3220SF.h @@ -32,6 +32,7 @@ extern "C" { #include #include "ti/drivers/net/wifi/wlan.h" +#include "ti/drivers/dpl/ClockP.h" extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c index d70037d5014..df8fcced168 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/drivers/pwm/PWMTimerCC32XX.c @@ -152,8 +152,6 @@ static const uint32_t gpioPinIndexes[8] = { #define PinConfigPinMode(config) (((config) >> 8) & 0xF) #define PinConfigPin(config) (((config) >> 0) & 0x3F) -extern uint32_t SystemCoreClock; - /* * ======== getDutyCounts ======== */ @@ -163,10 +161,7 @@ static uint32_t getDutyCounts(PWM_Duty_Units dutyUnits, uint32_t dutyValue, uint32_t duty = 0; ClockP_FreqHz freq; - freq.hi = 0; - freq.lo = SystemCoreClock; - - //ClockP_getCpuFreq(&freq); + ClockP_getCpuFreq(&freq); switch (dutyUnits) { case PWM_DUTY_COUNTS: @@ -199,10 +194,7 @@ static uint32_t getPeriodCounts(PWM_Period_Units periodUnits, uint32_t period = 0; ClockP_FreqHz freq; - freq.hi = 0; - freq.lo = SystemCoreClock; - - //ClockP_getCpuFreq(&freq); + ClockP_getCpuFreq(&freq); switch (periodUnits) { case PWM_PERIOD_COUNTS: From cae7427717c5b51a9b73b636fcbcbf96645ce959 Mon Sep 17 00:00:00 2001 From: Lin Gao Date: Wed, 14 Aug 2019 11:09:11 -0500 Subject: [PATCH 6/6] Cosmetic changes to incorporate review feedback --- .../TARGET_CC3220SF/analogin_api.c | 46 ++++++---- .../TARGET_CC32XX/TARGET_CC3220SF/flash_api.c | 13 ++- .../TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c | 27 +++--- .../TARGET_CC3220SF/gpio_irq_api.c | 89 ++++++++++--------- .../TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c | 13 ++- .../TARGET_CC32XX/TARGET_CC3220SF/objects.h | 6 +- .../TARGET_CC32XX/TARGET_CC3220SF/pinmap.c | 44 ++++++--- .../TARGET_CC32XX/TARGET_CC3220SF/port_api.c | 62 ++++++++----- .../TARGET_CC3220SF/pwmout_api.c | 56 ++++++------ .../TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c | 23 ++--- .../TARGET_CC32XX/TARGET_CC3220SF/spi_api.c | 89 +++++++------------ .../TARGET_CC32XX/TARGET_CC3220SF/trng_api.c | 30 +++---- .../TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c | 18 ++-- 13 files changed, 268 insertions(+), 248 deletions(-) diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c index b754440c4f1..7c636f9d310 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/analogin_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,38 +19,50 @@ #include "PeripheralPins.h" #include "PinNames.h" #include "cmsis.h" - -#include -#include -#include -#include -#include + +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/driverlib/adc.h" +#include "ti/devices/cc32xx/driverlib/prcm.h" +#include "ti/devices/cc32xx/driverlib/pin.h" +#include "ti/devices/cc32xx/inc/hw_memmap.h" #define ADC_DATA_MASK 0x3FFC //the data is from bit [13:2] #define ADC_RESOLUTION 0xFFF -void analogin_init(analogin_t *obj, PinName pin) { +void analogin_init(analogin_t *obj, PinName pin) +{ ADCEnable(CC3220SF_ADC_BASE); obj->pin = pin; pin_mode(pin, Analog); - switch(pin){ - case PIN_57:obj->adc_ch = ADC_CH_0;break; - case PIN_58:obj->adc_ch = ADC_CH_1;break; - case PIN_59:obj->adc_ch = ADC_CH_2;break; - case PIN_60:obj->adc_ch = ADC_CH_3;break; - default: MBED_ASSERT(NC != (PinName)NC); + switch (pin) { + case PIN_57: + obj->adc_ch = ADC_CH_0; + break; + case PIN_58: + obj->adc_ch = ADC_CH_1; + break; + case PIN_59: + obj->adc_ch = ADC_CH_2; + break; + case PIN_60: + obj->adc_ch = ADC_CH_3; + break; + default: + MBED_ASSERT(NC != (PinName)NC); } ADCChannelEnable(CC3220SF_ADC_BASE, obj->adc_ch); } -uint16_t analogin_read_u16(analogin_t *obj) { +uint16_t analogin_read_u16(analogin_t *obj) +{ unsigned long adc_raw = ADCFIFORead(CC3220SF_ADC_BASE, obj->adc_ch); - return (uint16_t) ((adc_raw & ADC_DATA_MASK) >> 2); + return (uint16_t)((adc_raw & ADC_DATA_MASK) >> 2); } -float analogin_read(analogin_t *obj) { +float analogin_read(analogin_t *obj) +{ uint16_t value = analogin_read_u16(obj); return (float)value * (1.0f / (float)ADC_RESOLUTION); } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c index 6ec865d6f81..ccdd4f81476 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,7 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #if DEVICE_FLASH #include "stdbool.h" @@ -45,17 +45,14 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) { return FlashProgram((unsigned long *)data, (unsigned long)address, - (unsigned long)size); + (unsigned long)size); } uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { - if ((address >= CC3200_FLASH_START_ADDRESS) && address < (CC3200_FLASH_START_ADDRESS + CC3200_FLASH_SIZE)) - { + if ((address >= CC3200_FLASH_START_ADDRESS) && address < (CC3200_FLASH_START_ADDRESS + CC3200_FLASH_SIZE)) { return CC3200_FLASH_SECTOR_SIZE; - } - else - { + } else { return MBED_FLASH_INVALID_SIZE; } } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c index e90551e7609..dbb449eb194 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,17 +18,17 @@ #include "pinmap.h" #include "PeripheralPins.h" -#include -#include -#include -#include -#include +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/driverlib/pin.h" +#include "ti/devices/cc32xx/driverlib/gpio.h" +#include "ti/devices/cc32xx/inc/hw_ints.h" +#include "ti/devices/cc32xx/driverlib/prcm.h" uint32_t gpio_set(PinName pin) { pin_function(pin, 0); - return (1); + return (1); } // function to initialise the gpio pin @@ -37,17 +37,17 @@ uint32_t gpio_set(PinName pin) void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; - if (pin == (PinName)NC) + if (pin == (PinName)NC) { return; + } unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO); obj->baseAddr = gpio_base; - obj->pin_mask = 1<<(pinmap_find_function(pin, PinMap_GPIO)%8); + obj->pin_mask = 1 << (pinmap_find_function(pin, PinMap_GPIO) % 8); // determine PRCM GPIO CLOCK index unsigned short prcm_peripheral = 0; - switch (gpio_base) - { + switch (gpio_base) { case CC3220SF_GPIOA0_BASE: prcm_peripheral = PRCM_GPIOA0; break; @@ -68,7 +68,7 @@ void gpio_init(gpio_t *obj, PinName pin) PRCMPeripheralClkEnable(prcm_peripheral, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); // wait for GPIO clock to settle - while(!PRCMPeripheralStatusGet(prcm_peripheral)); + while (!PRCMPeripheralStatusGet(prcm_peripheral)); } void gpio_mode(gpio_t *obj, PinMode mode) @@ -77,7 +77,6 @@ void gpio_mode(gpio_t *obj, PinMode mode) //set the pin mux to be GPIO which is PIN MODE 0 pin_mode(obj->pin, mode); PinModeSet(obj->pin, PIN_MODE_0); - } void gpio_dir(gpio_t *obj, PinDirection direction) @@ -93,7 +92,7 @@ int gpio_is_connected(const gpio_t *obj) void gpio_write(gpio_t *obj, int value) { - GPIOPinWrite(obj->baseAddr, obj->pin_mask, value*obj->pin_mask); + GPIOPinWrite(obj->baseAddr, obj->pin_mask, value * obj->pin_mask); } int gpio_read(gpio_t *obj) diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c index 0b43c989744..487450fbf81 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,23 +20,23 @@ #include "cmsis.h" #include "PeripheralPins.h" -#include -#include -#include -#include -#include -#include +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/inc/hw_gpio.h" +#include "ti/devices/cc32xx/driverlib/gpio.h" +#include "ti/devices/cc32xx/inc/hw_ints.h" +#include "ti/devices/cc32xx/inc/hw_memmap.h" +#include "ti/devices/cc32xx/inc/hw_common_reg.h" #define CHANNEL_NUM 32 static uint32_t channel_ids[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; -static void handle_interrupt_in(unsigned long gpio_port) { +static void handle_interrupt_in(unsigned long gpio_port) +{ uint32_t chan_base = 0; - switch ((unsigned long) gpio_port) - { + switch ((unsigned long) gpio_port) { case CC3220SF_GPIOA0_BASE: chan_base = 0; break; @@ -55,31 +55,32 @@ static void handle_interrupt_in(unsigned long gpio_port) { } uint16_t pin_mask = 0x01; - for(int i = 0; i < 8; i++){ + for (int i = 0; i < 8; i++) { //checking for interrupt on each GPIO pin - if((GPIOIntStatus((unsigned long)gpio_port, true) & pin_mask) > 0){ + if ((GPIOIntStatus((unsigned long)gpio_port, true) & pin_mask) > 0) { gpio_irq_event event = (gpio_irq_event)GPIOIntTypeGet((unsigned long)gpio_port, pin_mask); - if(event == GPIO_RISING_EDGE){ + if (event == GPIO_RISING_EDGE) { event = IRQ_RISE; - } - else if(event == GPIO_FALLING_EDGE){ + } else if (event == GPIO_FALLING_EDGE) { event = IRQ_FALL; } - if(channel_ids[chan_base+i] == 0) + if (channel_ids[chan_base + i] == 0) { continue; + } - irq_handler(channel_ids[chan_base+i], (gpio_irq_event)event); + irq_handler(channel_ids[chan_base + i], (gpio_irq_event)event); } GPIOIntClear((unsigned long)gpio_port, pin_mask); - pin_mask = pin_mask<<1; - } + pin_mask = pin_mask << 1; + } } -void gpio_irqA0(void) { +void gpio_irqA0(void) +{ handle_interrupt_in(CC3220SF_GPIOA0_BASE); } @@ -98,21 +99,23 @@ void gpio_irqA3(void) handle_interrupt_in(CC3220SF_GPIOA3_BASE); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) return -1; +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + if (pin == NC) { + return -1; + } + - unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO); unsigned long ch_num = pinmap_find_function(pin, PinMap_GPIO); obj->baseAddr = gpio_base; obj->pin = pin; obj->ch = ch_num; - obj->pin_mask = 1<<(ch_num%8); + obj->pin_mask = 1 << (ch_num % 8); irq_handler = handler; uint32_t vector = (uint32_t)gpio_irqA0; - switch (gpio_base) - { + switch (gpio_base) { case CC3220SF_GPIOA0_BASE: vector = (uint32_t)gpio_irqA0; obj->irq_offset = INT_GPIOA0_IRQn; @@ -137,37 +140,43 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 NVIC_DisableIRQ((IRQn_Type)obj->irq_offset); NVIC_SetVector((IRQn_Type)obj->irq_offset, vector); NVIC_EnableIRQ((IRQn_Type)obj->irq_offset); - + return 0; } -void gpio_irq_free(gpio_irq_t *obj) { +void gpio_irq_free(gpio_irq_t *obj) +{ channel_ids[obj->ch] = 0; GPIOIntDisable(obj->baseAddr, obj->pin_mask); } -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ - if(enable){ + if (enable) { GPIOIntEnable(obj->baseAddr, obj->pin_mask); - } - else{ + } else { GPIOIntDisable(obj->baseAddr, obj->pin_mask); } - switch(event){ - case IRQ_RISE:GPIOIntTypeSet(obj->baseAddr,obj->pin_mask, GPIO_RISING_EDGE); break; - case IRQ_FALL: GPIOIntTypeSet(obj->baseAddr,obj->pin_mask, GPIO_FALLING_EDGE); break; - default: break; + switch (event) { + case IRQ_RISE: + GPIOIntTypeSet(obj->baseAddr, obj->pin_mask, GPIO_RISING_EDGE); + break; + case IRQ_FALL: + GPIOIntTypeSet(obj->baseAddr, obj->pin_mask, GPIO_FALLING_EDGE); + break; + default: + break; } - - } -void gpio_irq_enable(gpio_irq_t *obj) { +void gpio_irq_enable(gpio_irq_t *obj) +{ GPIOIntEnable(obj->baseAddr, obj->pin_mask); } -void gpio_irq_disable(gpio_irq_t *obj) { +void gpio_irq_disable(gpio_irq_t *obj) +{ GPIOIntDisable(obj->baseAddr, obj->pin_mask); } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c index 5b3cd6bc484..26469d955ff 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/lp_ticker.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -35,11 +35,11 @@ static bool rtc_inited = false; -const ticker_info_t* lp_ticker_get_info() +const ticker_info_t *lp_ticker_get_info() { static const ticker_info_t info = { - RTC_FREQ, // 32KHz - RTC_BITS // 32 bit counter + RTC_FREQ, // 32KHz + RTC_BITS // 32 bit counter }; return &info; } @@ -47,7 +47,7 @@ const ticker_info_t* lp_ticker_get_info() void lp_ticker_init() { if (PRCMRTCInUseGet() == true) - // When RTC is in use, slow clock counter can't be accessed + // When RTC is in use, slow clock counter can't be accessed { return; } @@ -103,8 +103,7 @@ timestamp_t lp_ticker_read() { // Read forever until reaching two of the same volatile unsigned long long read_previous, read_current; - do - { + do { read_previous = PRCMSlowClkCtrFastGet(); read_current = PRCMSlowClkCtrFastGet(); } while (read_previous != read_current); diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h index 821bc030176..83d5766f865 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -54,7 +54,7 @@ struct port_s { struct pwmout_s { uint32_t period_us; float duty_percent; - void * handle; + void *handle; PWMName pwm; }; @@ -71,7 +71,7 @@ struct serial_s { UART_PAR parityType; /* Parity bit type for UART */ }; -struct analogin_s{ +struct analogin_s { PinName pin; unsigned long adc_ch; }; diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c index fd00109b57b..6c584fc90b4 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pinmap.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -17,10 +17,10 @@ #include "pinmap.h" #include "mbed_error.h" -#include -#include -#include -#include +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/inc/hw_memmap.h" +#include "ti/devices/cc32xx/inc/hw_ocp_shared.h" +#include "ti/devices/cc32xx/driverlib/pin.h" /** * Configure pin (mode, speed, output type and pull-up/pull-down) @@ -36,14 +36,30 @@ void pin_function(PinName pin, int function) void pin_mode(PinName pin, PinMode mode) { MBED_ASSERT(pin != (PinName)NC); - switch(mode) { - case PullNone: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); break; - case PullUp: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PU); break; - case PullDown: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PD); break; - case OpenDrain: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD); break; - case OpenDrainPullUp: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PU); break; - case OpenDrainPullDown: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PD); break; - case Analog: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_ANALOG); break; - default: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); break; + switch (mode) { + case PullNone: + PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); + break; + case PullUp: + PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PU); + break; + case PullDown: + PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PD); + break; + case OpenDrain: + PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD); + break; + case OpenDrainPullUp: + PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PU); + break; + case OpenDrainPullDown: + PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PD); + break; + case Analog: + PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_ANALOG); + break; + default: + PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); + break; } } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c index e29f98dbe56..64d1cca8883 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/port_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,11 +18,11 @@ #include "gpio_api.h" #include "PeripheralPins.h" -#include -#include -#include -#include -#include +#include "ti/devices/cc32xx/inc/hw_types.h" +#include "ti/devices/cc32xx/driverlib/pin.h" +#include "ti/devices/cc32xx/driverlib/gpio.h" +#include "ti/devices/cc32xx/inc/hw_ints.h" +#include "ti/devices/cc32xx/driverlib/prcm.h" #define NUM_PORTS 4 #define NUM_PINS_PER_PORT 8 @@ -51,27 +51,41 @@ const uint16_t PortPinTypes[] = { (uint16_t)PIN_TYPE_ANALOG // Revisit this, PIN_TYPE_ANALOG gets truncated to 16b }; -PinName port_pin(PortName port, int pin_n) { +PinName port_pin(PortName port, int pin_n) +{ int gpio_num = (port * 8) + pin_n; PinName pin = (PinName)pinTable[gpio_num]; return pin; } -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ obj->port = port; obj->mask = mask; - switch(port) { - case Port0: obj->baseAddr = CC3220SF_GPIOA0_BASE; obj->peripheralId = PRCM_GPIOA0; break; - case Port1: obj->baseAddr = CC3220SF_GPIOA1_BASE; obj->peripheralId = PRCM_GPIOA1; break; - case Port2: obj->baseAddr = CC3220SF_GPIOA2_BASE; obj->peripheralId = PRCM_GPIOA2; break; - case Port3: obj->baseAddr = CC3220SF_GPIOA3_BASE; obj->peripheralId = PRCM_GPIOA3; break; + switch (port) { + case Port0: + obj->baseAddr = CC3220SF_GPIOA0_BASE; + obj->peripheralId = PRCM_GPIOA0; + break; + case Port1: + obj->baseAddr = CC3220SF_GPIOA1_BASE; + obj->peripheralId = PRCM_GPIOA1; + break; + case Port2: + obj->baseAddr = CC3220SF_GPIOA2_BASE; + obj->peripheralId = PRCM_GPIOA2; + break; + case Port3: + obj->baseAddr = CC3220SF_GPIOA3_BASE; + obj->peripheralId = PRCM_GPIOA3; + break; } // initialize GPIO PORT clock PRCMPeripheralClkEnable(obj->peripheralId, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); // wait for GPIO clock to settle - while(!PRCMPeripheralStatusGet(obj->peripheralId)); + while (!PRCMPeripheralStatusGet(obj->peripheralId)); for (int i = 0; i < 8; i++) { if (obj->mask & (1 << i)) { @@ -84,7 +98,8 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { port_dir(obj, dir); } -void port_mode(port_t *obj, PinMode mode) { +void port_mode(port_t *obj, PinMode mode) +{ for (int i = 0; i < 8; i++) { if (obj->mask & (1 << i)) { pin_mode(port_pin(obj->port, i), mode); @@ -92,17 +107,24 @@ void port_mode(port_t *obj, PinMode mode) { } } -void port_dir(port_t *obj, PinDirection dir) { +void port_dir(port_t *obj, PinDirection dir) +{ switch (dir) { - case PIN_INPUT: GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_IN); break; - case PIN_OUTPUT: GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_OUT); break; + case PIN_INPUT: + GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_IN); + break; + case PIN_OUTPUT: + GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_OUT); + break; } } -void port_write(port_t *obj, int value) { +void port_write(port_t *obj, int value) +{ GPIOPinWrite(obj->baseAddr, obj->mask, value); } -int port_read(port_t *obj) { +int port_read(port_t *obj) +{ return (int)(GPIOPinRead(obj->baseAddr, obj->mask)); } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c index 348bd2fc0f4..01eeef57df5 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/pwmout_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,13 +18,14 @@ #include "pinmap.h" #include "PeripheralPins.h" -#include -#include -#include +#include "ti/drivers/pwm/PWMTimerCC32XX.h" +#include "ti/drivers/PWM.h" +#include "CC3220SF_LAUNCHXL.h" extern const PWM_Config PWM_config[]; -void pwmout_init(pwmout_t* obj, PinName pin) { +void pwmout_init(pwmout_t *obj, PinName pin) +{ PWM_Params pwmParams; int pwmIndex = CC3220SF_LAUNCHXL_PWMCOUNT; @@ -35,7 +36,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) { obj->pwm = pwm; - switch(pin) { + switch (pin) { case PIN_01: pwmIndex = CC3220SF_LAUNCHXL_PWM6; break; @@ -61,7 +62,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) { break; default: - while(1); + while (1); } obj->handle = (void *)&PWM_config[pwmIndex]; @@ -72,55 +73,60 @@ void pwmout_init(pwmout_t* obj, PinName pin) { obj->duty_percent = PWM_DEFAULT_DUTY_PERCENT; obj->period_us = PWM_DEFAULT_PERIOD_US; - if (PWM_open(pwmIndex, &pwmParams)) - { + if (PWM_open(pwmIndex, &pwmParams)) { PWM_start((PWM_Handle)obj->handle); - } - else - { - while(1); + } else { + while (1); } } -void pwmout_free(pwmout_t* obj) { +void pwmout_free(pwmout_t *obj) +{ PWM_stop((PWM_Handle)obj->handle); PWM_close((PWM_Handle)obj->handle); } -void pwmout_write(pwmout_t* obj, float value) { - PWM_setDuty((PWM_Handle)obj->handle, value*100); +void pwmout_write(pwmout_t *obj, float value) +{ + PWM_setDuty((PWM_Handle)obj->handle, value * 100); obj->duty_percent = value; } -float pwmout_read(pwmout_t* obj) { +float pwmout_read(pwmout_t *obj) +{ return (obj->duty_percent); } -void pwmout_period(pwmout_t* obj, float seconds) { +void pwmout_period(pwmout_t *obj, float seconds) +{ pwmout_period_us(obj, seconds * 1000 * 1000); } -void pwmout_period_ms(pwmout_t* obj, int ms) { +void pwmout_period_ms(pwmout_t *obj, int ms) +{ pwmout_period_us(obj, ms * 1000); } // Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t* obj, int us) { +void pwmout_period_us(pwmout_t *obj, int us) +{ PWM_setPeriod((PWM_Handle)obj->handle, us); obj->period_us = us; } -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ pwmout_pulsewidth_us(obj, seconds * 1000000.0f); } -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ pwmout_pulsewidth_us(obj, ms * 1000); } -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - if (obj->period_us) - { +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + if (obj->period_us) { float value = (float)us / (float)obj->period_us; pwmout_write(obj, value); } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c index ed488ae419f..81d4ad8207f 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/rtc_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,33 +20,36 @@ #include "ti/devices/cc32xx/inc/hw_types.h" #include "ti/devices/cc32xx/driverlib/prcm.h" -void rtc_init(void) { +void rtc_init(void) +{ static bool rtc_initialized = false; - if (!rtc_initialized) - { - if (!PRCMRTCInUseGet()) - { + if (!rtc_initialized) { + if (!PRCMRTCInUseGet()) { PRCMRTCInUseSet(); } rtc_initialized = true; } } -void rtc_free(void) { +void rtc_free(void) +{ } -int rtc_isenabled(void) { +int rtc_isenabled(void) +{ return PRCMRTCInUseGet(); } -time_t rtc_read(void) { +time_t rtc_read(void) +{ unsigned long ulSecs = 0; unsigned short usMsec = 0; PRCMRTCGet(&ulSecs, &usMsec); return ulSecs; } -void rtc_write(time_t t) { +void rtc_write(time_t t) +{ PRCMRTCSet(t, 0); } #endif diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c index cdfc8ac9228..11e3f5527f5 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/spi_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -46,8 +46,7 @@ static void spi_configure_driver_instance(spi_t *obj) struct spi_s *spi_inst = obj; #endif - if (spi_inst->clock_update) - { + if (spi_inst->clock_update) { SPIReset(spi_inst->baseAddr); SPIConfigSetExpClk(spi_inst->baseAddr, spi_inst->clock_config.ulSPIClk, spi_inst->clock_config.ulBitRate, spi_inst->clock_config.ulMode, @@ -100,12 +99,9 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel spi_inst->clock_config.ulConfig = SPI_4PIN_MODE; spi_inst->clock_config.ulConfig |= SPI_HW_CTRL_CS; spi_inst->clock_config.ulConfig |= SPI_CS_ACTIVELOW; - if (ssel == NC) - { + if (ssel == NC) { spi_inst->cs_control_gpio = true; - } - else - { + } else { spi_inst->cs_control_gpio = false; } spi_inst->clock_config.ulConfig |= SPI_TURBO_OFF; @@ -120,8 +116,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel MAP_PinTypeSPI((unsigned long) mosi & 0xff, (unsigned long) PIN_MODE_SPI); MAP_PinTypeSPI((unsigned long) miso & 0xff, (unsigned long) PIN_MODE_SPI); MAP_PinTypeSPI((unsigned long) sclk & 0xff, (unsigned long) PIN_MODE_SPI); - if (ssel != NC) - { + if (ssel != NC) { MAP_PinTypeSPI((unsigned long) ssel & 0xff, (unsigned long) PIN_MODE_SPI); } spi_inst->clock_update = true; @@ -163,8 +158,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) #else struct spi_s *spi_inst = obj; #endif - if ((uint32_t)bits != spi_inst->word_length) - { + if ((uint32_t)bits != spi_inst->word_length) { spi_inst->word_length = bits; spi_inst->clock_update = true; } @@ -180,30 +174,26 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) /* Convert Mbed HAL mode to TI mode. */ - if(mode == 0) { - if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_0) - { + if (mode == 0) { + if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_0) { spi_inst->clock_update = true; } spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_0; - } else if(mode == 1) { - if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_1) - { + } else if (mode == 1) { + if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_1) { spi_inst->clock_update = true; } spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_1; - } else if(mode == 2) { - if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_2) - { + } else if (mode == 2) { + if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_2) { spi_inst->clock_update = true; } spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_2; - } else if(mode == 3) { - if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_3) - { + } else if (mode == 3) { + if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_3) { spi_inst->clock_update = true; } - spi_inst->clock_config.ulSubMode= SPI_SUB_MODE_3; + spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_3; } spi_configure_driver_instance(spi_inst); } @@ -224,8 +214,7 @@ void spi_frequency(spi_t *obj, int hz) #endif spi_inst->clock_config.ulSPIClk = PRCMPeripheralClockGet(PRCM_GSPI); - if (spi_inst->clock_config.ulBitRate != (uint32_t)hz) - { + if (spi_inst->clock_config.ulBitRate != (uint32_t)hz) { spi_inst->clock_update = true; spi_inst->clock_config.ulBitRate = hz; } @@ -251,15 +240,13 @@ int spi_master_write(spi_t *obj, int value) /* Configure peripheral if necessary. */ spi_configure_driver_instance(obj); - if (!spi_inst->cs_control_gpio) - { + if (!spi_inst->cs_control_gpio) { SPICSEnable(spi_inst->baseAddr); } /* Transfer a data word. */ SPIDataPut(spi_inst->baseAddr, value); SPIDataGet(spi_inst->baseAddr, (unsigned long *)&data_read); - if (!spi_inst->cs_control_gpio) - { + if (!spi_inst->cs_control_gpio) { SPICSDisable(spi_inst->baseAddr); } return data_read & ((1 << spi_inst->word_length) - 1); @@ -294,18 +281,12 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha /* Configure peripheral if necessary. */ spi_configure_driver_instance(obj); - if (tx_length >= rx_length) - { - if (spi_inst->word_length == 16) - { + if (tx_length >= rx_length) { + if (spi_inst->word_length == 16) { spi_words = (tx_length >> 1); - } - else if (spi_inst->word_length == 32) - { + } else if (spi_inst->word_length == 32) { spi_words = (tx_length >> 2); - } - else if (spi_inst->word_length == 8) - { + } else if (spi_inst->word_length == 8) { spi_words = tx_length; } @@ -314,40 +295,30 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha (unsigned char *)rx_temp, (unsigned long) spi_words, SPI_CS_ENABLE | SPI_CS_DISABLE); // Copy the desired data from temp_rx - for (i = 0; i < rx_length; i ++) - { + for (i = 0; i < rx_length; i ++) { rx_buffer[i] = rx_temp[i]; } free(rx_temp); return (tx_length); - } - else // tx_length < rx_length + } else // tx_length < rx_length // Copy the data from tx_buffer to a temp buffer and fill the the rest of the tx_buffer with write_fill) { - if (spi_inst->word_length == 16) - { + if (spi_inst->word_length == 16) { spi_words = (rx_length >> 1); - } - else if (spi_inst->word_length == 32) - { + } else if (spi_inst->word_length == 32) { spi_words = (rx_length >> 2); - } - else if (spi_inst->word_length == 8) - { + } else if (spi_inst->word_length == 8) { spi_words = rx_length; } unsigned char *tx_temp = malloc(rx_length); - for (i = 0; i < tx_length; i ++) - { + for (i = 0; i < tx_length; i ++) { tx_temp[i] = tx_buffer[i]; } - for (i = tx_length; i < rx_length; i ++) - { + for (i = tx_length; i < rx_length; i ++) { tx_temp[i] = write_fill; } - if (!spi_inst->cs_control_gpio) - { + if (!spi_inst->cs_control_gpio) { cs_flags = SPI_CS_ENABLE | SPI_CS_DISABLE; } SPITransfer(spi_inst->baseAddr, (unsigned char *)tx_temp, diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c index 104a525f19f..f8456db5400 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/trng_api.c @@ -1,7 +1,7 @@ /* * Hardware entropy collector for the CC3200 * - * Copyright (C) 2018, ARM Limited, All Rights Reserved + * Copyright (C) 2018-2019, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -34,15 +34,11 @@ void trng_init(trng_t *obj) static bool trng_initialized = false; (void)obj; - if (!trng_initialized) - { + if (!trng_initialized) { int ret = CC3220SF_initSimplelink(); - if (ret == 0) - { + if (ret == 0) { trng_initialized = true; - } - else - { + } else { printf("trng_init failed with %d\n", ret); } } @@ -62,22 +58,16 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l (void)obj; /* Retrieve a buffer of true random numbers from the networking subsystem. Maximum buffer length is 172 bytes for each retrieval. if the requested length exceeds 172 bytes, it is trimmed to 172 bytes.*/ - if (length > 172) - { + if (length > 172) { bytes_count = 172; } - if (output) - { - status = sl_NetUtilGet(SL_NETUTIL_TRUE_RANDOM,0,output,&bytes_count); - if (output_length) - { - if (status == 0) - { + if (output) { + status = sl_NetUtilGet(SL_NETUTIL_TRUE_RANDOM, 0, output, &bytes_count); + if (output_length) { + if (status == 0) { *output_length = bytes_count; return 0; - } - else - { + } else { printf("sl_NetUtilGet failed with %d\n", status); *output_length = 0; } diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c index 4aeb613faf2..a2603e8ee24 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/us_ticker.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited + * Copyright (c) 2018-2019 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -28,7 +28,7 @@ bool us_ticker_initialized = false; -const ticker_info_t* us_ticker_get_info() +const ticker_info_t *us_ticker_get_info() { static const ticker_info_t info = { US_TICKER_FREQ, @@ -38,21 +38,18 @@ const ticker_info_t* us_ticker_get_info() } void us_ticker_init(void) { - if (!us_ticker_initialized) - { + if (!us_ticker_initialized) { TimerDisable(TIMERA0_BASE, TIMER_A); TimerConfigure(TIMERA0_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC); TimerIntClear(TIMERA0_BASE, TIMER_TIMA_DMA | TIMER_TIMA_MATCH | TIMER_CAPA_EVENT | - TIMER_CAPA_MATCH | TIMER_TIMA_TIMEOUT); - TimerPrescaleSet(TIMERA0_BASE, TIMER_A, (80-1)); + TIMER_CAPA_MATCH | TIMER_TIMA_TIMEOUT); + TimerPrescaleSet(TIMERA0_BASE, TIMER_A, (80 - 1)); TimerEnable(TIMERA0_BASE, TIMER_A); NVIC_ClearPendingIRQ(INT_TIMERA0A_IRQn); NVIC_SetVector(INT_TIMERA0A_IRQn, (uint32_t)us_ticker_irq_handler); NVIC_EnableIRQ(INT_TIMERA0A_IRQn); us_ticker_initialized = true; - } - else - { + } else { // Disable match interrupt. This is mbed OS requirement. TimerIntDisable(TIMERA0_BASE, TIMER_TIMA_MATCH); // Clear pending interrupt @@ -90,8 +87,7 @@ void us_ticker_fire_interrupt(void) void us_ticker_free(void) { - if (us_ticker_initialized) - { + if (us_ticker_initialized) { TimerDisable(TIMERA0_BASE, TIMER_A); NVIC_DisableIRQ(INT_TIMERA0A_IRQn); us_ticker_initialized = false;