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Relax us ticker frequency requirement + test update #11157
This change is required by the Samsung S111(S5JS100). On this board timer clock used for us ticker operates at 26MHz.
This change relaxes top limit to 100 MHz, but only for 32-bit timers.
Ticker common layer schedules one interrupt per timer rollover to trace elapsed time. We need to ensure that this operation is not performed too frequently. I.e. in case of 16-bit timer at 32 MHz, the timer rollover will happen after ~2 ms. This may cause that there will be no time for other tasks. That is why we increase the top limit, but only for 32-bit timers.
Pull request type
kjbracey-arm left a comment
Recent optimisations in #10609 were relying on the current limits.
But as long as this limit is only lifted for wide timers, I believe it doesn't break that. Maybe you could double-check - see
(I can imagine this being relaxed a bit more in future - maybe it isn't specific to 32-bit, maybe it could be a combined check of width+speed to ensure wrap time is greater than 8ms.)
@kjbracey-arm Thanks for the review.
Previously the worst case was for 16 bit counter @ 8 MHz. In this case, we have a rollover after ~ 8ms.