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DISCO_H747I dualcore support #11605

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merged 4 commits into from Oct 16, 2019

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@ABOSTM
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ABOSTM commented Oct 1, 2019

Description

Add 2 targets for DISCO_H747I dualcore:

  • DISCO_H747I -> for CM7 core
  • DISCO_H747I_CM4 -> for CM4 core

Current restrictions:

  • TICKLESS deactivated
  • DeepSleep not supported (DeepSleep wrapped to sleep)

Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.

Warning: Drag and drop of binary to DISCO_H747I disk will flash CM7.
In order to flash CM4, one can use STM32 CubeProgrammer tool.
Example of CubeProgrammer command line to flash CM4:
PATH="/c/Program Files/STMicroelectronics/STM32Cube/STM32CubeProgrammer/bin/":$PATH
STM32_Programmer_CLI -c port=SWD mode=UR -w BUILD/DISCO_H747I_CM4/ARM/<binary file name> 0x8100000

Tests executed:

  • On CM7 (with a blinky binary on CM4), all tests on all 3 toolchains: ARM, GCC_ARM and IAR
  • On CM4 (with a blinky binary on CM7), all tests on toolchain IAR and GCC_ARM
    With toolchain ARM: blinky on both core simultaneously

All tests are passed except:

  • tests-mbed_hal-sleep_manager
  • tests-mbed_hal-sleep

This is normal because DeepSleep is not yet supported.

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jeromecoutant commented Oct 1, 2019

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jeromecoutant left a comment

Regression tests on other targets done.

As explained in the description, CM4 support can not be executed with automatic CI,
but I saw manual tests executed and passed!

Thx @ABOSTM !

@ciarmcom ciarmcom requested review from ARMmbed/mbed-os-maintainers Oct 1, 2019
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ciarmcom commented Oct 1, 2019

@ciarmcom ciarmcom requested a review from ARMmbed/mbed-os-crypto Oct 1, 2019
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bulislaw left a comment

As far as I can tell, this is sort of a basic support only? It's up to the user to put whatever code on both cores and figure out how do they talk to each other?

@@ -103,11 +103,19 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)
if (ctx == NULL) {
return;
}
#if defined(DUAL_CORE)

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bulislaw Oct 1, 2019

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@Patater please review

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ABOSTM Oct 1, 2019

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You are right this is up to the user to put whatever on both cores, and to figure out how they could talk to each other.
The modification in this specific file aes_alt.c concerns the potential concurent access (by CM4 and CM7) to common resource (RCC registers). This is done through Hardware Semaphore.

{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO
{PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO
{PA_2_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO
// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to PMOD\#1- USART2_CTS_NSS

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bulislaw Oct 1, 2019

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Dead code.

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@jeromecoutant

jeromecoutant Oct 1, 2019

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Yes and no...
We used to keep all the lines in all targets .
As the PinMap table is weak, idea was to give the availability for customer to change easily the default choice.

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ABOSTM Oct 1, 2019

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From pin configuration point of view, PA_0 can be connected to TIM2_CH1.
Nevertheless TIM2 and TIM5 are reserved for us_ticker.
That is why thoses lines are commented out: it is nomore usable for PWM purpose.
but we keep those lines as reminder to show the capability.
It is done the same way for example on target NUCLEO_L4R5ZI_P.

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bulislaw Oct 4, 2019

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Makes sense.

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bulislaw left a comment

Would it benefit from a readme file in the target directory with description how to build and flash both images?

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jeromecoutant commented Oct 4, 2019

Would it benefit from a readme file in the target directory with description how to build and flash both images?

Good idea, I will do it asap (in a second time).
Thx

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adbridge commented Oct 7, 2019

@jeromecoutant is this still waiting for the readme update ?

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jeromecoutant commented Oct 7, 2019

No...
I will do it in a second time, please start CI

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adbridge commented Oct 7, 2019

CI started

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mbed-ci commented Oct 7, 2019

Test run: FAILED

Summary: 1 of 11 test jobs failed
Build number : 1
Build artifacts

Failed test jobs:

  • jenkins-ci/mbed-os-ci_exporter
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jeromecoutant commented Oct 8, 2019

Can you start again exporter CI ?

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mark-edgeworth left a comment

Reviewed only from a tools PoV. Looks ok.

ABOSTM added 4 commits Oct 14, 2019
Add 2 targets for DISCO_H747I dualcore:
* DISCO_H747I      -> for CM7 core
* DISCO_H747I_CM4  -> for CM4 core

Current restrictions:
* TICKLESS deactivated
* DeepSleep not supported (DeepSleep wrapped to sleep)

Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.

Warning: Drag and drop of binary to DISCO_H747I will flash CM7.
         In order to flash CM4, one can use STM32 CubeProgrammer tool.
@ABOSTM ABOSTM force-pushed the ABOSTM:DISCO_H747I_DUALCORE_SUPPORT branch from 6c728de to 6397a1d Oct 14, 2019
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ABOSTM commented Oct 14, 2019

Merge conflict solved.

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0xc0170 commented Oct 14, 2019

CI started

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mbed-ci commented Oct 15, 2019

Test run: SUCCESS

Summary: 11 of 11 test jobs passed
Build number : 2
Build artifacts

@0xc0170 0xc0170 added ready for merge and removed needs: CI labels Oct 15, 2019
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0xc0170 commented Oct 15, 2019

I'll review today and merge later.

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0xc0170 commented Oct 15, 2019

Would it benefit from a readme file in the target directory with description how to build and flash both images?

Was this added, @jeromecoutant @ABOSTM ? Github does not show me any readme file here

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0xc0170 commented Oct 15, 2019

I can't find docs for DUAL_CORE - what does it do ? When should I use one? (if I edit these changed files, how do I know where I should use this ?)

Readme might answer my questions

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jeromecoutant commented Oct 15, 2019

DUAL_CORE is set in MCU CMSIS file.

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MarceloSalazar commented Oct 16, 2019

@0xc0170 can we please merge this for 5.14.1?

@0xc0170 0xc0170 merged commit 16568da into ARMmbed:master Oct 16, 2019
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0xc0170 commented Oct 16, 2019

@0xc0170 can we please merge this for 5.14.1?

The code freeze was the previous week, I set this to 5.14.2 as the next patch release.

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