diff --git a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h index 90c61e98bfa..3caa99a65f7 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h +++ b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h @@ -82,7 +82,7 @@ #include "S25FL512S_config.h" #elif defined(TARGET_CYW9P62S1_43012EVB_01) -#include "S25FS128S_config.h" +#include "S25FS512S_config.h" #elif defined(TARGET_CY8CPROTO_064_SB) #include "S25FL128S_config.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c new file mode 100644 index 00000000000..cb430a41643 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_system(); + init_cycfg_clocks(); + init_cycfg_routing(); + init_cycfg_peripherals(); + init_cycfg_pins(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h new file mode 100644 index 00000000000..9abc7f0f4ab --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_system.h" +#include "cycfg_clocks.h" +#include "cycfg_routing.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp new file mode 100644 index 00000000000..6911b5befd4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -0,0 +1,24 @@ +/******************************************************************************* +* File Name: cycfg.timestamp +* +* Description: +* Sentinel file for determining if generated source is up to date. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c new file mode 100644 index 00000000000..2a4822d1d43 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,90 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_USB_CLK_DIV_HW, + .channel_num = CYBSP_USB_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_CSD_COMM_CLK_DIV_HW, + .channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_CSD_CLK_DIV_HW, + .channel_num = CYBSP_CSD_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_BT_UART_CLK_DIV_HW, + .channel_num = CYBSP_BT_UART_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) + + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h new file mode 100644 index 00000000000..ab4a3aeaa87 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_USB_CLK_DIV_ENABLED 1U +#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#define CYBSP_USB_CLK_DIV_NUM 0U +#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U +#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U +#define CYBSP_CSD_CLK_DIV_ENABLED 1U +#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_CSD_CLK_DIV_NUM 3U +#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U +#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_BT_UART_CLK_DIV_NUM 4U + +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h new file mode 100644 index 00000000000..90f1013f8a7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 00000000000..c4d24348d35 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) + +cy_stc_csd_context_t cy_csd_0_context = +{ + .lockKey = CY_CSD_NONE_KEY, +}; +const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_BT_UART_obj = + { + .type = CYHAL_RSC_SCB, + .block_num = 4U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, + .enableWakeFromSleep = false, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = + { + .type = CYHAL_RSC_SCB, + .block_num = 7U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_smif_config_t CYBSP_QSPI_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, + .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_obj = + { + .type = CYHAL_RSC_SMIF, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_NONE, + .c1Mode = CY_MCWDT_MODE_NONE, + .c2ToggleBit = 16U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_MCWDT0_obj = + { + .type = CYHAL_RSC_LPTIMER, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_rtc_config_t CYBSP_RTC_config = +{ + .sec = 0U, + .min = 0U, + .hour = 12U, + .amPm = CY_RTC_AM, + .hrFormat = CY_RTC_24_HOURS, + .dayOfWeek = CY_RTC_SUNDAY, + .date = 1U, + .month = CY_RTC_JANUARY, + .year = 0U, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_RTC_obj = + { + .type = CYHAL_RSC_RTC, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = +{ + .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, + .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, + .epBuffer = NULL, + .epBufferSize = 0U, + .dmaConfig[0] = NULL, + .dmaConfig[1] = NULL, + .dmaConfig[2] = NULL, + .dmaConfig[3] = NULL, + .dmaConfig[4] = NULL, + .dmaConfig[5] = NULL, + .dmaConfig[6] = NULL, + .dmaConfig[7] = NULL, + .enableLpm = false, + .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USBUART_obj = + { + .type = CYHAL_RSC_USB, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB4_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj); +#endif //defined (CY_USING_HAL) + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB7_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_RTC_obj); +#endif //defined (CY_USING_HAL) + + Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 00000000000..022dd4c62a7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,159 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_csd.h" +#include "cy_scb_uart.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cy_scb_ezi2c.h" +#include "cy_smif.h" +#include "cycfg_qspi_memslot.h" +#include "cy_mcwdt.h" +#include "cy_rtc.h" +#include "cy_usbfs_dev_drv.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_CSD_ENABLED 1U +#define CY_CAPSENSE_CORE 4u +#define CY_CAPSENSE_CPU_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 100000000u +#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define CY_CAPSENSE_PERI_DIV_INDEX 3u +#define Cmod_PORT GPIO_PRT7 +#define CintA_PORT GPIO_PRT7 +#define CintB_PORT GPIO_PRT7 +#define Button0_Rx0_PORT GPIO_PRT9 +#define Button0_Tx_PORT GPIO_PRT1 +#define Button1_Rx0_PORT GPIO_PRT7 +#define Button1_Tx_PORT GPIO_PRT1 +#define LinearSlider0_Sns0_PORT GPIO_PRT9 +#define LinearSlider0_Sns1_PORT GPIO_PRT9 +#define LinearSlider0_Sns2_PORT GPIO_PRT9 +#define LinearSlider0_Sns3_PORT GPIO_PRT9 +#define LinearSlider0_Sns4_PORT GPIO_PRT9 +#define Cmod_PIN 7u +#define CintA_PIN 1u +#define CintB_PIN 2u +#define Button0_Rx0_PIN 7u +#define Button0_Tx_PIN 5u +#define Button1_Rx0_PIN 0u +#define Button1_Tx_PIN 5u +#define LinearSlider0_Sns0_PIN 0u +#define LinearSlider0_Sns1_PIN 1u +#define LinearSlider0_Sns2_PIN 2u +#define LinearSlider0_Sns3_PIN 3u +#define LinearSlider0_Sns4_PIN 4u +#define Cmod_PORT_NUM 7u +#define CintA_PORT_NUM 7u +#define CintB_PORT_NUM 7u +#define CYBSP_CSD_HW CSD0 +#define CYBSP_CSD_IRQ csd_interrupt_IRQn +#define CYBSP_BT_UART_ENABLED 1U +#define CYBSP_BT_UART_HW SCB4 +#define CYBSP_BT_UART_IRQ scb_4_interrupt_IRQn +#define CYBSP_CSD_COMM_ENABLED 1U +#define CYBSP_CSD_COMM_HW SCB7 +#define CYBSP_CSD_COMM_IRQ scb_7_interrupt_IRQn +#define CYBSP_QSPI_ENABLED 1U +#define CYBSP_QSPI_HW SMIF0 +#define CYBSP_QSPI_IRQ smif_interrupt_IRQn +#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) +#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) +#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) +#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) +#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) +#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) +#define CYBSP_QSPI_DATALINES0_1 (1UL) +#define CYBSP_QSPI_DATALINES2_3 (1UL) +#define CYBSP_QSPI_DATALINES4_5 (0UL) +#define CYBSP_QSPI_DATALINES6_7 (0UL) +#define CYBSP_QSPI_SS0 (1UL) +#define CYBSP_QSPI_SS1 (0UL) +#define CYBSP_QSPI_SS2 (0UL) +#define CYBSP_QSPI_SS3 (0UL) +#define CYBSP_QSPI_DESELECT_DELAY 7 +#define CYBSP_MCWDT0_ENABLED 1U +#define CYBSP_MCWDT0_HW MCWDT_STRUCT0 +#define CYBSP_RTC_ENABLED 1U +#define CYBSP_RTC_10_MONTH_OFFSET (28U) +#define CYBSP_RTC_MONTH_OFFSET (24U) +#define CYBSP_RTC_10_DAY_OFFSET (20U) +#define CYBSP_RTC_DAY_OFFSET (16U) +#define CYBSP_RTC_1000_YEAR_OFFSET (12U) +#define CYBSP_RTC_100_YEAR_OFFSET (8U) +#define CYBSP_RTC_10_YEAR_OFFSET (4U) +#define CYBSP_RTC_YEAR_OFFSET (0U) +#define CYBSP_USBUART_ENABLED 1U +#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U +#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U +#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U +#define CYBSP_USBUART_HW USBFS0 +#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn +#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn +#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn + +extern cy_stc_csd_context_t cy_csd_0_context; +extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_BT_UART_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_smif_config_t CYBSP_QSPI_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_rtc_config_t CYBSP_RTC_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_RTC_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USBUART_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c new file mode 100644 index 00000000000..10cde43334e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -0,0 +1,918 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_WCO_IN_PORT_NUM, + .channel_num = CYBSP_WCO_IN_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_WCO_OUT_PORT_NUM, + .channel_num = CYBSP_WCO_OUT_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_QSPI_SS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_SS_PORT_NUM, + .channel_num = CYBSP_QSPI_SS_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_D3_PORT_NUM, + .channel_num = CYBSP_QSPI_D3_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_D2_PORT_NUM, + .channel_num = CYBSP_QSPI_D2_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_D1_PORT_NUM, + .channel_num = CYBSP_QSPI_D1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_QSPI_D0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_D0_PORT_NUM, + .channel_num = CYBSP_QSPI_D0_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_QSPI_SCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_SCK_PORT_NUM, + .channel_num = CYBSP_QSPI_SCK_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_USB_DP_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_DP_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_USB_DP_PORT_NUM, + .channel_num = CYBSP_USB_DP_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_USB_DM_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_DM_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_USB_DM_PORT_NUM, + .channel_num = CYBSP_USB_DM_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_EZI2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_EZI2C_SCL_PORT_NUM, + .channel_num = CYBSP_EZI2C_SCL_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_EZI2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_EZI2C_SDA_PORT_NUM, + .channel_num = CYBSP_EZI2C_SDA_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_BTN0_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_BTN0_PORT_NUM, + .channel_num = CYBSP_BTN0_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_LED8_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED8_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_LED8_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_LED8_PORT_NUM, + .channel_num = CYBSP_LED8_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWO_PORT_NUM, + .channel_num = CYBSP_SWO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDIO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDIO_PORT_NUM, + .channel_num = CYBSP_SWDIO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = CYBSP_SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDCK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDCK_PORT_NUM, + .channel_num = CYBSP_SWDCK_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_BTN1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_BTN1_PORT_NUM, + .channel_num = CYBSP_CSD_BTN1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CINA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CINA_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CINA_PORT_NUM, + .channel_num = CYBSP_CINA_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CINB_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CINB_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CINB_PORT_NUM, + .channel_num = CYBSP_CINB_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CMOD_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CMOD_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CMOD_PORT_NUM, + .channel_num = CYBSP_CMOD_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_BT_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_BT_UART_RX_PORT_NUM, + .channel_num = CYBSP_BT_UART_RX_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_BT_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_BT_UART_TX_PORT_NUM, + .channel_num = CYBSP_BT_UART_TX_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_BT_UART_RTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_BT_UART_RTS_PORT_NUM, + .channel_num = CYBSP_BT_UART_RTS_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_BT_UART_CTS_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_BT_UART_CTS_PORT_NUM, + .channel_num = CYBSP_BT_UART_CTS_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD0_PORT_NUM, + .channel_num = CYBSP_CSD_SLD0_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD1_PORT_NUM, + .channel_num = CYBSP_CSD_SLD1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD2_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD2_PORT_NUM, + .channel_num = CYBSP_CSD_SLD2_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD3_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD3_PORT_NUM, + .channel_num = CYBSP_CSD_SLD3_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_SLD4_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_SLD4_PORT_NUM, + .channel_num = CYBSP_CSD_SLD4_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_CSD_BTN0_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_CSD_BTN0_PORT_NUM, + .channel_num = CYBSP_CSD_BTN0_PIN, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_BTN0_PORT, CYBSP_BTN0_PIN, &CYBSP_BTN0_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_BTN0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_LED8_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CINA_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CINB_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h new file mode 100644 index 00000000000..8d22dcbb369 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -0,0 +1,916 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cycfg_routing.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_WCO_IN_ENABLED 1U +#define CYBSP_WCO_IN_PORT GPIO_PRT0 +#define CYBSP_WCO_IN_PORT_NUM 0U +#define CYBSP_WCO_IN_PIN 0U +#define CYBSP_WCO_IN_NUM 0U +#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_WCO_OUT_ENABLED 1U +#define CYBSP_WCO_OUT_PORT GPIO_PRT0 +#define CYBSP_WCO_OUT_PORT_NUM 0U +#define CYBSP_WCO_OUT_PIN 1U +#define CYBSP_WCO_OUT_NUM 1U +#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_QSPI_SS_ENABLED 1U +#define CYBSP_QSPI_SS_PORT GPIO_PRT11 +#define CYBSP_QSPI_SS_PORT_NUM 11U +#define CYBSP_QSPI_SS_PIN 2U +#define CYBSP_QSPI_SS_NUM 2U +#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_2_HSIOM + #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM +#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_QSPI_D3_ENABLED 1U +#define CYBSP_QSPI_D3_PORT GPIO_PRT11 +#define CYBSP_QSPI_D3_PORT_NUM 11U +#define CYBSP_QSPI_D3_PIN 3U +#define CYBSP_QSPI_D3_NUM 3U +#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_3_HSIOM + #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM +#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_QSPI_D2_ENABLED 1U +#define CYBSP_QSPI_D2_PORT GPIO_PRT11 +#define CYBSP_QSPI_D2_PORT_NUM 11U +#define CYBSP_QSPI_D2_PIN 4U +#define CYBSP_QSPI_D2_NUM 4U +#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_4_HSIOM + #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM +#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_QSPI_D1_ENABLED 1U +#define CYBSP_QSPI_D1_PORT GPIO_PRT11 +#define CYBSP_QSPI_D1_PORT_NUM 11U +#define CYBSP_QSPI_D1_PIN 5U +#define CYBSP_QSPI_D1_NUM 5U +#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_5_HSIOM + #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM +#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_QSPI_D0_ENABLED 1U +#define CYBSP_QSPI_D0_PORT GPIO_PRT11 +#define CYBSP_QSPI_D0_PORT_NUM 11U +#define CYBSP_QSPI_D0_PIN 6U +#define CYBSP_QSPI_D0_NUM 6U +#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG +#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_6_HSIOM + #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM +#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_QSPI_SCK_ENABLED 1U +#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 +#define CYBSP_QSPI_SCK_PORT_NUM 11U +#define CYBSP_QSPI_SCK_PIN 7U +#define CYBSP_QSPI_SCK_NUM 7U +#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_7_HSIOM + #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM +#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_USB_DP_ENABLED 1U +#define CYBSP_USB_DP_PORT GPIO_PRT14 +#define CYBSP_USB_DP_PORT_NUM 14U +#define CYBSP_USB_DP_PIN 0U +#define CYBSP_USB_DP_NUM 0U +#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DP_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_0_HSIOM + #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM +#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_USB_DM_ENABLED 1U +#define CYBSP_USB_DM_PORT GPIO_PRT14 +#define CYBSP_USB_DM_PORT_NUM 14U +#define CYBSP_USB_DM_PIN 1U +#define CYBSP_USB_DM_NUM 1U +#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DM_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_1_HSIOM + #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM +#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_EZI2C_SCL_ENABLED 1U +#define CYBSP_EZI2C_SCL_PORT GPIO_PRT1 +#define CYBSP_EZI2C_SCL_PORT_NUM 1U +#define CYBSP_EZI2C_SCL_PIN 0U +#define CYBSP_EZI2C_SCL_NUM 0U +#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_0_HSIOM + #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_1_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_EZI2C_SCL_HAL_PORT_PIN P1_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW +#endif //defined (CY_USING_HAL) +#define CYBSP_EZI2C_SDA_ENABLED 1U +#define CYBSP_EZI2C_SDA_PORT GPIO_PRT1 +#define CYBSP_EZI2C_SDA_PORT_NUM 1U +#define CYBSP_EZI2C_SDA_PIN 1U +#define CYBSP_EZI2C_SDA_NUM 1U +#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_1_HSIOM + #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_1_pin_1_HSIOM +#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_1_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_EZI2C_SDA_HAL_PORT_PIN P1_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW +#endif //defined (CY_USING_HAL) +#define CYBSP_BTN0_ENABLED 1U +#define CYBSP_BTN0_PORT GPIO_PRT1 +#define CYBSP_BTN0_PORT_NUM 1U +#define CYBSP_BTN0_PIN 4U +#define CYBSP_BTN0_NUM 4U +#define CYBSP_BTN0_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_BTN0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_4_HSIOM + #define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BTN0_HSIOM ioss_0_port_1_pin_4_HSIOM +#define CYBSP_BTN0_IRQ ioss_interrupts_gpio_1_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_BTN0_HAL_PORT_PIN P1_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BTN0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP +#endif //defined (CY_USING_HAL) +#define CYBSP_LED8_ENABLED 1U +#define CYBSP_LED8_PORT GPIO_PRT1 +#define CYBSP_LED8_PORT_NUM 1U +#define CYBSP_LED8_PIN 5U +#define CYBSP_LED8_NUM 5U +#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED8_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_1_pin_5_HSIOM + #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM +#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_LED8_HAL_PORT_PIN P1_5 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED8_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED8_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED8_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_SWO_ENABLED 1U +#define CYBSP_SWO_PORT GPIO_PRT6 +#define CYBSP_SWO_PORT_NUM 6U +#define CYBSP_SWO_PIN 4U +#define CYBSP_SWO_NUM 4U +#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_PORT_PIN P6_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_SWDIO_ENABLED 1U +#define CYBSP_SWDIO_PORT GPIO_PRT6 +#define CYBSP_SWDIO_PORT_NUM 6U +#define CYBSP_SWDIO_PIN 6U +#define CYBSP_SWDIO_NUM 6U +#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP +#endif //defined (CY_USING_HAL) +#define CYBSP_SWDCK_ENABLED 1U +#define CYBSP_SWDCK_PORT GPIO_PRT6 +#define CYBSP_SWDCK_PORT_NUM 6U +#define CYBSP_SWDCK_PIN 7U +#define CYBSP_SWDCK_NUM 7U +#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define CYBSP_SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_BTN1_ENABLED 1U +#define CYBSP_CSD_BTN1_PORT GPIO_PRT7 +#define CYBSP_CSD_BTN1_PORT_NUM 7U +#define CYBSP_CSD_BTN1_PIN 0U +#define CYBSP_CSD_BTN1_NUM 0U +#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_0_HSIOM + #define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_7_pin_0_HSIOM +#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_7_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1_HAL_PORT_PIN P7_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CINA_ENABLED 1U +#define CYBSP_CINA_PORT GPIO_PRT7 +#define CYBSP_CINA_PORT_NUM 7U +#define CYBSP_CINA_PIN 1U +#define CYBSP_CINA_NUM 1U +#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CINA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_1_HSIOM + #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM +#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CINA_HAL_PORT_PIN P7_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CINB_ENABLED 1U +#define CYBSP_CINB_PORT GPIO_PRT7 +#define CYBSP_CINB_PORT_NUM 7U +#define CYBSP_CINB_PIN 2U +#define CYBSP_CINB_NUM 2U +#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CINB_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_2_HSIOM + #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM +#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CINB_HAL_PORT_PIN P7_2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CMOD_ENABLED 1U +#define CYBSP_CMOD_PORT GPIO_PRT7 +#define CYBSP_CMOD_PORT_NUM 7U +#define CYBSP_CMOD_PIN 7U +#define CYBSP_CMOD_NUM 7U +#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CMOD_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_7_pin_7_HSIOM + #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM +#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CMOD_HAL_PORT_PIN P7_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_BT_UART_RX_ENABLED 1U +#define CYBSP_BT_UART_RX_PORT GPIO_PRT8 +#define CYBSP_BT_UART_RX_PORT_NUM 8U +#define CYBSP_BT_UART_RX_PIN 0U +#define CYBSP_BT_UART_RX_NUM 0U +#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_0_HSIOM + #define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_8_pin_0_HSIOM +#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_8_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RX_HAL_PORT_PIN P8_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE +#endif //defined (CY_USING_HAL) +#define CYBSP_BT_UART_TX_ENABLED 1U +#define CYBSP_BT_UART_TX_PORT GPIO_PRT8 +#define CYBSP_BT_UART_TX_PORT_NUM 8U +#define CYBSP_BT_UART_TX_PIN 1U +#define CYBSP_BT_UART_TX_NUM 1U +#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_1_HSIOM + #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_8_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_TX_HAL_PORT_PIN P8_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_BT_UART_RTS_ENABLED 1U +#define CYBSP_BT_UART_RTS_PORT GPIO_PRT8 +#define CYBSP_BT_UART_RTS_PORT_NUM 8U +#define CYBSP_BT_UART_RTS_PIN 2U +#define CYBSP_BT_UART_RTS_NUM 2U +#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_2_HSIOM + #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_8_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RTS_HAL_PORT_PIN P8_2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_BT_UART_CTS_ENABLED 1U +#define CYBSP_BT_UART_CTS_PORT GPIO_PRT8 +#define CYBSP_BT_UART_CTS_PORT_NUM 8U +#define CYBSP_BT_UART_CTS_PIN 3U +#define CYBSP_BT_UART_CTS_NUM 3U +#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_8_pin_3_HSIOM + #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_8_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_CTS_HAL_PORT_PIN P8_3 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD0_ENABLED 1U +#define CYBSP_CSD_SLD0_PORT GPIO_PRT9 +#define CYBSP_CSD_SLD0_PORT_NUM 9U +#define CYBSP_CSD_SLD0_PIN 0U +#define CYBSP_CSD_SLD0_NUM 0U +#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_0_HSIOM + #define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_9_pin_0_HSIOM +#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_9_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0_HAL_PORT_PIN P9_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD1_ENABLED 1U +#define CYBSP_CSD_SLD1_PORT GPIO_PRT9 +#define CYBSP_CSD_SLD1_PORT_NUM 9U +#define CYBSP_CSD_SLD1_PIN 1U +#define CYBSP_CSD_SLD1_NUM 1U +#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_1_HSIOM + #define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_9_pin_1_HSIOM +#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_9_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1_HAL_PORT_PIN P9_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD2_ENABLED 1U +#define CYBSP_CSD_SLD2_PORT GPIO_PRT9 +#define CYBSP_CSD_SLD2_PORT_NUM 9U +#define CYBSP_CSD_SLD2_PIN 2U +#define CYBSP_CSD_SLD2_NUM 2U +#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_2_HSIOM + #define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_9_pin_2_HSIOM +#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_9_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2_HAL_PORT_PIN P9_2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD3_ENABLED 1U +#define CYBSP_CSD_SLD3_PORT GPIO_PRT9 +#define CYBSP_CSD_SLD3_PORT_NUM 9U +#define CYBSP_CSD_SLD3_PIN 3U +#define CYBSP_CSD_SLD3_NUM 3U +#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_3_HSIOM + #define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_9_pin_3_HSIOM +#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_9_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3_HAL_PORT_PIN P9_3 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_SLD4_ENABLED 1U +#define CYBSP_CSD_SLD4_PORT GPIO_PRT9 +#define CYBSP_CSD_SLD4_PORT_NUM 9U +#define CYBSP_CSD_SLD4_PIN 4U +#define CYBSP_CSD_SLD4_NUM 4U +#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_4_HSIOM + #define ioss_0_port_9_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_9_pin_4_HSIOM +#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_9_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4_HAL_PORT_PIN P9_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_CSD_BTN0_ENABLED 1U +#define CYBSP_CSD_BTN0_PORT GPIO_PRT9 +#define CYBSP_CSD_BTN0_PORT_NUM 9U +#define CYBSP_CSD_BTN0_PIN 7U +#define CYBSP_CSD_BTN0_NUM 7U +#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_9_pin_7_HSIOM + #define ioss_0_port_9_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_9_pin_7_HSIOM +#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_9_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0_HAL_PORT_PIN P9_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) + +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_BTN0_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_BTN0_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_LED8_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CINA_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CINB_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CMOD_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c new file mode 100644 index 00000000000..14d433859db --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -0,0 +1,265 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.c +* +* Description: +* Provides definitions of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_qspi_memslot.h" + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xECU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_QUAD, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0x01U, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 4U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x06U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x04U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xDCU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x60U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x34U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x35U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x05U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x01U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = +{ + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x04U, + /* The size of the memory. */ + .memSize = 0x04000000U, + /* Specifies the Read command. */ + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, + /* Specifies the Erase command. */ + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x00040000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, + /* Specifies the Program command. */ + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, + /* Specifies the page size for programming. */ + .programSize = 0x00000200U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x01U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x02U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 2600U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 460000U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 1300U +}; + +const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = +{ + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_0, + /* Flags. */ + .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN, + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave is mapped to in the PSoC memory map. + Valid when the memory-mapped mode is enabled. */ + .baseAddress = 0x18000000U, + /* The size allocated in the PSoC memory map, for the memory slave device. + The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ + .memMappedSize = 0x4000000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + Valid when the memory mapped mode is enabled. */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 +}; + +const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { + &S25FL512S_4byteaddr_SlaveSlot_0 +}; + +const cy_stc_smif_block_config_t smifBlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR +}; + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h new file mode 100644 index 00000000000..0ee62b1d559 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -0,0 +1,50 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.h +* +* Description: +* Provides declarations of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#ifndef CYCFG_QSPI_MEMSLOT_H +#define CYCFG_QSPI_MEMSLOT_H +#include "cy_smif_memslot.h" + +#define CY_SMIF_DEVICE_NUM 1 + +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; + +extern const cy_stc_smif_block_config_t smifBlockConfig; + + +#endif /*CY_SMIF_MEMCONFIG_H*/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c new file mode 100644 index 00000000000..ec1467e1d3a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -0,0 +1,43 @@ +/******************************************************************************* +* File Name: cycfg_routing.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_routing.h" + +#include "cy_device_headers.h" + +void init_cycfg_routing(void) +{ + HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; + HSIOM->AMUX_SPLIT_CTL[5] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h new file mode 100644 index 00000000000..8a5ea321f77 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* File Name: cycfg_routing.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() +#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN +#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT +#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 +#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 +#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 +#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 +#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 +#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK +#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD +#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD +#define ioss_0_port_1_pin_0_HSIOM P1_0_SCB7_I2C_SCL +#define ioss_0_port_1_pin_1_HSIOM P1_1_SCB7_I2C_SDA +#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_0_HSIOM P8_0_SCB4_UART_RX +#define ioss_0_port_8_pin_1_HSIOM P8_1_SCB4_UART_TX +#define ioss_0_port_8_pin_2_HSIOM P8_2_SCB4_UART_RTS +#define ioss_0_port_8_pin_3_HSIOM P8_3_SCB4_UART_CTS +#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_9_pin_4_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_9_pin_7_HSIOM HSIOM_SEL_AMUXA + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c new file mode 100644 index 00000000000..8e29aa992f5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -0,0 +1,586 @@ +/******************************************************************************* +* File Name: cycfg_system.c +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_system.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_INIT 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP +#define CY_CFG_PWR_USING_ULP 0 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 4U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 1U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 2U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 3U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 4U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +{ + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() +{ + Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_ClkHf1Init() +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init() +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); +} +__STATIC_INLINE void Cy_SysClk_ClkHf3Init() +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init() +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init() +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init() +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_Pll0Init() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_ClkTimerInit() +{ + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0U); + Cy_SysClk_ClkTimerEnable(); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} +__STATIC_INLINE void init_cycfg_power(void) +{ + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #else /* Dedicated Supply */ + Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + /* Configure core regulator */ + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); + Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); + #endif /* CY_CFG_PWR_USING_LDO */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */ +} + + +void init_cycfg_system(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #ifdef CY_CFG_SYSCLK_MFO_ENABLED + Cy_SysClk_MfoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED + Cy_SysClk_ClkMfInit(); + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h new file mode 100644 index 00000000000..139dff5bdec --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: cycfg_system.h +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_systick.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dap_0_ENABLED 1U +#define srss_0_clock_0_ENABLED 1U +#define srss_0_clock_0_altsystickclk_0_ENABLED 1U +#define srss_0_clock_0_bakclk_0_ENABLED 1U +#define srss_0_clock_0_fastclk_0_ENABLED 1U +#define srss_0_clock_0_fll_0_ENABLED 1U +#define srss_0_clock_0_hfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF0 0UL +#define srss_0_clock_0_hfclk_1_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF1 1UL +#define srss_0_clock_0_hfclk_2_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF2 2UL +#define srss_0_clock_0_hfclk_3_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF3 3UL +#define srss_0_clock_0_ilo_0_ENABLED 1U +#define srss_0_clock_0_imo_0_ENABLED 1U +#define srss_0_clock_0_lfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define srss_0_clock_0_pathmux_0_ENABLED 1U +#define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_pathmux_2_ENABLED 1U +#define srss_0_clock_0_pathmux_3_ENABLED 1U +#define srss_0_clock_0_pathmux_4_ENABLED 1U +#define srss_0_clock_0_periclk_0_ENABLED 1U +#define srss_0_clock_0_pll_0_ENABLED 1U +#define srss_0_clock_0_slowclk_0_ENABLED 1U +#define srss_0_clock_0_timerclk_0_ENABLED 1U +#define srss_0_clock_0_wco_0_ENABLED 1U +#define srss_0_power_0_ENABLED 1U +#define CY_CFG_PWR_MODE_LP 0x01UL +#define CY_CFG_PWR_MODE_ULP 0x02UL +#define CY_CFG_PWR_MODE_ACTIVE 0x04UL +#define CY_CFG_PWR_MODE_SLEEP 0x08UL +#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL +#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP +#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP +#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_system(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg new file mode 100644 index 00000000000..909b041e9fd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -0,0 +1,3 @@ +set SMIF_BANKS { + 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index 8c300189954..432af6e408c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,29 +1,14 @@ -[Device="CY8C6247FDI-D32"] +[Device=CY8C6247FDI-D32] [Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[1].pin[5] -# CYBSP_USER_LED2 -ioss[0].port[11].pin[1] -# CYBSP_USER_BTN1 -ioss[0].port[1].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[5] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[1] -# CYBSP_DEBUG_UART_RTS -ioss[0].port[5].pin[2] -# CYBSP_DEBUG_UART_CTS -ioss[0].port[5].pin[3] - # WIFI # CYBSP_WIFI_SDIO udb[0] +peri[0].div_8[0] +cpuss[0].dw0[0].chan[0] +cpuss[0].dw0[0].chan[1] +cpuss[0].dw1[0].chan[1] +cpuss[0].dw1[0].chan[3] # CYBSP_WIFI_SDIO_D0 ioss[0].port[12].pin[1] # CYBSP_WIFI_SDIO_D1 @@ -37,4 +22,21 @@ ioss[0].port[12].pin[5] # CYBSP_WIFI_SDIO_CLK ioss[0].port[12].pin[0] # CYBSP_WIFI_WL_REG_ON -ioss[0].port[6].pin[2] \ No newline at end of file +ioss[0].port[6].pin[2] + +[RoutingResources] +# CYBSP_WIFI_SDIO +cpuss[0].dw0_tr_in[0] +cpuss[0].dw0_tr_in[1] +cpuss[0].dw1_tr_in[1] +cpuss[0].dw1_tr_in[3] + +udb[0].tr_udb[3] +udb[0].tr_udb[9] +udb[0].tr_udb[10] +udb[0].tr_udb[14] + +tr_group[0].input[46] +tr_group[0].input[47] +tr_group[0].input[48] +tr_group[0].input[49] diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense new file mode 100644 index 00000000000..55253013a71 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -0,0 +1,402 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi new file mode 100644 index 00000000000..6df618b3a8d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL512S-4byteaddr + true + None + 0x18000000 + 0x4000000 + 0x1BFFFFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL512S-4byteaddr + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus new file mode 100644 index 00000000000..45309c3de8f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -0,0 +1,746 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PeripheralNames.h new file mode 100644 index 00000000000..cf547ab3da4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PeripheralNames.h @@ -0,0 +1,118 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)SCB0_BASE, + UART_1 = (int)SCB1_BASE, + UART_2 = (int)SCB2_BASE, + UART_3 = (int)SCB3_BASE, + UART_4 = (int)SCB4_BASE, + UART_5 = (int)SCB5_BASE, + UART_6 = (int)SCB6_BASE, + UART_7 = (int)SCB7_BASE, +} UARTName; + +#define DEVICE_SPI_COUNT CY_IP_MXSCB_INSTANCES + +typedef enum { + SPI_0 = (int)SCB0_BASE, + SPI_1 = (int)SCB1_BASE, + SPI_2 = (int)SCB2_BASE, + SPI_3 = (int)SCB3_BASE, + SPI_4 = (int)SCB4_BASE, + SPI_5 = (int)SCB5_BASE, + SPI_6 = (int)SCB6_BASE, + SPI_7 = (int)SCB7_BASE, + SPI_8 = (int)SCB8_BASE, +} SPIName; + +typedef enum { + I2C_0 = (int)SCB0_BASE, + I2C_1 = (int)SCB1_BASE, + I2C_2 = (int)SCB2_BASE, + I2C_3 = (int)SCB3_BASE, + I2C_4 = (int)SCB4_BASE, + I2C_5 = (int)SCB5_BASE, + I2C_6 = (int)SCB6_BASE, + I2C_7 = (int)SCB7_BASE, + I2C_8 = (int)SCB8_BASE, +} I2CName; + +typedef enum { + PWM_32b_0 = TCPWM0_BASE, + PWM_32b_1, + PWM_32b_2, + PWM_32b_3, + PWM_32b_4, + PWM_32b_5, + PWM_32b_6, + PWM_32b_7, + PWM_16b_0 = TCPWM1_BASE, + PWM_16b_1, + PWM_16b_2, + PWM_16b_3, + PWM_16b_4, + PWM_16b_5, + PWM_16b_6, + PWM_16b_7, + PWM_16b_8, + PWM_16b_9, + PWM_16b_10, + PWM_16b_11, + PWM_16b_12, + PWM_16b_13, + PWM_16b_14, + PWM_16b_15, + PWM_16b_16, + PWM_16b_17, + PWM_16b_18, + PWM_16b_19, + PWM_16b_20, + PWM_16b_21, + PWM_16b_22, + PWM_16b_23, +} PWMName; + +typedef enum { + ADC_0 = (int)SAR_BASE, +} ADCName; + +typedef enum { + DAC_0 = (int)CTDAC0_BASE, +} DACName; + +typedef enum { + QSPI_0, +} QSPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PeripheralPins.c new file mode 100644 index 00000000000..de0b780accc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PeripheralPins.c @@ -0,0 +1,352 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +#if DEVICE_SERIAL +//*** SERIAL *** +const PinMap PinMap_UART_RX[] = { + {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)}, + {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)}, + {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, + {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)}, + {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, + {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)}, + {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)}, + {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, + {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, + {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)}, + {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_TX[] = { + {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)}, + {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)}, + {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, + {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)}, + {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, + {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, + {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)}, + {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, + {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, + {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)}, + {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_RTS[] = { + {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, + {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, + {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, + {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, + {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, + {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)}, + {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, + {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)}, + {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_CTS[] = { + {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, + {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, + {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, + {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, + {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)}, + {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)}, + {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, + {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)}, + {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)}, + {NC, NC, 0} +}; +#endif // DEVICE_SERIAL + + +#if DEVICE_I2C +//*** I2C *** +const PinMap PinMap_I2C_SCL[] = { + {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)}, + {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)}, + {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, + {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)}, + {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)}, + {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, + {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)}, + {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)}, + {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)}, + {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, + {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, + {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)}, + {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)}, + {NC, NC, 0} +}; +const PinMap PinMap_I2C_SDA[] = { + {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)}, + {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)}, + {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, + {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)}, + {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)}, + {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, + {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)}, + {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, + {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)}, + {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, + {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, + {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)}, + {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)}, + {NC, NC, 0} +}; +#endif // DEVICE_I2C + +#if DEVICE_SPI +//*** SPI *** +const PinMap PinMap_SPI_MOSI[] = { + {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)}, + {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)}, + {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, + {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)}, + {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, + {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)}, + {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)}, + {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)}, + {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, + {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, + {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)}, + {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_MISO[] = { + {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)}, + {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)}, + {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, + {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)}, + {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)}, + {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, + {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)}, + {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, + {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)}, + {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, + {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, + {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)}, + {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SCLK[] = { + {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, + {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, + {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, + {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)}, + {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, + {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)}, + {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, + {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)}, + {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, + {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)}, + {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SSEL[] = { + {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, + {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, + {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, + {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)}, + {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, + {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)}, + {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)}, + {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)}, + {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, + {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)}, + {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)}, + {NC, NC, 0} +}; +#endif // DEVICE_SPI + +#if DEVICE_PWMOUT +//*** PWM *** +const PinMap PinMap_PWM_OUT[] = { + // 16-bit PWM outputs + {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, + {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)}, + {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, + {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)}, + {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)}, + {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, + {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, + {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, + {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, + {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)}, + {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, + {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, + {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, + {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)}, + {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, + {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)}, + {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)}, + {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)}, + {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, + {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, + {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, + {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, + {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, + {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)}, + {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)}, + {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)}, + {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)}, + {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)}, + {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)}, + {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, + // 16-bit PWM inverted outputs + {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, + {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)}, + {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, + {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)}, + {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)}, + {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, + {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, + {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, + {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)}, + {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)}, + {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, + {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, + {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, + {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, + {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)}, + {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, + {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)}, + {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)}, + {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, + {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, + {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)}, + {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, + {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, + {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)}, + {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)}, + {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)}, + {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)}, + {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)}, + {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)}, + {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, + // 32-bit PWM outputs + {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, + {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)}, + {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, + {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)}, + {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)}, + {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, + {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, + {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, + {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, + {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)}, + {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, + {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, + {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, + {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)}, + {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, + {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)}, + {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)}, + {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)}, + {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, + {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, + {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, + {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, + {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, + {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)}, + {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)}, + {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)}, + {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)}, + {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)}, + {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)}, + {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, + // 32-bit PWM inverted outputs + {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, + {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)}, + {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, + {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)}, + {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)}, + {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, + {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, + {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, + {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)}, + {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)}, + {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, + {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, + {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, + {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, + {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)}, + {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, + {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)}, + {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)}, + {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, + {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, + {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)}, + {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, + {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, + {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)}, + {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)}, + {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)}, + {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)}, + {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)}, + {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)}, + {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, + {NC, NC, 0} +}; +#endif // DEVICE_PWMOUT + +#if DEVICE_ANALOGIN +const PinMap PinMap_ADC[] = { + {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_ANALOGOUT +const PinMap PinMap_DAC[] = { + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_QSPI +const PinMap PinMap_QSPI_SCLK[] = { + {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_SSEL[] = { + {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA0[] = { + {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA1[] = { + {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA2[] = { + {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA3[] = { + {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +#endif // DEVICE_QSPI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PinNames.h new file mode 100644 index 00000000000..38560ac0b53 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/PinNames.h @@ -0,0 +1,66 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "PinNamesTypes.h" +#include "cyhal_pin_package.h" + +// Generic signal names + +#define I2C_SCL P1_0 +#define I2C_SDA P1_1 + +#define UART_RX P5_0 +#define UART_TX P5_1 +#define UART_RTS P5_2 +#define UART_CTS P5_3 + +#define LED1 P1_5 +#define LED2 P11_0 + +#define SWITCH2 P1_4 +#define USER_BUTTON SWITCH2 +#define BUTTON1 USER_BUTTON + +#define QSPI_CLK P11_7 +#define QSPI_IO_0 P11_6 +#define QSPI_IO_1 P11_5 +#define QSPI_IO_2 P11_4 +#define QSPI_IO_3 P11_3 +#define QSPI_SEL P11_2 + +#define QSPI_FLASH1_IO0 QSPI_IO_0 +#define QSPI_FLASH1_IO1 QSPI_IO_1 +#define QSPI_FLASH1_IO2 QSPI_IO_2 +#define QSPI_FLASH1_IO3 QSPI_IO_3 +#define QSPI_FLASH1_SCK QSPI_CLK +#define QSPI_FLASH1_CSN QSPI_SEL + +// Standardized interfaces names +#define STDIO_UART_TX UART_TX +#define STDIO_UART_RX UART_RX +#define STDIO_UART_CTS UART_CTS +#define STDIO_UART_RTS UART_RTS + +#define USBTX UART_TX +#define USBRX UART_RX + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c new file mode 100644 index 00000000000..6ccc0e7252e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c @@ -0,0 +1,1470 @@ +/***************************************************************************//** +* \file SDIO_HOST.c +* +* \brief +* This file provides the source code to the API for the UDB based SDIO driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "SDIO_HOST.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifdef CY_RTOS_AWARE + + #include "cyabs_rtos.h" + + #define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) + static cy_semaphore_t sdio_transfer_finished_semaphore; + static bool sema_initialized = false; +#endif + +/* Backup struct used to store and restore non retention UDB registers */ +typedef struct +{ + uint32_t CY_SDIO_UDB_WRKMULT_CTL_0; + uint32_t CY_SDIO_UDB_WRKMULT_CTL_1; + uint32_t CY_SDIO_UDB_WRKMULT_CTL_2; + uint32_t CY_SDIO_UDB_WRKMULT_CTL_3; +} stc_sdio_backup_regs_t; + +/*Globals Needed for DMA */ +/*DMA channel structures*/ +cy_stc_dma_channel_config_t respChannelConfig; +cy_stc_dma_channel_config_t cmdChannelConfig; +cy_stc_dma_channel_config_t writeChannelConfig; +cy_stc_dma_channel_config_t readChannelConfig; + +/*DMA Descriptor structures*/ +cy_stc_dma_descriptor_t respDesr; +cy_stc_dma_descriptor_t cmdDesr; +cy_stc_dma_descriptor_t readDesr0; +cy_stc_dma_descriptor_t readDesr1; +cy_stc_dma_descriptor_t writeDesr0; +cy_stc_dma_descriptor_t writeDesr1; + +/*Global structure used for data keeping*/ +stc_sdio_gInternalData_t gstcInternalData; + +/*Global CRC table*/ +static uint8_t crcTable[256]; + +/*Global values used for DMA interrupt*/ +static uint32_t yCountRemainder; +static uint32_t yCounts; + +/* Global value for card interrupt */ +static uint8_t pfnCardInt_count = 0; + +/*Global structure to store UDB registers */ +static stc_sdio_backup_regs_t regs; + +static uint32_t udb_initialized = 0; + +cy_stc_syspm_callback_params_t sdio_pm_callback_params; +cy_stc_syspm_callback_t sdio_pm_callback_handler; + +/* Deep Sleep Mode API Support */ +static void SDIO_SaveConfig(void); +static void SDIO_RestoreConfig(void); + +/******************************************************************************* +* Function Name: SDIO_DeepSleepCallback +****************************************************************************//** +* +* Callback executed during Deep Sleep entry/exit +* +* \note +* Saves/Restores SDIO UDB registers +*******************************************************************************/ +cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) +{ + cy_en_syspm_status_t status = CY_SYSPM_FAIL; + + switch (mode) + { + case CY_SYSPM_CHECK_READY: + case CY_SYSPM_CHECK_FAIL: + status = CY_SYSPM_SUCCESS; + break; + + case CY_SYSPM_BEFORE_TRANSITION: + SDIO_SaveConfig(); + status = CY_SYSPM_SUCCESS; + break; + + case CY_SYSPM_AFTER_TRANSITION: + SDIO_RestoreConfig(); + status = CY_SYSPM_SUCCESS; + break; + + default: + break; + } + + return status; +} + +/******************************************************************************* +* Function Name: SDIO_Init +****************************************************************************//** +* +* Initializes the SDIO hardware +* +* \param pfuCb +* Pointer to structure that holds pointers to callback function +* see \ref stc_sdio_irq_cb_t. +* +* \note +* Sets SD Clock Frequency to 400 kHz +*******************************************************************************/ +void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) +{ + if ( !udb_initialized ) + { + udb_initialized = 1; + SDIO_Host_Config_TriggerMuxes(); + SDIO_Host_Config_UDBs(); + } + + /*Set Number of Blocks to 1 initially, this will be updated later*/ + SDIO_SetNumBlocks(1); + + /*Enable SDIO ISR*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + + /*Enable the Status Reg to generate an interrupt*/ + SDIO_STATUS_AUX_CTL |= (0x10); + + /*Set the priority of DW0, DW1, M4 and M0. DW1 should have highest*/ + /*First clear priority of all*/ + (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS3_CTL) &= ~0x0300; + (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) &= ~0x0300; + + /*Next set priority DW1 = 0, DW0 = 1, M4 = 2, M0 =3*/ + (* (reg32 *)CYREG_PROT_SMPU_MS2_CTL) |= 0x0100; + (* (reg32 *)CYREG_PROT_SMPU_MS0_CTL) |= 0x0200; + (* (reg32 *)CYREG_PROT_SMPU_MS14_CTL) |= 0x0200; + + /*Setup callback for card interrupt*/ + gstcInternalData.pstcCallBacks.pfnCardIntCb = pfuCb->pfnCardIntCb; + + /*Setup the DMA channels*/ + SDIO_SetupDMA(); + + /*Initialize CRC*/ + SDIO_Crc7Init(); + + /*Enable all the bit counters*/ + SDIO_CMD_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_WRITE_CRC_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_CRC_BIT_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + SDIO_BYTE_CNT_CONTROL_REG |= SDIO_ENABLE_CNT; + + /*Set block byte count to 64, this will be changed later */ + SDIO_SetBlockSize(64); + + /*Set the read and write FIFOs to use the half full status*/ + (*(reg32 *) SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG) |= 0x0c; + (*(reg32 *) SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG) |= 0x0c; + + /*Set clock to 400k, and enable it*/ + SDIO_SetSdClkFrequency(400000); + SDIO_EnableIntClock(); + SDIO_EnableSdClk(); +} + + +/******************************************************************************* +* Function Name: SDIO_SendCommand +****************************************************************************//** +* +* Send an SDIO command, don't wait for it to finish. +* +* \param pstcCmdConfig +* Command configuration structure. See \ref stc_sdio_cmd_config_t. +* +*******************************************************************************/ +void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig) +{ + /*buffer to hold command data*/ + static uint8_t u8cmdBuf[6]; + + /*Populate buffer*/ + /*Element 0 is the Most Significant Byte*/ + u8cmdBuf[0] = SDIO_HOST_DIR | pstcCmdConfig->u8CmdIndex; + u8cmdBuf[1] = (uint8_t)((pstcCmdConfig->u32Argument & 0xff000000)>>24); + u8cmdBuf[2] = (uint8_t)((pstcCmdConfig->u32Argument & 0x00ff0000)>>16); + u8cmdBuf[3] = (uint8_t)((pstcCmdConfig->u32Argument & 0x0000ff00)>>8); + u8cmdBuf[4] = (uint8_t)((pstcCmdConfig->u32Argument & 0x000000ff)); + + /*calculate the CRC of above data*/ + u8cmdBuf[5] = SDIO_CalculateCrc7(u8cmdBuf, 5); + /*Shift it up by 1 as the CRC takes the upper 7 bits of the last byte of the cmd*/ + u8cmdBuf[5] = u8cmdBuf[5] << 1; + /*Add on the end bit*/ + u8cmdBuf[5] = u8cmdBuf[5] | SDIO_CMD_END_BIT; + + /*Load the first byte into A0*/ + SDIO_CMD_COMMAND_A0_REG = u8cmdBuf[0]; + + /*If a response is expected setup DMA to receive the response*/ + if (pstcCmdConfig->bResponseRequired == true) + { + /*Clear the flag in hardware that says skip response*/ + SDIO_CONTROL_REG &= ~SDIO_CTRL_SKIP_RESPONSE; + + /*Set the destination address*/ + respDesr.dst = (uint32_t)(pstcCmdConfig->pu8ResponseBuf); + + /*Initialize the channel with the descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respDesr); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL); + } + else + { + /*Set the skip flag*/ + SDIO_CONTROL_REG |= SDIO_CTRL_SKIP_RESPONSE; + } + + /*Setup the Command DMA*/ + /*Set the source address*/ + cmdDesr.src = (uint32_t)(&u8cmdBuf[1]); + + /*Initialize the channel with the descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL , &cmdDesr); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); +} + + +/******************************************************************************* +* Function Name: SDIO_GetResponse +****************************************************************************//** +* +* Takes a 6 byte response buffer, and extracts the 32 bit response, also checks +* for index errors, CRC errors, and end bit errors. +* +* \param bCmdIndexCheck +* If True check for index errors +* +* \param bCmdCrcCheck +* If True check for CRC errors +* +* \param u8cmdIdx +* Command index, used for checking the index error +* +* \param pu32Response +* location to store 32 bit response +* +* \param pu8ResponseBuf +* buffer that holds the 6 bytes of response data +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8cmdIdx, uint32_t* pu32Response, uint8_t *pu8ResponseBuf) +{ + /*Function return*/ + en_sdio_result_t enRet = Error; + /*variable to hold temporary CRC*/ + uint8_t u8TmpCrc; + /*temporary response*/ + uint32_t u32TmpResponse; + + /*Zero out the pu32Response*/ + *pu32Response = 0; + + /*Check if the CRC needs to be checked*/ + if (bCmdCrcCheck) + { + /*Calculate the CRC*/ + u8TmpCrc = SDIO_CalculateCrc7(pu8ResponseBuf, 5); + + /*Shift calculated CRC up by one bit to match bit position of CRC*/ + u8TmpCrc = u8TmpCrc << 1; + + /*Compare calculated CRC with received CRC*/ + if ((u8TmpCrc & 0xfe) != (pu8ResponseBuf[5] & 0xfe)) + { + enRet |= CommandCrcError; + } + } + + /*Check if the index needs to be checked*/ + if (bCmdIndexCheck) + { + /*The index resides in the lower 6 bits of the 1st byte of the response*/ + if ((u8cmdIdx != (pu8ResponseBuf[0] & 0x3f))) + { + enRet |= CommandIdxError; + } + } + + /*Check the end bit*/ + if (!(pu8ResponseBuf[5] & 0x01)) + { + enRet |= CommandEndError; + } + + if (enRet == Error) + { + /*If we get here then there were no errors with the command populate the response*/ + u32TmpResponse = pu8ResponseBuf[1]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[2]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[3]; + u32TmpResponse = u32TmpResponse << 8; + u32TmpResponse |= pu8ResponseBuf[4]; + + *pu32Response = u32TmpResponse; + + enRet = Ok; + } + + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_InitDataTransfer +****************************************************************************//** +* +* Configure the data channel for a data transfer. For a write this doesn't start +* the write, that must be done separately after the response is received. +* +* \param stc_sdio_data_config_t +* Data configuration structure. See \ref stc_sdio_data_config_t +* +* +*******************************************************************************/ +void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig) +{ + /*hold size of entire transfer*/ + uint32_t dataSize; + + /*calculate how many bytes are going to be sent*/ + dataSize = pstcDataConfig->u16BlockSize * pstcDataConfig->u16BlockCount; + + /*Set the block size and number of blocks*/ + SDIO_SetBlockSize(pstcDataConfig->u16BlockSize); + SDIO_SetNumBlocks((pstcDataConfig->u16BlockCount) - 1); + + /*If we are reading data setup the DMA to receive read data*/ + if (pstcDataConfig->bRead == true) + { + /*First disable the write channel*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); + + /*Clear any pending interrupts in the DMA*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + + /*setup the destination addresses*/ + readDesr0.dst = (uint32_t)(pstcDataConfig->pu8Data); + readDesr1.dst = (uint32_t)((pstcDataConfig->pu8Data) + 1024); + + /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes + Remember X increment is in terms of data element size which is 16, thus why it is 1*/ + readDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); + readDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 1); + + /*The X Loop will always transfer 4 bytes. The FIFO will only trigger the + DMA when it has 4 bytes to send (2 in each F0 and F1). There is a possibility + that there could be 3,2,or 1 bytes still in the FIFOs. To solve this the DMA + will be SW triggered when hardware indicates all bytes have been received. + This leads to an extra 1, 2 or 3 bytes being received. So the RX buffer needs to + be at least 3 bytes bigger than the data size. + + Since the X loop is setup to 4, the maximum number of Y loop is 256 so one + descriptor can transfer 1024 bytes. Two descriptors can transfer 2048 bytes. + Since we don't know the maximum number of bytes to read only two descriptors will + be used. If more than 2048 bytes need to be read then and interrupt will be enabled + The descriptor that is not currently running will be updated in the ISR to receive + more data. + + So there are three conditions to check: + 1) Are we sending less than or equal to 1024 bytes if so use one descriptor + 2) Are we sending greater than 1024, but less than or equal to 2048, use two descriptors + 3) Greater than 2048, use two descriptors and the ISR + */ + + if (dataSize <= 1024) + { + /*Setup one descriptor*/ + /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + /*Setup descriptor 0 to point to nothing and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (dataSize <=2048) + { + /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ + + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + + /*Setup descriptor 0 to point to descriptor 1*/ + readDesr0.nextPtr = (uint32_t)(&readDesr1); + /*Setup descriptor 1 to point to nothing and disable */ + readDesr1.nextPtr = 0; + + /*Don't disable after first descriptor*/ + readDesr0.ctl &= ~0x01000000; + /*Disable after second descriptor*/ + readDesr1.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else /*dataSize must be greater than 2048*/ + { + /*These are for the ISR, Need to figure out how many "descriptors" + need to run, and the yCount for last descriptor. + Example: dataSize = 2080 + yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ + yCounts = (dataSize / 1024); + + /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is + no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ + yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); + + /*Setup the Y Ctrl for both descriptors*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + + /*Setup descriptor 0 to point to descriptor 1*/ + readDesr0.nextPtr = (uint32_t)(&readDesr1); + /*Setup descriptor 1 to point to descriptor 0*/ + readDesr1.nextPtr = (uint32_t)(&readDesr0); + + /*Don't disable the channel on completion of descriptor*/ + readDesr0.ctl &= ~0x01000000; + readDesr1.ctl &= ~0x01000000; + + /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ + yCounts -= 2; + + /*Enable DMA interrupt*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + + /*Initialize the channel with the first descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL , &readDesr0); + + /*Enable the channel*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Set the flag in the control register to enable the read*/ + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_READ; + } + + /*Otherwise it is a write*/ + else + { + /*First disable the Read channel*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Clear any pending interrupts in the DMA*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + + /*setup the SRC addresses*/ + writeDesr0.src = (uint32_t)(pstcDataConfig->pu8Data); + writeDesr1.src = (uint32_t)((pstcDataConfig->pu8Data) + 1024); + + + /*Setup the X control to transfer two 16 bit elements per transfer for a total of 4 bytes + Remember X increment is in terms of data element size which is 16, thus why it is 1*/ + writeDesr0.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); + writeDesr1.xCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 1) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 1); + + if (dataSize <= 1024) + { + /*Setup one descriptor*/ + /*Y Increment is 2 because the X is transfer 2 data elements (which are 16 bits)*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1) / 4) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + /*Setup descriptor 0 to point to nothing and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else if (dataSize <=2048) + { + /*setup the first descriptor for 1024, then setup 2nd descriptor for remainder*/ + + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (dataSize - 1025) / 4) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + + /*Setup descriptor 0 to point to descriptor 1*/ + writeDesr0.nextPtr = (uint32_t)(&writeDesr1); + /*Setup descriptor 1 to point to nothing and disable */ + writeDesr1.nextPtr = 0; + + /*Don't disable after first descriptor*/ + writeDesr0.ctl &= ~0x01000000; + /*Disable after second descriptor*/ + writeDesr1.ctl |= 0x01000000; + + /*Disable Interrupt*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else /*dataSize must be greater than 2048*/ + { + /*These are for the ISR, Need to figure out how many "descriptors" + need to run, and the yCount for last descriptor. + Example: dataSize = 2080 + yCounts = 2, yCountRemainder = 7 (send 8 more set of 4)*/ + yCounts = (dataSize / 1024); + + /*the Ycount register is a +1 register meaning 0 = 1. I However, need to know when there is + no remainder so I increase the value to make sure there is a remainder and decrement in the ISR*/ + yCountRemainder = (((dataSize - (yCounts * 1024)) + 3 ) / 4); + + /*Setup the Y Ctrl for both descriptors*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, 255) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + + /*Setup descriptor 0 to point to descriptor 1*/ + writeDesr0.nextPtr = (uint32_t)(&writeDesr1); + /*Setup descriptor 1 to point to descriptor 0*/ + writeDesr1.nextPtr = (uint32_t)(&writeDesr0); + + /*Don't disable the channel on completion of descriptor*/ + writeDesr0.ctl &= ~0x01000000; + writeDesr1.ctl &= ~0x01000000; + + /*Decrement yCounts by 2 since we already have 2 descriptors setup*/ + yCounts -= 2; + + /*Enable DMA interrupt*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + + /*Initialize the channel with the first descriptor*/ + Cy_DMA_Channel_SetDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL , &writeDesr0); + } +} + + +/******************************************************************************* +* Function Name: SDIO_SendCommandAndWait +****************************************************************************//** +* +* This function sends a command on the command channel and waits for that +* command to finish before returning. If a Command 53 is issued this function +* will handle all of the data transfer and wait to return until it is done. +* +* \param pstcCmd +* Pointer command configuration structure see \ref stc_sdio_cmd_t. +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) +{ + /* Store the command and data configurations*/ + stc_sdio_cmd_config_t stcCmdConfig; + stc_sdio_data_config_t stcDataConfig; + + uint32_t u32CmdTimeout = 0; + + /*Returns from various function calls*/ + en_sdio_result_t enRet = Error; + en_sdio_result_t enRetTmp = Ok; + + /* Hold value of if these checks are needed */ + uint8_t bCmdIndexCheck; + uint8_t bCmdCrcCheck; + static uint8_t u8responseBuf[6]; + + /* Clear statuses */ + gstcInternalData.stcEvents.u8CmdComplete = 0; + gstcInternalData.stcEvents.u8TransComplete = 0; + gstcInternalData.stcEvents.u8CRCError = 0; + + /* Setup the command configuration */ + stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx; + stcCmdConfig.u32Argument = pstcCmd->u32Arg; + +#ifdef CY_RTOS_AWARE + + cy_rslt_t result; + + /* Initialize the semaphore. This is not done in init because init is called + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * interrupt thread. + */ + if(!sema_initialized) + { + cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 ); + sema_initialized = true; + } +#else + + /* Variable used for holding timeout value */ + uint32_t u32Timeout = 0; +#endif + + /*Determine the type of response and if we need to do any checks*/ + /*Command 0 and 8 have no response, so don't wait for one*/ + if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8) + { + bCmdIndexCheck = false; + bCmdCrcCheck = false; + stcCmdConfig.bResponseRequired = false; + stcCmdConfig.pu8ResponseBuf = NULL; + } + + /*Command 5's response doesn't have a CRC or index, so don't check*/ + else if (pstcCmd->u32CmdIdx == 5) + { + bCmdIndexCheck = false; + bCmdCrcCheck = false; + stcCmdConfig.bResponseRequired = true; + stcCmdConfig.pu8ResponseBuf = u8responseBuf; + } + /*Otherwise check everything*/ + else + { + bCmdIndexCheck = true; + bCmdCrcCheck = true; + stcCmdConfig.bResponseRequired = true; + stcCmdConfig.pu8ResponseBuf = u8responseBuf; + } + + /*Check if the command is 53, if it is then setup the data transfer*/ + if (pstcCmd->u32CmdIdx == 53) + { + /*Set the number of blocks in the global struct*/ + stcDataConfig.u16BlockCount = (uint16_t)pstcCmd->u16BlockCnt; + /*Set the size of the data transfer*/ + stcDataConfig.u16BlockSize = (uint16_t)pstcCmd->u16BlockSize; + /*Set the direction are we reading or writing*/ + stcDataConfig.bRead = pstcCmd->bRead; + /*Set the pointer for the data*/ + stcDataConfig.pu8Data = pstcCmd->pu8Data; + + /*Get the data Transfer Ready*/ + SDIO_InitDataTransfer(&stcDataConfig); + + /*Set bit saying this was a CMD_53*/ + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_INT; + } + + /*Send the command*/ + SDIO_SendCommand(&stcCmdConfig); + + /*Wait for the command to finish*/ + do + { + //TODO: Use RTOS timeout + u32CmdTimeout++; + enRetTmp = SDIO_CheckForEvent(SdCmdEventCmdDone); + + } while ((enRetTmp != Ok) && (u32CmdTimeout < SDIO_CMD_TIMEOUT)); + + + if (u32CmdTimeout == SDIO_CMD_TIMEOUT) + { + enRet |= CMDTimeout; + } + else /*CMD Passed*/ + { + /*If a response is expected check it*/ + if (stcCmdConfig.bResponseRequired == true) + { + enRetTmp = SDIO_GetResponse(bCmdCrcCheck, bCmdIndexCheck, (uint8_t)pstcCmd->u32CmdIdx, pstcCmd->pu32Response, u8responseBuf); + if (enRetTmp != Ok) + { + enRet |= enRetTmp; + } + else /*Response good*/ + { + /*if it was command 53, check the response to ensure there was no error*/ + if ((pstcCmd->u32CmdIdx) == 53) + { + /*Make sure none of the error bits are set*/ + if (*(pstcCmd->pu32Response) & 0x0000cf00) + { + enRet |= ResponseFlagError; + } + else /*CMD53 Response good*/ + { + /*If it was command 53 and it was a write enable the write*/ + if (pstcCmd->bRead == false && enRet == Error) + { + Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + + /*Set the flag in the control register to enable the write*/ + Cy_DMA_Channel_Enable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + /*Enable the channel*/ + Cy_SysLib_DelayCycles(35); + SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE; + } + + #ifdef CY_RTOS_AWARE + /* Wait for the transfer to finish. + * Acquire semaphore and wait until it will be released + * in SDIO_IRQ: + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in + * SDIO_IRQ. + * 2. The cy_rtos_set_semaphore() increases + * sdio_transfer_finished_semaphore count. + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero + * and exit. Or timeout occurs + */ + result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); + + enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); + + if (result != CY_RSLT_SUCCESS) + #else + /* Wait for the transfer to finish */ + do + { + u32Timeout++; + enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone); + + } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT))); + + if (u32Timeout == SDIO_DAT_TIMEOUT) + #endif + { + enRet |= DataTimeout; + } + + /* if it was a read it is possible there is still extra data hanging out, trigger the + DMA again. This can result in extra data being transfered so the read buffer should be + 3 bytes bigger than needed*/ + if (pstcCmd->bRead == true) + { + Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2); + } + + if (enRetTmp == DataCrcError) + { + enRet |= DataCrcError; + } + }/*CMD53 response good*/ + }/*Not a CMD53*/ + } /*Response Good*/ + } /*No Response Required, thus no CMD53*/ + } /*CMD Passed*/ + +#ifndef CY_RTOS_AWARE + u32Timeout = 0; +#endif + + /*If there were no errors then indicate transfer was okay*/ + if (enRet == Error) + { + enRet = Ok; + } + + /*reset CmdTimeout value*/ + u32CmdTimeout = 0; + + /*Always Reset on exit to clean up*/ + Cy_DMA_Channel_Disable(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL ); + Cy_DMA_Channel_Disable(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL ); + /*No longer a CMD_53*/ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_INT | SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_READ); + SDIO_Reset(); + + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_CheckForEvent +****************************************************************************//** +* +* Checks to see if a specific event has occurred such a command complete or +* transfer complete. +* +* \param enEventType +* The type of event to check for. See \ref en_sdio_event_t. +* +* \return +* \ref en_sdio_result_t +* +*******************************************************************************/ +en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType) +{ + en_sdio_result_t enRet = Error; + + /*Disable Interrupts while modifying the global*/ + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + + /*Switch the event to check*/ + switch ( enEventType ) + { + /*If the command is done clear the flag*/ + case SdCmdEventCmdDone: + if (gstcInternalData.stcEvents.u8CmdComplete > 0) + { + gstcInternalData.stcEvents.u8CmdComplete = 0; + enRet = Ok; + } + break; + + /*If the transfer is done check for CRC Error and clear the flag*/ + case SdCmdEventTransferDone: + if (gstcInternalData.stcEvents.u8TransComplete > 0) + { + gstcInternalData.stcEvents.u8TransComplete = 0; + enRet = Ok; + } + /*Check for CRC error and set flags*/ + if (gstcInternalData.stcEvents.u8CRCError > 0) + { + enRet = DataCrcError; + gstcInternalData.stcEvents.u8CRCError = 0; + } + break; + } + + /*Re-enable Interrupts*/ + NVIC_EnableIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); + return enRet; +} + + +/******************************************************************************* +* Function Name: SDIO_CalculateCrc7 +****************************************************************************//** +* +* Calculate the 7 bit CRC for the command channel +* +* \param pu8Data +* Data to calculate CRC on +* +* \param u8Size +* Number of bytes to calculate CRC on +* +* \return +* CRC +* +* \note +* This code was copied from +* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code +* +*******************************************************************************/ +uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t u8Size) +{ + uint8_t data; + uint8_t remainder = 0; + uint32_t byte; + + for(byte = 0; byte < u8Size; ++byte) + { + data = pu8Data[byte] ^ remainder; + remainder = crcTable[data] ^ (remainder << 8); + } + + return (remainder>>1); +} + + +/******************************************************************************* +* Function Name: SDIO_Crc7Init +****************************************************************************//** +* +* Initialize 7-bit CRC Table +* +* \note +* This code was copied from +* http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code +* +*******************************************************************************/ +void SDIO_Crc7Init(void) +{ + uint8_t remainder; + uint8_t bit; + uint32_t dividend; + + for(dividend = 0; dividend < 256; ++dividend) + { + remainder = dividend; + + for(bit = 8; bit > 0; --bit) + { + if (remainder & SDIO_CRC_UPPER_BIT) + { + remainder = (remainder << 1) ^ SDIO_CRC7_POLY; + } + else + { + remainder = (remainder << 1); + } + } + + crcTable[dividend] = (remainder); + } +} + + +/******************************************************************************* +* Function Name: SDIO_SetBlockSize +****************************************************************************//** +* +* Sets the size of each block +* +* \param u8ByteCount +* Size of the block +* +*******************************************************************************/ +void SDIO_SetBlockSize(uint8_t u8ByteCount) +{ + SDIO_BYTE_COUNT_REG = u8ByteCount; +} + + +/******************************************************************************* +* Function Name: SDIO_SetNumBlocks +****************************************************************************//** +* +* Sets the number of blocks to send +* +* \param u8ByteCount +* Size of the block +* +*******************************************************************************/ +void SDIO_SetNumBlocks(uint8_t u8BlockCount) +{ + SDIO_DATA_BLOCK_COUNTER_A0_REG = u8BlockCount; + SDIO_DATA_BLOCK_COUNTER_D0_REG = u8BlockCount; + /*The one is used so that we can do 256 bytes*/ + SDIO_DATA_BLOCK_COUNTER_A1_REG = 1; + SDIO_DATA_BLOCK_COUNTER_D1_REG = 1; +} + + +/******************************************************************************* +* Function Name: SDIO_EnableIntClock +****************************************************************************//** +* +* Enable Internal clock for the block +* +*******************************************************************************/ +void SDIO_EnableIntClock(void) +{ + SDIO_CONTROL_REG |= SDIO_CTRL_INT_CLK; + Cy_SysClk_PeriphEnableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); +} + + +/******************************************************************************* +* Function Name: SDIO_DisableIntClock +****************************************************************************//** +* +* Enable Disable clock for the block +* +*******************************************************************************/ +void SDIO_DisableIntClock(void) +{ + SDIO_CONTROL_REG &= ~SDIO_CTRL_INT_CLK; + Cy_SysClk_PeriphDisableDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM); +} + + +/******************************************************************************* +* Function Name: SDIO_EnableSdClk +****************************************************************************//** +* +* Enable SD Clock out to pin +* +*******************************************************************************/ +void SDIO_EnableSdClk(void) +{ + SDIO_CONTROL_REG |= SDIO_CTRL_SD_CLK; +} + + +/******************************************************************************* +* Function Name: SDIO_DisableSdClk +****************************************************************************//** +* +* Disable SD Clock out to the pin +* +*******************************************************************************/ +void SDIO_DisableSdClk(void) +{ + SDIO_CONTROL_REG &= ~SDIO_CTRL_SD_CLK; +} + + +/******************************************************************************* +* Function Name: SDIO_SetSdClkFrequency +****************************************************************************//** +* +* Sets the frequency of the SD Clock +* +* \param u32SdClkFreqHz +* Frequency of SD Clock in Hz. +* +* \note +* Only an integer divider is used, so the desired frequency may not be meet +*******************************************************************************/ +void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) +{ + uint16_t u16Div; + u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); +} + + +/******************************************************************************* +* Function Name: SDIO_SetupDMA +****************************************************************************//** +* +* Configures the DMA for the SDIO block +* +*******************************************************************************/ +void SDIO_SetupDMA(void) +{ + /*Set the number of bytes to send*/ + SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.xCount = (SDIO_NUM_RESP_BYTES - 1); + /*Set the destination address*/ + SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config.dstAddress = (void*)SDIO_CMD_COMMAND_PTR; + + /*Initialize descriptor for cmd channel*/ + Cy_DMA_Descriptor_Init(&cmdDesr, &SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config); + + /*Set flag to disable descriptor when done*/ + cmdDesr.ctl |= 0x01000000; + + /*Configure channel*/ + /*CMD channel can be preempted, and has lower priority*/ + cmdChannelConfig.descriptor = &cmdDesr; + cmdChannelConfig.preemptable = 1; + cmdChannelConfig.priority = 1; + cmdChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_CMD_DMA_HW, SDIO_HOST_CMD_DMA_DW_CHANNEL, &cmdChannelConfig); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_CMD_DMA_HW); + + /*Set the number of bytes to receive*/ + SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.xCount = SDIO_NUM_RESP_BYTES; + /*Set the source address*/ + SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config.srcAddress = (void*)SDIO_CMD_RESPONSE_PTR; + + /*Initialize descriptor for response channel*/ + Cy_DMA_Descriptor_Init(&respDesr, &SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config); + + /*Set flag to disable descriptor when done*/ + respDesr.ctl |= 0x01000000; + + /*Configure channel*/ + /*response channel can be preempted, and has lower priority*/ + respChannelConfig.descriptor = &respDesr; + respChannelConfig.preemptable = 1; + respChannelConfig.priority = 1; + respChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Resp_DMA_HW, SDIO_HOST_Resp_DMA_DW_CHANNEL, &respChannelConfig); + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Resp_DMA_HW); + + /*Set the destination address*/ + SDIO_HOST_Write_DMA_Write_DMA_Desc_config.dstAddress = (void*)SDIO_DAT_WRITE_PTR; + + /*Initialize descriptor for write channel*/ + Cy_DMA_Descriptor_Init(&writeDesr0, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); + Cy_DMA_Descriptor_Init(&writeDesr1, &SDIO_HOST_Write_DMA_Write_DMA_Desc_config); + + /*Configure channel*/ + /*write channel cannot be preempted, and has highest priority*/ + writeChannelConfig.descriptor = &writeDesr0; + writeChannelConfig.preemptable = 0; + writeChannelConfig.priority = 0; + writeChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL, &writeChannelConfig); + + /*Enable the interrupt*/ + Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Write_DMA_HW); + + /*Set the source address*/ + SDIO_HOST_Read_DMA_Read_DMA_Desc_config.srcAddress = (void*)SDIO_DAT_READ_PTR; + /*Initialize descriptor for read channel*/ + Cy_DMA_Descriptor_Init(&readDesr0, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); + Cy_DMA_Descriptor_Init(&readDesr1, &SDIO_HOST_Read_DMA_Read_DMA_Desc_config); + + /*Configure channel*/ + /*read channel cannot be preempted, and has highest priority*/ + readChannelConfig.descriptor = &readDesr0; + readChannelConfig.preemptable = 0; + readChannelConfig.priority = 0; + readChannelConfig.enable = 0u; + + /*Configure Channel with initial Settings*/ + Cy_DMA_Channel_Init(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL, &readChannelConfig); + + /*Enable the interrupt*/ + Cy_DMA_Channel_SetInterruptMask(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL,CY_DMA_INTR_MASK); + + /*Enable DMA block*/ + Cy_DMA_Enable(SDIO_HOST_Read_DMA_HW); +} + + +/******************************************************************************* +* Function Name: SDIO_Reset +****************************************************************************//** +* +* Reset the SDIO interface +* +*******************************************************************************/ +void SDIO_Reset(void) +{ + /*Control register is in pulse mode, so this just pulses the reset*/ + SDIO_CONTROL_REG |= (SDIO_CTRL_RESET_DP); +} + + +/******************************************************************************* +* Function Name: SDIO_EnableChipInt +****************************************************************************//** +* +* Enables the SDIO Chip Int by setting the mask bit +* +*******************************************************************************/ +void SDIO_EnableChipInt(void) +{ + SDIO_STATUS_INT_MSK |= SDIO_STS_CARD_INT; +} + + +/******************************************************************************* +* Function Name: SDIO_DisableChipInt +****************************************************************************//** +* +* Enables the SDIO Chip Int by setting the mask bit +* +*******************************************************************************/ +void SDIO_DisableChipInt(void) +{ + SDIO_STATUS_INT_MSK &= ~SDIO_STS_CARD_INT; +} + + +/******************************************************************************* +* Function Name: SDIO_IRQ +****************************************************************************//** +* +* SDIO interrupt, checks for events, and calls callbacks +* +*******************************************************************************/ +void SDIO_IRQ(void) +{ + uint8_t u8Status; + + /* First read the status register */ + u8Status = SDIO_STATUS_REG; + + /* Check card interrupt */ + if (u8Status & SDIO_STS_CARD_INT ) + { + pfnCardInt_count++; + } + + /* Execute card interrupt callback if neccesary */ + if (0 != pfnCardInt_count) + { + if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) + { + gstcInternalData.pstcCallBacks.pfnCardIntCb(); + } + pfnCardInt_count--; + } + + /* If the command is complete set the flag */ + if (u8Status & SDIO_STS_CMD_DONE) + { + gstcInternalData.stcEvents.u8CmdComplete++; + } + + /* Check if a write is complete */ + if (u8Status & SDIO_STS_WRITE_DONE ) + { + + /* Clear the Write flag and CMD53 flag */ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT); + + /* Check if the CRC status return was bad */ + if (u8Status & SDIO_STS_CRC_ERR) + { + /* CRC was bad, set the flag */ + gstcInternalData.stcEvents.u8CRCError++; + } + + /* Set the done flag */ + + #ifdef CY_RTOS_AWARE + cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); + #else + gstcInternalData.stcEvents.u8TransComplete++; + #endif + } + + /* Check if a read is complete */ + if (u8Status & SDIO_STS_READ_DONE) + { + /* Clear the read flag */ + SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT); + + /* Check the CRC */ + if (u8Status & SDIO_STS_CRC_ERR) + { + /* CRC was bad, set the flag */ + gstcInternalData.stcEvents.u8CRCError++; + } + /* Okay we're done so set the done flag */ + #ifdef CY_RTOS_AWARE + cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true ); + #else + gstcInternalData.stcEvents.u8TransComplete++; + #endif + } + + NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER); +} + + +void SDIO_READ_DMA_IRQ(void) +{ + /*Shouldn't have to change anything unless it is the last descriptor*/ + + /*If the current descriptor is 0, then change descriptor 1*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr0) + { + /*We need to increment the destination address every time*/ + readDesr1.dst += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + readDesr1.nextPtr = 0; + readDesr1.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + readDesr1.nextPtr = 0; + readDesr1.ctl |= 0x01000000; + /*Also change the yCount*/ + readDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + } + + /*If the current descriptor is 1, then change descriptor 0*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL) == &readDesr1) + { + /*We need to increment the destination address everytime*/ + readDesr0.dst += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + readDesr0.nextPtr = 0; + readDesr0.ctl |= 0x01000000; + /*Also change the yCount*/ + readDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder-1)) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Read_Int_INTC_NUMBER); + } + } + + /*Clear the interrupt*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Read_DMA_HW, SDIO_HOST_Read_DMA_DW_CHANNEL); + /*decrement y counts*/ + yCounts--; +} + +void SDIO_WRITE_DMA_IRQ(void) +{ + /*We shouldn't have to change anything unless it is the last descriptor*/ + + /*If the current descriptor is 0, then change descriptor 1*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr0) + { + /*We also need to increment the destination address every-time*/ + writeDesr1.src += 2048; + + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + writeDesr1.nextPtr = 0; + writeDesr1.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + writeDesr1.nextPtr = 0; + writeDesr1.ctl |= 0x01000000; + /*Also change the yCount*/ + writeDesr1.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + } + + /*If the current descriptor is 1, then change descriptor 0*/ + if (Cy_DMA_Channel_GetCurrentDescriptor(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL) == &writeDesr1) + { + /*We also need to increment the destination address*/ + writeDesr0.src += 2048; + /*If this is the last descriptor*/ + if ((yCounts == 1) && (yCountRemainder == 0)) + { + /* In this case all we need to change is the next descriptor and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + else if (yCounts == 0 && (yCountRemainder > 0)) + { + /*change next descriptor, and disable*/ + writeDesr0.nextPtr = 0; + writeDesr0.ctl |= 0x01000000; + /*Also change the yCount*/ + writeDesr0.yCtl = _VAL2FLD(CY_DMA_CTL_COUNT, (yCountRemainder -1)) | + _VAL2FLD(CY_DMA_CTL_SRC_INCR, 2); + NVIC_DisableIRQ((IRQn_Type) SDIO_HOST_Write_Int_INTC_NUMBER); + } + } + + /*Clear the interrupt*/ + Cy_DMA_Channel_ClearInterrupt(SDIO_HOST_Write_DMA_HW, SDIO_HOST_Write_DMA_DW_CHANNEL); + yCounts--; +} + +void SDIO_Free(void) +{ +#ifdef CY_RTOS_AWARE + cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); +#endif +} + +/******************************************************************************* +* Function Name: SDIO_SaveConfig +******************************************************************************** +* +* Saves the user configuration of the SDIO UDB non-retention registers. Call the +* SDIO_SaveConfig() function before the Cy_SysPm_CpuEnterDeepSleep() function. +* +*******************************************************************************/ +static void SDIO_SaveConfig(void) +{ + regs.CY_SDIO_UDB_WRKMULT_CTL_0 = UDB->WRKMULT.CTL[0]; + regs.CY_SDIO_UDB_WRKMULT_CTL_1 = UDB->WRKMULT.CTL[1]; + regs.CY_SDIO_UDB_WRKMULT_CTL_2 = UDB->WRKMULT.CTL[2]; + regs.CY_SDIO_UDB_WRKMULT_CTL_3 = UDB->WRKMULT.CTL[3]; +} + + +/******************************************************************************* +* Function Name: SDIO_RestoreConfig +******************************************************************************** +* +* Restores the user configuration of the SDIO UDB non-retention registers. Call +* the SDIO_Wakeup() function after the Cy_SysPm_CpuEnterDeepSleep() function. +* +*******************************************************************************/ +static void SDIO_RestoreConfig(void) +{ + UDB->WRKMULT.CTL[0] = regs.CY_SDIO_UDB_WRKMULT_CTL_0; + UDB->WRKMULT.CTL[1] = regs.CY_SDIO_UDB_WRKMULT_CTL_1; + UDB->WRKMULT.CTL[2] = regs.CY_SDIO_UDB_WRKMULT_CTL_2; + UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3; +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h new file mode 100644 index 00000000000..05fff02eda6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h @@ -0,0 +1,415 @@ +/***************************************************************************//** +* \file SDIO_HOST.h +* +* \brief +* This file provides types definition, constants and function definition for +* the SDIO driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +******************************************************************************* +* \addtogroup group_udb_sdio_changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+*******************************************************************************/ + +/** +* \defgroup group_udb_sdio UDB_SDIO +* \{ +* SDIO - Secure Digital Input Output Is a standard for communicating with various + external devices such as Wifi and bluetooth devices. +* \{ +* \defgroup group_udb_sdio_general_description General Description +* \defgroup group_udb_sdio_changelog Changelog +* \} +* \defgroup group_udb_sdio_API API Reference +* \{ +* \defgroup group_udb_sdio_macros Macros +* \defgroup group_udb_sdio_functions Functions +* \defgroup group_udb_sdio_data_structures Data Structures +* \} +*/ + +/** +* \addtogroup group_udb_sdio_general_description +* \section group_udb_sdio_section_overview Overview +* This driver is currently designed to only support communication with certain +* Broadcom Wifi and Bluetooth chipsets, it is not designed to work with a general +* SDIO card, or even and SD card. Consult TDU#315 for information on limitations +* +* \section group_udb_sdio_section_configuration_considerations Configuration Considerations +* Features: +* * Always Four Wire Mode +* * Supports Card Interrupt +* * Uses DMA for command and data transfer +** +* \section group_udb_sdio_section_more_information More Information +* +* \} group_udb_sdio_general_description +*/ + +#if !defined(CY_SDIO_H) +#define CY_SDIO_H + +#include "SDIO_HOST_cfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* API Constants +***************************************/ + +/** +* \addtogroup group_udb_sdio_macros +* \{ +*/ + +#define SDIO_CMD_TIMEOUT (100000u) /**< Value used for firmware timeout*/ +#define SDIO_DAT_TIMEOUT (500000u) /**< Value used for firmware timeout*/ +#define SDIO_SRC_CLK_FREQ_HZ (10000000u) /**< Frequency of CLK_PERI*/ +#define SDIO_ENABLE_CNT (0x20u) /**< Bit to set in Aux Ctrl reg to enable 7 bit counters.*/ + +/*! +\defgroup group_sdio_cmd_constants Constants for the command channel +*/ +/* @{*/ +#define SDIO_HOST_DIR (0x40u) /**< Direction bit set in command */ +#define SDIO_CMD_END_BIT (0x01u) /**< End bit set in command*/ +#define SDIO_NUM_CMD_BYTES (6u) /**< Number of command bytes to send*/ +#define SDIO_NUM_RESP_BYTES (6u) /**< Number of response bytes to receive*/ +/*@} group_sdio_cmd_constants */ + +/*! +\defgroup group_sdio_ctrl_reg SDIO control register bits +*/ +/* @{*/ +#define SDIO_CTRL_INT_CLK (0x01u) /**< Enable the internal clock running the SDIO block*/ +#define SDIO_CTRL_SD_CLK (0x02u) /**< Enable the the SD Clock*/ +#define SDIO_CTRL_ENABLE_WRITE (0x04u) /**< Enable a write, should not be set if ENABLE_READ is set*/ +#define SDIO_CTRL_ENABLE_READ (0x08u) /**< Enable a read, should not be set if ENABLE_WRITE is set*/ +#define SDIO_CTRL_SKIP_RESPONSE (0x10u) /**< If set no response is required for the command*/ +#define SDIO_CTRL_RESET (0x20u) /**< If set the SDIO interface is reset*/ +#define SDIO_CTRL_RESET_DP (0x40u) /**< If set the SDIO interface is reset*/ +#define SDIO_CTRL_ENABLE_INT (0x80u) /**< Enables logic to detect card interrupt*/ +/*@} group_sdio_ctrl_reg */ + +/*! +\defgroup group_sdio_status_reg SDIO status register bits +*/ +/* @{*/ +#define SDIO_STS_CMD_DONE (0x01u) /**< The command is done*/ +#define SDIO_STS_WRITE_DONE (0x02u) /**< All data for a write has been sent*/ +#define SDIO_STS_READ_DONE (0x04u) /**< All data for a read has been read*/ +#define SDIO_STS_CRC_ERR (0x08u) /**< A CRC error was detected during a read or write*/ +#define SDIO_STS_CMD_IDLE (0x10u) /**< The command channel is idle*/ +#define SDIO_STS_DAT_IDLE (0x20u) /**< The data channel is idle*/ +#define SDIO_STS_CARD_INT (0x40u) /**< The SDIO card indicated an interrupt by driving DAT[1] low*/ +/*@} group_sdio_status_reg */ + +/*! +\defgroup group_sdio_crc Constants for 7bit CRC for command +*/ +/* @{*/ +#define SDIO_CRC7_POLY (0x12u) /**< Value of CRC polynomial*/ +#define SDIO_CRC_UPPER_BIT (0x80u) /**< Upper bit to test if it is high*/ +/*@} group_sdio_crc */ + +/** \} group_udb_sdio_macros */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_udb_sdio_data_structures +* \{ +*/ + +/** +* Create a type for the card interrupt call back +*/ +typedef void (* sdio_card_int_cb_t)(void); + +/** +* \brief This enum is used when checking for specific events +*/ +typedef enum en_sdio_event +{ + SdCmdEventCmdDone = (1u), /**< Check to see if a command is done*/ + SdCmdEventTransferDone = (2u) /**< Check to see if a transfer is done*/ + +}en_sdio_event_t; + +/** +* \brief Used to indicate the result of a function +*/ +typedef enum en_sdio_result +{ + Ok = 0x00, /**< No error*/ + Error = 0x01, /**< Non-specific error code*/ + CommandCrcError = 0x02, /**< There was a CRC error on the Command/Response*/ + CommandIdxError = 0x04, /**< The index for the command didn't match*/ + CommandEndError = 0x08, /**< There was an end bit error on the command*/ + DataCrcError = 0x10, /**< There was a data CRC Error*/ + CMDTimeout = 0x20, /**< The command didn't finish before the timeout period was over*/ + DataTimeout = 0x40, /**< The data didn't finish before the timeout period was over*/ + ResponseFlagError = 0x80 /**< There was an error in the response flag for command 53*/ + +} en_sdio_result_t; + +/** +* \brief Flags used to indicate an event occurred, set in the interrupt, cleared in the check events function +*/ +typedef struct stc_sdcmd_event_flag +{ + uint8_t u8CmdComplete; /**< If non-zero a command has completed*/ + uint8_t u8TransComplete; /**< If non-zero a transfer has completed*/ + uint8_t u8CRCError; /**< If non-zero a CRC error was detected in a data transfer*/ + +}stc_sdio_event_flag_t; + +/** +* \brief Holds pointers to callback functions +*/ +typedef struct stc_sdio_irq_cb +{ + sdio_card_int_cb_t pfnCardIntCb; /**< Pointer to card interrupt callback function*/ +}stc_sdio_irq_cb_t; + +/** +* \brief Global structure used to hold data from interrupt and other functions +*/ +typedef struct stc_sdio_gInternalData +{ + stc_sdio_irq_cb_t pstcCallBacks; /**< Holds pointers to all the call back functions*/ + stc_sdio_event_flag_t stcEvents; /**< Holds all of the event count flags, set in interrupt used in check events*/ +}stc_sdio_gInternalData_t; + +/** +* \brief structure used for configuring command +*/ +typedef struct stc_sdio_cmd_config +{ + uint8_t u8CmdIndex; /**< Command index*/ + uint32_t u32Argument; /**< The argument of command */ + uint8_t bResponseRequired; /**< TRUE: A Response is required*/ + uint8_t *pu8ResponseBuf; /**< Pointer to location to store response*/ + +}stc_sdio_cmd_config_t; + +/** +* \brief structure used for the data channel +*/ +typedef struct stc_sdio_data_config +{ + uint8_t bRead; /**< TRUE: Read, FALSE: write*/ + uint16_t u16BlockSize; /**< Block size*/ + uint16_t u16BlockCount; /**< Holds the number of blocks to send*/ + uint8_t *pu8Data; /**< Pointer data buffer*/ + +}stc_sdio_data_config_t; + +/** +* \brief structure used for configuring command and data +*/ +typedef struct stc_sdio_cmd +{ + uint32_t u32CmdIdx; /**< Command index*/ + uint32_t u32Arg; /**< The argument of command*/ + uint32_t *pu32Response; /**< Pointer to location to store response*/ + uint8_t *pu8Data; /**< Pointer data buffer*/ + uint8_t bRead; /**< TRUE: Read, FALSE: write*/ + uint16_t u16BlockCnt; /**< Number of blocks to send*/ + uint16_t u16BlockSize; /**< Block size*/ +}stc_sdio_cmd_t; + +/** \} group_udb_sdio_data_structures */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_udb_sdio_functions +* \{ +*/ + +/** \cond INTERNAL */ + +/* Main functions*/ +void SDIO_Init(stc_sdio_irq_cb_t* pfuCb); +en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd); +void SDIO_EnableIntClock(void); +void SDIO_DisableIntClock(void); +void SDIO_EnableSdClk(void); +void SDIO_DisableSdClk(void); +void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz); +void SDIO_Reset(void); +void SDIO_EnableChipInt(void); +void SDIO_DisableChipInt(void); +void SDIO_Free(void); + +/*Low Level Functions*/ +void SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig); +en_sdio_result_t SDIO_GetResponse(uint8_t bCmdIndexCheck, uint8_t bCmdCrcCheck, uint8_t u8CmdIdx, uint32_t* pu32Response, uint8_t* pu8ResponseBuf); +void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig); +en_sdio_result_t SDIO_CheckForEvent(en_sdio_event_t enEventType); +uint8_t SDIO_CalculateCrc7(uint8_t* pu8Data, uint8_t pu8Size); +void SDIO_SetBlockSize(uint8_t u8ByteCount); +void SDIO_SetNumBlocks(uint8_t u8BlockCount); +en_sdio_result_t SDIO_CheckReadCRC(void); + +/*DMA setup function*/ +void SDIO_SetupDMA(void); + +/*Interrupt Function*/ +void SDIO_IRQ(void); +void SDIO_READ_DMA_IRQ(void); +void SDIO_WRITE_DMA_IRQ(void); + +void SDIO_Crc7Init(void); + +cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode); + +/** \endcond */ + +/** \} group_udb_sdio_functions */ + + +/*************************************** +* Hardware Registers +***************************************/ + +/** \cond INTERNAL */ + +#define SDIO_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) + +#define SDIO_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG) + +#define SDIO_STATUS_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_REG) + +#define SDIO_STATUS_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_REG) + +#define SDIO_STATUS_INT_MSK (* (reg8*) \ +SDIO_HOST_bSDIO_StatusReg__MASK_REG) + +#define SDIO_STATUS_AUX_CTL (* (reg8 *) \ +SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG) + +#define SDIO_CMD_BIT_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CMD_BIT_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_WRITE_CRC_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_WRITE_CRC_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_BYTE_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_BYTE_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CRC_BIT_CNT_CONTROL_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_CRC_BIT_CNT_CONTROL_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A0_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D0_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D0_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A1_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_A1_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__A1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D1_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) + +#define SDIO_DATA_BLOCK_COUNTER_D1_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_blockCounter_u0__D1_REG) + +#define SDIO_CMD_COMMAND_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F0_REG) + +#define SDIO_CMD_COMMAND_A0_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__A0_REG) + +#define SDIO_CMD_COMMAND_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F0_REG) + +#define SDIO_CMD_RESPONSE_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F1_REG) + +#define SDIO_CMD_RESPONSE_PTR ( (reg8 *) \ +SDIO_HOST_bSDIO_CMD__F1_REG) + +#define SDIO_DAT_WRITE_REG (* (reg16 *) \ +SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) + +#define SDIO_DAT_WRITE_PTR ( (reg16 *) \ +SDIO_HOST_bSDIO_Write_DP__F0_F1_REG) + +#define SDIO_DAT_READ_REG (* (reg16 *) \ +SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) + +#define SDIO_DAT_READ_PTR ( (reg16 *) \ +SDIO_HOST_bSDIO_Read_DP__F0_F1_REG) + +#define SDIO_BYTE_COUNT_REG (* (reg8 *) \ +SDIO_HOST_bSDIO_byteCounter__PERIOD_REG) + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#endif /* (CY_SDIO_H) */ + +/** \} group_udb_sdio */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c new file mode 100644 index 00000000000..5232ed1701e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -0,0 +1,1037 @@ +/***************************************************************************//** +* \file SDIO_HOST_cfg.c +* +* \brief +* This file provides the configuration of the UDB based SDIO driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "SDIO_HOST_cfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/***************************CMD DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_16CYC, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1L, + .dstXincrement = 0L, + .xCount = 5UL, + .srcYincrement = 0L, + .dstYincrement = 0L, + .yCount = 1UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Read DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0L, + .dstXincrement = 2L, + .xCount = 10UL, + .srcYincrement = 0L, + .dstYincrement = 10L, + .yCount = 2UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Resp DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_1ELEMENT, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 0L, + .dstXincrement = 1L, + .xCount = 6UL, + .srcYincrement = 0L, + .dstYincrement = 0L, + .yCount = 1UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + +/***************************Write DMA Config Struct****************************/ +cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config = +{ + .retrigger = CY_DMA_RETRIG_4CYC, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_DISABLED, + .triggerInType = CY_DMA_X_LOOP, + .dataSize = CY_DMA_HALFWORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_2D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 2L, + .dstXincrement = 0L, + .xCount = 10UL, + .srcYincrement = 10L, + .dstYincrement = 0L, + .yCount = 2UL, + .nextDescriptor = NULL +}; + +cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc = +{ + .ctl = 0UL, + .src = 0UL, + .dst = 0UL, + .xCtl = 0UL, + .yCtl = 0UL, + .nextPtr = 0UL +}; + + + +/***************UDB Config code *****************/ + +#define CY_CFG_BASE_ADDR_COUNT 12u + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + + +#else + #error Unsupported toolchain +#endif + + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYFAR + #define CYFAR +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + +CYPACKED typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED_ATTR cy_cfg_addrvalue_t; + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +static const uint32 CYCODE cy_cfg_addr_table[] = +{ + 0x40340002u, /* Base address: 0x40340000 Count: 2 */ + 0x4034010Au, /* Base address: 0x40340100 Count: 10 */ + 0x40340301u, /* Base address: 0x40340300 Count: 1 */ + 0x40340405u, /* Base address: 0x40340400 Count: 5 */ + 0x4034205Cu, /* Base address: 0x40342000 Count: 92 */ + 0x40342238u, /* Base address: 0x40342200 Count: 56 */ + 0x4034242Cu, /* Base address: 0x40342400 Count: 44 */ + 0x4034262Eu, /* Base address: 0x40342600 Count: 46 */ + 0x40342837u, /* Base address: 0x40342800 Count: 55 */ + 0x40342A29u, /* Base address: 0x40342A00 Count: 41 */ + 0x40347104u, /* Base address: 0x40347100 Count: 4 */ + 0x40347804u, /* Base address: 0x40347800 Count: 4 */ +}; + +static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = +{ +{0x00u, 0xFFu}, + {0x09u, 0x01u}, + {0x09u, 0x01u}, + {0x0Du, 0x02u}, + {0x10u, 0x10u}, + {0x14u, 0x88u}, + {0x18u, 0x10u}, + {0x1Cu, 0x88u}, + {0x20u, 0x10u}, + {0x24u, 0x88u}, + {0x28u, 0x10u}, + {0x2Cu, 0x88u}, + {0x19u, 0x40u}, + {0x10u, 0x07u}, + {0x18u, 0x47u}, + {0x24u, 0x03u}, + {0x28u, 0x0Fu}, + {0x2Cu, 0x2Fu}, + {0x00u, 0x01u}, + {0x0Eu, 0x0Eu}, + {0x10u, 0x08u}, + {0x18u, 0x01u}, + {0x1Au, 0x08u}, + {0x1Cu, 0x01u}, + {0x1Eu, 0x02u}, + {0x22u, 0x01u}, + {0x28u, 0x01u}, + {0x2Au, 0x04u}, + {0x2Eu, 0x01u}, + {0x30u, 0x0Fu}, + {0x3Cu, 0x02u}, + {0x40u, 0x63u}, + {0x41u, 0x04u}, + {0x42u, 0x10u}, + {0x44u, 0x02u}, + {0x45u, 0x0Fu}, + {0x46u, 0xECu}, + {0x47u, 0xB0u}, + {0x48u, 0x2Du}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x02u}, + {0x4Fu, 0x0Cu}, + {0x50u, 0x08u}, + {0x51u, 0x10u}, + {0x5Cu, 0x0Cu}, + {0x5Eu, 0x0Cu}, + {0x63u, 0x09u}, + {0x65u, 0x08u}, + {0x68u, 0xC0u}, + {0x6Cu, 0x10u}, + {0x6Du, 0x11u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x01u}, + {0x71u, 0x10u}, + {0x72u, 0x50u}, + {0x73u, 0xA8u}, + {0x81u, 0x01u}, + {0x83u, 0x02u}, + {0x85u, 0x02u}, + {0x89u, 0x02u}, + {0x8Du, 0x02u}, + {0x91u, 0x30u}, + {0x93u, 0x04u}, + {0x95u, 0x06u}, + {0x97u, 0x38u}, + {0x99u, 0x20u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x10u}, + {0x9Du, 0x06u}, + {0x9Fu, 0x38u}, + {0xA3u, 0x02u}, + {0xA5u, 0x02u}, + {0xA6u, 0x01u}, + {0xABu, 0x01u}, + {0xB1u, 0x01u}, + {0xB2u, 0x01u}, + {0xB3u, 0x20u}, + {0xB5u, 0x10u}, + {0xB7u, 0x0Eu}, + {0xBDu, 0x80u}, + {0xBEu, 0x04u}, + {0xBFu, 0x14u}, + {0xC0u, 0x54u}, + {0xC1u, 0x06u}, + {0xC2u, 0x32u}, + {0xC6u, 0xF0u}, + {0xC7u, 0x0Eu}, + {0xC8u, 0x18u}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCFu, 0x2Fu}, + {0xD0u, 0x08u}, + {0xD1u, 0x10u}, + {0xDCu, 0x04u}, + {0xDDu, 0x0Cu}, + {0xDEu, 0x0Cu}, + {0xDFu, 0x04u}, + {0xE3u, 0x09u}, + {0xE4u, 0x50u}, + {0xE5u, 0xA8u}, + {0xE6u, 0x08u}, + {0xE7u, 0x03u}, + {0xE8u, 0x08u}, + {0xEAu, 0x18u}, + {0xEBu, 0x03u}, + {0xF0u, 0x58u}, + {0xF1u, 0xECu}, + {0x00u, 0x18u}, + {0x01u, 0x15u}, + {0x03u, 0x20u}, + {0x04u, 0x43u}, + {0x06u, 0x34u}, + {0x07u, 0x35u}, + {0x08u, 0x40u}, + {0x0Cu, 0x5Au}, + {0x0Eu, 0x25u}, + {0x0Fu, 0x4Au}, + {0x11u, 0x20u}, + {0x13u, 0x15u}, + {0x14u, 0x40u}, + {0x15u, 0x40u}, + {0x17u, 0x0Au}, + {0x18u, 0x20u}, + {0x19u, 0x10u}, + {0x1Bu, 0x25u}, + {0x1Cu, 0x40u}, + {0x1Du, 0x0Au}, + {0x1Fu, 0x40u}, + {0x20u, 0x20u}, + {0x21u, 0x0Cu}, + {0x23u, 0x03u}, + {0x24u, 0x40u}, + {0x2Au, 0x20u}, + {0x2Cu, 0x45u}, + {0x2Eu, 0x3Au}, + {0x30u, 0x40u}, + {0x32u, 0x0Eu}, + {0x33u, 0x70u}, + {0x34u, 0x01u}, + {0x35u, 0x0Cu}, + {0x36u, 0x31u}, + {0x37u, 0x03u}, + {0x3Au, 0xA8u}, + {0x3Cu, 0xA8u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x54u}, + {0x40u, 0x42u}, + {0x41u, 0x05u}, + {0x45u, 0x20u}, + {0x46u, 0x06u}, + {0x48u, 0x06u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Du, 0xA0u}, + {0x5Cu, 0x0Cu}, + {0x5Du, 0x04u}, + {0x5Eu, 0x0Cu}, + {0x63u, 0x09u}, + {0x66u, 0x40u}, + {0x67u, 0x40u}, + {0x68u, 0x10u}, + {0x69u, 0x50u}, + {0x02u, 0x60u}, + {0x08u, 0x87u}, + {0x0Au, 0x78u}, + {0x0Eu, 0x08u}, + {0x12u, 0x21u}, + {0x14u, 0x04u}, + {0x18u, 0xB9u}, + {0x1Au, 0x06u}, + {0x1Cu, 0x89u}, + {0x1Eu, 0x72u}, + {0x20u, 0x04u}, + {0x24u, 0x8Eu}, + {0x26u, 0x51u}, + {0x2Au, 0x04u}, + {0x2Eu, 0x01u}, + {0x30u, 0x80u}, + {0x34u, 0x7Fu}, + {0x3Au, 0x20u}, + {0x3Cu, 0x20u}, + {0x3Eu, 0x01u}, + {0x40u, 0x43u}, + {0x41u, 0x02u}, + {0x44u, 0x01u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x12u}, + {0x4Du, 0x5Cu}, + {0x4Eu, 0x78u}, + {0x57u, 0x02u}, + {0x58u, 0x77u}, + {0x5Cu, 0x0Cu}, + {0x5Eu, 0x0Cu}, + {0x5Fu, 0x0Cu}, + {0x62u, 0x08u}, + {0x63u, 0x09u}, + {0x64u, 0x50u}, + {0x65u, 0xA8u}, + {0x69u, 0x1Cu}, + {0x6Au, 0x58u}, + {0x6Bu, 0xA1u}, + {0x6Du, 0x10u}, + {0x70u, 0x10u}, + {0x71u, 0x1Du}, + {0x80u, 0x40u}, + {0x84u, 0x8Eu}, + {0x86u, 0x71u}, + {0x88u, 0x40u}, + {0x8Eu, 0x21u}, + {0x90u, 0x40u}, + {0x92u, 0x02u}, + {0x96u, 0x18u}, + {0x98u, 0x03u}, + {0x9Au, 0x04u}, + {0x9Cu, 0xCCu}, + {0x9Eu, 0x33u}, + {0xA0u, 0x08u}, + {0xA4u, 0x40u}, + {0xA8u, 0x46u}, + {0xAAu, 0xB1u}, + {0xACu, 0x10u}, + {0xAEu, 0x08u}, + {0xB2u, 0xF8u}, + {0xB4u, 0x07u}, + {0xB6u, 0x07u}, + {0xBAu, 0xA8u}, + {0xBCu, 0xA8u}, + {0xC0u, 0x43u}, + {0xC1u, 0x02u}, + {0xC4u, 0x01u}, + {0xC5u, 0x40u}, + {0xC6u, 0xB0u}, + {0xC8u, 0x0Au}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x13u}, + {0xCDu, 0x5Cu}, + {0xCEu, 0x77u}, + {0xDCu, 0x0Cu}, + {0xDEu, 0x0Cu}, + {0xE3u, 0x09u}, + {0xE4u, 0x50u}, + {0xE5u, 0xA8u}, + {0xE9u, 0x1Cu}, + {0xEAu, 0x58u}, + {0xEBu, 0xA1u}, + {0xEDu, 0x10u}, + {0xF0u, 0x10u}, + {0xF1u, 0x1Du}, + {0x00u, 0x40u}, + {0x01u, 0x14u}, + {0x03u, 0x20u}, + {0x04u, 0x33u}, + {0x05u, 0x3Cu}, + {0x06u, 0x44u}, + {0x08u, 0x97u}, + {0x09u, 0x3Cu}, + {0x0Au, 0x48u}, + {0x0Du, 0x01u}, + {0x11u, 0x03u}, + {0x12u, 0x91u}, + {0x15u, 0x03u}, + {0x16u, 0x08u}, + {0x1Bu, 0x03u}, + {0x1Cu, 0x13u}, + {0x1Eu, 0xECu}, + {0x1Fu, 0x03u}, + {0x20u, 0xADu}, + {0x21u, 0x04u}, + {0x22u, 0x52u}, + {0x27u, 0x2Cu}, + {0x29u, 0x02u}, + {0x2Eu, 0x12u}, + {0x2Fu, 0x04u}, + {0x30u, 0x07u}, + {0x31u, 0x18u}, + {0x33u, 0x07u}, + {0x34u, 0xF8u}, + {0x35u, 0x20u}, + {0x39u, 0x02u}, + {0x3Au, 0x22u}, + {0x3Cu, 0x22u}, + {0x3Fu, 0x15u}, + {0x40u, 0x43u}, + {0x41u, 0x02u}, + {0x44u, 0x06u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x12u}, + {0x4Du, 0x5Cu}, + {0x4Eu, 0x78u}, + {0x5Cu, 0x0Cu}, + {0x5Du, 0x04u}, + {0x5Eu, 0x0Cu}, + {0x63u, 0x09u}, + {0x64u, 0x50u}, + {0x65u, 0xA8u}, + {0x69u, 0x1Cu}, + {0x6Au, 0x58u}, + {0x6Bu, 0xA1u}, + {0x6Du, 0x10u}, + {0x70u, 0x10u}, + {0x71u, 0x1Du}, + {0x01u, 0x20u}, + {0x0Bu, 0x40u}, + {0x0Du, 0x10u}, + {0x11u, 0x32u}, + {0x13u, 0x09u}, + {0x15u, 0x0Au}, + {0x17u, 0x31u}, + {0x23u, 0x34u}, + {0x29u, 0x33u}, + {0x2Bu, 0x08u}, + {0x2Du, 0x0Cu}, + {0x31u, 0x0Cu}, + {0x33u, 0x01u}, + {0x35u, 0x02u}, + {0x37u, 0x70u}, + {0x39u, 0x02u}, + {0x3Fu, 0x55u}, + {0x40u, 0x16u}, + {0x41u, 0x02u}, + {0x44u, 0x04u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x12u}, + {0x4Du, 0x5Cu}, + {0x4Eu, 0x78u}, + {0x57u, 0x02u}, + {0x58u, 0x76u}, + {0x5Du, 0x04u}, + {0x5Eu, 0x0Cu}, + {0x5Fu, 0x0Cu}, + {0x62u, 0x08u}, + {0x63u, 0x09u}, + {0x64u, 0x50u}, + {0x65u, 0xA8u}, + {0x69u, 0x1Cu}, + {0x6Au, 0x58u}, + {0x6Bu, 0xA1u}, + {0x6Du, 0x10u}, + {0x70u, 0x10u}, + {0x71u, 0x1Du}, + {0xE8u, 0x63u}, + {0xECu, 0x53u}, + {0xF0u, 0x54u}, + {0xF4u, 0x01u}, + {0x00u, 0x01u}, + {0x10u, 0x01u}, + {0x14u, 0x01u}, + {0x18u, 0x01u}, +}; + + + +CYPACKED typedef struct +{ +void *address; +uint16 size; +} CYPACKED_ATTR cfg_memset_t; + + +CYPACKED typedef struct +{ + void *dest; + const void *src; + size_t size; +} CYPACKED_ATTR cfg_memcpy_t; + +static const cfg_memset_t CYCODE cfg_memset_list[] = +{ + /* address, size */ + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE), 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE), 116u}, +}; + +/* UDB_UDBPAIR5_UDBSNG1 Address: CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR5_UDBSNG1_VAL[] = { + 0x08u, 0x00u, 0x00u, 0x00u, 0x42u, 0x00u, 0x2Du, 0x00u, 0x08u, 0x24u, 0x00u, 0x00u, 0x22u, 0x24u, 0x45u, 0x00u, + 0x00u, 0x10u, 0x10u, 0x08u, 0x00u, 0x70u, 0x00u, 0x83u, 0x08u, 0x24u, 0x00u, 0x00u, 0x00u, 0x4Eu, 0x00u, 0xB0u, + 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x8Fu, 0x3Cu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, + 0x00u, 0xC0u, 0x00u, 0x1Fu, 0x60u, 0x00u, 0x1Fu, 0x20u, 0x80u, 0x00u, 0x00u, 0x00u, 0x80u, 0x08u, 0x10u, 0x41u, + 0x46u, 0x02u, 0x00u, 0x00u, 0x05u, 0x00u, 0x04u, 0x0Bu, 0x14u, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u}; + +/* UDB_UDBPAIR1_UDBSNG1 Address: CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR1_UDBSNG1_VAL[] = { + 0x08u, 0x0Au, 0x00u, 0xD0u, 0x02u, 0xB9u, 0x00u, 0x42u, 0x2Bu, 0x02u, 0x00u, 0x00u, 0x2Bu, 0x00u, 0x54u, 0x80u, + 0x2Au, 0x00u, 0x01u, 0x20u, 0x40u, 0x33u, 0x00u, 0xCCu, 0x04u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0xA0u, + 0x2Au, 0x00u, 0x00u, 0x00u, 0x01u, 0x8Au, 0x2Au, 0x71u, 0x20u, 0x7Bu, 0x00u, 0x80u, 0x00u, 0x04u, 0x00u, 0x00u, + 0x19u, 0xF8u, 0x07u, 0xF8u, 0x00u, 0x00u, 0x61u, 0x07u, 0x8Au, 0x80u, 0x00u, 0x0Au, 0x00u, 0x0Au, 0x45u, 0x40u, + 0x52u, 0x06u, 0x00u, 0x00u, 0x04u, 0x4Cu, 0x0Eu, 0x00u, 0x07u, 0xFFu, 0xFFu, 0x0Eu, 0x82u, 0x20u, 0x00u, 0x00u, + 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x0Cu, 0x0Cu, 0x04u, + 0x00u, 0x00u, 0x00u, 0x09u, 0x40u, 0x09u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x10u, 0x00u, 0x13u, 0x10u, 0x13u, + 0x40u, 0x03u, 0x00u, 0x10u}; + +/* UDB_UDBPAIR4_UDBSNG1 Address: CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR4_UDBSNG1_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x00u, 0x19u, 0x00u, 0x12u, 0x00u, 0x2Du, 0x00u, 0x04u, 0x00u, 0x00u, 0x11u, + 0x02u, 0x08u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x05u, 0x00u, 0x03u, 0x10u, 0x08u, + 0x15u, 0x00u, 0x2Au, 0x10u, 0x00u, 0x00u, 0x04u, 0x00u, 0x0Eu, 0x0Fu, 0x31u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x07u, 0x00u, 0x10u, 0x3Fu, 0x00u, 0x3Fu, 0x0Cu, 0x00u, 0x00u, 0xA0u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x04u, + 0x43u, 0x02u, 0x00u, 0x00u, 0x06u, 0x40u, 0xB0u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x74u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x08u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u}; + +/* UDB_UDBPAIR3_UDBSNG0 Address: CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR3_UDBSNG0_VAL[] = { + 0x3Cu, 0x00u, 0x00u, 0xC0u, 0x00u, 0x80u, 0x10u, 0x40u, 0x0Cu, 0x80u, 0x60u, 0x40u, 0x02u, 0x10u, 0x00u, 0x25u, + 0x04u, 0x80u, 0x08u, 0x40u, 0x00u, 0x19u, 0x10u, 0x22u, 0x04u, 0x00u, 0x0Bu, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x80u, + 0x10u, 0x00u, 0x00u, 0x24u, 0x00u, 0x40u, 0x00u, 0x80u, 0x7Cu, 0x25u, 0x00u, 0x1Au, 0x00u, 0x08u, 0x10u, 0x80u, + 0x01u, 0xC0u, 0x02u, 0x00u, 0x70u, 0x07u, 0x0Cu, 0x38u, 0x00u, 0x00u, 0x80u, 0x82u, 0x00u, 0xA2u, 0x04u, 0x00u, + 0x43u, 0x02u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0x12u, 0x5Cu, 0x78u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xDEu, 0x40u, 0x4Bu, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x0Cu, + 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u}; + +/* UDB_UDBPAIR2_UDBSNG1 Address: CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE Size (bytes): 116 */ +static const uint8 CYCODE BS_UDB_UDBPAIR2_UDBSNG1_VAL[] = { + 0x00u, 0x00u, 0x80u, 0x03u, 0x00u, 0xC9u, 0x00u, 0x12u, 0x00u, 0x00u, 0x00u, 0x01u, 0x70u, 0x01u, 0x00u, 0x80u, + 0x40u, 0x00u, 0x00u, 0x40u, 0x40u, 0xB3u, 0xAAu, 0x4Cu, 0xEAu, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x15u, 0x40u, + 0x40u, 0xB1u, 0xAAu, 0x04u, 0x43u, 0x00u, 0x00u, 0x01u, 0x4Cu, 0x05u, 0x00u, 0xBAu, 0x00u, 0x20u, 0x40u, 0x80u, + 0x03u, 0x7Fu, 0xC0u, 0x80u, 0x0Cu, 0x7Fu, 0x30u, 0x00u, 0xA2u, 0x00u, 0x08u, 0x22u, 0x08u, 0x22u, 0x51u, 0x04u, + 0x43u, 0x02u, 0x00u, 0x00u, 0x05u, 0xB0u, 0x40u, 0x00u, 0x0Au, 0xFFu, 0xFFu, 0xFFu, 0x13u, 0x5Cu, 0x77u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x00u, + 0x00u, 0x00u, 0x00u, 0x09u, 0x50u, 0xA8u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x58u, 0xA1u, 0x00u, 0x10u, 0x00u, 0x00u, + 0x10u, 0x1Du, 0x00u, 0x00u}; + +/* UDB_UDBPAIR0_ROUTE Address: CYDEV_UDB_UDBPAIR0_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR0_ROUTE_VAL[] = { + 0x14u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF5u, 0x7Fu, 0xF3u, 0x11u, + 0xF3u, 0x11u, 0xFFu, 0xF2u, 0xFFu, 0x2Fu, 0xFFu, 0xFFu, 0x00u, 0x11u, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xF7u, 0x5Fu, 0xFFu, 0x2Fu, 0x10u, 0x22u, 0x62u, 0x00u, 0x34u, + 0x2Fu, 0x62u, 0x73u, 0x00u, 0x11u, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x0Fu, 0x0Fu, 0x27u, + 0x20u, 0x22u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x10u, 0x11u, 0x40u, 0x1Du, 0x11u, 0x00u, 0xDDu, 0x11u, 0x10u, 0x10u, 0x11u, 0x00u, 0xD1u, 0x63u, 0x03u, 0x01u, + 0x13u, 0x37u, 0x00u, 0x13u, 0x11u, 0x00u, 0x13u, 0x16u, 0x11u, 0x11u, 0x16u, 0x19u, 0x11u, 0x01u, 0x11u, 0x11u, + 0x19u, 0x11u, 0x11u, 0x91u, 0x41u, 0x11u, 0x21u, 0x11u, 0x16u, 0x11u, 0x11u, 0x13u, 0x81u, 0x11u, 0x11u, 0x11u}; + +/* UDB_UDBPAIR1_ROUTE Address: CYDEV_UDB_UDBPAIR1_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR1_ROUTE_VAL[] = { + 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x42u, 0x36u, + 0x26u, 0x33u, 0x35u, 0xF5u, 0xF0u, 0x54u, 0x14u, 0x62u, 0x5Fu, 0x0Fu, 0x04u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x24u, 0x45u, 0x7Fu, 0x50u, 0x26u, 0x64u, 0xFFu, 0x3Fu, 0x32u, 0x42u, 0xF3u, 0x32u, + 0x3Fu, 0x7Fu, 0x37u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x02u, 0x05u, + 0xF6u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x10u, 0x13u, 0xF0u, 0x10u, 0x14u, 0x00u, 0x01u, 0x01u, 0x10u, 0x0Du, 0x63u, 0x00u, 0x70u, 0x10u, 0x08u, 0x30u, + 0x13u, 0x11u, 0x30u, 0x10u, 0x50u, 0x30u, 0x1Fu, 0xC1u, 0x33u, 0x10u, 0x0Fu, 0x01u, 0x31u, 0x0Du, 0x1Cu, 0x25u, + 0x11u, 0x01u, 0x12u, 0xFBu, 0x02u, 0x12u, 0x15u, 0x1Cu, 0x11u, 0x11u, 0x11u, 0x15u, 0x11u, 0x61u, 0x16u, 0x11u}; + +/* UDB_UDBPAIR2_ROUTE Address: CYDEV_UDB_UDBPAIR2_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR2_ROUTE_VAL[] = { + 0x06u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF4u, 0x33u, 0x35u, 0x44u, + 0x77u, 0x57u, 0xF2u, 0xFFu, 0xF4u, 0xFFu, 0x40u, 0xFFu, 0x32u, 0x63u, 0xFFu, 0xFFu, 0x3Fu, 0x5Fu, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0xF4u, 0x1Fu, 0x34u, 0x13u, 0x46u, 0x56u, 0x35u, 0x41u, 0x40u, 0x57u, 0x67u, 0x55u, + 0x3Fu, 0x63u, 0xF6u, 0xFFu, 0x4Fu, 0xFFu, 0xFFu, 0x52u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x00u, 0x00u, + 0x40u, 0x22u, 0x00u, 0xF0u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x10u, 0x11u, 0xF3u, 0x10u, 0x12u, 0x02u, 0x96u, 0x01u, 0x00u, 0x74u, 0xD1u, 0x00u, 0xF7u, 0x03u, 0x03u, 0x16u, + 0x1Fu, 0x31u, 0x10u, 0x00u, 0x03u, 0x10u, 0x41u, 0x35u, 0x10u, 0x16u, 0x0Fu, 0x76u, 0x11u, 0xB0u, 0xD1u, 0xDFu, + 0x09u, 0x00u, 0x0Fu, 0xFBu, 0x01u, 0x11u, 0x17u, 0x11u, 0x11u, 0x15u, 0xD5u, 0x1Du, 0x27u, 0x15u, 0x1Fu, 0x11u}; + +/* UDB_UDBPAIR3_ROUTE Address: CYDEV_UDB_UDBPAIR3_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR3_ROUTE_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, 0x41u, 0x53u, 0x15u, + 0x45u, 0x11u, 0xF4u, 0xF3u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0x33u, 0x63u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x32u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x31u, 0x02u, 0x14u, 0x56u, 0xF1u, 0x77u, 0x77u, 0x37u, 0xF0u, 0x56u, 0x73u, 0x45u, + 0x33u, 0x63u, 0xFFu, 0x03u, 0x15u, 0xF2u, 0xF2u, 0xF2u, 0xF1u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xB0u, 0x00u, 0xF0u, 0x17u, 0x1Fu, 0x02u, 0x1Fu, 0x60u, 0xA3u, 0xF4u, 0x15u, 0xA0u, 0xF1u, 0x0Fu, 0x00u, 0x31u, + 0x0Fu, 0xF3u, 0x3Au, 0x20u, 0x51u, 0x3Au, 0x13u, 0xF3u, 0xC0u, 0x10u, 0x4Au, 0x11u, 0x20u, 0x10u, 0x01u, 0xF1u, + 0x0Fu, 0x00u, 0x0Fu, 0xFFu, 0x41u, 0x11u, 0x41u, 0x4Du, 0x11u, 0x71u, 0x11u, 0x1Fu, 0xFCu, 0x11u, 0x1Fu, 0x1Cu}; + +/* UDB_UDBPAIR4_ROUTE Address: CYDEV_UDB_UDBPAIR4_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR4_ROUTE_VAL[] = { + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x74u, 0xF4u, 0x55u, 0x4Fu, + 0xF3u, 0x5Fu, 0x55u, 0x27u, 0x31u, 0x63u, 0x71u, 0x61u, 0x3Fu, 0x63u, 0x0Fu, 0x5Fu, 0xFFu, 0xFFu, 0xFFu, 0x12u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x64u, 0x31u, 0x70u, 0x77u, 0xF6u, 0x2Fu, 0x1Fu, 0x25u, 0x4Fu, 0xF7u, 0x3Fu, + 0x32u, 0x63u, 0x3Fu, 0x75u, 0xF4u, 0x1Fu, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, + 0x04u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0x70u, 0x30u, 0x26u, 0x14u, 0x2Fu, 0x0Cu, 0xA5u, 0x10u, 0x18u, 0x11u, 0x0Fu, 0xF0u, 0xF7u, 0x3Fu, 0x00u, 0x11u, + 0x0Fu, 0xFFu, 0xF8u, 0x16u, 0xF7u, 0x1Fu, 0x10u, 0x11u, 0xF4u, 0x13u, 0xFFu, 0x67u, 0x13u, 0x15u, 0x07u, 0xF1u, + 0x3Fu, 0xCDu, 0x2Fu, 0x4Fu, 0xF6u, 0x12u, 0x12u, 0x11u, 0x11u, 0x19u, 0x11u, 0x21u, 0xFFu, 0x11u, 0x1Fu, 0x11u}; + +/* UDB_UDBPAIR5_ROUTE Address: CYDEV_UDB_UDBPAIR5_ROUTE_BASE Size (bytes): 144 */ +static const uint8 CYCODE BS_UDB_UDBPAIR5_ROUTE_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x31u, 0x32u, 0xF3u, 0xF4u, + 0xFFu, 0x45u, 0xFFu, 0x43u, 0x12u, 0x35u, 0x33u, 0xFFu, 0x3Fu, 0x5Fu, 0x34u, 0xF0u, 0xFFu, 0x2Fu, 0xFFu, 0x12u, + 0xFFu, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xF3u, 0xF3u, 0xFFu, 0x44u, 0x1Fu, 0xF2u, 0x04u, 0x01u, 0x2Fu, + 0x30u, 0x2Fu, 0x3Fu, 0xFFu, 0xF0u, 0x10u, 0xFFu, 0x12u, 0xF3u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, + 0xF5u, 0x17u, 0x11u, 0x16u, 0x11u, 0x2Cu, 0x1Fu, 0x17u, 0x9Fu, 0x41u, 0x6Fu, 0xF4u, 0x1Fu, 0x33u, 0xCCu, 0x11u, + 0x63u, 0x1Fu, 0x29u, 0x71u, 0xF5u, 0x2Fu, 0x73u, 0x13u, 0xF1u, 0x13u, 0x11u, 0x1Au, 0x11u, 0x31u, 0x6Fu, 0x11u, + 0x11u, 0x1Fu, 0x11u, 0x1Au, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI0 Address: CYDEV_UDB_DSI0_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI0_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI1 Address: CYDEV_UDB_DSI1_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI1_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI2 Address: CYDEV_UDB_DSI2_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI2_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI3 Address: CYDEV_UDB_DSI3_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI3_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x15u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI4 Address: CYDEV_UDB_DSI4_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI4_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI5 Address: CYDEV_UDB_DSI5_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI5_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI6 Address: CYDEV_UDB_DSI6_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI6_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x09u, 0x1Fu, + 0x1Fu, 0x1Fu, 0x0Eu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x00u, 0x03u, 0xFFu, 0xF0u, 0xFFu, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0xD1u, 0x01u, 0x11u, + 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x1Du, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x10u, 0xD1u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI7 Address: CYDEV_UDB_DSI7_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI7_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x08u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x08u, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x16u, 0x04u, 0x12u, 0x10u, 0x0Du, 0x1Fu, 0x1Fu, 0x10u, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0xFFu, 0x0Fu, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x1Du, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x0Fu, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, + 0x11u, 0xF1u, 0x11u, 0x11u, 0x21u, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI8 Address: CYDEV_UDB_DSI8_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI8_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x04u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x20u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0xD1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0xF1u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x1Fu, 0xF1u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x1Fu, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI9 Address: CYDEV_UDB_DSI9_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI9_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI10 Address: CYDEV_UDB_DSI10_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI10_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x1Fu, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +/* UDB_DSI11 Address: CYDEV_UDB_DSI11_BASE Size (bytes): 124 */ +static const uint8 CYCODE BS_UDB_DSI11_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, + 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, + 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u, 0x11u}; + +static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE), BS_UDB_UDBPAIR5_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE), BS_UDB_UDBPAIR1_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE), BS_UDB_UDBPAIR4_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE), BS_UDB_UDBPAIR3_UDBSNG0_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE), BS_UDB_UDBPAIR2_UDBSNG1_VAL, 116u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR0_ROUTE_BASE), BS_UDB_UDBPAIR0_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR1_ROUTE_BASE), BS_UDB_UDBPAIR1_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR2_ROUTE_BASE), BS_UDB_UDBPAIR2_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR3_ROUTE_BASE), BS_UDB_UDBPAIR3_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR4_ROUTE_BASE), BS_UDB_UDBPAIR4_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_UDBPAIR5_ROUTE_BASE), BS_UDB_UDBPAIR5_ROUTE_VAL, 144u}, + {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), BS_UDB_DSI0_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI1_BASE), BS_UDB_DSI1_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI2_BASE), BS_UDB_DSI2_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI3_BASE), BS_UDB_DSI3_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI4_BASE), BS_UDB_DSI4_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI5_BASE), BS_UDB_DSI5_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI6_BASE), BS_UDB_DSI6_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI7_BASE), BS_UDB_DSI7_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI8_BASE), BS_UDB_DSI8_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI9_BASE), BS_UDB_DSI9_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI10_BASE), BS_UDB_DSI10_VAL, 124u}, + {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, +}; + +void SDIO_Host_Config_TriggerMuxes(void) +{ + /* Connect UDB to DMA */ + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB10, TRIG14_OUT_TR_GROUP0_INPUT49, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT6, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB14, TRIG14_OUT_TR_GROUP0_INPUT48, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT4, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB9, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); +} + +void SDIO_Host_Config_UDBs(void) +{ + + size_t i; + + /* Power on the UDB array */ + CY_SET_REG32(0x402101F0u, 0x05FA0003u); + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t *ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, ms->size); + } + + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t *mc = &cfg_memcpy_list[i]; + CYCONFIGCPYCODE(mc->dest, mc->src, mc->size); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* UDB_INT_CFG Starting address: CYDEV_UDB_UDBIF_INT_CLK_CTL */ + CY_SET_REG32((void *)(CYREG_UDB_UDBIF_INT_CLK_CTL), 0x00000001u); + + /* UDB_UDBPAIR0_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0), 0x004C404Cu); + + /* UDB_UDBPAIR0_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0), 0x044C4C44u); + + /* UDB_UDBPAIR1_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0), 0x004C444Cu); + + /* UDB_UDBPAIR1_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0), 0x044C4C44u); + + /* UDB_UDBPAIR2_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0), 0x4C4C404Cu); + + /* UDB_UDBPAIR2_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0), 0x004C4C4Cu); + + /* UDB_UDBPAIR3_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0), 0x0C8C8C8Cu); + + /* UDB_UDBPAIR3_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0), 0x004C404Cu); + + /* UDB_UDBPAIR4_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0), 0x004C444Cu); + + /* UDB_UDBPAIR4_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + + /* UDB_UDBPAIR5_UDBSNG0_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0), 0x4C4C0400u); + + /* UDB_UDBPAIR5_UDBSNG1_RC_CFG0 Starting address: CYDEV_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 */ + CY_SET_REG32((void *)(CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0), 0x4C4C4C4Cu); + + /* Enable UDB array and digital routing */ + CY_SET_REG32((void *)0x40347900u, CY_GET_REG32((void *)0x40347900u) | 0x106u); + } + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h new file mode 100644 index 00000000000..310fcec47ac --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -0,0 +1,869 @@ +/***************************************************************************//** +* \file SDIO_HOST_cfg.h +* +* \brief +* This file provides the configuration of the UDB based SDIO driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#if !defined(CY_SDIO_CFG_H) +#define CY_SDIO_CFG_H + +#include + +#include "cy_dma.h" +#include "cy_sysclk.h" +#include "cy_trigmux.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYREG_PROT_SMPU_MS0_CTL 0x40240000u +#define CYREG_PROT_SMPU_MS1_CTL 0x40240004u +#define CYREG_PROT_SMPU_MS2_CTL 0x40240008u +#define CYREG_PROT_SMPU_MS3_CTL 0x4024000cu +#define CYREG_PROT_SMPU_MS14_CTL 0x40240038u + +#define CYDEV_UDB_UDBPAIR1_UDBSNG0_BASE 0x40342200u +#define CYDEV_UDB_UDBPAIR0_UDBSNG1_BASE 0x40342080u + +#define CYREG_UDB_UDBPAIR0_UDBSNG0_RC_CFG0 0x4034205cu +#define CYREG_UDB_UDBPAIR0_UDBSNG1_RC_CFG0 0x403420dcu + +#define CYREG_UDB_UDBPAIR1_UDBSNG0_RC_CFG0 0x4034225cu +#define CYREG_UDB_UDBPAIR1_UDBSNG1_RC_CFG0 0x403422dcu + +#define CYREG_UDB_UDBPAIR2_UDBSNG0_RC_CFG0 0x4034245cu +#define CYREG_UDB_UDBPAIR2_UDBSNG1_RC_CFG0 0x403424dcu +#define CYREG_UDB_UDBPAIR3_UDBSNG0_RC_CFG0 0x4034265cu +#define CYREG_UDB_UDBPAIR3_UDBSNG1_RC_CFG0 0x403426dcu +#define CYREG_UDB_UDBPAIR4_UDBSNG0_RC_CFG0 0x4034285cu +#define CYREG_UDB_UDBPAIR4_UDBSNG1_RC_CFG0 0x403428dcu +#define CYREG_UDB_UDBPAIR5_UDBSNG0_RC_CFG0 0x40342a5cu +#define CYREG_UDB_UDBPAIR5_UDBSNG1_RC_CFG0 0x40342adcu + +#define CYDEV_UDB_UDBPAIR4_UDBSNG0_BASE 0x40342800u +#define CYDEV_UDB_UDBPAIR3_UDBSNG1_BASE 0x40342680u +#define CYDEV_UDB_UDBPAIR1_UDBSNG1_BASE 0x40342280u +#define CYDEV_UDB_UDBPAIR0_UDBSNG0_BASE 0x40342000u + +#define CYDEV_UDB_UDBPAIR0_ROUTE_BASE 0x40342100u +#define CYDEV_UDB_UDBPAIR1_ROUTE_BASE 0x40342300u +#define CYDEV_UDB_UDBPAIR2_ROUTE_BASE 0x40342500u +#define CYDEV_UDB_UDBPAIR3_ROUTE_BASE 0x40342700u +#define CYDEV_UDB_UDBPAIR4_ROUTE_BASE 0x40342900u +#define CYDEV_UDB_UDBPAIR5_ROUTE_BASE 0x40342b00u + + +#define CYDEV_UDB_UDBPAIR2_UDBSNG0_BASE 0x40342400u +#define CYDEV_UDB_UDBPAIR2_UDBSNG1_BASE 0x40342480u +#define CYDEV_UDB_UDBPAIR3_UDBSNG0_BASE 0x40342600u +#define CYDEV_UDB_UDBPAIR4_UDBSNG1_BASE 0x40342880u +#define CYDEV_UDB_UDBPAIR5_UDBSNG0_BASE 0x40342a00u +#define CYDEV_UDB_UDBPAIR5_UDBSNG1_BASE 0x40342a80u + + +#define CYDEV_UDB_DSI0_BASE 0x40346000u +#define CYDEV_UDB_DSI1_BASE 0x40346080u +#define CYDEV_UDB_DSI2_BASE 0x40346100u +#define CYDEV_UDB_DSI3_BASE 0x40346180u +#define CYDEV_UDB_DSI4_BASE 0x40346200u +#define CYDEV_UDB_DSI5_BASE 0x40346280u +#define CYDEV_UDB_DSI6_BASE 0x40346300u +#define CYDEV_UDB_DSI7_BASE 0x40346380u +#define CYDEV_UDB_DSI8_BASE 0x40346400u +#define CYDEV_UDB_DSI9_BASE 0x40346480u +#define CYDEV_UDB_DSI10_BASE 0x40346500u +#define CYDEV_UDB_DSI11_BASE 0x40346580u + +#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x40347904u + +/*************Defines for UDBs from Creator*****************************/ +/***********These come for cyfitter.h**********************************/ + +/* SDIO_HOST_bSDIO */ +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_blockCounter_u0__16BIT_F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_blockCounter_u0__32BIT_F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_blockCounter_u0__A0_A1_REG 0x40340008u +#define SDIO_HOST_bSDIO_blockCounter_u0__A0_REG 0x40341008u +#define SDIO_HOST_bSDIO_blockCounter_u0__A1_REG 0x40341108u +#define SDIO_HOST_bSDIO_blockCounter_u0__D0_D1_REG 0x40340108u +#define SDIO_HOST_bSDIO_blockCounter_u0__D0_REG 0x40341208u +#define SDIO_HOST_bSDIO_blockCounter_u0__D1_REG 0x40341308u +#define SDIO_HOST_bSDIO_blockCounter_u0__DP_AUX_CTL_REG 0x40341908u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG0 0x40342240u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG1 0x40342244u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG2 0x40342248u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG3 0x4034224Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_CFG4 0x40342250u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC0 0x40342264u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC1 0x40342268u +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC2 0x4034226Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__DPATH_OPC3 0x40342270u +#define SDIO_HOST_bSDIO_blockCounter_u0__F0_F1_REG 0x40340208u +#define SDIO_HOST_bSDIO_blockCounter_u0__F0_REG 0x40341408u +#define SDIO_HOST_bSDIO_blockCounter_u0__F1_REG 0x40341508u +#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG0 0x4034225Cu +#define SDIO_HOST_bSDIO_blockCounter_u0__RC_CFG1 0x40342260u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_CONTROL_REG 0x40341724u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_CONTROL_COUNT_REG 0x40341724u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_CONTROL_REG 0x40341724u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_COUNT_COUNT_REG 0x40341724u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_MASK_REG 0x40341824u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_MASK_PERIOD_REG 0x40341824u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_MASK_REG 0x40341824u +#define SDIO_HOST_bSDIO_byteCounter__16BIT_PERIOD_PERIOD_REG 0x40341824u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_REG 0x40341724u +#define SDIO_HOST_bSDIO_byteCounter__CONTROL_ST_REG 0x40340324u +#define SDIO_HOST_bSDIO_byteCounter__COUNT_REG 0x40341724u +#define SDIO_HOST_bSDIO_byteCounter__COUNT_ST_REG 0x40340324u +#define SDIO_HOST_bSDIO_byteCounter__MASK_CTL_AUX_CTL_REG 0x40340424u +#define SDIO_HOST_bSDIO_byteCounter__PER_CTL_AUX_CTL_REG 0x40340424u +#define SDIO_HOST_bSDIO_byteCounter__PERIOD_REG 0x40341824u +#define SDIO_HOST_bSDIO_byteCounter__RC_CFG0 0x403428DCu +#define SDIO_HOST_bSDIO_byteCounter__RC_CFG1 0x403428E0u +#define SDIO_HOST_bSDIO_byteCounter__SC_CFG0 0x403428D4u +#define SDIO_HOST_bSDIO_byteCounter__SC_CFG1 0x403428D8u +#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_byteCounter_ST__16BIT_STATUS_REG 0x40341624u +#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_REG 0x40341824u +#define SDIO_HOST_bSDIO_byteCounter_ST__MASK_ST_AUX_CTL_REG 0x40340424u +#define SDIO_HOST_bSDIO_byteCounter_ST__PER_ST_AUX_CTL_REG 0x40340424u +#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG0 0x403428DCu +#define SDIO_HOST_bSDIO_byteCounter_ST__RC_CFG1 0x403428E0u +#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG0 0x403428D4u +#define SDIO_HOST_bSDIO_byteCounter_ST__SC_CFG1 0x403428D8u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CNT_REG 0x40340324u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_CONTROL_REG 0x40340324u +#define SDIO_HOST_bSDIO_byteCounter_ST__STATUS_REG 0x40341624u +#define SDIO_HOST_bSDIO_CMD__16BIT_A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_CMD__16BIT_A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_CMD__16BIT_D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_CMD__16BIT_D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_CMD__16BIT_DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_CMD__16BIT_F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_CMD__16BIT_F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_CMD__32BIT_A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_CMD__32BIT_A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_CMD__32BIT_D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_CMD__32BIT_D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_CMD__32BIT_DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_CMD__32BIT_F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_CMD__32BIT_F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_CMD__A0_A1_REG 0x40340000u +#define SDIO_HOST_bSDIO_CMD__A0_REG 0x40341000u +#define SDIO_HOST_bSDIO_CMD__A1_REG 0x40341100u +#define SDIO_HOST_bSDIO_CMD__D0_D1_REG 0x40340100u +#define SDIO_HOST_bSDIO_CMD__D0_REG 0x40341200u +#define SDIO_HOST_bSDIO_CMD__D1_REG 0x40341300u +#define SDIO_HOST_bSDIO_CMD__DP_AUX_CTL_REG 0x40341900u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG0 0x40342040u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG1 0x40342044u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG2 0x40342048u +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG3 0x4034204Cu +#define SDIO_HOST_bSDIO_CMD__DPATH_CFG4 0x40342050u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC0 0x40342064u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC1 0x40342068u +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC2 0x4034206Cu +#define SDIO_HOST_bSDIO_CMD__DPATH_OPC3 0x40342070u +#define SDIO_HOST_bSDIO_CMD__F0_F1_REG 0x40340200u +#define SDIO_HOST_bSDIO_CMD__F0_REG 0x40341400u +#define SDIO_HOST_bSDIO_CMD__F1_REG 0x40341500u +#define SDIO_HOST_bSDIO_CMD__RC_CFG0 0x4034205Cu +#define SDIO_HOST_bSDIO_CMD__RC_CFG1 0x40342060u +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_AUX_CTL_REG 0x4034192Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_REG 0x4034172Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__CONTROL_ST_REG 0x4034032Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_REG 0x4034172Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__COUNT_ST_REG 0x4034032Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__MASK_CTL_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__PER_CTL_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__PERIOD_REG 0x4034182Cu +#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG0 0x40342ADCu +#define SDIO_HOST_bSDIO_cmdBitCounter__RC_CFG1 0x40342AE0u +#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG0 0x40342AD4u +#define SDIO_HOST_bSDIO_cmdBitCounter__SC_CFG1 0x40342AD8u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_REG 0x4034182Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__MASK_ST_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__PER_ST_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG0 0x40342ADCu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__RC_CFG1 0x40342AE0u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG0 0x40342AD4u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__SC_CFG1 0x40342AD8u +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_AUX_CTL_REG 0x4034192Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CNT_REG 0x4034032Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_CONTROL_REG 0x4034032Cu +#define SDIO_HOST_bSDIO_cmdBitCounter_ST__STATUS_REG 0x4034162Cu +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_CONTROL_COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_COUNT_COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_MASK_PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__16BIT_PERIOD_PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__CONTROL_ST_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_REG 0x40341728u +#define SDIO_HOST_bSDIO_crcBitCounter__COUNT_ST_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter__MASK_CTL_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter__PER_CTL_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter__PERIOD_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_crcBitCounter__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG0 0x40342A54u +#define SDIO_HOST_bSDIO_crcBitCounter__SC_CFG1 0x40342A58u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__16BIT_STATUS_REG 0x40341628u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_REG 0x40341828u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__MASK_ST_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__PER_ST_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_crcBitCounter_ST__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG0 0x40342A54u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__SC_CFG1 0x40342A58u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CNT_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_CONTROL_REG 0x40340328u +#define SDIO_HOST_bSDIO_crcBitCounter_ST__STATUS_REG 0x40341628u +#define SDIO_HOST_bSDIO_CtrlReg__0__MASK 0x01u +#define SDIO_HOST_bSDIO_CtrlReg__0__POS 0 +#define SDIO_HOST_bSDIO_CtrlReg__1__MASK 0x02u +#define SDIO_HOST_bSDIO_CtrlReg__1__POS 1 +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_CONTROL_REG 0x40341718u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_CONTROL_COUNT_REG 0x40341718u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_CONTROL_REG 0x40341718u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_COUNT_COUNT_REG 0x40341718u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_MASK_REG 0x40341818u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_MASK_PERIOD_REG 0x40341818u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_MASK_REG 0x40341818u +#define SDIO_HOST_bSDIO_CtrlReg__16BIT_PERIOD_PERIOD_REG 0x40341818u +#define SDIO_HOST_bSDIO_CtrlReg__2__MASK 0x04u +#define SDIO_HOST_bSDIO_CtrlReg__2__POS 2 +#define SDIO_HOST_bSDIO_CtrlReg__3__MASK 0x08u +#define SDIO_HOST_bSDIO_CtrlReg__3__POS 3 +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_CONTROL_REG 0x40341718u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_COUNT_REG 0x40341718u +#define SDIO_HOST_bSDIO_CtrlReg__32BIT_PERIOD_REG 0x40341818u +#define SDIO_HOST_bSDIO_CtrlReg__4__MASK 0x10u +#define SDIO_HOST_bSDIO_CtrlReg__4__POS 4 +#define SDIO_HOST_bSDIO_CtrlReg__6__MASK 0x40u +#define SDIO_HOST_bSDIO_CtrlReg__6__POS 6 +#define SDIO_HOST_bSDIO_CtrlReg__7__MASK 0x80u +#define SDIO_HOST_bSDIO_CtrlReg__7__POS 7 +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_REG 0x40341718u +#define SDIO_HOST_bSDIO_CtrlReg__CONTROL_ST_REG 0x40340318u +#define SDIO_HOST_bSDIO_CtrlReg__COUNT_REG 0x40341718u +#define SDIO_HOST_bSDIO_CtrlReg__COUNT_ST_REG 0x40340318u +#define SDIO_HOST_bSDIO_CtrlReg__MASK 0xDFu +#define SDIO_HOST_bSDIO_CtrlReg__MASK_CTL_AUX_CTL_REG 0x40340418u +#define SDIO_HOST_bSDIO_CtrlReg__PER_CTL_AUX_CTL_REG 0x40340418u +#define SDIO_HOST_bSDIO_CtrlReg__PERIOD_REG 0x40341818u +#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG0 0x4034265Cu +#define SDIO_HOST_bSDIO_CtrlReg__RC_CFG1 0x40342660u +#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG0 0x40342654u +#define SDIO_HOST_bSDIO_CtrlReg__SC_CFG1 0x40342658u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__16BIT_F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__32BIT_F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_A1_REG 0x40340010u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A0_REG 0x40341010u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__A1_REG 0x40341110u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_D1_REG 0x40340110u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D0_REG 0x40341210u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__D1_REG 0x40341310u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DP_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG0 0x40342440u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG1 0x40342444u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG2 0x40342448u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG3 0x4034244Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_CFG4 0x40342450u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC0 0x40342464u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC1 0x40342468u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC2 0x4034246Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__DPATH_OPC3 0x40342470u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_F1_REG 0x40340210u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F0_REG 0x40341410u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__F1_REG 0x40341510u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__MSK_DP_AUX_CTL_REG 0x40340410u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__PER_DP_AUX_CTL_REG 0x40340410u +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG0 0x4034245Cu +#define SDIO_HOST_bSDIO_DAT_CRC0_u0__RC_CFG1 0x40342460u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__16BIT_F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__32BIT_F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_A1_REG 0x40340014u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A0_REG 0x40341014u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__A1_REG 0x40341114u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_D1_REG 0x40340114u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D0_REG 0x40341214u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__D1_REG 0x40341314u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DP_AUX_CTL_REG 0x40341914u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG0 0x403424C0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG1 0x403424C4u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG2 0x403424C8u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG3 0x403424CCu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_CFG4 0x403424D0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC0 0x403424E4u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC1 0x403424E8u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC2 0x403424ECu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__DPATH_OPC3 0x403424F0u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_F1_REG 0x40340214u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F0_REG 0x40341414u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__F1_REG 0x40341514u +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG0 0x403424DCu +#define SDIO_HOST_bSDIO_DAT_CRC0_u1__RC_CFG1 0x403424E0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A0_REG 0x40341028u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_A1_REG 0x40341128u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D0_REG 0x40341228u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_D1_REG 0x40341328u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_DP_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F0_REG 0x40341428u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__16BIT_F1_REG 0x40341528u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_A1_REG 0x40340028u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A0_REG 0x40341028u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__A1_REG 0x40341128u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_D1_REG 0x40340128u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D0_REG 0x40341228u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__D1_REG 0x40341328u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DP_AUX_CTL_REG 0x40341928u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG0 0x40342A40u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG1 0x40342A44u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG2 0x40342A48u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG3 0x40342A4Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_CFG4 0x40342A50u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC0 0x40342A64u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC1 0x40342A68u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC2 0x40342A6Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__DPATH_OPC3 0x40342A70u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_F1_REG 0x40340228u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F0_REG 0x40341428u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__F1_REG 0x40341528u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__MSK_DP_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__PER_DP_AUX_CTL_REG 0x40340428u +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG0 0x40342A5Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u0__RC_CFG1 0x40342A60u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_A1_REG 0x4034002Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A0_REG 0x4034102Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__A1_REG 0x4034112Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_D1_REG 0x4034012Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D0_REG 0x4034122Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__D1_REG 0x4034132Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DP_AUX_CTL_REG 0x4034192Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG0 0x40342AC0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG1 0x40342AC4u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG2 0x40342AC8u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG3 0x40342ACCu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_CFG4 0x40342AD0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC0 0x40342AE4u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC1 0x40342AE8u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC2 0x40342AECu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__DPATH_OPC3 0x40342AF0u +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_F1_REG 0x4034022Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F0_REG 0x4034142Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__F1_REG 0x4034152Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__MSK_DP_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__PER_DP_AUX_CTL_REG 0x4034042Cu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG0 0x40342ADCu +#define SDIO_HOST_bSDIO_DAT_CRC1_u1__RC_CFG1 0x40342AE0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__16BIT_F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__32BIT_F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_A1_REG 0x40340020u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A0_REG 0x40341020u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__A1_REG 0x40341120u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_D1_REG 0x40340120u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D0_REG 0x40341220u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__D1_REG 0x40341320u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DP_AUX_CTL_REG 0x40341920u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG0 0x40342840u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG1 0x40342844u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG2 0x40342848u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG3 0x4034284Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_CFG4 0x40342850u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC0 0x40342864u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC1 0x40342868u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC2 0x4034286Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__DPATH_OPC3 0x40342870u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_F1_REG 0x40340220u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F0_REG 0x40341420u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__F1_REG 0x40341520u +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG0 0x4034285Cu +#define SDIO_HOST_bSDIO_DAT_CRC2_u0__RC_CFG1 0x40342860u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_A0_REG 0x40341024u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_A1_REG 0x40341124u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_D0_REG 0x40341224u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_D1_REG 0x40341324u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_DP_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_F0_REG 0x40341424u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__16BIT_F1_REG 0x40341524u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_A1_REG 0x40340024u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A0_REG 0x40341024u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__A1_REG 0x40341124u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_D1_REG 0x40340124u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D0_REG 0x40341224u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__D1_REG 0x40341324u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DP_AUX_CTL_REG 0x40341924u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG0 0x403428C0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG1 0x403428C4u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG2 0x403428C8u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG3 0x403428CCu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_CFG4 0x403428D0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC0 0x403428E4u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC1 0x403428E8u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC2 0x403428ECu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__DPATH_OPC3 0x403428F0u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_F1_REG 0x40340224u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F0_REG 0x40341424u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__F1_REG 0x40341524u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__MSK_DP_AUX_CTL_REG 0x40340424u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__PER_DP_AUX_CTL_REG 0x40340424u +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG0 0x403428DCu +#define SDIO_HOST_bSDIO_DAT_CRC2_u1__RC_CFG1 0x403428E0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__16BIT_F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__32BIT_F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_A1_REG 0x40340018u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A0_REG 0x40341018u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__A1_REG 0x40341118u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_D1_REG 0x40340118u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D0_REG 0x40341218u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__D1_REG 0x40341318u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DP_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG0 0x40342640u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG1 0x40342644u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG2 0x40342648u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG3 0x4034264Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_CFG4 0x40342650u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC0 0x40342664u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC1 0x40342668u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC2 0x4034266Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__DPATH_OPC3 0x40342670u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_F1_REG 0x40340218u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F0_REG 0x40341418u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__F1_REG 0x40341518u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__MSK_DP_AUX_CTL_REG 0x40340418u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__PER_DP_AUX_CTL_REG 0x40340418u +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG0 0x4034265Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u0__RC_CFG1 0x40342660u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__16BIT_F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__32BIT_F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_A1_REG 0x4034001Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A0_REG 0x4034101Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__A1_REG 0x4034111Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_D1_REG 0x4034011Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D0_REG 0x4034121Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__D1_REG 0x4034131Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DP_AUX_CTL_REG 0x4034191Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG0 0x403426C0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG1 0x403426C4u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG2 0x403426C8u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG3 0x403426CCu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_CFG4 0x403426D0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC0 0x403426E4u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC1 0x403426E8u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC2 0x403426ECu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__DPATH_OPC3 0x403426F0u +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_F1_REG 0x4034021Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F0_REG 0x4034141Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__F1_REG 0x4034151Cu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG0 0x403426DCu +#define SDIO_HOST_bSDIO_DAT_CRC3_u1__RC_CFG1 0x403426E0u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_Read_DP__16BIT_F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_Read_DP__32BIT_A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_Read_DP__32BIT_A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_Read_DP__32BIT_D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_Read_DP__32BIT_D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_Read_DP__32BIT_DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_Read_DP__32BIT_F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_Read_DP__32BIT_F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_Read_DP__A0_A1_REG 0x40340004u +#define SDIO_HOST_bSDIO_Read_DP__A0_REG 0x40341004u +#define SDIO_HOST_bSDIO_Read_DP__A1_REG 0x40341104u +#define SDIO_HOST_bSDIO_Read_DP__D0_D1_REG 0x40340104u +#define SDIO_HOST_bSDIO_Read_DP__D0_REG 0x40341204u +#define SDIO_HOST_bSDIO_Read_DP__D1_REG 0x40341304u +#define SDIO_HOST_bSDIO_Read_DP__DP_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG0 0x403420C0u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG1 0x403420C4u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG2 0x403420C8u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG3 0x403420CCu +#define SDIO_HOST_bSDIO_Read_DP__DPATH_CFG4 0x403420D0u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC0 0x403420E4u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC1 0x403420E8u +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC2 0x403420ECu +#define SDIO_HOST_bSDIO_Read_DP__DPATH_OPC3 0x403420F0u +#define SDIO_HOST_bSDIO_Read_DP__F0_F1_REG 0x40340204u +#define SDIO_HOST_bSDIO_Read_DP__F0_REG 0x40341404u +#define SDIO_HOST_bSDIO_Read_DP__F1_REG 0x40341504u +#define SDIO_HOST_bSDIO_Read_DP__RC_CFG0 0x403420DCu +#define SDIO_HOST_bSDIO_Read_DP__RC_CFG1 0x403420E0u +#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_Read_DP_PI__16BIT_STATUS_REG 0x40341604u +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_Read_DP_PI__32BIT_STATUS_REG 0x40341604u +#define SDIO_HOST_bSDIO_Read_DP_PI__MASK_REG 0x40341804u +#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG0 0x403420DCu +#define SDIO_HOST_bSDIO_Read_DP_PI__RC_CFG1 0x403420E0u +#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG0 0x403420D4u +#define SDIO_HOST_bSDIO_Read_DP_PI__SC_CFG1 0x403420D8u +#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_AUX_CTL_REG 0x40341904u +#define SDIO_HOST_bSDIO_Read_DP_PI__STATUS_REG 0x40341604u +#define SDIO_HOST_bSDIO_StatusReg__0__MASK 0x01u +#define SDIO_HOST_bSDIO_StatusReg__0__POS 0 +#define SDIO_HOST_bSDIO_StatusReg__1__MASK 0x02u +#define SDIO_HOST_bSDIO_StatusReg__1__POS 1 +#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_StatusReg__16BIT_STATUS_REG 0x40341618u +#define SDIO_HOST_bSDIO_StatusReg__2__MASK 0x04u +#define SDIO_HOST_bSDIO_StatusReg__2__POS 2 +#define SDIO_HOST_bSDIO_StatusReg__3__MASK 0x08u +#define SDIO_HOST_bSDIO_StatusReg__3__POS 3 +#define SDIO_HOST_bSDIO_StatusReg__32BIT_MASK_REG 0x40341818u +#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_StatusReg__32BIT_STATUS_REG 0x40341618u +#define SDIO_HOST_bSDIO_StatusReg__6__MASK 0x40u +#define SDIO_HOST_bSDIO_StatusReg__6__POS 6 +#define SDIO_HOST_bSDIO_StatusReg__MASK 0x4Fu +#define SDIO_HOST_bSDIO_StatusReg__MASK_REG 0x40341818u +#define SDIO_HOST_bSDIO_StatusReg__MASK_ST_AUX_CTL_REG 0x40340418u +#define SDIO_HOST_bSDIO_StatusReg__PER_ST_AUX_CTL_REG 0x40340418u +#define SDIO_HOST_bSDIO_StatusReg__RC_CFG0 0x4034265Cu +#define SDIO_HOST_bSDIO_StatusReg__RC_CFG1 0x40342660u +#define SDIO_HOST_bSDIO_StatusReg__SC_CFG0 0x40342654u +#define SDIO_HOST_bSDIO_StatusReg__SC_CFG1 0x40342658u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_AUX_CTL_REG 0x40341918u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_CNT_REG 0x40340318u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_CONTROL_REG 0x40340318u +#define SDIO_HOST_bSDIO_StatusReg__STATUS_REG 0x40341618u +#define SDIO_HOST_bSDIO_Write_DP__16BIT_A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Write_DP__16BIT_A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Write_DP__16BIT_D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Write_DP__16BIT_D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Write_DP__16BIT_DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Write_DP__16BIT_F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Write_DP__16BIT_F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Write_DP__32BIT_A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Write_DP__32BIT_A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Write_DP__32BIT_D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Write_DP__32BIT_D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Write_DP__32BIT_DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Write_DP__32BIT_F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Write_DP__32BIT_F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Write_DP__A0_A1_REG 0x4034000Cu +#define SDIO_HOST_bSDIO_Write_DP__A0_REG 0x4034100Cu +#define SDIO_HOST_bSDIO_Write_DP__A1_REG 0x4034110Cu +#define SDIO_HOST_bSDIO_Write_DP__D0_D1_REG 0x4034010Cu +#define SDIO_HOST_bSDIO_Write_DP__D0_REG 0x4034120Cu +#define SDIO_HOST_bSDIO_Write_DP__D1_REG 0x4034130Cu +#define SDIO_HOST_bSDIO_Write_DP__DP_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG0 0x403422C0u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG1 0x403422C4u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG2 0x403422C8u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG3 0x403422CCu +#define SDIO_HOST_bSDIO_Write_DP__DPATH_CFG4 0x403422D0u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC0 0x403422E4u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC1 0x403422E8u +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC2 0x403422ECu +#define SDIO_HOST_bSDIO_Write_DP__DPATH_OPC3 0x403422F0u +#define SDIO_HOST_bSDIO_Write_DP__F0_F1_REG 0x4034020Cu +#define SDIO_HOST_bSDIO_Write_DP__F0_REG 0x4034140Cu +#define SDIO_HOST_bSDIO_Write_DP__F1_REG 0x4034150Cu +#define SDIO_HOST_bSDIO_Write_DP__MSK_DP_AUX_CTL_REG 0x4034040Cu +#define SDIO_HOST_bSDIO_Write_DP__PER_DP_AUX_CTL_REG 0x4034040Cu +#define SDIO_HOST_bSDIO_Write_DP__RC_CFG0 0x403422DCu +#define SDIO_HOST_bSDIO_Write_DP__RC_CFG1 0x403422E0u +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_CONTROL_REG 0x4034170Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_CONTROL_COUNT_REG 0x4034170Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_CONTROL_REG 0x4034170Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_COUNT_COUNT_REG 0x4034170Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_MASK_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_MASK_PERIOD_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_MASK_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__16BIT_PERIOD_PERIOD_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_CONTROL_REG 0x4034170Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_COUNT_REG 0x4034170Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__32BIT_PERIOD_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_AUX_CTL_REG 0x4034190Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_REG 0x4034170Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__CONTROL_ST_REG 0x4034030Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_REG 0x4034170Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__COUNT_ST_REG 0x4034030Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__MASK_CTL_AUX_CTL_REG 0x4034040Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__PER_CTL_AUX_CTL_REG 0x4034040Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__PERIOD_REG 0x4034180Cu +#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG0 0x403422DCu +#define SDIO_HOST_bSDIO_Write_DP_PO__RC_CFG1 0x403422E0u +#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG0 0x403422D4u +#define SDIO_HOST_bSDIO_Write_DP_PO__SC_CFG1 0x403422D8u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_CONTROL_REG 0x40341710u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_CONTROL_COUNT_REG 0x40341710u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_CONTROL_REG 0x40341710u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_COUNT_COUNT_REG 0x40341710u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_MASK_REG 0x40341810u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_MASK_PERIOD_REG 0x40341810u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_MASK_REG 0x40341810u +#define SDIO_HOST_bSDIO_writeCrcCounter__16BIT_PERIOD_PERIOD_REG 0x40341810u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_CONTROL_REG 0x40341710u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_COUNT_REG 0x40341710u +#define SDIO_HOST_bSDIO_writeCrcCounter__32BIT_PERIOD_REG 0x40341810u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_REG 0x40341710u +#define SDIO_HOST_bSDIO_writeCrcCounter__CONTROL_ST_REG 0x40340310u +#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_REG 0x40341710u +#define SDIO_HOST_bSDIO_writeCrcCounter__COUNT_ST_REG 0x40340310u +#define SDIO_HOST_bSDIO_writeCrcCounter__MASK_CTL_AUX_CTL_REG 0x40340410u +#define SDIO_HOST_bSDIO_writeCrcCounter__PER_CTL_AUX_CTL_REG 0x40340410u +#define SDIO_HOST_bSDIO_writeCrcCounter__PERIOD_REG 0x40341810u +#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG0 0x4034245Cu +#define SDIO_HOST_bSDIO_writeCrcCounter__RC_CFG1 0x40342460u +#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG0 0x40342454u +#define SDIO_HOST_bSDIO_writeCrcCounter__SC_CFG1 0x40342458u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__16BIT_STATUS_REG 0x40341610u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_MASK_REG 0x40341810u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__32BIT_STATUS_REG 0x40341610u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_REG 0x40341810u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__MASK_ST_AUX_CTL_REG 0x40340410u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__PER_ST_AUX_CTL_REG 0x40340410u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG0 0x4034245Cu +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__RC_CFG1 0x40342460u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG0 0x40342454u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__SC_CFG1 0x40342458u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_AUX_CTL_REG 0x40341910u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CNT_REG 0x40340310u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_CONTROL_REG 0x40340310u +#define SDIO_HOST_bSDIO_writeCrcCounter_ST__STATUS_REG 0x40341610u +#define SDIO_HOST_CMD_DMA_DW__BLOCK_HW DW0 +#define SDIO_HOST_CMD_DMA_DW__BLOCK_NUMBER 0u +#define SDIO_HOST_CMD_DMA_DW__CHANNEL_HW DW0_CH_STRUCT1 +#define SDIO_HOST_CMD_DMA_DW__CHANNEL_NUMBER 1u +#define SDIO_HOST_CMD_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN1 +#define SDIO_HOST_Internal_Clock__DIV_IDX 0 +#define SDIO_HOST_Internal_Clock__DIV_NUM 0 +#define SDIO_HOST_Internal_Clock__DIV_TYPE CY_SYSCLK_DIV_8_BIT +#define SDIO_HOST_Read_DMA_DW__BLOCK_HW DW1 +#define SDIO_HOST_Read_DMA_DW__BLOCK_NUMBER 1u +#define SDIO_HOST_Read_DMA_DW__CHANNEL_HW DW1_CH_STRUCT3 +#define SDIO_HOST_Read_DMA_DW__CHANNEL_NUMBER 3u +#define SDIO_HOST_Read_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN3 +#define SDIO_HOST_Resp_DMA_DW__BLOCK_HW DW0 +#define SDIO_HOST_Resp_DMA_DW__BLOCK_NUMBER 0u +#define SDIO_HOST_Resp_DMA_DW__CHANNEL_HW DW0_CH_STRUCT0 +#define SDIO_HOST_Resp_DMA_DW__CHANNEL_NUMBER 0u +#define SDIO_HOST_Resp_DMA_DW__TR_IN TRIG0_OUT_CPUSS_DW0_TR_IN0 +#define SDIO_HOST_Write_DMA_DW__BLOCK_HW DW1 +#define SDIO_HOST_Write_DMA_DW__BLOCK_NUMBER 1u +#define SDIO_HOST_Write_DMA_DW__CHANNEL_HW DW1_CH_STRUCT1 +#define SDIO_HOST_Write_DMA_DW__CHANNEL_NUMBER 1u +#define SDIO_HOST_Write_DMA_DW__TR_IN TRIG1_OUT_CPUSS_DW1_TR_IN1 + + +/***************************CMD DMA***************************************/ +#define SDIO_HOST_CMD_DMA_DW_BLOCK (0u) +#define SDIO_HOST_CMD_DMA_DW_CHANNEL (1u) +#define SDIO_HOST_CMD_DMA_HW (DW0) +#define SDIO_HOST_CMD_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_CMD_DMA_PRIORITY (1u) +#define SDIO_HOST_CMD_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_CMD_DMA_PREEMPTABLE (true) +#define SDIO_HOST_CMD_DMA_BUFFERABLE (false) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_CMD_DMA_CMD_DMA_Desc; + +/***************************Read DMA***************************************/ +#define SDIO_HOST_Read_DMA_DW_BLOCK (1u) +#define SDIO_HOST_Read_DMA_DW_CHANNEL (3u) +#define SDIO_HOST_Read_DMA_HW (DW1) +#define SDIO_HOST_Read_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Read_DMA_PRIORITY (0u) +#define SDIO_HOST_Read_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Read_DMA_PREEMPTABLE (false) +#define SDIO_HOST_Read_DMA_BUFFERABLE (false) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Read_DMA_Read_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Read_DMA_Read_DMA_Desc; + +/***************************Resp DMA***************************************/ +#define SDIO_HOST_Resp_DMA_DW_BLOCK (0u) +#define SDIO_HOST_Resp_DMA_DW_CHANNEL (0u) +#define SDIO_HOST_Resp_DMA_HW (DW0) +#define SDIO_HOST_Resp_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Resp_DMA_PRIORITY (1u) +#define SDIO_HOST_Resp_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Resp_DMA_PREEMPTABLE (true) +#define SDIO_HOST_Resp_DMA_BUFFERABLE (false) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Resp_DMA_Resp_DMA_Desc; + +/***************************Write DMA***************************************/ +#define SDIO_HOST_Write_DMA_DW_BLOCK (1u) +#define SDIO_HOST_Write_DMA_DW_CHANNEL (1u) +#define SDIO_HOST_Write_DMA_HW (DW1) +#define SDIO_HOST_Write_DMA_INTR_MASK (CY_DMA_INTR_MASK) + +/* Channel settings */ +#define SDIO_HOST_Write_DMA_PRIORITY (0u) +#define SDIO_HOST_Write_DMA_DESCRIPTOR_NUM (1u) +#define SDIO_HOST_Write_DMA_PREEMPTABLE (false) +#define SDIO_HOST_Write_DMA_BUFFERABLE (true) + +extern cy_stc_dma_descriptor_config_t SDIO_HOST_Write_DMA_Write_DMA_Desc_config; +extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; + +/***************************SDIO Clock**************************************/ +/* The peripheral clock divider number */ +#define SDIO_HOST_Internal_Clock_DIV_NUM ((uint32_t)SDIO_HOST_Internal_Clock__DIV_NUM) +/* The peripheral clock divider type */ +#define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)SDIO_HOST_Internal_Clock__DIV_TYPE) + +/*Function for configuring TriggerMuxes*/ +void SDIO_Host_Config_TriggerMuxes(void); + +/*Function for configuring UDBs*/ +void SDIO_Host_Config_UDBs(void); + +/* SDIO_HOST_Read_Int */ +#define SDIO_HOST_Read_Int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Read_Int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Read_Int__INTC_NUMBER 69u +#define SDIO_HOST_Read_Int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Read_Int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Read_Int_INTC_NUMBER 69u + +/* SDIO_HOST_sdio_int */ +#define SDIO_HOST_sdio_int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_sdio_int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_sdio_int__INTC_NUMBER 122u +#define SDIO_HOST_sdio_int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_sdio_int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_sdio_int_INTC_NUMBER 122u + +/* SDIO_HOST_Write_Int */ +#define SDIO_HOST_Write_Int__INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Write_Int__INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Write_Int__INTC_NUMBER 67u +#define SDIO_HOST_Write_Int_INTC_CORTEXM4_ASSIGNED 1 +#define SDIO_HOST_Write_Int_INTC_CORTEXM4_PRIORITY 7u +#define SDIO_HOST_Write_Int_INTC_NUMBER 67u + +#if defined(__cplusplus) +} +#endif + +#endif /* !defined(CY_SDIO_CFG_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.c new file mode 100644 index 00000000000..d1d95a8108d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.c @@ -0,0 +1,117 @@ +/***************************************************************************//** +* \file cybsp.c +* +* Description: +* Provides initialization code for starting up the hardware contained on the +* Cypress board. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cybsp.h" +#include "cyhal_utils.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + +#if defined(CYBSP_WIFI_CAPABLE) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} +#endif + +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ + cy_rslt_t result = cyhal_hwmgr_init(); + init_cycfg_system(); + + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_register_sysclk_pm_callback(); + } + +#if defined(CYBSP_WIFI_CAPABLE) + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ + if (CY_RSLT_SUCCESS == result) + { + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); + } +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + + /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.h new file mode 100644 index 00000000000..f1cf031fd76 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.h @@ -0,0 +1,74 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cybsp_types.h" +#include "cycfg.h" +#if defined(CYBSP_WIFI_CAPABLE) +#include "cyhal_sdio.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + +#if defined(CYBSP_WIFI_CAPABLE) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp_types.h new file mode 100644 index 00000000000..3e1163e9c79 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp_types.h @@ -0,0 +1,228 @@ +/***************************************************************************//** +* \file CYW9P62S1-43012EVB-01/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CYW9P62S1-43012EVB-01 evaluation kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cyhal_pin_package.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + + +/** +* \addtogroup group_bsp_pins Pin Mappings +* \{ +*/ + +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** LED 8; User LED1 */ +#define CYBSP_LED8 (P1_5) +/** LED 9; User LED2 */ +#define CYBSP_LED9 (P11_0) + +/** LED 8; User LED1 */ +#define CYBSP_USER_LED1 (CYBSP_LED8) +/** LED 9; User LED2 */ +#define CYBSP_USER_LED2 (CYBSP_LED9) +/** LED 8; User LED1 */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 2; User Button 1 */ +#define CYBSP_SW2 (P1_4) + +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW2) +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) + +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ + +/** Pin: CYBSP_WIFI_SDIO_D0 */ +#define CYBSP_WIFI_SDIO_D0 (P12_1) +/** Pin: CYBSP_WIFI_SDIO_D1 */ +#define CYBSP_WIFI_SDIO_D1 (P12_2) +/** Pin: CYBSP_WIFI_SDIO_D2 */ +#define CYBSP_WIFI_SDIO_D2 (P12_3) +/** Pin: CYBSP_WIFI_SDIO_D3 */ +#define CYBSP_WIFI_SDIO_D3 (P12_4) +/** Pin: CYBSP_WIFI_SDIO_CMD */ +#define CYBSP_WIFI_SDIO_CMD (P12_5) +/** Pin: CYBSP_WIFI_SDIO_CLK */ +#define CYBSP_WIFI_SDIO_CLK (P12_0) +/** Pin: CYBSP_WIFI_WL_REG_ON */ +#define CYBSP_WIFI_WL_REG_ON (P6_2) +/** Pin: CYBSP_WIFI_HOST_WAKE */ +#define CYBSP_WIFI_HOST_WAKE (P6_0) + +/** Pin: CYBSP_BT_UART_RX */ +#define CYBSP_BT_UART_RX (P8_0) +/** Pin: CYBSP_BT_UART_TX */ +#define CYBSP_BT_UART_TX (P8_1) +/** Pin: CYBSP_BT_UART_RTS */ +#define CYBSP_BT_UART_RTS (P8_2) +/** Pin: CYBSP_BT_UART_CTS */ +#define CYBSP_BT_UART_CTS (P8_3) +/** Pin: BT Power */ +#define CYBSP_BT_POWER (P6_3) +/** Pin: CYBSP_BT_HOST_WAKE */ +#define CYBSP_BT_HOST_WAKE (P8_4) +/** Pin: CYBSP_BT_DEVICE_WAKE */ +#define CYBSP_BT_DEVICE_WAKE (P6_1) + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX (P5_0) +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX (P5_1) +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RTS (P5_2) +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_CTS (P5_3) + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL (P1_0) +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA (P1_1) + +/** Pin: CYBSP_TDO_SWO */ +#define CYBSP_TDO_SWO (P6_4) +/** Pin: CYBSP_TMS_SWDIO */ +#define CYBSP_TMS_SWDIO (P6_6) +/** Pin: CYBSP_SWCLK */ +#define CYBSP_SWCLK (P6_7) + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS (P11_2) +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 (P11_3) +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 (P11_4) +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 (P11_5) +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 (P11_6) +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK (P11_7) + +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) + +/** \} group_bsp_pins_comm */ + + +/** +* \addtogroup group_bsp_pins_arduino Arduino Header Pins +* \{ +*/ + +/** Arduino A0 */ +#define CYBSP_A0 P10_0 +/** Arduino A1 */ +#define CYBSP_A1 P10_1 +/** Arduino A2 */ +#define CYBSP_A2 P6_4 +/** Arduino A3 */ +#define CYBSP_A3 P6_5 +/** Arduino A4 */ +#define CYBSP_A4 P10_4 +/** Arduino A5 */ +#define CYBSP_A5 P10_5 +/** Arduino D0 */ +#define CYBSP_D0 (P5_0) +/** Arduino D1 */ +#define CYBSP_D1 (P5_1) +/** Arduino D2 */ +#define CYBSP_D2 (P5_2) +/** Arduino D3 */ +#define CYBSP_D3 (P5_3) +/** Arduino D4 */ +#define CYBSP_D4 (P5_4) +/** Arduino D5 */ +#define CYBSP_D5 (P5_5) +/** Arduino D6 */ +#define CYBSP_D6 (P5_6) +/** Arduino D7 */ +#define CYBSP_D7 (P5_7) +/** Arduino D8 */ +#define CYBSP_D8 (NC) +/** Arduino D9 */ +#define CYBSP_D9 (NC) +/** Arduino D10 */ +#define CYBSP_D10 (P0_5) +/** Arduino D11 */ +#define CYBSP_D11 (P0_2) +/** Arduino D12 */ +#define CYBSP_D12 (P0_3) +/** Arduino D13 */ +#define CYBSP_D13 (P0_4) +/** Arduino D14 */ +#define CYBSP_D14 (NC) +/** Arduino D15 */ +#define CYBSP_D15 (NC) + +/** \} group_bsp_pins_arduino */ + +/** \} group_bsp_pins */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct new file mode 100644 index 00000000000..7ccd6c547dc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -0,0 +1,313 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.sct +;* \version 2.60 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; Size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00045800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; Size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 + { + * (HEAP) + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + { + * (STACK) + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..5bd22714385 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,684 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00000400 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + + ALIGN + + ENDIF + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld new file mode 100644 index 00000000000..e7c641ea4fe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,461 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.60 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* Size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00045800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..3c2f44d1e07 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,631 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf new file mode 100644 index 00000000000..ae61379863e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,286 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.icf +* \version 2.60 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* Size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00100000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00045800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..f4ca47b4579 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -0,0 +1,1137 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h new file mode 100644 index 00000000000..423361f58ab --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6.h @@ -0,0 +1,680 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.60 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6_cm4.c new file mode 100644 index 00000000000..0a18f50a4d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/device/system_psoc6_cm4.c @@ -0,0 +1,552 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.60 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if ((rootPath == 1UL) || (rootPath == 2UL)) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/targets.json b/targets/targets.json index 7cde1f85f09..d4797698018 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9282,6 +9282,30 @@ "network-default-interface-type": "WIFI" } }, + "CYW9P62S1_43012EVB_01": { + "inherits": ["MCU_PSOC6_M4"], + "features": ["BLE"], + "components_remove": ["QSPIF"], + "device_has_remove": ["ANALOGOUT", "CRC", "TRNG", "QSPI"], + "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"], + "extra_labels_add": [ + "PSOC6_01", + "CM0P_SLEEP", + "WHD", + "43012", + "CYW43XXX", + "CORDIO" + ], + "extra_labels_remove": ["MXCRYPTO"], + "macros_add": ["CY8C6247FDI_D32", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], + "detect_code": ["1903"], + "post_binary_hook": { + "function": "PSOC6Code.complete" + }, + "overrides": { + "network-default-interface-type": "WIFI" + } + }, "FUTURE_SEQUANA_M0": { "inherits": ["MCU_PSOC6_M0"], "supported_form_factors": ["ARDUINO"],