From 18c973f1327cfa54a35f8596ead65f3e2ee07882 Mon Sep 17 00:00:00 2001
From: Steven Cooreman <steven.cooreman@silabs.com>
Date: Mon, 15 Jan 2018 16:13:15 +0100
Subject: [PATCH] Allow overriding of DCDC settings per target

Allow custom targets to override the DCDC settings by defining EMU_DCDCINIT_STK_DEFAULT to target-specific initialization values.
---
 .../TARGET_EFM32PG_STK3401/device_peripherals.h           | 5 +++++
 .../TARGET_EFM32PG12_STK3402/device_peripherals.h         | 5 +++++
 .../TARGET_EFR32MG1_BRD4150/device_peripherals.h          | 5 +++++
 .../TARGET_TB_SENSE_1/device_peripherals.h                | 5 +++++
 .../TARGET_TB_SENSE_12/device_peripherals.h               | 5 +++++
 .../TARGET_EFM32/common/mbed_overrides.c                  | 8 ++++++--
 6 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h
index 3147299bbdc..05bad32dc9d 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h
@@ -54,4 +54,9 @@
   cmuOscMode_Crystal,                                                           \
 }
 #endif
+
+/* DCDC settings */
+#if !defined(EMU_DCDCINIT_STK_DEFAULT)
+#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT
+#endif
 #endif
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h
index d9cd0fef8a3..d3f9b7d58a8 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h
@@ -54,4 +54,9 @@
   cmuOscMode_Crystal,                                                           \
 }
 #endif
+
+/* DCDC settings */
+#if !defined(EMU_DCDCINIT_STK_DEFAULT)
+#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT
+#endif
 #endif
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h
index 13cbb9af1a0..1a1c9c9f83a 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h
@@ -54,4 +54,9 @@
   cmuOscMode_Crystal,                                                           \
 }
 #endif
+
+/* DCDC settings */
+#if !defined(EMU_DCDCINIT_STK_DEFAULT)
+#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT
+#endif
 #endif
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h
index 976dce7abac..ccac6294382 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h
@@ -54,4 +54,9 @@
   cmuOscMode_Crystal,                                                           \
 }
 #endif
+
+/* DCDC settings */
+#if !defined(EMU_DCDCINIT_STK_DEFAULT)
+#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT
+#endif
 #endif
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h
index 976dce7abac..ccac6294382 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h
@@ -54,4 +54,9 @@
   cmuOscMode_Crystal,                                                           \
 }
 #endif
+
+/* DCDC settings */
+#if !defined(EMU_DCDCINIT_STK_DEFAULT)
+#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT
+#endif
 #endif
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c
index e3ded3571f2..bc8f479a6cd 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c
@@ -39,9 +39,13 @@ void mbed_sdk_init()
     CHIP_Init();
 
 #if defined(_SILICON_LABS_32B_SERIES_1)
-    EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT;
+#if defined(EMU_NO_DCDC)
+    EMU_DCDCPowerOff();
+#else
+    EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_STK_DEFAULT;
     EMU_DCDCInit(&dcdcInit);
-    
+#endif
+
 #if (CORE_CLOCK_SOURCE == HFXO)
     // Only init HFXO if not already done (e.g. by bootloader)
     if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) {