diff --git a/drivers/SerialWireOutput.h b/drivers/SerialWireOutput.h new file mode 100644 index 00000000000..2f8f9bd6163 --- /dev/null +++ b/drivers/SerialWireOutput.h @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(DEVICE_ITM) + +#include "hal/itm_api.h" +#include "platform/FileHandle.h" + +class SerialWireOutput : public FileHandle { +public: + SerialWireOutput(void) + { + /* Initialize ITM using internal init function. */ + mbed_itm_init(); + } + + virtual ssize_t write(const void *buffer, size_t size) + { + const unsigned char *buf = static_cast(buffer); + + /* Send buffer one character at a time over the ITM SWO port */ + for (size_t i = 0; i < size; i++) { + mbed_itm_send(ITM_PORT_SWO, buf[i]); + } + return size; + } + + virtual ssize_t read(void *buffer, size_t size) + { + /* Reading is not supported by this file handle */ + return -EBADF; + } + + virtual off_t seek(off_t offset, int whence = SEEK_SET) + { + /* Seeking is not support by this file handler */ + return -ESPIPE; + } + + virtual off_t size() + { + /* Size is not defined for this file handle */ + return -EINVAL; + } + + virtual int isatty() + { + /* File handle is used for terminal output */ + return true; + } + + virtual int close() + { + return 0; + } +}; + +#endif diff --git a/hal/itm_api.h b/hal/itm_api.h new file mode 100644 index 00000000000..0c5a739c43d --- /dev/null +++ b/hal/itm_api.h @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_ITM_API_H +#define MBED_ITM_API_H + +#if defined(DEVICE_ITM) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup hal_itm_port ITM Stimulus Ports + * + * @{ + */ + +enum { + ITM_PORT_SWO = 0 +}; + +/**@}*/ + +/** + * \defgroup itm_hal Instrumented Trace Macrocell HAL API + * @{ + */ + +/** + * @brief Target specific initialization function. + * This function is responsible for initializing and configuring + * the debug clock for the ITM and setting up the SWO pin for + * debug output. + * + * The only Cortex-M register that should be modified is the clock + * prescaler in TPI->ACPR. + * + * The generic mbed_itm_init initialization function will setup: + * + * ITM->LAR + * ITM->TPR + * ITM->TCR + * ITM->TER + * TPI->SPPR + * TPI->FFCR + * DWT->CTRL + * + * for SWO output on stimulus port 0. + */ +void itm_init(void); + +/** + * @brief Initialization function for both generic registers and target specific clock and pin. + */ +void mbed_itm_init(void); + +/** + * @brief Send data over ITM stimulus port. + * + * @param[in] port The stimulus port to send data over. + * @param[in] data The data to send. + * + * @return value of data sent. + */ +uint32_t mbed_itm_send(uint32_t port, uint32_t data); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /* MBED_ITM_API_H */ diff --git a/hal/mbed_itm_api.c b/hal/mbed_itm_api.c new file mode 100644 index 00000000000..5826570be21 --- /dev/null +++ b/hal/mbed_itm_api.c @@ -0,0 +1,87 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(DEVICE_ITM) + +#include "hal/itm_api.h" +#include "cmsis.h" + +#include + +#define ITM_ENABLE_WRITE 0xC5ACCE55 + +#define SWO_NRZ 0x02 +#define SWO_STIMULUS_PORT 0x01 + +void mbed_itm_init(void) +{ + static bool do_init = true; + + if (do_init) { + do_init = false; + + itm_init(); + + /* Enable write access to ITM registers. */ + ITM->LAR = ITM_ENABLE_WRITE; + + /* Trace Port Interface Selected Pin Protocol Register. */ + TPI->SPPR = (SWO_NRZ << TPI_SPPR_TXMODE_Pos); + + /* Trace Port Interface Formatter and Flush Control Register */ + TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos); + + /* Data Watchpoint and Trace Control Register */ + DWT->CTRL = (1 << DWT_CTRL_CYCTAP_Pos) | + (0xF << DWT_CTRL_POSTINIT_Pos) | + (0xF << DWT_CTRL_POSTPRESET_Pos) | + (1 << DWT_CTRL_CYCCNTENA_Pos); + + /* Trace Privilege Register. + * Disable access to trace channel configuration from non-privileged mode. + */ + ITM->TPR = 0x0; + + /* Trace Control Register */ + ITM->TCR = (1 << ITM_TCR_TraceBusID_Pos) | + (1 << ITM_TCR_DWTENA_Pos) | + (1 << ITM_TCR_SYNCENA_Pos) | + (1 << ITM_TCR_ITMENA_Pos); + + /* Trace Enable Register */ + ITM->TER = SWO_STIMULUS_PORT; + } +} + +uint32_t mbed_itm_send(uint32_t port, uint32_t data) +{ + /* Check if ITM and port is enabled */ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & (1UL << port) ) != 0UL) ) /* ITM Port enabled */ + { + /* write data to port */ + ITM->PORT[port].u32 = data; + + /* Wait until data has been clocked out */ + while (ITM->PORT[port].u32 == 0UL) { + __NOP(); + } + } + + return data; +} + +#endif // defined(DEVICE_ITM) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/itm_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/itm_api.c new file mode 100644 index 00000000000..593ef6b6f91 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/itm_api.c @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(DEVICE_ITM) + +#include "hal/itm_api.h" + +#include "nrf.h" +#include "nrf5x_lf_clk_helper.h" + +/* SWO frequency: 4000 kHz */ +void itm_init(void) +{ + /* Enable SWO trace functionality */ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + + /* set SWO clock speed to 4 MHz */ + NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) | + (CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos); + + /* set SWO pin */ + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | + (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | + (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + + /* set prescaler */ + TPI->ACPR = 0; +} + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/itm_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/itm_api.c new file mode 100644 index 00000000000..0e04f8e3271 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/itm_api.c @@ -0,0 +1,107 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(DEVICE_ITM) + +#include "hal/itm_api.h" +#include "cmsis.h" +#include "em_cmu.h" + +#include + +/* SWO frequency: 875 kHz */ +static void setupSWOForPrint(void) +{ +#if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK ) + // Enable GPIO clock. +#if defined( _CMU_HFPERCLKEN0_GPIO_MASK ) + CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; +#elif defined( _CMU_HFBUSCLKEN0_GPIO_MASK ) + CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO; +#endif + + // Enable Serial wire output pin +#if defined( _GPIO_ROUTE_SWOPEN_MASK ) + GPIO->ROUTE |= GPIO_ROUTE_SWOPEN; +#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK ) + GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN; +#endif +#endif + +#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_LEOPARD_FAMILY) || defined(_EFM32_WONDER_FAMILY) || defined(_EFM32_PEARL_FAMILY) + // Set location 0 +#if defined( _GPIO_ROUTE_SWOPEN_MASK ) + GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC0; +#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK ) + GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~(_GPIO_ROUTELOC0_SWVLOC_MASK)) | GPIO_ROUTELOC0_SWVLOC_LOC0; +#endif + + // Enable output on pin - GPIO Port F, Pin 2 + GPIO->P[5].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK); + GPIO->P[5].MODEL |= GPIO_P_MODEL_MODE2_PUSHPULL; +#else + // Set location 1 + GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC1; + + // Enable output on pin + GPIO->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK); + GPIO->P[2].MODEH |= GPIO_P_MODEH_MODE15_PUSHPULL; +#endif + + // Enable debug clock AUXHFRCO + CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN; + + // Wait until clock is ready + while (!(CMU->STATUS & CMU_STATUS_AUXHFRCORDY)); + + // Enable trace in core debug + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + /* Set TPIU prescaler for the current debug clock frequency. Target frequency + is 875 kHz so we choose a divider that gives us the closest match. + Actual divider is TPI->ACPR + 1. */ + uint32_t freq = CMU_ClockFreqGet(cmuClock_DBG) + (875000 / 2); + uint32_t div = freq / 875000; + TPI->ACPR = div - 1; +} + +static bool swoIsInitd() +{ +#if defined( _CMU_HFPERCLKEN0_GPIO_MASK ) + return ((CMU->HFPERCLKEN0 & CMU_HFPERCLKEN0_GPIO) && + (GPIO->ROUTE & GPIO_ROUTE_SWOPEN) && + (CMU->STATUS & CMU_STATUS_AUXHFRCORDY) && + (CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)); +#elif defined( _CMU_HFBUSCLKEN0_GPIO_MASK ) + return ((CMU->HFBUSCLKEN0 & CMU_HFBUSCLKEN0_GPIO) && + (GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN) && + (CMU->STATUS & CMU_STATUS_AUXHFRCORDY) && + (CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)); +#endif +} + +// As SWO has to be accessible everywhere, including ISRs, we can't easily +// communicate the dependency on clocks etc. to other components - so this +// function checks that things appear to be set up, and if not re-configures +// everything +void itm_init(void) +{ + if(!swoIsInitd()) { + setupSWOForPrint(); + } +} + +#endif diff --git a/targets/targets.json b/targets/targets.json index 8479326a9c7..016be1aeede 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2773,7 +2773,7 @@ "EFM32GG_STK3700": { "inherits": ["EFM32GG990F1024"], "progen": {"target": "efm32gg-stk"}, - "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"], + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH", "ITM"], "forced_reset_timeout": 2, "config": { "hf_clock_src": { @@ -3443,7 +3443,7 @@ "inherits": ["Target"], "core": "Cortex-M4F", "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"], - "device_has": ["STCLK_OFF_DURING_SLEEP"], + "device_has": ["STCLK_OFF_DURING_SLEEP", "ITM"], "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"], "OUTPUT_EXT": "hex", "is_disk_virtual": true, @@ -3546,7 +3546,7 @@ "inherits": ["Target"], "core": "Cortex-M4F", "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"], - "device_has": ["STCLK_OFF_DURING_SLEEP"], + "device_has": ["STCLK_OFF_DURING_SLEEP", "ITM"], "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"], "OUTPUT_EXT": "hex", "is_disk_virtual": true,