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standardise QSPI pin names #7817

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merged 2 commits into from Aug 24, 2018

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@maciejbocianski
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maciejbocianski commented Aug 17, 2018

Description

This PR is continuation of work on PR #7639

This PR try to standardise QSPI pin naming scheme to new format:
QSPI_FLASHn_XXX: for pins connected to the onboard flash
QSPIn_XXX: for pins available on external connector

Some targets support Dual-Flash, hence added port indexing (1, 2) to distinct which port is actually utilized

After more profound analysis of schematics and specs, it's not clear that any of targets allow to utilize two QSPI interfaces on external connectors. For all targets with dual-QSPI capable SoC (currently only STM platforms) specs clearly describes only one interface when it's routed to onboard flash or routed out to external connector.

@jeromecoutant @adustm can you help to figure out which targets can utilize both QSPI interfaces ont external connectors (targets marked with QSPI2??? on the list below)

@donatieng @bulislaw When it will be clear that any of targets support more then one QSPI interface on external connectors, then we could get back to discussion about QSPI_COUNT/QSPI_FLASH_COUNT

NOTE

This PR is not ready and cannot be merge until PR #7783 will be merged

Pull request type

[ ] Fix
[ ] Refactor
[ ] Target update
[X] Functionality change
[ ] Breaking change

List of targets with QSPI interace

  • ARM_SSG

    • BEETLE - has 2MB of external QSPI flash (no pin definions) is this target actively supported ???
    • MUSCA - in development
  • Freescale

    • K82F - in development
    • KL82Z - in development
  • NXP

    • MIMXRT1050 - 64Mbit QSPI Flash; - in development?
    • LPCXpresso54608 - 128 Mb Micron MT25QL128 Quad-SPI flash; - in development
    • LPC408X - in development?
  • Silicon Labs

    • EFM32GG11_STK3701 Giant Gecko - in development?
  • NORDIC

    • NRF52840 - QSPI1/QSPI_FLASH1
  • STM

    • NUCLEO_F412ZG - QSPI1/QSPI2???
    • DISCO_F413ZH - QSPI_FLASH1
    • NUCLEO_F413ZH - QSPI1/QSPI2???
    • NUCLEO_F446RE - needs driver QSPI pins definion fix
    • NUCLEO_F446ZE - QSPI1/QSPI2???
    • DISCO_F469NI - QSPI_FLASH1/QSPI2???
    • DISCO_F746NG - QSPI_FLASH1
    • NUCLEO_F746ZG - QSPI1
    • NUCLEO_F756ZG - QSPI1
    • NUCLEO_F767ZI - QSPI1
    • DISCO_F769NI - QSPI_FLASH1
    • NUCLEO_L432KC - QSPI1
    • NUCLEO_L433RC_P - QSPI1
    • DISCO_L475VG_IOT01A - QSPI_FLASH1
    • DISCO_L476VG - QSPI1/QSPI_FLASH1
    • NUCLEO_L476RG - no pins available
    • NUCLEO_L486RG - no pins available???
    • DISCO_L496AG - QSPI_FLASH1/QSPI2??
    • NUCLEO_L496ZG - QSPI1/QSPI2???

@cmonr cmonr requested review from jeromecoutant, offirko, 0xc0170, ARMmbed/mbed-os-hal and marcuschangarm Aug 17, 2018

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cmonr commented Aug 17, 2018

@maciejbocianski For clarity, is this dependent on #7639 or #7783?
Does #7639 still need to remain open?

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maciejbocianski commented Aug 17, 2018

@cmonr it's dependent only on #7783. #7639 has been closed.

QSPI_FLASH1_IO2 = PE_14,
QSPI_FLASH1_IO3 = PE_15,
QSPI_FLASH1_SCK = PE_10,
QSPI_FLASH1_CSN = PE_10,

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@offirko

offirko Aug 19, 2018

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PE_11 ?

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@maciejbocianski maciejbocianski force-pushed the maciejbocianski:qspi_pinnames branch 4 times, most recently from d4e4d64 to 7c2a42c Aug 20, 2018

@0xc0170 0xc0170 added needs: review and removed needs: work labels Aug 20, 2018

@bulislaw

Looks good, can you modify the porting guide mentioning the standard names for QSPI.

@donatieng

Thanks @maciejbocianski, happy with this new approach.

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maciejbocianski commented Aug 22, 2018

@cmonr cmonr added the risk: G label Aug 23, 2018

@maciejbocianski maciejbocianski force-pushed the maciejbocianski:qspi_pinnames branch from 7c2a42c to 9a41043 Aug 24, 2018

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maciejbocianski commented Aug 24, 2018

PR updated and rebased.
Ready to proceed

@0xc0170 0xc0170 requested a review from adustm Aug 24, 2018

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0xc0170 commented Aug 24, 2018

/morph build

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mbed-ci commented Aug 24, 2018

Build : SUCCESS

Build number : 2892
Build artifacts/logs : http://mbed-os.s3-website-eu-west-1.amazonaws.com/?prefix=builds/7817/

Triggering tests

/morph test
/morph uvisor-test
/morph export-build
/morph mbed2-build

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@0xc0170 0xc0170 added ready for merge and removed needs: CI labels Aug 24, 2018

@0xc0170 0xc0170 merged commit 31a6fb4 into ARMmbed:master Aug 24, 2018

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@cmonr cmonr removed the risk: G label Aug 25, 2018

stevew817 added a commit to SiliconLabs/mbed-os that referenced this pull request Aug 27, 2018

Apply changes corresponding to ARMmbed#7817
QSPI standard pin names were changed after the QSPI feature PR.

JarkkoPaso added a commit to JarkkoPaso/mbed-os that referenced this pull request Aug 29, 2018

Apply changes corresponding to ARMmbed#7817
QSPI standard pin names were changed after the QSPI feature PR.

pan- pushed a commit to pan-/mbed that referenced this pull request Aug 29, 2018

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bcostm commented Aug 30, 2018

@jeromecoutant @adustm can you help to figure out which targets can utilize both QSPI interfaces ont external connectors (targets marked with QSPI2??? on the list below)

In the board's PeripheralPins.c file we have added a comment describing where each pins are connected. If there is nothing mentioned that means the pin is normally accessible on the Morpho connector (for Nucleo boards).

Example with NUCLEO_F412ZG:

MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
    {PA_1,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // QUADSPI_BK1_IO3
    {PA_6,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // QUADSPI_BK2_IO0
    {PA_7,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // QUADSPI_BK2_IO1
...
    {PE_7,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // QUADSPI_BK2_IO0
    {PE_8,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // QUADSPI_BK2_IO1
...

The QSPI2_IO0 (mentioned QUADSPI_BK2_IO0 in the comment) can be configured using either PA_6 or PE_7. These 2 pins can be accessed on the CN11/CN12 headers.

Example with DISCO_F469NI:

MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
...
    {PE_7,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // QUADSPI_BK2_IO0 // Connected to D4
    {PE_8,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // QUADSPI_BK2_IO1 // Connected to D5
    {PE_9,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // QUADSPI_BK2_IO2 // Connected to D6
    {PE_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // QUADSPI_BK2_IO3 // Connected to D7
...
    {PG_9,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // QUADSPI_BK2_IO2 // Connected to USART6_RX
    {PG_14,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // QUADSPI_BK2_IO3 // Connected to ARDUINO USART6_TX
    {PH_2,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // QUADSPI_BK2_IO0 // Connected to SDCKE0 [MT48LC4M32B2B5-6A_CKE]
    {PH_3,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // QUADSPI_BK2_IO1 // Connected to SDNE0 [MT48LC4M32B2B5-6A_CS]
...

Here the QSPI2 pins are accessible on Arduino D4 to D7 but also on another component on the board. So it will be difficult to use these pins.

Example with DISCO_L496AG:

MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
...
    {PC_2,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK2_IO1 // Connected to DF_CKOUT
    {PC_3,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK2_IO2 // Connected to ARD_A2
    {PC_4,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK2_IO3 // Connected to ARD_A0
    {PC_11,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)},  // QUADSPI_BK2_NCS // Connected to uSD_D3
...
    {PD_4,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK2_IO0 // Connected to OE [OE_IS66WV51216EBLL]
    {PD_5,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK2_IO1 // Connected to WE [WE_IS66WV51216EBLL]

Same as above. The QSPI2 pins are connected to other components.

So, this has to be checked carefully board by board... But for what I see only the QSPI2 pins available on Nucleo boards (not Disco) can be used. Hope this helps...

cmonr added a commit to SeppoTakalo/mbed-os that referenced this pull request Sep 1, 2018

Apply changes corresponding to ARMmbed#7817
QSPI standard pin names were changed after the QSPI feature PR.
@jeromecoutant

Please take into account comments for next PR
Thx

@@ -307,6 +307,14 @@ typedef enum {
SYS_WKUP2 = PC_0,
SYS_WKUP3 = PC_1,
/**** QSPI pins ****/

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jeromecoutant Sep 5, 2018

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There is no QSPI in NUCLEO_F412...

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@bcostm

bcostm Sep 5, 2018

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There is no QSPI Flash memory on the board but the STM32F412 has a QSPI peripheral. This is why these macros have a different name (no FLASHn), for what I understood...

@@ -306,6 +306,14 @@ typedef enum {
SYS_WKUP2 = PC_0,
SYS_WKUP3 = PC_1,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,

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jeromecoutant Sep 5, 2018

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There is no QSPI in NUCLEO_F413...

@@ -325,6 +325,14 @@ typedef enum {
SYS_WKUP0 = PA_0,
SYS_WKUP1 = PC_13,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,

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jeromecoutant Sep 5, 2018

Contributor

There is no QSPI in NUCLEO_F446...

@@ -354,6 +354,14 @@ typedef enum {
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
/**** QSPI pins ****/
QSPI_FLASH1_IO0 = PD_11,

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jeromecoutant Sep 5, 2018

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There is no QSPI in NUCLEO_F746...

@@ -354,6 +354,14 @@ typedef enum {
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,

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@jeromecoutant

jeromecoutant Sep 5, 2018

Contributor

There is no QSPI in NUCLEO_F756...

@@ -359,6 +359,14 @@ typedef enum {
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
/**** QSPI pins ****/
QSPI1_IO0 = PD_11,

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jeromecoutant Sep 5, 2018

Contributor

There is no QSPI in NUCLEO_F767...

@@ -159,6 +159,15 @@ typedef enum {
SYS_WKUP1 = PA_0,
SYS_WKUP4 = PA_2,
/**** QSPI pins ****/
QSPI1_IO0 = PB_1,

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@jeromecoutant

jeromecoutant Sep 5, 2018

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There is no QSPI in NUCLEO_L432...

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@0xc0170

0xc0170 Sep 5, 2018

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Thanks @jeromecoutant , we will review

@@ -236,6 +236,14 @@ typedef enum {
SYS_WKUP2 = PC_13,
SYS_WKUP4 = PA_2,
/**** QSPI pins ****/
QSPI1_IO0 = PB_1,
QSPI1_IO1 = PB_0,

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@jeromecoutant

jeromecoutant Sep 5, 2018

Contributor

There is no QSPI in NUCLEO_L433...

@@ -258,6 +258,22 @@ typedef enum {
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
/**** QSPI pins ****/
QSPI1_IO0 = PE_12,
QSPI1_IO1 = PE_13,

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@jeromecoutant

jeromecoutant Sep 5, 2018

Contributor

Keeping QSPI1_Ixx definition is not useful

@@ -317,6 +317,14 @@ typedef enum {
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
/**** QSPI pins ****/
QSPI1_IO0 = PE_12,
QSPI1_IO1 = PB_0,

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@jeromecoutant

jeromecoutant Sep 5, 2018

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There is no QSPI in NUCLEO_L496...

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@maciejbocianski

maciejbocianski Sep 5, 2018

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@jeromecoutant so why QSPI pins are configured in

//*** QUADSPI ***
MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
{PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Only STM32L496ZG, not STM32L496ZG-P
{PC_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0
{PC_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1
{PC_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2
{PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS
{PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS
{PD_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0
{PD_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1
{PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_IO1
{PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2
{PD_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
{PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
{PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
{PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
{PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, // QUADSPI_CLK
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
{PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Only STM32L496ZG, not STM32L496ZG-P
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS
{PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
{NC, NC, 0}
};

and described as routed out to external connector in NUCLEO_L496ZG scheme?

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@jeromecoutant

jeromecoutant Sep 5, 2018

Contributor

STM32L496ZG chip have some QSPI pins.

NUCLEO board doesn't have QSPI embedded memory.
If a customer is connecting one, he can.

@stevew817 stevew817 referenced this pull request Sep 7, 2018

Merged

OOB Issue fixes #13

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