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FUTURE_SEQUANA_PSA: fixed deep sleep mode #9678

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merged 1 commit into from Feb 13, 2019

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@lrusinowicz
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commented Feb 12, 2019

Description

Enabled tickless mode for Sequana PSA M0 core code to allow it to enter
deep sleep mode. This fixes issue #9094 where tests were failing due to
M0 core not entering deep sleep mode, blocking the whole chip.
Fixed incorrect resource management on M0 core, which crashed tickless
mode.

Pull request type

[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change

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@orenc17

FUTURE_SEQUANA_PSA: fixed deep sleep mode
Enabled tickless mode for Sequana PSA M0 core code to allow it to enter
deep sleep mode. This fixes issue #9094 where tests were failing due to
M0 core not entering deep sleep mode, blocking the whole chip.
Fixed incorrect resource management on M0 core, which crashed tickless
mode.
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commented Feb 12, 2019

I've just noticed a conflict with #9666, so I will need to rebase it after #966 is merged in.

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commented Feb 12, 2019

@lrusinowicz, thank you for your changes.
@orenc17 @ARMmbed/mbed-os-maintainers please review.

@ciarmcom ciarmcom requested review from orenc17 and ARMmbed/mbed-os-maintainers Feb 12, 2019

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commented Feb 12, 2019

@lrusinowicz if #9666 is merged before please regenerate the binaries again

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commented Feb 12, 2019

@lrusinowicz if #9666 is merged before please regenerate the binaries again

@orenc17 Do you mean #9633? Because #9666 does not have a 'merged' status.

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commented Feb 12, 2019

@lrusinowicz if #9666 is merged before please regenerate the binaries again

@orenc17 Do you mean #9633? Because #9666 does not have a 'merged' status.

@lrusinowicz both
#9633 is the feature
#9666 is the actual implementation on FUTURE_SEQUANA_PSA

@ciarmcom ciarmcom requested a review from orenc17 Feb 12, 2019

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commented Feb 12, 2019

@lrusinowicz, thank you for your changes.
@orenc17 @ARMmbed/mbed-os-maintainers please review.

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commented Feb 12, 2019

Hmm, there was some back and forth, so making sure I understand.

@orenc17
Between this PR and #9666, once either is merged, the other will need to rebase and include an updated binary?

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LGTM. Will reapprove once question about magic number is addressed.

ipc_intr_Config.cm0pSrc = (cy_en_intr_t)cpuss_interrupts_ipc_0_IRQn + SPM_IPC_NOTIFY_CM0P_INTR; // Must match the interrupt we trigger using NOTIFY on CM4
ipc_intr_Config.intrPriority = 1;
if (cy_m0_nvic_reserve_channel(CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX, CY_PSA_MAILBOX_IRQN_ID) == (IRQn_Type)(-1)) {

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-1 is oddly specific. What does the magic number map to?

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lrusinowicz Feb 13, 2019

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It refers to targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/psoc6_utils.h:

 *
 * \param channel IRQn_Type     Channel to be reserved.
 * \param allocation_id uint32_t    Identifier.
 * \return  IRQ channel allocated or (-1) if no free channel is available.
 *
 */
IRQn_Type cy_m0_nvic_reserve_channel(IRQn_Type channel, uint32_t allocation_id);

Yeah, it's sloppy. But fixing this requires a global HAL implementation change, that I would rather prepare as a separate PR.

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commented Feb 12, 2019

Hmm, there was some back and forth, so making sure I understand.

@orenc17
Between this PR and #9666, once either is merged, the other will need to rebase and include an updated binary?

@cmonr, correct

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commented Feb 12, 2019

CI started

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commented Feb 12, 2019

Making a note here to prefer this PR over #9666 if it comes down to it.

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commented Feb 13, 2019

Test run: SUCCESS

Summary: 12 of 12 test jobs passed
Build number : 1
Build artifacts

@0xc0170 0xc0170 merged commit ba7aa88 into ARMmbed:master Feb 13, 2019

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commented Feb 21, 2019

PSA PR. Bumped to 5.12

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