The KM_centroids_kernel_accel IP is used for the training of KMeans applications. It is produced with SDSoC 2016.2 version.
The code provided in this folder is a C-based implementation of 'Partial Centroids Calculation (counts, sums)' for KMeans Training, optimized for ZC702 board, and is a case study of FPGA-Accelerated Machine Learning in Cloud Computing.
Testing KMeans kernel in Software (Intel)
make. (-O3 optimizations)
- 'chunkSize' is the size of the data chunk (max: 5000).
Testing KMeans kernel in Hardware
The C++ source files are provided here without project files, but they contain HLS/SDS directives specific to Xilinx SDSoC.
!The code of the hardware function is not fully annotated and contains only interface directives.!
If you want to create a SDSoC project using these sources you may find the following instructions helpful:
- Launch SDSoC and create a new empty project. Choose
zc702as target platform.
- Add the C++ sources in
KM_centroids_kernel_accelas hardware function. Set clock frequency at
- All design parameters are set in the file
Generate SD Card Image.
|Speedup (vs Intel)||4.05|
|HW accelerated (Estimated time)||58 msec|
|HW accelerated (Measured time)||57 msec|
Resource utilization estimates for hardware accelerator
For any question or discussion, please contact the authors: