The LR_gradients_kernel_accel IP is used for the training of Logistic Regression applications. It is produced with SDSoC 2016.2 version.
The code provided in this folder is a C-based implementation of 'Batch Gradient Descent Algorithm' for Logistic Regression Training, optimised for ZED board, and is a case study of FPGA-Accelerated Machine Learning in Cloud Computing.
Testing Logistic Regression example in Software (Intel)
make. (also extracts datasets)
- 'chunkSize' is the size of each data chunk (max: 5000).
- 'alpha' is the learning rate.
- 'iteration' is the number of iterations.
Testing Logistic Regression example in Hardware
The C++ source files are provided here without project files, but they contain HLS/SDS directives specific to Xilinx SDSoC.
!The code of the hardware function is not fully annotated and contains only interface directives.!
If you want to create a SDSoC project using these sources you may find the following instructions helpful:
- Launch SDSoC and create a new empty project. Choose
zedas target platform.
- Add the C++ sources in
LR_gradients_kernel_accelas hardware function. Set clock frequency at
- All design parameters are set in the file
Generate SD Card Image.
|Speedup (vs Intel)||5.89|
|HW accelerated (Estimated time)||48 msec|
|HW accelerated (Measured time)||47 msec|
Resource utilization estimates for hardware accelerator
For any question or discussion, please contact the authors: