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Logistic Regression

The LR_gradients_kernel_accel IP is used for the training of Logistic Regression applications. It is produced with SDSoC 2016.2 version.

The code provided in this folder is a C-based implementation of 'Batch Gradient Descent Algorithm' for Logistic Regression Training, optimised for ZED board, and is a case study of FPGA-Accelerated Machine Learning in Cloud Computing.

Testing Logistic Regression example in Software (Intel)

  1. Compiling
    1. Run make. (also extracts datasets)
  2. Execution
    1. Edit conf. (optional)
      1. 'chunkSize' is the size of each data chunk (max: 5000).
      2. 'alpha' is the learning rate.
      3. 'iteration' is the number of iterations.
    2. Run ./LogisticRegression.

Testing Logistic Regression example in Hardware

The C++ source files are provided here without project files, but they contain HLS/SDS directives specific to Xilinx SDSoC.

!The code of the hardware function is not fully annotated and contains only interface directives.!

If you want to create a SDSoC project using these sources you may find the following instructions helpful:

  1. Launch SDSoC and create a new empty project. Choose zed as target platform.
  2. Add the C++ sources in src/ and set LR_gradients_kernel_accel as hardware function. Set clock frequency at 142.86 MHz.
  3. All design parameters are set in the file src/accelerator.h.
  4. Select Generate Bitstream and Generate SD Card Image.
  5. Run SDRelease.

Performance (LR_gradients_kernel, 5000 chunkSize)

Speedup (vs Intel) 5.89
SW-only ARM Cortex-A9 @ 666.67MHz (Measured time) 1003 msec
SW-only Intel Core i5-5200U @ 2.20GHz (Measured time) 277 msec
HW accelerated (Estimated time) 48 msec
HW accelerated (Measured time) 47 msec

Resource utilization estimates for hardware accelerator

Resource Used Total % Utilization
DSP 160 220 72.73
BRAM 42 140 30
LUT 44491 53200 83.63
FF 48292 106400 45.39


For any question or discussion, please contact the authors:

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