This repository contains several Verilog codes and .bsf files created for different purposes.
Each file demonstrates a specific digital design or function.
| File Name | Description |
|---|---|
| `` | . |
| `` | . |
| `` | . |
| `` | . |
| `` | . |
| `` | . |
| `` | . |
| `` |
- Language: Verilog
- Synthesis: Quartus
- Simulator: ModelSim
This repository is part of my portfolio, showcasing my skills in Verilog programming and digital logic design.
This project is open-source for learning and demonstration purposes.