most of this shit works now

design_files/ah_func/ah_func.v

@@ -0,0 +1,76 @@
+module ah_func(	clk,
+				dataa,
+				datab,
+				result
+			);
+
+parameter thirty_two	= 32'h00000000;
+parameter fixed_one 	= 32'h20000000;
+parameter fixed_zero 	= 32'h00000000;
+
+input 	[31:0] dataa, datab;
+output 	[31:0] result;		
+
+//Stage 1 => buffer the inputs
+
+wire [31:0] a_buf, b_buf;
+
+`define STAGES 20
+ahfp_pipeline_buffer buf_a (clk, dataa, a_buf);
+ahfp_pipeline_buffer buf_b (clk, datab, b_buf);		
+`undef STAGES							
+//Stage 1 => get the floor result
+
+wire 	[31:0] floor_res;
+reg		[31:0] floor_res_reg;
+
+ahfp_floor_divide_four floor (dataa, floor_res);
+always @(posedge clk) begin
+	floor_res_reg <= floor_res;
+end
+
+//Stage 2 => subtract floor result from 
+
+wire [31:0] floor_sub_res;
+
+ahfp_add_sub_multi sub (clk,floor_res_reg,thirty_two,floor_sub_res);
+
+//Stage 3 => cos of the floor sub result
+
+//TODO: get modulo of result
+
+//convert to fixed
+wire 	[31:0] fixed_theta_in;
+reg 	[31:0] fixed_theta_in_reg;
+ahfp_float_2_fixed float_2_fixed (floor_sub_res,fixed_theta_in);
+always @(posedge clk) begin
+	fixed_theta_in_reg <= fixed_theta_in;
+end
+
+//calculate cos
+wire	[31:0] cos;
+ahfp_cordic_fixed cordic (fixed_one,fixed_zero,fixed_theta_in_reg,cos);
+
+//convert back to float
+wire 	[31:0] float_cos_out;
+wire 	[31:0] float_cos_out_reg;
+ahfp_fixed_2_float fixed_2_float (cos,float_cos_out);
+always @(posedge clk) begin
+	float_cos_out_reg <= float_cos_out;
+end
+
+//Stage 4 => multiply with cos and add 1
+
+//buffer x again, after getting it
+`define STAGES 5
+wire [31:0] x_buf;
+
+`undef STAGES
+wire [31:0] mul_cos_res;
+wire [31:0] cos_add_one_res;
+ahfp_mul_multi mul_cos (clk, float_cos_out_reg, {a_buf[31],a_buf[30:23]+1,a_buf[22:0]}, mul_cos_res);
+ahfp_add_sub_multi cos_add_one (clk, mul_cos_res, float_one, cos_add_one_res); 
+
+
+
+endmodule

design_files/ahfp_add_multi/ahfp_add_multi.v

@@ -102,7 +102,7 @@ always @ (posedge clk) begin
 	//Stage 7
 	res <= underflow ? 32'd0 
 	                : overflow ? {z_s_final, 31'h7F800000}
-					: {z_s_final, z_e_final, z_m_final};
+					: {z_s_final, z_e_final[7:0], z_m_final[22:0]};
 	///////////////
 	end
 

design_files/ahfp_add_multi/ahfp_add_multi_tb.v

@@ -8,13 +8,14 @@ reg clk;
 reg [31:0] dataa,datab,result_correct;
 wire [31:0] result;
 
-ahfp_add dut (	.dataa(dataa),
-		.datab(datab),
-		.result(result));
+ahfp_add_multi dut (.clk(clk),
+					.dataa(dataa),
+					.datab(datab),
+					.result(result));
 
 initial // Clock generator
   begin
-    clk = 0;
+    clk = 1;
     forever #10 clk = !clk;
   end
 

design_files/ahfp_add_multi/ahfp_add_multi_test.tcl

@@ -0,0 +1,41 @@
+# make work directory
+vlib work
+vmap work work
+
+# compile design
+vlog -reportprogress 300 -work work C:/Users/Alex/DSD_v2/design_files/ahfp_add_multi/ahfp_add_multi.v
+vlog -reportprogress 300 -work work C:/Users/Alex/DSD_v2/design_files/ahfp_add_multi/ahfp_add_multi_tb.v
+
+# simulate design
+vsim -c work.ahfp_add_multi
+vsim -c work.test_ahfp_add_multi
+
+#window views
+#view objects
+#view locals
+#view source
+view transcript
+view wave -undock
+
+#add all waves to wave view
+add wave *
+
+add wave -position insertpoint  \
+sim:/test_ahfp_add_multi/dut/e_tmp
+add wave -position insertpoint  \
+sim:/test_ahfp_add_multi/dut/m_tmp
+add wave -position insertpoint  \
+sim:/test_ahfp_add_multi/dut/z_e
+add wave -position insertpoint  \
+sim:/test_ahfp_add_multi/dut/z_m
+add wave -position insertpoint  \
+sim:/test_ahfp_add_multi/dut/a_m_tmp
+add wave -position insertpoint  \
+sim:/test_ahfp_add_multi/dut/b_m_tmp
+add wave -position insertpoint  \
+sim:/test_ahfp_add_multi/dut/a_e_tmp
+add wave -position insertpoint  \
+sim:/test_ahfp_add_multi/dut/b_e_tmp
+
+#run simulation
+run 500

design_files/ahfp_add_sub_multi/ahfp_add_sub_multi.v

@@ -1,6 +1,5 @@
 //TODO: 
 // - create a testbench
-
 module ahfp_add_sub_multi(
 	clk,
 	dataa,
@@ -27,20 +26,25 @@ wire out_mux, out_mux_buf;
 // 0 - addition
 // 1 - subtraction
 
-`define STAGES 5
+`define STAGES 7
+`define WIDTH 1
+`include "../ahfp_pipeline_buffer/ahfp_pipeline_buffer.v"
 ahfp_pipeline_buffer buffer(.clk(clk),
 							.in(out_mux),
 							.out(out_mux_buf)
 							);
 
 `undef STAGES
-
+`undef WIDTH				
+
+`include "../ahfp_add_multi/ahfp_add_multi.v"
 ahfp_add_multi add (.clk(clk),
 					.dataa(add_a),
 					.datab(add_b),
 					.result(add_res)
 					);
 
+`include "../ahfp_sub_multi/ahfp_sub_multi.v"
 ahfp_sub_multi sub (.clk(clk),
 					.dataa(sub_a),
 					.datab(sub_b),

design_files/ahfp_add_sub_multi/ahfp_add_sub_tb.v → design_files/ahfp_add_sub_multi/ahfp_add_sub_multi_tb.v

@@ -2,17 +2,18 @@
 // testbench reference: https://people.ece.cornell.edu/land/courses/ece5760/Verilog/LatticeTestbenchPrimer.pdf
 
 `timescale 1ns / 1ns
-module test_ahfp_add_sub;
+module test_ahfp_add_sub_multi;
+`define DELAY 7
 
 reg clk;
 reg [31:0] 	dataa, datab, result_correct;
 wire [31:0] result;
 
-ahfp_add_sub dut (	.clk(clk),
-					.dataa(dataa),
-					.datab(datab),
-					.result(result)
-					);
+ahfp_add_sub_multi dut (.clk(clk),
+						.dataa(dataa),
+						.datab(datab),
+						.result(result)
+						);
 
 initial // Clock generator
   begin
@@ -26,52 +27,52 @@ initial
 		//test 1 (time 0ns)
 		dataa 			<= #0 	32'h00000000;
 		datab			<= #0 	32'h3F800000;
-		result_correct	<= #20 	32'h3F800000;
+		result_correct	<= #(20*`DELAY) 	32'h3F800000;
 
 		//test 2 (time 20ns)
 		dataa 			<= #20 	32'h3F800000;
 		datab			<= #20	32'h40000000;
-		result_correct	<= #40	32'h40400000;
+		result_correct	<= #(20*`DELAY +20)	32'h40400000;
 
 		//test 3 (time 40ns)
 		dataa 			<= #40 	32'hC0000000;
 		datab			<= #40	32'h40800000;
-		result_correct	<= #60	32'h40000000;
+		result_correct	<= #(20*`DELAY +40)	32'h40000000;
 
 		//test 4 (time 60ns)
 		dataa			<= #60	32'h40400000;
 		datab			<= #60	32'h40600000;
-		result_correct	<= #80	32'h40D00000;
+		result_correct	<= #(20*`DELAY +60)	32'h40D00000;
 
 		//test 5 (time 80ns)
 		dataa			<= #80	32'h43FA0000;
 		datab			<= #80	32'hC1133333;
-		result_correct	<= #100	32'h43F56666;
+		result_correct	<= #(20*`DELAY +80)	32'h43F56666;
 
 		//test 6 (time 100ns)
 		dataa			<= #100	32'h41EC0000;
 		datab			<= #100	32'h453BF800;
-		result_correct	<= #120	32'h453DD000;
+		result_correct	<= #(20*`DELAY +100)	32'h453DD000;
 
 		//test 7 (time 120ns)
 		dataa			<= #120	32'hC2FF999A;
 		datab			<= #120	32'h42FCCCCD;
-		result_correct	<= #140	32'hBFB33340;
+		result_correct	<= #(20*`DELAY +120)	32'hBFB33340;
 
 		//test 8 (time 140ns)
 		dataa			<= #140	32'h46A5E51F;
 		datab			<= #140	32'hC35FAB85;
-		result_correct	<= #160	32'h46A425C8;	
+		result_correct	<= #(20*`DELAY +140)	32'h46A425C8;	
 
 		//test 9 (time 160ns)
 		dataa			<= #160	32'hC640E400;
 		datab			<= #160	32'hC7F12040;
-		result_correct	<= #180	32'hC8049E60;		
+		result_correct	<= #(20*`DELAY +160)	32'hC8049E60;		
 
 		//test 10 (time 180ns)
 		dataa			<= #180	32'h3F8E363B;
 		datab			<= #180	32'h3AA137FA;
-		result_correct	<= #200	32'h3F8E5E89;	
+		result_correct	<= #(20*`DELAY +180)	32'h3F8E5E89;	
 	end
 
 initial

design_files/ahfp_add_sub_multi/ahfp_add_sub_multi_test.tcl

@@ -0,0 +1,33 @@
+# make work directory
+vlib work
+vmap work work
+
+# compile design
+vlog -reportprogress 300 -work work C:/Users/Alex/DSD_v2/design_files/ahfp_add_sub_multi/ahfp_add_sub_multi.v
+vlog -reportprogress 300 -work work C:/Users/Alex/DSD_v2/design_files/ahfp_add_sub_multi/ahfp_add_sub_multi_tb.v
+
+# simulate design
+vsim -c work.test_ahfp_add_sub_multi
+
+#window views
+#view objects
+#view locals
+#view source
+view transcript
+view wave -undock
+
+#add all waves to wave view
+add wave *
+
+
+add wave -position insertpoint  \
+sim:/test_ahfp_add_sub_multi/dut/sub_res
+add wave -position insertpoint  \
+sim:/test_ahfp_add_sub_multi/dut/add_res
+add wave -position insertpoint  \
+sim:/test_ahfp_add_sub_multi/dut/out_mux
+add wave -position insertpoint  \
+sim:/test_ahfp_add_sub_multi/dut/out_mux_buf
+
+#run simulation
+run 500

design_files/ahfp_cordic_fixed/ahfp_cordic_fixed.v

@@ -5,8 +5,7 @@ module ahfp_cordic( clk,
                     x_start,
                     y_start,
                     theta,
-                    x_cos,
-                    y_sin
+                    x_cos
                   );
 
   //parameters
@@ -19,7 +18,7 @@ module ahfp_cordic( clk,
   input [31:0] theta;
 
   //outputs
-  output [31:0] x_cos,y_sin;
+  output [31:0] x_cos;
 
   //variables
   reg [31:0] x [0:N-1];
@@ -78,7 +77,6 @@ module ahfp_cordic( clk,
   endgenerate
 
   assign x_cos = x[N-1];
-  assign y_sin = y[N-1];
 
 endmodule
 

design_files/ahfp_floor/ahfp_floor.v

@@ -1,4 +1,4 @@
-module floor(
+module ahfp_floor(
 	data,
 	result
 	);
@@ -12,10 +12,6 @@ module floor(
 	assign e = data[30:23];
 	assign m = data[22:0];
 
-	/*
-	TODO:
-	 - convert to a switch case set of statements
-	*/
 
 	wire [22:0] m_tmp;
 
@@ -42,13 +38,11 @@ module floor(
 					(e==8'd147) 	? m & 23'b11111111111111111111000 : 
 					(e==8'd148) 	? m & 23'b11111111111111111111100 : 
 					(e==8'd149) 	? m & 23'b11111111111111111111110 :  
-				m;
+					m;
 
-	assign result[30:23] 	= 	(data[31]==1'b1) ? 8'd0  :
-								(e<8'd127) 		 ? 8'd0  : e;
-	assign result[22:0]  	= 	(data[31]==1'b1) ? 23'd0 :
-								(e<8'd127) 		 ? 23'd0 : m_tmp;
+	assign result[30:23] 	=   (e<8'd127)  ? 8'd0  : e;
+	assign result[22:0]  	= 	(e<8'd127) 	? 23'd0 : m_tmp;
 
-	assign result[31]		= 1'b0;
+	assign result[31]		= data[31];
 
 endmodule

design_files/ahfp_floor/ahfp_floor_tb.v

@@ -2,14 +2,14 @@
 // testbench reference: https://people.ece.cornell.edu/land/courses/ece5760/Verilog/LatticeTestbenchPrimer.pdf
 
 `timescale 1ns / 1ns
-module test_floor;
+module test_ahfp_floor;
 
 reg clk;
 reg [31:0] data,result_correct;
 wire [31:0] result;
 
-floor dut (	.data(data),
-		.result(result));
+ahfp_floor dut (.data(data),
+			.result(result));
 
 initial // Clock generator
   begin

design_files/ahfp_floor/ahfp_floor_test.tcl

@@ -7,8 +7,8 @@ vlog -reportprogress 300 -work work C:/Users/Alex/DSD_v2/design_files/ahfp_floor
 vlog -reportprogress 300 -work work C:/Users/Alex/DSD_v2/design_files/ahfp_floor/ahfp_floor_tb.v
 
 # simulate design
-vsim -c work.floor
-vsim -c work.test_floor
+vsim -c work.ahfp_floor
+vsim -c work.test_ahfp_floor
 
 #window views
 #view objects