Permalink
Commits on Nov 15, 2018
  1. update test times to accommodate bios ramtest

    bunnie
    bunnie committed Nov 15, 2018
Commits on Nov 7, 2018
  1. update all the binaries and submodules

    bunnie
    bunnie committed Nov 7, 2018
  2. don't commit/store .o files

    bunnie
    bunnie committed Nov 7, 2018
  3. add code diagnostic readout, narrow torelance to 4.5%

    bunnie
    bunnie committed Nov 7, 2018
    5% is the total tolerance band we want to allow for
    supplies, but the jig itself has about a 0.3%+/-0.1% voltage
    accuracy. Set to 4.5% to accommodate worst case jig parametrics
    to guarantee no supply outside 5%. Should be minimal false
    negatives, most supplies will corner to within 3% tolerance
    if all the constituent components are correct.
Commits on Oct 29, 2018
  1. update README

    bunnie
    bunnie committed Oct 29, 2018
  2. update submodules

    bunnie
    bunnie committed Oct 29, 2018
  3. add a pass-test test

    bunnie
    bunnie committed Oct 29, 2018
  4. fix typo on ExecStopSuccess

    bunnie
    bunnie committed Oct 29, 2018
Commits on Oct 26, 2018
  1. update submodule dependency for tester images

    bunnie
    bunnie committed Oct 26, 2018
  2. update idcode to actual 100T idcode

    bunnie
    bunnie committed Oct 26, 2018
  3. add "quick" test scenario

    bunnie
    bunnie committed Oct 26, 2018
    This is a quick RAM test scenario for PCBA-only testing
Commits on Oct 25, 2018
  1. cleanup missing files, add systemd service files

    bunnie
    bunnie committed Oct 25, 2018
    systemd files also added in this commit
    
    see exclave.service; includes instructions on how to install/update
    the service
  2. full sequence for auto-full PCB tester complete

    bunnie
    bunnie committed Oct 25, 2018
    - ADC driver working now
    - dut on/off scripts added
    - hot plug trigger added
Commits on Oct 22, 2018
Commits on Oct 21, 2018
  1. fix up test escapes & improve output quality

    bunnie
    bunnie committed Oct 21, 2018
    * check for BIOS failures on SDRAM firmware load in check-REPL
    * catch 100T FPGA case, handle more gracefully
  2. update submodule refs

    bunnie
    bunnie committed Oct 21, 2018
  3. full test sequence for the "main" test is now complete

    bunnie
    bunnie committed Oct 21, 2018
    UI also works too
Commits on Oct 17, 2018
  1. clean up failure/exits

    bunnie
    bunnie committed Oct 17, 2018
  2. Tester now can perform the core test loop.

    bunnie
    bunnie committed Oct 17, 2018
    Still need to add the post-test firmware burn procedure and/or
    error handling exits but we're going to look at developing the
    the test output UI a bit before worrying about the exit clause
    and final firmware burn.
  3. add flterm as a submodule dependency

    bunnie
    bunnie committed Oct 17, 2018
Commits on Oct 14, 2018
  1. add the openocd scripts

    bunnie
    bunnie committed Oct 14, 2018
Commits on Oct 13, 2018
  1. add submodules for referencing the production images via git

    bunnie
    bunnie committed Oct 13, 2018
    netv2-fpga is added twice: once to be set at the tester-master
    branch (for tester images), and once to be set at the master branch.
    
    This is done because the tester requires submodule states that
    are incompatible with the production build.
  2. some initial jig setup files

    bunnie
    bunnie committed Oct 13, 2018
    Attempt to pull in the tester binaries (production tester image)
    from the git repo directly.
  3. ignore emacs droppings

    bunnie
    bunnie committed Oct 13, 2018
  4. first commit

    bunnie
    bunnie committed Oct 13, 2018