{"payload":{"header_redesign_enabled":false,"results":[{"id":"340277898","archived":false,"color":"#adb2cb","followers":1,"has_funding_file":false,"hl_name":"Anikin1610/RISCV-RV32I-Core","hl_trunc_description":"Behavioural model of a RV32I Core written in VHDL","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":340277898,"name":"RISCV-RV32I-Core","owner_id":28539727,"owner_login":"Anikin1610","updated_at":"2021-03-11T09:17:44.802Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":47,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AAnikin1610%252FRISCV-RV32I-Core%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/Anikin1610/RISCV-RV32I-Core/star":{"post":"NGxmSzBJiJp_5jU05RclJMvv8jToS6fYavoEwr4XERymWBkITB2qWzHVdkbt-qNRrf9Hj9npiuxLrWOO_jacZw"},"/Anikin1610/RISCV-RV32I-Core/unstar":{"post":"1YsSzMcSgUkwN5Bv0E80ZUGOWd-xohJhir82uzCQBCP9LztcHBPF6-2GTGYnJlzSR7gNo1HhxUkgIF0f-OJozA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"6Qr2iwKllSfknws5A8D_eepWXC28pD_vROC405oVw3VAlkb-EBmqtzYk4ADmMiT90Xp3LCuK-5fhXksR1LVfJg"}}},"title":"Repository search results"}