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SSC ACIA Status Register bit7 not set when IRQ enabled and using TCP Port 1977 #308

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burniouf opened this Issue Dec 13, 2015 · 48 comments

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burniouf commented Dec 13, 2015

Applewin 1.25.0.4
Serial Port set as "TCP"

When Enabling IRQ in ACIA CMD register (with value %00000101) an IRQ signal is generated (properly caught by IRQ handler) but bit 7 of ACIA status Register is not set to "1".

Seems OK when Serial Port set as "COM1"

@tomcw tomcw added the bug label Dec 27, 2015

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tomcw Dec 27, 2015

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I took a quick look.

Comparing to CommReceive(), it looks like CommTcpSerialReceive() needs to also set m_vbRxIrqPending. This flag is then checked (and cleared) in CommStatus().

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tomcw commented Dec 27, 2015

I took a quick look.

Comparing to CommReceive(), it looks like CommTcpSerialReceive() needs to also set m_vbRxIrqPending. This flag is then checked (and cleared) in CommStatus().

@tomcw tomcw self-assigned this Dec 27, 2015

@tomcw tomcw added this to the 1.26 milestone Dec 27, 2015

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burniouf Dec 27, 2015

personaly, i would add :
"m_vbRxIrqPending = true;"
after line 395 in AppleWin / source / SerialComms.cpp
am i right?

when release 1.26 (with this fix) will be released?

burniouf commented Dec 27, 2015

personaly, i would add :
"m_vbRxIrqPending = true;"
after line 395 in AppleWin / source / SerialComms.cpp
am i right?

when release 1.26 (with this fix) will be released?

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sicklittlemonkey Dec 28, 2015

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sicklittlemonkey commented Dec 28, 2015

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It would be less of a problem if we had been able to use proper object-oriented principles

Agreed! :)

when release 1.26 (with this fix) will be released?

I want to complete #260, and have a small window to do this now... so January.

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tomcw commented Dec 28, 2015

It would be less of a problem if we had been able to use proper object-oriented principles

Agreed! :)

when release 1.26 (with this fix) will be released?

I want to complete #260, and have a small window to do this now... so January.

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burniouf Jan 4, 2016

Something else in the same area that should be more an enhancement than a bug fix, but,
is it possible to set DSR and CTS lines low when TCP connection is established, and high when TCP connection is dropped?

burniouf commented Jan 4, 2016

Something else in the same area that should be more an enhancement than a bug fix, but,
is it possible to set DSR and CTS lines low when TCP connection is established, and high when TCP connection is dropped?

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sicklittlemonkey Jan 4, 2016

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I created a separate issue for that enhancement:
#311

Cheers,
Nick.

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sicklittlemonkey commented Jan 4, 2016

I created a separate issue for that enhancement:
#311

Cheers,
Nick.

@tomcw tomcw modified the milestones: 1.26, 1.27 Oct 16, 2016

@tomcw tomcw closed this in 7e38429 Dec 19, 2017

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The fix was trivially simple (for the ACIA Status.Interrupt not being set) ...but I've not tested it!

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tomcw commented Dec 19, 2017

The fix was trivially simple (for the ACIA Status.Interrupt not being set) ...but I've not tested it!

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burniouf Dec 19, 2017

Yeah!!!
2 years later, i must dig in the code of A2osX to find where i met this issue.
Which version should i use to check this bugfix ?

burniouf commented Dec 19, 2017

Yeah!!!
2 years later, i must dig in the code of A2osX to find where i met this issue.
Which version should i use to check this bugfix ?

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Great! I didn't know if you were still about to test this.
I'll do a build tomorrow and put the link here.

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tomcw commented Dec 19, 2017

Great! I didn't know if you were still about to test this.
I'll do a build tomorrow and put the link here.

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tomcw Dec 20, 2017

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Here's the new build of AppleWin 1.26.3.6 (tagged as pre-release).

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tomcw commented Dec 20, 2017

Here's the new build of AppleWin 1.26.3.6 (tagged as pre-release).

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burniouf Dec 20, 2017

Bit 7 of ACIA Status seems to be set properly, now.
I uncommented the fix for this bug line 252 in :

https://github.com/burniouf/A2osX/blob/master/DRV/SSC.DRV.S.txt

but the driver is not accepting incoming char any more....
must resume where i left 2 years ago...
Actually, usng a simplier IRQ manager:

*--------------------------------------

  • IRQ Handler

  • on exit, CC if handled
    *--------------------------------------
    IRQ ldx DEVSLOTn0
    lda SSC.STATUS,x

  •   		and #SSC.STATUS.IRQ		Useless
      		bpl .9					IRQ from this device ? no, exit !!!!Applewin bug #308!!!!
    
      		bit #SSC.STATUS.RDRF	incoming char?
      		beq .4					
    

*------------ IRQ In

			pha						save SSC.STATUS
			
			lda INBUF.HEAD
			tay						save actual head for later
			
			inc
			and #BUF.MASK
			cmp INBUF.TAIL				
			beq .3					buffer full, discard and exit
			
			sta INBUF.HEAD
			
			lda SSC.DATA,x			read data to clear IRQ
			sta INBUF,y

.3 pla get back SSC.STATUS

*------------ IRQ Out

.4 bit #SSC.STATUS.TDRE
beq .8 no transmition possible....

			ldy OUTBUF.TAIL			something to transmit ?
			cpy OUTBUF.HEAD
			beq .8					in that case, HOW TO CLEAR IRQ ????
			
			lda OUTBUF,y
			sta SSC.DATA,x			write data to clear IRQ
			
			tya
			inc
			and #BUF.MASK
			
			sta OUTBUF.TAIL	

.8 clc
rts

.9 sec
rts

.....not much success...digging into 6551 datasheet...
i ll keep you informed.

burniouf commented Dec 20, 2017

Bit 7 of ACIA Status seems to be set properly, now.
I uncommented the fix for this bug line 252 in :

https://github.com/burniouf/A2osX/blob/master/DRV/SSC.DRV.S.txt

but the driver is not accepting incoming char any more....
must resume where i left 2 years ago...
Actually, usng a simplier IRQ manager:

*--------------------------------------

  • IRQ Handler

  • on exit, CC if handled
    *--------------------------------------
    IRQ ldx DEVSLOTn0
    lda SSC.STATUS,x

  •   		and #SSC.STATUS.IRQ		Useless
      		bpl .9					IRQ from this device ? no, exit !!!!Applewin bug #308!!!!
    
      		bit #SSC.STATUS.RDRF	incoming char?
      		beq .4					
    

*------------ IRQ In

			pha						save SSC.STATUS
			
			lda INBUF.HEAD
			tay						save actual head for later
			
			inc
			and #BUF.MASK
			cmp INBUF.TAIL				
			beq .3					buffer full, discard and exit
			
			sta INBUF.HEAD
			
			lda SSC.DATA,x			read data to clear IRQ
			sta INBUF,y

.3 pla get back SSC.STATUS

*------------ IRQ Out

.4 bit #SSC.STATUS.TDRE
beq .8 no transmition possible....

			ldy OUTBUF.TAIL			something to transmit ?
			cpy OUTBUF.HEAD
			beq .8					in that case, HOW TO CLEAR IRQ ????
			
			lda OUTBUF,y
			sta SSC.DATA,x			write data to clear IRQ
			
			tya
			inc
			and #BUF.MASK
			
			sta OUTBUF.TAIL	

.8 clc
rts

.9 sec
rts

.....not much success...digging into 6551 datasheet...
i ll keep you informed.

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tomcw Dec 20, 2017

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Hi Rémy - out of interest, what are you using for development? AppleWin, other emulator or real h/w?

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tomcw commented Dec 20, 2017

Hi Rémy - out of interest, what are you using for development? AppleWin, other emulator or real h/w?

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burniouf Dec 21, 2017

i use mainly AppleWin....
and JACE because it supports DHGR mixed mode & ThunderClock emulation...
...and of course testing on readl H/W.
see:
burniouf/A2osX#29

I could be a very cool AppleWin implements DHGR Mixed Mode!

burniouf commented Dec 21, 2017

i use mainly AppleWin....
and JACE because it supports DHGR mixed mode & ThunderClock emulation...
...and of course testing on readl H/W.
see:
burniouf/A2osX#29

I could be a very cool AppleWin implements DHGR Mixed Mode!

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I could be a very cool AppleWin implements DHGR Mixed Mode!

AppleWin 1.26 versions should support all graphics modes (if not then this is a bug).

By DHGR mix mode do you mean this:

  • top 160 lines DHGR
  • bottom 32 lines either TEXT40 or TEXT80
    ?
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tomcw commented Dec 21, 2017

I could be a very cool AppleWin implements DHGR Mixed Mode!

AppleWin 1.26 versions should support all graphics modes (if not then this is a bug).

By DHGR mix mode do you mean this:

  • top 160 lines DHGR
  • bottom 32 lines either TEXT40 or TEXT80
    ?
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burniouf Dec 21, 2017

no,

if bit 7=1 -> color
if bit 7= 0 -> mono

See Chapter 6 in:

ftp://ftp.apple.asimov.net/pub/apple_II/documentation/hardware/video/Ext80ColumnAppleColorCard.pdf

And:

https://patentimages.storage.googleapis.com/pdfs/US4631692.pdf

already implemented in JACE.

the A2osX DHGR.DRV already implement this "MIXED" mode for BitBLT, RECT....etc....LINE functions..

burniouf commented Dec 21, 2017

no,

if bit 7=1 -> color
if bit 7= 0 -> mono

See Chapter 6 in:

ftp://ftp.apple.asimov.net/pub/apple_II/documentation/hardware/video/Ext80ColumnAppleColorCard.pdf

And:

https://patentimages.storage.googleapis.com/pdfs/US4631692.pdf

already implemented in JACE.

the A2osX DHGR.DRV already implement this "MIXED" mode for BitBLT, RECT....etc....LINE functions..

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burniouf Dec 21, 2017

Finally made A2osX SSC.I.drv working in AppleWin....

strange behaviour...when reading INPUT register after IRQ, seems internal queue not advancing to next char...added a loop in IRQ handler to bypass.

must run this new driver on REAL hardware.

burniouf commented Dec 21, 2017

Finally made A2osX SSC.I.drv working in AppleWin....

strange behaviour...when reading INPUT register after IRQ, seems internal queue not advancing to next char...added a loop in IRQ handler to bypass.

must run this new driver on REAL hardware.

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burniouf Dec 21, 2017

*--------------------------------------

  • IRQ Handler

  • on exit, CC if handled
    *--------------------------------------
    IRQ ldx DEVSLOTn0
    lda SSC.STATUS,x

  •   		and #SSC.STATUS.IRQ		Useless
      		bpl .9					IRQ from this device ? no, exit !!!!Applewin bug #308!!!!
    
      		bit #SSC.STATUS.RDRF	incoming char?
      		beq .3					
    

*------------ IRQ In

.1 lda INBUF.HEAD
tay save actual head for later

			inc
			and #BUF.MASK
			cmp INBUF.TAIL				
			beq .2					buffer full, discard and exit
			
			sta INBUF.HEAD

			lda SSC.DATA,x			read data to clear IRQ
			sta INBUF,y

.2 lda SSC.STATUS,x
bit #SSC.STATUS.RDRF incoming char?
bne .1

*------------ IRQ Out

.3 bit #SSC.STATUS.TDRE
beq .8 no transmition possible....

.4 ldy OUTBUF.TAIL something to transmit ?
cpy OUTBUF.HEAD
beq .8 in that case, HOW TO CLEAR IRQ ????

			lda OUTBUF,y
			sta SSC.DATA,x			write data to clear IRQ
			
			tya
			inc
			and #BUF.MASK
			
			sta OUTBUF.TAIL	
			
			lda SSC.STATUS,x
			bit #SSC.STATUS.TDRE
			bne .4

.8 clc
rts

.9 sec
rts
*--------------------------------------

burniouf commented Dec 21, 2017

*--------------------------------------

  • IRQ Handler

  • on exit, CC if handled
    *--------------------------------------
    IRQ ldx DEVSLOTn0
    lda SSC.STATUS,x

  •   		and #SSC.STATUS.IRQ		Useless
      		bpl .9					IRQ from this device ? no, exit !!!!Applewin bug #308!!!!
    
      		bit #SSC.STATUS.RDRF	incoming char?
      		beq .3					
    

*------------ IRQ In

.1 lda INBUF.HEAD
tay save actual head for later

			inc
			and #BUF.MASK
			cmp INBUF.TAIL				
			beq .2					buffer full, discard and exit
			
			sta INBUF.HEAD

			lda SSC.DATA,x			read data to clear IRQ
			sta INBUF,y

.2 lda SSC.STATUS,x
bit #SSC.STATUS.RDRF incoming char?
bne .1

*------------ IRQ Out

.3 bit #SSC.STATUS.TDRE
beq .8 no transmition possible....

.4 ldy OUTBUF.TAIL something to transmit ?
cpy OUTBUF.HEAD
beq .8 in that case, HOW TO CLEAR IRQ ????

			lda OUTBUF,y
			sta SSC.DATA,x			write data to clear IRQ
			
			tya
			inc
			and #BUF.MASK
			
			sta OUTBUF.TAIL	
			
			lda SSC.STATUS,x
			bit #SSC.STATUS.TDRE
			bne .4

.8 clc
rts

.9 sec
rts
*--------------------------------------

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strange behaviour...when reading INPUT register after IRQ, seems internal queue not advancing to next char...added a loop in IRQ handler to bypass.

By internal queue - do you mean your 6502 code? Or AppleWin's internal queue?
Which code is the loop you added?

btw:

  • reading SSC.STATUS will de-assert the IRQ (not SSC.DATA)
  • AppleWin doesn't yet support the SSC's "TX register empty" interrupt (just in case you try to test with AppleWin and wonder why it's not working!)
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tomcw commented Dec 21, 2017

strange behaviour...when reading INPUT register after IRQ, seems internal queue not advancing to next char...added a loop in IRQ handler to bypass.

By internal queue - do you mean your 6502 code? Or AppleWin's internal queue?
Which code is the loop you added?

btw:

  • reading SSC.STATUS will de-assert the IRQ (not SSC.DATA)
  • AppleWin doesn't yet support the SSC's "TX register empty" interrupt (just in case you try to test with AppleWin and wonder why it's not working!)
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burniouf Dec 21, 2017

  • By internal queue - do you mean your 6502 code? Or AppleWin's internal queue?
    sorry, i meant APPLEWIN queue (if exists)

  • Which code is the loop you added?
    https://github.com/burniouf/A2osX/blob/master/DRV/SSC.I.DRV.S.txt

  • AppleWin doesn't yet support the SSC's "TX register empty"
    AH....thanx for the information....never get it to run properly ;-)

burniouf commented Dec 21, 2017

  • By internal queue - do you mean your 6502 code? Or AppleWin's internal queue?
    sorry, i meant APPLEWIN queue (if exists)

  • Which code is the loop you added?
    https://github.com/burniouf/A2osX/blob/master/DRV/SSC.I.DRV.S.txt

  • AppleWin doesn't yet support the SSC's "TX register empty"
    AH....thanx for the information....never get it to run properly ;-)

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By internal queue - do you mean your 6502 code? Or AppleWin's internal queue?
sorry, i meant APPLEWIN queue (if exists)

Your code:

*------------ IRQ In

.1			lda INBUF.HEAD
			tay			save actual head for later
				
			inc
			and #BUF.MASK
			cmp INBUF.TAIL				
			beq .2			buffer full, discard and exit
				
			sta INBUF.HEAD

			lda SSC.DATA,x		read data to clear IRQ
			sta INBUF,y

.2			lda SSC.STATUS,x
			bit #SSC.STATUS.RDRF	incoming char?
			bne .1

My understanding is that your code will just keep reading SSC.DATA,x until SSC.STATUS.RDRF becomes 0.

AppleWin has an internal buffer of 128 bytes, and it will receive up to 128 for each TCP socket recv(). So (depending on what data you are sending to AppleWin) it's very likely that packets of >1 byte will be received, and so your code will loop until it's read all the data from that TCP recv() buffer.

I assume that you are not missing any data?
And also that you are not getting any duplicate or bad data?

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tomcw commented Dec 21, 2017

By internal queue - do you mean your 6502 code? Or AppleWin's internal queue?
sorry, i meant APPLEWIN queue (if exists)

Your code:

*------------ IRQ In

.1			lda INBUF.HEAD
			tay			save actual head for later
				
			inc
			and #BUF.MASK
			cmp INBUF.TAIL				
			beq .2			buffer full, discard and exit
				
			sta INBUF.HEAD

			lda SSC.DATA,x		read data to clear IRQ
			sta INBUF,y

.2			lda SSC.STATUS,x
			bit #SSC.STATUS.RDRF	incoming char?
			bne .1

My understanding is that your code will just keep reading SSC.DATA,x until SSC.STATUS.RDRF becomes 0.

AppleWin has an internal buffer of 128 bytes, and it will receive up to 128 for each TCP socket recv(). So (depending on what data you are sending to AppleWin) it's very likely that packets of >1 byte will be received, and so your code will loop until it's read all the data from that TCP recv() buffer.

I assume that you are not missing any data?
And also that you are not getting any duplicate or bad data?

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burniouf Dec 21, 2017

yes, this way it works very well in AppleWin, no miss, no duplicate.....but i don't know the behaviour on real hardware after this change....
for now i'm focused on DHGR & GUI development, and i'm lacking beta testers.. :-(

any chance TX register empty IRQ implemented ?

burniouf commented Dec 21, 2017

yes, this way it works very well in AppleWin, no miss, no duplicate.....but i don't know the behaviour on real hardware after this change....
for now i'm focused on DHGR & GUI development, and i'm lacking beta testers.. :-(

any chance TX register empty IRQ implemented ?

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@burniouf - btw your code is doing this (in 2 places):

 sta SSC.DATA,x 

...which is doing a false read of SSC.DATA+X too!

On a real Apple II you could lose input data (receive data) because of this false read.
NB. AppleWin doesn't do this false read - a good example of why you should always test on real hardware.

See how the SSC's firmware avoids this false read by doing this (at $CC0D):

 sta $BFFF,Y
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tomcw commented Dec 30, 2017

@burniouf - btw your code is doing this (in 2 places):

 sta SSC.DATA,x 

...which is doing a false read of SSC.DATA+X too!

On a real Apple II you could lose input data (receive data) because of this false read.
NB. AppleWin doesn't do this false read - a good example of why you should always test on real hardware.

See how the SSC's firmware avoids this false read by doing this (at $CC0D):

 sta $BFFF,Y
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burniouf Jan 1, 2018

Except that a2osx is targeting 65c02 or higher , which is NOT doing false read
I experienced this while writing uthernet II driver

burniouf commented Jan 1, 2018

Except that a2osx is targeting 65c02 or higher , which is NOT doing false read
I experienced this while writing uthernet II driver

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From Sather's "Understanding the Apple IIe", table 4.3 "65C02 Instructions", row 22 shows that just like for the 6502, the STA ABS,X (no PX) still does a false read at address ABS+X. Also on the preceding page (4-26), he explains that the disk II's logic sequence is designed around the "STA $C080,X" instruction doing this double access.

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tomcw commented Jan 1, 2018

From Sather's "Understanding the Apple IIe", table 4.3 "65C02 Instructions", row 22 shows that just like for the 6502, the STA ABS,X (no PX) still does a false read at address ABS+X. Also on the preceding page (4-26), he explains that the disk II's logic sequence is designed around the "STA $C080,X" instruction doing this double access.

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@burniouf above you reported:

strange behaviour...when reading INPUT register after IRQ, seems internal queue not advancing to next char

This just got fixed in a78f1e0:

  • Fixed TCP mode which was only generating an IRQ for first byte received

I'll update this issue when there's a new build.

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tomcw commented Apr 8, 2018

@burniouf above you reported:

strange behaviour...when reading INPUT register after IRQ, seems internal queue not advancing to next char

This just got fixed in a78f1e0:

  • Fixed TCP mode which was only generating an IRQ for first byte received

I'll update this issue when there's a new build.

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burniouf Apr 9, 2018

Great!

Let me know when build s ready, in the meantime, i 'll rewrite from scratch these SSC drivers to remove this "false read" code...

Thanx

burniouf commented Apr 9, 2018

Great!

Let me know when build s ready, in the meantime, i 'll rewrite from scratch these SSC drivers to remove this "false read" code...

Thanx

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New AppleWin 1.27.2.0 build here.
Let me know how you get on.

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tomcw commented Apr 12, 2018

New AppleWin 1.27.2.0 build here.
Let me know how you get on.

@tomcw tomcw modified the milestones: 1.27, 1.27.2 Apr 12, 2018

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btw, see this project for my SSC tests for {Polling|Interrupt x Rx|Tx}:
https://github.com/AppleWin/AppleWin-Test/tree/master/Projects/GH522-SSC-TX-RX

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tomcw commented Apr 13, 2018

btw, see this project for my SSC tests for {Polling|Interrupt x Rx|Tx}:
https://github.com/AppleWin/AppleWin-Test/tree/master/Projects/GH522-SSC-TX-RX

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burniouf Apr 14, 2018

At my side, seems to work better, now.
Implemented in this driver:

https://github.com/burniouf/A2osX/blob/master/DRV/X.SSC.DRV.S.txt

(note : rewrote the whole stuff to avoid "false read")

I will test this on real hardware, an then add DSR/CTS monitoring.

Do i need special switch in Applewin cmd line to enable the TCP/IP DSR/CTS functionality ?

burniouf commented Apr 14, 2018

At my side, seems to work better, now.
Implemented in this driver:

https://github.com/burniouf/A2osX/blob/master/DRV/X.SSC.DRV.S.txt

(note : rewrote the whole stuff to avoid "false read")

I will test this on real hardware, an then add DSR/CTS monitoring.

Do i need special switch in Applewin cmd line to enable the TCP/IP DSR/CTS functionality ?

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Do i need special switch in Applewin cmd line to enable the TCP/IP DSR/CTS functionality ?

For CTS (and RTS), these just work.
For DSR (and DCD, DTR), you'll need to specify the -modem switch (or -dtr/-dcd/-dsr for the specific signal you want AppleWin to support).

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tomcw commented Apr 14, 2018

Do i need special switch in Applewin cmd line to enable the TCP/IP DSR/CTS functionality ?

For CTS (and RTS), these just work.
For DSR (and DCD, DTR), you'll need to specify the -modem switch (or -dtr/-dcd/-dsr for the specific signal you want AppleWin to support).

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burniouf Apr 14, 2018

i added the -modem switch to the cmd line, and tried monitoring the DTR line with not much success. :-(
i use putty to connect to A2osX 127.0.0.1:1977. i connect succesfully to A2osX/SSC.I.DRV (RX/TX IRQ working properly now, no lost chars...etc...) but when i close PUTTY to drop the TCP connection....the DTR bit in STATUS register does not go high...

burniouf commented Apr 14, 2018

i added the -modem switch to the cmd line, and tried monitoring the DTR line with not much success. :-(
i use putty to connect to A2osX 127.0.0.1:1977. i connect succesfully to A2osX/SSC.I.DRV (RX/TX IRQ working properly now, no lost chars...etc...) but when i close PUTTY to drop the TCP connection....the DTR bit in STATUS register does not go high...

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tomcw Apr 14, 2018

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but when i close PUTTY to drop the TCP connection....the DTR bit in STATUS register does not go high...

Actually the Status reg contains DSR and DCD (it's the Control reg that has DTR). But I assume this is a typo and you mean DSR (not DTR).

Anyway, I see what's wrong...
The Status register's DSR and DCD bits are only supported when using a real COM port. For TCP they always remain zero.

And it's the same for CTS (read from the DIPSW2 reg), ie. it's only supported for a real COM port, not TCP (always zero).

I'll re-open this issue, and see what DSR+DCD emulation I can provide when using TCP mode.

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tomcw commented Apr 14, 2018

but when i close PUTTY to drop the TCP connection....the DTR bit in STATUS register does not go high...

Actually the Status reg contains DSR and DCD (it's the Control reg that has DTR). But I assume this is a typo and you mean DSR (not DTR).

Anyway, I see what's wrong...
The Status register's DSR and DCD bits are only supported when using a real COM port. For TCP they always remain zero.

And it's the same for CTS (read from the DIPSW2 reg), ie. it's only supported for a real COM port, not TCP (always zero).

I'll re-open this issue, and see what DSR+DCD emulation I can provide when using TCP mode.

@tomcw tomcw reopened this Apr 14, 2018

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burniouf Apr 14, 2018

oops, yes ! i meant DSR.

btw, the current Applewin status allow me to go ahead with many pending features in A2osX....
Thanx for your support.

burniouf commented Apr 14, 2018

oops, yes ! i meant DSR.

btw, the current Applewin status allow me to go ahead with many pending features in A2osX....
Thanx for your support.

tomcw added a commit that referenced this issue Apr 14, 2018

SSC work:
. SSC: For TCP mode, support DSR, DCD & CTS status bits (#308).
. SSC: Now DTR must also be set to enable interrupts (in addition to the respective Tx/Rx interrupt bit).
. SSC: When reading the Status register, throttle calls to GetCommModemStatus() to a maximum of once every 8ms.
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tomcw Apr 14, 2018

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This build should support DSR, DCD (and CTS) for the TCP mode.
(I'm testing with PUTTY too)
AppleWin1.27.3.0.zip

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tomcw commented Apr 14, 2018

This build should support DSR, DCD (and CTS) for the TCP mode.
(I'm testing with PUTTY too)
AppleWin1.27.3.0.zip

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burniouf Apr 14, 2018

IT WORKS!!!

burniouf commented Apr 14, 2018

IT WORKS!!!

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burniouf commented Apr 14, 2018

image

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burniouf commented Apr 14, 2018

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burniouf Apr 14, 2018

now LOGIN & SHELL are properly killed when i cut the link!

burniouf commented Apr 14, 2018

now LOGIN & SHELL are properly killed when i cut the link!

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burniouf commented Apr 14, 2018

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burniouf Apr 14, 2018

...and next connection is prompted at LOGIN again.

many thanx.
Remy

burniouf commented Apr 14, 2018

...and next connection is prompted at LOGIN again.

many thanx.
Remy

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tomcw Apr 15, 2018

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Great! Thanks for confirming.

Some things I want to do to polish this are:

  • Remove the need for the -modem switch (I need to do some testing with the Apple II comms app called ZLINK) - #553
  • Extend the AppleWin regression tests to include this disconnect/reconnect (ie. test ACIA Status bits DSR and DCD) - AppleWin/AppleWin-Test@2ced199
  • Improve help docs about SSC support - #554
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tomcw commented Apr 15, 2018

Great! Thanks for confirming.

Some things I want to do to polish this are:

  • Remove the need for the -modem switch (I need to do some testing with the Apple II comms app called ZLINK) - #553
  • Extend the AppleWin regression tests to include this disconnect/reconnect (ie. test ACIA Status bits DSR and DCD) - AppleWin/AppleWin-Test@2ced199
  • Improve help docs about SSC support - #554
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tomcw May 26, 2018

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NB. Official release AppleWin1.27.4 (superseding 1.27.3).

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tomcw commented May 26, 2018

NB. Official release AppleWin1.27.4 (superseding 1.27.3).

@tomcw tomcw closed this May 26, 2018

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burniouf May 26, 2018

Just to be sure...i need to test again WITHOUT -modem switch, right ?

burniouf commented May 26, 2018

Just to be sure...i need to test again WITHOUT -modem switch, right ?

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tomcw May 27, 2018

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Yes, correct: without the -modem switch.

Details the -modem switch (alias: -dcd) can be used in COM mode to use the actual value of DCD - the default (ie. without this switch) is for DCD to mirror the state of DSR.

NB. In TCP mode, this switch has no affect. Whilst there's a TCP connection then DCD and DSR will both be low (ie. active). The same for CTS.

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tomcw commented May 27, 2018

Yes, correct: without the -modem switch.

Details the -modem switch (alias: -dcd) can be used in COM mode to use the actual value of DCD - the default (ie. without this switch) is for DCD to mirror the state of DSR.

NB. In TCP mode, this switch has no affect. Whilst there's a TCP connection then DCD and DSR will both be low (ie. active). The same for CTS.

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burniouf May 28, 2018

AppleWin 1.27.4 Without "-modem"
I confirm the bahaviour is as expected.
same test as above succedeed.
Good Job!

burniouf commented May 28, 2018

AppleWin 1.27.4 Without "-modem"
I confirm the bahaviour is as expected.
same test as above succedeed.
Good Job!

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tomcw May 29, 2018

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Thanks for re-checking this - it's good to know nothing has broken (but I do have regression tests now for this behaviour).

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tomcw commented May 29, 2018

Thanks for re-checking this - it's good to know nothing has broken (but I do have regression tests now for this behaviour).

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