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6502 interrupt should delay 1 opcode when interrupt occurs on last cycle of opcode #724
Spun off from #718.
Due to 6502 pipelining, on the last cycle of any opcode (other than completing the opcode), additionally either:
So if IRQ is asserted on the last cycle, then the next opcode decode is is already happening, so the interrupt will be taken after the next opcode completes.