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# Main Clocks & SPI FLASH Clk #
NET "clk100" LOC = P55 | IOSTANDARD = LVCMOS33; //N_GCLK
NET "clk" TNM_NET = "clk";
NET "clk100" TNM_NET = "clk100";
NET "pclk" TNM_NET = "pclk";
TIMESPEC TS_clk100 = PERIOD "clk100" 5 ns HIGH 50 %;
TIMESPEC "TS_test" = FROM "clk" TO "pclk" TIG;
TIMESPEC "TS_test2" = FROM "pclk" TO "clk" TIG;
//NET "SCK" LOC = P94 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //P_GCLK
# Synchronous Ram Signals #
//NET "SRA[0]" LOC = P26 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[1]" LOC = P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[2]" LOC = P29 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[3]" LOC = P30 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[4]" LOC = P32 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[5]" LOC = P33 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[6]" LOC = P34 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //VREF
//NET "SRA[7]" LOC = P35 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[8]" LOC = P16 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //N_GCLK
//NET "SRA[9]" LOC = P15 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //P_GCLK
//NET "SRA[10]" LOC = P14 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //N_GCLK
//NET "SRA[11]" LOC = P12 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[12]" LOC = P11 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[13]" LOC = P10 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[14]" LOC = P9 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[15]" LOC = P8 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[16]" LOC = P7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[17]" LOC = P6 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[18]" LOC = P5 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[19]" LOC = P2 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRA[20]" LOC = P1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //VREF
//NET "SRD[0]" LOC = P121 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[1]" LOC = P126 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //N_GCLK
//NET "SRD[2]" LOC = P131 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //N_GCLK
//NET "SRD[3]" LOC = P132 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //P_GCLK
//NET "SRD[4]" LOC = P134 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //P_GCLK
//NET "SRD[5]" LOC = P137 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[6]" LOC = P138 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[7]" LOC = P139 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[8]" LOC = P118 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[9]" LOC = P119 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[10]" LOC = P120 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //VREF
//NET "SRD[11]" LOC = P133 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //N_GCLK
//NET "SRD[12]" LOC = P140 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[13]" LOC = P141 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[14]" LOC = P142 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "SRD[15]" LOC = P143 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //VREF
//NET "WEn" LOC = P21 | IOSTANDARD = LVCMOS33; //N_GCLK
//NET "SRCLK" LOC = P22 | IOSTANDARD = LVCMOS33; //P_GCLK
//NET "SRCS" LOC = P23 | IOSTANDARD = LVCMOS33; //N_GCLK
# RGBin Signals #
//NET "Rin[0]" LOC = P64 | IOSTANDARD = LVCMOS33; //CSI
//NET "Rin[1]" LOC = P62 | IOSTANDARD = LVCMOS33; //Dx
//NET "Rin[2]" LOC = P61 | IOSTANDARD = LVCMOS33; //Dx
//NET "Rin[3]" LOC = P59 | IOSTANDARD = LVCMOS33; //Dx
//NET "Rin[4]" LOC = P58 | IOSTANDARD = LVCMOS33; //Dx
//NET "Gin[0]" LOC = P57 | IOSTANDARD = LVCMOS33; //Dx
//NET "Gin[1]" LOC = P56 | IOSTANDARD = LVCMOS33; //N_GCLK
//NET "Gin[2]" LOC = P48 | IOSTANDARD = LVCMOS33; //Dx
//NET "Gin[3]" LOC = P47 | IOSTANDARD = LVCMOS33; //RDWR_B_VREF
//NET "Gin[4]" LOC = P46 | IOSTANDARD = LVCMOS33; //Dx
//NET "Gin[5]" LOC = P45 | IOSTANDARD = LVCMOS33; //Dx
//NET "Bin[0]" LOC = P44 | IOSTANDARD = LVCMOS33; //Dx
//NET "Bin[1]" LOC = P43 | IOSTANDARD = LVCMOS33; //Dx
//NET "Bin[2]" LOC = P41 | IOSTANDARD = LVCMOS33; //Dx
//NET "Bin[3]" LOC = P40 | IOSTANDARD = LVCMOS33; //Dx
//NET "Bin[4]" LOC = P38 | IOSTANDARD = LVCMOS33; //CSO
//NET "HSYNCin" LOC = P123 | IOSTANDARD = LVCMOS33; //P_GCLK
//NET "VSYNCin" LOC = P51 | IOSTANDARD = LVCMOS33; //N_GCLK
//NET "PCLKin" LOC = P88 | IOSTANDARD = LVCMOS33; //N_GCLK
# RGblue Signals #
NET "red[0]" LOC = P105 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "red[1]" LOC = P104 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //VREF
NET "red[2]" LOC = P102 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "red[3]" LOC = P101 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "red[4]" LOC = P100 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "green[0]" LOC = P99 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "green[1]" LOC = P98 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "green[2]" LOC = P97 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "green[3]" LOC = P83 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "green[4]" LOC = P82 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "green[5]" LOC = P81 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "blue[0]" LOC = P80 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "blue[1]" LOC = P79 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "blue[2]" LOC = P78 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
NET "blue[3]" LOC = P75 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //AWAKE
NET "blue[4]" LOC = P74 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //DOUT_BUSY
//NET "DACBLANKn" LOC = P85 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //P_GCLK Alt. v1.0h -> NET "SRA[21]" LOC = P85 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //P_GCLK
NET "hsync" LOC = P124 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //N_GCLK
NET "vsync" LOC = P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //P_GCLK
NET "pclk_out" LOC = P87 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //P_GCLK
# SD Card and I/O #
//NET "BOARDRDYn" LOC = P115 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O -- Alt. v1.0h S5
//NET "BOARDCLK" LOC = P127 | IOSTANDARD = LVCMOS33; //N_GCLK
//NET "BOARDEN" LOC = P17 | IOSTANDARD = LVCMOS33; //P_GCLK
//NET "BOARDRWn" LOC = P24 | IOSTANDARD = LVCMOS33; //P_GCLK
//NET "IOD[0]" LOC = P66 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //Dx
//NET "IOD[1]" LOC = P67 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //Dx
//NET "IOD[2]" LOC = P116 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "IOD[3]" LOC = P117 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O
//NET "IOD[4]" LOC = P114 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O -- Alt. MicroSD CSn or v1.0h S3
//NET "IOD[5]" LOC = P111 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O -- Alt. MicroSD MISO or v1.0h S4
//NET "IOD[6]" LOC = P112 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //USER I/O -- Alt. MicroSD MOSI or v1.0h S2
//NET "IOD[7]" LOC = P92 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //N_GCLK
# SPI Flash Data #
//NET "SO" LOC = P95 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //N_GCLK
//NET "SI" LOC = P93 | IOSTANDARD = LVCMOS33; //P_GCLK
//NET "FEN12n" LOC = P72 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12; //CMPCS_B_2
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