Skip to content

ADRV9009 Platform User Guide

nnaufel edited this page Jun 9, 2020 · 16 revisions
Clone this wiki locally

Introduction

The ADRV9009 Platform is a complete development platform for applications that require high-performance radios over a wideband frequency range. It connects an Intel Arria® 10 SoC FPGA to an ADRV9009 evaluation board by using the space-saving high-speed JESD204B serial interface.

The Arrow High-Speed Radio Card Development Board is a complete development platform for applications that require high-performance radios over a wideband frequency range, with the space-saving high-speed GSPS JESD204B serial interface. Featuring Analog Devices’ ADRV9009, a highly integrated wideband RF transceiver with integrated synthesizers and DSP functions, and the Intel Arria 10 SoC FPGA on the Critical Link MitySOM®-A10S, the kit allows them to communicate across 12.288Gbps per lane with 2 serial lanes per transmitter and 1 serial lane per receiver. Also provided are all the timing and power components required to both develop solutions and demonstrate the capabilities of JESD204B.

With lane rates up to 12.288Gbps this is the ideal platform for developing a wide range of applications including:

  • 3G/4G/5G TDD Macro Cell Base Stations
  • TDD Active Antenna Systems
  • Massive MIMO
  • Phased Array Radar
  • Electronic Warfare
  • Military Communications
  • Portable Test Equipment

Table of Contents

  1. Quick Start Guide
  2. Platform Architecture
  3. Build the Example Design
  4. ADRV9009 MATLAB Profile Generator

Return to Arrow Highspeed Converter Platforms Home