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Advanced VLSI Systems Design Coursework Project
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8 Bit Carry Select Adder - Final Project
CMOS Inverter - 45nm
CMOS Master Slave D Flip Flop - 45nm
CMOS Parity Gen - 45nm
Homework Problems
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README.md

README.md

VLSI-8-Bit-Carry-Select-Adder

This repository contains my Coursework (ESE-555-Advanced VLSI Systems Design) Project Designs. Each folder contains the problem statement and the reports for the projects. The designs were built in Cadance Virtuoso (Schematic & Layout) and simulated using HPICE (Post-Layout).

Refer Project Handouts for detailed descriptions.

Copyright (c) 2017 Aswinnatesh | All Rights Reserved

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