diff --git a/src/Verilog.Vivado/BRAM1.v b/src/Verilog.Vivado/BRAM1.v
deleted file mode 100644
index 439192774..000000000
--- a/src/Verilog.Vivado/BRAM1.v
+++ /dev/null
@@ -1,64 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
- `define BSV_ASSIGNMENT_DELAY
-`endif
-
-// Single-Ported BRAM
-module BRAM1(CLK,
-             EN,
-             WE,
-             ADDR,
-             DI,
-             DO
-             );
-
-   parameter                      PIPELINED  = 0;
-   parameter                      ADDR_WIDTH = 1;
-   parameter                      DATA_WIDTH = 1;
-   parameter                      MEMSIZE    = 1;
-
-   input                          CLK;
-   input                          EN;
-   input                          WE;
-   input [ADDR_WIDTH-1:0]         ADDR;
-   input [DATA_WIDTH-1:0]         DI;
-   output [DATA_WIDTH-1:0]        DO;
-
-   (* RAM_STYLE = "BLOCK" *)
-   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];
-   reg [DATA_WIDTH-1:0]           DO_R;
-   reg [DATA_WIDTH-1:0]           DO_R2;
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else
-   // synopsys translate_off
-   integer                        i;
-   initial
-   begin : init_block
-      for (i = 0; i < MEMSIZE; i = i + 1) begin
-         RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      end
-      DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-   end
-   // synopsys translate_on
-`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
-
-   always @(posedge CLK) begin
-      if (EN) begin
-         if (WE) begin
-            RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
-            DO_R <= `BSV_ASSIGNMENT_DELAY DI;
-         end
-         else begin
-            DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
-         end
-      end
-      DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
-   end
-
-   // Output driver
-   assign DO = (PIPELINED) ? DO_R2 : DO_R;
-
-endmodule // BRAM1
diff --git a/src/Verilog.Vivado/BRAM1BE.v b/src/Verilog.Vivado/BRAM1BE.v
deleted file mode 100644
index 8f1932ede..000000000
--- a/src/Verilog.Vivado/BRAM1BE.v
+++ /dev/null
@@ -1,111 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
- `define BSV_ASSIGNMENT_DELAY
-`endif
-
-// Single-Ported BRAM with byte enables
-module BRAM1BE(CLK,
-               EN,
-               WE,
-               ADDR,
-               DI,
-               DO
-              );
-
-   parameter                      PIPELINED  = 0;
-   parameter                      ADDR_WIDTH = 1;
-   parameter                      DATA_WIDTH = 1;
-   parameter                      CHUNKSIZE  = 1;
-   parameter                      WE_WIDTH   = 1;
-   parameter                      MEMSIZE    = 1;
-
-   input                          CLK;
-   input                          EN;
-   input [WE_WIDTH-1:0]           WE;
-   input [ADDR_WIDTH-1:0]         ADDR;
-   input [DATA_WIDTH-1:0]         DI;
-   output [DATA_WIDTH-1:0]        DO;
-
-   (* RAM_STYLE = "BLOCK" *)
-   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];
-   reg [DATA_WIDTH-1:0]           DO_R;
-   reg [DATA_WIDTH-1:0]           DO_R2;
-
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else
-   // synopsys translate_off
-   initial
-   begin : init_block
-      integer   i;
-      for (i = 0; i < MEMSIZE; i = i + 1) begin
-         RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      end
-      DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-   end
-   // synopsys translate_on
-`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASK, IMASK;
-   reg [DATA_WIDTH-1:0]  DATA;
-   wire [DATA_WIDTH-1:0] DATAwr;
-
-   assign DATAwr = RAM[ADDR] ;
-
-   always @(WE or DI or DATAwr) begin : combo1
-      integer j;
-      MASK  = 0;
-      IMASK = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else       MASK = (MASK << 8);
-      end
-      IMASK = ~MASK;
-
-      DATA = (DATAwr & IMASK) | (DI & MASK);
-   end
-
-   always @(posedge CLK) begin
-      if (EN) begin
-         if (WE) begin
-            RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
-            DO_R      <= `BSV_ASSIGNMENT_DELAY DATA;
-         end
-         else begin
-            DO_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
-         end
-      end
-   end
-`else
-   generate
-      genvar i;
-      for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we
-         always @(posedge CLK) begin
-            if (EN) begin
-               if (WE[i]) begin
-                  RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-                  DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-               end
-               else begin
-                  DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-               end
-            end
-         end
-      end      
-   endgenerate
-
-`endif // !`ifdef __ICARUS__
-
-   // Output driver
-   always @(posedge CLK) begin
-      DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
-   end
-   
-   assign DO = (PIPELINED) ? DO_R2 : DO_R;
-
-endmodule // BRAM1BE
diff --git a/src/Verilog.Vivado/BRAM1BELoad.v b/src/Verilog.Vivado/BRAM1BELoad.v
deleted file mode 100644
index 3661bc0e3..000000000
--- a/src/Verilog.Vivado/BRAM1BELoad.v
+++ /dev/null
@@ -1,117 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
- `define BSV_ASSIGNMENT_DELAY
-`endif
-
-// Single-Ported BRAM with byte enables and ability to load from file
-module BRAM1BELoad(CLK,
-                   EN,
-                   WE,
-                   ADDR,
-                   DI,
-                   DO
-                  );
-
-   parameter                      FILENAME   = "";
-   parameter                      PIPELINED  = 0;
-   parameter                      ADDR_WIDTH = 1;
-   parameter                      DATA_WIDTH = 1;
-   parameter                      CHUNKSIZE  = 1;
-   parameter                      WE_WIDTH   = 1;
-   parameter                      MEMSIZE    = 1;
-   parameter                      BINARY     = 0;
-
-   input                          CLK;
-   input                          EN;
-   input [WE_WIDTH-1:0]           WE;
-   input [ADDR_WIDTH-1:0]         ADDR;
-   input [DATA_WIDTH-1:0]         DI;
-   output [DATA_WIDTH-1:0]        DO;
-
-   (* RAM_STYLE = "BLOCK" *)
-   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];
-   reg [DATA_WIDTH-1:0]           DO_R;
-   reg [DATA_WIDTH-1:0]           DO_R2;
-
-   // synopsys translate_off
-   initial
-   begin : init_block
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else
-      DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
-   end
-   // synopsys translate_on
-
-   initial
-   begin : init_rom_block
-      if (BINARY)
-        $readmemb(FILENAME, RAM, 0, MEMSIZE-1);
-      else
-        $readmemh(FILENAME, RAM, 0, MEMSIZE-1);
-   end
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASK, IMASK;
-   reg [DATA_WIDTH-1:0]  DATA;
-   wire [DATA_WIDTH-1:0] DATAwr;
-
-   assign DATAwr = RAM[ADDR] ;
-
-
-   always @(WE or DI or DATAwr) begin : combo1
-      integer j;
-      MASK  = 0;
-      IMASK = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else       MASK = (MASK << 8);
-      end
-      IMASK = ~MASK;
-
-      DATA = (DATAwr & IMASK) | (DI & MASK);
-   end
-
-   
-   always @(posedge CLK) begin
-      if (EN) begin
-         if (WE) begin
-            RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
-            DO_R      <= `BSV_ASSIGNMENT_DELAY DATA;
-         end
-         else begin
-            DO_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
-         end
-      end
-   end
-`else
-   generate
-      genvar i;
-      for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we
-         always @(posedge CLK) begin
-            if (EN) begin
-               if (WE[i]) begin
-                  RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-                  DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-               end
-               else begin
-                  DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-               end
-            end
-         end
-      end      
-   endgenerate
-`endif // !`ifdef __ICARUS__
-
-   // Output driver
-   always @(posedge CLK) begin
-      DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
-   end
-   
-   assign DO = (PIPELINED) ? DO_R2 : DO_R;
-
-endmodule // BRAM1BELoad
diff --git a/src/Verilog.Vivado/BRAM1Load.v b/src/Verilog.Vivado/BRAM1Load.v
deleted file mode 100644
index d099daaa5..000000000
--- a/src/Verilog.Vivado/BRAM1Load.v
+++ /dev/null
@@ -1,70 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
- `define BSV_ASSIGNMENT_DELAY
-`endif
-
-// Single-Ported BRAM
-module BRAM1Load(CLK,
-                 EN,
-                 WE,
-                 ADDR,
-                 DI,
-                 DO
-                 );
-
-   parameter                      FILENAME   = "";
-   parameter                      PIPELINED  = 0;
-   parameter                      ADDR_WIDTH = 1;
-   parameter                      DATA_WIDTH = 1;
-   parameter                      MEMSIZE    = 1;
-   parameter                      BINARY     = 0;
-
-   input                          CLK;
-   input                          EN;
-   input                          WE;
-   input [ADDR_WIDTH-1:0]         ADDR;
-   input [DATA_WIDTH-1:0]         DI;
-   output [DATA_WIDTH-1:0]        DO;
-
-   (* RAM_STYLE = "BLOCK" *)
-   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];
-   reg [DATA_WIDTH-1:0]           DO_R;
-   reg [DATA_WIDTH-1:0]           DO_R2;
-
-   // synopsys translate_off
-   initial
-   begin : init_block
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else
-      DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
-   end
-   // synopsys translate_on
-
-   initial
-   begin : init_rom_block
-      if (BINARY)
-        $readmemb(FILENAME, RAM, 0, MEMSIZE-1);
-      else
-        $readmemh(FILENAME, RAM, 0, MEMSIZE-1);
-   end
-
-   always @(posedge CLK) begin
-      if (EN) begin
-         if (WE) begin
-            RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
-            DO_R <= `BSV_ASSIGNMENT_DELAY DI;
-         end
-         else begin
-            DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
-         end
-      end
-      DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
-   end
-
-   // Output driver
-   assign DO = (PIPELINED) ? DO_R2 : DO_R;
-
-endmodule // BRAM1Load
diff --git a/src/Verilog.Vivado/BRAM2.v b/src/Verilog.Vivado/BRAM2.v
deleted file mode 100644
index 98d73891c..000000000
--- a/src/Verilog.Vivado/BRAM2.v
+++ /dev/null
@@ -1,95 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
- `define BSV_ASSIGNMENT_DELAY
-`endif
-
-// Dual-Ported BRAM (WRITE FIRST)
-module BRAM2(CLKA,
-             ENA,
-             WEA,
-             ADDRA,
-             DIA,
-             DOA,
-             CLKB,
-             ENB,
-             WEB,
-             ADDRB,
-             DIB,
-             DOB
-             );
-
-   parameter                      PIPELINED  = 0;
-   parameter                      ADDR_WIDTH = 1;
-   parameter                      DATA_WIDTH = 1;
-   parameter                      MEMSIZE    = 1;
-
-   input                          CLKA;
-   input                          ENA;
-   input                          WEA;
-   input [ADDR_WIDTH-1:0]         ADDRA;
-   input [DATA_WIDTH-1:0]         DIA;
-   output [DATA_WIDTH-1:0]        DOA;
-
-   input                          CLKB;
-   input                          ENB;
-   input                          WEB;
-   input [ADDR_WIDTH-1:0]         ADDRB;
-   input [DATA_WIDTH-1:0]         DIB;
-   output [DATA_WIDTH-1:0]        DOB;
-
-   (* RAM_STYLE = "BLOCK" *)
-   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
-   reg [DATA_WIDTH-1:0]           DOA_R;
-   reg [DATA_WIDTH-1:0]           DOB_R;
-   reg [DATA_WIDTH-1:0]           DOA_R2;
-   reg [DATA_WIDTH-1:0]           DOB_R2;
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else
-   // synopsys translate_off
-   integer                        i;
-   initial
-   begin : init_block
-      for (i = 0; i < MEMSIZE; i = i + 1) begin
-         RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      end
-      DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-   end
-   // synopsys translate_on
-`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
-
-   always @(posedge CLKA) begin
-      if (ENA) begin
-         if (WEA) begin
-            RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
-            DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
-         end
-         else begin
-            DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
-         end
-      end
-      DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
-   end
-
-   always @(posedge CLKB) begin
-      if (ENB) begin
-         if (WEB) begin
-            RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
-            DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
-         end
-         else begin
-            DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
-         end
-      end
-      DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
-   end
-
-   // Output drivers
-   assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
-   assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
-
-endmodule // BRAM2
diff --git a/src/Verilog.Vivado/BRAM2BE.v b/src/Verilog.Vivado/BRAM2BE.v
deleted file mode 100644
index 64c1daffe..000000000
--- a/src/Verilog.Vivado/BRAM2BE.v
+++ /dev/null
@@ -1,189 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
- `define BSV_ASSIGNMENT_DELAY
-`endif
-
-// Dual-Ported BRAM (WRITE FIRST) with byte enables
-module BRAM2BE(CLKA,
-               ENA,
-               WEA,
-               ADDRA,
-               DIA,
-               DOA,
-               CLKB,
-               ENB,
-               WEB,
-               ADDRB,
-               DIB,
-               DOB
-              );
-
-   parameter                      PIPELINED  = 0;
-   parameter                      ADDR_WIDTH = 1;
-   parameter                      DATA_WIDTH = 1;
-   parameter                      CHUNKSIZE  = 1;
-   parameter                      WE_WIDTH   = 1;
-   parameter                      MEMSIZE    = 1;
-
-   input                          CLKA;
-   input                          ENA;
-   input [WE_WIDTH-1:0]           WEA;
-   input [ADDR_WIDTH-1:0]         ADDRA;
-   input [DATA_WIDTH-1:0]         DIA;
-   output [DATA_WIDTH-1:0]        DOA;
-
-   input                          CLKB;
-   input                          ENB;
-   input [WE_WIDTH-1:0]           WEB;
-   input [ADDR_WIDTH-1:0]         ADDRB;
-   input [DATA_WIDTH-1:0]         DIB;
-   output [DATA_WIDTH-1:0]        DOB;
-
-   (* RAM_STYLE = "BLOCK" *)
-   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
-   reg [DATA_WIDTH-1:0]           DOA_R;
-   reg [DATA_WIDTH-1:0]           DOA_R2;
-   reg [DATA_WIDTH-1:0]           DOB_R;
-   reg [DATA_WIDTH-1:0]           DOB_R2;
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else
-   // synopsys translate_off
-   integer                        i;
-   initial
-   begin : init_block
-      for (i = 0; i < MEMSIZE; i = i + 1) begin
-         RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      end
-      DOA_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOB_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-   end
-   // synopsys translate_on
-`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
-
-   // PORT A
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASKA, IMASKA;
-   reg  [DATA_WIDTH-1:0] DATA_A;
-   wire [DATA_WIDTH-1:0] DATA_Awr;
-
-   assign DATA_Awr = RAM[ADDRA];
-
-   always @(WEA or DIA or DATA_Awr) begin : combo1
-      integer j;
-      MASKA  = 0;
-      IMASKA = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WEA[j]) MASKA = (MASKA << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else        MASKA = (MASKA << 8);
-      end
-      IMASKA = ~MASKA;
-
-      DATA_A = (DATA_Awr & IMASKA) | (DIA & MASKA);
-   end
-
-   always @(posedge CLKA) begin
-      if (ENA) begin
-         if (WEA) begin
-            RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DATA_A;
-            DOA_R      <= `BSV_ASSIGNMENT_DELAY DATA_A;
-         end
-         else begin
-            DOA_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
-         end
-      end
-   end
-`else
-   generate
-      genvar j;
-      for(j = 0; j < WE_WIDTH; j = j + 1) begin: porta_we
-         always @(posedge CLKA) begin
-            if (ENA) begin
-               if (WEA[j]) begin
-                  RAM[ADDRA][((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIA[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
-                  DOA_R[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY DIA[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
-               end
-               else begin
-                  DOA_R[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA][((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
-               end
-            end
-         end
-      end
-   endgenerate
-`endif // !`ifdef __ICARUS__
-
-
-   // PORT B
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASKB, IMASKB;
-   reg  [DATA_WIDTH-1:0] DATA_B;
-   wire [DATA_WIDTH-1:0] DATA_Bwr;
-
-   assign DATA_Bwr = RAM[ADDRB];
-
-   always @(WEB or DIB or DATA_Bwr) begin : combo2
-      integer j;
-      MASKB  = 0;
-      IMASKB = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WEB[j]) MASKB = (MASKB << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else        MASKB = (MASKB << 8);
-      end
-      IMASKB = ~MASKB;
-
-      DATA_B = (DATA_Bwr & IMASKB) | (DIB & MASKB);
-   end
-
-   always @(posedge CLKB) begin
-      if (ENB) begin
-         if (WEB) begin
-            RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DATA_B;
-            DOB_R      <= `BSV_ASSIGNMENT_DELAY DATA_B;
-         end
-         else begin
-            DOB_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
-         end
-      end
-   end
-`else
-   generate
-      genvar k;
-      for(k = 0; k < WE_WIDTH; k = k + 1) begin: portb_we
-         always @(posedge CLKB) begin
-            if (ENB) begin
-               if (WEB[k]) begin
-                  RAM[ADDRB][((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIB[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
-                  DOB_R[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY DIB[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
-               end
-               else begin
-                  DOB_R[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB][((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
-               end
-            end
-         end
-      end
-   endgenerate
-`endif // !`ifdef __ICARUS__
-
-
-   // Output drivers
-   always @(posedge CLKA) begin
-      DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
-   end
-
-   always @(posedge CLKB) begin
-      DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
-   end
-
-   assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
-   assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
-
-endmodule // BRAM2BE
diff --git a/src/Verilog.Vivado/BRAM2BELoad.v b/src/Verilog.Vivado/BRAM2BELoad.v
deleted file mode 100644
index 4402ae7af..000000000
--- a/src/Verilog.Vivado/BRAM2BELoad.v
+++ /dev/null
@@ -1,193 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
- `define BSV_ASSIGNMENT_DELAY
-`endif
-
-// Dual-Ported BRAM (WRITE FIRST) with byte enables and ability to load from a file
-module BRAM2BELoad(CLKA,
-                   ENA,
-                   WEA,
-                   ADDRA,
-                   DIA,
-                   DOA,
-                   CLKB,
-                   ENB,
-                   WEB,
-                   ADDRB,
-                   DIB,
-                   DOB
-                  );
-
-   parameter                      FILENAME   = "";
-   parameter                      PIPELINED  = 0;
-   parameter                      ADDR_WIDTH = 1;
-   parameter                      DATA_WIDTH = 1;
-   parameter                      CHUNKSIZE  = 1;
-   parameter                      WE_WIDTH   = 1;
-   parameter                      MEMSIZE    = 1;
-   parameter                      BINARY     = 0;
-
-   input                          CLKA;
-   input                          ENA;
-   input [WE_WIDTH-1:0]           WEA;
-   input [ADDR_WIDTH-1:0]         ADDRA;
-   input [DATA_WIDTH-1:0]         DIA;
-   output [DATA_WIDTH-1:0]        DOA;
-
-   input                          CLKB;
-   input                          ENB;
-   input [WE_WIDTH-1:0]           WEB;
-   input [ADDR_WIDTH-1:0]         ADDRB;
-   input [DATA_WIDTH-1:0]         DIB;
-   output [DATA_WIDTH-1:0]        DOB;
-
-   (* RAM_STYLE = "BLOCK" *)
-   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
-   reg [DATA_WIDTH-1:0]           DOA_R;
-   reg [DATA_WIDTH-1:0]           DOA_R2;
-   reg [DATA_WIDTH-1:0]           DOB_R;
-   reg [DATA_WIDTH-1:0]           DOB_R2;
-
-   // synopsys translate_off
-   initial
-   begin : init_block
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else
-      DOA_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOB_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
-   end
-   // synopsys translate_on
-
-   initial
-   begin : init_rom_block
-      if (BINARY)
-        $readmemb(FILENAME, RAM, 0, MEMSIZE-1);
-      else
-        $readmemh(FILENAME, RAM, 0, MEMSIZE-1);
-   end
-   
-   // PORT A
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASKA, IMASKA;
-   reg  [DATA_WIDTH-1:0] DATA_A;
-   wire [DATA_WIDTH-1:0] DATA_Awr;
-
-   assign DATA_Awr = RAM[ADDRA];
-
-   always @(WEA or DIA or DATA_Awr) begin : combo1
-      integer j;
-      MASKA  = 0;
-      IMASKA = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WEA[j]) MASKA = (MASKA << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else        MASKA = (MASKA << 8);
-      end
-      IMASKA = ~MASKA;
-
-      DATA_A = (DATA_Awr & IMASKA) | (DIA & MASKA);
-   end
-
-   always @(posedge CLKA) begin
-      if (ENA) begin
-         if (WEA) begin
-            RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DATA_A;
-            DOA_R      <= `BSV_ASSIGNMENT_DELAY DATA_A;
-         end
-         else begin
-            DOA_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
-         end
-      end
-   end
-`else
-   generate
-      genvar i;
-      for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we
-         always @(posedge CLKA) begin
-            if (ENA) begin
-               if (WEA[i]) begin
-                  RAM[ADDRA][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIA[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-                  DOA_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY DIA[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-               end
-               else begin
-                  DOA_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
-               end
-            end
-         end
-      end
-   endgenerate
-`endif // !`ifdef __ICARUS__
-
-   // PORT B
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASKB, IMASKB;
-   reg  [DATA_WIDTH-1:0] DATA_B;
-   wire [DATA_WIDTH-1:0] DATA_Bwr;
-
-   assign DATA_Bwr = RAM[ADDRB];
-
-   always @(WEB or DIB or DATA_Bwr) begin : combo2
-      integer j;
-      MASKB  = 0;
-      IMASKB = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WEB[j]) MASKB = (MASKB << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else        MASKB = (MASKB << 8);
-      end
-      IMASKB = ~MASKB;
-
-      DATA_B = (DATA_Bwr & IMASKB) | (DIB & MASKB);
-   end
-
-   always @(posedge CLKB) begin
-      if (ENB) begin
-         if (WEB) begin
-            RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DATA_B;
-            DOB_R      <= `BSV_ASSIGNMENT_DELAY DATA_B;
-         end
-         else begin
-            DOB_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
-         end
-      end
-   end
-`else
-   generate
-      genvar k;
-      for(k = 0; k < WE_WIDTH; k = k + 1) begin: portb_we
-         always @(posedge CLKB) begin
-            if (ENB) begin
-               if (WEB[k]) begin
-                  RAM[ADDRB][((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIB[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
-                  DOB_R[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY DIB[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
-               end
-               else begin
-                  DOB_R[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB][((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
-               end
-            end
-         end
-      end
-   endgenerate
-`endif // !`ifdef __ICARUS__
-
-   // Output drivers
-   always @(posedge CLKA) begin
-      DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
-   end
-
-   always @(posedge CLKB) begin
-      DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
-   end
-
-   assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
-   assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
-
-endmodule // BRAM2BELoad
diff --git a/src/Verilog.Vivado/BRAM2Load.v b/src/Verilog.Vivado/BRAM2Load.v
deleted file mode 100644
index c061d3486..000000000
--- a/src/Verilog.Vivado/BRAM2Load.v
+++ /dev/null
@@ -1,101 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
- `define BSV_ASSIGNMENT_DELAY
-`endif
-
-// Dual-Ported BRAM (WRITE FIRST)
-module BRAM2Load(CLKA,
-                 ENA,
-                 WEA,
-                 ADDRA,
-                 DIA,
-                 DOA,
-                 CLKB,
-                 ENB,
-                 WEB,
-                 ADDRB,
-                 DIB,
-                 DOB
-                 );
-
-   parameter                      FILENAME   = "";
-   parameter                      PIPELINED  = 0;
-   parameter                      ADDR_WIDTH = 1;
-   parameter                      DATA_WIDTH = 1;
-   parameter                      MEMSIZE    = 1;
-   parameter                      BINARY     = 0;
-
-   input                          CLKA;
-   input                          ENA;
-   input                          WEA;
-   input [ADDR_WIDTH-1:0]         ADDRA;
-   input [DATA_WIDTH-1:0]         DIA;
-   output [DATA_WIDTH-1:0]        DOA;
-
-   input                          CLKB;
-   input                          ENB;
-   input                          WEB;
-   input [ADDR_WIDTH-1:0]         ADDRB;
-   input [DATA_WIDTH-1:0]         DIB;
-   output [DATA_WIDTH-1:0]        DOB;
-
-   (* RAM_STYLE = "BLOCK" *)
-   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
-   reg [DATA_WIDTH-1:0]           DOA_R;
-   reg [DATA_WIDTH-1:0]           DOB_R;
-   reg [DATA_WIDTH-1:0]           DOA_R2;
-   reg [DATA_WIDTH-1:0]           DOB_R2;
-
-   // synopsys translate_off
-   initial
-   begin : init_block
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else
-      DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-      DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
-`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
-   end
-   // synopsys translate_on
-
-   initial
-   begin : init_rom_block
-      if (BINARY)
-        $readmemb(FILENAME, RAM, 0, MEMSIZE-1);
-      else
-        $readmemh(FILENAME, RAM, 0, MEMSIZE-1);
-   end
-
-   always @(posedge CLKA) begin
-      if (ENA) begin
-         if (WEA) begin
-            RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
-            DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
-         end
-         else begin
-            DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
-         end
-      end
-      DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
-   end
-
-   always @(posedge CLKB) begin
-      if (ENB) begin
-         if (WEB) begin
-            RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
-            DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
-         end
-         else begin
-            DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
-         end
-      end
-      DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
-   end
-
-   // Output drivers
-   assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
-   assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
-
-endmodule // BRAM2Load
diff --git a/src/Verilog.Vivado/MakeClock.v b/src/Verilog.Vivado/MakeClock.v
deleted file mode 100644
index 331291b80..000000000
--- a/src/Verilog.Vivado/MakeClock.v
+++ /dev/null
@@ -1,125 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
-  `define BSV_ASSIGNMENT_DELAY
-`endif
-
-`ifdef BSV_POSITIVE_RESET
-  `define BSV_RESET_VALUE 1'b1
-  `define BSV_RESET_EDGE posedge
-`else
-  `define BSV_RESET_VALUE 1'b0
-  `define BSV_RESET_EDGE negedge
-`endif
-
-
-// Bluespec primitive module which allows creation of clocks
-// with non-constant periods.  The CLK_IN and COND_IN inputs
-// are registered and used to compute the CLK_OUT and
-// CLK_GATE_OUT outputs.
-module MakeClock ( CLK, RST,
-                   CLK_IN, CLK_IN_EN,
-                   COND_IN, COND_IN_EN,
-                   CLK_VAL_OUT, COND_OUT,
-                   CLK_OUT, CLK_GATE_OUT );
-
-   parameter initVal = 0;
-   parameter initGate = 1;
-
-   input  CLK;
-   input  RST;
-
-   input  CLK_IN;
-   input  CLK_IN_EN;
-   input  COND_IN;
-   input  COND_IN_EN;
-
-   output CLK_VAL_OUT;
-   output COND_OUT;
-   (* CLOCK_SIGNAL = "YES" *)
-   (* BUFFER_TYPE = "BUFG" *)
-   output CLK_OUT;
-   output CLK_GATE_OUT;
-
-   (* KEEP = "TRUE" *)
-   reg current_clk;
-   reg CLK_VAL_OUT;
-   reg current_gate;
-   reg new_gate;
-
-   // The use of blocking assignment within this block insures
-   // that the clock generated from the generate clock (current_clK) occurs before any
-   // LHS of nonblocking assignments also from CLKoccur.
-   // Basically, this insures that CLK_OUT and CLK occur within
-   // the same phase of the execution cycle,  before any state
-   // updates occur. see
-   // http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf
-   always @(posedge CLK or `BSV_RESET_EDGE RST)
-   begin
-     if (RST == `BSV_RESET_VALUE)
-     begin
-       current_clk = initVal;
-     end
-     else
-     begin
-       if (CLK_IN_EN)
-         current_clk = CLK_IN;
-     end
-   end
-
-   // Duplicate flop for DRC -- clocks cannot be used as data
-   always @(posedge CLK or `BSV_RESET_EDGE RST)
-   begin
-     if (RST == `BSV_RESET_VALUE)
-     begin
-       CLK_VAL_OUT <=  `BSV_ASSIGNMENT_DELAY initVal;
-     end
-     else
-     begin
-       if (CLK_IN_EN)
-         CLK_VAL_OUT <=  `BSV_ASSIGNMENT_DELAY CLK_IN;
-     end
-   end
-
-   always @(posedge CLK or `BSV_RESET_EDGE RST)
-   begin
-     if (RST == `BSV_RESET_VALUE)
-       new_gate   <=  `BSV_ASSIGNMENT_DELAY initGate;
-     else
-     begin
-       if (COND_IN_EN)
-         new_gate <=  `BSV_ASSIGNMENT_DELAY  COND_IN;
-     end
-   end
-
-
-   // Use latch to avoid glitches
-   // Gate can only change when clock is low
-   // There remains a fundamental race condition in this design, which
-   // is triggered when the current_clk rises and the the new_gate
-   // changes.  We recommend to avoid changing the gate in the same
-   // cycle when the clock rises.
-   always @( current_clk or new_gate )
-     begin
-        if (current_clk == 1'b0)
-          current_gate  <= `BSV_ASSIGNMENT_DELAY new_gate ;
-     end
-
-   assign CLK_OUT      = current_clk && current_gate;
-   assign CLK_GATE_OUT = current_gate;
-   assign COND_OUT     = new_gate;
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
-   initial begin
-      #0 ;
-      current_clk  = 1'b0 ;
-      current_gate = 1'b1 ;
-      new_gate     = 1'b1 ;
-      CLK_VAL_OUT  = 1'b0;
-   end
-   // synopsys translate_on
-`endif // BSV_NO_INITIAL_BLOCKS
-
-endmodule
diff --git a/src/Verilog.Vivado/RegFile.v b/src/Verilog.Vivado/RegFile.v
deleted file mode 100644
index f89e9e1b4..000000000
--- a/src/Verilog.Vivado/RegFile.v
+++ /dev/null
@@ -1,101 +0,0 @@
-
-`ifdef  BSV_WARN_REGFILE_ADDR_RANGE
-`else
-`define BSV_WARN_REGFILE_ADDR_RANGE 0 
-`endif
-
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
-`define BSV_ASSIGNMENT_DELAY
-`endif
-
-
-// Multi-ported Register File
-module RegFile(CLK,
-               ADDR_IN, D_IN, WE,
-               ADDR_1, D_OUT_1,
-               ADDR_2, D_OUT_2,
-               ADDR_3, D_OUT_3,
-               ADDR_4, D_OUT_4,
-               ADDR_5, D_OUT_5
-               );
-   parameter                   addr_width = 1;
-   parameter                   data_width = 1;
-   parameter                   lo = 0;
-   parameter                   hi = 1;
-
-   input                       CLK;
-   input [addr_width - 1 : 0]  ADDR_IN;
-   input [data_width - 1 : 0]  D_IN;
-   input                       WE;
-
-   input [addr_width - 1 : 0]  ADDR_1;
-   output [data_width - 1 : 0] D_OUT_1;
-
-   input [addr_width - 1 : 0]  ADDR_2;
-   output [data_width - 1 : 0] D_OUT_2;
-
-   input [addr_width - 1 : 0]  ADDR_3;
-   output [data_width - 1 : 0] D_OUT_3;
-
-   input [addr_width - 1 : 0]  ADDR_4;
-   output [data_width - 1 : 0] D_OUT_4;
-
-   input [addr_width - 1 : 0]  ADDR_5;
-   output [data_width - 1 : 0] D_OUT_5;
-
-   (* RAM_STYLE = "DISTRIBUTED" *)
-   reg [data_width - 1 : 0]    arr[lo:hi];
-
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
-   initial
-     begin : init_block
-        integer                     i;          // temporary for generate reset value
-        for (i = lo; i <= hi; i = i + 1) begin
-           arr[i] = {((data_width + 1)/2){2'b10}} ;
-        end
-     end // initial begin
-   // synopsys translate_on
-`endif // BSV_NO_INITIAL_BLOCKS
-
-
-   always@(posedge CLK)
-     begin
-        if (WE)
-          arr[ADDR_IN] <= `BSV_ASSIGNMENT_DELAY D_IN;
-     end // always@ (posedge CLK)
-
-   assign D_OUT_1 = arr[ADDR_1];
-   assign D_OUT_2 = arr[ADDR_2];
-   assign D_OUT_3 = arr[ADDR_3];
-   assign D_OUT_4 = arr[ADDR_4];
-   assign D_OUT_5 = arr[ADDR_5];
-
-   // synopsys translate_off
-   always@(posedge CLK)
-     begin : runtime_check
-        reg enable_check;
-        enable_check = `BSV_WARN_REGFILE_ADDR_RANGE ;
-        if ( enable_check )
-           begin
-              if (( ADDR_1 < lo ) || (ADDR_1 > hi) )
-                $display( "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", ADDR_1 ) ;
-              if (( ADDR_2 < lo ) || (ADDR_2 > hi) )
-                $display( "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", ADDR_2 ) ;
-              if (( ADDR_3 < lo ) || (ADDR_3 > hi) )
-                $display( "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", ADDR_3 ) ;
-              if (( ADDR_4 < lo ) || (ADDR_4 > hi) )
-                $display( "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", ADDR_4 ) ;
-              if (( ADDR_5 < lo ) || (ADDR_5 > hi) )
-                $display( "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", ADDR_5 ) ;
-              if ( WE && ( ADDR_IN < lo ) || (ADDR_IN > hi) )
-                $display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ;
-           end
-     end
-   // synopsys translate_on
-
-endmodule
diff --git a/src/Verilog.Vivado/SizedFIFO.v b/src/Verilog.Vivado/SizedFIFO.v
deleted file mode 100644
index a2a89444d..000000000
--- a/src/Verilog.Vivado/SizedFIFO.v
+++ /dev/null
@@ -1,259 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
-  `define BSV_ASSIGNMENT_DELAY
-`endif
-
-`ifdef BSV_POSITIVE_RESET
-  `define BSV_RESET_VALUE 1'b1
-  `define BSV_RESET_EDGE posedge
-`else
-  `define BSV_RESET_VALUE 1'b0
-  `define BSV_RESET_EDGE negedge
-`endif
-
-`ifdef BSV_ASYNC_RESET
- `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
-`else
- `define BSV_ARESET_EDGE_META
-`endif
-
-`ifdef BSV_RESET_FIFO_HEAD
- `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
-`else
- `define BSV_ARESET_EDGE_HEAD
-`endif
-
-`ifdef BSV_RESET_FIFO_ARRAY
- `define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
-`else
- `define BSV_ARESET_EDGE_ARRAY
-`endif
-
-
-// Sized fifo.  Model has output register which improves timing
-module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
-   parameter               p1width = 1; // data width
-   parameter               p2depth = 3;
-   parameter               p3cntr_width = 1; // log(p2depth-1)
-   // The -1 is allowed since this model has a fast output register
-   parameter               guarded = 1'b1;
-   localparam              p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
-
-   input                   CLK;
-   input                   RST;
-   input                   CLR;
-   input [p1width - 1 : 0] D_IN;
-   input                   ENQ;
-   input                   DEQ;
-
-   output                  FULL_N;
-   output                  EMPTY_N;
-   output [p1width - 1 : 0] D_OUT;
-
-   reg                      not_ring_full;
-   reg                      ring_empty;
-
-   reg [p3cntr_width-1 : 0] head;
-   wire [p3cntr_width-1 : 0] next_head;
-
-   reg [p3cntr_width-1 : 0]  tail;
-   wire [p3cntr_width-1 : 0] next_tail;
-
-   // if the depth is too small, don't create an ill-sized array;
-   // instead, make a 1-sized array and let the initial block report an error
-   (* RAM_STYLE = "DISTRIBUTED" *)
-   reg [p1width - 1 : 0]     arr[0: p2depth2];
-
-   reg [p1width - 1 : 0]     D_OUT;
-   reg                       hasodata;
-
-   wire [p3cntr_width-1:0]   depthLess2 = p2depth2[p3cntr_width-1:0] ;
-
-   wire [p3cntr_width-1 : 0] incr_tail;
-   wire [p3cntr_width-1 : 0] incr_head;
-
-   assign                    incr_tail = tail + 1'b1 ;
-   assign                    incr_head = head + 1'b1 ;
-
-   assign    next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
-   assign    next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
-
-   assign    EMPTY_N = hasodata;
-   assign    FULL_N  = not_ring_full;
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
-   initial
-     begin : initial_block
-        integer   i;
-        D_OUT         = {((p1width + 1)/2){2'b10}} ;
-
-        ring_empty    = 1'b1;
-        not_ring_full = 1'b1;
-        hasodata      = 1'b0;
-        head          = {p3cntr_width {1'b0}} ;
-        tail          = {p3cntr_width {1'b0}} ;
-
-        for (i = 0; i <= p2depth2; i = i + 1)
-          begin
-             arr[i]   = D_OUT ;
-          end
-     end
-   // synopsys translate_on
-`endif // BSV_NO_INITIAL_BLOCKS
-
-
-   always @(posedge CLK `BSV_ARESET_EDGE_META)
-     begin
-        if (RST == `BSV_RESET_VALUE)
-          begin
-             head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
-             tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
-             ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
-             not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
-             hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
-          end // if (RST == `BSV_RESET_VALUE)
-        else
-         begin
-
-             casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
-               // Clear operation
-               5'b1????: begin
-                  head          <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
-                  tail          <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
-                  ring_empty    <= `BSV_ASSIGNMENT_DELAY 1'b1;
-                  not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
-                  hasodata      <= `BSV_ASSIGNMENT_DELAY 1'b0;
-               end
-               // -----------------------
-               // DEQ && ENQ case -- change head and tail if added to ring
-               5'b011?0: begin
-                  tail          <= `BSV_ASSIGNMENT_DELAY next_tail;
-                  head          <= `BSV_ASSIGNMENT_DELAY next_head;
-               end
-               // -----------------------
-               // DEQ only and NO data is in ring
-               5'b010?1: begin
-                  hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
-               end
-               // DEQ only and data is in ring (move the head pointer)
-               5'b010?0: begin
-                  head          <= `BSV_ASSIGNMENT_DELAY next_head;
-                  not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
-                  ring_empty    <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
-               end
-               // -----------------------
-               // ENQ only when empty
-               5'b0010?: begin
-                  hasodata      <= `BSV_ASSIGNMENT_DELAY 1'b1;
-                  end
-               // ENQ only when not empty
-               5'b0011?: begin
-                  if ( not_ring_full ) // Drop this test to save redundant test
-                    // but be warnned that with test fifo overflow causes loss of new data
-                    // while without test fifo drops all but head entry! (pointer overflow)
-                   begin
-                      tail          <= `BSV_ASSIGNMENT_DELAY next_tail;
-                      ring_empty    <= `BSV_ASSIGNMENT_DELAY 1'b0;
-                      not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
-                   end
-               end
-             endcase
-         end // else: !if(RST == `BSV_RESET_VALUE)
-     end // always @ (posedge CLK)
-
-   // Update the fast data out register
-   always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
-     begin
-`ifdef  BSV_RESET_FIFO_HEAD
-        if (RST == `BSV_RESET_VALUE)
-          begin
-             D_OUT    <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
-          end // if (RST == `BSV_RESET_VALUE)
-        else
-`endif
-        begin
-             casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
-               // DEQ && ENQ cases
-               5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
-               5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
-               // DEQ only and data is in ring
-               5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
-               // ENQ only when empty
-               5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
-             endcase
-          end // else: !if(RST == `BSV_RESET_VALUE)
-     end // always @ (posedge CLK)
-
-   // Update the memory array  reset is OFF
-   always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
-     begin: array
-`ifdef BSV_RESET_FIFO_ARRAY
-        if (RST == `BSV_RESET_VALUE)
-          begin: rst_array
-             integer i;
-             for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
-               begin
-                   arr[i]  <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
-               end
-          end // if (RST == `BSV_RESET_VALUE)
-        else
-`endif
-         begin
-            if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
-              begin
-                 arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
-              end
-         end // else: !if(RST == `BSV_RESET_VALUE)
-     end // always @ (posedge CLK)
-
-   // synopsys translate_off
-   always@(posedge CLK)
-     begin: error_checks
-        reg deqerror, enqerror ;
-
-        deqerror =  0;
-        enqerror = 0;
-        if (RST == ! `BSV_RESET_VALUE)
-           begin
-              if ( ! EMPTY_N && DEQ )
-                begin
-                   deqerror = 1 ;
-                   $display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
-                end
-              if ( ! FULL_N && ENQ && (!DEQ || guarded) )
-                begin
-                   enqerror =  1 ;
-                   $display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
-                end
-           end
-     end // block: error_checks
-   // synopsys translate_on
-
-   // synopsys translate_off
-   // Some assertions about parameter values
-   initial
-     begin : parameter_assertions
-        integer ok ;
-        ok = 1 ;
-
-        if ( p2depth <= 1)
-          begin
-             ok = 0;
-             $display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
-          end
-
-        if ( p3cntr_width <= 0 )
-          begin
-             ok = 0;
-             $display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
-          end
-
-        if ( ok == 0 ) $finish ;
-
-      end // initial begin
-   // synopsys translate_on
-
-endmodule
diff --git a/src/Verilog/ASSIGN1.v b/src/Verilog/ASSIGN1.v
deleted file mode 100644
index 4bedc0bd1..000000000
--- a/src/Verilog/ASSIGN1.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module ASSIGN1(IN, OUT);
-   output OUT;
-   input IN;
-   assign OUT = IN;
-endmodule
diff --git a/src/Verilog/BRAM1.v b/src/Verilog/BRAM1.v
index a6a5cda4f..628ce16e2 100644
--- a/src/Verilog/BRAM1.v
+++ b/src/Verilog/BRAM1.v
@@ -25,6 +25,9 @@ module BRAM1(CLK,
    input [DATA_WIDTH-1:0]         DI;
    output [DATA_WIDTH-1:0]        DO;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "BLOCK" *)
+`endif
    reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];
    reg [DATA_WIDTH-1:0]           DO_R;
    reg [DATA_WIDTH-1:0]           DO_R2;
diff --git a/src/Verilog/BRAM1BE.v b/src/Verilog/BRAM1BE.v
index b8a5cde14..30aada53d 100644
--- a/src/Verilog/BRAM1BE.v
+++ b/src/Verilog/BRAM1BE.v
@@ -27,6 +27,9 @@ module BRAM1BE(CLK,
    input [DATA_WIDTH-1:0]         DI;
    output [DATA_WIDTH-1:0]        DO;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "BLOCK" *)
+`endif
    reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];
    reg [DATA_WIDTH-1:0]           DO_R;
    reg [DATA_WIDTH-1:0]           DO_R2;
@@ -47,40 +50,6 @@ module BRAM1BE(CLK,
    // synopsys translate_on
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
 
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASK, IMASK;
-   reg [DATA_WIDTH-1:0]  DATA;
-   wire [DATA_WIDTH-1:0] DATAwr;
-
-   assign DATAwr = RAM[ADDR] ;
-
-   always @(WE or DI or DATAwr) begin : combo1
-      integer j;
-      MASK  = 0;
-      IMASK = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else       MASK = (MASK << 8);
-      end
-      IMASK = ~MASK;
-
-      DATA = (DATAwr & IMASK) | (DI & MASK);
-   end
-
-   always @(posedge CLK) begin
-      if (EN) begin
-         if (WE) begin
-            RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
-            DO_R      <= `BSV_ASSIGNMENT_DELAY DATA;
-         end
-         else begin
-            DO_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
-         end
-      end
-   end
-`else
    generate
       genvar i;
       for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we
@@ -98,8 +67,6 @@ module BRAM1BE(CLK,
       end      
    endgenerate
 
-`endif // !`ifdef __ICARUS__
-
    // Output driver
    always @(posedge CLK) begin
       DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
diff --git a/src/Verilog/BRAM1BELoad.v b/src/Verilog/BRAM1BELoad.v
index bbe333321..67348f1da 100644
--- a/src/Verilog/BRAM1BELoad.v
+++ b/src/Verilog/BRAM1BELoad.v
@@ -29,6 +29,9 @@ module BRAM1BELoad(CLK,
    input [DATA_WIDTH-1:0]         DI;
    output [DATA_WIDTH-1:0]        DO;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "BLOCK" *)
+`endif
    reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];
    reg [DATA_WIDTH-1:0]           DO_R;
    reg [DATA_WIDTH-1:0]           DO_R2;
@@ -52,42 +55,6 @@ module BRAM1BELoad(CLK,
         $readmemh(FILENAME, RAM, 0, MEMSIZE-1);
    end
 
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASK, IMASK;
-   reg [DATA_WIDTH-1:0]  DATA;
-   wire [DATA_WIDTH-1:0] DATAwr;
-
-   assign DATAwr = RAM[ADDR] ;
-
-
-   always @(WE or DI or DATAwr) begin : combo1
-      integer j;
-      MASK  = 0;
-      IMASK = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else       MASK = (MASK << 8);
-      end
-      IMASK = ~MASK;
-
-      DATA = (DATAwr & IMASK) | (DI & MASK);
-   end
-
-   
-   always @(posedge CLK) begin
-      if (EN) begin
-         if (WE) begin
-            RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
-            DO_R      <= `BSV_ASSIGNMENT_DELAY DATA;
-         end
-         else begin
-            DO_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
-         end
-      end
-   end
-`else
    generate
       genvar i;
       for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we
@@ -104,7 +71,6 @@ module BRAM1BELoad(CLK,
          end
       end      
    endgenerate
-`endif // !`ifdef __ICARUS__
 
    // Output driver
    always @(posedge CLK) begin
diff --git a/src/Verilog/BRAM1Load.v b/src/Verilog/BRAM1Load.v
index c514fe4f3..30a4b0633 100644
--- a/src/Verilog/BRAM1Load.v
+++ b/src/Verilog/BRAM1Load.v
@@ -27,6 +27,9 @@ module BRAM1Load(CLK,
    input [DATA_WIDTH-1:0]         DI;
    output [DATA_WIDTH-1:0]        DO;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "BLOCK" *)
+`endif
    reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];
    reg [DATA_WIDTH-1:0]           DO_R;
    reg [DATA_WIDTH-1:0]           DO_R2;
diff --git a/src/Verilog/BRAM2.v b/src/Verilog/BRAM2.v
index 417ee3148..8bbe53aa8 100644
--- a/src/Verilog/BRAM2.v
+++ b/src/Verilog/BRAM2.v
@@ -38,6 +38,9 @@ module BRAM2(CLKA,
    input [DATA_WIDTH-1:0]         DIB;
    output [DATA_WIDTH-1:0]        DOB;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "BLOCK" *)
+`endif
    reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
    reg [DATA_WIDTH-1:0]           DOA_R;
    reg [DATA_WIDTH-1:0]           DOB_R;
diff --git a/src/Verilog/BRAM2BE.v b/src/Verilog/BRAM2BE.v
index 50d40bcc1..3230dc719 100644
--- a/src/Verilog/BRAM2BE.v
+++ b/src/Verilog/BRAM2BE.v
@@ -40,6 +40,9 @@ module BRAM2BE(CLKA,
    input [DATA_WIDTH-1:0]         DIB;
    output [DATA_WIDTH-1:0]        DOB;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "BLOCK" *)
+`endif
    reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
    reg [DATA_WIDTH-1:0]           DOA_R;
    reg [DATA_WIDTH-1:0]           DOA_R2;
@@ -64,41 +67,6 @@ module BRAM2BE(CLKA,
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
 
    // PORT A
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASKA, IMASKA;
-   reg  [DATA_WIDTH-1:0] DATA_A;
-   wire [DATA_WIDTH-1:0] DATA_Awr;
-
-   assign DATA_Awr = RAM[ADDRA];
-
-   always @(WEA or DIA or DATA_Awr) begin : combo1
-      integer j;
-      MASKA  = 0;
-      IMASKA = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WEA[j]) MASKA = (MASKA << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else        MASKA = (MASKA << 8);
-      end
-      IMASKA = ~MASKA;
-
-      DATA_A = (DATA_Awr & IMASKA) | (DIA & MASKA);
-   end
-
-   always @(posedge CLKA) begin
-      if (ENA) begin
-         if (WEA) begin
-            RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DATA_A;
-            DOA_R      <= `BSV_ASSIGNMENT_DELAY DATA_A;
-         end
-         else begin
-            DOA_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
-         end
-      end
-   end
-`else
    generate
       genvar j;
       for(j = 0; j < WE_WIDTH; j = j + 1) begin: porta_we
@@ -115,45 +83,8 @@ module BRAM2BE(CLKA,
          end
       end
    endgenerate
-`endif // !`ifdef __ICARUS__
-
 
    // PORT B
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASKB, IMASKB;
-   reg  [DATA_WIDTH-1:0] DATA_B;
-   wire [DATA_WIDTH-1:0] DATA_Bwr;
-
-   assign DATA_Bwr = RAM[ADDRB];
-
-   always @(WEB or DIB or DATA_Bwr) begin : combo2
-      integer j;
-      MASKB  = 0;
-      IMASKB = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WEB[j]) MASKB = (MASKB << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else        MASKB = (MASKB << 8);
-      end
-      IMASKB = ~MASKB;
-
-      DATA_B = (DATA_Bwr & IMASKB) | (DIB & MASKB);
-   end
-
-   always @(posedge CLKB) begin
-      if (ENB) begin
-         if (WEB) begin
-            RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DATA_B;
-            DOB_R      <= `BSV_ASSIGNMENT_DELAY DATA_B;
-         end
-         else begin
-            DOB_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
-         end
-      end
-   end
-`else
    generate
       genvar k;
       for(k = 0; k < WE_WIDTH; k = k + 1) begin: portb_we
@@ -170,8 +101,6 @@ module BRAM2BE(CLKA,
          end
       end
    endgenerate
-`endif // !`ifdef __ICARUS__
-
 
    // Output drivers
    always @(posedge CLKA) begin
diff --git a/src/Verilog/BRAM2BELoad.v b/src/Verilog/BRAM2BELoad.v
index c65959688..3b9534ffe 100644
--- a/src/Verilog/BRAM2BELoad.v
+++ b/src/Verilog/BRAM2BELoad.v
@@ -42,6 +42,9 @@ module BRAM2BELoad(CLKA,
    input [DATA_WIDTH-1:0]         DIB;
    output [DATA_WIDTH-1:0]        DOB;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "BLOCK" *)
+`endif
    reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
    reg [DATA_WIDTH-1:0]           DOA_R;
    reg [DATA_WIDTH-1:0]           DOA_R2;
@@ -70,41 +73,6 @@ module BRAM2BELoad(CLKA,
    end
    
    // PORT A
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASKA, IMASKA;
-   reg  [DATA_WIDTH-1:0] DATA_A;
-   wire [DATA_WIDTH-1:0] DATA_Awr;
-
-   assign DATA_Awr = RAM[ADDRA];
-
-   always @(WEA or DIA or DATA_Awr) begin : combo1
-      integer j;
-      MASKA  = 0;
-      IMASKA = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WEA[j]) MASKA = (MASKA << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else        MASKA = (MASKA << 8);
-      end
-      IMASKA = ~MASKA;
-
-      DATA_A = (DATA_Awr & IMASKA) | (DIA & MASKA);
-   end
-
-   always @(posedge CLKA) begin
-      if (ENA) begin
-         if (WEA) begin
-            RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DATA_A;
-            DOA_R      <= `BSV_ASSIGNMENT_DELAY DATA_A;
-         end
-         else begin
-            DOA_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
-         end
-      end
-   end
-`else
    generate
       genvar i;
       for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we
@@ -121,44 +89,8 @@ module BRAM2BELoad(CLKA,
          end
       end
    endgenerate
-`endif // !`ifdef __ICARUS__
 
    // PORT B
-
-   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.
-`ifdef __ICARUS__
-   reg [DATA_WIDTH-1:0]  MASKB, IMASKB;
-   reg  [DATA_WIDTH-1:0] DATA_B;
-   wire [DATA_WIDTH-1:0] DATA_Bwr;
-
-   assign DATA_Bwr = RAM[ADDRB];
-
-   always @(WEB or DIB or DATA_Bwr) begin : combo2
-      integer j;
-      MASKB  = 0;
-      IMASKB = 0;
-
-      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
-         if (WEB[j]) MASKB = (MASKB << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
-         else        MASKB = (MASKB << 8);
-      end
-      IMASKB = ~MASKB;
-
-      DATA_B = (DATA_Bwr & IMASKB) | (DIB & MASKB);
-   end
-
-   always @(posedge CLKB) begin
-      if (ENB) begin
-         if (WEB) begin
-            RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DATA_B;
-            DOB_R      <= `BSV_ASSIGNMENT_DELAY DATA_B;
-         end
-         else begin
-            DOB_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
-         end
-      end
-   end
-`else
    generate
       genvar k;
       for(k = 0; k < WE_WIDTH; k = k + 1) begin: portb_we
@@ -175,7 +107,6 @@ module BRAM2BELoad(CLKA,
          end
       end
    endgenerate
-`endif // !`ifdef __ICARUS__
 
    // Output drivers
    always @(posedge CLKA) begin
diff --git a/src/Verilog/BRAM2Load.v b/src/Verilog/BRAM2Load.v
index da1b20415..e9cfb603e 100644
--- a/src/Verilog/BRAM2Load.v
+++ b/src/Verilog/BRAM2Load.v
@@ -40,6 +40,9 @@ module BRAM2Load(CLKA,
    input [DATA_WIDTH-1:0]         DIB;
    output [DATA_WIDTH-1:0]        DOB;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "BLOCK" *)
+`endif
    reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
    reg [DATA_WIDTH-1:0]           DOA_R;
    reg [DATA_WIDTH-1:0]           DOB_R;
diff --git a/src/Verilog/ClockGater.v b/src/Verilog/ClockGater.v
deleted file mode 100644
index 9c4532d02..000000000
--- a/src/Verilog/ClockGater.v
+++ /dev/null
@@ -1,43 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
-  `define BSV_ASSIGNMENT_DELAY
-`endif
-
-`ifdef BSV_POSITIVE_RESET
-  `define BSV_RESET_VALUE 1'b1
-  `define BSV_RESET_EDGE posedge
-`else
-  `define BSV_RESET_VALUE 1'b0
-  `define BSV_RESET_EDGE negedge
-`endif
-
-
-// Bluespec primitive module which gates a clock
-// To avoid glitches, CLK_GATE_OUT only changes  when CLK_IN is low.
-// CLK_GATE_OUT follows CLK_GATE_IN in the same cycle, but COND is first
-// registered, thus delaying the gate condition by one cycle.
-// In this model, the oscillator CLK_OUT does *not* stop when the CLK_GATE_IN or
-// COND are deasserted.
-module ClockGater(
-		  // ports for the internal register
-		  CLK,
-		  RST,
-                  COND,
-		  // ports for the output clock
-                  CLK_OUT,
-                  CLK_GATE_OUT );
-
-   parameter init = 1 ;
-
-   input  CLK ;
-   input  RST ;
-   input  COND ;
-   output CLK_OUT ;
-   output CLK_GATE_OUT ;
-
-   // BUFG buf_gC(.I(CLK), .O(CLK_OUT));
-   assign CLK_OUT = CLK;
-   //BUFG buf_gG(.I(COND),   .O(CLK_GATE_OUT));
-   assign CLK_GATE_OUT = COND;
-endmodule // GatedClock
diff --git a/src/Verilog/DualGrayCntr.v b/src/Verilog/DualGrayCntr.v
deleted file mode 100644
index 5ba5c51ed..000000000
--- a/src/Verilog/DualGrayCntr.v
+++ /dev/null
@@ -1,133 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
-  `define BSV_ASSIGNMENT_DELAY
-`endif
-
-`ifdef BSV_POSITIVE_RESET
-  `define BSV_RESET_VALUE 1'b1
-  `define BSV_RESET_EDGE posedge
-`else
-  `define BSV_RESET_VALUE 1'b0
-  `define BSV_RESET_EDGE negedge
-`endif
-
-
-// module which implements a dual Gray code and and binary counter
-// allowing increments or holds
-module DualGrayCntr (
-                 CLK,
-                 RST,
-                 INCR,
-                 B_OUT,         // Binary code output
-                 G_OUT          // Gray code output
-                 );
-   parameter             width = 1 ; // Minimum value = 1
-   parameter             init = {width {1'b0}} ;
-
-   input                 CLK ;
-   input                 RST ;
-   input                 INCR ;
-   output [width -1 : 0] B_OUT ;
-   output [width -1 : 0] G_OUT ;
-
-   reg [width -1 : 0]    B_reg ;// flop variable
-   reg [width -1 : 0]    G_reg ;// flop variable
-
-   // combnational signals
-   reg [width -1 : 0]    nextB;
-   reg [width -1 : 0]    nextG;
-
-   assign                G_OUT = G_reg ,
-                         B_OUT = B_reg ;
-
-   always @(posedge CLK or `BSV_RESET_EDGE RST)
-     begin
-        if (RST == `BSV_RESET_VALUE )
-          begin
-             B_reg <= `BSV_ASSIGNMENT_DELAY init ;
-             G_reg <= `BSV_ASSIGNMENT_DELAY init ;
-          end
-        else if ( INCR )
-          begin
-             B_reg <= `BSV_ASSIGNMENT_DELAY nextB ;
-             G_reg <= `BSV_ASSIGNMENT_DELAY nextG ;
-          end
-     end // always @ (posedge CLK)
-
-   // Combinational block
-   always @( B_reg )
-     begin : incr_block
-        nextB = B_reg + 1'b1 ;
-        nextG = nextB ^ (nextB >> 1) ;
-     end // block: incr_block
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
-   initial
-     begin
-        B_reg      = {((width + 1)/2){2'b10}} ;
-        G_reg      = {((width + 1)/2){2'b10}} ;
-      end
-   // synopsys translate_on
-
-   // Some assertions about parameter values
-   initial
-     begin : parameter_assertions
-        integer ok ;
-        ok = 1 ;
-
-        if ( width <= `BSV_ASSIGNMENT_DELAY 0 )
-          begin
-             ok = 0;
-             $display ( "ERROR DualGrayCntr.v: width parameter must be greater than 0" ) ;
-          end
-
-        if ( ok == 0 ) $finish ;
-
-      end // initial begin
-      // synopsys translate_on
-`endif // BSV_NO_INITIAL_BLOCKS
-
-endmodule // GrayCntr
-
-
-
-`ifdef testBluespec
-module testDualGrayCntr() ;
-   parameter dsize = 5 ;
-
-   wire      CLK ;
-   wire [dsize -1 :0] BOUT ;
-   wire [dsize -1 :0] GOUT ;
-
-   reg                RST ;
-
-   ClockGen#(20,10,10)  sysclk( CLK );
-
-   initial
-     begin
-        RST = `BSV_RESET_VALUE ;
-        $display( "running test" ) ;
-
-        $dumpfile("DualGrayCntr.dump");
-        $dumpvars(5) ;
-        $dumpon ;
-        #200 ;
-        RST = !`BSV_RESET_VALUE ;
-
-        #10000 $finish ;
-     end
-
-   DualGrayCntr #(dsize,0)
-     dut( CLK, RST,  1'b1, BOUT, GOUT ) ;
-
-   always @(negedge CLK)
-     begin
-        #1
-         $display( "Cntr is: %b %b" , BOUT, GOUT ) ;
-      end
-
-endmodule
-`endif
diff --git a/src/Verilog/GrayCntr.v b/src/Verilog/GrayCntr.v
deleted file mode 100644
index 912b9f745..000000000
--- a/src/Verilog/GrayCntr.v
+++ /dev/null
@@ -1,140 +0,0 @@
-
-`ifdef BSV_ASSIGNMENT_DELAY
-`else
-  `define BSV_ASSIGNMENT_DELAY
-`endif
-
-`ifdef BSV_POSITIVE_RESET
-  `define BSV_RESET_VALUE 1'b1
-  `define BSV_RESET_EDGE posedge
-`else
-  `define BSV_RESET_VALUE 1'b0
-  `define BSV_RESET_EDGE negedge
-`endif
-
-
-// module which implements a Gray code counter allowing increments or holds
-module GrayCntr (
-                 CLK,
-                 RST,
-                 INCR,
-                 Q_OUT
-                 );
-   parameter             width = 2 ; // Minimum value = 2
-   parameter             init = {width {1'b0}} ;
-
-   input                 CLK ;
-   input                 RST ;
-   input                 INCR ;
-   output [width -1 : 0] Q_OUT ;
-
-   reg [width -1 : 0]    Q_reg ;// flop variable
-   reg                   toggle;
-
-   // combnational signals
-   reg [width -1 : 0]    flips ;
-
-   assign                Q_OUT = Q_reg ;
-
-   always @(posedge CLK or `BSV_RESET_EDGE RST)
-     begin
-        if (RST == `BSV_RESET_VALUE)
-          begin
-             Q_reg <= `BSV_ASSIGNMENT_DELAY init ;
-             toggle <= `BSV_ASSIGNMENT_DELAY 0 ;
-          end
-        else begin
-           if ( INCR )
-             begin
-                Q_reg <= `BSV_ASSIGNMENT_DELAY Q_reg ^ flips ;
-                toggle <= `BSV_ASSIGNMENT_DELAY ~ toggle ;
-             end
-        end // else: !if(RST == `BSV_RESET_VALUE)
-     end // always @ (posedge CLK)
-
-   // Combinational block
-   always @(Q_reg or toggle)
-     begin : incr_block
-        integer               i;
-        reg [width - 1: 0]    tempshift;
-
-        flips[0] = ! toggle ;
-        for ( i = 1 ; i < (width - 1) ; i = i+1 )
-          begin
-             tempshift = Q_reg << (1 + width - i ) ;
-             flips[i] =  toggle & Q_reg[i-1] & ~(| tempshift ) ;
-          end
-        tempshift = Q_reg << 2 ;
-        flips[width-1] = toggle & ~(| tempshift ) ;
-
-     end // block: incr_block
-
-`ifdef BSV_NO_INITIAL_BLOCKS
-`else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
-   initial
-     begin
-        Q_reg      = {((width + 1)/2){2'b10}} ;
-        toggle     = 1'b1 ;
-      end
-   // synopsys translate_on
-
-   // synopsys translate_off
-   // Some assertions about parameter values
-   initial
-     begin : parameter_assertions
-        integer ok ;
-        ok = 1 ;
-
-        if ( width <= `BSV_ASSIGNMENT_DELAY 1 )
-          begin
-             ok = 0;
-             $display ( "ERROR GrayCntr.v: width parameter must be greater than 1" ) ;
-          end
-
-        if ( ok == 0 ) $finish ;
-
-      end // initial begin
-      // synopsys translate_on
-`endif // BSV_NO_INITIAL_BLOCKS
-
-endmodule // GrayCntr
-
-
-
-`ifdef testBluespec
-module testGrayCntr() ;
-   parameter dsize = 5 ;
-
-   wire      CLK ;
-   wire [dsize -1 :0] QOUT ;
-
-   reg                RST ;
-
-   ClockGen#(20,10,10)  sysclk( CLK );
-
-   initial
-     begin
-        RST = `BSV_RESET_VALUE ;
-        $display( "running test" ) ;
-
-        $dumpfile("GrayCntr.dump");
-        $dumpvars(5) ;
-        $dumpon ;
-        #200 ;
-        RST = !`BSV_RESET_VALUE ;
-
-        #10000 $finish ;
-     end
-
-   GrayCntr #(dsize,0)
-     dut( CLK, RST,  1'b1, QOUT ) ;
-
-   always @(negedge CLK)
-     begin
-        #1
-         $display( "Cntr is: %b" , QOUT ) ;
-      end
-
-endmodule
-`endif
diff --git a/src/Verilog/MakeClock.v b/src/Verilog/MakeClock.v
index a60a6e5aa..462ff133c 100644
--- a/src/Verilog/MakeClock.v
+++ b/src/Verilog/MakeClock.v
@@ -36,10 +36,19 @@ module MakeClock ( CLK, RST,
 
    output CLK_VAL_OUT;
    output COND_OUT;
-   output CLK_OUT;
    output CLK_GATE_OUT;
 
+`ifdef VIVADO
+   (* CLOCK_SIGNAL = "YES" *)
+   (* BUFFER_TYPE = "BUFG" *)
+`endif
+   output CLK_OUT;
+
+`ifdef VIVADO
+   (* KEEP = "TRUE" *)
+`endif
    reg current_clk;
+
    reg CLK_VAL_OUT;
    reg current_gate;
    reg new_gate;
diff --git a/src/Verilog/Makefile b/src/Verilog/Makefile
index 8aee769ea..5236c68a5 100644
--- a/src/Verilog/Makefile
+++ b/src/Verilog/Makefile
@@ -3,7 +3,6 @@
 INSTALL_NAME = Verilog
 
 VERI_FILES = \
-	ASSIGN1.v \
 	BRAM1.v \
 	BRAM1Load.v \
 	BRAM1BE.v \
@@ -16,7 +15,6 @@ VERI_FILES = \
 	BypassWire.v \
 	BypassWire0.v \
 	ClockDiv.v \
-	ClockGater.v \
 	ClockGen.v \
 	ClockInverter.v \
 	ClockMux.v \
diff --git a/src/Verilog/RegFile.v b/src/Verilog/RegFile.v
index 72ec88409..990fbdc9e 100644
--- a/src/Verilog/RegFile.v
+++ b/src/Verilog/RegFile.v
@@ -45,6 +45,9 @@ module RegFile(CLK,
    input [addr_width - 1 : 0]  ADDR_5;
    output [data_width - 1 : 0] D_OUT_5;
 
+`ifdef VIVADO
+   (* RAM_STYLE = "DISTRIBUTED" *)
+`endif
    reg [data_width - 1 : 0]    arr[lo:hi];
 
 
diff --git a/src/Verilog/SizedFIFO.v b/src/Verilog/SizedFIFO.v
index 18714ac6a..a41e9f7ca 100644
--- a/src/Verilog/SizedFIFO.v
+++ b/src/Verilog/SizedFIFO.v
@@ -62,6 +62,9 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
 
    // if the depth is too small, don't create an ill-sized array;
    // instead, make a 1-sized array and let the initial block report an error
+`ifdef VIVADO
+   (* RAM_STYLE = "DISTRIBUTED" *)
+`endif
    reg [p1width - 1 : 0]     arr[0: p2depth2];
 
    reg [p1width - 1 : 0]     D_OUT;
diff --git a/src/Verilog/common.mk b/src/Verilog/common.mk
index ef2919023..b39368c45 100644
--- a/src/Verilog/common.mk
+++ b/src/Verilog/common.mk
@@ -54,6 +54,7 @@ test:	$(VERI_FILES)
 	$(IVERILOG) $(call MDARGS, BSV_RESET_FIFO_HEAD BSV_RESET_FIFO_ARRAY) $+
 	$(IVERILOG) $(call MDARGS, BSV_ASYNC_FIFO_RESET BSV_RESET_FIFO_HEAD BSV_RESET_FIFO_ARRAY) $+
 	$(IVERILOG) $(call MDARGS, BSV_POSITIVE_RESET BSV_ASYNC_FIFO_RESET BSV_RESET_FIFO_HEAD BSV_RESET_FIFO_ARRAY) $+
+	$(IVERILOG) $(call MDARGS, VIVADO) $+
 
 .PHONY: testvcs
 testvcs:	$(VERI_FILES)
diff --git a/util/bluetcl-scripts/listVlogFiles.tcl b/util/bluetcl-scripts/listVlogFiles.tcl
index daef17dfb..12f2f0c74 100644
--- a/util/bluetcl-scripts/listVlogFiles.tcl
+++ b/util/bluetcl-scripts/listVlogFiles.tcl
@@ -171,8 +171,6 @@ foreach mod [array names mod_info] {
     # Some primitives use other primitives
     if {$mod_type == "primitive"} {
 	switch -exact $mod {
-	    "DualGrayCntr"  {addfile [lookupfile "ClockGen" $libs {v}] primitives}
-	    "GrayCntr"      {addfile [lookupfile "ClockGen" $libs {v}] primitives}
 	    "MakeReset"     {addfile [lookupfile "SyncReset" $libs {v}] primitives}
 	    "MakeResetA"    {addfile [lookupfile "SyncResetA" $libs {v}] primitives}
 	    "SyncFIFOLevel" {addfile [lookupfile "ClockGen" $libs {v}] primitives