diff --git a/QGL/ControlFlow.py b/QGL/ControlFlow.py
index 9c78ba2b..a735f24e 100644
--- a/QGL/ControlFlow.py
+++ b/QGL/ControlFlow.py
@@ -93,7 +93,7 @@ def qwait(kind="TRIG", addr=None, channels=None):
     elif kind == "CMP":
         return LoadCmp(channels)
     elif kind == "RAM":
-        if not addr:
+        if addr is None:
             raise Exception('Please specify address')
         return [WriteAddrInstruction('INVALIDATE', None, 1, addr, 0xffffffff, False), LoadCmpVramInstruction('LOADCMPVRAM', 1, addr, 0xff, False)]
 
diff --git a/tests/test_ControlFlow.py b/tests/test_ControlFlow.py
index a4af54f4..2eb40b3f 100644
--- a/tests/test_ControlFlow.py
+++ b/tests/test_ControlFlow.py
@@ -84,9 +84,11 @@ def test_repeat(self):
 
     def test_qwait(self):
         q1 = self.q1
-        seq1 = [qwait(), qwait(kind="CMP")]
+        seq1 = [qwait(), qwait(kind="CMP"), qwait(kind = "RAM", addr = 0)]
         assert (isinstance(seq1[0], ControlFlow.Wait))
         assert (isinstance(seq1[1], ControlFlow.LoadCmp))
+        assert (isinstance(seq1[2][0], TdmInstructions.WriteAddrInstruction))
+        assert (isinstance(seq1[2][1], TdmInstructions.LoadCmpVramInstruction))
 
     def test_compile(self):
         q1 = self.q1