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Provide support for the Loongarch CPU architecture #46
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zzSunil
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1. Modify the irq entry code to adapting the generic interrupt management provide by irq pipeline. 2. Interrupt mask virtualization arch-specific code is implemented to provide real and virtual interrupt control for inband and oob stage. 3. Adapting clock chip devices for proxying. BUPT-OS#46 Signed-off-by: Zheng Zhang
zzSunil
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Add IRQ_PIPELINE adn DOVETAIL kconfig option for Loongarch BUPT-OS#46 Signed-off-by: Zheng Zhang
zzSunil
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1. Add more irq-chip device support for loongarch BUPT-OS#46 Signed-off-by: Zheng Zhang
zzSunil
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Add IRQ_PIPELINE adn DOVETAIL kconfig option for Loongarch BUPT-OS#46 Signed-off-by: Zheng Zhang
zzSunil
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1. Add more irq-chip device support for loongarch BUPT-OS#46 Signed-off-by: Zheng Zhang
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1. Add more irq-chip device support for loongarch 2. Resove code review problem BUPT-OS#46 Signed-off-by: Zheng Zhang
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1. Add more irq-chip device support for loongarch 2. Resove code review problem BUPT-OS#46 Signed-off-by: Zheng Zhang fixup
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1. Add more irq-chip device support for loongarch 2. Resove code review problem BUPT-OS#46 Signed-off-by: Zheng Zhang
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1. Modify the irq entry code to adapting the generic interrupt management provide by irq pipeline. 2. Interrupt mask virtualization arch-specific code is implemented to provide real and virtual interrupt control for inband and oob stage. 3. Adapting clock chip devices for proxying. BUPT-OS/RROS#46 Signed-off-by: Zheng Zhang
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Add IRQ_PIPELINE adn DOVETAIL kconfig option for Loongarch BUPT-OS/RROS#46 Signed-off-by: Zheng Zhang
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1. Add more irq-chip device support for loongarch 2. Resove code review problem BUPT-OS/RROS#46 Signed-off-by: Zheng Zhang
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1. Modify the irq entry code to adapting the generic interrupt management provide by irq pipeline. 2. Interrupt mask virtualization arch-specific code is implemented to provide real and virtual interrupt control for inband and oob stage. 3. Adapting clock chip devices for proxying. #46 Signed-off-by: Zheng Zhang
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Add IRQ_PIPELINE adn DOVETAIL kconfig option for Loongarch #46 Signed-off-by: Zheng Zhang
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1. Add more irq-chip device support for loongarch 2. Resove code review problem #46 Signed-off-by: Zheng Zhang
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Dovetail is the current interrupt virtualization layer used by RROS, which only supports three CPU architectures: x86, aarch64, and aarch32. In order to run RROS on a Loongarch architecture CPU, it is necessary to first port the Dovetail architecture-related parts to Loongarch.
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