My solutions to Alteras example labs
Verilog Assembly Coq Other
Switch branches/tags
Nothing to show
Clone or download
Latest commit bc033bf Jan 3, 2014

README.md

This is my set of solutions to Altera's DE2 example labs. These were done as part of a course I took at university during the Fall of 2010. I am publishing this code because I found these labs challenging and had a hard time getting help on them. However, the labs did help me learn Verilog (and Hardware Description Languages in general) and I recommend trying to complete the labs without these solutions first.

I have only included the Verilog source files rather than the entire project directory. I wasn't sure how the project files would migrate between versions of Quartus, but the Verilog files should always be fine. I collected these solutions a few months after completion of the labs, so hopefully I didn't miss any important files. Lab 1 is missing due to a hard drive failure, but the remainder of the digital logic labs are present (lab 10 is in the lab 9 folder as they were very tightly coupled).

The computer organization labs might be a little jumbled up. Around the time I started working on them Altera changed the files they had posted online, so I have done a small amout of work from both sets.

If anyone has any questions or comments (eg a critical file is missing), you can email me at questions@benbergman.ca and I will try to respond in a timely manner. If you found these labs helpful and were able to complete sections that I am missing, please consider submitting a pull request. I regularly get requests for missing sections, so it would be very much appreciated.

Bitdeli Badge