# Changelog

All notable changes to the "FPGA Develop Support" extension will be documented in this file.

The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

## [Unreleased]

## [0.2.6] - 2020-03-30

- TODO: Add change summary

## [0.1.6] - 2020-03-19

- Add support for IP design and bd design
- Add module jump (`Alt + F12` or `F12`)
- Change the startup shortcut key
- Fix some bugs to enhance robustness

## [0.1.4] - 2020-03-10

- Address the BUG existing in 0.1.3

## [0.1.2] - 2020-03-03

- Add Xilinx IP of Soc's cortexM3
- Provide an example for `m3_for_xilinx.bd`
- Resolve the file structure conversion problem

## [0.0.2] - 2020-02-28

- Added testbench / instance function

## [0.0.1] - 2020-02-15

- Initial Release

[Unreleased]: https://github.com/Bestduan/fpga_support_plug/compare/06093a8fb5711b1979ff1695c629f866a00cd5f2...HEAD
[0.2.6]:      https://github.com/Bestduan/fpga_support_plug/compare/ca730fcf38e34a6ede6b41499e0d84939629e7a7...06093a8fb5711b1979ff1695c629f866a00cd5f2
[0.1.6]:      https://github.com/Bestduan/fpga_support_plug/compare/55d3179c8c7d52e2c6730da8d33676e0296e95d9...ca730fcf38e34a6ede6b41499e0d84939629e7a7
[0.1.4]:      https://github.com/Bestduan/fpga_support_plug/compare/d2a752cc39a181b8ed0460bead989f0e623239ef...55d3179c8c7d52e2c6730da8d33676e0296e95d9
[0.1.2]:      https://github.com/Bestduan/fpga_support_plug/compare/3e7755939489bec1c912fc66f79c476b71c4a40e...d2a752cc39a181b8ed0460bead989f0e623239ef
[0.0.2]:      https://github.com/Bestduan/fpga_support_plug/compare/d42c5177a1e2edc871a22e3c00325b99a4061b16...3e7755939489bec1c912fc66f79c476b71c4a40e
[0.0.1]:      https://github.com/Bestduan/fpga_support_plug/compare/b7b7a91dee4a61d1b1d6ab47f3259b10b8138f3e...d42c5177a1e2edc871a22e3c00325b99a4061b16