Skip to content
A single instruction set processor architecture
VHDL
Branch: master
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
README.md
TopCtrl.vhd

README.md

NISC

A single instruction set processor architecture
This is my first time using Github.
Currently only preliminary specifications are given and may be further refined.
Suggestions and requests are welcome.
When I figure out how to do it I would like to list proposals and have a vote on which to implement.
Implementing this might be a good project for a processor design course.
VHDL code to follow when specs are firm.

About NISC

NISC is my particular brand of One Instruction Set Computer (OISC) with Transport Triggered Architecture (TTA).
The operation it performs is Move.
I call it NISC for Null Instruction Set Computer because the set of all opcodes is the null set.
There is no instruction which tells it to Move. It just Moves.
It is not related to No Instruction Set Computing.
I didn't want to call it SISC for Single Instruction Set Computer because SISC sounds like CISC and I like to avoid confusion. I wasn't sure how to pronounce OISC. I also ruled out Mono-Instuction Set Computer (MISC) because I didn't want it filed under Misc.
Although there is no opcode, instructions take two (or three) arguments.
The arguments are source address, destination address, and immediate data.
The source address and destination address are always present but the immediate data is optional.
NISC is an entire family with a scalable architecture.
What will be described is NISC6 because data and addresses are 2 to the 6th power (64 bits). NISC5 has 32 bit data and addresses.

The Controller

  • There is a state machine which controls overall operation.
  • There are 3 registers which are not directly visible to the programmer.
  1. SAR Source Address Register
  2. DAR Destination Address Register
  3. TMP Temporary Register
  • Everything else is memory mapped starting at the beginning of memory. There is a single memory space.
  • The memory is not byte addressable like many processors. Each address holds a 64 bit Word.
  • It is Little Endian where applicable.
  • Peripherals should be memory mapped.

This is the Von Neumann version with unified code and data address space. Using a Harvard architecture with separate code and data spaces would double throughput but would require instruction invalidation for Jumps and Calls. I wanted to keep it simple. Making data and address widths equal allows us to fetch an address in a single cycle. If the data width is less than address width then multiple cycles are needed to fetch an address. With a wider data width, both addresses may be read at once saving a cycle.

The state machine controller normally cycles through 4 states:

  1. Output AP, Fetch Source Address, Increment AP (Argument Pointer, same as a Program Counter)
  2. Output AP, Fetch Destination Address, Increment AP
  3. Read from Source Address into TMP
  4. Write TMP to Destination Address and then it repeats.

Before it gets to state 1 the machine looks for Int and DMA Requests and will go to other states to acknowledge them. Once state 1 starts Int and DMA Requests will not be accepted again until state 4 finishes. Block instructions also alter this cycle by repeating state 3 and/or state 4 a counted number of times.

Address Definitions

Overview

Processor addresses start at the beginning of memory. 128K Words Reserved for processor internals.
Peripherals should be mapped following the processor addresses.
RAM is mapped after the peripherals and before ROM.
ROM is expected at the highest part of memory.

Processor Addresses

AddrWidthNameReadWriteDMA RdDMA WrNOTES
1, 2, 3
000064APAPJumpAPAP4
000164APX(AP++)Call0no effect5
000264RNDRandomRel JumpRNDno effect6
000364CTRCount Rel CallCTRno effect7
000464IARInt Addr RegInt AddrIARIAR8, 9
000564ICRInt Ctrl RegInt Ctrl RegICRICR10
000664DMACRDMA Ctrl RegDMA Ctrl RegDMACRDMACR11
000764BLKCNT BLKCNT RegBLKCNT RegBLKCNTBLKCNT12
000864BLKCTRLBLKCTRL Reg BLKCTRL RegBLKCTRLBLKCTRL13
000964ACCACCACCACCACC14
000A64ACCI(ACC)(ACC)ACCno effect15
000B64ANDCYTMP AND ACC=>ACCCYCY16, 17
000C64ORZFTMP OR ACC=>ACCZFZF16, 18
000D64XORBITCNTTMP XOR ACC=>ACCBITCNTBITCNT16, 19
000E64ADDBCRZTMP + ACC=>ACCBCRZBCRZ20
000F64ADCBCROTMP + ACC + C=>ACCBCROBCRO21
001064SUBBCLZACC - TMP=>ACCBCLZBCLZ22
001164SBBBCLOACC - TMP - C=>ACCBCLOBCLO23
001264CMPall 1sadjust ZF and CYall 1sno effect24
00136SWAPTBDACC modifiedTBDno effect25
001464ILVIHigh ILVIBit interleaveHigh ILVIload only26
001564DLVIHigh DLVIBit deinterleaveHigh DLVIload only27
001664ILVPHigh ILVPPair interleaveHigh ILVPload only28
001764DLVPHigh DLVPPair deinterleaveHigh DLVPload only29
001864ILVNHigh ILVNNibble interleaveHigh ILVNload only30
001964DLVNHigh DLVNNibble deinterleaveHigh DLVNload only31
001A64ILVBHigh ILVBByte interleaveHigh ILVBload only32
001B64DLVBHigh DLVBByte deinterleaveHigh DLVBload only33
001C64ILVQHigh ILVQQuarter interleaveHigh ILVQload only34
001D64DLVQHigh DLVQQuarter deinterleaveHigh DLVQload only35
001E64ILVHHigh ILVHHalf interleaveHigh ILVHload only36
001F64DLVHHigh DLVHHalf deinterleaveHigh DLVHload only37
002064CVCV/NC ValueCV Value CV ValueCV Value38
002164NCCV/NC ValueNC ValueNC ValueNC Value39
002264ZVZV/NZ ValueZV Value ZV ValueZV Value40
002364NZZV/NZ ValueNZ ValueNZ ValueNZ Value41
002464POPO/PE ValuePO Value PO ValuePO Value42
002564PEPO/PE ValuePE ValuePE ValuePE Value43
44
003064WReg0WReg0 WReg0 WReg0WReg045
003164WReg1WReg1 WReg1 WReg1WReg145
003264WReg2WReg2 WReg2 WReg2WReg245
003364WReg3WReg3 WReg3 WReg3WReg345
003464WReg4WReg4 WReg4 WReg4WReg445
003564WReg5WReg5 WReg5 WReg5WReg545
003664WReg6WReg6 WReg6 WReg6WReg645
003764WReg7WReg7 WReg7 WReg7WReg745
003864WReg8WReg8 WReg8 WReg8WReg845
003964WReg9WReg9 WReg9 WReg9WReg945
003A64WRegAWRegA WRegA WRegAWRegA45
003B64WRegBWRegB WRegB WRegBWRegB45
003C64WRegCWRegC WRegC WRegCWRegC45
003D64WRegDWRegD WRegD WRegDWRegD45
003E64WRegEWRegE WRegE WRegEWRegE45
003F64WRegFWRegF WRegF WRegFWRegF45
0040
to
007F
64BRLS 46
008064Cnt1Cnt1Cnt1Cnt1Cnt147
008164Lim1Lim1Lim1Lim1Lim148
008264Und1Und1
or
Ovr1
Und1Und1Und149
008364Ovr1Und1
or
Ovr1
Ovr1Ovr1Ovr150
008464Cnt2Cnt2Cnt2Cnt2Cnt251
008564Lim2Lim2Lim2Lim2Lim252
008664Und2Und2
or
Ovr2
Und2Und2Und253
008764Ovr2Und2
or
Ovr2
Ovr2Ovr2Ovr254
008864Cnt3Cnt3Cnt3Cnt3Cnt351
008964Lim3Lim3Lim3Lim3Lim352
008A64Und3Und3
or
Ovr3
Und3Und3Und353
008B64Ovr3Und3
or
Ovr3
Ovr3Ovr3Ovr354
008C64Cnt4Cnt4Cnt4Cnt4Cnt451
008D64Lim4Lim4Lim4Lim4Lim452
008E64Und4Und4
or
Ovr4
Und4Und4Und453
008F64Ovr4Und4
or
Ovr4
Ovr4Ovr4Ovr454
009064Cnt5Cnt5Cnt5Cnt5Cnt551
009164Lim5Lim5Lim5Lim5Lim552
009264Und5Und5
or
Ovr5
Und5Und5Und553
009364Ovr5Und5
or
Ovr5
Ovr5Ovr5Ovr554
009464Cnt6Cnt6Cnt6Cnt6Cnt651
009564Lim6Lim6Lim6Lim6Lim652
009664Und6Und6
or
Ovr6
Und6Und6Und653
009764Ovr6Und6
or
Ovr6
Ovr6Ovr6Ovr654
009864Cnt7Cnt7Cnt7Cnt7Cnt751
009964Lim7Lim7Lim7Lim7Lim752
009A64Und7Und7
or
Ovr7
Und7Und7Und753
009B64Ovr7Und7
or
Ovr7
Ovr7Ovr7Ovr754
009C64Cnt8Cnt8Cnt8Cnt8Cnt851
009D64Lim8Lim8Lim8Lim8Lim852
009E64Und8Und8
or
Ovr8
Und8Und8Und853
009F64Ovr8Und8
or
Ovr8
Ovr8Ovr8Ovr854
00Ax64RegAxRegAxRegAxRegAxRegAx55, 56
00Bx64RegBx(RegAx)(RegAx)RegAxno effect55, 57
00Cx64RegCx(RegAx--)(++RegAx)RegAxno effect55, 58
00Dx64RegDx(--RegAx)(RegAx++)RegAxno effect55, 59
00Ex64RegEx(RegAx++)(--RegAx)RegAxno effect55, 60
00Fx64RegFx(++RegAx) (RegAx--) RegAxno effect55, 61
010064CHOP CHOPCHOPCHOP CHOP62
010164CHOPI(CHOP)(CHOP)0no effect63
0102
0103
32CHOPLH
CHOPHH
CHOP(31 downto 0)
CHOP(63 downto 32)
CHOP(31 downto 0)
CHOP(63 downto 32)
0no effect64
0104
0105
0106
0107
16CHOPQ0
CHOPQ1
CHOPQ2
CHOPQ3
CHOP(15 downto 0)
CHOP(31 downto 16)
CHOP(47 downto 32)
CHOP(63 downto 48)
CHOP(15 downto 0)
CHOP(31 downto 16)
CHOP(47 downto 32)
CHOP(63 downto 48)
0no effect65
0108
to
010F
8CHOPB0
to
CHOPB7
CHOP(7 downto 0)
to
CHOP(63 downto 56)
CHOP(7 downto 0)
to
CHOP(63 downto 56)
0no effect66
0110
to
011F
4CHOPN0
to
CHOPN15
CHOP(3 downto 0)
to
CHOP(63 downto 60)
CHOP(3 downto 0)
to
CHOP(63 downto 60)
0no effect67
0120
to
013F
2CHOPP0
to
CHOPP31
CHOP(1 downto 0)
to
CHOP(63 downto 62)
CHOP(1 downto 0)
to
CHOP(63 downto 62)
0no effect68
0140
to
017F
1CHOPB0
to
CHOPB63
CHOP(0)
to
CHOP(63)
CHOP(0)
to
CHOP(63)
0no effect69
44
10000
to
1FFFF
64CONST0000
to
FFFF
no effect0000
to
FFFF
no effect70

NOTES:

  1. DMA Read and Write must be different to avoid triggering the TTA effects.
  2. Only the 4 lowest hex digits of address are shown. The high 12 digits are all 0's.
  3. Addresses not shown (skipped) are undefined and should Read as 0. Write should have no effect.
  4. Argument Pointer is the same as a Program Counter. Reset sets all bits.
  5. Reading APX reads from memory pointed to by AP and increments AP. Writing APX pushes AP onto the stack and loads AP (Call).
  • Reading APX is the only instruction which uses the third argument as immediate data.
  1. RND is an LFSR (Read only) which shifts on each clock. Writing adds to AP (Relative Jump).
  2. CTR is an up-counter incremented on every clock. Writing CTR pushes AP onto the stack and adds to AP (Relative Call).
  3. Interrupt Address Register holds the address of the ISR (Interrupt Service Routine) called during Interrupt Acknowledge.
  4. Only one interrupt is implemented in processor. External interrupt controller may expand this.
  5. Interrupt Control Register is a work in progress. Enable/Disable Bit is a minimum.
  6. DMA Control defaults to enabled and can be used for debugging, allowing a single processor cycle then reading all registers.
  7. BLKCNT is a counter with the number of times to repeat an instruction, counts after Write cycle when enabled.
  8. BLKCTRL controls block operation. When loaded, the next instruction is a block instruction.
  • Bit 0 - Setting this bit starts a Block Instruction
  • Bit 1 - 0 = decrement Block Counter, 1 = increment Block Counter
  • Bit 2 - 1 = increment SAR
  • Bit 3 - 1 = decrement SAR, when Bit 2 and Bit 3 are the same SAR is unchanged
  • Bit 4 - 1 = increment DAR
  • Bit 5 - 1 = decrement DAR, when Bit 4 and Bit 5 sre the same DAR is unchanged
  • Bit 6 - 1 = read only once, write using same data. Bits 2 and 3 are ignored. Typically used for block fill.
  1. Accumulator is affected by writes to this and the following 7 addresses.
  2. Accumulator Indirect uses ACC as a pointer to memory.
  3. Write clears Carry Flag. Zero Flag is set if all ACC bits are zero, cleared otherwise.
  4. Write to AND causes data to be ANDed with ACC. Reading returns CY (Carry Flag).
  5. Write to OR causes data to be ORed with ACC. Reading returns ZF (Zero Flag).
  6. Write to XOR causes data to be XORed with ACC. Reading returns BITCNT (Count of set bits in ACC) from 0 to 64.
  7. Write to ADD adds data to ACC. CY and ZF are adjusted appropriately. BCRZ is bit count from right (LSB) to first zero.
  8. Write to ADC adds data and CY to ACC. CY and ZF are adjusted. BCRO is bit count from right to first 1 (0 to 64).
  9. Write to SUB subtracts data from ACC. CY and ZF are adjusted. BCLZ is bit count from left (MSB) to first zero.
  10. Write to SBB subtracts data and CY from ACC. CY and ZF are adjusted. BCLZ is bit count from left to first 1 bit.
  11. CMP is compare. ZF and CY are adjusted as if value was subtracted from ACC. ACC is unchanged.
  12. Swaps parts of ACC. TBD means To Be Determined.
  • Bit 0 swaps Bits within Pairs
  • Bit 1 swaps Pairs within Nibbles
  • Bit 2 swaps Nibbles within Bytes
  • Bit 3 swaps Bytes within Quarter Words
  • Bit 4 swaps Quarter Words within Half Words
  • Bit 5 swaps Half Words within ACC
  1. Individual Bits are interleaved with Bits of ACC. Low order bits are in ACC. High order bits are available here.
  2. Individual Bits are deinterleaved with Bits of ACC. Odd bits in ACC. Even bits are available here.
  3. Bit Pairs are interleaved with Bits of ACC. Low order Pairs are in ACC. High order Pairs are available here.
  4. Bit Pairs are deinterleaved with Bits of ACC. Odd Pairs in ACC. Even Pairs are available here.
  5. Nibbles are interleaved with ACC. Low order Nibbles are in ACC. High order Nibbles are available here.
  6. Nibbles are deinterleaved with ACC. Odd Nibbles in ACC. Even Nibbles are available here.
  7. Bytes are interleaved with ACC. Low order Bytes are in ACC. High order Bytes are available here.
  8. Byte are deinterleaved with ACC. Odd Bytes in ACC. Even Bytes are available here.
  9. Quarter Words are interleaved with ACC. Low order Quarters are in ACC. High order Quarters are available here.
  10. Quarter Words are deinterleaved with ACC. Odd Quarters in ACC. Even Quarters are available here.
  11. Half Words are interleaved with ACC. Low Halves are in ACC. High Halves are available here.
  12. Half Words are deinterleaved with ACC. Odd Halves in ACC. Even Halves are available here.
  13. Write to CV sets the value returned when reading either CV or NC if CY is set when reading.
  14. Write to NC sets the value returned when reading either CV or NC if CY is clear when reading.
  15. Write to ZV sets the value returned when reading either ZV or NZ if ZF is set when reading.
  16. Write to NZ sets the value returned when reading either ZV or NZ if ZF is clear when reading.
  17. Write to PO sets the value returned when reading either PO or PE if BITCNT(0) is set when reading. Parity odd.
  18. Write to PE sets the value returned when reading either PO or PE if BITCNT(0) is clear when reading. Parity even.
  19. Space for more stuff.
  20. Working Registers. These 16 registers do nothing special. They are just like RAM except they never generate wait states.
  21. Barrel Rotate. There is only one register here. All addresses in this range read and write to it rotated relative to their addresses. Write to 30 and read from 31 rotates one bit to the right. Write to 38 and read from 30 rotates 8 bits to the left.
  22. Unsigned counter which counts down when Und1 is read and counts up when Ovr1 is read.
  23. Unsigned Limit register against which Cnt1 is compared.
  24. Unsigned register which returns Und1 if Cnt1 =< Lim1 else returns Ovr1. Reading decrements Cnt1. DMA Rd does not affect Cnt1.
  25. Unsigned register which returns Ovr1 if Cnt1 >= Lim1 else returns Und1. Reading increments Cnt1. DMA Rd does not affect Cnt1.
  26. Unsigned counter similar to Cnt1.
  27. Unsigned Limit register similar to Lim1.
  28. Unsigned register similar to Und1.
  29. Unsigned register similar to Ovr1.
  30. x here means all values from 0 to F.
  31. There are sixteen registers.
  32. These addresses use the Ax registers as memory pointers for read and write.
  33. These addresses use the Ax registers as stack pointers. Postdecremented read, Preincremented write.
  34. These addresses use the Ax registers as stack pointers. Predecremented read, Postincremented write.
  35. These addresses use the Ax registers as stack pointers. Postincremented read, Predecremented write.
  36. These addresses use the Ax registers as stack pointers. Preincremented read, Postdecremented write.
  • 00FF is the system stack used for Call and Relative Call when the AP gets pushed.
  1. There is only one register in the next 0x80 addresses. It gets CHOPped into pieces and put back together.
  2. CHOP may be used as a memory pointer by using this address.
  3. CHOP Low Half and Chop High Half are read and written here. They are in the low bits of a read. The high bits of the read are all zeroes. Only the low bits of a write are used. The high bits of the write are irrelevant and ignored.
  4. CHOP in 4 16-bit quarters. Upper bits are zeroes for read and don't care for write.
  5. CHOP 8 Bytes.
  6. CHOP 16 Nibbles (4 Bits each).
  7. CHOP Pairs of Bits. There are 32 of them.
  8. CHOP Bits, all 64 of them individually addressable.
  9. Small constant ROM. There is not actually a ROM here. With a little bit of hardware we can detect reads in this range and return the low 16 bits of address, eliminating the need to store small constants in the 0000-FFFF range in memory or to use them as immediate data in APX read instruction. With the huge memory space we have, I don't consider this wasteful.
You can’t perform that action at this time.