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base fork: BlackBears/ATtiny861-I2C-ADC-slave
base: 9efd438572
...
head fork: BlackBears/ATtiny861-I2C-ADC-slave
compare: 6bdaba1f1f
  • 2 commits
  • 8 files changed
  • 0 commit comments
  • 1 contributor
Commits on Mar 24, 2013
@BlackBears touched and built project 5157bdc
@BlackBears removed opcode constants
fixed error in reading data byte from I2C
6bdaba1
View
BIN  AM861_I2C_SLAVE_ADC.atsuo
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12 AM861_I2C_SLAVE_ADC/AM861_I2C_SLAVE_ADC.c
@@ -33,11 +33,6 @@
#endif
// OPERATIONAL CODES
-static const uint8_t RADC0 = 0x00;
-static const uint8_t RADC1 = 0x01;
-static const uint8_t RADC2 = 0x02;
-static const uint8_t RADC3 = 0x03;
-static const uint8_t RADC4 = 0x04;
enum { RADC0 = 0, RADC1, RADC2, RADC3, RADC4, RADC5, RADC6, RADC7, RADC8, RADC9, RADCT = 0x3F };
typedef uint8_t adc_code_t;
@@ -48,6 +43,9 @@ uint16_t read_temp(void);
int main(void)
{
+ DDRB |= (1<<PB6);
+
+ PORTB |= (1<<PB6);
unsigned char slaveAddress, temp;
sei();
@@ -63,13 +61,13 @@ int main(void)
for(;;) {
if(usiTwiDataInReceiveBuffer()) {
uint16_t v;
- temp = usiTwiReceiveByte();
adc_code_t code = (adc_code_t)usiTwiReceiveByte();
if( code == RADCT ) {
+ PORTB &= ~(1<<PB6);
v = read_temp();
}
else {
- v = read_temp((uint8_t)code);
+ v = read_adc((uint8_t)code);
}
usiTwiTransmitByte((uint8_t)v);
usiTwiTransmitByte((uint8_t)(v >> 8));
View
BIN  AM861_I2C_SLAVE_ADC/Debug/AM861_I2C_SLAVE_ADC.elf
Binary file not shown
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84 AM861_I2C_SLAVE_ADC/Debug/AM861_I2C_SLAVE_ADC.hex
@@ -1,44 +1,48 @@
-:1000000012C021C020C01FC01EC01DC01CC08BC09C
-:10001000A6C019C018C017C016C015C014C013C0A0
+:1000000012C021C020C01FC01EC01DC01CC0A5C082
+:10001000C0C019C018C017C016C015C014C013C086
:1000200012C011C010C011241FBECFE5D2E0DEBF48
:10003000CDBF10E0A0E6B0E001C01D92A838B10726
-:10004000E1F713D033C1DCCF87B980EC86B900006B
+:10004000E1F725D04DC1DCCF87B980EC86B900003F
:1000500000003699FECF24B135B1932F80E030E017
-:10006000282B392B822F932F08951F93789486EC99
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-:10009000109285001092740010926300109262001A
-:1000A0008093610087B3856087BBC29AC09AB89875
-:1000B00088EA8DB980EF8EB9089520916200909101
-:1000C000630081E0291709F480E00895209162001F
-:1000D0002F5F2F70909163002917E1F3E4E6F0E0C1
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-:1000F000809185009817D1F3809185008F5F8F7074
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+:1002C000EF91BF91AF919F918F917F916F915F91CE
+:1002D0004F913F912F910F900FBE0F901F90189547
+:0402E000F894FFCFC0
:00000001FF
View
635 AM861_I2C_SLAVE_ADC/Debug/AM861_I2C_SLAVE_ADC.lss
@@ -3,31 +3,31 @@ AM861_I2C_SLAVE_ADC.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
- 0 .text 000002b0 00000000 00000000 00000074 2**1
+ 0 .text 000002e4 00000000 00000000 00000074 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 1 .bss 00000028 00800060 00800060 00000324 2**0
+ 1 .bss 00000028 00800060 00800060 00000358 2**0
ALLOC
- 2 .stab 000006cc 00000000 00000000 00000324 2**2
+ 2 .stab 000006cc 00000000 00000000 00000358 2**2
CONTENTS, READONLY, DEBUGGING
- 3 .stabstr 00000097 00000000 00000000 000009f0 2**0
+ 3 .stabstr 00000097 00000000 00000000 00000a24 2**0
CONTENTS, READONLY, DEBUGGING
- 4 .debug_aranges 00000040 00000000 00000000 00000a87 2**0
+ 4 .debug_aranges 00000040 00000000 00000000 00000abb 2**0
CONTENTS, READONLY, DEBUGGING
- 5 .debug_pubnames 00000102 00000000 00000000 00000ac7 2**0
+ 5 .debug_pubnames 00000110 00000000 00000000 00000afb 2**0
CONTENTS, READONLY, DEBUGGING
- 6 .debug_info 000003a7 00000000 00000000 00000bc9 2**0
+ 6 .debug_info 00000444 00000000 00000000 00000c0b 2**0
CONTENTS, READONLY, DEBUGGING
- 7 .debug_abbrev 000001dc 00000000 00000000 00000f70 2**0
+ 7 .debug_abbrev 000001ff 00000000 00000000 0000104f 2**0
CONTENTS, READONLY, DEBUGGING
- 8 .debug_line 000004f7 00000000 00000000 0000114c 2**0
+ 8 .debug_line 00000577 00000000 00000000 0000124e 2**0
CONTENTS, READONLY, DEBUGGING
- 9 .debug_frame 000000b0 00000000 00000000 00001644 2**2
+ 9 .debug_frame 000000c0 00000000 00000000 000017c8 2**2
CONTENTS, READONLY, DEBUGGING
- 10 .debug_str 000002f2 00000000 00000000 000016f4 2**0
+ 10 .debug_str 00000349 00000000 00000000 00001888 2**0
CONTENTS, READONLY, DEBUGGING
- 11 .debug_loc 0000009d 00000000 00000000 000019e6 2**0
+ 11 .debug_loc 000000e9 00000000 00000000 00001bd1 2**0
CONTENTS, READONLY, DEBUGGING
- 12 .debug_pubtypes 0000005d 00000000 00000000 00001a83 2**0
+ 12 .debug_pubtypes 0000006c 00000000 00000000 00001cba 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
@@ -40,8 +40,8 @@ Disassembly of section .text:
8: 1e c0 rjmp .+60 ; 0x46 <__bad_interrupt>
a: 1d c0 rjmp .+58 ; 0x46 <__bad_interrupt>
c: 1c c0 rjmp .+56 ; 0x46 <__bad_interrupt>
- e: 8b c0 rjmp .+278 ; 0x126 <__vector_7>
- 10: a6 c0 rjmp .+332 ; 0x15e <__vector_8>
+ e: a5 c0 rjmp .+330 ; 0x15a <__vector_7>
+ 10: c0 c0 rjmp .+384 ; 0x192 <__vector_8>
12: 19 c0 rjmp .+50 ; 0x46 <__bad_interrupt>
14: 18 c0 rjmp .+48 ; 0x46 <__bad_interrupt>
16: 17 c0 rjmp .+46 ; 0x46 <__bad_interrupt>
@@ -74,18 +74,18 @@ Disassembly of section .text:
3c: a8 38 cpi r26, 0x88 ; 136
3e: b1 07 cpc r27, r17
40: e1 f7 brne .-8 ; 0x3a <.do_clear_bss_loop>
- 42: 13 d0 rcall .+38 ; 0x6a <main>
- 44: 33 c1 rjmp .+614 ; 0x2ac <_exit>
+ 42: 25 d0 rcall .+74 ; 0x8e <main>
+ 44: 4d c1 rjmp .+666 ; 0x2e0 <_exit>
00000046 <__bad_interrupt>:
46: dc cf rjmp .-72 ; 0x0 <__vectors>
00000048 <read_adc>:
+}
+
+// read selected channel with 10-bit precision
uint16_t read_adc(uint8_t chan) {
// if 8-bit precision only is required, then set the ADLAR bit and just read ADCH
- //ADMUX = (chan & ~0b00001111) | (1<<REFS0);
- //ADMUX = (1<<ADLAR) | chan;
- //ADMUX = (1<<ADLAR) | (1<<MUX1);
ADMUX = chan;
48: 87 b9 out 0x07, r24 ; 7
ADCSRA = (1<<ADEN) | (1<<ADSC);
@@ -98,7 +98,6 @@ uint16_t read_adc(uint8_t chan) {
while ( ADCSRA & ( 1 << ADSC ) );
52: 36 99 sbic 0x06, 6 ; 6
54: fe cf rjmp .-4 ; 0x52 <read_adc+0xa>
- //return ADCH;
uint8_t result_l = ADCL;
56: 24 b1 in r18, 0x04 ; 4
uint8_t result_h = ADCH;
@@ -109,538 +108,590 @@ uint16_t read_adc(uint8_t chan) {
5e: 30 e0 ldi r19, 0x00 ; 0
60: 28 2b or r18, r24
62: 39 2b or r19, r25
+}
64: 82 2f mov r24, r18
66: 93 2f mov r25, r19
68: 08 95 ret
-0000006a <main>:
-#endif
+0000006a <read_temp>:
+
+uint16_t read_temp(void) {
+ // MUX5..0 set to 0b111111 to enable special ADC11 channel
+ // set 1.1V internal reference
+ ADMUX = (1<<REFS1) | (1<<MUX4) | (1<<MUX3) | (1<<MUX2) | (1<<MUX1) | (1<<MUX0) ;
+ 6a: 8f e9 ldi r24, 0x9F ; 159
+ 6c: 87 b9 out 0x07, r24 ; 7
+ ADCSRB |= (1<<MUX5);
+ 6e: 1b 9a sbi 0x03, 3 ; 3
+ asm volatile ("NOP" ::);
+ 70: 00 00 nop
+ asm volatile ("NOP" ::);
+ 72: 00 00 nop
+ while ( ADCSRA & ( 1 << ADSC ) );
+ 74: 36 99 sbic 0x06, 6 ; 6
+ 76: fe cf rjmp .-4 ; 0x74 <read_temp+0xa>
+ uint8_t result_l = ADCL;
+ 78: 24 b1 in r18, 0x04 ; 4
+ uint8_t result_h = ADCH;
+ 7a: 35 b1 in r19, 0x05 ; 5
+ ADCSRB &= ~(1<<MUX5);
+ 7c: 1b 98 cbi 0x03, 3 ; 3
+ return (result_h << 8) | result_l;
+ 7e: 93 2f mov r25, r19
+ 80: 80 e0 ldi r24, 0x00 ; 0
+ 82: 30 e0 ldi r19, 0x00 ; 0
+ 84: 28 2b or r18, r24
+ 86: 39 2b or r19, r25
+ 88: 82 2f mov r24, r18
+ 8a: 93 2f mov r25, r19
+ 8c: 08 95 ret
+
+0000008e <main>:
uint16_t read_adc(uint8_t chan);
+uint16_t read_temp(void);
int main(void)
{
- 6a: 1f 93 push r17
+ 8e: 1f 93 push r17
+ DDRB |= (1<<PB6);
+ 90: be 9a sbi 0x17, 6 ; 23
+
+ PORTB |= (1<<PB6);
+ 92: c6 9a sbi 0x18, 6 ; 24
unsigned char slaveAddress, temp;
sei();
- 6c: 78 94 sei
+ 94: 78 94 sei
// enable the ADC circuitry, free-running mode, interrupt with /2 prescaler
ADCSRA = (1<<ADEN) | (1<<ADSC) | (1<<ADPS2) | (1<<ADPS1);
- 6e: 86 ec ldi r24, 0xC6 ; 198
- 70: 86 b9 out 0x06, r24 ; 6
+ 96: 86 ec ldi r24, 0xC6 ; 198
+ 98: 86 b9 out 0x06, r24 ; 6
// wait for complete conversion
while ( ADCSRA & ( 1 << ADSC ) );
- 72: 36 99 sbic 0x06, 6 ; 6
- 74: fe cf rjmp .-4 ; 0x72 <main+0x8>
+ 9a: 36 99 sbic 0x06, 6 ; 6
+ 9c: fe cf rjmp .-4 ; 0x9a <main+0xc>
slaveAddress = 0x26; // This can be change to your own address
usiTwiSlaveInit(slaveAddress);
- 76: 86 e2 ldi r24, 0x26 ; 38
- 78: 0b d0 rcall .+22 ; 0x90 <usiTwiSlaveInit>
+ 9e: 86 e2 ldi r24, 0x26 ; 38
+ a0: 11 d0 rcall .+34 ; 0xc4 <usiTwiSlaveInit>
for(;;) {
if(usiTwiDataInReceiveBuffer()) {
- 7a: 4c d0 rcall .+152 ; 0x114 <usiTwiDataInReceiveBuffer>
- 7c: 88 23 and r24, r24
- 7e: 31 f0 breq .+12 ; 0x8c <main+0x22>
- temp = usiTwiReceiveByte();
- 80: 35 d0 rcall .+106 ; 0xec <usiTwiReceiveByte>
- uint16_t v = read_adc(temp);
- 82: e2 df rcall .-60 ; 0x48 <read_adc>
- 84: 19 2f mov r17, r25
+ a2: 52 d0 rcall .+164 ; 0x148 <usiTwiDataInReceiveBuffer>
+ a4: 88 23 and r24, r24
+ a6: 61 f0 breq .+24 ; 0xc0 <main+0x32>
+ uint16_t v;
+ adc_code_t code = (adc_code_t)usiTwiReceiveByte();
+ a8: 3b d0 rcall .+118 ; 0x120 <usiTwiReceiveByte>
+ if( code == RADCT ) {
+ aa: 8f 33 cpi r24, 0x3F ; 63
+ ac: 21 f4 brne .+8 ; 0xb6 <main+0x28>
+ PORTB &= ~(1<<PB6);
+ ae: c6 98 cbi 0x18, 6 ; 24
+ v = read_temp();
+ b0: dc df rcall .-72 ; 0x6a <read_temp>
+ b2: 19 2f mov r17, r25
+ b4: 02 c0 rjmp .+4 ; 0xba <main+0x2c>
+ }
+ else {
+ v = read_adc((uint8_t)code);
+ b6: c8 df rcall .-112 ; 0x48 <read_adc>
+ b8: 19 2f mov r17, r25
+ }
usiTwiTransmitByte((uint8_t)v);
- 86: 22 d0 rcall .+68 ; 0xcc <usiTwiTransmitByte>
+ ba: 22 d0 rcall .+68 ; 0x100 <usiTwiTransmitByte>
usiTwiTransmitByte((uint8_t)(v >> 8));
- 88: 81 2f mov r24, r17
- 8a: 20 d0 rcall .+64 ; 0xcc <usiTwiTransmitByte>
+ bc: 81 2f mov r24, r17
+ be: 20 d0 rcall .+64 ; 0x100 <usiTwiTransmitByte>
}
asm volatile ("NOP" ::);
- 8c: 00 00 nop
+ c0: 00 00 nop
}
- 8e: f5 cf rjmp .-22 ; 0x7a <main+0x10>
+ c2: ef cf rjmp .-34 ; 0xa2 <main+0x14>
-00000090 <usiTwiSlaveInit>:
+000000c4 <usiTwiSlaveInit>:
void
flushTwiBuffers(
void
)
{
rxTail = 0;
- 90: 10 92 85 00 sts 0x0085, r1
+ c4: 10 92 85 00 sts 0x0085, r1
rxHead = 0;
- 94: 10 92 74 00 sts 0x0074, r1
+ c8: 10 92 74 00 sts 0x0074, r1
txTail = 0;
- 98: 10 92 63 00 sts 0x0063, r1
+ cc: 10 92 63 00 sts 0x0063, r1
txHead = 0;
- 9c: 10 92 62 00 sts 0x0062, r1
+ d0: 10 92 62 00 sts 0x0062, r1
)
{
flushTwiBuffers( );
slaveAddress = ownAddress;
- a0: 80 93 61 00 sts 0x0061, r24
+ d4: 80 93 61 00 sts 0x0061, r24
// low when a start condition is detected or a counter overflow (only
// for USIWM1, USIWM0 = 11). This inserts a wait state. SCL is released
// by the ISRs (USI_START_vect and USI_OVERFLOW_vect).
// Set SCL and SDA as output
DDR_USI |= ( 1 << PORT_USI_SCL ) | ( 1 << PORT_USI_SDA );
- a4: 87 b3 in r24, 0x17 ; 23
- a6: 85 60 ori r24, 0x05 ; 5
- a8: 87 bb out 0x17, r24 ; 23
+ d8: 87 b3 in r24, 0x17 ; 23
+ da: 85 60 ori r24, 0x05 ; 5
+ dc: 87 bb out 0x17, r24 ; 23
// set SCL high
PORT_USI |= ( 1 << PORT_USI_SCL );
- aa: c2 9a sbi 0x18, 2 ; 24
+ de: c2 9a sbi 0x18, 2 ; 24
// set SDA high
PORT_USI |= ( 1 << PORT_USI_SDA );
- ac: c0 9a sbi 0x18, 0 ; 24
+ e0: c0 9a sbi 0x18, 0 ; 24
// Set SDA as input
DDR_USI &= ~( 1 << PORT_USI_SDA );
- ae: b8 98 cbi 0x17, 0 ; 23
+ e2: b8 98 cbi 0x17, 0 ; 23
USICR =
- b0: 88 ea ldi r24, 0xA8 ; 168
- b2: 8d b9 out 0x0d, r24 ; 13
+ e4: 88 ea ldi r24, 0xA8 ; 168
+ e6: 8d b9 out 0x0d, r24 ; 13
// no toggle clock-port pin
( 0 << USITC );
// clear all interrupt flags and reset overflow counter
USISR = ( 1 << USI_START_COND_INT ) | ( 1 << USIOIF ) | ( 1 << USIPF ) | ( 1 << USIDC );
- b4: 80 ef ldi r24, 0xF0 ; 240
- b6: 8e b9 out 0x0e, r24 ; 14
+ e8: 80 ef ldi r24, 0xF0 ; 240
+ ea: 8e b9 out 0x0e, r24 ; 14
} // end usiTwiSlaveInit
- b8: 08 95 ret
+ ec: 08 95 ret
-000000ba <usiTwiDataInTransmitBuffer>:
+000000ee <usiTwiDataInTransmitBuffer>:
bool usiTwiDataInTransmitBuffer(void)
{
// return 0 (false) if the receive buffer is empty
return txHead != txTail;
- ba: 20 91 62 00 lds r18, 0x0062
- be: 90 91 63 00 lds r25, 0x0063
- c2: 81 e0 ldi r24, 0x01 ; 1
- c4: 29 17 cp r18, r25
- c6: 09 f4 brne .+2 ; 0xca <usiTwiDataInTransmitBuffer+0x10>
- c8: 80 e0 ldi r24, 0x00 ; 0
+ ee: 20 91 62 00 lds r18, 0x0062
+ f2: 90 91 63 00 lds r25, 0x0063
+ f6: 81 e0 ldi r24, 0x01 ; 1
+ f8: 29 17 cp r18, r25
+ fa: 09 f4 brne .+2 ; 0xfe <usiTwiDataInTransmitBuffer+0x10>
+ fc: 80 e0 ldi r24, 0x00 ; 0
} // end usiTwiDataInTransmitBuffer
- ca: 08 95 ret
+ fe: 08 95 ret
-000000cc <usiTwiTransmitByte>:
+00000100 <usiTwiTransmitByte>:
{
uint8_t tmphead;
// calculate buffer index
tmphead = ( txHead + 1 ) & TWI_TX_BUFFER_MASK;
- cc: 20 91 62 00 lds r18, 0x0062
- d0: 2f 5f subi r18, 0xFF ; 255
- d2: 2f 70 andi r18, 0x0F ; 15
+ 100: 20 91 62 00 lds r18, 0x0062
+ 104: 2f 5f subi r18, 0xFF ; 255
+ 106: 2f 70 andi r18, 0x0F ; 15
// wait for free space in buffer
while ( tmphead == txTail );
- d4: 90 91 63 00 lds r25, 0x0063
- d8: 29 17 cp r18, r25
- da: e1 f3 breq .-8 ; 0xd4 <usiTwiTransmitByte+0x8>
+ 108: 90 91 63 00 lds r25, 0x0063
+ 10c: 29 17 cp r18, r25
+ 10e: e1 f3 breq .-8 ; 0x108 <usiTwiTransmitByte+0x8>
// store data in buffer
txBuf[ tmphead ] = data;
- dc: e4 e6 ldi r30, 0x64 ; 100
- de: f0 e0 ldi r31, 0x00 ; 0
- e0: e2 0f add r30, r18
- e2: f1 1d adc r31, r1
- e4: 80 83 st Z, r24
+ 110: e4 e6 ldi r30, 0x64 ; 100
+ 112: f0 e0 ldi r31, 0x00 ; 0
+ 114: e2 0f add r30, r18
+ 116: f1 1d adc r31, r1
+ 118: 80 83 st Z, r24
// store new index
txHead = tmphead;
- e6: 20 93 62 00 sts 0x0062, r18
+ 11a: 20 93 62 00 sts 0x0062, r18
} // end usiTwiTransmitByte
- ea: 08 95 ret
+ 11e: 08 95 ret
-000000ec <usiTwiReceiveByte>:
+00000120 <usiTwiReceiveByte>:
void
)
{
// wait for Rx data
while ( rxHead == rxTail );
- ec: 90 91 74 00 lds r25, 0x0074
- f0: 80 91 85 00 lds r24, 0x0085
- f4: 98 17 cp r25, r24
- f6: d1 f3 breq .-12 ; 0xec <usiTwiReceiveByte>
+ 120: 90 91 74 00 lds r25, 0x0074
+ 124: 80 91 85 00 lds r24, 0x0085
+ 128: 98 17 cp r25, r24
+ 12a: d1 f3 breq .-12 ; 0x120 <usiTwiReceiveByte>
// calculate buffer index
rxTail = ( rxTail + 1 ) & TWI_RX_BUFFER_MASK;
- f8: 80 91 85 00 lds r24, 0x0085
- fc: 8f 5f subi r24, 0xFF ; 255
- fe: 8f 70 andi r24, 0x0F ; 15
- 100: 80 93 85 00 sts 0x0085, r24
+ 12c: 80 91 85 00 lds r24, 0x0085
+ 130: 8f 5f subi r24, 0xFF ; 255
+ 132: 8f 70 andi r24, 0x0F ; 15
+ 134: 80 93 85 00 sts 0x0085, r24
// return data from the buffer.
return rxBuf[ rxTail ];
- 104: 80 91 85 00 lds r24, 0x0085
- 108: e5 e7 ldi r30, 0x75 ; 117
- 10a: f0 e0 ldi r31, 0x00 ; 0
- 10c: e8 0f add r30, r24
- 10e: f1 1d adc r31, r1
+ 138: 80 91 85 00 lds r24, 0x0085
+ 13c: e5 e7 ldi r30, 0x75 ; 117
+ 13e: f0 e0 ldi r31, 0x00 ; 0
+ 140: e8 0f add r30, r24
+ 142: f1 1d adc r31, r1
} // end usiTwiReceiveByte
- 110: 80 81 ld r24, Z
- 112: 08 95 ret
+ 144: 80 81 ld r24, Z
+ 146: 08 95 ret
-00000114 <usiTwiDataInReceiveBuffer>:
+00000148 <usiTwiDataInReceiveBuffer>:
void
)
{
// return 0 (false) if the receive buffer is empty
return rxHead != rxTail;
- 114: 20 91 74 00 lds r18, 0x0074
- 118: 90 91 85 00 lds r25, 0x0085
- 11c: 81 e0 ldi r24, 0x01 ; 1
- 11e: 29 17 cp r18, r25
- 120: 09 f4 brne .+2 ; 0x124 <usiTwiDataInReceiveBuffer+0x10>
- 122: 80 e0 ldi r24, 0x00 ; 0
+ 148: 20 91 74 00 lds r18, 0x0074
+ 14c: 90 91 85 00 lds r25, 0x0085
+ 150: 81 e0 ldi r24, 0x01 ; 1
+ 152: 29 17 cp r18, r25
+ 154: 09 f4 brne .+2 ; 0x158 <usiTwiDataInReceiveBuffer+0x10>
+ 156: 80 e0 ldi r24, 0x00 ; 0
} // end usiTwiDataInReceiveBuffer
- 124: 08 95 ret
+ 158: 08 95 ret
-00000126 <__vector_7>:
+0000015a <__vector_7>:
USI Start Condition ISR
********************************************************************************/
ISR( USI_START_VECTOR )
{
- 126: 1f 92 push r1
- 128: 0f 92 push r0
- 12a: 0f b6 in r0, 0x3f ; 63
- 12c: 0f 92 push r0
- 12e: 11 24 eor r1, r1
- 130: 8f 93 push r24
+ 15a: 1f 92 push r1
+ 15c: 0f 92 push r0
+ 15e: 0f b6 in r0, 0x3f ; 63
+ 160: 0f 92 push r0
+ 162: 11 24 eor r1, r1
+ 164: 8f 93 push r24
// set default starting conditions for new TWI package
overflowState = USI_SLAVE_CHECK_ADDRESS;
- 132: 10 92 60 00 sts 0x0060, r1
+ 166: 10 92 60 00 sts 0x0060, r1
// set SDA as input
DDR_USI &= ~( 1 << PORT_USI_SDA );
- 136: b8 98 cbi 0x17, 0 ; 23
+ 16a: b8 98 cbi 0x17, 0 ; 23
// wait for SCL to go low to ensure the Start Condition has completed (the
// start detector will hold SCL low ) - if a Stop Condition arises then leave
// the interrupt to prevent waiting forever - don't use USISR to test for Stop
// Condition as in Application Note AVR312 because the Stop Condition Flag is
// going to be set from the last TWI sequence
while (
- 138: b2 9b sbis 0x16, 2 ; 22
- 13a: 02 c0 rjmp .+4 ; 0x140 <__vector_7+0x1a>
+ 16c: b2 9b sbis 0x16, 2 ; 22
+ 16e: 02 c0 rjmp .+4 ; 0x174 <__vector_7+0x1a>
// SCL his high
( PIN_USI & ( 1 << PIN_USI_SCL ) ) &&
- 13c: b0 9b sbis 0x16, 0 ; 22
- 13e: fc cf rjmp .-8 ; 0x138 <__vector_7+0x12>
+ 170: b0 9b sbis 0x16, 0 ; 22
+ 172: fc cf rjmp .-8 ; 0x16c <__vector_7+0x12>
// and SDA is low
!( ( PIN_USI & ( 1 << PIN_USI_SDA ) ) )
);
if ( !( PIN_USI & ( 1 << PIN_USI_SDA ) ) )
- 140: b0 99 sbic 0x16, 0 ; 22
- 142: 03 c0 rjmp .+6 ; 0x14a <__vector_7+0x24>
+ 174: b0 99 sbic 0x16, 0 ; 22
+ 176: 03 c0 rjmp .+6 ; 0x17e <__vector_7+0x24>
{
// a Stop Condition did not occur
USICR =
- 144: 88 ef ldi r24, 0xF8 ; 248
- 146: 8d b9 out 0x0d, r24 ; 13
- 148: 02 c0 rjmp .+4 ; 0x14e <__vector_7+0x28>
+ 178: 88 ef ldi r24, 0xF8 ; 248
+ 17a: 8d b9 out 0x0d, r24 ; 13
+ 17c: 02 c0 rjmp .+4 ; 0x182 <__vector_7+0x28>
}
else
{
// a Stop Condition did occur
USICR =
- 14a: 88 ea ldi r24, 0xA8 ; 168
- 14c: 8d b9 out 0x0d, r24 ; 13
+ 17e: 88 ea ldi r24, 0xA8 ; 168
+ 180: 8d b9 out 0x0d, r24 ; 13
// no toggle clock-port pin
( 0 << USITC );
} // end if
USISR =
- 14e: 80 ef ldi r24, 0xF0 ; 240
- 150: 8e b9 out 0x0e, r24 ; 14
+ 182: 80 ef ldi r24, 0xF0 ; 240
+ 184: 8e b9 out 0x0e, r24 ; 14
( 1 << USI_START_COND_INT ) | ( 1 << USIOIF ) |
( 1 << USIPF ) |( 1 << USIDC ) |
// set USI to sample 8 bits (count 16 external SCL pin toggles)
( 0x0 << USICNT0);
} // end ISR( USI_START_VECTOR )
- 152: 8f 91 pop r24
- 154: 0f 90 pop r0
- 156: 0f be out 0x3f, r0 ; 63
- 158: 0f 90 pop r0
- 15a: 1f 90 pop r1
- 15c: 18 95 reti
-
-0000015e <__vector_8>:
+ 186: 8f 91 pop r24
+ 188: 0f 90 pop r0
+ 18a: 0f be out 0x3f, r0 ; 63
+ 18c: 0f 90 pop r0
+ 18e: 1f 90 pop r1
+ 190: 18 95 reti
+
+00000192 <__vector_8>:
Only disabled when waiting for a new Start Condition.
********************************************************************************/
ISR( USI_OVERFLOW_VECTOR )
{
- 15e: 1f 92 push r1
- 160: 0f 92 push r0
- 162: 0f b6 in r0, 0x3f ; 63
- 164: 0f 92 push r0
- 166: 11 24 eor r1, r1
- 168: 2f 93 push r18
- 16a: 3f 93 push r19
- 16c: 4f 93 push r20
- 16e: 5f 93 push r21
- 170: 6f 93 push r22
- 172: 7f 93 push r23
- 174: 8f 93 push r24
- 176: 9f 93 push r25
- 178: af 93 push r26
- 17a: bf 93 push r27
- 17c: ef 93 push r30
- 17e: ff 93 push r31
+ 192: 1f 92 push r1
+ 194: 0f 92 push r0
+ 196: 0f b6 in r0, 0x3f ; 63
+ 198: 0f 92 push r0
+ 19a: 11 24 eor r1, r1
+ 19c: 2f 93 push r18
+ 19e: 3f 93 push r19
+ 1a0: 4f 93 push r20
+ 1a2: 5f 93 push r21
+ 1a4: 6f 93 push r22
+ 1a6: 7f 93 push r23
+ 1a8: 8f 93 push r24
+ 1aa: 9f 93 push r25
+ 1ac: af 93 push r26
+ 1ae: bf 93 push r27
+ 1b0: ef 93 push r30
+ 1b2: ff 93 push r31
switch ( overflowState )
- 180: 80 91 60 00 lds r24, 0x0060
- 184: 82 30 cpi r24, 0x02 ; 2
- 186: 09 f4 brne .+2 ; 0x18a <__vector_8+0x2c>
- 188: 5c c0 rjmp .+184 ; 0x242 <__vector_8+0xe4>
- 18a: 83 30 cpi r24, 0x03 ; 3
- 18c: 30 f4 brcc .+12 ; 0x19a <__vector_8+0x3c>
- 18e: 88 23 and r24, r24
- 190: 69 f0 breq .+26 ; 0x1ac <__vector_8+0x4e>
- 192: 81 30 cpi r24, 0x01 ; 1
- 194: 09 f0 breq .+2 ; 0x198 <__vector_8+0x3a>
- 196: 79 c0 rjmp .+242 ; 0x28a <__stack+0x2b>
- 198: 34 c0 rjmp .+104 ; 0x202 <__vector_8+0xa4>
- 19a: 84 30 cpi r24, 0x04 ; 4
- 19c: 09 f4 brne .+2 ; 0x1a0 <__vector_8+0x42>
- 19e: 59 c0 rjmp .+178 ; 0x252 <__vector_8+0xf4>
- 1a0: 84 30 cpi r24, 0x04 ; 4
- 1a2: 38 f1 brcs .+78 ; 0x1f2 <__vector_8+0x94>
- 1a4: 85 30 cpi r24, 0x05 ; 5
- 1a6: 09 f0 breq .+2 ; 0x1aa <__vector_8+0x4c>
- 1a8: 70 c0 rjmp .+224 ; 0x28a <__stack+0x2b>
- 1aa: 5a c0 rjmp .+180 ; 0x260 <__stack+0x1>
+ 1b4: 80 91 60 00 lds r24, 0x0060
+ 1b8: 82 30 cpi r24, 0x02 ; 2
+ 1ba: 09 f4 brne .+2 ; 0x1be <__vector_8+0x2c>
+ 1bc: 5c c0 rjmp .+184 ; 0x276 <__stack+0x17>
+ 1be: 83 30 cpi r24, 0x03 ; 3
+ 1c0: 30 f4 brcc .+12 ; 0x1ce <__vector_8+0x3c>
+ 1c2: 88 23 and r24, r24
+ 1c4: 69 f0 breq .+26 ; 0x1e0 <__vector_8+0x4e>
+ 1c6: 81 30 cpi r24, 0x01 ; 1
+ 1c8: 09 f0 breq .+2 ; 0x1cc <__vector_8+0x3a>
+ 1ca: 79 c0 rjmp .+242 ; 0x2be <__stack+0x5f>
+ 1cc: 34 c0 rjmp .+104 ; 0x236 <__vector_8+0xa4>
+ 1ce: 84 30 cpi r24, 0x04 ; 4
+ 1d0: 09 f4 brne .+2 ; 0x1d4 <__vector_8+0x42>
+ 1d2: 59 c0 rjmp .+178 ; 0x286 <__stack+0x27>
+ 1d4: 84 30 cpi r24, 0x04 ; 4
+ 1d6: 38 f1 brcs .+78 ; 0x226 <__vector_8+0x94>
+ 1d8: 85 30 cpi r24, 0x05 ; 5
+ 1da: 09 f0 breq .+2 ; 0x1de <__vector_8+0x4c>
+ 1dc: 70 c0 rjmp .+224 ; 0x2be <__stack+0x5f>
+ 1de: 5a c0 rjmp .+180 ; 0x294 <__stack+0x35>
{
// Address mode: check address and send ACK (and next USI_SLAVE_SEND_DATA) if OK,
// else reset USI
case USI_SLAVE_CHECK_ADDRESS:
if ( ( USIDR == 0 ) || ( ( USIDR >> 1 ) == slaveAddress) )
- 1ac: 8f b1 in r24, 0x0f ; 15
- 1ae: 88 23 and r24, r24
- 1b0: 31 f0 breq .+12 ; 0x1be <__vector_8+0x60>
- 1b2: 9f b1 in r25, 0x0f ; 15
- 1b4: 96 95 lsr r25
- 1b6: 80 91 61 00 lds r24, 0x0061
- 1ba: 98 17 cp r25, r24
- 1bc: a9 f4 brne .+42 ; 0x1e8 <__vector_8+0x8a>
+ 1e0: 8f b1 in r24, 0x0f ; 15
+ 1e2: 88 23 and r24, r24
+ 1e4: 31 f0 breq .+12 ; 0x1f2 <__vector_8+0x60>
+ 1e6: 9f b1 in r25, 0x0f ; 15
+ 1e8: 96 95 lsr r25
+ 1ea: 80 91 61 00 lds r24, 0x0061
+ 1ee: 98 17 cp r25, r24
+ 1f0: a9 f4 brne .+42 ; 0x21c <__vector_8+0x8a>
{
// callback
if(_onTwiDataRequest) _onTwiDataRequest();
- 1be: e0 91 86 00 lds r30, 0x0086
- 1c2: f0 91 87 00 lds r31, 0x0087
- 1c6: 30 97 sbiw r30, 0x00 ; 0
- 1c8: 09 f0 breq .+2 ; 0x1cc <__vector_8+0x6e>
- 1ca: 09 95 icall
+ 1f2: e0 91 86 00 lds r30, 0x0086
+ 1f6: f0 91 87 00 lds r31, 0x0087
+ 1fa: 30 97 sbiw r30, 0x00 ; 0
+ 1fc: 09 f0 breq .+2 ; 0x200 <__vector_8+0x6e>
+ 1fe: 09 95 icall
if ( USIDR & 0x01 )
- 1cc: 78 9b sbis 0x0f, 0 ; 15
- 1ce: 04 c0 rjmp .+8 ; 0x1d8 <__vector_8+0x7a>
+ 200: 78 9b sbis 0x0f, 0 ; 15
+ 202: 04 c0 rjmp .+8 ; 0x20c <__vector_8+0x7a>
{
overflowState = USI_SLAVE_SEND_DATA;
- 1d0: 81 e0 ldi r24, 0x01 ; 1
- 1d2: 80 93 60 00 sts 0x0060, r24
- 1d6: 03 c0 rjmp .+6 ; 0x1de <__vector_8+0x80>
+ 204: 81 e0 ldi r24, 0x01 ; 1
+ 206: 80 93 60 00 sts 0x0060, r24
+ 20a: 03 c0 rjmp .+6 ; 0x212 <__vector_8+0x80>
}
else
{
overflowState = USI_SLAVE_REQUEST_DATA;
- 1d8: 84 e0 ldi r24, 0x04 ; 4
- 1da: 80 93 60 00 sts 0x0060, r24
+ 20c: 84 e0 ldi r24, 0x04 ; 4
+ 20e: 80 93 60 00 sts 0x0060, r24
} // end if
SET_USI_TO_SEND_ACK( );
- 1de: 1f b8 out 0x0f, r1 ; 15
- 1e0: b8 9a sbi 0x17, 0 ; 23
- 1e2: 8e e7 ldi r24, 0x7E ; 126
- 1e4: 8e b9 out 0x0e, r24 ; 14
- 1e6: 51 c0 rjmp .+162 ; 0x28a <__stack+0x2b>
+ 212: 1f b8 out 0x0f, r1 ; 15
+ 214: b8 9a sbi 0x17, 0 ; 23
+ 216: 8e e7 ldi r24, 0x7E ; 126
+ 218: 8e b9 out 0x0e, r24 ; 14
+ 21a: 51 c0 rjmp .+162 ; 0x2be <__stack+0x5f>
}
else
{
SET_USI_TO_TWI_START_CONDITION_MODE( );
- 1e8: 88 ea ldi r24, 0xA8 ; 168
- 1ea: 8d b9 out 0x0d, r24 ; 13
- 1ec: 80 e7 ldi r24, 0x70 ; 112
- 1ee: 8e b9 out 0x0e, r24 ; 14
- 1f0: 4c c0 rjmp .+152 ; 0x28a <__stack+0x2b>
+ 21c: 88 ea ldi r24, 0xA8 ; 168
+ 21e: 8d b9 out 0x0d, r24 ; 13
+ 220: 80 e7 ldi r24, 0x70 ; 112
+ 222: 8e b9 out 0x0e, r24 ; 14
+ 224: 4c c0 rjmp .+152 ; 0x2be <__stack+0x5f>
break;
// Master write data mode: check reply and goto USI_SLAVE_SEND_DATA if OK,
// else reset USI
case USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA:
if ( USIDR )
- 1f2: 8f b1 in r24, 0x0f ; 15
- 1f4: 88 23 and r24, r24
- 1f6: 29 f0 breq .+10 ; 0x202 <__vector_8+0xa4>
+ 226: 8f b1 in r24, 0x0f ; 15
+ 228: 88 23 and r24, r24
+ 22a: 29 f0 breq .+10 ; 0x236 <__vector_8+0xa4>
{
// if NACK, the master does not want more data
SET_USI_TO_TWI_START_CONDITION_MODE( );
- 1f8: 88 ea ldi r24, 0xA8 ; 168
- 1fa: 8d b9 out 0x0d, r24 ; 13
- 1fc: 80 e7 ldi r24, 0x70 ; 112
- 1fe: 8e b9 out 0x0e, r24 ; 14
+ 22c: 88 ea ldi r24, 0xA8 ; 168
+ 22e: 8d b9 out 0x0d, r24 ; 13
+ 230: 80 e7 ldi r24, 0x70 ; 112
+ 232: 8e b9 out 0x0e, r24 ; 14
return;
- 200: 44 c0 rjmp .+136 ; 0x28a <__stack+0x2b>
+ 234: 44 c0 rjmp .+136 ; 0x2be <__stack+0x5f>
// copy data from buffer to USIDR and set USI to shift byte
// next USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA
case USI_SLAVE_SEND_DATA:
// Get data from Buffer
if ( txHead != txTail )
- 202: 90 91 62 00 lds r25, 0x0062
- 206: 80 91 63 00 lds r24, 0x0063
- 20a: 98 17 cp r25, r24
- 20c: a9 f0 breq .+42 ; 0x238 <__vector_8+0xda>
+ 236: 90 91 62 00 lds r25, 0x0062
+ 23a: 80 91 63 00 lds r24, 0x0063
+ 23e: 98 17 cp r25, r24
+ 240: a9 f0 breq .+42 ; 0x26c <__stack+0xd>
{
txTail = ( txTail + 1 ) & TWI_TX_BUFFER_MASK;
- 20e: 80 91 63 00 lds r24, 0x0063
- 212: 8f 5f subi r24, 0xFF ; 255
- 214: 8f 70 andi r24, 0x0F ; 15
- 216: 80 93 63 00 sts 0x0063, r24
+ 242: 80 91 63 00 lds r24, 0x0063
+ 246: 8f 5f subi r24, 0xFF ; 255
+ 248: 8f 70 andi r24, 0x0F ; 15
+ 24a: 80 93 63 00 sts 0x0063, r24
USIDR = txBuf[ txTail ];
- 21a: 80 91 63 00 lds r24, 0x0063
- 21e: e4 e6 ldi r30, 0x64 ; 100
- 220: f0 e0 ldi r31, 0x00 ; 0
- 222: e8 0f add r30, r24
- 224: f1 1d adc r31, r1
- 226: 80 81 ld r24, Z
- 228: 8f b9 out 0x0f, r24 ; 15
+ 24e: 80 91 63 00 lds r24, 0x0063
+ 252: e4 e6 ldi r30, 0x64 ; 100
+ 254: f0 e0 ldi r31, 0x00 ; 0
+ 256: e8 0f add r30, r24
+ 258: f1 1d adc r31, r1
+ 25a: 80 81 ld r24, Z
+ 25c: 8f b9 out 0x0f, r24 ; 15
{
// the buffer is empty
SET_USI_TO_TWI_START_CONDITION_MODE( );
return;
} // end if
overflowState = USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA;
- 22a: 82 e0 ldi r24, 0x02 ; 2
- 22c: 80 93 60 00 sts 0x0060, r24
+ 25e: 82 e0 ldi r24, 0x02 ; 2
+ 260: 80 93 60 00 sts 0x0060, r24
SET_USI_TO_SEND_DATA( );
- 230: b8 9a sbi 0x17, 0 ; 23
- 232: 80 e7 ldi r24, 0x70 ; 112
- 234: 8e b9 out 0x0e, r24 ; 14
+ 264: b8 9a sbi 0x17, 0 ; 23
+ 266: 80 e7 ldi r24, 0x70 ; 112
+ 268: 8e b9 out 0x0e, r24 ; 14
break;
- 236: 29 c0 rjmp .+82 ; 0x28a <__stack+0x2b>
+ 26a: 29 c0 rjmp .+82 ; 0x2be <__stack+0x5f>
USIDR = txBuf[ txTail ];
}
else
{
// the buffer is empty
SET_USI_TO_TWI_START_CONDITION_MODE( );
- 238: 88 ea ldi r24, 0xA8 ; 168
- 23a: 8d b9 out 0x0d, r24 ; 13
- 23c: 80 e7 ldi r24, 0x70 ; 112
- 23e: 8e b9 out 0x0e, r24 ; 14
+ 26c: 88 ea ldi r24, 0xA8 ; 168
+ 26e: 8d b9 out 0x0d, r24 ; 13
+ 270: 80 e7 ldi r24, 0x70 ; 112
+ 272: 8e b9 out 0x0e, r24 ; 14
return;
- 240: 24 c0 rjmp .+72 ; 0x28a <__stack+0x2b>
+ 274: 24 c0 rjmp .+72 ; 0x2be <__stack+0x5f>
break;
// set USI to sample reply from master
// next USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA
case USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA:
overflowState = USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA;
- 242: 83 e0 ldi r24, 0x03 ; 3
- 244: 80 93 60 00 sts 0x0060, r24
+ 276: 83 e0 ldi r24, 0x03 ; 3
+ 278: 80 93 60 00 sts 0x0060, r24
SET_USI_TO_READ_ACK( );
- 248: b8 98 cbi 0x17, 0 ; 23
- 24a: 1f b8 out 0x0f, r1 ; 15
- 24c: 8e e7 ldi r24, 0x7E ; 126
- 24e: 8e b9 out 0x0e, r24 ; 14
+ 27c: b8 98 cbi 0x17, 0 ; 23
+ 27e: 1f b8 out 0x0f, r1 ; 15
+ 280: 8e e7 ldi r24, 0x7E ; 126
+ 282: 8e b9 out 0x0e, r24 ; 14
break;
- 250: 1c c0 rjmp .+56 ; 0x28a <__stack+0x2b>
+ 284: 1c c0 rjmp .+56 ; 0x2be <__stack+0x5f>
// Master read data mode: set USI to sample data from master, next
// USI_SLAVE_GET_DATA_AND_SEND_ACK
case USI_SLAVE_REQUEST_DATA:
overflowState = USI_SLAVE_GET_DATA_AND_SEND_ACK;
- 252: 85 e0 ldi r24, 0x05 ; 5
- 254: 80 93 60 00 sts 0x0060, r24
+ 286: 85 e0 ldi r24, 0x05 ; 5
+ 288: 80 93 60 00 sts 0x0060, r24
SET_USI_TO_READ_DATA( );
- 258: b8 98 cbi 0x17, 0 ; 23
- 25a: 80 e7 ldi r24, 0x70 ; 112
- 25c: 8e b9 out 0x0e, r24 ; 14
+ 28c: b8 98 cbi 0x17, 0 ; 23
+ 28e: 80 e7 ldi r24, 0x70 ; 112
+ 290: 8e b9 out 0x0e, r24 ; 14
break;
- 25e: 15 c0 rjmp .+42 ; 0x28a <__stack+0x2b>
+ 292: 15 c0 rjmp .+42 ; 0x2be <__stack+0x5f>
// copy data from USIDR and send ACK
// next USI_SLAVE_REQUEST_DATA
case USI_SLAVE_GET_DATA_AND_SEND_ACK:
// put data into buffer
// Not necessary, but prevents warnings
rxHead = ( rxHead + 1 ) & TWI_RX_BUFFER_MASK;
- 260: 80 91 74 00 lds r24, 0x0074
- 264: 8f 5f subi r24, 0xFF ; 255
- 266: 8f 70 andi r24, 0x0F ; 15
- 268: 80 93 74 00 sts 0x0074, r24
+ 294: 80 91 74 00 lds r24, 0x0074
+ 298: 8f 5f subi r24, 0xFF ; 255
+ 29a: 8f 70 andi r24, 0x0F ; 15
+ 29c: 80 93 74 00 sts 0x0074, r24
rxBuf[ rxHead ] = USIDR;
- 26c: 90 91 74 00 lds r25, 0x0074
- 270: 8f b1 in r24, 0x0f ; 15
- 272: e5 e7 ldi r30, 0x75 ; 117
- 274: f0 e0 ldi r31, 0x00 ; 0
- 276: e9 0f add r30, r25
- 278: f1 1d adc r31, r1
- 27a: 80 83 st Z, r24
+ 2a0: 90 91 74 00 lds r25, 0x0074
+ 2a4: 8f b1 in r24, 0x0f ; 15
+ 2a6: e5 e7 ldi r30, 0x75 ; 117
+ 2a8: f0 e0 ldi r31, 0x00 ; 0
+ 2aa: e9 0f add r30, r25
+ 2ac: f1 1d adc r31, r1
+ 2ae: 80 83 st Z, r24
// next USI_SLAVE_REQUEST_DATA
overflowState = USI_SLAVE_REQUEST_DATA;
- 27c: 84 e0 ldi r24, 0x04 ; 4
- 27e: 80 93 60 00 sts 0x0060, r24
+ 2b0: 84 e0 ldi r24, 0x04 ; 4
+ 2b2: 80 93 60 00 sts 0x0060, r24
SET_USI_TO_SEND_ACK( );
- 282: 1f b8 out 0x0f, r1 ; 15
- 284: b8 9a sbi 0x17, 0 ; 23
- 286: 8e e7 ldi r24, 0x7E ; 126
- 288: 8e b9 out 0x0e, r24 ; 14
+ 2b6: 1f b8 out 0x0f, r1 ; 15
+ 2b8: b8 9a sbi 0x17, 0 ; 23
+ 2ba: 8e e7 ldi r24, 0x7E ; 126
+ 2bc: 8e b9 out 0x0e, r24 ; 14
break;
} // end switch
} // end ISR( USI_OVERFLOW_VECTOR )
- 28a: ff 91 pop r31
- 28c: ef 91 pop r30
- 28e: bf 91 pop r27
- 290: af 91 pop r26
- 292: 9f 91 pop r25
- 294: 8f 91 pop r24
- 296: 7f 91 pop r23
- 298: 6f 91 pop r22
- 29a: 5f 91 pop r21
- 29c: 4f 91 pop r20
- 29e: 3f 91 pop r19
- 2a0: 2f 91 pop r18
- 2a2: 0f 90 pop r0
- 2a4: 0f be out 0x3f, r0 ; 63
- 2a6: 0f 90 pop r0
- 2a8: 1f 90 pop r1
- 2aa: 18 95 reti
-
-000002ac <_exit>:
- 2ac: f8 94 cli
-
-000002ae <__stop_program>:
- 2ae: ff cf rjmp .-2 ; 0x2ae <__stop_program>
+ 2be: ff 91 pop r31
+ 2c0: ef 91 pop r30
+ 2c2: bf 91 pop r27
+ 2c4: af 91 pop r26
+ 2c6: 9f 91 pop r25
+ 2c8: 8f 91 pop r24
+ 2ca: 7f 91 pop r23
+ 2cc: 6f 91 pop r22
+ 2ce: 5f 91 pop r21
+ 2d0: 4f 91 pop r20
+ 2d2: 3f 91 pop r19
+ 2d4: 2f 91 pop r18
+ 2d6: 0f 90 pop r0
+ 2d8: 0f be out 0x3f, r0 ; 63
+ 2da: 0f 90 pop r0
+ 2dc: 1f 90 pop r1
+ 2de: 18 95 reti
+
+000002e0 <_exit>:
+ 2e0: f8 94 cli
+
+000002e2 <__stop_program>:
+ 2e2: ff cf rjmp .-2 ; 0x2e2 <__stop_program>
View
101 AM861_I2C_SLAVE_ADC/Debug/AM861_I2C_SLAVE_ADC.map
@@ -123,7 +123,7 @@ LOAD c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/av
.rela.plt
*(.rela.plt)
-.text 0x00000000 0x2b0
+.text 0x00000000 0x2e4
*(.vectors)
.vectors 0x00000000 0x26 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/../../../../avr/lib/avr25/crttn861.o
0x00000000 __vector_default
@@ -194,28 +194,29 @@ LOAD c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/av
0x00000046 __vector_10
0x00000046 __vector_16
0x00000046 __vector_18
- .text 0x00000048 0x48 AM861_I2C_SLAVE_ADC.o
+ .text 0x00000048 0x7c AM861_I2C_SLAVE_ADC.o
0x00000048 read_adc
- 0x0000006a main
- .text 0x00000090 0x21c usiTwiSlave.o
- 0x00000090 usiTwiSlaveInit
- 0x000000ba usiTwiDataInTransmitBuffer
- 0x000000cc usiTwiTransmitByte
- 0x000000ec usiTwiReceiveByte
- 0x00000114 usiTwiDataInReceiveBuffer
- 0x00000126 __vector_7
- 0x0000015e __vector_8
- .text 0x000002ac 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_exit.o)
- .text 0x000002ac 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_clear_bss.o)
- 0x000002ac . = ALIGN (0x2)
+ 0x0000006a read_temp
+ 0x0000008e main
+ .text 0x000000c4 0x21c usiTwiSlave.o
+ 0x000000c4 usiTwiSlaveInit
+ 0x000000ee usiTwiDataInTransmitBuffer
+ 0x00000100 usiTwiTransmitByte
+ 0x00000120 usiTwiReceiveByte
+ 0x00000148 usiTwiDataInReceiveBuffer
+ 0x0000015a __vector_7
+ 0x00000192 __vector_8
+ .text 0x000002e0 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_exit.o)
+ .text 0x000002e0 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_clear_bss.o)
+ 0x000002e0 . = ALIGN (0x2)
*(.text.*)
- .text.libgcc 0x000002ac 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_exit.o)
- .text.libgcc 0x000002ac 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_clear_bss.o)
- 0x000002ac . = ALIGN (0x2)
+ .text.libgcc 0x000002e0 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_exit.o)
+ .text.libgcc 0x000002e0 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_clear_bss.o)
+ 0x000002e0 . = ALIGN (0x2)
*(.fini9)
- .fini9 0x000002ac 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_exit.o)
- 0x000002ac _exit
- 0x000002ac exit
+ .fini9 0x000002e0 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_exit.o)
+ 0x000002e0 _exit
+ 0x000002e0 exit
*(.fini9)
*(.fini8)
*(.fini8)
@@ -234,11 +235,11 @@ LOAD c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/av
*(.fini1)
*(.fini1)
*(.fini0)
- .fini0 0x000002ac 0x4 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_exit.o)
+ .fini0 0x000002e0 0x4 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/avr25\libgcc.a(_exit.o)
*(.fini0)
- 0x000002b0 _etext = .
+ 0x000002e4 _etext = .
-.data 0x00800060 0x0 load address 0x000002b0
+.data 0x00800060 0x0 load address 0x000002e4
0x00800060 PROVIDE (__data_start, .)
*(.data)
.data 0x00800060 0x0 c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/avrtoolchain/bin/../lib/gcc/avr/4.5.1/../../../../avr/lib/avr25/crttn861.o
@@ -267,8 +268,8 @@ LOAD c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/av
COMMON 0x00800086 0x2 AM861_I2C_SLAVE_ADC.o
0x00800086 _onTwiDataRequest
0x00800088 PROVIDE (__bss_end, .)
- 0x000002b0 __data_load_start = LOADADDR (.data)
- 0x000002b0 __data_load_end = (__data_load_start + SIZEOF (.data))
+ 0x000002e4 __data_load_start = LOADADDR (.data)
+ 0x000002e4 __data_load_end = (__data_load_start + SIZEOF (.data))
.noinit 0x00800088 0x0
0x00800088 PROVIDE (__noinit_start, .)
@@ -336,45 +337,45 @@ LOAD c:/program files/atmel/atmel studio 6.0/extensions/atmel/avrgcc/3.3.2.31/av
0x00000020 0x20 usiTwiSlave.o
.debug_pubnames
- 0x00000000 0x102
+ 0x00000000 0x110
*(.debug_pubnames)
.debug_pubnames
- 0x00000000 0x3e AM861_I2C_SLAVE_ADC.o
+ 0x00000000 0x4c AM861_I2C_SLAVE_ADC.o
.debug_pubnames
- 0x0000003e 0xc4 usiTwiSlave.o
+ 0x0000004c 0xc4 usiTwiSlave.o
-.debug_info 0x00000000 0x3a7
+.debug_info 0x00000000 0x444
*(.debug_info)
- .debug_info 0x00000000 0x137 AM861_I2C_SLAVE_ADC.o
- .debug_info 0x00000137 0x270 usiTwiSlave.o
+ .debug_info 0x00000000 0x1d4 AM861_I2C_SLAVE_ADC.o
+ .debug_info 0x000001d4 0x270 usiTwiSlave.o
*(.gnu.linkonce.wi.*)
-.debug_abbrev 0x00000000 0x1dc
+.debug_abbrev 0x00000000 0x1ff
*(.debug_abbrev)
- .debug_abbrev 0x00000000 0xb6 AM861_I2C_SLAVE_ADC.o
- .debug_abbrev 0x000000b6 0x126 usiTwiSlave.o
+ .debug_abbrev 0x00000000 0xd9 AM861_I2C_SLAVE_ADC.o
+ .debug_abbrev 0x000000d9 0x126 usiTwiSlave.o
-.debug_line 0x00000000 0x4f7
+.debug_line 0x00000000 0x577
*(.debug_line)
- .debug_line 0x00000000 0x1b2 AM861_I2C_SLAVE_ADC.o
- .debug_line 0x000001b2 0x345 usiTwiSlave.o
+ .debug_line 0x00000000 0x232 AM861_I2C_SLAVE_ADC.o
+ .debug_line 0x00000232 0x345 usiTwiSlave.o
-.debug_frame 0x00000000 0xb0
+.debug_frame 0x00000000 0xc0
*(.debug_frame)
- .debug_frame 0x00000000 0x30 AM861_I2C_SLAVE_ADC.o
- .debug_frame 0x00000030 0x80 usiTwiSlave.o
+ .debug_frame 0x00000000 0x40 AM861_I2C_SLAVE_ADC.o
+ .debug_frame 0x00000040 0x80 usiTwiSlave.o
-.debug_str 0x00000000 0x2f2
+.debug_str 0x00000000 0x349
*(.debug_str)
- .debug_str 0x00000000 0x13c AM861_I2C_SLAVE_ADC.o
- 0x170 (size before relaxing)
- .debug_str 0x0000013c 0x1b6 usiTwiSlave.o
+ .debug_str 0x00000000 0x193 AM861_I2C_SLAVE_ADC.o
+ 0x1cc (size before relaxing)
+ .debug_str 0x00000193 0x1b6 usiTwiSlave.o
0x2cc (size before relaxing)
-.debug_loc 0x00000000 0x9d
+.debug_loc 0x00000000 0xe9
*(.debug_loc)
- .debug_loc 0x00000000 0x7b AM861_I2C_SLAVE_ADC.o
- .debug_loc 0x0000007b 0x22 usiTwiSlave.o
+ .debug_loc 0x00000000 0xc7 AM861_I2C_SLAVE_ADC.o
+ .debug_loc 0x000000c7 0x22 usiTwiSlave.o
.debug_macinfo
*(.debug_macinfo)
@@ -382,8 +383,8 @@ OUTPUT(AM861_I2C_SLAVE_ADC.elf elf32-avr)
LOAD linker stubs
.debug_pubtypes
- 0x00000000 0x5d
+ 0x00000000 0x6c
.debug_pubtypes
- 0x00000000 0x2b AM861_I2C_SLAVE_ADC.o
+ 0x00000000 0x3a AM861_I2C_SLAVE_ADC.o
.debug_pubtypes
- 0x0000002b 0x32 usiTwiSlave.o
+ 0x0000003a 0x32 usiTwiSlave.o
View
BIN  AM861_I2C_SLAVE_ADC/Debug/AM861_I2C_SLAVE_ADC.o
Binary file not shown
View
2  AM861_I2C_SLAVE_ADC/Debug/make3936-1.bat
@@ -0,0 +1,2 @@
+@echo off
+echo Invoking: AVR/GNU C Compiler

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