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fixed syntax error in forwarding unit and created empty tb
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Christer committed Nov 11, 2012
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148 changes: 74 additions & 74 deletions oving1/forwarding_unit.vhd
View file
@@ -1,74 +1,74 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:18:02 11/11/2012
-- Design Name:
-- Module Name: forwarding_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity forwarding_unit is
Port ( exmem_reg_write : in STD_LOGIC;
memwb_reg_write : in STD_LOGIC;
exmem_reg_rd : in STD_LOGIC_VECTOR (4 downto 0);
memwb_reg_rd : in STD_LOGIC_VECTOR (4 downto 0);
idex_reg_rs : in STD_LOGIC_VECTOR (4 downto 0);
idex_reg_rt : in STD_LOGIC_VECTOR (4 downto 0);
forward_a : out STD_LOGIC_VECTOR (1 downto 0);
forward_b : out STD_LOGIC_VECTOR (1 downto 0));
end forwarding_unit;

architecture Behavioral of forwarding_unit is

begin

process
begin
-- 1a
if (exmem_reg_write and (exmem_reg_rd /= "00000") and (exmem_reg_rd = idex_register_rs)) then
forward_a <= "10";
-- 2a
elsif (memwb_reg_write and (memwb_reg_rd /= "00000") and (exmem_reg_rd /= idex_register_rs) and (memwb_reg_rd = idex_reg_rs)) then
forward_a <= "01";
-- default
else
forward_a <= "00";
end if;

-- 1b
if (exmem_reg_write and (exmem_reg_rd /= "00000") and (exmem_reg_rd = idex_register_rt)) then
forward_b <= "10";
-- 2b
elsif (memwb_reg_write and (memwb_reg_rd /= "00000") and (memwb_reg_rd /= idex_register_rt) and (memwb_reg_rd = idex_reg_rt)) then
forward_b <= "01";
-- default
else
forward_b <= "00";
end if;

end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:18:02 11/11/2012
-- Design Name:
-- Module Name: forwarding_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity forwarding_unit is
Port ( exmem_reg_write : in STD_LOGIC;
memwb_reg_write : in STD_LOGIC;
exmem_reg_rd : in STD_LOGIC_VECTOR (4 downto 0);
memwb_reg_rd : in STD_LOGIC_VECTOR (4 downto 0);
idex_reg_rs : in STD_LOGIC_VECTOR (4 downto 0);
idex_reg_rt : in STD_LOGIC_VECTOR (4 downto 0);
forward_a : out STD_LOGIC_VECTOR (1 downto 0);
forward_b : out STD_LOGIC_VECTOR (1 downto 0));
end forwarding_unit;

architecture Behavioral of forwarding_unit is

begin

process
begin
-- 1a
if (exmem_reg_write and (exmem_reg_rd /= "00000") and (exmem_reg_rd = idex_reg_rs)) then
forward_a <= "10";
-- 2a
elsif (memwb_reg_write and (memwb_reg_rd /= "00000") and (exmem_reg_rd /= idex_reg_rs) and (memwb_reg_rd = idex_reg_rs)) then
forward_a <= "01";
-- default
else
forward_a <= "00";
end if;

-- 1b
if (exmem_reg_write and (exmem_reg_rd /= "00000") and (exmem_reg_rd = idex_reg_rt)) then
forward_b <= "10";
-- 2b
elsif (memwb_reg_write and (memwb_reg_rd /= "00000") and (memwb_reg_rd /= idex_reg_rt) and (memwb_reg_rd = idex_reg_rt)) then
forward_b <= "01";
-- default
else
forward_b <= "00";
end if;

end process;

end Behavioral;

6 changes: 3 additions & 3 deletions oving1/iseconfig/toplevel.xreport
View file
@@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-11-11T15:51:51</DateModified>
<DateModified>2012-11-11T16:05:45</DateModified>
<ModuleName>toplevel</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>//sambaad.stud.ntnu.no/terjesc/git/GitHub/tdt4255/oving1/iseconfig/toplevel.xreport</SavedFilePath>
<ImplementationReportsDirectory>Z:/git/GitHub/tdt4255/oving1\</ImplementationReportsDirectory>
<SavedFilePath>C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/iseconfig/toplevel.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\</ImplementationReportsDirectory>
<DateInitialized>2012-09-28T22:24:59</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
Expand Down
133 changes: 103 additions & 30 deletions oving1/oving1.gise
View file
@@ -1,30 +1,103 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

<!-- -->

<!-- For tool use only. Do not edit. -->

<!-- -->

<!-- ProjectNavigator created generated project file. -->

<!-- For use in tracking generated file and other information -->

<!-- allowing preservation of process status. -->

<!-- -->

<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->

<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="oving1.xise"/>

<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_NCD" xil_pn:name="toplevel_guide.ncd" xil_pn:origination="imported"/>
</files>

<transforms xmlns="http://www.xilinx.com/XMLSchema"/>

</generated_project>
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

<!-- -->

<!-- For tool use only. Do not edit. -->

<!-- -->

<!-- ProjectNavigator created generated project file. -->

<!-- For use in tracking generated file and other information -->

<!-- allowing preservation of process status. -->

<!-- -->

<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->

<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="oving1.xise"/>

<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="tb_toplevel.fdo"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="toplevel_guide.ncd" xil_pn:origination="imported"/>
</files>

<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1352646716" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1352646716">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352647073" xil_pn:in_ck="7061694717294192413" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1352647073">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="control_unit.vhd"/>
<outfile xil_pn:name="forwarding_unit.vhd"/>
<outfile xil_pn:name="pc.vhd"/>
<outfile xil_pn:name="reg_32.vhd"/>
<outfile xil_pn:name="reg_exmem.vhd"/>
<outfile xil_pn:name="reg_idex.vhd"/>
<outfile xil_pn:name="reg_ifid.vhd"/>
<outfile xil_pn:name="reg_memwb.vhd"/>
<outfile xil_pn:name="tb_adder.vhd"/>
<outfile xil_pn:name="tb_alu.vhd"/>
<outfile xil_pn:name="tb_alu_control.vhd"/>
<outfile xil_pn:name="tb_control_unit.vhd"/>
<outfile xil_pn:name="tb_forwarding_unit.vhd"/>
<outfile xil_pn:name="tb_pc.vhd"/>
<outfile xil_pn:name="tb_reg_exmem.vhd"/>
<outfile xil_pn:name="tb_reg_idex.vhd"/>
<outfile xil_pn:name="tb_reg_ifid.vhd"/>
<outfile xil_pn:name="tb_reg_memwb.vhd"/>
<outfile xil_pn:name="tb_sign_extend.vhd"/>
<outfile xil_pn:name="tb_toplevel.vhd"/>
</transform>
<transform xil_pn:end_ts="1352646716" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3623050530995557290" xil_pn:start_ts="1352646716">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352646716" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3144195386269199572" xil_pn:start_ts="1352646716">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352646716" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8177611997605138438" xil_pn:start_ts="1352646716">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352647074" xil_pn:in_ck="7061694717294192413" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1352647073">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="control_unit.vhd"/>
<outfile xil_pn:name="forwarding_unit.vhd"/>
<outfile xil_pn:name="pc.vhd"/>
<outfile xil_pn:name="reg_32.vhd"/>
<outfile xil_pn:name="reg_exmem.vhd"/>
<outfile xil_pn:name="reg_idex.vhd"/>
<outfile xil_pn:name="reg_ifid.vhd"/>
<outfile xil_pn:name="reg_memwb.vhd"/>
<outfile xil_pn:name="tb_adder.vhd"/>
<outfile xil_pn:name="tb_alu.vhd"/>
<outfile xil_pn:name="tb_alu_control.vhd"/>
<outfile xil_pn:name="tb_control_unit.vhd"/>
<outfile xil_pn:name="tb_forwarding_unit.vhd"/>
<outfile xil_pn:name="tb_pc.vhd"/>
<outfile xil_pn:name="tb_reg_exmem.vhd"/>
<outfile xil_pn:name="tb_reg_idex.vhd"/>
<outfile xil_pn:name="tb_reg_ifid.vhd"/>
<outfile xil_pn:name="tb_reg_memwb.vhd"/>
<outfile xil_pn:name="tb_sign_extend.vhd"/>
<outfile xil_pn:name="tb_toplevel.vhd"/>
</transform>
<transform xil_pn:end_ts="1352647077" xil_pn:in_ck="7061694717294192413" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1352647074">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="tb_toplevel.fdo"/>
</transform>
</transforms>

</generated_project>
10 changes: 8 additions & 2 deletions oving1/oving1.xise
View file
Expand Up @@ -150,6 +150,12 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="tb_forwarding_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
</files>

<autoManagedFiles>
Expand Down Expand Up @@ -392,8 +398,8 @@
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_reg_exmem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_reg_exmem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_toplevel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_toplevel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
Expand Down
2 changes: 1 addition & 1 deletion oving1/pepExtractor.prj
View file
@@ -1 +1 @@
work "reg_memwb.vhd"
work "forwarding_unit.vhd"

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