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made another pipeline reg and fixed some syntax

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commit fe7cdde74d5887f223be9b1daa80687699f34e5f 1 parent 805c049
@chribru chribru authored
View
2  oving1/_xmsgs/pn_parser.xmsgs
@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;Z:/git/GitHub/tdt4255/oving1/idex.vhd&quot; into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/reg_idex.vhd&quot; into library work</arg>
</msg>
</messages>
View
21 oving1/_xmsgs/xst.xmsgs
@@ -5,5 +5,26 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
+<msg type="error" file="HDLCompiler" num="845" delta="new" >"\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 72: Type of aggregate cannot be determined without context ; <arg fmt="%d" index="1">0</arg> visible types match here
+</msg>
+
+<msg type="error" file="HDLCompiler" num="845" delta="new" >"\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 73: Type of aggregate cannot be determined without context ; <arg fmt="%d" index="1">0</arg> visible types match here
+</msg>
+
+<msg type="error" file="HDLCompiler" num="845" delta="new" >"\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 74: Type of aggregate cannot be determined without context ; <arg fmt="%d" index="1">0</arg> visible types match here
+</msg>
+
+<msg type="error" file="HDLCompiler" num="845" delta="new" >"\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 75: Type of aggregate cannot be determined without context ; <arg fmt="%d" index="1">0</arg> visible types match here
+</msg>
+
+<msg type="error" file="HDLCompiler" num="845" delta="new" >"\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 76: Type of aggregate cannot be determined without context ; <arg fmt="%d" index="1">0</arg> visible types match here
+</msg>
+
+<msg type="error" file="HDLCompiler" num="845" delta="new" >"\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 78: Type of aggregate cannot be determined without context ; <arg fmt="%d" index="1">0</arg> visible types match here
+</msg>
+
+<msg type="error" file="HDLCompiler" num="854" delta="new" >"\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 64: Unit &lt;<arg fmt="%s" index="1">behavioral</arg>&gt; ignored due to previous errors.
+</msg>
+
</messages>
View
39 oving1/iseconfig/oving1.projectmgr
@@ -17,13 +17,13 @@
<ClosedNode>/toplevel - Behavioral Z:|github|tdt4255|oving1|toplevel.vhd/MIPS_SC_PROCESSOR - processor - Behavioral/inst_pc_handle - pc_handle - Behavioral</ClosedNode>
</ClosedNodes>
<SelectedItems>
- <SelectedItem>MIPS_SC_PROCESSOR - processor - Behavioral (Z:/github/tdt4255/oving1/processor.vhd)</SelectedItem>
+ <SelectedItem>reg_idex - Behavioral (C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/reg_idex.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000e7000000020000000000000000000000000000000064ffffffff000000810000000000000002000000e70000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
- <CurrentItem>MIPS_SC_PROCESSOR - processor - Behavioral (Z:/github/tdt4255/oving1/processor.vhd)</CurrentItem>
+ <CurrentItem>reg_idex - Behavioral (C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/reg_idex.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
@@ -43,13 +43,13 @@
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
- <SelectedItem>Z:\github\tdt4255\oving1\processor.vhd</SelectedItem>
+ <SelectedItem>reg_idex.vhd</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000040101000100000000000000000000000064ffffffff000000810000000000000004000000e50000000100000000000000240000000100000000000000660000000100000000000002320000000100000000</ViewHeaderState>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001d3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000e50000000100000000000000240000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem>Z:\github\tdt4255\oving1\processor.vhd</CurrentItem>
+ <CurrentItem>reg_idex.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
@@ -58,12 +58,12 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000f9000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f90000000100000000</ViewHeaderState>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
- <CurrentView>Behavioral Simulation</CurrentView>
+ <CurrentView>Implementation</CurrentView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
@@ -74,34 +74,41 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
- <SelectedItem></SelectedItem>
+ <SelectedItem>Check Syntax</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000139000000010000000100000000000000000000000064ffffffff000000810000000000000001000001390000000100000000</ViewHeaderState>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a0000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a00000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem></CurrentItem>
+ <CurrentItem>Check Syntax</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/adder - Behavioral Z:|github|tdt4255|oving1|adder.vhd</ClosedNode>
<ClosedNode>/alu - Behavioral Z:|github|tdt4255|oving1|alu.vhd</ClosedNode>
+ <ClosedNode>/tb_adder - behavior C:|Users|chribru|Desktop|GitHub|tdt4255|oving1|tb_adder.vhd</ClosedNode>
+ <ClosedNode>/tb_alu - behavior C:|Users|chribru|Desktop|GitHub|tdt4255|oving1|tb_alu.vhd</ClosedNode>
+ <ClosedNode>/tb_alu_control - behavior C:|Users|chribru|Desktop|GitHub|tdt4255|oving1|tb_alu_control.vhd</ClosedNode>
<ClosedNode>/tb_alu_control - behavior Z:|github|tdt4255|oving1|tb_alu_control.vhd</ClosedNode>
+ <ClosedNode>/tb_control_unit - behavior C:|Users|chribru|Desktop|GitHub|tdt4255|oving1|tb_control_unit.vhd</ClosedNode>
<ClosedNode>/tb_control_unit - behavior Z:|github|tdt4255|oving1|tb_control_unit.vhd</ClosedNode>
+ <ClosedNode>/tb_pc - behavior C:|Users|chribru|Desktop|GitHub|tdt4255|oving1|tb_pc.vhd</ClosedNode>
<ClosedNode>/tb_pc_handle - behavior C:|Users|chribru|Desktop|GitHub|tdt4255|oving1|tb_pc_handle.vhd</ClosedNode>
<ClosedNode>/tb_pc_handle - behavior Z:|github|tdt4255|oving1|tb_pc_handle.vhd</ClosedNode>
+ <ClosedNode>/tb_shift_two - behavior C:|Users|chribru|Desktop|GitHub|tdt4255|oving1|tb_shift_two.vhd</ClosedNode>
+ <ClosedNode>/tb_sign_extend - behavior C:|Users|chribru|Desktop|GitHub|tdt4255|oving1|tb_sign_extend.vhd</ClosedNode>
<ClosedNode>/tb_sign_extend - behavior Z:|github|tdt4255|oving1|tb_sign_extend.vhd</ClosedNode>
<ClosedNode>/tb_toplevel - behavior Z:|github|tdt4255|oving1|tb_toplevel.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
- <SelectedItem>tb_toplevel - behavior (Z:/github/tdt4255/oving1/tb_toplevel.vhd)</SelectedItem>
+ <SelectedItem>reg_ifid - Behavioral (C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/reg_ifid.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e2000000020000000000000000000000000000000064ffffffff000000810000000000000002000001e20000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
- <CurrentItem>tb_toplevel - behavior (Z:/github/tdt4255/oving1/tb_toplevel.vhd)</CurrentItem>
+ <CurrentItem>reg_ifid - Behavioral (C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/reg_ifid.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
@@ -109,13 +116,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
- <SelectedItem/>
+ <SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000139000000010000000100000000000000000000000064ffffffff000000810000000000000001000001390000000100000000</ViewHeaderState>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a0000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a00000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem/>
+ <CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
@@ -126,7 +133,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000139000000010000000100000000000000000000000064ffffffff000000810000000000000001000001390000000100000000</ViewHeaderState>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a0000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a00000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
View
6 oving1/iseconfig/toplevel.xreport
@@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
- <DateModified>2012-10-13T20:11:51</DateModified>
+ <DateModified>2012-10-13T22:23:07</DateModified>
<ModuleName>toplevel</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
- <SavedFilePath>//sambaad.stud.ntnu.no/terjesc/git/GitHub/tdt4255/oving1/iseconfig/toplevel.xreport</SavedFilePath>
- <ImplementationReportsDirectory>Z:/git/GitHub/tdt4255/oving1\</ImplementationReportsDirectory>
+ <SavedFilePath>C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/iseconfig/toplevel.xreport</SavedFilePath>
+ <ImplementationReportsDirectory>C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\</ImplementationReportsDirectory>
<DateInitialized>2012-09-28T22:24:59</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
View
9 oving1/oving1.gise
@@ -45,6 +45,15 @@
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="reg_32.prj"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="reg_32.stx"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="reg_32.xst"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="reg_exmem.prj"/>
+ <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="reg_exmem.stx"/>
+ <file xil_pn:fileType="FILE_XST" xil_pn:name="reg_exmem.xst"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="reg_idex.prj"/>
+ <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="reg_idex.stx"/>
+ <file xil_pn:fileType="FILE_XST" xil_pn:name="reg_idex.xst"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="reg_ifid.prj"/>
+ <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="reg_ifid.stx"/>
+ <file xil_pn:fileType="FILE_XST" xil_pn:name="reg_ifid.xst"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="tb_alu.fdo"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="tb_toplevel.fdo"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="toplevel.bgn" xil_pn:subbranch="FPGAConfiguration"/>
View
12 oving1/oving1.xise
@@ -129,6 +129,14 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
+ <file xil_pn:name="reg_idex.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="reg_exmem.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
</files>
<autoManagedFiles>
@@ -371,8 +379,8 @@
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_toplevel" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_toplevel" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/reg_ifid" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.reg_ifid" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
View
1  oving1/reg_exmem.lso
@@ -0,0 +1 @@
+work
View
1  oving1/reg_exmem.prj
@@ -0,0 +1 @@
+vhdl work "reg_exmem.vhd"
View
57 oving1/reg_exmem.stx
@@ -0,0 +1,57 @@
+Release 12.4 - xst M.81d (nt64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+--> Parameter TMPDIR set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.09 secs
+
+--> Parameter xsthdpdir set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.09 secs
+
+--> Reading design: reg_exmem.prj
+
+TABLE OF CONTENTS
+ 1) Synthesis Options Summary
+ 2) HDL Parsing
+ 3) HDL Elaboration
+ 4) HDL Synthesis
+ 4.1) HDL Synthesis Report
+ 5) Advanced HDL Synthesis
+ 5.1) Advanced HDL Synthesis Report
+ 6) Low Level Synthesis
+ 7) Partition Report
+ 8) Design Summary
+ 8.1) Primitive and Black Box Usage
+ 8.2) Device utilization summary
+ 8.3) Partition Resource Summary
+ 8.4) Timing Report
+ 8.4.1) Clock Information
+ 8.4.2) Asynchronous Control Signals Information
+ 8.4.3) Timing Summary
+ 8.4.4) Timing Details
+ 8.4.5) Cross Clock Domains Report
+
+
+=========================================================================
+* HDL Parsing *
+=========================================================================
+Parsing VHDL file "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_exmem.vhd" into library work
+Parsing entity <reg_exmem>.
+Parsing architecture <Behavioral> of entity <reg_exmem>.
+
+
+Total REAL time to Xst completion: 3.00 secs
+Total CPU time to Xst completion: 3.11 secs
+
+-->
+
+Total memory usage is 183824 kilobytes
+
+Number of errors : 0 ( 0 filtered)
+Number of warnings : 0 ( 0 filtered)
+Number of infos : 0 ( 0 filtered)
+
View
83 oving1/reg_exmem.vhd
@@ -0,0 +1,83 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:55:32 10/13/2012
+-- Design Name:
+-- Module Name: idex - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity reg_exmem is
+ Port ( reg_write_in : in STD_LOGIC;
+ reg_write_out : out STD_LOGIC;
+ branch_in : in STD_LOGIC;
+ branch_out : out STD_LOGIC;
+ mem_read_in : in STD_LOGIC;
+ mem_read_out : out STD_LOGIC;
+ mem_write_in : in STD_LOGIC;
+ mem_write_out : out STD_LOGIC;
+ pc_in : in STD_LOGIC_VECTOR (31 downto 0);
+ pc_out : out STD_LOGIC_VECTOR (31 downto 0);
+ alu_res_in : in STD_LOGIC_VECTOR (31 downto 0);
+ alu_res_out : out STD_LOGIC_VECTOR (31 downto 0);
+ read_data_2_in : in STD_LOGIC_VECTOR (31 downto 0);
+ read_data_2_out : out STD_LOGIC_VECTOR (31 downto 0);
+ rd_selected_in : in STD_LOGIC_VECTOR (4 downto 0);
+ rd_selected_out : out STD_LOGIC_VECTOR (4 downto 0);
+ clk : in STD_LOGIC;
+ reset : in STD_LOGIC);
+
+end reg_exmem;
+
+architecture Behavioral of reg_exmem is
+
+begin
+
+process (reg_write_in, branch_in, mem_read_in, mem_write_in, pc_in, alu_res_in, read_data_2_in,
+ rd_selected_in, clk, reset)
+ begin
+ if (reset = '1') then
+ reg_write_out <= '0';
+ branch_out <= '0';
+ mem_read_out <= '0';
+ mem_write_out <= '0';
+ pc_out <= (others => '0');
+ alu_res_out <= (others => '0');
+ read_data_2_out <= (others => '0');
+ rd_selected_out <= (others => '0');
+ elsif (rising_edge(clk)) then
+ reg_write_out <= reg_write_in;
+ branch_out <= branch_in;
+ mem_read_out <= mem_read_in;
+ mem_write_out <= mem_write_in;
+ pc_out <= pc_in;
+ alu_res_out <= alu_res_in;
+ read_data_2_out <= read_data_2_in;
+ rd_selected_out <= rd_selected_in;
+ end if;
+end process;
+
+end Behavioral;
+
View
51 oving1/reg_exmem.xst
@@ -0,0 +1,51 @@
+set -tmpdir "C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp"
+set -xsthdpdir "C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst"
+run -compileonly yes
+-p xc6slx16-2-csg324
+-top reg_exmem
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+-ifn reg_exmem.prj
+-ifmt mixed
View
1  oving1/reg_idex.lso
@@ -0,0 +1 @@
+work
View
1  oving1/reg_idex.prj
@@ -0,0 +1 @@
+vhdl work "reg_idex.vhd"
View
60 oving1/reg_idex.stx
@@ -0,0 +1,60 @@
+Release 12.4 - xst M.81d (nt64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+--> Parameter TMPDIR set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.11 secs
+
+--> Parameter xsthdpdir set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.11 secs
+
+--> Reading design: reg_idex.prj
+
+TABLE OF CONTENTS
+ 1) Synthesis Options Summary
+ 2) HDL Parsing
+ 3) HDL Elaboration
+ 4) HDL Synthesis
+ 4.1) HDL Synthesis Report
+ 5) Advanced HDL Synthesis
+ 5.1) Advanced HDL Synthesis Report
+ 6) Low Level Synthesis
+ 7) Partition Report
+ 8) Design Summary
+ 8.1) Primitive and Black Box Usage
+ 8.2) Device utilization summary
+ 8.3) Partition Resource Summary
+ 8.4) Timing Report
+ 8.4.1) Clock Information
+ 8.4.2) Asynchronous Control Signals Information
+ 8.4.3) Timing Summary
+ 8.4.4) Timing Details
+ 8.4.5) Cross Clock Domains Report
+
+
+=========================================================================
+* HDL Parsing *
+=========================================================================
+Parsing VHDL file "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" into library work
+Parsing entity <reg_idex>.
+Parsing architecture <Behavioral> of entity <reg_idex>.
+ERROR:HDLCompiler:845 - "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 72: Type of aggregate cannot be determined without context ; 0 visible types match here
+ERROR:HDLCompiler:845 - "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 73: Type of aggregate cannot be determined without context ; 0 visible types match here
+ERROR:HDLCompiler:845 - "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 74: Type of aggregate cannot be determined without context ; 0 visible types match here
+ERROR:HDLCompiler:845 - "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 75: Type of aggregate cannot be determined without context ; 0 visible types match here
+ERROR:HDLCompiler:845 - "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 76: Type of aggregate cannot be determined without context ; 0 visible types match here
+ERROR:HDLCompiler:845 - "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 78: Type of aggregate cannot be determined without context ; 0 visible types match here
+ERROR:HDLCompiler:854 - "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd" Line 64: Unit <behavioral> ignored due to previous errors.
+VHDL file \Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_idex.vhd ignored due to errors
+-->
+
+Total memory usage is 183248 kilobytes
+
+Number of errors : 7 ( 0 filtered)
+Number of warnings : 0 ( 0 filtered)
+Number of infos : 0 ( 0 filtered)
+
View
6 oving1/idex.vhd → oving1/reg_idex.vhd
@@ -29,7 +29,7 @@ use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
-entity idex is
+entity reg_idex is
Port ( reg_write_in : in STD_LOGIC;
reg_write_out : out STD_LOGIC;
branch_in : in STD_LOGIC;
@@ -59,9 +59,9 @@ entity idex is
clk : in STD_LOGIC;
reset : in STD_LOGIC);
-end idex;
+end reg_idex;
-architecture Behavioral of idex is
+architecture Behavioral of reg_idex is
begin
View
14 oving1/reg_idex.vhdPreview
@@ -0,0 +1,14 @@
+[Preview]
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F795CA6677D4AC8113E6DECBAA595B6CA95943CE3ACD8B87F5CF2B31BF3DE49FFBF8C031D5ACB5CC3F87F5BB5A419F59241A9154A24F73D0F99AB580F6A5BBE11181FC73D0ADE17922FFDC769A35FB6CA159B33AB7769A357FFF74A1BE5E07CD5A2537CCBF4F42DFB4E7E89B6669956F87BE69F44DA36F1AA136EDC568D3B6CB79A6FDC8A4A558ACEB6D77EB9BE6FA07C35337EB99313F3401EBB58E7CD3104B907F0E9A356877A10F3B3FF817B9981AF1756B23A98B2D356B76AC87FBD79C709F86F418FD842E6227CD9AB66FE234346B18FBB6D2ACC1170779F1D027E8D6CE0C7CA27520FF5CF4D3BFB5D7AC35C6C1F80C2A33797DAF21075D3BCD9A8EB5CD3818F9E7AC5FB1D5A805356BD000BACFB69D7FB0AB590B8E83E99B46C88BD3A6BDCAE31D8C77AD9E0CF7B7A9598BFBEB67C1FEBB9A357B3D62D3BA894DB62EBC0B76D2AC21C6E23ACD3F97CAB6D5ACB9FA37EBEF8EFC73A96CDD1FBF55FE39773E18F1CEFAA8B7D3ACD9727B9D7FCE6AD6381F4C08218410EA22A88B2084BC59BCAC7C726E3C0FCE63D8BC6CF8AE9D34DFADF3A61EBB77B913CF1EFBDD3D9DA9E75DB379CEB69B138F373D83945E877A5A69758379E3500ECF601D39EB9C79854EF2C6615EA0942BE8736A97376E6D6DB34F764E04ED2247DE7679E3AE4E795BF623DACFCCD615FC2CEB79E33C7F0E17CF79BBBC713A0762EEB5DD5E65376F1C7CDAA7AE4ED59FA1791E9A378E7F8384BA88574E17E1FACA7C69E2C2627A60470D830BD6D83D73DDED471B52F636D7EBB7D33F542BA526FD03D6ACE0C500EDC3487A51B50CADF40F272FDD96AA37A87A84BF9E1891C2D5A4EA1F5291E3FEBADA76FA0778F3FCFBD3485DFF006F8736FA07DB27AFBAA1ED416BE15D1A91DEFE8CEA1F623DA1969E3D8893378A3312896EFAA4B5D33FE0F3FD62F0649396E1D0407A5BFD03AEC1B5562F51F5E26DF50FAE670FDE63D03F700E98D037EDE5FAA6B5D345D0378DBE6984904D9E573E392FD97A4EF9457AF6206FDCA08981C81B3738F28DE68D437EB69EDE7ACE38C496A0B79B9B37AE7FE4AAE6711B3B17F58F63BD5DFA3D7CA7BC7147635774CF08F2C60D84BB5AE68DC3B1ED53F4E303DA0672D4A1BD5022AB1EBEE148BCE55C049EF3E8959244C31F690CC6BFDBE58D435C846FDA6EB40D3BC550376F9C3B174108218410420821E4CDF56E418EF6A0F6DE5D2307D48A3D5FE0F3FB2A79E8D0E7979017C7F1BEB8CE258EC4BA657074CAD74534CD059F9E9068B45F6335D6EEAD870E3C7C5C6F9EA0DE2B385788751F9B770C1E3AF0E3D9F4D079A4F39ADBEDC56A97F72D67EAB5B9DFEA1E3A6B5B3C74DCBC6FB59257F7CA09776F7AE884229B1E3A0D4F9C561E3AC8FD663D74FAE3FDBE870E7C776CDE37AC47EA9EE18687CE578303BE874EBBBC6FDB7AE8B4C9FB961B0EFBCF733411D931EF1B9EAD5D7B83874ED043A955DE37D57678557AE810F29CF88789C15E754D92C9B87AE4B41A03E1BCF5D181DECB7AE8601DCED5A075E2A163354CF0D081CEC9F5D069B5E6D789860C7B82AD8E4C3D741C1D592B0D19345DD08A4147E67BE8146ABE86CC6AC25A79E84047663D74D637363564F84E613564EAA183F28E678FF5D069A721DB8D878ED590E1F3B0CFF3CFBDFD3B6AC85C1F23E8CE5C1D99D561043564F65D460F1D429ECF5C443299F1F721CC383E044DE357477F8F32D64307797F5C0DDA4EE3E035A72EF5D031F1061E3A955ACDD73959FD543B2D73ABBC6FD61BCD7AE8B8B9DF5AE57D431E366832F06FEBA16363103C74AC274E2B0F1DE47EB31E3AD944C8F7D0D198D9C8FB667D7D5CCF9E6D3D741AE3E04E3D746CDEB7471D78E8B879DFF06C5D3FA4A04EB955DEB7767E488490378F7679DFAA95193F1605634BBBBC6F6E5DEAA1D328B76ECBB5F1D0C1B52D3D744CBDC1BC6FAE678FF5D06997F76D371E3A36EFDB5E7AE8D83D93CCFB460821849037652E02DF4BA98B20849097438F89B53BCD07E33BAAFD6E8E32D64327B84ED36EEFA9EBA1E37ABEB4D54635BC605A79E8C4DB78E8D83EA24FD82B1DF4D0592C979ADE2976FEA095874EDEB4B9B65EF33D82DD7905BDBEE1A1E3FA0ADB396ECC55C04307F31B2DF7ADE53DDF43077DB5BE45C17E347BE8A41C0F9D3529CE64D5E7677DBDE63F4FF8BB77E2A1633F0F3BDFE1EE5BA3870E21AFA6360DF10D79DFD40B2C5F136F2C2AE1C33D8DFC723BC7E088F99B0FED3F28A727D24D9AA9767DC2FA502B0D9ADD1F3CD21F6B8A2D88C1D1B19CAF418B9D8BAB26EC868977563736353CA2FA33AC212206B7D3A0417B67F3B8FDF14058F567C8E3B668625F2B0D5AA55AF1356FC8E35648465583367CF293B66B6F8949F33C42750D9ACDA9D72A8F9BD5A0218F1BF464D09F218FDBA9D871C9C406747DD03ECFA9E92BBE06ED4A21EF6BD682FE0DAE060D6B74EEDA1BF2B8D1438790173B17F1DEBEB089C1113F0623360CC57AB6E822ACAF0362B0EFA16362402731D8F5D041CCD8C94347F50C6D3C74A0896BE5A15343EC6E78E8587F9CA0878EF5B971FDBC5A79E8A00C3C7462C9AB660C1C69EBA133F8D509DF4307E7BF34D7751DF8583D74666E4CB6D5A0590F1D78286CFA16B5F7D0F9F6F259F5D079EBEDDF0BFEBB3CD023C78F1D176F28EA3F4FEFE23F3BF2D081EF9AF5D0815ECDD5A0D1438790573756DBFC912FC24307B4F3D0C1BEBE561E3AD8A7613D7470DCCA43A77B28AB7B36108FB3A59AEF8913F4D0891E3BAC1E3AEFBCFB8E8E2B51E6912983F2A8CB7AE81CFCC3DBBE870ECEF79D88AAE70EAE9938136D3B17613D74BC8961C7B7A8BD878EABB57B560F1D8C83AD870EC6C1F4D0218431B815AD3468A954CACFD1D9D22B3C90C70D73B376DE1773BAB61EC460579BE6AE492675FCDDC8E3D6983FB665DA69D0EC79E471B3E55BE50AB51A34C4569B2F7533A7DE8BD7A0D5F72553834608218410D2EEBBEB6E72BD3D6BCEB99789BBE74CF7526CB3678F1042F6EA7BA9CD1B67F55DF8FE6BE351F07BBFD53FE1FB73A956DBFCDEBDBEF93D3DF8DD1975E1BBF79A13E7AC86AC5DAC6BE9F9D3D0A9E15A7B9CD6B9D475BF5FEDBEB7DB9FDBF63AD1BCD9E7619F41ABBC71AEE6CDE680B37322C899C6384E08D98EDF1EEE97DFBEF59624C2FB7C0D5A2E3DA09E66FB4311F5476B158333C33129950BD275F890C6AE52B52AFDD168CB186C7DD77EAE96FC7AA16B4B7A3F4B34D2BDC573AD5D0C86DECA7A7EA19E4F426189BEFF478DC1AE37D8767AB768BF899573531A8377D2BC59BDDBB12EE4EE29FB1AB4769AB702F2B635CE57B2938EDF18F55E8490F6DFBF6DDE38572715FF3C5AD73AC59B756AF0D412795732031F48A55A94F7DE3BA0F30DD82380180C5D5B50B380180C2DC3D8D425BF5E68B7BAA263AAE36AB596DF2A06DB3C675FC63E91784F5886CF0FC8F817FFA5EF854E3C7FA0774BC413BA56075FB49D346F56EFB6B151DB366F9CD5B3B9659ABC6EA8F7228474188FDBE9A49E0725E463DFA3EFEA9DE8B2A077EB1F88496AA057BD2E77D2BC59BD1BC6CABA87A14DDE38AB79CB99786BF56B839F1DE3EF142164D731B89D4EEA75C0DD9FAC5AB61D346F56EF66F711BBBE6BED346FAE7E8DBF538410420821D4A61142087939DA34BF5ECF336D99EFEFB9C296398F76B91A7CCF357CE76FCC2360FDAFDDFDA01EAC954183E67A9FE97EBB36BA5F578306BD1CDA44FF728E8F9CBDEF961A34F88D51834608790A10AFA25DDDBE278FD545201F59B250ABE78D0BEC3B465C83360D79D8FE75EAB49EB7F9E6EA7B5FB7CE27A35EF8C57C69C6D4E3B7AB3BE68E737518C9B8E7F7A9EC8D4BDEBBB9ED381C79E7867315B93DFE859FDF0D7B9393E7BFDACC39E7EE215EAFE79D9B2B55E5C2A9A8E69D430EB8AF4F1D53BF2137E71C72FDE03E3673C85524636238F3AD11429E761DCE7A17B831389B49FBDAAB5631B894CFA86FA38EA11B7314DBEDD1D03D19665C991CF75A8E45DB8D83D187E0BE88BA476FFB7BC2FB60319B9042A9DC94DF0DFA319B73CE2DFF68A39E770E9E6636CF1CF2BEC53E0DE938D7CD3907BFB52A72D33572C8418FD1EA391142C8ABA24D7B16CF9FB586D70DF661747ACD9C898BD0A00D0DF4FAFE66C73E3EA0FAB3FEEE2E9938DDEC69060D1AF66940838663E8CEBAC311C9163CD5998522711DF7B6D2A0611E83BF3B84104208216F8E2EC27A3F60EE815A08420879F1313891AD48F6F451C6E0174CDD8FF9E5EF7FAE609F23BD3008792676EBD993C75C6B7758A6460765EAA7924442FB350FD2DA62BA6519AC6575E2D3D36E4DAE9D4F4FA6FC48C2F1A16DF7A3B93E3DE5B9293F071CD6D2B6F3E9C19C2F7C7A6C5EBACB8303B2B8B6DE914F4F506F71EED85FB7E4A6434E3894472E3BE401453D988BC633802FD057A63D9B9B2E36929574A659739129AEF979A45AE5A3432EBAEED888E6FF402EBA48DF3F34B75CAD9295A17C4DF3D14DC406646CEAB2641361CD4587FC7EF679BACF3CF83EC69A652CDAAF6BAAC535E843EAFE1A9BFE44FC9B2264B7EB70BBF1ECB1F1F5FC69131F4C2C426EB97631186B5FF05FE8C4A7A75D0C6EE7D383FAAC67DB76F7677D7ACAA59C9F030E7988ADEEAE954FCFE571C4B79A9F970E656EDCCC74E4D3D3142B4D99FCCDADB9E96CBD00DE41E813BC830AE58AD685EBFCDC7489846A9B9BEACD9455C3E1EAFEDC7554E4A2431CC57B0FB9E86C6EB95E13777FF34E97E6A33B7CECB8BE6BE00B875C74955AD57F9EF6998FC49AF392429337991E57DD09B485D00D961BF9E8DA7D7E849057CBB367AF7C7AA009432CDDA99CF5E9713512C801877994763E3DAE4602DA076824D66B73BBF6E9416EBADADCD896DC74572E9DD3F238FEE2C409ED13BC83A0BDB09A0C9B9B0E39AF33D9E6BD893AFECCD763DF76F9E8F09EEA34179D3ED31D9E27C6C1D04D0F4423FA197A663C1EF4C82384D0B3A79D4F8F9B03CE7AB8B7F4E931E56CCE395C6B7DE277EBD383B91D689983B9E91E617EA6A175CE15F2FE798C915117DAB3B9E9A0A52ECDCCB49D0FDE2E1F1DC6EC7B9D8B0EEF3E3BDFCFF960420821845017415D04F50F849017E1D963F72A636F33D668B0EFCC7AF6B8DF576D3DF82EBC5B9F1EEBDBFBB43E3DB6EF4FEDD3D39857409DF69D62E725AC4F4FD33AA569AF64EECFCD096AE715EC7C85DFA7867731DA2D9AF6D2C994CE73E05CD093CECEFBDAF760AB9C1C4DEFBEACA7F556D6D6C4337DCFCF142537775BFB8DB95E5B3FEE4B75DD981369E4E76B351FE3EF5F77E67D99238F9097EBD963BD79CE0E9DD535F2622A62626C5CAA5E3CE0D173DB5F27DAAD4FCFC633FAF46C6C3C7A269F9EC2D5E4A64FCFE5CBAA036BF6E969D6295CB83C2EFFFE3422E5DAA21492E74DBB35A994CAF2F537F5F2D03E20C6A14FA8EBC205EC6B59D7F67A3FF95C429188C47A425BF663BBFA07F779BAC4CDFB139FD3178327A5FFD497AAA978FBB76FCBC10F3E9481BE5372F346469FA13767E2E6A37A5DE3E9BA862EEE555513F2E5A9FEA6CF0FBA0DD567FC30EDFB2659FD03DEAFF42722E4E57BF61435B77151C7D0C17130CAA4E2297F6CB55B9F1E1DD73E834FCFF9E4D567F2E9C1B1F5E9B1F1A8C9A727A01F409C5E37B1F5EB9161D9FF41AF6413212D7366C2F37D7DCE0F8C6A9F4E0E7E2167063ED1F3682FFAE9DF342EE3D8D5C8B93A60BC6326FB475BC660CD4D0A7DC57FBDDF340EC7679A33EF17F7DF36FFB4D5A0596FCFE038F89B5173BFE6BDA7EF1F3B1E6FE880A94123E4D7A14DB363BFA7BDFE597C7A0647BE79269F1E1CC3A7E7CAE880EACFB0CF63DDC4CC561A34C4D7E8B1C3AA413B783CA27A3268D050268BB988161AB46F4DBD56F376A837AAE5A1415B0F7C4F70E7228EBF77BCEDE7020D1A62F05E69D0303E8F4607253F35BC652E821042082184BC9EDF03EC77F75673278410F2A2E7896FCFCDBC31F9E4188309212F459BD6C809E7EAA7700CBF8178DFF1967A61AC9979D9AC9F5B0E73BFD03305D7E7DC78BEE6C439CDAB51A9B68D75580F0CEAB0ECDEB68AAE07D68FDDB526D4DB6E5F98FDB96DCF5EEFEE9F0B7A4FB8FA357B7FC1B5C2C572A97D9E39EAB808213B003D412D5F5FE7FEFD873DBEAE179AA748AA6862F03F9AB5505E55D6AA9E9ED7FF3BB9E5C627D366DC5C925AA9390E42C786766EDE1CF7356FD0A9C16BABF63FB7B7946F07B457564B857A7EC6DAFDD921FF3EB6D3BEE1DD51ADB8FAB50DCD3507DDC160A6AC1AB691F4A2DE87AB5FFB3933A1FA35AF5C53FD1A34657F3D31A2FA35E49A4B458EB7C9335774745CDCDF4008D968BBA61E3DDAA57306EF8412F21B1119EADEA7DE87FBBAC212DEF75E530C812F6224129664CF475235314FE45DC90C7C2033C51B750FC616FB08A2A727D41B676CEA52471E6AEDC6C1ED3CD430C6558FB74868DB71A7F55083CE0DBA0DF8A8C1AF2C79B5D0D643AD300E7D56ADC91FEDA353131D79A8F93AAEB50A7FD708217BBA7F3919FF7CCBB8B3B458DE9DFFCB1E79A8598DD84EB1CE7AA8A5A05F33635FF8A8412BD6D31B6EEBA1068F61E8D7741CDEF04D1B3B17DDB5871A21841042082184104276D669611FD7E9F38937469B4608212F9AA3A7B3BA966573D8586D9ACD8513D4A6614D2E1E096B9E396F2CA1E5AD2EA2AB272EA35F44B7E48AB379EA862E7972EC785406C66E686EB94E3CD422A9ACFAE7A45311397C2CEAE73F6B773F5817EB8D25B7E490CB158B3AB73BD0DF2D95DCD5E635C3400E39E474430EB9D8C898E67D8B7587D58BAC750E394FFA7BFEC95C6A8490575617617D2852F99ABCF7A7A81CEDFEC4CF49B9530C86FEEBB889C1EB1B558DC136FFD94EEB732D73C8C103CEF4191A86A6B1FB46730E399BD3EDEB4F0FF8FE95B8A776FA8756DE468410D209EABB0BFFE0467E9F5463FF04E613703E934C36C560BB4763FCC2E7BE3EB894CFA857EF763158F764946ABBF65043FF9EC543EDD05F069FC9430DF7623DD4107B11A39B3CD44CBC670C2684BC686DDA4C36D3B1EEB595E76EA7E0DADD7AA859BF75770F5C0A7EF0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7F8F71F403EAD4C539A817FDBD5EF36C6F34FF6AB7C0727B5C1C75773C8D8FF3194FD4E7EBE6A954A9313FEC36FAE474D038CAC8E2289A5737EB8D2C8E5229A4703BF5A893EF2B1A470905424C7B2648DC65834CAD80C3E1EEC45156B319B14080C569348EEAA54F2C8EE2F4A9A34FB4DEC0E9D35F83271A47E9958A73FA44E3A86E7DE2F211F763ED7C2BCD97B739BAD837DB689DB0B8E6E2FCF35EF3336E928FC8EFE62FE523E2F144CF7CC4FEFECDE3A8EFD9E616972197C991CF24BE6AFD496F9E849437C2E6E4BC79FB96D5A08686C7A0335AD83CAD760DCA6ED62395DEFDE1FBE1BB79FA9AF527CA4C7BCD98DEDA73C26A50955281AB5B5CE0E96BD49F340A7987235A831AEE7F0A8D5C42FC3C0BB4F6338ECA47A7AC964B6B50DCBC92CBB6B6EEC749AB716E3DADDBF647E4F245B85CAE2BFB238AF9428723DA23F1F1B8F7FC435ACBE57A6A7FB785653F268C3A18887F46D7FDB1982D6C3D9FF67A6174ED89318194AD1974D83A65B9F276DDC944EEF94A2177A37CF9A63FC0B1F18576B6EECF098B9D2EF274639DBB41BE9CBBD6F7C793C9EE656BDAB559F22D05A095493B7527EFE20A143219641A333E1C1661714E11068DB019B5989CF7C1E39EE138BA079E5A84A77436C758A26C1D5D8A975A9D791BD44A0735E6FB058966757394C966185F94B33FBA761937A7EA3C4F5AD1385B6F8EF2642731944AC2233ED707164F69F5C64BDA24A73E9B48D4D126A14881870F1EE0CDC03BA24D79F0256A886512BC1E1C441FB1A5F91944F355FCFB9F3FB11CF9AF8F9F40417CC17FFEFC6F121B9DF59BD33530691DF7D1C387E093588CFF6E90C552ED3AEED2FA16E6BDEE1FBA07E9733CDD549B28538968F4125309CA14D1A683DA21ABDFB67310F435FF26F1271B0DC6D375FD1007B51AF1F9AB1C4F1778A273E4DB6B375296DA730A55E3C2CE5ACDEDBCC42F8F9E231D0BB1BCC4904080572F1E4242C62909336D8EF8BC372C2F31F4FA31E328115AEF70448F45FB629FBF19611C2DCD7A3A7DB16D8EB8BED8339EF6F6F297FCBDF6DAA9BDE61476E725A836D1BC36E5281C4D60DAE362DA94EDE288E628685E82FE1D0A05D99CA9EB3862DBC9F8338E7EECBED876BE7C6044885629C572E506C948676E2E173F7D5B96CAE6D9BAC907E57D96D3E1E2A7BF164F5CFCF46DF646B479EAF48997AAE7FA61EF237EE2EC7A9B70CFB35ED881376F50D9DD815E6B84D5A4C6A46BEA0FF5975FD76F34E59EE6E633DD014F6D7FAF9D87B8EBFE725A77E2AEF5FDF044FBF6E89AF9DDFDE5B46FCF3BE3EAE814CD49BCE58DE1F58B472C27215168302494E0D5CB178C2397CBC3E9D43DF1D4FE0D9993D3D31E79BEABFBCBF7493CB6EC5BE4FCBD7BE489AE71447F1B634CAA21BE9F9CE5F9A836D118AAAD4D9427A77B11369B95E5F9DADA446328DA6B446328AA4DD4F7138904649B191687030B733E4E9BEE982796A7A8D66F1D43516D3A8BA14E99EFB74798DA0E4590CBA6B1CBF97EF7C613CDF3D1B94F176328A3D9706EEE138DA18CE491E622284756870D4A8D165A124B518E386DBA7BEBFC2E5A79FF9CEF77BE5EF4F1C6F9728EA32F378B631252B10852A1185A8504EEC9098847DF115D6ADD59FDC96874703CDD414FF9E51C75ED4EEB4F1C4FF7C753E3F8F88BEB4F2ABD955B03E28E79DADB2B74FCBDEEDF48EBCE47DCA4FE74C6511A6B9B01CCCCCC72D7F89EF2E5ED7CC4CCCCFCBDAC1FB1BABCC6C550B75CEFB5BBCF87D69F62B178A7C79CCBEF7D7DAB93FB5AA233C13BE180506DC4ECCC14EBF5A6FD0957F144D7E2BBCBF523B87AEEF546BF7FC2B1048AF9DC953C5D5E57E2E8DCBEB7C9EF71F5DC9B5BFBF735E83A5C93935330D85DF0AF2C3036741A239EBCE88346A3837F7996B1A1D66AF0F1E880BB767F264F5D3E5A9B8DEEB8E9221B9C71C6D91DFA822784B9129743F81A7690CDA292882346B42960B1C3AF52E2E4E32936A47A846D0E841C0EECCCCE604DAA4062CA85F4CA0A823627C2561B16FA06B0C41F45D46EC1865A87B9D76FB12AD72039E54162928CF36D20645423BBBA8A5DDFDC9573CD38FB63F681E61D0221E4B6C2C8AFAEA04A62A652248466AD8646A98C4224820FAD268E8FAE8F431B240EA2F6A1D9E0AEED1DF044EFF9D8CC1C36141A6C198D589529B0A2D4224F3828A78B08592D0813B6C2161376BC4EBC176A907059B86BF8958DDEF3ADA3160ECB55D473E7E3CC56A385623080FD440AA57802A9C5451C12AE9AB51A77EDBE324FF4EF0D1A27E97488BBA750C997B141B426ECF1129D59C6A68AF035264389FCBFD6C44A6C53BEEC262CF1C6919A9F426CCA8BB0DB8B4D8D09419309D93937F2D10CB6741A942341728C556CCAC48859C931ED767C201A18767A10221AB822D520A051E2B8CEFDDEDEAD6BB5CD631CA4B38CAFE64119273D7212ED6D171F3B79283AB6FCFB3A29AD7AADB3CF71EB049554FAD3F6C3AF723F7E2F3CF9F8626C2AA5884C78E07B3B8AF9E7CFB030348275B10C9B7211F93E4C312E5678C3CC2F6CEE67B12A51226C36204218DCD418097372C28891F887126CC844286E6F2017CB21A896627954485814635BAB44C06C42D2EB41B3F511EF79622C8D8C61436741D0EEC4326F0CEF47C7B0A990204E7CC790418F753E8FE5991233B3844B25EA953A62D35E721E15D634666C4A24D8D629D9FBDCA6FB8BA5C43F7522E6B4C1AF24E733EABF1B864A8904F1E3AEF7CB5ADDEB2CE7F7982FD7F6EB2EB2C6F218F5065A35C2D615BF23DAE689EE47D9BDC8EC87AE63D1E7F49CBDF8ED35E6A4C9AD2DC1D977A473475CADEFBEF211D4170B3ABDF0F1E458110A907D3F83CCEA0682563B9604322CBE7A4EFC381BF1DD0C48CCCEB33C4364C205BFC68A986B92F8EE19A2532308693548FB7CC497D8E3AEF53DD97E3C896238866228845A368DA3CA018AB124F10193D80B8671B09344399944359362B989DA6E1E7BDB647B3AC3F219E5641A959D1D9C1CD6BEC8F73AC8E5897E7175946E7FCFAF3360CB6842C6B788158509B32F5F337F6FDB6221F18D1651870D0789286186C44B936EACF346183F89690FE2F38B58E6CB99FF4563A7CC7A002BE27144488C1575B9B01FDA4274C28D98C304BFDE847585122B321982E4B8C727A7C4573420E375B1DC4740AF211C13FF4DABC0B66B0E736F87B03AD48F0D850AA7C775E25B7AB1A526E7595BC59A5C8F65A1889DF387CB83B3B980C7E7FC3ACA48DB873A2C1D5CCAD7F5F2ABDAF153FB38B5DD02F1E72AE7E2A78BB113CD7DD472E99EC764FB7E9AC34873F5DDFE258DF3BE67EEFEAAF1532557619ABAA9D2614D61EC9CEB47E0E8AF163F7D8E65CE38E38CB3ABCC4CFC3B834A04855285930FA78824E6B1B9A9C6ECCC20B6B76D4826D7100D3BE0F30DA1B41F413AB386446206EF7D7C84031AC4E3D338FD4F7B57DA95461245EFFFFF9C3889C75D5C11113C82083A23015164138166D1060DA0CDAA60D3A89899AE224D909018278EE09CF7E11E40BB045F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+
View
51 oving1/reg_idex.xst
@@ -0,0 +1,51 @@
+set -tmpdir "C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp"
+set -xsthdpdir "C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst"
+run -compileonly yes
+-p xc6slx16-2-csg324
+-top reg_idex
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+-ifn reg_idex.prj
+-ifmt mixed
View
1  oving1/reg_ifid.lso
@@ -0,0 +1 @@
+work
View
2  oving1/reg_ifid.prj
@@ -0,0 +1,2 @@
+vhdl work "reg_32.vhd"
+vhdl work "reg_ifid.vhd"
View
60 oving1/reg_ifid.stx
@@ -0,0 +1,60 @@
+Release 12.4 - xst M.81d (nt64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+--> Parameter TMPDIR set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.11 secs
+
+--> Parameter xsthdpdir set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.11 secs
+
+--> Reading design: reg_ifid.prj
+
+TABLE OF CONTENTS
+ 1) Synthesis Options Summary
+ 2) HDL Parsing
+ 3) HDL Elaboration
+ 4) HDL Synthesis
+ 4.1) HDL Synthesis Report
+ 5) Advanced HDL Synthesis
+ 5.1) Advanced HDL Synthesis Report
+ 6) Low Level Synthesis
+ 7) Partition Report
+ 8) Design Summary
+ 8.1) Primitive and Black Box Usage
+ 8.2) Device utilization summary
+ 8.3) Partition Resource Summary
+ 8.4) Timing Report
+ 8.4.1) Clock Information
+ 8.4.2) Asynchronous Control Signals Information
+ 8.4.3) Timing Summary
+ 8.4.4) Timing Details
+ 8.4.5) Cross Clock Domains Report
+
+
+=========================================================================
+* HDL Parsing *
+=========================================================================
+Parsing VHDL file "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_32.vhd" into library work
+Parsing entity <reg_32>.
+Parsing architecture <Behavioral> of entity <reg_32>.
+Parsing VHDL file "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_ifid.vhd" into library work
+Parsing entity <reg_ifid>.
+Parsing architecture <Behavioral> of entity <reg_ifid>.
+
+
+Total REAL time to Xst completion: 3.00 secs
+Total CPU time to Xst completion: 3.12 secs
+
+-->
+
+Total memory usage is 183056 kilobytes
+
+Number of errors : 0 ( 0 filtered)
+Number of warnings : 0 ( 0 filtered)
+Number of infos : 0 ( 0 filtered)
+
View
51 oving1/reg_ifid.xst
@@ -0,0 +1,51 @@
+set -tmpdir "C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp"
+set -xsthdpdir "C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst"
+run -compileonly yes
+-p xc6slx16-2-csg324
+-top reg_ifid
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+-ifn reg_ifid.prj
+-ifmt mixed
View
496 oving1/toplevel_envsettings.html
@@ -15,58 +15,58 @@
</tr>
<tr>
<td>PATHEXT</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
-<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td>
+<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td>
+<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td>
</tr>
<tr>
<td>Path</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td>C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.4\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\lib\nt64;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>c:\Python27;<br>c:\modeltech_6.6d\win32;<br>C:\Program Files\TortoiseHg\;<br>o:\;<br>o:\tools;<br>o:\netprog\perl\bin;<br>c:\Python24;<br>c:\Program Files\Sicstus prolog\bin;<br>o:\src\sml\bin;<br>C:\Program Files\Java\jdk1.5.0_01\bin;<br>C:\Program Files\Java\jre1.5.0_01\bin;<br>o:\src\jikes;<br>c:\program files\rational\common</td>
-<td>C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.4\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\lib\nt64;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>c:\Python27;<br>c:\modeltech_6.6d\win32;<br>C:\Program Files\TortoiseHg\;<br>o:\;<br>o:\tools;<br>o:\netprog\perl\bin;<br>c:\Python24;<br>c:\Program Files\Sicstus prolog\bin;<br>o:\src\sml\bin;<br>C:\Program Files\Java\jdk1.5.0_01\bin;<br>C:\Program Files\Java\jre1.5.0_01\bin;<br>o:\src\jikes;<br>c:\program files\rational\common</td>
-<td>C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.4\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\lib\nt64;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>c:\Python27;<br>c:\modeltech_6.6d\win32;<br>C:\Program Files\TortoiseHg\;<br>o:\;<br>o:\tools;<br>o:\netprog\perl\bin;<br>c:\Python24;<br>c:\Program Files\Sicstus prolog\bin;<br>o:\src\sml\bin;<br>C:\Program Files\Java\jdk1.5.0_01\bin;<br>C:\Program Files\Java\jre1.5.0_01\bin;<br>o:\src\jikes;<br>c:\program files\rational\common</td>
+<td>C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.4\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\lib\nt64;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>c:\Python27;<br>c:\modeltech_6.6d\win32;<br>C:\Program Files\TortoiseHg\;<br>C:\Program Files\TortoiseGit\bin;<br>o:\;<br>o:\tools;<br>o:\netprog\perl\bin;<br>c:\Python24;<br>c:\Program Files\Sicstus prolog\bin;<br>o:\src\sml\bin;<br>C:\Program Files\Java\jdk1.5.0_01\bin;<br>C:\Program Files\Java\jre1.5.0_01\bin;<br>o:\src\jikes;<br>c:\program files\rational\common</td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.4\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\lib\nt64;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>c:\Python27;<br>c:\modeltech_6.6d\win32;<br>C:\Program Files\TortoiseHg\;<br>o:\;<br>o:\tools;<br>o:\netprog\perl\bin;<br>c:\Python24;<br>c:\Program Files\Sicstus prolog\bin;<br>o:\src\sml\bin;<br>C:\Program Files\Java\jdk1.5.0_01\bin;<br>C:\Program Files\Java\jre1.5.0_01\bin;<br>o:\src\jikes;<br>c:\program files\rational\common</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.4\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\lib\nt64;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>c:\Python27;<br>c:\modeltech_6.6d\win32;<br>C:\Program Files\TortoiseHg\;<br>o:\;<br>o:\tools;<br>o:\netprog\perl\bin;<br>c:\Python24;<br>c:\Program Files\Sicstus prolog\bin;<br>o:\src\sml\bin;<br>C:\Program Files\Java\jdk1.5.0_01\bin;<br>C:\Program Files\Java\jre1.5.0_01\bin;<br>o:\src\jikes;<br>c:\program files\rational\common</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.4\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.4\ISE_DS\common\lib\nt64;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>c:\Python27;<br>c:\modeltech_6.6d\win32;<br>C:\Program Files\TortoiseHg\;<br>o:\;<br>o:\tools;<br>o:\netprog\perl\bin;<br>c:\Python24;<br>c:\Program Files\Sicstus prolog\bin;<br>o:\src\sml\bin;<br>C:\Program Files\Java\jdk1.5.0_01\bin;<br>C:\Program Files\Java\jre1.5.0_01\bin;<br>o:\src\jikes;<br>c:\program files\rational\common</font></td>
</tr>
<tr>
<td>XILINX</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td>C:\Xilinx\12.4\ISE_DS\ISE\</td>
-<td>C:\Xilinx\12.4\ISE_DS\ISE\</td>
<td>C:\Xilinx\12.4\ISE_DS\ISE\</td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE\</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE\</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE\</font></td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td>2100@xilinx.license.idi.ntnu.no</td>
-<td>2100@xilinx.license.idi.ntnu.no</td>
<td>2100@xilinx.license.idi.ntnu.no</td>
+<td><font color=gray>2100@xilinx.license.idi.ntnu.no</font></td>
+<td><font color=gray>2100@xilinx.license.idi.ntnu.no</font></td>
+<td><font color=gray>2100@xilinx.license.idi.ntnu.no</font></td>
</tr>
<tr>
<td>XILINX_DSP</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td>C:\Xilinx\12.4\ISE_DS\ISE</td>
-<td>C:\Xilinx\12.4\ISE_DS\ISE</td>
<td>C:\Xilinx\12.4\ISE_DS\ISE</td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\ISE</font></td>
</tr>
<tr>
<td>XILINX_EDK</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td>C:\Xilinx\12.4\ISE_DS\EDK</td>
-<td>C:\Xilinx\12.4\ISE_DS\EDK</td>
<td>C:\Xilinx\12.4\ISE_DS\EDK</td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\EDK</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\EDK</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\EDK</font></td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td>C:\Xilinx\12.4\ISE_DS\PlanAhead</td>
-<td>C:\Xilinx\12.4\ISE_DS\PlanAhead</td>
<td>C:\Xilinx\12.4\ISE_DS\PlanAhead</td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\PlanAhead</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\PlanAhead</font></td>
+<td><font color=gray>C:\Xilinx\12.4\ISE_DS\PlanAhead</font></td>
</tr>
</TABLE>
-<A NAME="Translation Property Settings"></A>
+<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
@@ -75,22 +75,316 @@
<td><b>Default Value</b></td>
</tr>
<tr>
-<td>-intstyle</td>
+<td>-ifn</td>
+<td>&nbsp;</td>
+<td>toplevel.prj</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ifmt</td>
+<td>&nbsp;</td>
+<td>mixed</td>
+<td>Mixed</td>
+</tr>
+<tr>
+<td>-ofn</td>
+<td>&nbsp;</td>
+<td>toplevel</td>
<td>&nbsp;</td>
-<td>ise</td>
-<td>None</td>
</tr>
<tr>
-<td>-dd</td>
+<td>-ofmt</td>
<td>&nbsp;</td>
-<td>_ngo</td>
-<td>None</td>
+<td>NGC</td>
+<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
-<td>xc6slx16-csg324-2</td>
-<td>None</td>
+<td>xc6slx16-2-csg324</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-top</td>
+<td>&nbsp;</td>
+<td>toplevel</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-opt_mode</td>
+<td>Optimization Goal</td>
+<td>Speed</td>
+<td>Speed</td>
+</tr>
+<tr>
+<td>-opt_level</td>
+<td>Optimization Effort</td>
+<td>1</td>
+<td>1</td>
+</tr>
+<tr>
+<td>-power</td>
+<td>Power Reduction</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-iuc</td>
+<td>Use synthesis Constraints File</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-keep_hierarchy</td>
+<td>Keep Hierarchy</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-netlist_hierarchy</td>
+<td>Netlist Hierarchy</td>
+<td>As_Optimized</td>
+<td>As_Optimized</td>
+</tr>
+<tr>
+<td>-rtlview</td>
+<td>Generate RTL Schematic</td>
+<td>Yes</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-glob_opt</td>
+<td>Global Optimization Goal</td>
+<td>AllClockNets</td>
+<td>AllClockNets</td>
+</tr>
+<tr>
+<td>-read_cores</td>
+<td>Read Cores</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-write_timing_constraints</td>
+<td>Write Timing Constraints</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-cross_clock_analysis</td>
+<td>Cross Clock Analysis</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-bus_delimiter</td>
+<td>Bus Delimiter</td>
+<td>&lt;&gt;</td>
+<td>&lt;&gt;</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio</td>
+<td>Slice Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-bram_utilization_ratio</td>
+<td>BRAM Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-dsp_utilization_ratio</td>
+<td>DSP Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-reduce_control_sets</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-fsm_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-fsm_encoding</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-safe_implementation</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-fsm_style</td>
+<td>&nbsp;</td>
+<td>LUT</td>
+<td>LUT</td>
+</tr>
+<tr>
+<td>-ram_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-ram_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-rom_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-shreg_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-rom_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-auto_bram_packing</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-resource_sharing</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-async_to_sync</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-use_dsp48</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-iobuf</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-max_fanout</td>
+<td>&nbsp;</td>
+<td>100000</td>
+<td>100000</td>
+</tr>
+<tr>
+<td>-bufg</td>
+<td>&nbsp;</td>
+<td>16</td>
+<td>16</td>
+</tr>
+<tr>
+<td>-register_duplication</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-register_balancing</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-optimize_primitives</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-use_clock_enable</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-use_sync_set</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-use_sync_reset</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-iob</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-equivalent_register_removal</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio_maxmargin</td>
+<td>&nbsp;</td>
+<td>5</td>
+<td>0</td>
+</tr>
+</TABLE>
+<A NAME="Translation Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td><font color=gray>-intstyle</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>ise</font></td>
+<td><font color=gray>None</font></td>
+</tr>
+<tr>
+<td><font color=gray>-dd</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>_ngo</font></td>
+<td><font color=gray>None</font></td>
+</tr>
+<tr>
+<td><font color=gray>-p</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>xc6slx16-csg324-2</font></td>
+<td><font color=gray>None</font></td>
</tr>
</TABLE>
<A NAME="Map Property Settings"></A>
@@ -105,64 +399,64 @@
<td><b>Default Value</b></td>
</tr>
<tr>
-<td>-ol</td>
-<td>Place & Route Effort Level (Overall)</td>
-<td>high</td>
-<td>high</td>
+<td><font color=gray>-ol</font></td>
+<td><font color=gray>Place & Route Effort Level (Overall)</font></td>
+<td><font color=gray>high</font></td>
+<td><font color=gray>high</font></td>
</tr>
<tr>
-<td>-xt</td>
-<td>Extra Cost Tables</td>
-<td>0</td>
-<td>0</td>
+<td><font color=gray>-xt</font></td>
+<td><font color=gray>Extra Cost Tables</font></td>
+<td><font color=gray>0</font></td>
+<td><font color=gray>0</font></td>
</tr>
<tr>
-<td>-ir</td>
-<td>Use RLOC Constraints</td>
-<td>OFF</td>
-<td>OFF</td>
+<td><font color=gray>-ir</font></td>
+<td><font color=gray>Use RLOC Constraints</font></td>
+<td><font color=gray>OFF</font></td>
+<td><font color=gray>OFF</font></td>
</tr>
<tr>
-<td>-t</td>
-<td>Starting Placer Cost Table (1-100) Map</td>
-<td>1</td>
-<td>0</td>
+<td><font color=gray>-t</font></td>
+<td><font color=gray>Starting Placer Cost Table (1-100) Map</font></td>
+<td><font color=gray>1</font></td>
+<td><font color=gray>0</font></td>
</tr>
<tr>
-<td>-intstyle</td>
-<td>&nbsp;</td>
-<td>ise</td>
-<td>None</td>
+<td><font color=gray>-intstyle</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>ise</font></td>
+<td><font color=gray>None</font></td>
</tr>
<tr>
-<td>-lc</td>
-<td>LUT Combining</td>
-<td>off</td>
-<td>off</td>
+<td><font color=gray>-lc</font></td>
+<td><font color=gray>LUT Combining</font></td>
+<td><font color=gray>off</font></td>
+<td><font color=gray>off</font></td>
</tr>
<tr>
-<td>-o</td>
-<td>&nbsp;</td>
-<td>toplevel_map.ncd</td>
-<td>None</td>
+<td><font color=gray>-o</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>toplevel_map.ncd</font></td>
+<td><font color=gray>None</font></td>
</tr>
<tr>
-<td>-w</td>
-<td>&nbsp;</td>
-<td>true</td>
-<td>false</td>
+<td><font color=gray>-w</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>true</font></td>
+<td><font color=gray>false</font></td>
</tr>
<tr>
-<td>-pr</td>
-<td>Pack I/O Registers/Latches into IOBs</td>
-<td>off</td>
-<td>off</td>
+<td><font color=gray>-pr</font></td>
+<td><font color=gray>Pack I/O Registers/Latches into IOBs</font></td>
+<td><font color=gray>off</font></td>
+<td><font color=gray>off</font></td>
</tr>
<tr>
-<td>-p</td>
-<td>&nbsp;</td>
-<td>xc6slx16-csg324-2</td>
-<td>None</td>
+<td><font color=gray>-p</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>xc6slx16-csg324-2</font></td>
+<td><font color=gray>None</font></td>
</tr>
</TABLE>
<A NAME="Place and Route Property Settings"></A>
@@ -177,28 +471,28 @@
<td><b>Default Value</b></td>
</tr>
<tr>
-<td>-intstyle</td>
-<td>&nbsp;</td>
-<td>ise</td>
-<td>&nbsp;</td>
+<td><font color=gray>-intstyle</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>ise</font></td>
+<td><font color=gray>&nbsp;</font></td>
</tr>
<tr>
-<td>-mt</td>
-<td>Enable Multi-Threading</td>
-<td>off</td>
-<td>off</td>
+<td><font color=gray>-mt</font></td>
+<td><font color=gray>Enable Multi-Threading</font></td>
+<td><font color=gray>off</font></td>
+<td><font color=gray>off</font></td>
</tr>
<tr>
-<td>-ol</td>
-<td>Place & Route Effort Level (Overall)</td>
-<td>high</td>
-<td>std</td>
+<td><font color=gray>-ol</font></td>
+<td><font color=gray>Place & Route Effort Level (Overall)</font></td>
+<td><font color=gray>high</font></td>
+<td><font color=gray>std</font></td>
</tr>
<tr>
-<td>-w</td>
-<td>&nbsp;</td>
-<td>true</td>
-<td>false</td>
+<td><font color=gray>-w</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>true</font></td>
+<td><font color=gray>false</font></td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
@@ -215,31 +509,31 @@
</tr>
<tr>
<td>CPU Architecture/Speed</td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td>Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz/2400 MHz</td>
-<td>Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz/2400 MHz</td>
<td>Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz/2400 MHz</td>
+<td><font color=gray>Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz/2400 MHz</font></td>
+<td><font color=gray>Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz/2400 MHz</font></td>
+<td><font color=gray>Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz/2400 MHz</font></td>
</tr>
<tr>
<td>Host</td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td>dmlab09</td>
-<td>dmlab09</td>
-<td>dmlab09</td>
+<td>dmlab05</td>
+<td><font color=gray>dmlab09</font></td>
+<td><font color=gray>dmlab09</font></td>
+<td><font color=gray>dmlab09</font></td>
</tr>
<tr>
<td>OS Name</td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td>Microsoft </td>
-<td>Microsoft </td>
<td>Microsoft </td>
+<td><font color=gray>Microsoft </font></td>
+<td><font color=gray>Microsoft </font></td>
+<td><font color=gray>Microsoft </font></td>
</tr>
<tr>
<td>OS Release</td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td>Service Pack 1 (build 7601)</td>
-<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
+<td><font color=gray>Service Pack 1 (build 7601)</font></td>
+<td><font color=gray>Service Pack 1 (build 7601)</font></td>
+<td><font color=gray>Service Pack 1 (build 7601)</font></td>
</tr>
</TABLE>
</BODY> </HTML>
View
55 oving1/toplevel_summary.html
@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>toplevel Project Status (10/13/2012 - 20:18:47)</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>toplevel Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>oving1.xise</TD>
@@ -43,7 +43,7 @@
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
-<A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\toplevel_envsettings.html'>
+<A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\toplevel_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
@@ -53,7 +53,36 @@
-
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
+<TD ALIGN=RIGHT>17727</TD>
+<TD ALIGN=RIGHT>18224</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>97%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
+<TD ALIGN=RIGHT>14595</TD>
+<TD ALIGN=RIGHT>9112</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>160%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
+<TD ALIGN=RIGHT>8299</TD>
+<TD ALIGN=RIGHT>24023</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>34%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
+<TD ALIGN=RIGHT>138</TD>
+<TD ALIGN=RIGHT>232</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>59%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGCTRLs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>16</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>6%</TD>
+</TR>
+</TABLE>
@@ -65,22 +94,22 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\toplevel.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>lø 13. okt 20:22:02 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\toplevel.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 19:55:24 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\toplevel_map.mrp'>Map Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 19:55:24 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\toplevel.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 19:55:24 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\toplevel.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>lø 13. okt 21:41:04 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\toplevel.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 15:29:39 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\toplevel_map.mrp'>Map Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 15:29:39 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\toplevel.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 15:29:39 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\toplevel.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 19:55:24 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\toplevel.bgn'>Bitgen Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 19:55:24 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\toplevel.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 15:29:39 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\toplevel.bgn'>Bitgen Report</A></TD><TD>Out of Date</TD><TD>lø 13. okt 15:29:39 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\netgen/synthesis/toplevel_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lø 13. okt 19:55:24 2012</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lø 13. okt 19:55:25 2012</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/git/GitHub/tdt4255/oving1\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lø 13. okt 19:55:25 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\netgen/synthesis/toplevel_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lø 13. okt 15:29:39 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lø 13. okt 15:29:39 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/chribru/Desktop/GitHub/tdt4255/oving1\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lø 13. okt 15:29:39 2012</TD></TR>
</TABLE>
-<br><center><b>Date Generated:</b> 10/13/2012 - 20:18:48</center>
+<br><center><b>Date Generated:</b> 10/13/2012 - 22:24:46</center>
</BODY></HTML>
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