diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f3fab3e6b6f9..a3bceb236792 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9299,7 +9299,7 @@ RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
   if (DL.isFatPointer(AI->getPointerOperand()->getType())) {
     if (!RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) &&
         AI->getOperation() == AtomicRMWInst::Xchg &&
-        DL.isFatPointer(AI->getPointerOperand()->getType()))
+        DL.isFatPointer(AI->getValOperand()->getType()))
       return AtomicExpansionKind::CmpXChg;
     return AtomicExpansionKind::None;
   }