From 1f423d3c31fde022573b78db8b5e431c4ee8b7ee Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Tue, 3 Nov 2020 11:45:41 +0000 Subject: [PATCH] [CHERI-RISCV] Swap CheriStoreCond_r operand order to match AMO_rr --- .../Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp | 12 ++++-------- llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td | 2 +- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp index ebaba99c0510..13858dff9412 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp @@ -968,11 +968,9 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchg( BuildMI(LoopTailMBB, DL, TII->get(RISCV::ADDI), ScratchReg) .addReg(NewValReg) .addImm(0); - // Note: SC_*_CAP has the address register as the second argument not the - // first even though it is called rs1 in tablegen. BuildMI(LoopTailMBB, DL, SCInst, ScratchReg) - .addReg(ScratchReg) - .addReg(AddrReg); + .addReg(AddrReg) + .addReg(ScratchReg); } else { BuildMI(LoopTailMBB, DL, SCInst, ScratchReg) .addReg(AddrReg) @@ -1094,11 +1092,9 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchgCap( // bnez scratch, loophead BuildMI(LoopTailMBB, DL, TII->get(RISCV::CMove), ScratchReg) .addReg(NewValReg); - // Note: SC_C_CAP has the address register as the second argument not the - // first even though it is called rs1 in tablegen. BuildMI(LoopTailMBB, DL, SCInst, ScratchReg) - .addReg(ScratchReg) - .addReg(AddrReg); + .addReg(AddrReg) + .addReg(ScratchReg); // In the explicit case the output register of SC_C_CAP/DDC is a capability // register so we have to extract the GPR register. SCResultReg = TRI->getSubReg(ScratchReg, RISCV::sub_cap_addr); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td index 29d252be4d2f..38794353683a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td @@ -120,7 +120,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $rs2" in class CheriStoreCond_r op, string opcodestr, RegisterClass rs2Class, RegisterOperand rs1Operand> : RVInstCheriTwoSrc<0x7c, op, 0, OPC_CHERI, (outs rs2Class:$rd), - (ins rs2Class:$rs2, rs1Operand:$rs1), + (ins rs1Operand:$rs1, rs2Class:$rs2), opcodestr, "$rs2, $rs1">; let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in