1D binary cellular automata implemented on Xilinx Spartan 6
VHDL
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Nexys3_Master.ucf
cell.vhd
cell1d.vhd
celltest.vhd
clockgen.vhd
debounce.vhd
decimal7seg.vhd
onepulse.vhd
readme
vgacontroller.vhd
vgatest.vhd

readme

Cellular automata tested on digilent nexys3 spartan 6.


Set DCM to output 65Mhz