Folding BIKE: Scalable Hardware Implementation for Reconfigurable Devices
Contains HDL code for the PQC Key Encapsulation Mechanism BIKE for Xilinx FPGAs.
Features
The HDL folder contains VHDL files for the key generation, encapsulation, and decapsulation for the security levels 1 and 3. As explained in the paper [1], the implementations are scalable with the parameter b. For each algorithm and each security level there are three implementations with b=32, b=64, and b=128. For the key generation we additionally investigated three different strategies (S1, S2, S3) and added the corresponding VHDL code to this repository. In summary, our implementation comes with the following features:
- Complete hardware implementation of BIKE
- Investigations of different inversion strategies
- Hardware implementation of the Black-Gray-Flip decoder
- Paramized implementation to fit different use-cases
Contact and Support
Please contact Jan Richter-Brockmann (jan.richter-brockmann@rub.de) or Tim Güneysu (tim.gueneysu@rub.de) if you have any questions, comments, if you found a bug that should be corrected, or if you want to reuse the VHDL code or parts of it for your own research projects. Additionally, some modules are generated by MathSage scripts. If you would like to get access to these scripts, please contact Jan Richter-Brockmann or Tim Güneysu as well.
Licensing
Copyright (c) 2020, Jan Richter-Brockmann. All rights reserved.
Please see LICENSE for further license instructions.