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ChampSim is a trace-based simulator for a microarchitecture study. You can sign up to the public mailing list by sending an empty mail to A set of traces used for the 2nd Cache Replacement Championship (CRC-2) can be found from this link. (

Clone ChampSim repository

git clone


ChampSim takes five parameters: Branch predictor, L1D prefetcher, L2C prefetcher, LLC replacement policy, and the number of cores. For example, ./ bimodal no no lru 1 builds a single-core processor with bimodal branch predictor, no L1/L2 data prefetchers, and the baseline LRU replacement policy for the LLC.

$ ./ bimodal no no lru 1


Run simulation

Copy scripts/ to the ChampSim root directory and change TRACE_DIR in

  • Single-core simulation: Run simulation with script.
$ ./ bimodal-no-no-lru-1core 1 10 bzip2_183B

$ ./ ${binary} ${n_warm} ${n_sim} ${trace} ${option}

${binary}: ChampSim binary compiled by "" (bimodal-no-no-lru-1core)
${n_warm}: number of instructions for warmup (1 million)
${n_sim}:  number of instructinos for detailed simulation (10 million)
${trace}: trace name (bzip2)
${option}: extra option for "-low_bandwidth" (src/

Simulation results will be stored under "results_${n_sim}M" as a form of "${trace}-${binary}-${option}.txt".

  • Multi-core simulation: Run simulation with or
    Note that ${trace} is replaced with ${num} that represents a unique ID for randomly mixed multi-programmed workloads.
$ ./ ${binary} ${n_warm} ${n_sim} ${num} ${option}

${num}: mix number is the corresponding line number written in sim_list/4core_workloads.txt

Add your own branch predictor, data prefetchers, and replacement policy

Copy an empty template

$ cp branch/ prefetcher/mybranch.bpred
$ cp prefetcher/ prefetcher/mypref.l1d_pref
$ cp prefetcher/ prefetcher/mypref.l2c_pref
$ cp replacement/ replacement/myrepl.llc_repl

Work on your algorithms with your favorite text editor

$ vim branch/mybranch.bpred
$ vim prefetcher/mypref.l1d_pref
$ vim prefetcher/mypref.l2c_pref
$ vim replacement/myrepl.llc_repl

Compile and test

$ ./ mybranch mypref mypref myrepl 1
$ ./ mybranch-mypref-mypref-myrepl-1core 1 10 bzip2_183B

How to create traces

We have included only 4 sample traces, taken from SPEC CPU 2006. These traces are short (10 million instructions), and do not necessarily cover the range of behaviors your replacement algorithm will likely see in the full competition trace list (not included). We STRONGLY recommend creating your own traces, covering a wide variety of program types and behaviors.

The included Pin Tool champsim_tracer.cpp can be used to generate new traces. We used Pin 3.2 (pin-3.2-81205-gcc-linux), and it may require installing,, or other libraries, if you do not already have them. Please refer to the Pin documentation ( for working with Pin 3.2.

Use the Pin tool like this

pin -t obj-intel64/ -- <your program here>

The tracer has three options you can set:

Specify the output file for your trace.
The default is default_trace.champsim

-s <number>
Specify the number of instructions to skip in the program before tracing begins.
The default value is 0.

-t <number>
The number of instructions to trace, after -s instructions have been skipped.
The default value is 1,000,000.

For example, you could trace 200,000 instructions of the program ls, after skipping the first 100,000 instructions, with this command:

pin -t obj/ -o traces/ls_trace.champsim -s 100000 -t 200000 -- ls

Traces created with the are approximately 64 bytes per instruction, but they generally compress down to less than a byte per instruction using xz compression.

Evaluate Simulation

ChampSim measures the IPC (Instruction Per Cycle) value as a performance metric.
There are some other useful metrics printed out at the end of simulation.

Good luck and be a champion!