From 8086479aec652f023b0d97df18c33582a86017f1 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 14 May 2025 08:17:53 +0200 Subject: [PATCH] Adding a Verilog example using PicoSoC Signed-off-by: gatecat --- .github/workflows/main.yaml | 8 +- .gitignore | 1 + .gitmodules | 3 + picosoc_verilog/README.md | 4 + picosoc_verilog/chipflow.toml | 15 + picosoc_verilog/design/design.py | 82 ++++++ picosoc_verilog/design/picorv32 | 1 + picosoc_verilog/design/picosoc_asic_top.v | 135 +++++++++ picosoc_verilog/design/software/.gitignore | 4 + picosoc_verilog/design/software/doit_build.py | 92 +++++++ picosoc_verilog/design/software/main.c | 259 ++++++++++++++++++ picosoc_verilog/design/software/sections.lds | 63 +++++ picosoc_verilog/design/software/start.s | 162 +++++++++++ picosoc_verilog/design/steps/_init_.py | 0 picosoc_verilog/design/steps/software.py | 26 ++ .../design/tests/events_reference.json | 217 +++++++++++++++ picosoc_verilog/design/tests/input.json | 4 + 17 files changed, 1074 insertions(+), 2 deletions(-) create mode 100644 .gitmodules create mode 100644 picosoc_verilog/README.md create mode 100644 picosoc_verilog/chipflow.toml create mode 100644 picosoc_verilog/design/design.py create mode 160000 picosoc_verilog/design/picorv32 create mode 100644 picosoc_verilog/design/picosoc_asic_top.v create mode 100644 picosoc_verilog/design/software/.gitignore create mode 100644 picosoc_verilog/design/software/doit_build.py create mode 100644 picosoc_verilog/design/software/main.c create mode 100644 picosoc_verilog/design/software/sections.lds create mode 100644 picosoc_verilog/design/software/start.s create mode 100644 picosoc_verilog/design/steps/_init_.py create mode 100644 picosoc_verilog/design/steps/software.py create mode 100644 picosoc_verilog/design/tests/events_reference.json create mode 100644 picosoc_verilog/design/tests/input.json diff --git a/.github/workflows/main.yaml b/.github/workflows/main.yaml index 90b6111..919904c 100644 --- a/.github/workflows/main.yaml +++ b/.github/workflows/main.yaml @@ -26,10 +26,12 @@ jobs: runs-on: ubuntu-latest strategy: matrix: - design: ['mcu_soc', 'minimal'] + design: ['mcu_soc', 'minimal', 'picosoc_verilog'] steps: - name: Check out source code uses: actions/checkout@v4 + with: + submodules: true - uses: actions/setup-python@v4 with: @@ -61,10 +63,12 @@ jobs: runs-on: ubuntu-latest strategy: matrix: - design: ['mcu_soc', 'minimal'] + design: ['mcu_soc', 'minimal', 'picosoc_verilog'] steps: - name: Check out source code uses: actions/checkout@v4 + with: + submodules: true - name: Set up PDM uses: pdm-project/setup-pdm@v4 diff --git a/.gitignore b/.gitignore index fc6682a..02da293 100644 --- a/.gitignore +++ b/.gitignore @@ -24,6 +24,7 @@ __pycache__/ /build /mcu_soc/build /minimal/build +/picosoc_verilog/build # testbenches *.vcd diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..a34d6da --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "picosoc_verilog/design/picorv32"] + path = picosoc_verilog/design/picorv32 + url = https://github.com/YosysHQ/picorv32 diff --git a/picosoc_verilog/README.md b/picosoc_verilog/README.md new file mode 100644 index 0000000..c30c471 --- /dev/null +++ b/picosoc_verilog/README.md @@ -0,0 +1,4 @@ +# PicoSoC (Verilog) + +This example design shows how an existing Verilog design (picosoc) can be wrapped in a minimal layer of Amaranth and submitted to the ChipFlow platform. + diff --git a/picosoc_verilog/chipflow.toml b/picosoc_verilog/chipflow.toml new file mode 100644 index 0000000..61e4d71 --- /dev/null +++ b/picosoc_verilog/chipflow.toml @@ -0,0 +1,15 @@ +[chipflow] +project_name = "chipflow-examples-picosoc" + +[chipflow.top] +soc = "design.design:MySoC" + +[chipflow.steps] +software = "design.steps.software:MySoftwareStep" + +[chipflow.silicon] +process = "sky130" +package = "openframe" + +[chipflow.test] +event_reference = "design/tests/events_reference.json" diff --git a/picosoc_verilog/design/design.py b/picosoc_verilog/design/design.py new file mode 100644 index 0000000..0b988ff --- /dev/null +++ b/picosoc_verilog/design/design.py @@ -0,0 +1,82 @@ +import os + +from chipflow_lib.platforms.sim import SimPlatform + +from amaranth import Module, Instance, ClockSignal, ResetSignal +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out, flipped, connect + +from chipflow_lib.platforms import ( + GPIOSignature, UARTSignature, QSPIFlashSignature, + BinaryData, attach_data + ) + +__all__ = ["MySoC"] + + +class MySoC(wiring.Component): + def __init__(self): + # Top level interfaces + + super().__init__({ + "flash": Out(QSPIFlashSignature()), + "uart_0": Out(UARTSignature()), + "gpio_0": Out(GPIOSignature(pin_count=8)), + }) + + def elaborate(self, platform): + m = Module() + + base = os.path.dirname(__file__) + + verilog_sources = [ + f"{base}/picosoc_asic_top.v", + f"{base}/picorv32/picosoc/spimemio.v", + f"{base}/picorv32/picosoc/simpleuart.v", + f"{base}/picorv32/picosoc/picosoc.v", + f"{base}/picorv32/picorv32.v", + ] + + if platform is not None: + for verilog_file in verilog_sources: + with open(verilog_file, 'r') as f: + platform.add_file(verilog_file, f) + + m.submodules.soc = soc = Instance("picosoc_asic_top", + # Clock and reset + i_clk=ClockSignal(), + i_resetn=~ResetSignal(), + + # UART + o_ser_tx=self.uart_0.tx.o, + i_ser_rx=self.uart_0.rx.i, + + # SPI flash + o_flash_csb=self.flash.csn.o, + o_flash_clk=self.flash.clk.o, + + o_flash_io0_oe=self.flash.d.oe[0], + o_flash_io1_oe=self.flash.d.oe[1], + o_flash_io2_oe=self.flash.d.oe[2], + o_flash_io3_oe=self.flash.d.oe[3], + + o_flash_io0_do=self.flash.d.o[0], + o_flash_io1_do=self.flash.d.o[1], + o_flash_io2_do=self.flash.d.o[2], + o_flash_io3_do=self.flash.d.o[3], + + i_flash_io0_di=self.flash.d.i[0], + i_flash_io1_di=self.flash.d.i[1], + i_flash_io2_di=self.flash.d.i[2], + i_flash_io3_di=self.flash.d.i[3], + + # LEDs + o_leds=self.gpio_0.gpio.o + ) + + # Hardwire GPIO to output enabled + m.d.comb += self.gpio_0.gpio.oe.eq(0xFF) + + attach_data(self.flash, None, BinaryData(filename="software.bin", offset=0x00100000)) + + return m diff --git a/picosoc_verilog/design/picorv32 b/picosoc_verilog/design/picorv32 new file mode 160000 index 0000000..87c89ac --- /dev/null +++ b/picosoc_verilog/design/picorv32 @@ -0,0 +1 @@ +Subproject commit 87c89acc18994c8cf9a2311e871818e87d304568 diff --git a/picosoc_verilog/design/picosoc_asic_top.v b/picosoc_verilog/design/picosoc_asic_top.v new file mode 100644 index 0000000..eea863a --- /dev/null +++ b/picosoc_verilog/design/picosoc_asic_top.v @@ -0,0 +1,135 @@ +/* + * PicoSoC - A simple example SoC using PicoRV32 + * + * Copyright (C) 2017 Claire Xenia Wolf + * Copyright (C) 2025 Myrtle Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`define PICOSOC_MEM picosoc_asic_mem + +module picosoc_asic_top ( + input clk, + input resetn, + + output ser_tx, + input ser_rx, + + output [7:0] leds, + + output flash_csb, + output flash_clk, + + output flash_io0_oe, + output flash_io1_oe, + output flash_io2_oe, + output flash_io3_oe, + + output flash_io0_do, + output flash_io1_do, + output flash_io2_do, + output flash_io3_do, + + input flash_io0_di, + input flash_io1_di, + input flash_io2_di, + input flash_io3_di +); + + wire iomem_valid; + reg iomem_ready; + wire [3:0] iomem_wstrb; + wire [31:0] iomem_addr; + wire [31:0] iomem_wdata; + reg [31:0] iomem_rdata; + + reg [31:0] gpio; + assign leds = gpio; + + always @(posedge clk) begin + if (!resetn) begin + gpio <= 0; + end else begin + iomem_ready <= 0; + if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin + iomem_ready <= 1; + iomem_rdata <= gpio; + if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0]; + if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8]; + if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16]; + if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24]; + end + end + end + + picosoc soc ( + .clk (clk ), + .resetn (resetn ), + + .ser_tx (ser_tx ), + .ser_rx (ser_rx ), + + .flash_csb (flash_csb ), + .flash_clk (flash_clk ), + + .flash_io0_oe (flash_io0_oe), + .flash_io1_oe (flash_io1_oe), + .flash_io2_oe (flash_io2_oe), + .flash_io3_oe (flash_io3_oe), + + .flash_io0_do (flash_io0_do), + .flash_io1_do (flash_io1_do), + .flash_io2_do (flash_io2_do), + .flash_io3_do (flash_io3_do), + + .flash_io0_di (flash_io0_di), + .flash_io1_di (flash_io1_di), + .flash_io2_di (flash_io2_di), + .flash_io3_di (flash_io3_di), + + .irq_5 (1'b0 ), + .irq_6 (1'b0 ), + .irq_7 (1'b0 ), + + .iomem_valid (iomem_valid ), + .iomem_ready (iomem_ready ), + .iomem_wstrb (iomem_wstrb ), + .iomem_addr (iomem_addr ), + .iomem_wdata (iomem_wdata ), + .iomem_rdata (iomem_rdata ) + ); +endmodule + +module picosoc_asic_mem #( + parameter integer WORDS = 256 +) ( + input clk, + input [3:0] wen, + input [21:0] addr, + input [31:0] wdata, + output reg [31:0] rdata +); + reg [31:0] mem [0:WORDS-1]; + + always @(posedge clk) begin + if (wen == 4'b0) + rdata <= mem[addr]; + if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0]; + if (wen[1]) mem[addr][15: 8] <= wdata[15: 8]; + if (wen[2]) mem[addr][23:16] <= wdata[23:16]; + if (wen[3]) mem[addr][31:24] <= wdata[31:24]; + end +endmodule + diff --git a/picosoc_verilog/design/software/.gitignore b/picosoc_verilog/design/software/.gitignore new file mode 100644 index 0000000..1e73dec --- /dev/null +++ b/picosoc_verilog/design/software/.gitignore @@ -0,0 +1,4 @@ +*.o +*.elf +*.bin +generated/ diff --git a/picosoc_verilog/design/software/doit_build.py b/picosoc_verilog/design/software/doit_build.py new file mode 100644 index 0000000..933cff6 --- /dev/null +++ b/picosoc_verilog/design/software/doit_build.py @@ -0,0 +1,92 @@ +import os +import sys +from pathlib import Path +import shutil + +from doit import create_after +from doit.action import CmdAction +import chipflow_lib.config + + +BUILD_DIR = "./build/software" +DESIGN_DIR = os.path.dirname(__file__) + "/.." +RISCVCC = f"{sys.executable} -m ziglang cc -target riscv32-freestanding-musl" +CINCLUDES = f"-I. -I{BUILD_DIR} -I{DESIGN_DIR}/software" +LINKER_SCR = f"{DESIGN_DIR}/software/sections.lds" +SOFTWARE_START = f"{DESIGN_DIR}/software/start.s" +CFLAGS = f"-g -mcpu=baseline_rv32-a-c-d -mabi=ilp32 -Wl,--build-id=none,-Bstatic,-T," +CFLAGS += f"{LINKER_SCR},--strip-debug -static -ffreestanding -nostdlib {CINCLUDES}" + + +def task_gather_depencencies(): + src_files = [] + target_files = [] + + # Project dependencies + rel_paths = _get_source_rel_paths(f"{DESIGN_DIR}/software", ["*.c", "*.h"]) + for rel_path in rel_paths: + src_files.append(f"{DESIGN_DIR}/software{rel_path}") + target_files.append(f"{BUILD_DIR}/{rel_path}") + + def copy_files(): + _create_build_dir() + for i in range(len(src_files)): + shutil.copyfile(src_files[i - 1], target_files[i - 1]) + + return { + "actions": [(copy_files)], + "file_dep": src_files, + "targets": target_files, + "verbosity": 2 + } + + +@create_after(executed="gather_depencencies", target_regex=".*/software\\.elf") +def task_build_software_elf(): + sources = [SOFTWARE_START] + sources += _gather_source_paths(f"{BUILD_DIR}", ["*.c"]) + + sources_str = " ".join(sources) + + return { + "actions": [f"{RISCVCC} {CFLAGS} -o {BUILD_DIR}/software.elf {sources_str}"], + "file_dep": sources + [LINKER_SCR], + "targets": [f"{BUILD_DIR}/software.elf"], + "verbosity": 2 + } + + +@create_after(executed="build_software_elf", target_regex=".*/software\\.bin") +def task_build_software(): + return { + "actions": [f"{sys.executable} -m ziglang objcopy -O binary " + f"{BUILD_DIR}/software.elf {BUILD_DIR}/software.bin"], + "file_dep": [f"{BUILD_DIR}/software.elf"], + "targets": [f"{BUILD_DIR}/software.bin"], + } + + +def _create_build_dir(): + Path(f"{BUILD_DIR}").mkdir(parents=True, exist_ok=True) + + +def _get_source_rel_paths(source_dir, globs): + abs_source_dir = str(Path(source_dir).absolute()) + rel_paths = [] + for glob in globs: + source_paths = list(Path(abs_source_dir).glob(glob)) + for source_path in source_paths: + dst = str(source_path).replace(abs_source_dir, "") + rel_paths.append(dst) + + return rel_paths + + +def _gather_source_paths(source_dir, globs): + sources = [] + for glob in globs: + source_paths = list(Path(source_dir).glob(glob)) + for source_path in source_paths: + sources.append(f"{source_dir}/" + str(source_path.name)) + + return sources diff --git a/picosoc_verilog/design/software/main.c b/picosoc_verilog/design/software/main.c new file mode 100644 index 0000000..a52eab8 --- /dev/null +++ b/picosoc_verilog/design/software/main.c @@ -0,0 +1,259 @@ +/* + * PicoSoC - A simple example SoC using PicoRV32 + * + * Copyright (C) 2017 Claire Xenia Wolf + * Copyright (C) 2025 Myrtle Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +# define MEM_TOTAL 0x200 /* 2 KB */ + + +// a pointer to this is a null pointer, but the compiler does not +// know that because "sram" is a linker symbol from sections.lds. +extern uint32_t sram; + +#define reg_spictrl (*(volatile uint32_t*)0x02000000) +#define reg_uart_clkdiv (*(volatile uint32_t*)0x02000004) +#define reg_uart_data (*(volatile uint32_t*)0x02000008) +#define reg_leds (*(volatile uint32_t*)0x03000000) + +// -------------------------------------------------------- + +extern uint32_t flashio_worker_begin; +extern uint32_t flashio_worker_end; + +void flashio(uint8_t *data, int len, uint8_t wrencmd) +{ + uint32_t func[&flashio_worker_end - &flashio_worker_begin]; + + uint32_t *src_ptr = &flashio_worker_begin; + uint32_t *dst_ptr = func; + + while (src_ptr != &flashio_worker_end) + *(dst_ptr++) = *(src_ptr++); + + ((void(*)(uint8_t*, uint32_t, uint32_t))func)(data, len, wrencmd); +} + +void set_flash_qspi_flag() +{ + uint8_t buffer[8]; + + // Read Configuration Registers (RDCR1 35h) + buffer[0] = 0x35; + buffer[1] = 0x00; // rdata + flashio(buffer, 2, 0); + uint8_t sr2 = buffer[1]; + + // Write Enable Volatile (50h) + Write Status Register 2 (31h) + buffer[0] = 0x31; + buffer[1] = sr2 | 2; // Enable QSPI + flashio(buffer, 2, 0x50); +} + +void set_flash_mode_spi() +{ + reg_spictrl = (reg_spictrl & ~0x007f0000) | 0x00000000; +} + +void set_flash_mode_dual() +{ + reg_spictrl = (reg_spictrl & ~0x007f0000) | 0x00400000; +} + +void set_flash_mode_quad() +{ + reg_spictrl = (reg_spictrl & ~0x007f0000) | 0x00240000; +} + +void set_flash_mode_qddr() +{ + reg_spictrl = (reg_spictrl & ~0x007f0000) | 0x00670000; +} + +void enable_flash_crm() +{ + reg_spictrl |= 0x00100000; +} + +// -------------------------------------------------------- + +void putchar(char c) +{ + if (c == '\n') + putchar('\r'); + reg_uart_data = c; +} + +void print(const char *p) +{ + while (*p) + putchar(*(p++)); +} + +void print_hex(uint32_t v, int digits) +{ + for (int i = 7; i >= 0; i--) { + char c = "0123456789abcdef"[(v >> (4*i)) & 15]; + if (c == '0' && i >= digits) continue; + putchar(c); + digits = i; + } +} + +void print_dec(uint32_t v) +{ + if (v >= 1000) { + print(">=1000"); + return; + } + + if (v >= 900) { putchar('9'); v -= 900; } + else if (v >= 800) { putchar('8'); v -= 800; } + else if (v >= 700) { putchar('7'); v -= 700; } + else if (v >= 600) { putchar('6'); v -= 600; } + else if (v >= 500) { putchar('5'); v -= 500; } + else if (v >= 400) { putchar('4'); v -= 400; } + else if (v >= 300) { putchar('3'); v -= 300; } + else if (v >= 200) { putchar('2'); v -= 200; } + else if (v >= 100) { putchar('1'); v -= 100; } + + if (v >= 90) { putchar('9'); v -= 90; } + else if (v >= 80) { putchar('8'); v -= 80; } + else if (v >= 70) { putchar('7'); v -= 70; } + else if (v >= 60) { putchar('6'); v -= 60; } + else if (v >= 50) { putchar('5'); v -= 50; } + else if (v >= 40) { putchar('4'); v -= 40; } + else if (v >= 30) { putchar('3'); v -= 30; } + else if (v >= 20) { putchar('2'); v -= 20; } + else if (v >= 10) { putchar('1'); v -= 10; } + + if (v >= 9) { putchar('9'); v -= 9; } + else if (v >= 8) { putchar('8'); v -= 8; } + else if (v >= 7) { putchar('7'); v -= 7; } + else if (v >= 6) { putchar('6'); v -= 6; } + else if (v >= 5) { putchar('5'); v -= 5; } + else if (v >= 4) { putchar('4'); v -= 4; } + else if (v >= 3) { putchar('3'); v -= 3; } + else if (v >= 2) { putchar('2'); v -= 2; } + else if (v >= 1) { putchar('1'); v -= 1; } + else putchar('0'); +} + + +// -------------------------------------------------------- + +void cmd_read_flash_id() +{ + uint8_t buffer[17] = { 0x9F, /* zeros */ }; + flashio(buffer, 17, 0); + + for (int i = 1; i <= 16; i++) { + putchar(' '); + print_hex(buffer[i], 2); + } + putchar('\n'); +} + +uint8_t cmd_read_flash_reg(uint8_t cmd) +{ + uint8_t buffer[2] = {cmd, 0}; + flashio(buffer, 2, 0); + return buffer[1]; +} + +void print_reg_bit(int val, const char *name) +{ + for (int i = 0; i < 12; i++) { + if (*name == 0) + putchar(' '); + else + putchar(*(name++)); + } + + putchar(val ? '1' : '0'); + putchar('\n'); +} + +void cmd_read_flash_regs() +{ + putchar('\n'); + + uint8_t sr1 = cmd_read_flash_reg(0x05); + uint8_t sr2 = cmd_read_flash_reg(0x35); + uint8_t sr3 = cmd_read_flash_reg(0x15); + + print_reg_bit(sr1 & 0x01, "S0 (BUSY)"); + print_reg_bit(sr1 & 0x02, "S1 (WEL)"); + print_reg_bit(sr1 & 0x04, "S2 (BP0)"); + print_reg_bit(sr1 & 0x08, "S3 (BP1)"); + print_reg_bit(sr1 & 0x10, "S4 (BP2)"); + print_reg_bit(sr1 & 0x20, "S5 (TB)"); + print_reg_bit(sr1 & 0x40, "S6 (SEC)"); + print_reg_bit(sr1 & 0x80, "S7 (SRP)"); + putchar('\n'); + + print_reg_bit(sr2 & 0x01, "S8 (SRL)"); + print_reg_bit(sr2 & 0x02, "S9 (QE)"); + print_reg_bit(sr2 & 0x04, "S10 ----"); + print_reg_bit(sr2 & 0x08, "S11 (LB1)"); + print_reg_bit(sr2 & 0x10, "S12 (LB2)"); + print_reg_bit(sr2 & 0x20, "S13 (LB3)"); + print_reg_bit(sr2 & 0x40, "S14 (CMP)"); + print_reg_bit(sr2 & 0x80, "S15 (SUS)"); + putchar('\n'); + + print_reg_bit(sr3 & 0x01, "S16 ----"); + print_reg_bit(sr3 & 0x02, "S17 ----"); + print_reg_bit(sr3 & 0x04, "S18 (WPS)"); + print_reg_bit(sr3 & 0x08, "S19 ----"); + print_reg_bit(sr3 & 0x10, "S20 ----"); + print_reg_bit(sr3 & 0x20, "S21 (DRV0)"); + print_reg_bit(sr3 & 0x40, "S22 (DRV1)"); + print_reg_bit(sr3 & 0x80, "S23 (HOLD)"); + putchar('\n'); +} + +// -------------------------------------------------------- + +void main() +{ + reg_leds = 31; + reg_uart_clkdiv = 217; + print("Booting..\n"); + + reg_leds = 63; + set_flash_qspi_flag(); + + reg_leds = 127; + + set_flash_mode_quad(); + + reg_leds = 85; + + print("\n"); + print(" ____ _ ____ ____\n"); + print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n"); + print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n"); + print(" | __/| | (_| (_) |__) | (_) | |___\n"); + print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n"); + print("\n"); + + while (1) {}; +} diff --git a/picosoc_verilog/design/software/sections.lds b/picosoc_verilog/design/software/sections.lds new file mode 100644 index 0000000..699b451 --- /dev/null +++ b/picosoc_verilog/design/software/sections.lds @@ -0,0 +1,63 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00100000, LENGTH = 0x400000 /* entire flash, 4 MiB */ + RAM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x200 +} + +SECTIONS { + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.srodata) /* .rodata sections (constants, strings, etc.) */ + *(.srodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + _sidata = _etext; /* This is used by the startup in order to initialize the .data secion */ + } >FLASH + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + _ram_start = .; /* create a global symbol at ram start for garbage collector */ + . = ALIGN(4); + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.sdata) /* .sdata sections */ + *(.sdata*) /* .sdata* sections */ + . = ALIGN(4); + _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(.sbss) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end; used by startup code */ + } >RAM + + /* this is to define the start of the heap, and make sure we have a minimum size */ + .heap : + { + . = ALIGN(4); + _heap_start = .; /* define a global symbol at heap start */ + } >RAM +} diff --git a/picosoc_verilog/design/software/start.s b/picosoc_verilog/design/software/start.s new file mode 100644 index 0000000..7ef8ee0 --- /dev/null +++ b/picosoc_verilog/design/software/start.s @@ -0,0 +1,162 @@ +.section .text + +start: +.globl start +_start: +.globl _start + +# zero-initialize register file +addi x1, zero, 0 +# x2 (sp) is initialized by reset +addi x3, zero, 0 +addi x4, zero, 0 +addi x5, zero, 0 +addi x6, zero, 0 +addi x7, zero, 0 +addi x8, zero, 0 +addi x9, zero, 0 +addi x10, zero, 0 +addi x11, zero, 0 +addi x12, zero, 0 +addi x13, zero, 0 +addi x14, zero, 0 +addi x15, zero, 0 +addi x16, zero, 0 +addi x17, zero, 0 +addi x18, zero, 0 +addi x19, zero, 0 +addi x20, zero, 0 +addi x21, zero, 0 +addi x22, zero, 0 +addi x23, zero, 0 +addi x24, zero, 0 +addi x25, zero, 0 +addi x26, zero, 0 +addi x27, zero, 0 +addi x28, zero, 0 +addi x29, zero, 0 +addi x30, zero, 0 +addi x31, zero, 0 + +# Update LEDs +li a0, 0x03000000 +li a1, 1 +sw a1, 0(a0) + +# zero initialize entire scratchpad memory +li a0, 0x00000000 +setmemloop: +sw a0, 0(a0) +addi a0, a0, 4 +blt a0, sp, setmemloop + +# Update LEDs +li a0, 0x03000000 +li a1, 3 +sw a1, 0(a0) + +# copy data section +la a0, _sidata +la a1, _sdata +la a2, _edata +bge a1, a2, end_init_data +loop_init_data: +lw a3, 0(a0) +sw a3, 0(a1) +addi a0, a0, 4 +addi a1, a1, 4 +blt a1, a2, loop_init_data +end_init_data: + +# Update LEDs +li a0, 0x03000000 +li a1, 7 +sw a1, 0(a0) + +# zero-init bss section +la a0, _sbss +la a1, _ebss +bge a0, a1, end_init_bss +loop_init_bss: +sw zero, 0(a0) +addi a0, a0, 4 +blt a0, a1, loop_init_bss +end_init_bss: + +# Update LEDs +li a0, 0x03000000 +li a1, 15 +sw a1, 0(a0) + +# call main +call main +loop: +j loop + +.global flashio_worker_begin +.global flashio_worker_end + +.balign 4 + +flashio_worker_begin: +# a0 ... data pointer +# a1 ... data length +# a2 ... optional WREN cmd (0 = disable) + +# address of SPI ctrl reg +li t0, 0x02000000 + +# Set CS high, IO0 is output +li t1, 0x120 +sh t1, 0(t0) + +# Enable Manual SPI Ctrl +sb zero, 3(t0) + +# Send optional WREN cmd +beqz a2, flashio_worker_L1 +li t5, 8 +andi t2, a2, 0xff +flashio_worker_L4: +srli t4, t2, 7 +sb t4, 0(t0) +ori t4, t4, 0x10 +sb t4, 0(t0) +slli t2, t2, 1 +andi t2, t2, 0xff +addi t5, t5, -1 +bnez t5, flashio_worker_L4 +sb t1, 0(t0) + +# SPI transfer +flashio_worker_L1: +beqz a1, flashio_worker_L3 +li t5, 8 +lbu t2, 0(a0) +flashio_worker_L2: +srli t4, t2, 7 +sb t4, 0(t0) +ori t4, t4, 0x10 +sb t4, 0(t0) +lbu t4, 0(t0) +andi t4, t4, 2 +srli t4, t4, 1 +slli t2, t2, 1 +or t2, t2, t4 +andi t2, t2, 0xff +addi t5, t5, -1 +bnez t5, flashio_worker_L2 +sb t2, 0(a0) +addi a0, a0, 1 +addi a1, a1, -1 +j flashio_worker_L1 +flashio_worker_L3: + +# Back to MEMIO mode +li t1, 0x80 +sb t1, 3(t0) + +ret + +.balign 4 +flashio_worker_end: diff --git a/picosoc_verilog/design/steps/_init_.py b/picosoc_verilog/design/steps/_init_.py new file mode 100644 index 0000000..e69de29 diff --git a/picosoc_verilog/design/steps/software.py b/picosoc_verilog/design/steps/software.py new file mode 100644 index 0000000..bca0151 --- /dev/null +++ b/picosoc_verilog/design/steps/software.py @@ -0,0 +1,26 @@ +from ..software import doit_build + +from doit.cmd_base import ModuleTaskLoader +from doit.doit_cmd import DoitMain + +class MySoftwareStep(): + """Custom step to build the software.""" + + doit_build_module = doit_build + + def __init__(self, config): + pass + + def build_cli_parser(self, parser): + pass + + def run_cli(self, args): + self.build() + + def doit_build(self): + "Run the overridden doit_build_module" + DoitMain(ModuleTaskLoader(self.doit_build_module)).run(["build_software"]) + + def build(self): + "Build the software for your design" + self.doit_build() diff --git a/picosoc_verilog/design/tests/events_reference.json b/picosoc_verilog/design/tests/events_reference.json new file mode 100644 index 0000000..d9cd9f0 --- /dev/null +++ b/picosoc_verilog/design/tests/events_reference.json @@ -0,0 +1,217 @@ +{ +"events": [ +{ "timestamp": 0, "peripheral": "gpio_0", "event": "change", "payload": "00000000" }, +{ "timestamp": 4570, "peripheral": "gpio_0", "event": "change", "payload": "00000001" }, +{ "timestamp": 171216, "peripheral": "gpio_0", "event": "change", "payload": "00000011" }, +{ "timestamp": 172762, "peripheral": "gpio_0", "event": "change", "payload": "00000111" }, +{ "timestamp": 174052, "peripheral": "gpio_0", "event": "change", "payload": "00001111" }, +{ "timestamp": 175478, "peripheral": "gpio_0", "event": "change", "payload": "00011111" }, +{ "timestamp": 187732, "peripheral": "uart_0", "event": "tx", "payload": 66 }, +{ "timestamp": 195416, "peripheral": "uart_0", "event": "tx", "payload": 111 }, +{ "timestamp": 203100, "peripheral": "uart_0", "event": "tx", "payload": 111 }, +{ "timestamp": 210784, "peripheral": "uart_0", "event": "tx", "payload": 116 }, +{ "timestamp": 218468, "peripheral": "uart_0", "event": "tx", "payload": 105 }, +{ "timestamp": 226152, "peripheral": "uart_0", "event": "tx", "payload": 110 }, +{ "timestamp": 233836, "peripheral": "uart_0", "event": "tx", "payload": 103 }, +{ "timestamp": 241520, "peripheral": "uart_0", "event": "tx", "payload": 46 }, +{ "timestamp": 249204, "peripheral": "uart_0", "event": "tx", "payload": 46 }, +{ "timestamp": 258570, "peripheral": "uart_0", "event": "tx", "payload": 13 }, +{ "timestamp": 262730, "peripheral": "gpio_0", "event": "change", "payload": "00111111" }, +{ "timestamp": 262952, "peripheral": "uart_0", "event": "tx", "payload": 10 }, +{ "timestamp": 906576, "peripheral": "gpio_0", "event": "change", "payload": "01111111" }, +{ "timestamp": 909000, "peripheral": "gpio_0", "event": "change", "payload": "01010101" }, +{ "timestamp": 915816, "peripheral": "uart_0", "event": "tx", "payload": 13 }, +{ "timestamp": 920198, "peripheral": "uart_0", "event": "tx", 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"uart_0", "event": "tx", "payload": 95 }, +{ "timestamp": 1735250, "peripheral": "uart_0", "event": "tx", "payload": 95 }, +{ "timestamp": 1739632, "peripheral": "uart_0", "event": "tx", "payload": 124 }, +{ "timestamp": 1744014, "peripheral": "uart_0", "event": "tx", "payload": 13 }, +{ "timestamp": 1748396, "peripheral": "uart_0", "event": "tx", "payload": 10 }, +{ "timestamp": 1752778, "peripheral": "uart_0", "event": "tx", "payload": 13 }, +{ "timestamp": 1757160, "peripheral": "uart_0", "event": "tx", "payload": 10 } +] +} diff --git a/picosoc_verilog/design/tests/input.json b/picosoc_verilog/design/tests/input.json new file mode 100644 index 0000000..f0d9a0b --- /dev/null +++ b/picosoc_verilog/design/tests/input.json @@ -0,0 +1,4 @@ +{ + "commands": [ + ] +}