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Pipelined VGA text/character generator controller in Verilog
Easy-to-use JTAG TAP and Debug Controller core written in Verilog
TCP socket bootloader for the ESP32 over WPA2-Enterprise networks
Custom 50Mhz QAM/PSK ham radio for my rover project
RISC Architecture with In-order Superscalar INterlocked-pipeline - 64 Bits
in the last year
January - February 2019
ChrisPVille has no activity
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