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Pinned

  1. RL02-USB Interface

    Eagle 13 2

  2. Pipelined VGA text/character generator controller in Verilog

    Verilog 4

  3. Easy-to-use JTAG TAP and Debug Controller core written in Verilog

    Verilog 4 2

  4. TCP socket bootloader for the ESP32 over WPA2-Enterprise networks

    C 3

  5. RISC Architecture with In-order Superscalar INterlocked-pipeline - 64 Bits

    1

  6. Schematics for the Nintendo 64 Disk Drive (N64DD)

    10

53 contributions in the last year

May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Mon Wed Fri

Contribution activity

April - May 2021

ChrisPVille has no activity yet for this period.

March 2021

Created 6 commits in 1 repository
Created 1 repository

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