Skip to content
View ChrisPVille's full-sized avatar


Block or Report

Block or report ChrisPVille

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. aux-display aux-display Public

    CAD and Conky configs for a 1920x480 HSD088IPW1 Display

    Shell 21 3

  2. VGA-CharGen VGA-CharGen Public

    Pipelined VGA text/character generator controller in Verilog

    Verilog 8

  3. jtaglet jtaglet Public

    Easy-to-use JTAG TAP and Debug Controller core written in Verilog

    Verilog 14 7

  4. RL02 RL02 Public

    RL02-USB Interface

    Eagle 16 3

  5. 64dd-schematics 64dd-schematics Public

    Schematics for the Nintendo 64 Disk Drive (N64DD)


  6. mig_example mig_example Public

    Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer

    Verilog 25 6