Block or report user

Report or block ChrisPVille

Hide content and notifications from this user.

Contact Support about this user’s behavior.

Report abuse

Pinned repositories

  1. RL02

    RL02-USB Interface

    Eagle 11 2

  2. VGA-CharGen

    Pipelined VGA text/character generator controller in Verilog

    Verilog 2

  3. jtaglet

    Easy-to-use JTAG TAP and Debug Controller core written in Verilog

    Verilog

  4. esp32-tcp-boot

    TCP socket bootloader for the ESP32 over WPA2-Enterprise networks

    C 1

  5. RoverRadio

    Custom 50Mhz QAM/PSK ham radio for my rover project

    KiCad Layout

  6. raisin64

    RISC Architecture with In-order Superscalar INterlocked-pipeline - 64 Bits

130 contributions in 2018

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Mon Wed Fri

Contribution activity

January 2018

Seeing something unexpected? Take a look at the GitHub profile guide.