Join the platform over 31 million developers
call home for hosting code, managing projects, and building their best
Hide content and notifications from this user.
Learn more about blocking users
Contact Support about this user’s behavior.
Learn more about reporting abuse
Pipelined VGA text/character generator controller in Verilog
Easy-to-use JTAG TAP and Debug Controller core written in Verilog
TCP socket bootloader for the ESP32 over WPA2-Enterprise networks
Custom 50Mhz QAM/PSK ham radio for my rover project
RISC Architecture with In-order Superscalar INterlocked-pipeline - 64 Bits
Seeing something unexpected? Take a look at the
GitHub profile guide.