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Pinned

  1. RL02-USB Interface

    Eagle 11 2

  2. Pipelined VGA text/character generator controller in Verilog

    Verilog 2

  3. Easy-to-use JTAG TAP and Debug Controller core written in Verilog

    Verilog 1

  4. TCP socket bootloader for the ESP32 over WPA2-Enterprise networks

    C 2

  5. Custom 50Mhz QAM/PSK ham radio for my rover project

    KiCad Layout

  6. RISC Architecture with In-order Superscalar INterlocked-pipeline - 64 Bits

24 contributions in 2019

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Mon Wed Fri

Contribution activity

June - September 2019

ChrisPVille has no activity yet for this period.

May 2019

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