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  • Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer

    Verilog 1 1 Updated Feb 1, 2020
  • Machine configuration files for my OpenPnP based Pick and Place machine

    JavaScript The Unlicense Updated Dec 8, 2019
  • openpnp Archived

    Forked from openpnp/openpnp

    Open Source SMT Pick and Place Hardware and Software

    Java 285 GNU General Public License v3.0 Updated Oct 28, 2019
  • Verilog Updated Mar 28, 2019
  • Reference implementation of the Raisin64 on a Nexys 4 DDR board

    Verilog Apache License 2.0 Updated Mar 28, 2019
  • Fork of binutils-gdb for the Raisin64

    C Other Updated Mar 14, 2019
  • Source and build tree for the Raisin64 project documentation

    HTML Updated Dec 20, 2018
  • RISC Architecture with In-order Superscalar INterlocked-pipeline - 64 Bits

    1 Updated Dec 9, 2018
  • Pipelined VGA text/character generator controller in Verilog

    Verilog 4 Apache License 2.0 Updated Dec 8, 2018
  • OpenOCD port for the Raisin64

    C GNU General Public License v2.0 Updated Nov 27, 2018
  • Easy-to-use JTAG TAP and Debug Controller core written in Verilog

    Verilog 2 2 Apache License 2.0 Updated Nov 26, 2018
  • Updated Oct 7, 2018
  • HPLG filter for output devices

    C 1 BSD 2-Clause "Simplified" License Updated May 24, 2018
  • Quokka 6502 Microprocessor Trainer

    Verilog Apache License 2.0 Updated May 7, 2018
  • edtest

    Forked from ripark/edtest

    Example for COSC class demos

    1 Updated Oct 20, 2017
  • Python based incremental file backup using large archives for minimal cost AWS Glacier storage

    Python GNU General Public License v3.0 Updated Sep 4, 2017
  • TCP socket bootloader for the ESP32 over WPA2-Enterprise networks

    C 2 GNU Lesser General Public License v2.1 Updated Jul 17, 2017
  • Custom 50Mhz QAM/PSK ham radio for my rover project

    KiCad Layout GNU General Public License v3.0 Updated Sep 25, 2015
  • RL02-USB Interface

    Eagle 11 2 Other Updated May 7, 2015
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