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Read LTO/Ultrium cartridges' medium auxiliary memory attributes from a tape drive

C 2 Updated Sep 27, 2016

Retrieves your activation data (activation_bytes) from Audible servers. Using https://github.com/inAudible-NG/tables project instead is recommended.

Python 321 61 Updated Jun 18, 2018

Convert Audible's .aax filetype to MP3, FLAC, M4A, or OPUS

Shell 278 57 Updated Jul 26, 2018

A fast, extensible progress bar for Python and CLI

Python 7,079 353 Updated Aug 15, 2018

HPLG filter for output devices

C 1 1 Updated Sep 9, 2017

An implementation of DisplayPort protocol for FPGAs

VHDL 119 18 Updated May 19, 2016

hilite.me converts your code snippets into pretty-printed HTML format, easily embeddable into blog posts, emails and websites.

Python 181 51 Updated Aug 28, 2014

An attempt to implement EV Nova in the browser

JavaScript 8 2 Updated Aug 15, 2018

Improvements made to the cheap T-962 reflow oven utilizing the _existing_ controller HW

C 239 76 Updated Aug 4, 2018

Enhanced 6502/65C02 Microprogrammed Verilog Processor Core

Verilog 2 2 Updated May 27, 2018

An open source USB bootloader for FPGAs

AGS Script 70 10 Updated Aug 4, 2018

Text mode diagrams using UTF-8 characters and fancy colors

Python 330 16 Updated May 31, 2017

Small portable AES128/192/256 in C

C 1,113 471 Updated Jul 26, 2018

Gpredict satellite tracking application

C 197 69 Updated Jul 14, 2018

🍰 bit field diagram renderer

JavaScript 26 8 Updated Aug 12, 2018

Tool for partial deblobbing of Intel ME/TXE firmware images

Python 2,551 153 Updated May 24, 2018

Exploring tools for visualizing data with Python.

Jupyter Notebook 2 Updated Jun 5, 2018

A 32-bit RISC-V / MIPS ISA retargetable CPU core

VHDL 165 62 Updated Jul 13, 2018

Game engine agnostic robust messaging solution

C# 2 Updated Sep 15, 2017

MIPS assembler and IDE

Java 23 4 Updated Jul 22, 2015

Silicon proven Verilog library for IC and FPGA designers

Verilog 378 121 Updated Feb 5, 2018

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Verilog 113 23 Updated Jul 12, 2017

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Verilog 80 12 Updated Feb 19, 2016

Mirror of git://source.ffmpeg.org/ffmpeg.git

C 11,883 4,765 Updated Aug 16, 2018

N64 Bare Metal Mips Assembly Programming

C++ 107 19 Updated Aug 11, 2018

Digital timing diagram editor

JavaScript 164 26 Updated May 8, 2018

Implementation of divoom-aurabox

Python 41 7 Updated Mar 17, 2018

The GNU MCU Eclipse plug-ins for ARM & RISC-V C/C++ developers

C 355 65 Updated Aug 15, 2018

This is the source code for La CasaC project

HTML 6 1 Updated Aug 27, 2017

This is the official source code of FreeCAD, a free and opensource multiplatform 3D parametric modeler

C++ 2,754 1,046 Updated Aug 16, 2018