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acpuclock-7x30: Added overclocking and undervolting support
Thanks to CastagnaIT, Doomsday94 and Diablo96 for their sources
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Christopher83 committed Jun 12, 2014
1 parent 56458b6 commit 899d5a2
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Showing 2 changed files with 154 additions and 9 deletions.
29 changes: 29 additions & 0 deletions arch/arm/mach-msm/Kconfig
Expand Up @@ -1633,6 +1633,35 @@ config MSM_CPU_FREQ_MIN
depends on MSM_CPU_FREQ_SET_MIN_MAX
default 245760

choice
prompt "CPU Frequency Voltages"
depends on ARCH_MSM7X30
default MSM_CPU_FREQ_DEFAULT_V

config MSM_CPU_FREQ_DEFAULT_V
bool "Default CPU frequency voltages"
help
Enabling this option allow to use default CPU frequency voltages.

config MSM_CPU_FREQ_NORMAL_UV
bool "Normally undervolted CPU frequency voltages"
help
Enabling this option allow to use normally undervolted CPU frequency voltages.

config MSM_CPU_FREQ_EXTREME_UV
bool "Extremely undervolted CPU frequency voltages"
help
Enabling this option allow to use extremely undervolted CPU frequency voltages.

endchoice

config MSM_CPU_FREQ_OVERCLOCKING
bool "Enable support for CPU overclocking"
depends on ARCH_MSM7X30
default y
help
Enabling this option allow to use all overclock frequencies.

endif # CPU_FREQ_MSM

config MSM_AVS_HW
Expand Down
134 changes: 125 additions & 9 deletions arch/arm/mach-msm/acpuclock-7x30.c
Expand Up @@ -89,10 +89,23 @@ static struct clock_state drv_state = { 0 };
static struct clkctl_acpu_speed *backup_s;

static struct pll pll2_tbl[] = {
{ 42, 0, 1, 0 }, /* 806 MHz */
{ 53, 1, 3, 0 }, /* 1024 MHz */
{ 125, 0, 1, 1 }, /* 1200 MHz */
{ 73, 0, 1, 0 }, /* 1401 MHz */
{ 42, 0, 1, 0 }, /* 42 * 19,2MHz = 806,4 MHz */
{ 47, 1, 3, 0 }, /* 47 * 19,2MHz = 902,4 MHz */
{ 53, 1, 3, 0 }, /* 53 * 19,2MHz = 1017,6 MHz */
{ 58, 1, 3, 0 }, /* 58 * 19,2MHz = 1113,6 MHz */
{ 63, 1, 3, 0 }, /* 63 * 19,2MHz = 1209,6 MHz */
{ 68, 1, 3, 0 }, /* 68 * 19,2MHz = 1305,6 MHz */
{ 73, 0, 1, 0 }, /* 73 * 19,2MHz = 1401,6 MHz */
#ifdef CONFIG_MSM_CPU_FREQ_OVERCLOCKING
{ 79, 1, 3, 0 }, /* 79 * 19,2MHz = 1516,8 MHz */
{ 81, 1, 3, 0 }, /* 81 * 19,2MHz = 1555,2 MHz */
{ 84, 1, 3, 0 }, /* 84 * 19,2MHz = 1612,8 MHz */
{ 86, 1, 3, 0 }, /* 86 * 19,2MHz = 1651,2 MHz */
{ 89, 1, 3, 0 }, /* 89 * 19,2MHz = 1708,8 MHz */
{ 92, 1, 3, 0 }, /* 92 * 19,2MHz = 1766,4 MHz */
{ 94, 1, 3, 0 }, /* 94 * 19,2MHz = 1804,8 MHz */
{ 95, 1, 3, 0 }, /* 95 * 19,2MHz = 1824,0 MHz */
#endif
};

/* Use negative numbers for sources that can't be enabled/disabled */
Expand All @@ -115,6 +128,78 @@ static struct clk *acpuclk_sources[MAX_SOURCE];
* Do NOT change the AXI frequency unless you are _absoulutely_ sure you
* know all the h/w requirements.
*/
#ifdef CONFIG_MSM_CPU_FREQ_EXTREME_UV

static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 0, 24576, LPXO, 0, 0, 30720000, 750, VDD_RAW(750) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 750, VDD_RAW(750) },
{ 0, 122880, PLL_3, 5, 5, 61440000, 750, VDD_RAW(750) },
{ 0, 184320, PLL_3, 5, 4, 61440000, 750, VDD_RAW(750) },
{ 1, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 750, VDD_RAW(750) },
{ 1, 245760, PLL_3, 5, 2, 61440000, 750, VDD_RAW(750) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 800, VDD_RAW(800) },
/* AXI has MSMC1 implications. See above. */
{ 1, 768000, PLL_1, 2, 0, 153600000, 925, VDD_RAW(925) },
/*
* AXI has MSMC1 implications. See above.
*/
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 950, VDD_RAW(950), &pll2_tbl[0]},
{ 1, 902400, PLL_2, 3, 0, UINT_MAX, 975, VDD_RAW(975), &pll2_tbl[1]},
{ 1, 1017600, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000), &pll2_tbl[2]},
{ 1, 1113600, PLL_2, 3, 0, UINT_MAX, 1025, VDD_RAW(1025), &pll2_tbl[3]},
{ 1, 1209600, PLL_2, 3, 0, UINT_MAX, 1050, VDD_RAW(1050), &pll2_tbl[4]},
{ 1, 1305600, PLL_2, 3, 0, UINT_MAX, 1075, VDD_RAW(1075), &pll2_tbl[5]},
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &pll2_tbl[6]},
#ifdef CONFIG_MSM_CPU_FREQ_OVERCLOCKING
{ 1, 1516800, PLL_2, 3, 0, UINT_MAX, 1150, VDD_RAW(1150), &pll2_tbl[7]},
{ 1, 1555200, PLL_2, 3, 0, UINT_MAX, 1175, VDD_RAW(1175), &pll2_tbl[8]},
{ 1, 1612800, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[9]},
{ 1, 1651200, PLL_2, 3, 0, UINT_MAX, 1225, VDD_RAW(1225), &pll2_tbl[10]},
{ 1, 1708800, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[11]},
{ 1, 1766400, PLL_2, 3, 0, UINT_MAX, 1275, VDD_RAW(1275), &pll2_tbl[12]},
{ 1, 1804800, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1300), &pll2_tbl[13]},
{ 1, 1824000, PLL_2, 3, 0, UINT_MAX, 1325, VDD_RAW(1325), &pll2_tbl[14]},
#endif
{ 0 }
};

#elif defined(CONFIG_MSM_CPU_FREQ_NORMAL_UV)

static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 0, 24576, LPXO, 0, 0, 30720000, 800, VDD_RAW(800) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 800, VDD_RAW(800) },
{ 0, 122880, PLL_3, 5, 5, 61440000, 800, VDD_RAW(800) },
{ 0, 184320, PLL_3, 5, 4, 61440000, 800, VDD_RAW(800) },
{ 1, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 800, VDD_RAW(800) },
{ 1, 245760, PLL_3, 5, 2, 61440000, 800, VDD_RAW(800) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 850, VDD_RAW(850) },
/* AXI has MSMC1 implications. See above. */
{ 1, 768000, PLL_1, 2, 0, 153600000, 1000, VDD_RAW(1000) },
/*
* AXI has MSMC1 implications. See above.
*/
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 1025, VDD_RAW(1025), &pll2_tbl[0]},
{ 1, 902400, PLL_2, 3, 0, UINT_MAX, 1050, VDD_RAW(1050), &pll2_tbl[1]},
{ 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &pll2_tbl[1]},
{ 1, 1113600, PLL_2, 3, 0, UINT_MAX, 1125, VDD_RAW(1125), &pll2_tbl[2]},
{ 1, 1209600, PLL_2, 3, 0, UINT_MAX, 1150, VDD_RAW(1150), &pll2_tbl[3]},
{ 1, 1305600, PLL_2, 3, 0, UINT_MAX, 1175, VDD_RAW(1175), &pll2_tbl[4]},
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[5]},
#ifdef CONFIG_MSM_CPU_FREQ_OVERCLOCKING
{ 1, 1516800, PLL_2, 3, 0, UINT_MAX, 1225, VDD_RAW(1225), &pll2_tbl[6]},
{ 1, 1555200, PLL_2, 3, 0, UINT_MAX, 1225, VDD_RAW(1225), &pll2_tbl[8]},
{ 1, 1612800, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[9]},
{ 1, 1651200, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[10]},
{ 1, 1708800, PLL_2, 3, 0, UINT_MAX, 1275, VDD_RAW(1275), &pll2_tbl[11]},
{ 1, 1766400, PLL_2, 3, 0, UINT_MAX, 1275, VDD_RAW(1275), &pll2_tbl[12]},
{ 1, 1804800, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1300), &pll2_tbl[13]},
{ 1, 1824000, PLL_2, 3, 0, UINT_MAX, 1325, VDD_RAW(1325), &pll2_tbl[14]},
#endif
{ 0 }
};

#else

static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 0, 24576, LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
Expand All @@ -129,12 +214,27 @@ static struct clkctl_acpu_speed acpu_freq_tbl[] = {
* AXI has MSMC1 implications. See above.
*/
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &pll2_tbl[0]},
{ 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[1]},
{ 1, 1200000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[2]},
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[3]},
{ 1, 902400, PLL_2, 3, 0, UINT_MAX, 1125, VDD_RAW(1125), &pll2_tbl[1]},
{ 1, 1017600, PLL_2, 3, 0, UINT_MAX, 1175, VDD_RAW(1175), &pll2_tbl[2]},
{ 1, 1113600, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[3]},
{ 1, 1209600, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[4]},
{ 1, 1305600, PLL_2, 3, 0, UINT_MAX, 1225, VDD_RAW(1225), &pll2_tbl[5]},
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[6]},
#ifdef CONFIG_MSM_CPU_FREQ_OVERCLOCKING
{ 1, 1516800, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[7]},
{ 1, 1555200, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[8]},
{ 1, 1612800, PLL_2, 3, 0, UINT_MAX, 1275, VDD_RAW(1275), &pll2_tbl[9]},
{ 1, 1651200, PLL_2, 3, 0, UINT_MAX, 1275, VDD_RAW(1275), &pll2_tbl[10]},
{ 1, 1708800, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1300), &pll2_tbl[11]},
{ 1, 1766400, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1300), &pll2_tbl[12]},
{ 1, 1804800, PLL_2, 3, 0, UINT_MAX, 1325, VDD_RAW(1325), &pll2_tbl[13]},
{ 1, 1824000, PLL_2, 3, 0, UINT_MAX, 1325, VDD_RAW(1325), &pll2_tbl[14]},
#endif
{ 0 }
};

#endif

#define MAX_CLK 1401600
unsigned long acpuclk_usr_set_max(void)
{
Expand Down Expand Up @@ -201,8 +301,7 @@ static void acpuclk_set_src(const struct clkctl_acpu_speed *s)
mb();
}

static int acpuclk_7x30_set_rate(int cpu, unsigned long rate,
enum setrate_reason reason)
static int acpuclk_7x30_set_rate(int cpu, unsigned long rate, enum setrate_reason reason)
{
struct clkctl_acpu_speed *tgt_s, *strt_s;
int res, rc = 0;
Expand Down Expand Up @@ -328,6 +427,12 @@ static unsigned long acpuclk_7x30_get_rate(int cpu)
return 0;
}

unsigned long clk_get_max_axi_khz(void)
{
return MAX_AXI_KHZ;
}
EXPORT_SYMBOL(clk_get_max_axi_khz);

/*----------------------------------------------------------------------------
* Clock driver initialization
*---------------------------------------------------------------------------*/
Expand Down Expand Up @@ -451,11 +556,14 @@ static inline void setup_cpufreq_table(void) { }
void __devinit pll2_fixup(void)
{
struct clkctl_acpu_speed *speed = acpu_freq_tbl;

#ifndef CONFIG_MSM_CPU_FREQ_OVERCLOCKING
u8 pll2_l = readl_relaxed(PLL2_L_VAL_ADDR) & 0xFF;

for ( ; speed->acpu_clk_khz; speed++) {
if (speed->src != PLL_2)
backup_s = speed;

if (speed->pll_rate && speed->pll_rate->l == pll2_l) {
speed++;
speed->acpu_clk_khz = 0;
Expand All @@ -465,6 +573,12 @@ void __devinit pll2_fixup(void)

pr_err("Unknown PLL2 lval %d\n", pll2_l);
BUG();
#else
for ( ; speed->acpu_clk_khz; speed++) {
if (speed->src != PLL_2)
backup_s = speed;
}
#endif
}

#define RPM_BYPASS_MASK (1 << 3)
Expand Down Expand Up @@ -508,6 +622,8 @@ static int __devinit acpuclk_7x30_probe(struct platform_device *pdev)
setup_cpufreq_table();
acpuclk_register(&acpuclk_7x30_data);

pr_info("ACPU init done, clock rate is: %d KHz\n", drv_state.current_speed->acpu_clk_khz);

return 0;
}

Expand Down

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