diff --git a/drivers/vpp/aml_vpp.c b/drivers/vpp/aml_vpp.c index 01ca4f191f6..9d0aba78334 100644 --- a/drivers/vpp/aml_vpp.c +++ b/drivers/vpp/aml_vpp.c @@ -1155,6 +1155,36 @@ static void set_viu2_osd_matrix_rgb2yuv(bool on) } } +static void set_vpp_osd2_rgb2yuv(bool on) +{ + int *m = NULL; + + /* RGB -> 709 limit */ + m = RGB709_to_YUV709l_coeff; + + /* VPP WRAP OSD3 matrix */ + vpp_reg_write(VPP_OSD2_MATRIX_PRE_OFFSET0_1, + ((m[0] & 0xfff) << 16) | (m[1] & 0xfff)); + vpp_reg_write(VPP_OSD2_MATRIX_PRE_OFFSET2, + m[2] & 0xfff); + vpp_reg_write(VPP_OSD2_MATRIX_COEF00_01, + ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff)); + vpp_reg_write(VPP_OSD2_MATRIX_COEF02_10, + ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff)); + vpp_reg_write(VPP_OSD2_MATRIX_COEF11_12, + ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff)); + vpp_reg_write(VPP_OSD2_MATRIX_COEF20_21, + ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff)); + vpp_reg_write(VPP_OSD2_MATRIX_COEF22, + m[11] & 0x1fff); + vpp_reg_write(VPP_OSD2_MATRIX_OFFSET0_1, + ((m[18] & 0xfff) << 16) | (m[19] & 0xfff)); + vpp_reg_write(VPP_OSD2_MATRIX_OFFSET2, + m[20] & 0xfff); + vpp_reg_setb(VPP_OSD2_MATRIX_EN_CTRL, on, 0, 1); + VPP_PR("vpp osd2 matrix rgb2yuv..............\n"); +} + /* for txlx, set vpp default data path to u10 */ @@ -1554,17 +1584,28 @@ void vpp_init(void) set_vpp_bitdepth(); } else if (is_osd_high_version()) { /* osd1: rgb->yuv limit,osd2: rgb2yuv limit,osd3: rgb2yuv limit*/ + if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_TM2) { + /* tm2: osd out is yuv */ + set_osd1_rgb2yuv(1); + set_osd2_rgb2yuv(1); + set_osd3_rgb2yuv(1); + } else { + /* g12a ~ sm1: osd out is rgb */ + set_vpp_osd2_rgb2yuv(1); + } + #if 0 set_osd1_rgb2yuv(1); set_osd2_rgb2yuv(1); if ((get_cpu_id().family_id != MESON_CPU_MAJOR_ID_TL1)) set_osd3_rgb2yuv(1); - + #endif /* set vpp data path to u12 */ set_vpp_bitdepth(); - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)) + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) hdr_func(OSD1_HDR, HDR_BYPASS); } else { /* set dummy data default YUV black */ diff --git a/drivers/vpp/aml_vpp_reg.h b/drivers/vpp/aml_vpp_reg.h index b726ef976d0..23a6abc397b 100644 --- a/drivers/vpp/aml_vpp_reg.h +++ b/drivers/vpp/aml_vpp_reg.h @@ -383,6 +383,21 @@ #define VIU2_OSD1_MATRIX_EN_CTRL 0x1e7d #endif +#define VPP_OSD2_MATRIX_COEF00_01 0x3920 +#define VPP_OSD2_MATRIX_COEF02_10 0x3921 +#define VPP_OSD2_MATRIX_COEF11_12 0x3922 +#define VPP_OSD2_MATRIX_COEF20_21 0x3923 +#define VPP_OSD2_MATRIX_COEF22 0x3924 +#define VPP_OSD2_MATRIX_COEF13_14 0x3925 +#define VPP_OSD2_MATRIX_COEF23_24 0x3926 +#define VPP_OSD2_MATRIX_COEF15_25 0x3927 +#define VPP_OSD2_MATRIX_CLIP 0x3928 +#define VPP_OSD2_MATRIX_OFFSET0_1 0x3929 +#define VPP_OSD2_MATRIX_OFFSET2 0x392a +#define VPP_OSD2_MATRIX_PRE_OFFSET0_1 0x392b +#define VPP_OSD2_MATRIX_PRE_OFFSET2 0x392c +#define VPP_OSD2_MATRIX_EN_CTRL 0x392d + /*hdr2 register end*/ //#define GAMMA_CNTL_PORT 0x1400 diff --git a/drivers/vpp/hdr2.c b/drivers/vpp/hdr2.c index 2ce9b4c7282..55e8244010e 100644 --- a/drivers/vpp/hdr2.c +++ b/drivers/vpp/hdr2.c @@ -2,6 +2,7 @@ #include #include "hdr2.h" #include "aml_vpp_reg.h" +#include int cgain_lut0[65] = { 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, @@ -311,6 +312,8 @@ int rgb2yuvpre[3] = {0, 0, 0}; int rgb2yuvpos[3] = {64, 512, 512}; int yuv2rgbpre[3] = {-64, -512, -512}; int yuv2rgbpos[3] = {0, 0, 0}; +int bypass_pre[3] = {0, 0, 0}; +int bypass_pos[3] = {0, 0, 0}; int yuv2rgbmat[15] = { 1197, 0, 0, 1197, 1851, 0, 1197, 0, 1163, 1197, 2271, 0, 1197, 0, 2011}; @@ -522,7 +525,13 @@ void set_hdr_matrix( if (mtx_sel & HDR_IN_MTX) { for (i = 0; i < 15; i++) mtx[i] = hdr_mtx_param->mtx_in[i]; - vpp_reg_write(MATRIXI_EN_CTRL, hdr_mtx_param->mtx_on); + + if ((hdr_mtx_param->mtx_only == MTX_ONLY) && + (!hdr_mtx_param->mtx_on)) + vpp_reg_write(MATRIXI_EN_CTRL, 1); + else + vpp_reg_write(MATRIXI_EN_CTRL, + hdr_mtx_param->mtx_on); /*yuv in*/ vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_on, 4, 1); @@ -543,13 +552,15 @@ void set_hdr_matrix( vpp_reg_write(MATRIXI_COEF22, mtx[2 * 3 + 2]); vpp_reg_write(MATRIXI_OFFSET0_1, - (yuv2rgbpos[0] << 16) | (yuv2rgbpos[1] & 0xFFF)); + (hdr_mtx_param->mtxi_pos_offset[0] << 16) | + (hdr_mtx_param->mtxi_pos_offset[1] & 0xFFF)); vpp_reg_write(MATRIXI_OFFSET2, - yuv2rgbpos[2]); + hdr_mtx_param->mtxi_pos_offset[2]); vpp_reg_write(MATRIXI_PRE_OFFSET0_1, - (yuv2rgbpre[0] << 16)|(yuv2rgbpre[1] & 0xFFF)); + (hdr_mtx_param->mtxi_pre_offset[0] << 16) | + (hdr_mtx_param->mtxi_pre_offset[1] & 0xFFF)); vpp_reg_write(MATRIXI_PRE_OFFSET2, - yuv2rgbpre[2]); + hdr_mtx_param->mtxi_pre_offset[2]); } else if (mtx_sel & HDR_GAMUT_MTX) { for (i = 0; i < 9; i++) @@ -684,13 +695,15 @@ void set_hdr_matrix( vpp_reg_write(MATRIXO_COEF22, mtx[2 * 3 + 2]); vpp_reg_write(MATRIXO_OFFSET0_1, - (rgb2yuvpos[0] << 16) | (rgb2yuvpos[1]&0xFFF)); + (hdr_mtx_param->mtxo_pos_offset[0] << 16) | + (hdr_mtx_param->mtxo_pos_offset[1]&0xFFF)); vpp_reg_write(MATRIXO_OFFSET2, - rgb2yuvpos[2]); + hdr_mtx_param->mtxo_pos_offset[2]); vpp_reg_write(MATRIXO_PRE_OFFSET0_1, - (rgb2yuvpre[0] << 16)|(rgb2yuvpre[1]&0xFFF)); + (hdr_mtx_param->mtxo_pre_offset[0] << 16) | + (hdr_mtx_param->mtxo_pre_offset[1]&0xFFF)); vpp_reg_write(MATRIXO_PRE_OFFSET2, - rgb2yuvpre[2]); + hdr_mtx_param->mtxo_pre_offset[2]); } } @@ -862,7 +875,6 @@ void hdr_func(enum hdr_module_sel module_sel, bit_depth = 10; else return; - /*lut parameters*/ if (hdr_process_select & HDR_BYPASS) { /*for g12a/g12b osd blend shift rtl bug*/ @@ -992,20 +1004,58 @@ void hdr_func(enum hdr_module_sel module_sel, hdr_mtx_param.mtx_only = HDR_ONLY; /*for g12a/g12b osd blend shift rtl bug*/ if (((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)) && + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B && + get_cpu_id().chip_rev == MESON_CPU_CHIP_REVISION_A)) && (hdr_process_select & HDR_BYPASS) && (module_sel & OSD1_HDR)) { for (i = 0; i < 15; i++) { - hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i]; + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i]; hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i]; hdr_mtx_param.mtx_out[i] = rgb2ycbcr_709[i]; if (i < 9) hdr_mtx_param.mtx_gamut[i] = bypass_coeff[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } } hdr_mtx_param.mtx_on = MTX_ON; hdr_mtx_param.p_sel = HDR_BYPASS; + } else if (((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B && + get_cpu_id().chip_rev == MESON_CPU_CHIP_REVISION_B)) && + (module_sel & OSD1_HDR)) { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_out[i] = bypass_coeff[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + bypass_coeff[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + rgb2yuvpos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + bypass_pos[i]; + } + } + hdr_mtx_param.mtx_on = MTX_OFF; + hdr_mtx_param.p_sel = HDR_BYPASS; + hdr_mtx_param.mtx_only = MTX_ONLY; } else { for (i = 0; i < 15; i++) { hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; @@ -1015,6 +1065,16 @@ void hdr_func(enum hdr_module_sel module_sel, if (i < 9) hdr_mtx_param.mtx_gamut[i] = bypass_coeff[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + bypass_pos[i]; + } } hdr_mtx_param.mtx_on = MTX_OFF; hdr_mtx_param.p_sel = HDR_BYPASS; @@ -1028,6 +1088,16 @@ void hdr_func(enum hdr_module_sel module_sel, hdr_mtx_param.mtx_out[i] = rgb2ycbcr_709[i]; if (i < 9) hdr_mtx_param.mtx_gamut[i] = ncl_2020_709[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + yuv2rgbpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + yuv2rgbpos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } } hdr_mtx_param.mtx_on = MTX_ON; @@ -1038,13 +1108,52 @@ void hdr_func(enum hdr_module_sel module_sel, } else if (hdr_process_select & SDR_HDR) { hdr_mtx_param.mtx_only = HDR_ONLY; - for (i = 0; i < 15; i++) { - hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i]; - hdr_mtx_param.mtx_cgain[i] = rgb2ycbcr_ncl2020[i]; - hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; - hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; - if (i < 9) - hdr_mtx_param.mtx_gamut[i] = ncl_709_2020[i]; + if (((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A)) && + (module_sel & OSD1_HDR)) { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_cgain[i] = + rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + ncl_709_2020[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_coeff[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_coeff[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } + } else { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i]; + hdr_mtx_param.mtx_cgain[i] = + rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + ncl_709_2020[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + yuv2rgbpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + yuv2rgbpos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } } hdr_mtx_param.mtx_on = MTX_ON; hdr_mtx_param.p_sel = SDR_HDR; @@ -1062,13 +1171,52 @@ void hdr_func(enum hdr_module_sel module_sel, hdr_mtx_param.p_sel = HLG_HDR; } else if (hdr_process_select & SDR_HLG) { hdr_mtx_param.mtx_only = HDR_ONLY; - for (i = 0; i < 15; i++) { - hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i]; - hdr_mtx_param.mtx_cgain[i] = rgb2ycbcr_ncl2020[i]; - hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; - hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; - if (i < 9) - hdr_mtx_param.mtx_gamut[i] = ncl_709_2020[i]; + if (((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A)) && + (module_sel & OSD1_HDR)) { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_cgain[i] = + rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + ncl_709_2020[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } + } else { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i]; + hdr_mtx_param.mtx_cgain[i] = + rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + ncl_709_2020[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + yuv2rgbpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + yuv2rgbpos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } } hdr_mtx_param.mtx_on = MTX_ON; hdr_mtx_param.p_sel = SDR_HLG; diff --git a/drivers/vpp/hdr2.h b/drivers/vpp/hdr2.h index 7b5d32a9ff6..9d5ced8f6da 100644 --- a/drivers/vpp/hdr2.h +++ b/drivers/vpp/hdr2.h @@ -60,6 +60,10 @@ struct hdr_proc_mtx_param_s { int mtx_cgain[15]; int mtx_ogain[15]; int mtx_out[15]; + int mtxi_pre_offset[3]; + int mtxi_pos_offset[3]; + int mtxo_pre_offset[3]; + int mtxo_pos_offset[3]; unsigned int mtx_on; enum hdr_process_sel p_sel; };