From 82b600a846e84fd45c6be075b07f889be0990e0c Mon Sep 17 00:00:00 2001
From: Dimitri Papadopoulos
 <3234522+DimitriPapadopoulos@users.noreply.github.com>
Date: Thu, 8 Sep 2022 23:01:03 +0200
Subject: [PATCH] Fix typos found by codespell

---
 cli/xxhsum.c | 2 +-
 xxhash.h     | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/cli/xxhsum.c b/cli/xxhsum.c
index 99fc5ae5..0744669c 100644
--- a/cli/xxhsum.c
+++ b/cli/xxhsum.c
@@ -699,7 +699,7 @@ static ParseLineResult XSUM_parseLine1(ParsedLine* parsedLine, char* line, int r
         if (hash_len==32) parsedLine->algo = algo_xxh128;
     }
 
-    /* Check current CLI accpets the algorithm or not */
+    /* Check current CLI accepts the algorithm or not */
     if(! XSUM_algoBitmask_Accepts(algoBitmask, parsedLine->algo)) {
         return ParseLine_invalidFormat;
     }
diff --git a/xxhash.h b/xxhash.h
index 9338f04b..7c838a5a 100644
--- a/xxhash.h
+++ b/xxhash.h
@@ -3136,7 +3136,7 @@ enum XXH_VECTOR_TYPE /* fake enum */ {
  * @ingroup tuning
  * @brief Selects the minimum alignment for XXH3's accumulators.
  *
- * When using SIMD, this should match the alignment reqired for said vector
+ * When using SIMD, this should match the alignment required for said vector
  * type, so, for example, 32 for AVX2.
  *
  * Default: Auto detected.
@@ -3378,7 +3378,7 @@ XXH_FORCE_INLINE uint64x2_t XXH_vld1q_u64(void const* ptr)
  * have more than 2 NEON (F0/F1) micro-ops. If you are only using NEON instructions,
  * you are only using 2/3 of the CPU bandwidth.
  *
- * This is even more noticable on the more advanced cores like the A76 which
+ * This is even more noticeable on the more advanced cores like the A76 which
  * can dispatch 8 micro-ops per cycle, but still only 2 NEON micro-ops at once.
  *
  * Therefore, @ref XXH3_NEON_LANES lanes will be processed using NEON, and the