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Merge commit 'M76XXTSNCJNLYA6140' into 7x27_common-2.6.35

Conflicts:
	drivers/mmc/host/msm_sdcc.c

Change-Id: Id11335f4a6875ccd34f4a1c8d0ae7477c26b120e
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2 parents b18cfd2 + 1dfb38a commit 1b4507461ece67188addb88091c0b154527b9840 Jinkyu Choi committed
Showing with 5,199 additions and 2,263 deletions.
  1. +4 −0 arch/arm/Kconfig
  2. +1 −1 arch/arm/configs/msm7627-perf_defconfig
  3. +1 −1 arch/arm/configs/msm7627_defconfig
  4. +3 −1 arch/arm/configs/msm7630-perf_defconfig
  5. +2 −1 arch/arm/configs/msm7630_defconfig
  6. +7 −3 arch/arm/configs/msm8660-perf_defconfig
  7. +6 −2 arch/arm/configs/msm8660_defconfig
  8. +1 −1 arch/arm/configs/qsd8650-perf_defconfig
  9. +1 −1 arch/arm/configs/qsd8650_defconfig
  10. +1 −1 arch/arm/configs/qsd8650a-perf_defconfig
  11. +1 −1 arch/arm/configs/qsd8650a_defconfig
  12. +1 −0 arch/arm/include/asm/mach/mmc.h
  13. +4 −0 arch/arm/include/asm/mmu.h
  14. +120 −0 arch/arm/include/asm/sched_clock.h
  15. +1 −0 arch/arm/kernel/Makefile
  16. +74 −0 arch/arm/kernel/sched_clock.c
  17. +6 −3 arch/arm/kernel/stacktrace.c
  18. +4 −0 arch/arm/kernel/time.c
  19. +1 −1 arch/arm/mach-msm/Makefile
  20. +47 −72 arch/arm/mach-msm/acpuclock-8x60.c
  21. +0 −4 arch/arm/mach-msm/board-msm7x27.c
  22. +102 −54 arch/arm/mach-msm/board-msm7x30.c
  23. +291 −69 arch/arm/mach-msm/board-msm8x60.c
  24. +23 −24 arch/arm/mach-msm/board-qrdc.c
  25. +0 −4 arch/arm/mach-msm/board-qsd8x50.c
  26. +0 −4 arch/arm/mach-msm/board-qsd8x50a-st1x.c
  27. +436 −281 arch/arm/mach-msm/clock-7x30.c
  28. +1,191 −644 arch/arm/mach-msm/clock-8x60.c
  29. +3 −6 arch/arm/mach-msm/clock-8x60.h
  30. +0 −53 arch/arm/mach-msm/clock-8x60_mxo.c
  31. +42 −11 arch/arm/mach-msm/clock-debug.c
  32. +40 −34 arch/arm/mach-msm/clock-local.c
  33. +12 −9 arch/arm/mach-msm/clock-local.h
  34. +0 −8 arch/arm/mach-msm/clock-pcom.c
  35. +0 −7 arch/arm/mach-msm/clock-rpm.c
  36. +0 −7 arch/arm/mach-msm/clock-voter.c
  37. +1 −1 arch/arm/mach-msm/clock.c
  38. +17 −10 arch/arm/mach-msm/clock.h
  39. +13 −17 arch/arm/mach-msm/devices-msm8x60.c
  40. +0 −2 arch/arm/mach-msm/gpio-v2.c
  41. +25 −18 arch/arm/mach-msm/include/mach/camera.h
  42. +0 −1 arch/arm/mach-msm/include/mach/qdsp6v2/q6asm.h
  43. +28 −48 arch/arm/mach-msm/mpm.c
  44. +3 −2 arch/arm/mach-msm/mpm.h
  45. +80 −25 arch/arm/mach-msm/msm_watchdog.c
  46. +3 −0 arch/arm/mach-msm/pm-8x60.c
  47. +2 −0 arch/arm/mach-msm/pm.c
  48. +2 −0 arch/arm/mach-msm/pm2.c
  49. +5 −0 arch/arm/mach-msm/qdsp5v2/audpreproc.c
  50. +2 −2 arch/arm/mach-msm/qdsp5v2/snddev_data_timpani.c
  51. +24 −55 arch/arm/mach-msm/qdsp5v2/timpani_profile_7x30.h
  52. +7 −1 arch/arm/mach-msm/qdsp5v2/voice.c
  53. +1 −1 arch/arm/mach-msm/qdsp6v2/apr.c
  54. +2 −2 arch/arm/mach-msm/qdsp6v2/audio_lpa.c
  55. +14 −8 arch/arm/mach-msm/qdsp6v2/pcm_in.c
  56. +2 −2 arch/arm/mach-msm/qdsp6v2/q6adm.c
  57. +1 −1 arch/arm/mach-msm/qdsp6v2/q6afe.c
  58. +4 −10 arch/arm/mach-msm/qdsp6v2/q6asm.c
  59. +1 −1 arch/arm/mach-msm/restart.c
  60. +39 −20 arch/arm/mach-msm/rpm_resources.c
  61. +22 −30 arch/arm/mach-msm/timer.c
  62. +5 −0 arch/s390/include/asm/mmu.h
  63. +0 −4 arch/s390/mm/vmem.c
  64. +31 −6 drivers/cpufreq/cpufreq.c
  65. +2 −2 drivers/crypto/msm/inc/qce.h
  66. +4 −1 drivers/crypto/msm/inc/qcedev.h
  67. +10 −12 drivers/crypto/msm/qce.c
  68. +59 −38 drivers/crypto/msm/qcedev.c
  69. +870 −123 drivers/crypto/msm/qcrypto.c
  70. +0 −9 drivers/gpu/msm/Kconfig
  71. +199 −116 drivers/gpu/msm/kgsl.c
  72. +14 −11 drivers/gpu/msm/kgsl.h
  73. +28 −6 drivers/gpu/msm/kgsl_device.h
  74. +42 −69 drivers/gpu/msm/kgsl_drawctxt.c
  75. +9 −7 drivers/gpu/msm/kgsl_drawctxt.h
  76. +1 −1 drivers/gpu/msm/kgsl_drm.c
  77. +0 −2 drivers/gpu/msm/kgsl_g12.h
  78. +5 −5 drivers/gpu/msm/kgsl_g12_cmdstream.c
  79. +2 −1 drivers/gpu/msm/kgsl_g12_cmdstream.h
  80. +9 −35 drivers/gpu/msm/kgsl_g12_drawctxt.c
  81. +3 −2 drivers/gpu/msm/kgsl_g12_drawctxt.h
  82. +12 −63 drivers/gpu/msm/kgsl_mmu.c
  83. +52 −0 drivers/gpu/msm/kgsl_pwrctrl.c
  84. +6 −1 drivers/gpu/msm/kgsl_pwrctrl.h
  85. +7 −8 drivers/gpu/msm/kgsl_ringbuffer.c
  86. +1 −1 drivers/gpu/msm/kgsl_ringbuffer.h
  87. +28 −6 drivers/gpu/msm/kgsl_yamato.c
  88. +1 −3 drivers/gpu/msm/kgsl_yamato.h
  89. +56 −5 drivers/input/misc/pmic8058-othc.c
  90. +6 −0 drivers/media/radio/radio-tavarua.c
  91. +4 −6 drivers/media/video/msm/imx074.c
  92. +53 −29 drivers/media/video/msm/msm_camera.c
  93. +25 −5 drivers/media/video/msm/mt9p012_fox.c
  94. +4 −0 drivers/mfd/marimba-core.c
  95. +1 −1 drivers/misc/pmic8058-xoadc.c
  96. +60 −31 drivers/mmc/host/msm_sdcc.c
  97. +1 −1 drivers/net/wireless/libra/qcomwlan_pwrif.c
  98. +1 −0 drivers/power/isl9519q.c
  99. +65 −46 drivers/power/pmic8058-charger.c
  100. +53 −14 drivers/serial/msm_serial_hs.c
  101. +3 −3 drivers/usb/gadget/composite.c
  102. +10 −0 drivers/usb/otg/msm72k_otg.c
  103. +34 −1 drivers/video/Kconfig
  104. +1 −0 drivers/video/msm/Makefile
  105. +620 −0 drivers/video/msm/lcdc_samsung_oled_pt.c
  106. +1 −1 drivers/video/msm/lcdc_samsung_wsvga.c
  107. +16 −5 drivers/video/msm/mdp4.h
  108. +61 −18 drivers/video/msm/mdp4_overlay.c
Sorry, we could not display the entire diff because it was too big.
View
4 arch/arm/Kconfig
@@ -38,6 +38,9 @@ config HAVE_PWM
config SYS_SUPPORTS_APM_EMULATION
bool
+config HAVE_SCHED_CLOCK
+ bool
+
config GENERIC_GPIO
bool
@@ -592,6 +595,7 @@ config ARCH_MSM
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_HAS_BARRIERS
select COMMON_CLKDEV
+ select HAVE_SCHED_CLOCK
help
Support for Qualcomm MSM/QSD based systems. This runs on the
ARM11/Scorpion apps processor of the MSM/QSD and depends on a
View
2 arch/arm/configs/msm7627-perf_defconfig
@@ -74,7 +74,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
View
2 arch/arm/configs/msm7627_defconfig
@@ -74,7 +74,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
View
4 arch/arm/configs/msm7630-perf_defconfig
@@ -74,7 +74,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
@@ -1968,6 +1968,8 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
# CONFIG_USB_DEVICEFS is not set
CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_MON is not set
View
3 arch/arm/configs/msm7630_defconfig
@@ -74,7 +74,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
@@ -1818,6 +1818,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
# CONFIG_USB_DEVICEFS is not set
CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_MON is not set
View
10 arch/arm/configs/msm8660-perf_defconfig
@@ -76,7 +76,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
@@ -342,7 +342,7 @@ CONFIG_MSM_SMD_TTY=y
# CONFIG_MSM_SMD_QMI is not set
CONFIG_MSM_SMD_PKT=y
CONFIG_MSM_SDIO_CMUX=y
-CONFIG_MSM_DSPS=y
+# CONFIG_MSM_DSPS is not set
CONFIG_MSM_SDIO_CTL=y
CONFIG_MSM_ONCRPCROUTER=y
CONFIG_MSM_ONCRPCROUTER_DEBUG=y
@@ -373,7 +373,7 @@ CONFIG_MSM_PM_TIMEOUT_HALT=y
# CONFIG_MSM_PM_TIMEOUT_RESET_CHIP is not set
CONFIG_MSM_IDLE_WAIT_ON_MODEM=0
CONFIG_MSM_PIL=y
-# CONFIG_MSM_SECURE_PIL is not set
+CONFIG_MSM_SECURE_PIL=y
CONFIG_MSM_SCM=y
CONFIG_MSM_RPM_LOG=y
# CONFIG_SMMU is not set
@@ -1847,6 +1847,7 @@ CONFIG_FB_MSM_DTV=y
# CONFIG_FB_MSM_MDDI_ORISE is not set
# CONFIG_FB_MSM_MDDI_QUICKVX is not set
# CONFIG_FB_MSM_MDDI_AUTO_DETECT is not set
+CONFIG_FB_MSM_LCDC_AUTO_DETECT=y
CONFIG_FB_MSM_LCDC_PANEL=y
# CONFIG_FB_MSM_MIPI_DSI_TOSHIBA is not set
# CONFIG_FB_MSM_MIPI_DSI_NOVATEK is not set
@@ -1859,6 +1860,7 @@ CONFIG_FB_MSM_LCDC_SAMSUNG_WSVGA=y
# CONFIG_FB_MSM_LCDC_GORDON_VGA is not set
# CONFIG_FB_MSM_LCDC_TOSHIBA_WVGA_PT is not set
# CONFIG_FB_MSM_LCDC_SHARP_WVGA_PT is not set
+CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT=y
# CONFIG_FB_MSM_LCDC_WXGA is not set
# CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT is not set
# CONFIG_FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT is not set
@@ -1868,9 +1870,11 @@ CONFIG_FB_MSM_LCDC_SAMSUNG_WSVGA_PANEL=y
# CONFIG_FB_MSM_LCDC_GORDON_VGA_PANEL is not set
# CONFIG_FB_MSM_LCDC_TOSHIBA_WVGA_PT_PANEL is not set
# CONFIG_FB_MSM_LCDC_SHARP_WVGA_PT_PANEL is not set
+# CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT_PANEL is not set
# CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM is not set
# CONFIG_FB_MSM_MIPI_PANEL_DETECT is not set
# CONFIG_FB_MSM_MDDI_PANEL_AUTO_DETECT is not set
+CONFIG_FB_MSM_LCDC_PANEL_AUTO_DETECT=y
# CONFIG_FB_MSM_MDDI_PRISM_WVGA is not set
# CONFIG_FB_MSM_MDDI_TOSHIBA_WVGA_PORTRAIT is not set
# CONFIG_FB_MSM_MDDI_TOSHIBA_VGA is not set
View
8 arch/arm/configs/msm8660_defconfig
@@ -75,7 +75,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
@@ -341,7 +341,7 @@ CONFIG_MSM_SMD_TTY=y
# CONFIG_MSM_SMD_QMI is not set
CONFIG_MSM_SMD_PKT=y
CONFIG_MSM_SDIO_CMUX=y
-CONFIG_MSM_DSPS=y
+# CONFIG_MSM_DSPS is not set
CONFIG_MSM_SDIO_CTL=y
CONFIG_MSM_ONCRPCROUTER=y
CONFIG_MSM_ONCRPCROUTER_DEBUG=y
@@ -1847,6 +1847,7 @@ CONFIG_FB_MSM_DTV=y
# CONFIG_FB_MSM_MDDI_ORISE is not set
# CONFIG_FB_MSM_MDDI_QUICKVX is not set
# CONFIG_FB_MSM_MDDI_AUTO_DETECT is not set
+CONFIG_FB_MSM_LCDC_AUTO_DETECT=y
CONFIG_FB_MSM_LCDC_PANEL=y
# CONFIG_FB_MSM_MIPI_DSI_TOSHIBA is not set
# CONFIG_FB_MSM_MIPI_DSI_NOVATEK is not set
@@ -1859,6 +1860,7 @@ CONFIG_FB_MSM_LCDC_SAMSUNG_WSVGA=y
# CONFIG_FB_MSM_LCDC_GORDON_VGA is not set
# CONFIG_FB_MSM_LCDC_TOSHIBA_WVGA_PT is not set
# CONFIG_FB_MSM_LCDC_SHARP_WVGA_PT is not set
+CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT=y
# CONFIG_FB_MSM_LCDC_WXGA is not set
# CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT is not set
# CONFIG_FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT is not set
@@ -1868,9 +1870,11 @@ CONFIG_FB_MSM_LCDC_SAMSUNG_WSVGA_PANEL=y
# CONFIG_FB_MSM_LCDC_GORDON_VGA_PANEL is not set
# CONFIG_FB_MSM_LCDC_TOSHIBA_WVGA_PT_PANEL is not set
# CONFIG_FB_MSM_LCDC_SHARP_WVGA_PT_PANEL is not set
+# CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT_PANEL is not set
# CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM is not set
# CONFIG_FB_MSM_MIPI_PANEL_DETECT is not set
# CONFIG_FB_MSM_MDDI_PANEL_AUTO_DETECT is not set
+CONFIG_FB_MSM_LCDC_PANEL_AUTO_DETECT=y
# CONFIG_FB_MSM_MDDI_PRISM_WVGA is not set
# CONFIG_FB_MSM_MDDI_TOSHIBA_WVGA_PORTRAIT is not set
# CONFIG_FB_MSM_MDDI_TOSHIBA_VGA is not set
View
2 arch/arm/configs/qsd8650-perf_defconfig
@@ -74,7 +74,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
View
2 arch/arm/configs/qsd8650_defconfig
@@ -74,7 +74,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
View
2 arch/arm/configs/qsd8650a-perf_defconfig
@@ -74,7 +74,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
View
2 arch/arm/configs/qsd8650a_defconfig
@@ -74,7 +74,7 @@ CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
# CONFIG_CGROUP_MEM_RES_CTLR is not set
CONFIG_CGROUP_SCHED=y
-# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_FAIR_GROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_BLK_CGROUP is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
View
1 arch/arm/include/asm/mach/mmc.h
@@ -32,6 +32,7 @@ struct mmc_platform_data {
unsigned int msmsdcc_fmax;
bool nonremovable;
bool pclk_src_dfab;
+ int (*cfg_mpm_sdiowakeup)(struct device *, bool);
};
#endif
View
4 arch/arm/include/asm/mmu.h
@@ -13,6 +13,10 @@ typedef struct {
#ifdef CONFIG_CPU_HAS_ASID
#define ASID(mm) ((mm)->context.id & 255)
+
+/* init_mm.context.id_lock should be initialized. */
+#define INIT_MM_CONTEXT(name) \
+ .context.id_lock = __SPIN_LOCK_UNLOCKED(name.context.id_lock),
#else
#define ASID(mm) (0)
#endif
View
120 arch/arm/include/asm/sched_clock.h
@@ -0,0 +1,120 @@
+/*
+ * sched_clock.h: support for extending counters to full 64-bit ns counter
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASM_SCHED_CLOCK
+#define ASM_SCHED_CLOCK
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct clock_data {
+ u64 epoch_ns;
+ u32 epoch_cyc;
+ u32 epoch_cyc_copy;
+ u32 mult;
+ u32 shift;
+};
+
+#define DEFINE_CLOCK_DATA(name) struct clock_data name
+
+static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
+{
+ return (cyc * mult) >> shift;
+}
+
+/*
+ * Atomically update the sched_clock epoch. Your update callback will
+ * be called from a timer before the counter wraps - read the current
+ * counter value, and call this function to safely move the epochs
+ * forward. Only use this from the update callback.
+ */
+static inline void update_sched_clock(struct clock_data *cd, u32 cyc, u32 mask)
+{
+ unsigned long flags;
+ u64 ns = cd->epoch_ns +
+ cyc_to_ns((cyc - cd->epoch_cyc) & mask, cd->mult, cd->shift);
+
+ /*
+ * Write epoch_cyc and epoch_ns in a way that the update is
+ * detectable in cyc_to_fixed_sched_clock().
+ */
+ raw_local_irq_save(flags);
+ cd->epoch_cyc = cyc;
+ smp_wmb();
+ cd->epoch_ns = ns;
+ smp_wmb();
+ cd->epoch_cyc_copy = cyc;
+ raw_local_irq_restore(flags);
+}
+
+/*
+ * If your clock rate is known at compile time, using this will allow
+ * you to optimize the mult/shift loads away. This is paired with
+ * init_fixed_sched_clock() to ensure that your mult/shift are correct.
+ */
+static inline unsigned long long cyc_to_fixed_sched_clock(struct clock_data *cd,
+ u32 cyc, u32 mask, u32 mult, u32 shift)
+{
+ u64 epoch_ns;
+ u32 epoch_cyc;
+
+ /*
+ * Load the epoch_cyc and epoch_ns atomically. We do this by
+ * ensuring that we always write epoch_cyc, epoch_ns and
+ * epoch_cyc_copy in strict order, and read them in strict order.
+ * If epoch_cyc and epoch_cyc_copy are not equal, then we're in
+ * the middle of an update, and we should repeat the load.
+ */
+ do {
+ epoch_cyc = cd->epoch_cyc;
+ smp_rmb();
+ epoch_ns = cd->epoch_ns;
+ smp_rmb();
+ } while (epoch_cyc != cd->epoch_cyc_copy);
+
+ return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, mult, shift);
+}
+
+/*
+ * Otherwise, you need to use this, which will obtain the mult/shift
+ * from the clock_data structure. Use init_sched_clock() with this.
+ */
+static inline unsigned long long cyc_to_sched_clock(struct clock_data *cd,
+ u32 cyc, u32 mask)
+{
+ return cyc_to_fixed_sched_clock(cd, cyc, mask, cd->mult, cd->shift);
+}
+
+/*
+ * Initialize the clock data - calculate the appropriate multiplier
+ * and shift. Also setup a timer to ensure that the epoch is refreshed
+ * at the appropriate time interval, which will call your update
+ * handler.
+ */
+void init_sched_clock(struct clock_data *, void (*)(void),
+ unsigned int, unsigned long);
+
+/*
+ * Use this initialization function rather than init_sched_clock() if
+ * you're using cyc_to_fixed_sched_clock, which will warn if your
+ * constants are incorrect.
+ */
+static inline void init_fixed_sched_clock(struct clock_data *cd,
+ void (*update)(void), unsigned int bits, unsigned long rate,
+ u32 mult, u32 shift)
+{
+ init_sched_clock(cd, update, bits, rate);
+ if (cd->mult != mult || cd->shift != shift) {
+ pr_crit("sched_clock: wrong multiply/shift: %u>>%u vs calculated %u>>%u\n"
+ "sched_clock: fix multiply/shift to avoid scheduler hiccups\n",
+ mult, shift, cd->mult, cd->shift);
+ }
+}
+
+extern void sched_clock_postinit(void);
+
+#endif
View
1 arch/arm/kernel/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o
obj-$(CONFIG_ARTHUR) += arthur.o
obj-$(CONFIG_ISA_DMA) += dma-isa.o
obj-$(CONFIG_PCI) += bios32.o isa.o
+obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o
View
74 arch/arm/kernel/sched_clock.c
@@ -0,0 +1,74 @@
+/*
+ * sched_clock.c: support for extending counters to full 64-bit ns counter
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+
+#include <asm/sched_clock.h>
+
+static void sched_clock_poll(unsigned long wrap_ticks);
+static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
+static void (*sched_clock_update_fn)(void);
+
+static void sched_clock_poll(unsigned long wrap_ticks)
+{
+ mod_timer(&sched_clock_timer, round_jiffies(jiffies + wrap_ticks));
+ sched_clock_update_fn();
+}
+
+void __init init_sched_clock(struct clock_data *cd, void (*update)(void),
+ unsigned int clock_bits, unsigned long rate)
+{
+ unsigned long r, w;
+ u64 res, wrap;
+ char r_unit;
+
+ sched_clock_update_fn = update;
+
+ /* calculate the mult/shift to convert counter ticks to ns. */
+ clocks_calc_mult_shift(&cd->mult, &cd->shift, rate, NSEC_PER_SEC, 60);
+
+ r = rate;
+ if (r >= 4000000) {
+ r /= 1000000;
+ r_unit = 'M';
+ } else {
+ r /= 1000;
+ r_unit = 'k';
+ }
+
+ /* calculate how many ns until we wrap */
+ wrap = cyc_to_ns((1ULL << clock_bits) - 1, cd->mult, cd->shift);
+ do_div(wrap, NSEC_PER_MSEC);
+ w = wrap;
+
+ /* calculate the ns resolution of this counter */
+ res = cyc_to_ns(1ULL, cd->mult, cd->shift);
+ pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lums\n",
+ clock_bits, r, r_unit, res, w);
+
+ /*
+ * Start the timer to keep sched_clock() properly updated and
+ * sets the initial epoch.
+ */
+ sched_clock_timer.data = msecs_to_jiffies(w - (w / 10));
+ update();
+
+ /*
+ * Ensure that sched_clock() starts off at 0ns
+ */
+ cd->epoch_ns = 0;
+}
+
+void __init sched_clock_postinit(void)
+{
+ sched_clock_poll(sched_clock_timer.data);
+}
View
9 arch/arm/kernel/stacktrace.c
@@ -94,10 +94,13 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
if (tsk != current) {
#ifdef CONFIG_SMP
/*
- * What guarantees do we have here that 'tsk'
- * is not running on another CPU?
+ * What guarantees do we have here that 'tsk' is not
+ * running on another CPU? For now, ignore it as we
+ * can't guarantee we won't explode.
*/
- BUG();
+ if (trace->nr_entries < trace->max_entries)
+ trace->entries[trace->nr_entries++] = ULONG_MAX;
+ return;
#else
data.no_sched_functions = 1;
frame.fp = thread_saved_fp(tsk);
View
4 arch/arm/kernel/time.c
@@ -29,6 +29,7 @@
#include <asm/leds.h>
#include <asm/thread_info.h>
+#include <asm/sched_clock.h>
#include <asm/stacktrace.h>
#include <asm/mach/time.h>
@@ -161,5 +162,8 @@ device_initcall(timer_init_sysfs);
void __init time_init(void)
{
system_timer->init();
+#ifdef CONFIG_HAVE_SCHED_CLOCK
+ sched_clock_postinit();
+#endif
}
View
2 arch/arm/mach-msm/Makefile
@@ -119,7 +119,7 @@ obj-$(CONFIG_MACH_QSD8X50A_SURF) += board-qsd8x50.o
obj-$(CONFIG_MACH_QSD8X50A_FFA) += board-qsd8x50.o
obj-$(CONFIG_MACH_QSD8X50A_ST1_5) += board-qsd8x50a-st1x.o
obj-$(CONFIG_ARCH_MSM8X60) += devices-msm8x60.o clock-local.o clock-8x60.o acpuclock-8x60.o
-obj-$(CONFIG_ARCH_MSM8X60) += clock-8x60_mxo.o clock-rpm.o spm.o restart.o
+obj-$(CONFIG_ARCH_MSM8X60) += clock-rpm.o spm.o restart.o
obj-$(CONFIG_ARCH_MSM8X60) += subsystem-fatal-8x60.o
obj-$(CONFIG_ARCH_MSM8X60) += saw-regulator.o
obj-$(CONFIG_ARCH_MSM8X60) += rpm-regulator.o
View
119 arch/arm/mach-msm/acpuclock-8x60.c
@@ -53,10 +53,11 @@
#define L_VAL_SCPLL_CAL_MIN 0x08 /* = 432 MHz with 27MHz source */
#define L_VAL_SCPLL_CAL_MAX 0x1C /* = 1512 MHz with 27MHz source */
-#define MAX_VDD_SC 1200000 /* uV */
-#define MAX_VDD_MEM 1200000 /* uV */
-#define MAX_VDD_DIG 1200000 /* uV */
+#define MAX_VDD_SC 1250000 /* uV */
#define MAX_AXI 310500 /* KHz */
+#define SCPLL_LOW_VDD_FMAX 594000 /* KHz */
+#define SCPLL_LOW_VDD 1000000 /* uV */
+#define SCPLL_NOMINAL_VDD 1100000 /* uV */
/* SCPLL Modes. */
#define SCPLL_POWER_DOWN 0
@@ -85,6 +86,10 @@
#define SPSS1_CLK_CTL_ADDR (MSM_ACC1_BASE + 0x04)
#define SPSS1_CLK_SEL_ADDR (MSM_ACC1_BASE + 0x08)
#define SPSS_L2_CLK_SEL_ADDR (MSM_GCC_BASE + 0x38)
+
+/* Speed bin register. */
+#define QFPROM_SPEED_BIN_PRI (MSM_QFPROM_BASE + 0x00C0)
+
static const void * const clk_ctl_addr[] = {SPSS0_CLK_CTL_ADDR,
SPSS1_CLK_CTL_ADDR};
static const void * const clk_sel_addr[] = {SPSS0_CLK_SEL_ADDR,
@@ -176,49 +181,6 @@ static struct msm_bus_scale_pdata bus_client_pdata = {
static uint32_t bus_perf_client;
-/* CPU and L2 frequency tables that apply to 8660 v1 SoCs. */
-/* L2 frequencies = 2 * 27 MHz * L_VAL */
-static struct clkctl_l2_speed l2_freq_tbl_v1[] = {
- [0] = {MAX_AXI, 0, 0, 1000000, 1100000, 4},
- [1] = {432000, 1, 0x08, 1000000, 1100000, 4},
- [2] = {432000, 1, 0x08, 1100000, 1200000, 6},
- [3] = {432000, 1, 0x08, 1100000, 1200000, 6},
- [4] = {432000, 1, 0x08, 1100000, 1200000, 6},
- [5] = {432000, 1, 0x08, 1200000, 1200000, 8},
- [6] = {432000, 1, 0x08, 1200000, 1200000, 8},
- [7] = {432000, 1, 0x08, 1200000, 1200000, 8},
- [8] = {432000, 1, 0x08, 1200000, 1200000, 8},
- [9] = {432000, 1, 0x08, 1200000, 1200000, 8},
-};
-
-#define L2(x) (&l2_freq_tbl_v1[(x)])
- /* SCPLL frequencies = 2 * 27 MHz * L_VAL */
-static struct clkctl_acpu_speed acpu_freq_tbl_v1[] = {
- { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 900000, 0x03006000},
- /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */
- { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 925000, 0x03006000},
- { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 925000, 0x03006000},
- { {0, 0}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(4), 975000, 0x03006000},
- { {0, 0}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(4), 975000, 0x03006000},
- { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(4), 975000, 0x03006000},
- { {0, 0}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(9), 1025000, 0x03006000},
- { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(9), 1025000, 0x03006000},
- { {0, 0}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(9), 1100000, 0x03006000},
- { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(9), 1100000, 0x03006000},
- { {0, 0}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(9), 1175000, 0x03006000},
- { {0, 0}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 1175000, 0x03006000},
- { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(9), 1175000, 0x03006000},
- { {0, 0}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(9), 1200000, 0x03006000},
- { {0, 0}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(9), 1200000, 0x03006000},
- { {0, 0}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(9), 1200000, 0x03006000},
- { {0, 0}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(9), 1200000, 0x03006000},
- { {0, 0}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(9), 1200000, 0x03006000},
- { {0, 0}, 0 },
-};
-
-#undef L2
-
-/* CPU and L2 frequency tables that apply to 8660 v2 SoCs. */
/* L2 frequencies = 2 * 27 MHz * L_VAL */
static struct clkctl_l2_speed l2_freq_tbl_v2[] = {
[0] = { MAX_AXI, 0, 0, 1000000, 1100000, 4},
@@ -237,10 +199,11 @@ static struct clkctl_l2_speed l2_freq_tbl_v2[] = {
[13] = {1080000, 1, 0x14, 1100000, 1200000, 7},
[14] = {1134000, 1, 0x15, 1100000, 1200000, 7},
[15] = {1188000, 1, 0x16, 1200000, 1200000, 8},
+ [16] = {1404000, 1, 0x1A, 1200000, 1250000, 8},
};
#define L2(x) (&l2_freq_tbl_v2[(x)])
- /* SCPLL frequencies = 2 * 27 MHz * L_VAL */
+/* SCPLL frequencies = 2 * 27 MHz * L_VAL */
static struct clkctl_acpu_speed acpu_freq_tbl_v2[] = {
{ {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000},
/* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */
@@ -261,11 +224,10 @@ static struct clkctl_acpu_speed acpu_freq_tbl_v2[] = {
{ {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1137500, 0x03006000},
{ {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1162500, 0x03006000},
{ {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1187500, 0x03006000},
+ { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(16), 1250000, 0x03006000},
{ {0, 0}, 0 },
};
-
-/* acpu_freq_tbl row to use when reconfiguring SC/L2 PLLs. Should be the same
- * for both v1 and v2 tables. */
+/* acpu_freq_tbl row to use when reconfiguring SC/L2 PLLs. */
#define CAL_IDX 1
static struct clkctl_acpu_speed *acpu_freq_tbl;
@@ -541,7 +503,7 @@ int acpuclk_set_rate(int cpu, unsigned long rate, enum setrate_reason reason)
{
struct clkctl_acpu_speed *tgt_s, *strt_s;
struct clkctl_l2_speed *tgt_l2;
- unsigned int vdd_mem, vdd_dig;
+ unsigned int vdd_mem, vdd_dig, pll_vdd_dig;
int freq_index = 0;
int rc = 0;
@@ -579,7 +541,14 @@ int acpuclk_set_rate(int cpu, unsigned long rate, enum setrate_reason reason)
/* Calculate vdd_mem and vdd_dig requirements.
* vdd_mem must be >= vdd_sc */
vdd_mem = max(tgt_s->vdd_sc, tgt_s->l2_level->vdd_mem);
- vdd_dig = tgt_s->l2_level->vdd_dig;
+ /* Factor-in PLL vdd_dig requirements. */
+ if ((tgt_s->l2_level->khz > SCPLL_LOW_VDD_FMAX) ||
+ (tgt_s->pll == ACPU_SCPLL
+ && tgt_s->acpuclk_khz > SCPLL_LOW_VDD_FMAX))
+ pll_vdd_dig = SCPLL_NOMINAL_VDD;
+ else
+ pll_vdd_dig = SCPLL_LOW_VDD;
+ vdd_dig = max(tgt_s->l2_level->vdd_dig, pll_vdd_dig);
/* Increase VDD levels if needed. */
if ((reason == SETRATE_CPUFREQ || reason == SETRATE_INIT)
@@ -689,27 +658,20 @@ static void __init unselect_scplls(void)
drv_state.current_l2_speed = acpu_freq_tbl[CAL_IDX].l2_level;
}
-/* Ensure SCPLLs use the 27MHz XO. */
+/* Ensure SCPLLs use the 27MHz PXO. */
static void __init scpll_set_refs(void)
{
int cpu;
uint32_t regval;
- int use_pxo = pxo_is_27mhz();
/* Bit 4 = 0:PXO, 1:MXO. */
for_each_possible_cpu(cpu) {
regval = readl(sc_pll_base[cpu] + SCPLL_CFG_OFFSET);
- if (use_pxo)
- regval &= ~BIT(4);
- else
- regval |= BIT(4);
+ regval &= ~BIT(4);
writel(regval, sc_pll_base[cpu] + SCPLL_CFG_OFFSET);
}
regval = readl(sc_pll_base[L2] + SCPLL_CFG_OFFSET);
- if (use_pxo)
- regval &= ~BIT(4);
- else
- regval |= BIT(4);
+ regval &= ~BIT(4);
writel(regval, sc_pll_base[L2] + SCPLL_CFG_OFFSET);
}
@@ -787,17 +749,30 @@ static void __init cpufreq_table_init(void)
static void __init cpufreq_table_init(void) {}
#endif
-static void __init select_freq_tables(void)
+static void __init select_freq_plan(void)
{
- if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
- acpu_freq_tbl = acpu_freq_tbl_v2;
- l2_freq_tbl = l2_freq_tbl_v2;
- l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl_v2);
- } else {
- acpu_freq_tbl = acpu_freq_tbl_v1;
- l2_freq_tbl = l2_freq_tbl_v1;
- l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl_v1);
+ uint32_t speed_bin, max_khz;
+ struct clkctl_acpu_speed *f;
+
+ acpu_freq_tbl = acpu_freq_tbl_v2;
+ l2_freq_tbl = l2_freq_tbl_v2;
+ l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl_v2);
+
+ speed_bin = readl(QFPROM_SPEED_BIN_PRI) & 0xF;
+ if (speed_bin == 0x1)
+ max_khz = 1512000;
+ else
+ max_khz = 1188000;
+
+ /* Truncate the table based to max_khz. */
+ for (f = acpu_freq_tbl; f->acpuclk_khz != 0; f++) {
+ if (f->acpuclk_khz > max_khz) {
+ f->acpuclk_khz = 0;
+ break;
+ }
}
+ f--;
+ pr_info("Max ACPU freq: %u KHz\n", f->acpuclk_khz);
}
void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
@@ -809,7 +784,7 @@ void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
/* Configure hardware. */
- select_freq_tables();
+ select_freq_plan();
unselect_scplls();
scpll_set_refs();
for_each_possible_cpu(cpu)
View
4 arch/arm/mach-msm/board-msm7x27.c
@@ -1944,12 +1944,8 @@ static void __init msm7x2x_init(void)
#ifdef CONFIG_KGSL_PER_PROCESS_PAGE_TABLE
kgsl_pdata.pt_va_size = SZ_32M;
- /* Maximum of 32 concurrent processes */
- kgsl_pdata.pt_max_count = 32;
#else
kgsl_pdata.pt_va_size = SZ_128M;
- /* We only ever have one pagetable for everybody */
- kgsl_pdata.pt_max_count = 1;
#endif
#endif
usb_mpp_init();
View
156 arch/arm/mach-msm/board-msm7x30.c
@@ -1532,6 +1532,19 @@ static int __init buses_init(void)
#define TIMPANI_RESET_GPIO 1
+struct bahama_config_register{
+ u8 reg;
+ u8 value;
+ u8 mask;
+};
+
+enum version{
+ VER_1_0,
+ VER_2_0,
+ VER_UNSUPPORTED = 0xFF
+};
+
+
static struct vreg *vreg_marimba_1;
static struct vreg *vreg_marimba_2;
static struct vreg *vreg_marimba_3;
@@ -1540,6 +1553,36 @@ static struct msm_gpio timpani_reset_gpio_cfg[] = {
{ GPIO_CFG(TIMPANI_RESET_GPIO, 0, GPIO_CFG_OUTPUT,
GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "timpani_reset"} };
+static u8 read_bahama_ver(void)
+{
+ int rc;
+ struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
+ u8 bahama_version;
+
+ rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
+ if (rc < 0) {
+ printk(KERN_ERR
+ "%s: version read failed: %d\n",
+ __func__, rc);
+ return rc;
+ } else {
+ printk(KERN_INFO
+ "%s: version read got: 0x%x\n",
+ __func__, bahama_version);
+ }
+
+ switch (bahama_version) {
+ case 0x08: /* varient of bahama v1 */
+ case 0x10:
+ case 0x00:
+ return VER_1_0;
+ case 0x09: /* variant of bahama v2 */
+ return VER_2_0;
+ default:
+ return VER_UNSUPPORTED;
+ }
+}
+
static int config_timpani_reset(void)
{
int rc;
@@ -1620,6 +1663,47 @@ static void msm_timpani_shutdown_power(void)
ARRAY_SIZE(timpani_reset_gpio_cfg));
};
+static unsigned int msm_bahama_core_config(int type)
+{
+ int rc = 0;
+
+ if (type == BAHAMA_ID) {
+
+ int i;
+ struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
+
+ const struct bahama_config_register v20_init[] = {
+ /* reg, value, mask */
+ { 0xF4, 0x84, 0xFF }, /* AREG */
+ { 0xF0, 0x04, 0xFF } /* DREG */
+ };
+
+ if (read_bahama_ver() == VER_2_0) {
+ for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
+ u8 value = v20_init[i].value;
+ rc = marimba_write_bit_mask(&config,
+ v20_init[i].reg,
+ &value,
+ sizeof(v20_init[i].value),
+ v20_init[i].mask);
+ if (rc < 0) {
+ printk(KERN_ERR
+ "%s: reg %d write failed: %d\n",
+ __func__, v20_init[i].reg, rc);
+ return rc;
+ }
+ printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
+ " mask 0x%02x\n",
+ __func__, v20_init[i].reg,
+ v20_init[i].value, v20_init[i].mask);
+ }
+ }
+ }
+ printk(KERN_INFO "core type: %d\n", type);
+
+ return rc;
+}
+
static unsigned int msm_bahama_setup_power(void)
{
int rc;
@@ -2177,6 +2261,7 @@ static struct marimba_platform_data marimba_pdata = {
.bahama_setup = msm_bahama_setup_power,
.bahama_shutdown = msm_bahama_shutdown_power,
.marimba_gpio_config = msm_marimba_gpio_config_svlte,
+ .bahama_core_config = msm_bahama_core_config,
.fm = &marimba_fm_pdata,
.codec = &mariba_codec_pdata,
};
@@ -3794,12 +3879,8 @@ static struct kgsl_platform_data kgsl_pdata = {
#ifdef CONFIG_KGSL_PER_PROCESS_PAGE_TABLE
.pt_va_size = SZ_32M,
- /* Maximum of 32 concurrent processes */
- .pt_max_count = 32,
#else
.pt_va_size = SZ_128M,
- /* We only ever have one pagetable for everybody */
- .pt_max_count = 1,
#endif
};
@@ -4310,7 +4391,6 @@ int mdp_core_clk_rate_table[] = {
122880000,
122880000,
192000000,
- 192000000,
};
static struct msm_panel_common_pdata mdp_pdata = {
@@ -4609,7 +4689,7 @@ static const char *vregs_bt_bahama_name[] = {
};
static struct vreg *vregs_bt_bahama[ARRAY_SIZE(vregs_bt_bahama_name)];
-static u8 bha_version;
+static u8 bahama_version;
static int marimba_bt(int on)
{
@@ -4745,12 +4825,6 @@ static int bahama_bt(int on)
int i;
struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
- struct bahama_config_register {
- u8 reg;
- u8 value;
- u8 mask;
- };
-
struct bahama_variant_register {
const size_t size;
const struct bahama_config_register *set;
@@ -4834,55 +4908,33 @@ static int bahama_bt(int on)
}
};
+ u8 offset = 0; /* index into bahama configs */
+
/* Init mutex to get/set FM/BT status respectively */
mutex_init(&config.xfer_lock);
on = on ? 1 : 0;
- /* Reset version */
- bha_version = 0xFF;
+ bahama_version = read_bahama_ver();
- rc = marimba_read_bit_mask(&config, 0x00, &bha_version, 1, 0x1F);
- if (rc < 0) {
- dev_err(&msm_bt_power_device.dev,
- "%s: version read failed: %d\n",
- __func__, rc);
- return rc;
- } else {
- dev_info(&msm_bt_power_device.dev,
- "%s: version read got: 0x%x\n",
- __func__, bha_version);
- }
-
- switch (bha_version) {
- case 0x08: /* varients of bahama v1 */
- case 0x10:
- case 0x00:
- bha_version = 0x00;
- break;
- case 0x09: /* variant of bahama v2 */
- /* bahama v2 has different bring-up & shutdown sequence */
- /* based on FM status */
- bha_version = marimba_get_fm_status(&config) ? 0x02 : 0x01;
- break;
- default:
- bha_version = 0xFF;
- }
-
- if ((bha_version >= ARRAY_SIZE(bt_bahama[on])) ||
- (bt_bahama[on][bha_version].size == 0)) {
+ if (bahama_version == VER_UNSUPPORTED) {
dev_err(&msm_bt_power_device.dev,
"%s: unsupported version\n",
__func__);
return -EIO;
}
- p = bt_bahama[on][bha_version].set;
+ if (bahama_version == VER_2_0) {
+ if (marimba_get_fm_status(&config))
+ offset = 0x01;
+ }
+
+ p = bt_bahama[on][bahama_version + offset].set;
dev_info(&msm_bt_power_device.dev,
- "%s: found version %d\n", __func__, bha_version);
+ "%s: found version %d\n", __func__, bahama_version);
- for (i = 0; i < bt_bahama[on][bha_version].size; i++) {
+ for (i = 0; i < bt_bahama[on][bahama_version + offset].size; i++) {
u8 value = (p+i)->value;
rc = marimba_write_bit_mask(&config,
(p+i)->reg,
@@ -4909,12 +4961,11 @@ static int bahama_bt(int on)
/* Destory mutex */
mutex_destroy(&config.xfer_lock);
- if ((bha_version == 0x01 || bha_version == 0x02)
- && on) { /*variant of bahama v2 */
+ if (bahama_version == VER_2_0 && on) { /* variant of bahama v2 */
/* Disable s2 as bahama v2 uses internal LDO regulator */
for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
if (!strcmp(vregs_bt_bahama_name[i], "s2")) {
- vreg_disable(vregs_bt_bahama[i]);
+ rc = vreg_disable(vregs_bt_bahama[i]);
if (rc < 0) {
printk(KERN_ERR
"%s: vreg %s disable "
@@ -4960,8 +5011,7 @@ static int bluetooth_power_regulators(int on, int bahama_not_marimba)
}
for (i = 0; i < vregs_size; i++) {
- if (bahama_not_marimba &&
- (bha_version == 0x01 || bha_version == 0x02) &&
+ if (bahama_not_marimba && (bahama_version == VER_2_0) &&
!on && !strcmp(vregs_bt_bahama_name[i], "s2"))
continue;
rc = on ? vreg_enable(vregs[i]) :
@@ -5060,15 +5110,13 @@ static int bluetooth_power(int on)
if (rc < 0)
return -EIO;
- if (bha_version != 0x01 && bha_version != 0x02) {
+ if (bahama_version == VER_1_0) {
rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
if (rc < 0) {
printk(KERN_ERR "%s: vreg level off failed "
"(%d)\n", __func__, rc);
return -EIO;
}
- /* Reset version */
- bha_version = 0xFF;
}
}
View
360 arch/arm/mach-msm/board-msm8x60.c
@@ -92,6 +92,7 @@
#include "cpuidle.h"
#include "pm.h"
#include "rpm.h"
+#include "mpm.h"
#include "spm.h"
#include "rpm_log.h"
#include "timer.h"
@@ -99,7 +100,6 @@
#include "rpm-regulator.h"
#include "gpiomux.h"
#include "gpiomux-8x60.h"
-#include "mpm.h"
#define MSM_SHARED_RAM_PHYS 0x40000000
@@ -375,7 +375,7 @@ static struct regulator_init_data saw_s0_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.min_uV = 840000,
- .max_uV = 1200000,
+ .max_uV = 1250000,
},
.num_consumer_supplies = 1,
.consumer_supplies = &saw_s0_supply,
@@ -385,7 +385,7 @@ static struct regulator_init_data saw_s1_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.min_uV = 840000,
- .max_uV = 1200000,
+ .max_uV = 1250000,
},
.num_consumer_supplies = 1,
.consumer_supplies = &saw_s1_supply,
@@ -1997,10 +1997,20 @@ static struct resource msm_fb_resources[] = {
}
};
+#ifdef CONFIG_FB_MSM_LCDC_AUTO_DETECT
static int msm_fb_detect_panel(const char *name)
{
- if (!strcmp(name, "lcdc_samsung_wsvga"))
- return 0;
+ if (machine_is_msm8x60_fluid()) {
+ if (!strncmp(name, "lcdc_samsung_oled", 20))
+ return 0;
+ if (!strncmp(name, "lcdc_samsung_wsvga", 20))
+ return -ENODEV;
+ } else {
+ if (!strncmp(name, "lcdc_samsung_wsvga", 20))
+ return 0;
+ if (!strncmp(name, "lcdc_samsung_oled", 20))
+ return -ENODEV;
+ }
pr_warning("%s: not supported '%s'", __func__, name);
return -ENODEV;
}
@@ -2008,13 +2018,16 @@ static int msm_fb_detect_panel(const char *name)
static struct msm_fb_platform_data msm_fb_pdata = {
.detect_client = msm_fb_detect_panel,
};
+#endif /* CONFIG_FB_MSM_LCDC_AUTO_DETECT */
static struct platform_device msm_fb_device = {
.name = "msm_fb",
.id = 0,
.num_resources = ARRAY_SIZE(msm_fb_resources),
.resource = msm_fb_resources,
+#ifdef CONFIG_FB_MSM_LCDC_AUTO_DETECT
.dev.platform_data = &msm_fb_pdata,
+#endif /* CONFIG_FB_MSM_LCDC_AUTO_DETECT */
};
#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
@@ -2127,6 +2140,55 @@ static struct platform_device lcdc_samsung_panel_device = {
}
};
+#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
+#ifdef CONFIG_SPI_QUP
+static struct spi_board_info lcdc_samsung_spi_board_info[] __initdata = {
+ {
+ .modalias = "lcdc_samsung_ams367pe02",
+ .mode = SPI_MODE_3,
+ .bus_num = 1,
+ .chip_select = 0,
+ .max_speed_hz = 10800000,
+ }
+};
+#else
+static int lcdc_spi_gpio_array_num[] = {
+ 73, /* spi_clk */
+ 72, /* spi_cs */
+ 70, /* spi_mosi */
+ };
+
+static uint32_t lcdc_spi_gpio_config_data[] = {
+ /* spi_clk */
+ GPIO_CFG(73, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
+ /* spi_cs0 */
+ GPIO_CFG(72, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
+ /* spi_mosi */
+ GPIO_CFG(70, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
+};
+
+static void lcdc_config_spi_gpios(int enable)
+{
+ int n;
+ for (n = 0; n < ARRAY_SIZE(lcdc_spi_gpio_config_data); ++n)
+ gpio_tlmm_config(lcdc_spi_gpio_config_data[n], 0);
+}
+#endif
+
+static struct msm_panel_common_pdata lcdc_samsung_oled_panel_data = {
+#ifndef CONFIG_SPI_QUP
+ .panel_config_gpio = lcdc_config_spi_gpios,
+ .gpio_num = lcdc_spi_gpio_array_num,
+#endif
+};
+
+static struct platform_device lcdc_samsung_oled_panel_device = {
+ .name = "lcdc_samsung_oled",
+ .id = 0,
+ .dev.platform_data = &lcdc_samsung_oled_panel_data,
+};
+#endif
+
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
static struct resource hdmi_msm_resources[] = {
{
@@ -2854,16 +2916,16 @@ static struct rpm_vreg_pdata rpm_vreg_init_pdata[RPM_VREG_ID_MAX] = {
RPM_VREG_INIT_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
RPM_VREG_INIT_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
- RPM_VREG_INIT_SMPS(PM8058_S0, 0, 1, 1, 500000, 1200000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
- RPM_VREG_INIT_SMPS(PM8058_S1, 0, 1, 1, 500000, 1200000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_INIT_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 0,
+ RPM_VREG_FREQ_1p60),
+ RPM_VREG_INIT_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 0,
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8058_S2, 0, 1, 0, 1200000, 1400000, SMPS_HMIN,
- RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p75),
+ RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_VS(PM8058_LVS0, 0, 1, 0, 0),
RPM_VREG_INIT_VS(PM8058_LVS1, 0, 1, 0, 0),
@@ -2880,11 +2942,11 @@ static struct rpm_vreg_pdata rpm_vreg_init_pdata[RPM_VREG_ID_MAX] = {
RPM_VREG_INIT_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN, 0),
RPM_VREG_INIT_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN,
- RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p75),
+ RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_VS(PM8901_LVS0, 1, 1, 0, 0),
RPM_VREG_INIT_VS(PM8901_LVS1, 0, 1, 0, 0),
@@ -3335,6 +3397,9 @@ static struct platform_device *surf_devices[] __initdata = {
&msm_fb_device,
&msm_device_kgsl,
&lcdc_samsung_panel_device,
+#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
+ &lcdc_samsung_oled_panel_device,
+#endif
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
&hdmi_msm_device,
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
@@ -4136,9 +4201,16 @@ static struct hsed_bias_config hsed_bias_config = {
static struct othc_hsed_config hsed_config_1 = {
.hsed_bias_config = &hsed_bias_config,
- .detection_delay_ms = 200,
+ /*
+ * The detection delay and switch reporting delay are
+ * required to encounter a hardware bug (spurious switch
+ * interrupts on slow insertion/removal of the headset).
+ * This will introduce a delay in reporting the accessory
+ * insertion and removal to the userspace.
+ */
+ .detection_delay_ms = 1500,
/* Switch info */
- .switch_debounce_ms = 1000,
+ .switch_debounce_ms = 1500,
.othc_support_n_switch = false,
.switch_config = &switch_config,
/* Accessory info */
@@ -4147,11 +4219,18 @@ static struct othc_hsed_config hsed_config_1 = {
.othc_num_accessories = ARRAY_SIZE(othc_accessories),
};
+static struct othc_regulator_config othc_reg = {
+ .regulator = "8058_l5",
+ .max_uV = 2850000,
+ .min_uV = 2850000,
+};
+
/* MIC_BIAS0 is configured as normal MIC BIAS */
static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
.micbias_select = OTHC_MICBIAS_0,
.micbias_capability = OTHC_MICBIAS,
.micbias_enable = OTHC_SIGNAL_OFF,
+ .micbias_regulator = &othc_reg,
};
/* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
@@ -4159,6 +4238,7 @@ static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
.micbias_select = OTHC_MICBIAS_1,
.micbias_capability = OTHC_MICBIAS_HSED,
.micbias_enable = OTHC_SIGNAL_PWM_TCXO,
+ .micbias_regulator = &othc_reg,
.hsed_config = &hsed_config_1,
.hsed_name = "8660_handset",
};
@@ -4168,6 +4248,7 @@ static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
.micbias_select = OTHC_MICBIAS_2,
.micbias_capability = OTHC_MICBIAS,
.micbias_enable = OTHC_SIGNAL_OFF,
+ .micbias_regulator = &othc_reg,
};
static struct resource resources_othc_0[] = {
@@ -4631,13 +4712,13 @@ static struct pm8058_platform_data pm8058_platform_data = {
.num_subdevs = ARRAY_SIZE(pm8058_subdevs),
.sub_devices = pm8058_subdevs,
- .irq_trigger_flags = IRQF_TRIGGER_HIGH,
+ .irq_trigger_flags = IRQF_TRIGGER_LOW,
};
static struct i2c_board_info pm8058_boardinfo[] __initdata = {
{
I2C_BOARD_INFO("pm8058-core", 0x55),
- .irq = TLMM_SCSS_DIR_CONN_IRQ_1,
+ .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
.platform_data = &pm8058_platform_data,
},
};
@@ -5069,13 +5150,13 @@ static struct pm8901_platform_data pm8901_platform_data = {
.irq_base = PM8901_IRQ_BASE,
.num_subdevs = ARRAY_SIZE(pm8901_subdevs),
.sub_devices = pm8901_subdevs,
- .irq_trigger_flags = IRQF_TRIGGER_HIGH,
+ .irq_trigger_flags = IRQF_TRIGGER_LOW,
};
static struct i2c_board_info pm8901_boardinfo[] __initdata = {
{
I2C_BOARD_INFO("pm8901-core", 0x55),
- .irq = TLMM_SCSS_DIR_CONN_IRQ_2,
+ .irq = MSM_GPIO_TO_INT(PM8901_GPIO_INT),
.platform_data = &pm8901_platform_data,
},
};
@@ -5086,9 +5167,50 @@ static struct i2c_board_info pm8901_boardinfo[] __initdata = {
|| defined(CONFIG_GPIO_SX150X_MODULE))
static struct regulator *vreg_bahama;
-static unsigned int msm_bahama_setup_power(void)
+struct bahama_config_register{
+ u8 reg;
+ u8 value;
+ u8 mask;
+};
+
+enum version{
+ VER_1_0,
+ VER_2_0,
+ VER_UNSUPPORTED = 0xFF
+};
+
+static u8 read_bahama_ver(void)
+{
+ int rc;
+ struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
+ u8 bahama_version;
+
+ rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
+ if (rc < 0) {
+ printk(KERN_ERR
+ "%s: version read failed: %d\n",
+ __func__, rc);
+ return rc;
+ } else {
+ printk(KERN_INFO
+ "%s: version read got: 0x%x\n",
+ __func__, bahama_version);
+ }
+
+ switch (bahama_version) {
+ case 0x08: /* varient of bahama v1 */
+ case 0x10:
+ case 0x00:
+ return VER_1_0;
+ case 0x09: /* variant of bahama v2 */
+ return VER_2_0;
+ default:
+ return VER_UNSUPPORTED;
+ }
+}
+static unsigned int msm_bahama_setup_power(void)
{
int rc = 0;
const char *msm_bahama_regulator = "8058_s3";
@@ -5156,6 +5278,48 @@ static unsigned int msm_bahama_shutdown_power(int value)
return 0;
};
+
+static unsigned int msm_bahama_core_config(int type)
+{
+ int rc = 0;
+
+ if (type == BAHAMA_ID) {
+
+ int i;
+ struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
+
+ const struct bahama_config_register v20_init[] = {
+ /* reg, value, mask */
+ { 0xF4, 0x84, 0xFF }, /* AREG */
+ { 0xF0, 0x04, 0xFF } /* DREG */
+ };
+
+ if (read_bahama_ver() == VER_2_0) {
+ for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
+ u8 value = v20_init[i].value;
+ rc = marimba_write_bit_mask(&config,
+ v20_init[i].reg,
+ &value,
+ sizeof(v20_init[i].value),
+ v20_init[i].mask);
+ if (rc < 0) {
+ printk(KERN_ERR
+ "%s: reg %d write failed: %d\n",
+ __func__, v20_init[i].reg, rc);
+ return rc;
+ }
+ printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
+ " mask 0x%02x\n",
+ __func__, v20_init[i].reg,
+ v20_init[i].value, v20_init[i].mask);
+ }
+ }
+ }
+ printk(KERN_INFO "core type: %d\n", type);
+
+ return rc;
+}
+
static struct regulator *fm_regulator_s3;
static struct msm_xo_voter *fm_clock;
@@ -5279,6 +5443,7 @@ static struct marimba_platform_data marimba_pdata = {
.slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
.bahama_setup = msm_bahama_setup_power,
.bahama_shutdown = msm_bahama_shutdown_power,
+ .bahama_core_config = msm_bahama_core_config,
.fm = &marimba_fm_pdata,
};
@@ -5697,15 +5862,6 @@ static void __init msm8x60_init_tlmm(void)
{
if (machine_is_msm8x60_rumi3())
msm_gpio_install_direct_irq(0, 0, 1);
-
- msm_gpio_install_direct_irq(PM8058_GPIO_INT, 1, 0);
- msm_set_direct_connect(TLMM_SCSS_DIR_CONN_IRQ_1,
- MSM_GPIO_TO_INT(PM8058_GPIO_INT), 1);
-
- msm_gpio_install_direct_irq(PM8901_GPIO_INT, 2, 0);
- msm_set_direct_connect(TLMM_SCSS_DIR_CONN_IRQ_2,
- MSM_GPIO_TO_INT(PM8901_GPIO_INT), 1);
-
}
#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
@@ -6385,6 +6541,30 @@ static unsigned int msm8x60_sdcc_slot_status(struct device *dev)
}
#endif
#endif
+
+#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
+static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, bool is_wake_up)
+{
+ struct platform_device *pdev;
+ enum msm_mpm_pin pin;
+
+ pdev = container_of(dev, struct platform_device, dev);
+
+ /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
+ if (pdev->id == 4)
+ pin = MSM_MPM_PIN_SDC4_DAT1;
+ else
+ return -EINVAL;
+
+ if (is_wake_up) {
+ msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
+ msm_mpm_set_pin_wake(pin, 1);
+ } else
+ msm_mpm_set_pin_wake(pin, 0);
+
+ return 0;
+}
+#endif
#endif
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
@@ -6448,6 +6628,7 @@ static struct mmc_platform_data msm8x60_sdc4_data = {
.msmsdcc_fmax = 48000000,
.nonremovable = 1,
.pclk_src_dfab = 1,
+ .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
};
#endif
@@ -6668,6 +6849,19 @@ static void setup_display_power(void)
}
}
+#define _GET_REGULATOR(var, name) do { \
+ if (var == NULL) { \
+ var = regulator_get(NULL, name); \
+ if (IS_ERR(var)) { \
+ pr_err("'%s' regulator not found, rc=%ld\n", \
+ name, PTR_ERR(var)); \
+ var = NULL; \
+ } \
+ } \
+} while (0)
+
+#define GPIO_RESX_N (GPIO_EXPANDER_GPIO_BASE + 2)
+
static void display_common_power(int on)
{
int rc;
@@ -6737,6 +6931,51 @@ static void display_common_power(int on)
}
}
}
+#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
+ else if (machine_is_msm8x60_fluid()) {
+ static struct regulator *fluid_reg;
+ static struct regulator *fluid_reg2;
+
+ if (on) {
+ _GET_REGULATOR(fluid_reg, "8901_l2");
+ if (!fluid_reg)
+ return;
+ _GET_REGULATOR(fluid_reg2, "8058_s3");
+ if (!fluid_reg2) {
+ regulator_put(fluid_reg);
+ return;
+ }
+ rc = gpio_request(GPIO_RESX_N, "RESX_N");
+ if (rc) {
+ regulator_put(fluid_reg2);
+ regulator_put(fluid_reg);
+ return;
+ }
+ regulator_set_voltage(fluid_reg, 2850000, 2850000);
+ regulator_set_voltage(fluid_reg2, 1800000, 1800000);
+ regulator_enable(fluid_reg);
+ regulator_enable(fluid_reg2);
+ msleep(20);
+ gpio_direction_output(GPIO_RESX_N, 0);
+ udelay(10);
+ gpio_set_value_cansleep(GPIO_RESX_N, 1);
+ display_power_on = 1;
+ setup_display_power();
+ } else {
+ gpio_set_value_cansleep(GPIO_RESX_N, 0);
+ gpio_free(GPIO_RESX_N);
+ msleep(20);
+ regulator_disable(fluid_reg2);
+ regulator_disable(fluid_reg);
+ regulator_put(fluid_reg2);
+ regulator_put(fluid_reg);
+ display_power_on = 0;
+ setup_display_power();
+ fluid_reg = NULL;
+ fluid_reg2 = NULL;
+ }
+ }
+#endif
return;
out4:
@@ -7068,6 +7307,7 @@ static struct msm_bus_vectors mdp_1080p_vectors[] = {
.ib = 417600000,
},
};
+
static struct msm_bus_paths mdp_bus_scale_usecases[] = {
{
ARRAY_SIZE(mdp_init_vectors),
@@ -7276,7 +7516,6 @@ int mdp_core_clk_rate_table[] = {
59080000,
85330000,
200000000,
- 200000000,
};
static struct msm_panel_common_pdata mdp_pdata = {
.gpio = MDP_VSYNC_GPIO,
@@ -7381,7 +7620,6 @@ static const struct {
} bt_regs_info[] = {
{ "8058_s3", 1800000, 1800000 },
{ "8058_s2", 1300000, 1300000 },
- { "8058_l2", 1800000, 1800000 },
{ "8058_l8", 2900000, 3050000 },
};
@@ -7391,7 +7629,6 @@ static struct {
{ false },
{ false },
{ false },
- { false },
};
static struct regulator *bt_regs[ARRAY_SIZE(bt_regs_info)];
@@ -7401,12 +7638,6 @@ static int bahama_bt(int on)
int i;
struct marimba config = { .mod_id = SLAVE_ID_BAHAMA};
- struct bahama_config_register {
- u8 reg;
- u8 value;
- u8 mask;
- };
-
struct bahama_variant_register {
const size_t size;
const struct bahama_config_register *set;
@@ -7488,36 +7719,28 @@ static int bahama_bt(int on)
}
};
+ u8 offset = 0; /* index into bahama configs */
+
/* Init mutex to get/set FM/BT status respectively */
mutex_init(&config.xfer_lock);
on = on ? 1 : 0;
- rc = marimba_read_bit_mask(&config, 0x00, &version, 1, 0x1F);
+ version = read_bahama_ver();
- if (rc < 0) {
+ if (version == VER_UNSUPPORTED) {
dev_err(&msm_bt_power_device.dev,
- "%s: version read failed: %d\n",
- __func__, rc);
- return rc;
+ "%s: unsupported version\n",
+ __func__);
+ return -EIO;
}
- switch (version) {
- case 0x00: /* varients of bahama v1 */
- case 0x08:
- case 0X10:
- version = 0x00;
- break;
- case 0x09: /* variant of bahama v2 */
- version = marimba_get_fm_status(&config) ? 0x02 : 0x01;
- break;
- default:
- version = 0xFF;
- dev_err(&msm_bt_power_device.dev,
- "%s: unsupported version\n", __func__);
- break;
+
+ if (version == VER_2_0) {
+ if (marimba_get_fm_status(&config))
+ offset = 0x01;
}
/* Voting off 1.3V S2 Regulator,BahamaV2 used in Normal mode */
- if (on && ((version == 0x02) || (version == 0x01))) {
+ if (on && (version == VER_2_0)) {
for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
if ((!strcmp(bt_regs_info[i].name, "8058_s2"))
&& (bt_regs_status[i].enabled == true)) {
@@ -7531,20 +7754,13 @@ static int bahama_bt(int on)
}
}
}
- if ((version >= ARRAY_SIZE(bt_bahama[on])) ||
- (bt_bahama[on][version].size == 0)) {
- dev_err(&msm_bt_power_device.dev,
- "%s: unsupported version\n",
- __func__);
- return -EIO;
- }
- p = bt_bahama[on][version].set;
+ p = bt_bahama[on][version + offset].set;
dev_info(&msm_bt_power_device.dev,
"%s: found version %d\n", __func__, version);
- for (i = 0; i < bt_bahama[on][version].size; i++) {
+ for (i = 0; i < bt_bahama[on][version + offset].size; i++) {
u8 value = (p+i)->value;
rc = marimba_write_bit_mask(&config,
(p+i)->reg,
@@ -7965,6 +8181,12 @@ static void __init msm8x60_init(struct msm_board_data *board_data)
platform_device_register(&smsc911x_device);
+#if defined(CONFIG_SPI_QUP) && defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT)
+ if (machine_is_msm8x60_fluid()) {
+ spi_register_board_info(lcdc_samsung_spi_board_info,
+ ARRAY_SIZE(lcdc_samsung_spi_board_info));
+ }
+#endif
msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
msm_pm_data);
View
47 arch/arm/mach-msm/board-qrdc.c
@@ -77,7 +77,6 @@
#include "cpuidle.h"
#include "pm.h"
#include "rpm.h"
-#include "mpm.h"
#include "spm.h"
#include "rpm_log.h"
#include "timer.h"
@@ -177,7 +176,7 @@ static struct regulator_init_data saw_s0_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.min_uV = 840000,
- .max_uV = 1200000,
+ .max_uV = 1250000,
},
.num_consumer_supplies = 1,
.consumer_supplies = &saw_s0_supply,
@@ -187,7 +186,7 @@ static struct regulator_init_data saw_s1_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.min_uV = 840000,
- .max_uV = 1200000,
+ .max_uV = 1250000,
},
.num_consumer_supplies = 1,
.consumer_supplies = &saw_s1_supply,
@@ -1403,16 +1402,16 @@ static struct rpm_vreg_pdata rpm_vreg_init_pdata[RPM_VREG_ID_MAX] = {
RPM_VREG_INIT_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
RPM_VREG_INIT_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
- RPM_VREG_INIT_SMPS(PM8058_S0, 0, 1, 1, 500000, 1200000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
- RPM_VREG_INIT_SMPS(PM8058_S1, 0, 1, 1, 500000, 1200000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_INIT_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 0,
+ RPM_VREG_FREQ_1p60),
+ RPM_VREG_INIT_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 0,
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8058_S2, 0, 1, 0, 1200000, 1400000, SMPS_HMIN,
- RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p75),
+ RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_VS(PM8058_LVS0, 0, 1, 0, 0),
RPM_VREG_INIT_VS(PM8058_LVS1, 0, 1, 0, 0),
@@ -1429,11 +1428,11 @@ static struct rpm_vreg_pdata rpm_vreg_init_pdata[RPM_VREG_ID_MAX] = {
RPM_VREG_INIT_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN, 0),
RPM_VREG_INIT_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 0,
- RPM_VREG_FREQ_1p75),
+ RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN,
- RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p75),
+ RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p60),
RPM_VREG_INIT_VS(PM8901_LVS0, 1, 1, 0, 0),
RPM_VREG_INIT_VS(PM8901_LVS1, 0, 1, 0, 0),
@@ -1825,11 +1824,18 @@ static struct pmic8058_vibrator_pdata pmic_vib_pdata = {
#define PM8058_OTHC_CNTR_BASE1 0x134
#define PM8058_OTHC_CNTR_BASE2 0x137
+static struct othc_regulator_config othc_reg = {
+ .regulator = "8058_l5",
+ .max_uV = 2850000,
+ .min_uV = 2850000,
+};
+
/* MIC_BIAS0 is configured as normal MIC BIAS */
static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
.micbias_select = OTHC_MICBIAS_0,
.micbias_capability = OTHC_MICBIAS,
.micbias_enable = OTHC_SIGNAL_OFF,
+ .micbias_regulator = &othc_reg,
};
/* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
@@ -1837,6 +1843,7 @@ static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
.micbias_select = OTHC_MICBIAS_1,
.micbias_capability = OTHC_MICBIAS,
.micbias_enable = OTHC_SIGNAL_OFF,
+ .micbias_regulator = &othc_reg,
};
/* MIC_BIAS2 is configured as normal MIC BIAS */
@@ -1844,6 +1851,7 @@ static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
.micbias_select = OTHC_MICBIAS_2,
.micbias_capability = OTHC_MICBIAS,
.micbias_enable = OTHC_SIGNAL_OFF,
+ .micbias_regulator = &othc_reg,
};
static struct resource resources_othc_0[] = {
@@ -2520,13 +2528,13 @@ static struct pm8901_platform_data pm8901_platform_data = {
.irq_base = PM8901_IRQ_BASE,
.num_subdevs = ARRAY_SIZE(pm8901_subdevs),
.sub_devices = pm8901_subdevs,
- .irq_trigger_flags = IRQF_TRIGGER_HIGH,
+ .irq_trigger_flags = IRQF_TRIGGER_LOW,
};
static struct i2c_board_info pm8901_boardinfo[] __initdata = {
{
I2C_BOARD_INFO("pm8901-core", 0x55),
- .irq = TLMM_SCSS_DIR_CONN_IRQ_2,
+ .irq = MSM_GPIO_TO_INT(PM8901_GPIO_INT),
.platform_data = &pm8901_platform_data,
},
};
@@ -2799,14 +2807,6 @@ static void __init msm8x60_init_tlmm(void)
for (n = 0; n < ARRAY_SIZE(msm8x60_tlmm_cfgs); ++n)
gpio_tlmm_config(msm8x60_tlmm_cfgs[n], 0);
-
- msm_gpio_install_direct_irq(PM8058_GPIO_INT, 1, 0);
- msm_set_direct_connect(TLMM_SCSS_DIR_CONN_IRQ_1,
- MSM_GPIO_TO_INT(PM8058_GPIO_INT), 1);
- msm_gpio_install_direct_irq(PM8901_GPIO_INT, 2, 0);
- msm_set_direct_connect(TLMM_SCSS_DIR_CONN_IRQ_2,
- MSM_GPIO_TO_INT(PM8901_GPIO_INT), 1);
-
}
#define GPIO_SDC3_WP_SWITCH (GPIO_EXPANDER_GPIO_BASE + (16 * 1) + 6)
@@ -4024,7 +4024,6 @@ static int mdp_core_clk_rate_table[] = {
128000000,
160000000,
200000000,
- 200000000,
};
static struct msm_panel_common_pdata mdp_pdata = {
.mdp_core_clk_rate = 200000000,
View
4 arch/arm/mach-msm/board-qsd8x50.c
@@ -1220,12 +1220,8 @@ static struct kgsl_platform_data kgsl_pdata = {
.idle_timeout_2d = 0,
#ifdef CONFIG_KGSL_PER_PROCESS_PAGE_TABLE
.pt_va_size = SZ_32M,
- /* Maximum of 32 concurrent processes */
- .pt_max_count = 32,
#else
.pt_va_size = SZ_128M,
- /* We only ever have one pagetable for everybody */
- .pt_max_count = 1,
#endif
};
View
4 arch/arm/mach-msm/board-qsd8x50a-st1x.c
@@ -1460,12 +1460,8 @@ static struct kgsl_platform_data kgsl_pdata = {
.idle_timeout_2d = HZ/10,
#ifdef CONFIG_KGSL_PER_PROCESS_PAGE_TABLE
.pt_va_size = SZ_32M,
- /* Maximum of 32 concurrent processes */
- .pt_max_count = 32,
#else
.pt_va_size = SZ_128M,
- /* We only ever have one pagetable for everybody */
- .pt_max_count = 1,
#endif
};
View
717 arch/arm/mach-msm/clock-7x30.c
@@ -112,13 +112,15 @@
/* MUX source input identifiers. */
-#define SRC_SEL_PLL0 4 /* Modem PLL */
-#define SRC_SEL_PLL1 1 /* Global PLL */
-#define SRC_SEL_PLL3 3 /* Multimedia/Peripheral PLL or Backup PLL1 */
-#define SRC_SEL_PLL4 2 /* Display PLL */
-#define SRC_SEL_LPXO 6 /* Low-power XO */
-#define SRC_SEL_TCXO 0 /* Used for sources that always source from TCXO */
-#define SRC_SEL_AXI 0 /* Used for rates that sync to AXI */
+#define SRC_SEL_PLL0 4 /* Modem PLL */
+#define SRC_SEL_PLL1 1 /* Global PLL */
+#define SRC_SEL_PLL3 3 /* Multimedia/Peripheral PLL or Backup PLL1 */
+#define SRC_SEL_PLL4 2 /* Display PLL */
+#define SRC_SEL_LPXO_SDAC 5 /* Low-power XO for SDAC */
+#define SRC_SEL_LPXO 6 /* Low-power XO */
+#define SRC_SEL_TCXO 0 /* Used for rates from TCXO */
+#define SRC_SEL_AXI 0 /* Used for rates that sync to AXI */
+#define SRC_SEL_GND 7 /* No clock */
/* Source name to PLL mappings. */
#define SRC_PLL0 PLL_0
@@ -126,8 +128,10 @@
#define SRC_PLL3 PLL_3
#define SRC_PLL4 PLL_4
#define SRC_LPXO LPXO
+#define SRC_LPXO_SDAC LPXO
#define SRC_TCXO TCXO
#define SRC_AXI AXI