This is a frequency divider model which provide frequency division upto 16 of the input clock.
- Icarus Verilog (iverilog) GTKWave installation
- Yosys installation
- Python installation
- Docker installation
- Openlane installation
- Magic installation
- klayout installation
- ngspice installation
- Tapeout : Caravel Flow Installation
Viewing layout in klayout
Note
- 1. Post layout synthesis gate count
- 2. Area (box command)
- 3. Performance
- 4. Flop/Standard cell ratio
- 5. Power (internal,switching,leakage and total)
- Error 1 : make mount permission denied
- Error 2 : placement failed error
- Error 3 : Files name mismatch error
- Error 4 : No Macro Error
- Error 5 : sky130_vsdinv not reflecting in stat
- Error 6: List index out of range
- Error 7: Can't read sky130_vsdinv error in tcl window
- Error 8: PL_TARGET DENSITY error
References
Author
Contributors
Acknowledgement
This document is a model and analysis of a Freqency Divider. This model will contain a 4 bit number lines to select by which factor does the input frequency has to be divided. It is simulated using verilog, synthesis is performed using yosys.
A frequency divider takes an input frequency and generated a output frequency depending on the division factor. One of the well-known application of frequency divider is a phase lock loop, which generates multiples of a reference frequency. The other applications include frequency synthesizers, audio equipments, radar and satellite communication, Military equipments and RF devices. It is basically used in any application where frequency matching is needed and down scaling of frequency has to performed.
Fig 1: Frequency Divider
Fig 2: Basic I/O diagram
The installtion commands are given by taking ubuntu as the operating system.
For installating various softwares used in this project, open the terminal by right clicking on an empty space and type the respective commands in the terminal:
Note: If any of the commands that do not have sudo in the prefix doesnot go through, please add a prefix of sudo and try running it.
$ sudo apt-get update
$ sudo apt-get install iverilog gtkwave
This can be installed on windows as well by directly downloading and installing the .exe file of icarus
Open the terminal by right clicking on am empty space in the directory u want to install and type the following commands:
$ git clone https://github.com/YosysHQ/yosys.git
$ cd yosys-master
$ sudo apt install make (If make is not installed please install it)
$ sudo apt-get install build-essential clang bison flex \
    libreadline-dev gawk tcl-dev libffi-dev git \
    graphviz xdot pkg-config python3 libboost-system-dev \
    libboost-python-dev libboost-filesystem-dev zlib1g-dev
$ make
$ sudo make install
$ sudo apt install -y build-essential python3 python3-venv python3-pip
$ sudo apt-get remove docker docker-engine docker.io containerd runc (removes older version of docker if installed)
$ sudo apt-get update
$ sudo apt-get install \
ca-certificates \
curl \
gnupg \
lsb-release
$ sudo mkdir -p /etc/apt/keyrings
$ curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg
$ echo \
"deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/ubuntu \
$(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
$ sudo apt-get update
$ sudo apt-get install docker-ce docker-ce-cli containerd.io docker-compose-plugin
$ apt-cache madison docker-ce (copy the version string you want to install)
$ sudo apt-get install docker-ce=<VERSION_STRING> docker-ce-cli=<VERSION_STRING> containerd.io docker-compose-plugin (paste the version string copies in place of <VERSION_STRING>)
$ sudo docker run hello-world (If the docker is successfully installed u will get a success message here)
$ git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$ cd OpenLane/
$ make
$ make test
For Magic to be installed and work properly the following softwares have to be installed first:
$ sudo apt-get install csh
$ sudo apt-get install x11
$ sudo apt-get install xorg
$ sudo apt-get install xorg openbox
$ sudo apt-get install gcc
$ sudo apt-get install build-essential
$ sudo apt-get install freeglut3-dev
$ sudo apt-get install tcl-dev tk-dev
After all the softwares are installed, run the following commands for installing magic:
$ git clone https://github.com/RTimothyEdwards/magic
$ cd magic
$ ./configure
$ make
$ make install
$ sudo apt-get install klayout
$ sudo apt-get install ngspice
To start the project you first need to create a new repository based on the caravel_user_project <https://github.com/efabless/caravel_user_project/>_ template and make sure your repo is public and includes a README.
- Follow https://github.com/efabless/caravel_user_project/generate to create a new repository.
- Clone the reposity using the following command:
$ git clone <your github repo URL>
To setup your local environment run:
$ cd <project_name> # project_name is the name of your repo
$ mkdir dependencies
$ export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src # you need to export this whenever you start a new shell
$ export PDK_ROOT=$(pwd)/dependencies/pdks # you need to export this whenever you start a new shell
# export the PDK variant depending on your shuttle, if you don't know leave it to the default
$ export PDK=sky130B
$ make setup
To clone the repository, download the netlist files and simulate the results, Enter the following commands in your terminal:
$ git clone https://github.com/DantuNandiniDevi/iiitb_freqdiv
$ cd iiitb_freqdiv
$ iverilog -o iiitb_freqdiv_out.out iiitb_freqdiv.v iiitb_freqdiv_tb.v
$ ./iiitb_freqdiv_out.out
$ gtkwave iiitb_freqdiv_vcd.vcd
$ yosys
yosys> read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib
yosys> read_verilog iiitb_freqdiv.v
yosys> synth -top iiitb_freqdiv
yosys> dfflibmap -liberty ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib
yosys> abc -liberty ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib
yosys> stat
yosys> show
yosys> write_verilog iiitb_freqdiv_netlist.v
$ iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 ../verilog_model/primitives.v ../verilog_model/sky130_fd_sc_hd.v iiitb_freqdiv_netlist.v iiitb_freqdiv_tb.v
$ ./a.out
$ gtkwave iiitb_freqdiv_vcd.vcd
Open Terminal in the folder you want to create the custom inverter cell.
$ git clone https://github.com/nickson-jose/vsdstdcelldesign.git
$ cd vsdstdcelldesign
$ cp ./libs/sky130A.tech sky130A.tech
$ magic -T sky130A.tech sky130_inv.mag &
The above layout will open. The design can be verified and various layers can be seen and examined by selecting the area of examination and type what in the tcl window.
To extract Spice netlist, Type the following commands in tcl window.
% extract all
% ext2spice cthresh 0 rthresh 0
% ext2spice
cthresh 0 rthresh 0 is used to extract parasitic capacitances from the cell.
The spice netlist has to be edited to add the libraries we are using, The final spice netlist should look like the following:
* SPICE3 file created from sky130_inv.ext - technology: sky130A
.option scale=0.01u
.include ./libs/pshort.lib
.include ./libs/nshort.lib
M1001 Y A VGND VGND nshort_model.0 ad=1435 pd=152 as=1365 ps=148 w=35 l=23
M1000 Y A VPWR VPWR pshort_model.0 ad=1443 pd=152 as=1517 ps=156 w=37 l=23
VDD VPWR 0 3.3V
VSS VGND 0 0V
Va A VGND PULSE(0V 3.3V 0 0.1ns 0.1ns 2ns 4ns)
C0 Y VPWR 0.08fF
C1 A Y 0.02fF
C2 A VPWR 0.08fF
C3 Y VGND 0.18fF
C4 VPWR VGND 0.74fF
.tran 1n 20n
.control
run
.endc
.end
Open the terminal in the directory where ngspice is stored and type the following command, ngspice console will open:
$ ngspice sky130_inv.spice
Now you can plot the graphs for the designed inverter model.
-> plot y vs time a
Four timing parameters are used to characterize the inverter standard cell:
- Rise time: Time taken for the output to rise from 20% of max value to 80% of max value
Rise time = (2.23843 - 2.17935) = 59.08ps - Fall time- Time taken for the output to fall from 80% of max value to 20% of max value
Fall time = (4.09291 - 4.05004) = 42.87ps - Cell rise delay = time(50% output rise) - time(50% input fall)
Cell rise delay = (2.20636 - 2.15) = 56.36ps - Cell fall delay = time(50% output fall) - time(50% input rise)
Cell fall delay = (4.07479 - 4.05) = 24.79ps
To get a grid and to ensure the ports are placed correctly we can use
% grid 0.46um 0.34um 0.23um 0.17um
To save the file with a different name, use the folllowing command in tcl window
% save sky130_vsdinv.mag
Now open the sky130_vsdinv.mag using the magic command in terminal
$ magic -T sky130A.tech sky130_vsdinv.mag
In the tcl command type the following command to generate sky130_vsdinv.lef
$ lef write
A sky130_vsdinv.lef file will be created.
The layout is generated using OpenLane. To run a custom design on openlane, Navigate to the openlane folder and run the following commands:
$ cd designs
$ mkdir iiitb_freqdiv
$ cd iiitb_freqdiv
$ mkdir src
$ touch config.json
$ cd src
$ touch iiitb_freqdiv.v
The iiitb_freqdiv.v file should contain the verilog RTL code you have used and got the post synthesis simulation for.
Copy sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.lib and sky130_vsdinv.lef files to src folder in your design.
The final src folder should look like this:
The contents of the config.json are as follows. this can be modified specifically for your design as and when required.
As mentioned by kunal sir dont use defined DIE_AREA and FP_SIZING : absolute, use FP_SIZING : relative
{
"DESIGN_NAME": "iiitb_freqdiv",
"VERILOG_FILES": "dir::src/iiitb_freqdiv.v",
"CLOCK_PORT": "clkin",
"CLOCK_NET": "clkin",
"GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
"CLOCK_PERIOD": 10,
"PL_TARGET_DENSITY": 0.7,
"FP_SIZING" : "relative",
"pdk::sky130*": {
"FP_CORE_UTIL": 30,
"scl::sky130_fd_sc_hd": {
"FP_CORE_UTIL": 20
}
},
"LIB_SYNTH": "dir::src/sky130_fd_sc_hd__typical.lib",
"LIB_FASTEST": "dir::src/sky130_fd_sc_hd__fast.lib",
"LIB_SLOWEST": "dir::src/sky130_fd_sc_hd__slow.lib",
"LIB_TYPICAL": "dir::src/sky130_fd_sc_hd__typical.lib",
"TEST_EXTERNAL_GLOB": "dir::../iiitb_freqdiv/src/*"
}
Save all the changes made above and Navigate to the openlane folder in terminal and give the following command :
$ make mount (if this command doesnot go through prefix it with sudo)
After entering the openlane container give the following command:
$ ./flow.tcl -interactive
This command will take you into the tcl console. In the tcl console type the following commands:
% package require openlane 0.9
% prep -design iiitb_freqdiv
The following commands are to merge external the lef files to the merged.nom.lef. In our case sky130_vsdiat is getting merged to the lef file
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
The contents of the merged.nom.lef file should contain the Macro definition of sky130_vsdinv
% run_synthesis
Details of the gates used
Setup and Hold Slack after synthesis
Flop Ratio = Ratio of total number of flip flops / Total number of cells present in the design = 8/71 = 0.1125
The sky130_vsdinv should also reflect in your netlist after synthesis
% run_floorplan
Die Area
Core Area
Navigate to results->floorplan and type the Magic command in terminal to open the floorplan
$ magic -T /home/nandu/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_freqdiv.def &
Floorplan view
All the cells are placed in the left corner of the floorplan
% run_placement
Navigate to results->placement and type the Magic command in terminal to open the placement view
$ magic -T /home/nandu/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_freqdiv.def &
Placement View
sky130_vsdinv in the placement view :
The sky130_vsdinv should also reflect in your netlist after placement
% run_cts
% run_routing
Navigate to results->routing and type the Magic command in terminal to open the routing view
$ magic -T /home/nandu/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_freqdiv.def &
Routing View
sky130_vsdinv in the routing view :
Area report by magic :
The sky130_vsdinv should also reflect in your netlist after routing
We can also run the whole flow at once instead of step by step process by giving the following command in openlane container
$ ./flow.tcl -design iiitb_freqdiv
All the steps will be automated and all the files will be generated.
we can open the mag file and view the layout after the whole process by the following command, you can follow the path as per the image.
$ magic -T /home/nandu/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech iiitb_freqdiv.mag &
Gate Count = 71
Area = 5397.065 um2
$ sta <br>
OpenSTA> read_liberty -max /home/nandu/OpenLane/designs/iiitb_freqdiv/src/sky130_fd_sc_hd__fast.lib <br>
OpenSTA> read_liberty -min /home/nandu/OpenLane/designs/iiitb_freqdiv/src/sky130_fd_sc_hd__slow.lib <br>
OpenSTA> read_verilog /home/nandu/OpenLane/designs/iiitb_freqdiv/runs/RUN_2022.09.27_14.17.25/results/routing/iiitb_freqdiv.resized.v <br>
OpenSTA> link_design iiitb_freqdiv <br>
OpenSTA> read_sdc /home/nandu/OpenLane/designs/iiitb_freqdiv/runs/RUN_2022.09.27_14.17.25/results/cts/iiitb_freqdiv.sdc <br>
OpenSTA> read_spef /home/nandu/OpenLane/designs/iiitb_freqdiv/runs/RUN_2022.09.27_14.17.25/results/routing/iiitb_freqdiv.nom.spef <br>
OpenSTA> set_propagated_clock [all_clocks] <br>
OpenSTA> report_checks <br>
Performance = 1/(clock period - slack) = 1/(10 - 1.70)ns = 120.482Mhz
Flop Ratio = Ratio of total number of flip flops / Total number of cells present in the design = 8/71 = 0.1125
Internal Power = 97.9 uW (74.4%)
Switching Power = 33.7 uW (25.6%)
Leakage Power = 0.459 nW (0.00%)
Total Power = 132 uW (100%)
Installation screenshot
We have to edit the user_pro_example.v according to our code and edit/add a suitable test bench to verify the design.
$ make verify-user_proj_example-rtl
$ make user_proj_example
Layout view of user_proj_example
$ make verify-user_proj_example-gl
$ make user_project_wrapper
Layout view of user_project_wrapper
$ make precheck
$ make run-precheck
If the below error occurs while doing make mount replace it with sudo make mount
If you face the below error play around with the values of PL_TARGET_DENSITY, FP_CORE_UTIL and CLOCK_PERIOD until it works for your design, these values are very custom for each and every design.
Make sure the name of the module is same throughout, otherwise it will not infer the macro.
If you are getting the below error please add "TEST_EXTERNAL_GLOB": "dir::../iiitb_freqdiv/src/*" to the config.json file.
If the sky130_vsdinv files are not getting reflected in stat even when the merging was successful and the cell is seen in the merged.nom.lef file. Please use the libraries uploaded in this github page to get the sky130_vsdinv to reflecct in your stat.
"SYNTH_DRIVING_CELL":"sky130_vsdinv" please add this to the config.json file while including these libraries.
If you are getting the below error, please check the file name and macro name of sky130_vsdinv shoud be same as the once mentioned in sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.lib
If you are getting the below error, please use merged.nom.lef file while opening def files using magic.
$ magic -T /home/nandu/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_freqdiv.def &
If you get the below error, change the PL_TARGET_DENSITY to the mentioned value.
-
http://pgandhi189.blogspot.com/2014/11/universal-frequency-dividor.html ,Verilog code and testbench was taken from here
-
https://eng.libretexts.org/Bookshelves/ElectricalEngineering/Electronics/Microwave and RF Design IV%3A Modules (Steer)/06%3A Mixer and Source Modules/6.08%3A Frequency Divider,some content and fig.1. was taken from here..
-
https://github.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop
- Dantu Nandini Devi
- Dantu Nandini Devi
- Vasanthi D R
- Kunal Ghosh
- Vasanthi D R, PhD Student, IIITB
- Kunal Ghosh, VSD Corp. Pvt. Ltd.
- Nanditha Rao, Professor, IIITB
- Madhav Rao, Professor, IIITB
- Efabless Corporation
- Skywater Foundry
- Open Road
- Dantu Nandini Devi, MS by Research Student, IIITB, nandini.dantu@gmail.com
- Vasanthi D R, PhD Student, IIITB, vasanthi.dr@iiitb.ac.in
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com
- Nanditha Rao, nanditha.rao@iiitb.ac.in
- Madhav Rao, mr@iiitb.ac.in